Low Power,
Differential ADC Driver
Data Sheet ADA4932-1/ADA4932-2
Rev. E Document Feedback
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FEATURES
High performance at low power
High speed
−3 dB bandwidth of 560 MHz, G = 1
0.1 dB gain flatness to 300 MHz
Slew rate: 2800 V/μs, 25% to 75%
Fast 0.1% settling time of 9 ns
Low power: 9.6 mA per amplifier
Low harmonic distortion
100 dB SFDR at 10 MHz
90 dB SFDR at 20 MHz
Low input voltage noise: 3.6 nV/√Hz
±0.5 mV typical input offset voltage
Externally adjustable gain
Can be used with gains less than 1
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Input common-mode range shifted down by 1 VBE
Wide supply range: +3 V to ±5 V
Available in 16-lead and 24-lead LFCSP packages
APPLICATIONS
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Line drivers
FUNCTIONAL BLOCK DIAGRAM
–FB
+IN
–IN
+FB
–OUT
PD
+OUT
V
OCM
0
7752-001
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
A
DA4932-1
–V
S
–V
S
–V
S
–V
S
+
V
S
+
V
S
+
V
S
+
V
S
Figure 1. ADA4932-1
07752-002
2
1
3
4
5
6
18
17
16
15
14
13
+IN2
–
FB2
+V
S1
+V
S1
+FB1
–IN1
–OUT2
PD2
–V
S2
–V
S2
V
OCM1
+OUT1
8
9
10
11
7
+FB2
+V
S2
+V
S2
V
OCM2
12
+OUT2
–IN2
20
19
21
PD1
–OUT1
–V
S1
22 –V
S1
23 –FB1
24 +IN1
ADA4932-2
Figure 2. ADA4932-2
GENERAL DESCRIPTION
The ADA4932-1/ADA4932-2 are the next generation AD8132
with higher performance and lower noise and power consumption.
They are an ideal choice for driving high performance ADCs as
a single-ended-to-differential or differential-to-differential
amplifier. The output common-mode voltage is user adjustable
by means of an internal common-mode feedback loop, allowing
the ADA4932-1/ADA4932-2 output to match the input of the
ADC. The internal feedback loop also provides exceptional
output balance as well as suppression of even-order harmonic
distortion products.
With the ADA4932-1/ADA4932-2, differential gain configurations
are easily realized with a simple external four-resistor feedback
network that determines the closed-loop gain of the amplifier.
The ADA4932-1/ADA4932-2 were fabricated using the
Analog Devices, Inc., proprietary silicon-germanium (SiGe)
complementary bipolar process, enabling it to achieve low levels
of distortion and noise at low power consumption.
The low offset and excellent dynamic performance of the
ADA4932-1/ADA4932-2 make them well suited for a wide
variety of data acquisition and signal processing applications.
The ADA4932-1 is available in a 16-lead LFCSP, and the
ADA4932-2 is available in a 24-lead LFCSP. The pinouts are
optimized to facilitate the printed circuit board (PCB) layout
and minimize distortion. The ADA4932-1/ADA4932-2 are
specified to operate over the −40°C to +105°C temperature
range; both operate on supplies between +3 V and ±5 V.
ADA4932-1/ADA4932-2 Data Sheet
Rev. E | Page 2 of 27
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±5 V Operation ............................................................................. 3
5 V Operation ............................................................................... 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
Maximum Power Dissipation ..................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuits ..................................................................................... 17
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 19
Applications Information .............................................................. 20
Analyzing an Application Circuit ............................................ 20
Setting the Closed-Loop Gain .................................................. 20
Estimating the Output Noise Voltage ...................................... 20
Impact of Mismatches in the Feedback Networks ................. 21
Calculating the Input Impedance for an Application Circuit .... 21
Input Common-Mode Voltage Range ..................................... 23
Input and Output Capacitive AC Coupling ............................ 23
Setting the Output Common-Mode Voltage .......................... 23
High Performance Precision ADC Driver .............................. 23
High Performance ADC Driving ................................................. 25
Layout, Grounding, and Bypassing .............................................. 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
5/2016—Rev. D to Rev. E
Changed ADA4932 Family to ADA4932-1/ADA4932-2,
ADA4932-x to ADA4932-1/ADA4932-2, and CP-16-2 to
CP-16-21 ......................................................................... Throughout
Deleted Figure 2 and Figure 3; Renumbered Sequentially .......... 1
Added Figure 2 .................................................................................. 1
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
4/2014—Rev. C to Rev. D
Changes to Features Section, Figure 2, and Figure 3 ................... 1
Changes to Setting the Output Common-Mode Voltage Section .. 23
Added High Performance Precision ADC Driver Section ....... 24
Moved Layout, Grounding, and Bypassing Section ................... 26
1/2014—Rev. B to Rev. C
Changes to Figure 51 ...................................................................... 16
3/2013—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
8/2009—Rev. 0 to Rev. A
Changes to Features Section ............................................................ 1
Changes to Figure 11 ......................................................................... 9
Changes to Figure 43 and Figure 45 ............................................ 15
Changes to Figure 52, Figure 53, and Figure 54 ......................... 17
10/2008—Revision 0: Initial Version
Data Sheet ADA4932-1/ADA4932-2
Rev. E | Page 3 of 27
SPECIFICATIONS
±5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = −5 V, VOCM = 0 V, RF = 499 , RG = 499 , RT = 53.6 (when used), RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 54 for signal definitions.
±DIN to VOUT, dm Performance
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT, dm = 0.1 V p-p 560 MHz
V
OUT, dm = 0.1 V p-p, RF = RG = 205 Ω 1000 MHz
−3 dB Large Signal Bandwidth VOUT, dm = 2.0 V p-p 360 MHz
V
OUT, dm = 2.0 V p-p, RF = RG = 205 Ω 360 MHz
Bandwidth for 0.1 dB Flatness VOUT, dm = 2.0 V p-p, ADA4932-1, RL = 200 Ω 300 MHz
V
OUT, dm = 2.0 V p-p, ADA4932-2, RL = 200 Ω 100 MHz
Slew Rate VOUT, dm = 2 V p-p, 25% to 75% 2800 V/μs
Settling Time to 0.1% VOUT, dm = 2 V step 9 ns
Overdrive Recovery Time VIN = 0 V to 5 V ramp, G = 2 20 ns
NOISE/HARMONIC PERFORMANCE See Figure 53 for distortion test circuit
Second Harmonic VOUT, dm = 2 V p-p, 1 MHz −110 dBc
V
OUT, dm = 2 V p-p, 10 MHz −100 dBc
V
OUT, dm = 2 V p-p, 20 MHz −90 dBc
V
OUT, dm = 2 V p-p, 50 MHz −72 dBc
Third Harmonic VOUT, dm = 2 V p-p, 1 MHz −130 dBc
V
OUT, dm = 2 V p-p, 10 MHz −120 dBc
V
OUT, dm = 2 V p-p, 20 MHz −105 dBc
V
OUT, dm = 2 V p-p, 50 MHz −80 dBc
IMD f1 = 30 MHz, f2 = 30.1 MHz, VOUT, dm = 2 V p-p −91 dBc
Voltage Noise (RTI) f = 1 MHz 3.6 nV/√Hz
Input Current Noise f = 1 MHz 1.0 pA/√Hz
Crosstalk f = 10 MHz, ADA4932-2 −100 dB
INPUT CHARACTERISTICS
Offset Voltage V+DIN = V−DIN = VOCM = 0 V −2.2 ±0.5 +2.2 mV
T
MIN to TMAX variation −3.7 μV/°C
Input Bias Current −5.2 −2.5 −0.1 μA
T
MIN to TMAX variation −9.5 nA/°C
Input Offset Current −0.2 ±0.025 +0.2 μA
Input Resistance Differential 11 MΩ
Common mode 16 MΩ
Input Capacitance 0.5 pF
Input Common-Mode Voltage Range −VS + 0.2 to
+VS − 1.8
V
CMRR ∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V −100 −87 dB
Open-Loop Gain 64 66 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ∆VOUT, single-ended output,
RF = RG = 10 kΩ, RL = 1 kΩ
−VS + 1.4 to
+VS − 1.4
−VS + 1.2 to
+VS − 1.2
V
Linear Output Current 200 kHz, RL, dm = 10 Ω, SFDR = 68 dB 80 mA rms
Output Balance Error ∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 2 V p-p, 1 MHz,
see Figure 52 for output balance test circuit
−64 −60 dB
ADA4932-1/ADA4932-2 Data Sheet
Rev. E | Page 4 of 27
VOCM to VOUT, cm Performance
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT, cm = 100 mV p-p 270 MHz
−3 dB Large Signal Bandwidth VOUT, cm = 2 V p-p 105 MHz
Slew Rate VIN = 1.5 V to 3.5 V, 25% to 75% 410 V/µs
Input Voltage Noise (RTI) f = 1 MHz 9.6 nV/√Hz
VOCM INPUT CHARACTERISTICS
Input Voltage Range −VS + 1.2 to +VS − 1.2 V
Input Resistance 22 25 29 kΩ
Input Offset Voltage V+DIN = V−DIN = 0 V −5.1 ±1 +5.1 mV
VOCM CMRR ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V −100 −86 dB
Gain ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V 0.995 0.998 1.000 V/V
General Performance
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range 3.0 11 V
Quiescent Current per Amplifier 9.0 9.6 10.1 mA
TMIN to TMAX variation 35 µA/°C
Powered down 0.9 1.0 mA
Power Supply Rejection Ratio ΔVOUT, dm/ΔVS, ΔVS = 1 V p-p −96 −84 dB
POWER-DOWN (PD)
PD Input Voltage Powered down ≤(+VS − 2.5) V
Enabled ≥(+VS − 1.8) V
Turn-Off Time 1100 ns
Turn-On Time 16 ns
PD Pin Bias Current per Amplifier
Enabled PD = 5 V −10 +0.7 +10 µA
Disabled PD = 0 V −240 −195 −140 µA
OPERATING TEMPERATURE RANGE −40 +105 °C
Data Sheet ADA4932-1/ADA4932-2
Rev. E | Page 5 of 27
5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = 2.5 V, RF = 499 , RG = 499 , RT = 53.6 (when used), RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 54 for signal definitions.
±DIN to VOUT, dm Performance
Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT, dm = 0.1 V p-p 560 MHz
V
OUT, dm = 0.1 V p-p, RF = RG = 205 Ω 990 MHz
−3 dB Large Signal Bandwidth VOUT, dm = 2.0 V p-p 315 MHz
V
OUT, dm = 2.0 V p-p, RF = RG = 205 Ω 320 MHz
Bandwidth for 0.1 dB Flatness VOUT, dm = 2.0 V p-p, ADA4932-1, RL = 200 Ω 120 MHz
V
OUT, dm = 2.0 V p-p, ADA4932-2, RL = 200 Ω 200 MHz
Slew Rate VOUT, dm = 2 V p-p, 25% to 75% 2200 V/μs
Settling Time to 0.1% VOUT, dm = 2 V step 10 ns
Overdrive Recovery Time VIN = 0 V to 2.5 V ramp, G = 2 20 ns
NOISE/HARMONIC PERFORMANCE See Figure 53 for distortion test circuit
Second Harmonic VOUT, dm = 2 V p-p, 1 MHz −110 dBc
V
OUT, dm = 2 V p-p, 10 MHz −100 dBc
V
OUT, dm = 2 V p-p, 20 MHz −90 dBc
V
OUT, dm = 2 V p-p, 50 MHz −72 dBc
Third Harmonic VOUT, dm = 2 V p-p, 1 MHz −120 dBc
V
OUT, dm = 2 V p-p, 10 MHz −100 dBc
V
OUT, dm = 2 V p-p, 20 MHz −87 dBc
V
OUT, dm = 2 V p-p, 50 MHz −70 dBc
IMD f1 = 30 MHz, f2 = 30.1 MHz, VOUT, dm = 2 V p-p −91 dBc
Voltage Noise (RTI) f = 1 MHz 3.6 nV/√Hz
Input Current Noise f = 1 MHz 1.0 pA/√Hz
Crosstalk f = 10 MHz, ADA4932-2 −100 dB
INPUT CHARACTERISTICS
Offset Voltage V+DIN = V−DIN = VOCM = 2.5 V −2.2 ±0.5 +2.2 mV
T
MIN to TMAX variation −3.7 μV/°C
Input Bias Current −5.3 −3.0 −0.23 μA
T
MIN to TMAX variation −9.5 nA/°C
Input Offset Current −0.25 ±0.025 +0.25 μA
Input Resistance Differential 11 MΩ
Common mode 16 MΩ
Input Capacitance 0.5 pF
Input Common-Mode Voltage Range −VS + 0.2 to
+VS − 1.8
V
CMRR ∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V −100 −87 dB
Open-Loop Gain 64 66 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ∆VOUT, single-ended output,
RF = RG = 10 kΩ, RL = 1 kΩ
−VS + 1.15 to
+VS − 1.15
−VS + 1.02 to
+VS − 1.02
V
Linear Output Current 200 kHz, RL, dm = 10 Ω, SFDR = 67 dB 53 mA rms
Output Balance Error ∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V p-p, 1 MHz,
see Figure 52 for output balance test circuit
−64 −60 dB
ADA4932-1/ADA4932-2 Data Sheet
Rev. E | Page 6 of 27
VOCM to VOUT, cm Performance
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT, cm = 100 mV p-p 260 MHz
−3 dB Large Signal Bandwidth VOUT, cm = 2 V p-p 90 MHz
Slew Rate VIN = 1.5 V to 3.5 V, 25% to 75% 360 V/µs
Input Voltage Noise (RTI) f = 1 MHz 9.6 nV/√Hz
VOCM INPUT CHARACTERISTICS
Input Voltage Range −VS + 1.2 to +VS − 1.2 V
Input Resistance 22 25 29 kΩ
Input Offset Voltage V+DIN = V−DIN = 2.5 V −6.5 −3.0 +6.5 mV
VOCM CMRR ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V −100 −86 dB
Gain ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V 0.995 0.998 1.000 V/V
General Performance
Table 6.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range 3.0 11 V
Quiescent Current per Amplifier 8.2 8.8 9.5 mA
TMIN to TMAX variation 35 µA/°C
Powered down 0.7 0.8 mA
Power Supply Rejection Ratio ΔVOUT, dm/ΔVS, ΔVS = 1 V p-p −96 −84 dB
POWER-DOWN (PD)
PD Input Voltage Powered down ≤(+VS − 2.5) V
Enabled ≥(+VS − 1.8) V
Turn-Off Time 1100 ns
Turn-On Time 16 ns
PD Pin Bias Current per Amplifier
Enabled PD = 5 V −10 +0.7 +10 µA
Disabled PD = 0 V −100 −70 −40 µA
OPERATING TEMPERATURE RANGE −40 +105 °C
Data Sheet ADA4932-1/ADA4932-2
Rev. E | Page 7 of 27
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
Supply Voltage 11 V
Power Dissipation See Figure 3
Input Current, +IN, −IN, PD ±5 mA
Storage Temperature Range −65°C to +125°C
Operating Temperature Range
ADA4932-1 −40°C to +105°C
ADA4932-2 −40°C to +105°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD 51-7.
Table 8. Thermal Resistance
Package Type θJA Unit
ADA4932-1, 16-Lead LFCSP (Exposed Pad) 91 °C/W
ADA4932-2, 24-Lead LFCSP (Exposed Pad) 65 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4932-1/
ADA4932-2 package is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C, which is
the glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4932-1/
ADA4932-2. Exceeding a junction temperature of 150°C for an
extended period can result in changes in the silicon devices,
potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads/
exposed pad from metal traces, through holes, ground, and power
planes reduces θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the single 16-lead
LFCSP (91°C/W) and the dual 24-lead LFCSP (65°C/W) on a
JEDEC standard 4-layer board with the exposed pad soldered to
a PCB pad that is connected to a solid plane.
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
–40 100806040200–20
MAXIMUM POWER DISSIPATION (W)
AMBIENT TEMPERATURE (°C)
ADA4932-1
ADA4932-2
07752-204
Figure 3. Maximum Power Dissipation vs. Ambient Temperature for
a 4-Layer Board
ESD CAUTION
ADA4932-1/ADA4932-2 Data Sheet
Rev. E | Page 8 of 27
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
07752-005
NOTES
1. SOLDER EXPOSED PADDLE ON BACK OF PACKAGE
TO GROUND PLANE OR TO A POWER PLANE.
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
–FB
+IN
–IN
+FB
–OUT
PD
+OUT
V
OCM
–V
S
–V
S
–V
S
–V
S
+V
S
+V
S
+V
S
+V
S
ADA4932-1
TOP VIEW
(Not to Scale)
Figure 4. ADA4932-1 Pin Configuration
07752-006
2
1
3
4
5
6
18
17
16
15
14
13
+IN2
–FB2
+V
S1
+V
S1
+FB1
–IN1
–OUT2
PD2
–V
S2
–V
S2
V
OCM1
+OUT1
8
9
10
11
7
+FB2
+V
S2
+V
S2
V
OCM2
12
+OUT2
–IN2
20
19
21
PD1
–OUT1
–V
S1
22 –V
S1
23 –FB1
24 +IN1
NOTES
1. SOLDER EXPOSED PADDLE ON BACK OF PACKAGE
TO GROUND PLANE OR TO A POWER PLANE.
ADA4932-2
TOP VIEW
(Not to Scale)
Figure 5. ADA4932-2 Pin Configuration
Table 9. ADA4932-1 Pin Function Descriptions
Pin No. Mnemonic Description
1 −FB Negative Output for Feedback Component Connection.
2 +IN Positive Input Summing Node.
3 −IN Negative Input Summing Node.
4 +FB Positive Output for Feedback Component Connection.
5 to 8 +VS Positive Supply Voltage.
9 VOCM Output Common-Mode Voltage.
10 +OUT Positive Output for Load Connection.
11 −OUT Negative Output for Load Connection.
12 PD Power-Down Pin.
13 to 16 −VS Negative Supply Voltage.
17 Exposed Paddle (EPAD) Solder the exposed paddle on the back of the package to a ground plane or to a power plane.
Table 10. ADA4932-2 Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN1 Negative Input Summing Node 1.
2 +FB1 Positive Output Feedback 1.
3, 4 +VS1 Positive Supply Voltage 1.
5 −FB2 Negative Output Feedback 2.
6 +IN2 Positive Input Summing Node 2.
7 −IN2 Negative Input Summing Node 2.
8 +FB2 Positive Output Feedback 2.
9, 10 +VS2 Positive Supply Voltage 2.
11 VOCM2 Output Common-Mode Voltage 2.
12 +OUT2 Positive Output 2.
13 −OUT2 Negative Output 2.
14 PD2 Power-Down Pin 2.
15, 16 −VS2 Negative Supply Voltage 2.
17 VOCM1 Output Common-Mode Voltage 1.
18 +OUT1 Positive Output 1.
19 −OUT1 Negative Output 1.
20 PD1 Power-Down Pin 1.
21, 22 −VS1 Negative Supply Voltage 1.
23 −FB1 Negative Output Feedback 1.
24 +IN1 Positive Input Summing Node 1.
25 Exposed Paddle (EPAD) Solder the exposed paddle on the back of the package to a ground plane or to a power plane.
Data Sheet ADA4932-1/ADA4932-2
Rev. E | Page 9 of 27
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, −VS = −5 V, VOCM = 0 V, RG = 499 , RF = 499 , RT = 53.6 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted.
Refer to Figure 51 for test setup. Refer to Figure 54 for signal definitions.
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1M 10M 100M 1G
NORMALIZED CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
IN
= 100mV p-p
R
F
= 499Ω
R
G
=499Ω, 249Ω
07752-007
GAIN = 1
GAIN = 2
Figure 6. Small Signal Frequency Response for Various Gains
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1M 10M 100M 1G 10G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
R
F
=R
G
=499Ω
R
F
=R
G
=205Ω
V
OUT, dm
= 100mV p-p
07752-008
Figure 7. Small Signal Frequency Response for Various RF and RG
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1M 10M 100M 1G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
OUT, dm
= 100mV p-p
07752-009
V
S
= ±5V
V
S
= ±2.5V
Figure 8. Small Signal Frequency Response for Various Supplies
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1M 10M 100M 1G
FREQUENCY (Hz)
V
IN
= 2V p-p
R
F
= 499Ω
R
G
=499Ω, 249Ω
07752-010
GAIN = 1
GAIN = 2
NORMALIZED CLOSED-LOOP GAIN (dB)
Figure 9. Large Signal Frequency Response for Various Gains
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1 10 100 1k
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
V
OUT, dm
= 2V p-p
R
F
= R
G
= 205Ω
R
F
= R
G
= 499Ω
07752-058
Figure 10. Large Signal Frequency Response for Various RF and RG
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1M 10M 100M 1G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
OUT, dm
= 2V p-p
07752-012
V
S
= ±5V
V
S
= ±2.5V
Figure 11. Large Signal Frequency Response for Various Supplies
ADA4932-1/ADA4932-2 Data Sheet
Rev. E | Page 10 of 27
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1M 10M 100M 1G
CLOSED-LOOP G
A
IN (dB)
FREQUENCY (Hz)
V
OUT, dm
= 100mV p-p
07752-013
T
A
=–40°C
T
A
= +25°C
T
A
= +105°C
Figure 12. Small Signal Frequency Response for Various Temperatures
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1M 10M 100M 1G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
OUT, dm
= 100mV p-p
07752-014
R
L
= 1kΩ
R
L
= 200Ω
Figure 13. Small Signal Frequency Response at Various Loads
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1M 10M 100M 1G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
OUT, dm
= 100mV p-p
07752-015
V
OCM
=0V
V
OCM
= +2.5V
V
OCM
= –2.5V
Figure 14. Small Signal Frequency Response for Various VOCM Levels
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1M 10M 100M 1G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
OUT, dm
= 2V p-p
07752-016
T
A
=–40°C
T
A
= +25°C
T
A
= +105°C
Figure 15. Large Signal Frequency Response for Various Temperatures
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1M 10M 100M 1G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
OUT, dm
= 2V p-p
07752-017
R
L
= 1kΩ
R
L
= 200Ω
Figure 16. Large Signal Frequency Response at Various Loads
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1M 10M 100M 1G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
OUT, dm
= 2V p-p
07752-018
V
OCM
=0V
V
OCM
= +2.5V
V
OCM
= –2.5V
Figure 17. Large Signal Frequency Response for Various VOCM Levels
Data Sheet ADA4932-1/ADA4932-2
Rev. E | Page 11 of 27
–8
–6
–4
–2
0
2
4
1M 10M 100M 1G 10G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
OUT, dm
= 100mV p-p
07752-019
C
L
=0pF
C
L
=0.9pF
C
L
=1.8pF
Figure 18. Small Signal Frequency Response at Various Capacitive Loads
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
1M 10M 100M 1G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
V
OUT, dm
= 100mV p-p
07752-020
ADA4932-1, R
L
= 1kΩ
ADA4932-1, R
L
= 200Ω
ADA4932-2, CH 1, R
L
= 1kΩ
ADA4932-2, CH 1, R
L
= 200Ω
ADA4932-2, CH 2, R
L
= 1kΩ
ADA4932-2, CH 2, R
L
= 200Ω
Figure 19. 0.1 dB Flatness Small Signal Frequency Response for Various Loads
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
1M 10M 100M 1G
V
OCM
GAIN (dB)
FREQUENCY (Hz)
V
OUT, cm
= 100mV p-p
07752-021
V
OCM
(DC) = 0V
V
OCM
(DC) = +2.5V
V
OCM
(DC) = –2.5V
Figure 20. VOCM Small Signal Frequency Response at Various DC Levels
–10
–8
–6
–4
–2
0
2
4
10M 100M 1G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
CL=0pF
CL=0.9pF
CL=1.8pF
07752-022
VOUT, dm = 2V p-p
Figure 21. Large Signal Frequency Response at Various Capacitive Loads
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
1M 10M 100M 1G
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
VOUT, dm = 2V p-p
07752-023
ADA4932-1, RL= 1kΩ
ADA4932-1, RL= 200Ω
ADA4932-2, CH 1, R L= 1kΩ
ADA4932-2, CH 1, R L= 200Ω
ADA4932-2, CH 2, R L= 1kΩ
ADA4932-2, CH 2, R L= 200Ω
Figure 22. 0.1 dB Flatness Large Signal Frequency Response for Various Loads
2
–8
–7
–6
–5
–4
–3
–2
–1
0
1
V
OCM
GAIN (dB)
FREQUENCY (Hz)
V
OUT, cm
= 2V p-p
1M 1G100M10M
V
OCM
(DC) = 0V
V
OCM
(DC) = +2.5V
V
OCM
(DC) = –2.5V
07752-224
Figure 23. VOCM Large Signal Frequency Response at Various DC Levels
ADA4932-1/ADA4932-2 Data Sheet
Rev. E | Page 12 of 27
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–
40
100k 1M 10M 100M
HARMONIC DISTORTION (dBc)
FREQUENCY (Hz)
VOUT, dm = 2V p-p
07752-025
HD2, RL=1kΩ
HD3, RL=1kΩ
HD2, RL=200Ω
HD3, RL=200Ω
Figure 24. Harmonic Distortion vs. Frequency at Various Loads
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–
40
100k 1M 10M 100M
HARMONIC DISTORTION (dBc)
FREQUENCY (Hz)
07752-026
HD2, ±5.0V
HD3, ±5.0V
HD2, ±2.5V
HD3, ±2.5V
VOUT, dm = 2V p-p
VOCM = 0V
Figure 25. Harmonic Distortion vs. Frequency at Various Supplies
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–
30
–4 –3 –2 –1 0 1 2 3 4
HARMONIC DISTORTION (dBc)
VOCM (V p-p)
07752-027
VOUT = 2V p-p
HD2 AT 10MHz
HD3 AT 10MHz
HD2 AT 30MHz
HD3 AT 30MHz
Figure 26. Harmonic Distortion vs. VOCM at Various Frequencies, ±5 V Supplies
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–
40
100k 1M 10M 100M
HARMONIC DISTORTION (dBc)
FREQUENCY (Hz)
VOUT, dm = 2V p-p
07752-028
HD2, G = 1
HD3, G = 1
HD2, G = 2
HD3, G = 2
Figure 27. Harmonic Distortion vs. Frequency at Various Gains
–130
–140
–120
–110
–100
–90
–80
–70
–60
–50
–
40
01 32 45678910
HARMONIC DISTORTION (dBc)
VOUT, dm (V p-p)
07752-029
VOCM = 0V
HD2, ±5.0V
HD3, ±5.0V
HD2, ±2.5V
HD3, ±2.5V
Figure 28. Harmonic Distortion vs. VOUT, dm and Supply Voltage, f = 10 MHz
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–
20
1.4 1.6 2.01.8 2.2 2.4 2.6 2.8 3.0 3.2 3.4
HARMONIC DISTORTION (dBc)
VOCM (V)
07752-030
VOUT = 2V p-p
HD2 AT 10MHz
HD3 AT 10MHz
HD2 AT 30MHz
HD3 AT 30MHz
Figure 29. Harmonic Distortion vs. VOCM at Various Frequencies, +5 V Supply
Data Sheet ADA4932-1/ADA4932-2
Rev. E | Page 13 of 27
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–
40
100k 1M 10M 100M
HARMONIC DISTORTION (dBc)
FREQUENCY (Hz)
07752-031
HD2, 2V p-p
HD3, 2V p-p
HD2, 4V p-p
HD3, 4V p-p
Figure 30. Harmonic Distortion vs. Frequency at Various VOUT, dm
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–
40
100k 1M 10M 100M
SPURIOUS-FREE DYNAMIC RANGE (dBc)
FREQUENCY (Hz)
VOUT, dm = 2V p-p
07752-032
RL = 200Ω
RL = 1kΩ
Figure 31. Spurious-Free Dynamic Range vs. Frequency at Various Loads
–100
–90
–80
–60
–70
–50
–40
–30
–
20
1M 10M 100M 1G
CMMR (dB)
FREQUENCY (Hz)
07752-033
R
L, dm
= 200Ω
Figure 32. CMRR vs. Frequency
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–
40
100k 1M 10M 100M
HARMONIC DISTORTION (dBc)
FREQUENCY (Hz)
V
OUT, dm
= 2V p-p
07752-034
HD2, R
F
=R
G
=499Ω
HD3, R
F
=R
G
=499Ω
HD2, R
F
=R
G
=200Ω
HD3, R
F
=R
G
=200Ω
Figure 33. Harmonic Distortion vs. Frequency at Various RF and RG
10
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
NORMALIZED SPECTRUM (dBc)
FREQUENCY (MHz)
VOUT, dm = 2V p-p
29.6 29.7 29.8 29.9 30.0 30.1 30.2 30.3 30.4 30.5
07752-235
Figure 34. 30 MHz Intermodulation Distortion
–140
–120
–100
–80
–60
–40
–20
0
1M 10M 100M 1G
PSSR (dB)
FREQUENCY (Hz)
RL, dm = 200Ω
07752-036
–PSRR
+PSRR
Figure 35. PSRR vs. Frequency
ADA4932-1/ADA4932-2 Data Sheet
Rev. E | Page 14 of 27
–
10
–70
–60
–50
–40
–30
–20
1M 1G100M10M
OUTPUT BALANCE (dB)
FREQUENCY (Hz)
RL, dm = 200Ω
07752-237
Figure 36. Output Balance vs. Frequency
–60
–50
–40
–30
–20
–10
0
1M 10M 100M 1G
S-PARAMETERS (dB)
FREQUENCY (Hz)
07752-038
RL= 200Ω
INPUT SINGLE-ENDED, 50Ω LOAD TERMINATION
OUTPUT DIFFERENTIAL, 100Ω SOURCE TERMINATION
S11: COMMON-MODE-TO-COMMON-MODE
S22: DIFFERENTIAL-TO-DIFFERENTIAL
S11
S22
Figure 37. Return Loss (S11, S22) vs. Frequency
1
10
100
10 100
INPUT VOLTAGE NOISE (nV/√Hz)
FREQUENCY (Hz)
1k 10k 100k 1M
07752-039
Figure 38. Voltage Noise Spectral Density, Referred to Input
80
–80
–60
–40
–20
0
20
40
60
90
–270
–225
–180
–135
–90
–45
0
45
1k 10k 100k 1M 10M 100M 1G 10G
GAIN (dB)
PHASE (Degrees)
FREQUENCY (Hz)
GAIN
PHASE
07752-240
Figure 39. Open-Loop Gain and Phase vs. Frequency
100
10
1
0.1
OUTPUT IMPEDANCE (Ω)
FREQUENCY (Hz)
100k 1G100M10M1M
07752-241
Figure 40. Closed-Loop Output Impedance Magnitude vs. Frequency, G = 1
10
8
6
4
2
0
–2
–4
–6
–8
–10
VOLTAGE (V)
TIME (ns)
0 100 200 300 400 500 600 700 800 900 1000
2 × V
IN
V
OUT, dm
07752-242
Figure 41.Overdrive Recovery, G = 2
Data Sheet ADA4932-1/ADA4932-2
Rev. E | Page 15 of 27
0 5 10 15 20 25 30
OUTPUT VOLTAG E (V)
TIME (ns)
0
7752-059
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
Figure 42. Small Signal Pulse Response
0.08
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
OUTPUT VOLTAGE (V)
TIME (ns)
030252015105
C
L
= 0pF
C
L
= 0.9pF
C
L
= 1.8pF
07752-244
Figure 43. Small Signal Pulse Response for Various Capacitive Loads
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0 5 10 15 20 25 30
OUTPUT VOLTAGE (V)
TIME (ns)
07752-060
Figure 44. VOCM Small Signal Pulse Response
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
0 5 10 15 20 25 30
OUTPUT VOLTAGE (V)
TIME (ns)
07752-146
Figure 45. Large Signal Pulse Response
1.5
–1.5
–1.0
–0.5
0
0.5
1.0
OUTPUT VOLTAGE (V)
TIME (ns)
030252015105
C
L
= 0pF
C
L
= 0.9pF
C
L
= 1.8pF
07752-247
Figure 46. Large Signal Pulse Response for Various Capacitive Loads
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
0 5 10 15 20 25 30
OUTPUT VOLTAGE (V)
TIME (ns)
07752-148
Figure 47. VOCM Large Signal Pulse Response
ADA4932-1/ADA4932-2 Data Sheet
Rev. E | Page 16 of 27
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
–2.0
–1.6
–1.2
–0.8
–0.4
0
0.4
0.8
1.2
1.6
2.0
02468101214161820
ERROR (%)
VOLTAGE (V)
TIME (ns)
INPUT
OUTPUT
ERROR
07752-149
Figure 48. Settling Time
–160
–140
–120
–100
–80
–40
–60
–20
0
1M 10M 100M 1G
CROSSTALK (dB)
FREQUENCY (Hz)
07752-150
V
OUT, dm
= 2V p-p
R
L, dm
= 200Ω
CHANNEL 1 TO CHANNEL 2
CHANNEL 2 TO CHANNEL 1
Figure 49. Crosstalk vs. Frequency, ADA4932-2
1.2
–0.6
0.2
0
0.4
0.6
0.8
1.0
OUTPUT VOLTAGE (V)
PD VOLTAGE (V)
TIME (µs)
04.03.53.01.51.00.5
07752-252
–0.4
–0.2
8
–10
–2
–4
0
2
4
6
–8
–6
2.0 2.5
V
OUT, dm
PD R
L, dm
= 200Ω
GAIN = 9
Figure 50. PD Response Time
Data Sheet ADA4932-1/ADA4932-2
Rev. E | Page 17 of 27
TEST CIRCUITS
ADA4932-1/
ADA4932-2
1kΩ
+5V
–5V
499Ω
499Ω50Ω
DC-COUPLED
GENERATOR
499Ω
499Ω
V
OCM
53.6Ω
25.5Ω
V
IN
07752-043
Figure 51. Equivalent Basic Test Circuit, G = 1
+5V
0.1µF
–5V
499Ω
499Ω50Ω
499Ω
NETWOR
K
ANALYZER
INPUT
NETWORK
ANALYZER
INPUT
NETWORK
ANALYZER
OUTPUT
AC-COUPLED 50Ω
50Ω
499Ω
49.9Ω
49.9Ω
V
OCM
53.6Ω
V
IN
07752-044
25.5Ω
ADA4932-1/
ADA4932-2
Figure 52. Test Circuit for Output Balance, CMRR
ADA4932-1/
ADA4932-2
+5V
–5V
499Ω
499Ω50Ω
499Ω
442Ω
442Ω
499Ω
V
OCM
53.6Ω261Ω
200ΩHP
LP
2:1 50Ω
CT
V
IN
LOW-PASS
FILTER
DC-COUPLED
GENERATOR
0.1µF
0.1µF
DUAL
FILTER
07752-045
25.5Ω
Figure 53. Test Circuit for Distortion Measurements
ADA4932-1/ADA4932-2 Data Sheet
Rev. E | Page 18 of 27
TERMINOLOGY
+IN
–IN +OUT
–OUT
+D
IN
–
FB
+FB
–D
IN
V
OCM
R
G
R
F
R
G
V
OUT, dm
R
L, dm
R
F
ADA4932-1/
ADA4932-2
0
7752-046
Figure 54. Signal and Circuit Definitions
Differential Voltage
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or
equivalently, output differential mode voltage) is defined as
VOUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common ground reference.
Similarly, the differential input voltage is defined as
VIN, dm = (+DIN − (−DIN))
Common-Mode Voltage
Common-mode voltage refers to the average of two node voltages
with respect to the local ground reference. The output common-
mode voltage is defined as
VOUT, cm = (V+OUT + V−OUT)/2
Balance
Output balance is a measure of how close the output differential
signals are to being equal in amplitude and opposite in phase.
Output balance is most easily determined by placing a well-
matched resistor divider between the differential voltage nodes
and comparing the magnitude of the signal at the divider midpoint
with the magnitude of the differential signal (see Figure 52). By
this definition, output balance is the magnitude of the output
common-mode voltage divided by the magnitude of the output
differential mode voltage.
dmOUT
cmOUT
V
V
ErrorBalanceOutput
,
,
Data Sheet ADA4932-1/ADA4932-2
Rev. E | Page 19 of 27
THEORY OF OPERATION
The ADA4932-1/ADA4932-2 differ from conventional op amps
in that it has two outputs whose voltages move in opposite
directions and an additional input, VOCM. Like an op amp, it relies
on high open-loop gain and negative feedback to force these
outputs to the desired voltages. The ADA4932-1/ADA4932-2
behave much like standard voltage feedback op amps and
facilitates single-ended-to-differential conversions, common-
mode level shifting, and amplifications of differential signals.
Like an op amp, the ADA4932-1/ADA4932-2 have high input
impedance and low output impedance. Because they use voltage
feedback, the ADA4932-1/ADA4932-2 manifest a nominally
constant gain bandwidth product.
Two feedback loops are employed to control the differential and
common-mode output voltages. The differential feedback, set
with external resistors, controls only the differential output voltage.
The common-mode feedback controls only the common-mode
output voltage. This architecture makes it easy to set the output
common-mode level to any arbitrary value within the specified
limits. The output common-mode voltage is forced, by the internal
common-mode feedback loop, to be equal to the voltage applied
to the VOCM input.
The internal common-mode feedback loop produces outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. This results in
differential outputs that are very close to the ideal of being
identical in amplitude and are exactly 180° apart in phase.
ADA4932-1/ADA4932-2 Data Sheet
Rev. E | Page 20 of 27
APPLICATIONS INFORMATION
ANALYZING AN APPLICATION CIRCUIT
The ADA4932-1/ADA4932-2 use high open-loop gain and
negative feedback to force their differential and common-mode
output voltages in such a way as to minimize the differential
and common-mode error voltages. The differential error
voltage is defined as the voltage between the differential inputs
labeled +IN and −IN (see Figure 54). For most purposes, this
voltage is zero. Similarly, the difference between the actual
output common-mode voltage and the voltage applied to VOCM
is also zero. Starting from these principles, any application circuit
can be analyzed.
SETTING THE CLOSED-LOOP GAIN
Using the approach described in the Analyzing an Application
Circuit section, the differential gain of the circuit in Figure 54
can be determined by
G
F
dmIN
dmOUT
R
R
V
V
,
,
This presumes that the input resistors (RG) and feedback resistors
(RF) on each side are equal.
ESTIMATING THE OUTPUT NOISE VOLTAGE
The differential output noise of the ADA4932-1/ADA4932-2
can be estimated using the noise model in Figure 55. The input-
referred noise voltage density, vnIN, is modeled as a differential
input, and the noise currents, inIN− and inIN+, appear between
each input and ground. The output voltage due to vnIN is obtained
by multiplying vnIN by the noise gain, GN (defined in the GN
equation that follows). The noise currents are uncorrelated with
the same mean-square value, and each produces an output voltage
that is equal to the noise current multiplied by the associated
feedback resistance. The noise voltage density at the VOCM/VOCMx
pin is vnCM. When the feedback networks have the same feedback
factor, as is true in most cases, the output noise due to vnCM is
common mode. Each of the four resistors contributes (4kTRxx)1/2.
The noise from the feedback resistors appears directly at the output,
and the noise from the gain resistors appears at the output multip-
lied by RF/RG. Table 11 summarizes the input noise sources, the
multiplication factors, and the output-referred noise density terms.
ADA4932-1/
ADA4932-2
+
R
F2
V
nOD
V
nCM
V
OCM
V
nIN
R
F1
R
G2
R
G1
V
nRF1
V
nRF2
V
nRG1
V
nRG2
i
nIN+
i
nIN–
07752-047
Figure 55. Noise Model
Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks
Input Noise Contribution Input Noise Term
Input Noise
Voltage Density
Output
Multiplication Factor
Differential Output Noise
Voltage Density Term
Differential Input vnIN v
nIN G
N v
nO1 = GN(vnIN)
Inverting Input inIN− inIN− × (RF2) 1 vnO2 = (inIN−)(RF2)
Noninverting Input inIN+ inIN+ × (RF1) 1 vnO3 = (inIN+)(RF1)
VOCM Input vnCM v
nCM 0 vnO4 = 0 V
Gain Resistor, RG1 v
nRG1 (4kTRG1)1/2 R
F1/RG1 v
nO5 = (RF1/RG1)(4kTRG1)1/2
Gain Resistor, RG2 v
nRG2 (4kTRG2)1/2 R
F2/RG2 v
nO6 = (RF2/RG2)(4kTRG2)1/2
Feedback Resistor, RF1 v
nRF1 (4kTRF1)1/2 1 vnO7 = (4kTRF1)1/2
Feedback Resistor, RF2 v
nRF2 (4kTRF2)1/2 1 vnO8 = (4kTRF2)1/2
Table 12. Differential Input, DC-Coupled
Nominal Gain (dB) RF (Ω) RG (Ω) RIN, dm (Ω) Differential Output Noise Density (nV/√Hz)
0 499 499 998 9.25
6 499 249 498 12.9
10 768 243 486 18.2
Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω
Nominal Gain (dB) RF (Ω) RG1 (Ω) RT (Ω) (Std 1%) RIN, cm (Ω) RG2 (Ω)1 Differential Output Noise Density (nV/√Hz)
0 511 499 53.6 665 525 9.19
6 523 249 57.6 374 276 12.6
10 806 243 57.6 392 270 17.7
1 RG2 = RG1 + (RS||RT).
Data Sheet ADA4932-1/ADA4932-2
Rev. E | Page 21 of 27
Similar to the case of a conventional op amp, the output noise
voltage densities can be estimated by multiplying the input-
referred terms at +IN and −IN by the appropriate output factor,
where:
21
Nββ
G
2 is the circuit noise gain.
G1
F1
G1
1RR
R
β
and
G2
F2
G2
2RR
R
β
are the feedback factors.
When the feedback factors are matched, RF1/RG1 = RF2/RG2, β1 =
β2 = β, and the noise gain becomes
G
F
NR
R
β
G 1
1
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
8
1i
2
nOinOD vv
Table 12 and Table 13 list several common gain settings,
associated resistor values, input impedance, and output noise
density for both balanced and unbalanced input configurations.
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
The gain from the VOCM/VOCMx pin to VOUT, dm is equal to
2(β1 − β2)/(β1 + β2)
When β1 = β2, this term goes to zero and there is no differential
output voltage due to the voltage on the VOCM input (including
noise). The extreme case occurs when one loop is open and the
other has 100% feedback; in this case, the gain from VOCM input
to VOUT, dm is either +2 or −2, depending on which loop is closed.
The feedback loops are nominally matched to within 1% in
most applications, and the output noise and offsets due to the
VOCM input are negligible. If the loops are intentionally mismatched
by a large amount, it is necessary to include the gain term from
VOCM to VOUT, dm and account for the extra noise. For example, if
β1 = 0.5 and β2 = 0.25, the gain from VOCM to VOUT, dm is 0.67. If
the VOCM/VOCMx pin is set to 2.5 V, a differential offset voltage is
present at the output of (2.5 V)(0.67) = 1.67 V. The differential
output noise contribution is (9.6 nV/√Hz)(0.67) = 6.4 nV/√Hz.
Both of these results are undesirable in most applications;
therefore, it is best to use nominally matched feedback factors.
Mismatched feedback networks also result in a degradation of
the ability of the circuit to reject input common-mode signals,
much the same as for a four-resistor difference amplifier made
from a conventional op amp.
As a practical summarization of the above issues, resistors of 1%
tolerance produce a worst-case input CMRR of approximately
40 dB, a worst-case differential-mode output offset of 25 mV
due to a 2.5 V VOCM input, negligible VOCM noise contribution,
and no significant degradation in output balance error.
CALCULATING THE INPUT IMPEDANCE FOR AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 56, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is RIN, dm = RG + RG = 2 × RG.
+VS
–VS
+IN
–IN
RF
RF
+DIN
–DIN
VOCM
RG
RG
VOUT, dm
07752-048
ADA4932-1/
ADA4932-2
Figure 56. ADA4932-1/ADA4932-2 Configured for Balanced (Differential) Inputs
For an unbalanced, single-ended input signal (see Figure 57),
the input impedance is
F
G
F
G
seIN
RR
R
R
R
2
1
,
ADA4932-1/
ADA4932-2
R
L
V
OUT, dm
+V
S
–V
S
R
G
R
G
R
F
R
F
V
OCM
R
IN, se
0
7752-049
Figure 57. The ADA4932-1/ADA4932-2 with Unbalanced (Single-Ended) Input
The input impedance of the circuit is effectively higher than it is
for a conventional op amp connected as an inverter because a
fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor, RG. The common-mode voltage at the
amplifier input terminals can be easily determined by noting that
the voltage at the inverting input is equal to the noninverting
output voltage divided down by the voltage divider that is formed
by RF and RG in the lower loop. This voltage is present at both
input terminals due to negative voltage feedback and is in phase
ADA4932-1/ADA4932-2 Data Sheet
Rev. E | Page 22 of 27
with the input signal, thus reducing the effective voltage across
RG in the upper loop and partially bootstrapping RG.
Terminating a Single-Ended Input
This section describes how to properly terminate a single-ended
input to the ADA4932-1/ADA4932-2 with a gain of 1, RF = 499 Ω,
and RG = 499 Ω. An example using an input source with a
terminated output voltage of 1 V p-p and source resistance of 50 Ω
illustrates the four steps that must be followed. Note that
because the terminated output voltage of the source is 1 V p-p,
the open-circuit output voltage of the source is 2 V p-p. The
source shown in Figure 58 indicates this open-circuit voltage.
1. Calculate the input impedance by using the following
formula:
665
)499499(2
499
1
499
)(2
1
,
F
G
F
G
seIN
RR
R
R
R
R
S
50Ω
V
S
2V p-p
R
IN, se
665Ω
ADA4932-1/
ADA4932-2
R
L
V
OUT, dm
+V
S
–V
S
R
G
499Ω
R
G
499Ω
R
F
499Ω
R
F
499Ω
V
OCM
07752-050
Figure 58. Calculating Single-Ended Input Impedance, RIN
2. To match the 50 Ω source resistance, calculate the
termination resistor, RT, using RT||665 Ω = 50 Ω. The
closest standard 1% value for RT is 53.6 Ω.
ADA4932-1/
ADA4932-2
R
L
V
OUT, dm
+V
S
–V
S
R
S
50Ω
R
G
499Ω
R
G
499Ω
R
F
499Ω
R
F
499Ω
V
OCM
V
S
2V p-p
R
IN, se
50Ω
R
T
53.6Ω
07752-051
Figure 59. Adding Termination Resistor, RT
3. Figure 59 shows that the effective RG in the upper feedback
loop is now greater than the RG in the lower loop due to the
addition of the termination resistors. To compensate for the
imbalance of the gain resistors, add a correction resistor (RTS)
in series with RG in the lower loop. RTS is the Thevenin
equivalent of the source resistance, RS, and the termination
resistance, RT, and is equal to RS||RT.
R
S
50Ω
V
S
2
V p-
p
R
T
53.6Ω
R
TH
25.9Ω
V
TH
1.03V p-p
0
7752-052
Figure 60. Calculating the Thevenin Equivalent
RTS = RTH = RS||RT = 25.9 Ω. Note that VTH is greater than
1 V p-p, which was obtained with RT = 50 Ω. The modified
circuit with the Thevenin equivalent (closest 1% value used for
RTH) of the terminated source and RTS in the lower feedback
loop is shown in Figure 61.
ADA4932-1/
ADA4932-2 R
L
V
OUT, dm
+V
S
–V
S
R
TH
25.5Ω
R
G
499Ω
R
G
499Ω
R
F
499Ω
R
F
499Ω
V
OCM
V
TH
1.03V p-p
R
TS
25.5Ω
07752-053
Figure 61. Thevenin Equivalent and Matched Gain Resistors
Figure 61 presents a tractable circuit with matched
feedback loops that can be easily evaluated.
It is useful to point out two effects that occur with a
terminated input. The first is that the value of RG is increased
in both loops, lowering the overall closed-loop gain. The
second is that VTH is a little larger than 1 V p-p, as it would
be if RT = 50 Ω. These two effects have opposite impacts on
the output voltage, and for large resistor values in the feedback
loops (~1 kΩ), the effects essentially cancel each other out.
For small RF and RG, or high gains, however, the diminished
closed-loop gain is not canceled completely by the increased
VTH. This can be seen by evaluating Figure 61.
The desired differential output in this example is 1 V p-p
because the terminated input signal was 1 V p-p and the
closed-loop gain = 1. The actual differential output voltage,
however, is equal to (1.03 V p-p)(499/524.5) = 0.98 V p-p.
To obtain the desired output voltage of 1 V p-p, a final gain
adjustment can be made by increasing RF without modifying
any of the input circuitry (see Step 4).
Data Sheet ADA4932-1/ADA4932-2
Rev. E | Page 23 of 27
4. The feedback resistor value is modified as a final gain
adjustment to obtain the desired output voltage.
To make the output voltage VOUT = 1 V p-p, calculate RF by
using the following formula:
509
03.1
5.5241
,
ppV
ppV
V
RRVDesired
R
TH
TS
G
dmOUT
F
The closest standard 1% value to 509 Ω is 511 Ω, which
gives a differential output voltage of 1.00 V p-p.
The final circuit is shown in Figure 62.
ADA4932-1/
ADA4932-2
R
L
V
OUT, dm
1.00V p-p
+V
S
–V
S
R
S
50Ω
R
G
499Ω
R
G
499Ω
R
F
511Ω
R
F
511Ω
V
OCM
V
S
2V p-p
1V p-p
R
T
53.6Ω
R
TS
25.5Ω
07752-054
Figure 62. Terminated Single-Ended-to-Differential System with G = 2
INPUT COMMON-MODE VOLTAGE RANGE
The ADA4932-1/ADA4932-2 input common-mode range is
shifted down by approximately one VBE, in contrast to other
ADC drivers with centered input ranges such as the ADA4939-1/
ADA4939-2. The downward-shifted input common-mode
range is especially suited to dc-coupled, single-ended-to-
differential, and single-supply applications.
For ±5 V operation, the input common-mode range at the
summing nodes of the amplifier is specified as −4.8 V to +3.2 V,
and is specified as +0.2 V to +3.2 V with a +5 V supply. To
avoid nonlinearities, the voltage swing at the +IN and −IN
terminals must be confined to these ranges.
INPUT AND OUTPUT CAPACITIVE AC COUPLING
While the ADA4932-1/ADA4932-2 is best suited to dc-coupled
applications, it is nonetheless possible to use it in ac-coupled
circuits. Input ac coupling capacitors can be inserted between
the source and RG. This ac coupling blocks the flow of the dc
common-mode feedback current and causes the ADA4932-1/
ADA4932-2 dc input common-mode voltage to equal the dc
output common-mode voltage. These ac coupling capacitors must
be placed in both loops to keep the feedback factors matched.
Output ac coupling capacitors can be placed in series between
each output and its respective load.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VOCM/VOCMx pin of the ADA4932-1/ADA4932-2 is internally
biased with a voltage divider comprised of two 50 kΩ resistors
across the supplies, with a tap at a voltage approximately equal
to the midsupply point, [(+VS) + (−VS)]/2. Because of this
internal divider, the VOCM/VOCMx pin sources and sinks current,
depending on the externally applied voltage and its associated
source resistance. Relying on the internal bias results in an
output common-mode voltage that is within about 100 mV of
the expected value.
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external
source or resistor divider be used with source resistance less
than 100 Ω. If an external voltage divider consisting of equal
resistor values is used to set VOCM to midsupply with greater
accuracy than produced internally, higher values can be used
because the external resistors are placed in parallel with the
internal resistors. The output common-mode offset listed in the
Specifications section assumes that the VOCM input is driven by a
low impedance voltage source.
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC; however, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VOCM/VOCMx pin is approximately 25 kΩ. If
multiple ADA4932-1/ADA4932-2 devices share one ADC
reference output, a buffer may be necessary to drive the parallel
inputs.
HIGH PERFORMANCE PRECISION ADC DRIVER
Using a differential amplifier to drive an ADC successfully is
linked to balancing each side of the differential amplifier
correctly. Figure 64 shows the schematic for the ADA4932-1,
AD7626, and associated circuitry. In the test circuit used, a
2.4 MHz band-pass filter follows the signal source. The band-
pass filter eliminates harmonics of the 2.4 MHz signal and
ensures that only the frequency of interest is passed and
processed by the ADA4932-1 and AD7626.
The ADA4932-1 is particularly useful when driving higher fre-
quency inputs to the AD7626, a 10 MSPS ADC with a switched
capacitor input. The resistor (R8, R9) and capacitor (C5, C6)
circuit between the ADA4932-1 and AD7626 IN+ and IN− pins
acts as a low-pass filter to noise. The filter limits the input band-
width to the AD7626, but its main function is to optimize the
interface between the driving amplifier and the AD7626. The
series resistor isolates the driver amplifier from high frequency
switching spikes from the ADC switched capacitor front end.
The AD7626 data sheet shows values of 20 and 56 pF. In
Figure 64, these values were empirically optimized to 33 and
56 pF. The resistor-capacitor combination can be optimized slightly
for the circuit and input frequency being converted by simply
varying the R-C combination; however, keep in mind that
having the incorrect combination limits the THD and linearity
performance of the AD7626. In addition, increasing the bandwidth
as seen by the ADC introduces more noise.
ADA4932-1/ADA4932-2 Data Sheet
Rev. E | Page 24 of 27
Another aspect of optimization is the selection of the power
supply voltages for the ADA4932-1. In the circuit, the output
common-mode voltage (VCM pin) of the AD7626 is 2.048 V
for the internal reference voltage of 4.096 V, and each input
(IN+, IN−) swings between 0 V and 4.096 V, 180° out of phase.
This provides an 8.2 V full-scale differential input to the ADC.
The ADA4932-1 output stage requires about 1.4 V headroom
with respect to each supply voltage for linear operation.
Optimum distortion performance is obtained when the supply
voltages are approximately symmetrical about the common-mode
voltage. If a negative supply of −2.5 V is chosen, then a positive
supply of at least +6.5 V is needed for symmetry about the
common-mode voltage of 2.048 V.
Experiments performed indicate that a positive supply of 7.25 V
gives the best overall distortion for a 2.4 MHz tone. Using a low
jitter clock source and a single tone −1 dBFS amplitude, 2.402 MHz
input to the AD7626 yielded the results shown in Figure 63 of
88.49 dB SNR and −86.17 dBc THD. At this input level, the ADC
limits the SFDR to 83.8 dB. As can be seen from the plot, the
harmonics of the fundamental alias back into the pass band.
For example, when sampling at 10 MSPS, the third harmonic
(7.206 MHz) is aliased into the pass band at 10.000 MHz –
7.206 MHz = 2.794 MHz.
FREQUENCY (MHz)
07752-064
Figure 63. AD7626 Output, 64,000 Point, FFT Plot −1 dBFS Amplitude
2.40173 MHz Input Ton, 10.000 MSPS Sampling Rate
The nonharmonic noise admitted through the pass band of the
band-pass filter used in the circuit is replaced by the average
noise across the Nyquist bandwidth when calculating the SNR
and THD. The performance of this or any high speed circuit is
highly dependent on proper PCB layout. This includes, but is
not limited to, power supply bypassing, controlled impedance
lines (where required), component placement, signal routing,
and power and ground planes. For a more detailed analysis of
this circuit, refer to Circuit Note CN-0105.
2.4MHz
BPF
FROM
50Ω
SIGNAL
SOURCE
ADA4932-1
VCM VDD1 VDD2 VIO
07752-065
V
OCM
AD8031
AD7626
0.1µF
0.1µF
+5
V
+5V +2.5V +2.5V
R3
499Ω
R5
499Ω
R2
53.6Ω
R1
53.6Ω
C1
2.2nF
R4
39Ω
0.1µF
0.1µF
0.1µF
R7
499Ω
R6
499Ω
+2.048V
1
56 7 8
–FB
2
9
+IN
3–IN
4+FB
16 15 14 13
+7.25V
–2.5V
+V
S
–V
S
–OUT
+OUT
PAD
R8
33Ω
R9
33Ω
11
10
C5
56pF
C6
56pF
IN–
IN+
0V TO
+4.096V
+4.096V
TO 0V
GND
0.1µF 0.1µF 0.1µF
Figure 64. ADA4932-1 Driving the AD7626 (All Connections and Decoupling Not Shown)
Data Sheet ADA4932-1/ADA4932-2
Rev. E | Page 25 of 27
HIGH PERFORMANCE ADC DRIVING
The ADA4932-1/ADA4932-2 are ideally suited for broadband
dc-coupled applications. The circuit in Figure 65 shows a front-
end connection for an ADA4932-1 driving an AD9245, a 14-bit,
20 MSPS/40 MSPS/65 MSPS/80 MSPS ADC, with dc coupling
on the ADA4932-1 input and output. (The AD9245 achieves
its optimum performance when driven differentially.) The
ADA4932-1 eliminates the need for a transformer to drive the
ADC and performs a single-ended-to-differential conversion and
buffering of the driving signal.
The ADA4932-1 is configured with a single 3.3 V supply and a
gain of 1 for a single-ended input to differential output. The
53.6 Ω termination resistor, in parallel with the single-ended
input impedance of approximately 665 Ω, provides a 50 Ω
termination for the source. The additional 25.5 Ω (524.5 Ω
total) at the inverting input balances the parallel impedance
of the 50 Ω source and the termination resistor driving the
noninverting input.
In this example, the signal generator has a 1 V p-p symmetric,
ground-referenced bipolar output when terminated in 50 Ω.
The VOCM input is bypassed for noise reduction, and set externally
with 1% resistors to maximize output dynamic range on the
tight 3.3 V supply.
Because the inputs are dc-coupled, dc common-mode current
flows in the feedback loops, and a nominal dc level of 0.84 V is
present at the amplifier input terminals. A fraction of the output
signal is also present at the input terminals as a common-mode
signal; its level is equal to the ac output swing at the noninverting
output, divided down by the feedback factor of the lower loop.
In this example, this ripple is 0.5 V p-p × [524.5/(524.5 + 511)] =
0.25 V p-p. This ac signal is riding on the 0.84 V dc level, produc-
ing a voltage swing between 0.72 V and 0.97 V at the input
terminals. This is well within the specified limits of 0.2 V to 1.5 V.
With an output common-mode voltage of 1.65 V, each ADA4932-1
output swings between 1.4 V and 1.9 V, opposite in phase,
providing a gain of 1 and a 1 V p-p differential signal to the
ADC input. The differential RC section between the ADA4932-1
output and the ADC provides single-pole low-pass filtering and
extra buffering for the current spikes that are output from the
ADC input when its SHA capacitors are discharged.
The AD9245 is configured for a 1 V p-p full-scale input by
connecting its SENSE pin to VREF, as shown in Figure 65.
ADA4932-1
3.3V
50Ω499Ω
499Ω
25.5Ω
10kΩ
1%
511Ω
511Ω
33Ω
33Ω
V
OCM
2V p-p
SIGNAL
GENERATOR
1V p-p CENTERED
AT GROUND
53.6Ω
0.1µF
0.1µF 10µF +
0.1µF 0.1µF
10kΩ
1%
20pF
VIN– AVDD
VIN+ VREF SENSE AGND
AD9245
V
OUT, dm
= 1V p-p
V
OUT, cm
= 1.65V
07752-270
Figure 65. ADA4932-1 Driving an AD9245 ADC with DC-Coupled Input and Output
ADA4932-1/ADA4932-2 Data Sheet
Rev. E | Page 26 of 27
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4932-1/ADA4932-2 are
sensitive to the PCB environment in which it operates.
Realizing its superior performance requires attention to the
details of high speed PCB design.
The first requirement is a solid ground plane that covers as much
of the board area around the ADA4932-1/ADA4932-2 as
possible. However, the area near the feedback resistors (RF), gain
resistors (RG), and clear the input summing nodes (Pin 2 and
Pin 3) of all ground and power planes (see Figure 66). Clearing the
ground and power planes minimizes any stray capacitance at
these nodes and thus minimizes peaking of the response of the
amplifier at high frequencies.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity 4-layer
circuit board, as described in EIA/JESD51-7.
0
7752-055
Figure 66. Ground and Power Plane Voiding in Vicinity of RF and RG
Bypass the power supply pins as close to the device as possible
and directly to a nearby ground plane. Use high frequency ceramic
chip capacitors. It is recommended to use two parallel bypass
capacitors (1000 pF and 0.1 μF) for each supply. Place the 1000
pF capacitor closer to the device. Further away, provide low
frequency bulk bypassing using 10 μF tantalum capacitors from
each supply to ground.
Ensure that signal routing is short and direct to avoid parasitic
effects. Wherever complementary signals exist, provide a
symmetrical layout to maximize balanced performance. When
routing differential signals over a long distance, keep PCB
traces close together, and twist any differential wiring to
minimize loop area. Doing this reduces radiated energy and
makes the circuit less susceptible to interference.
1.30
0.80
0.80
1.30
07752-056
Figure 67. Recommended PCB Thermal Attach Pad Dimensions (Millimeters)
0.30
PLATED
VIA HOLE
1.30
GROUND PLANE
POWER PLANE
BOTTOM METAL
TOP METAL
07752-057
Figure 68. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters)
Data Sheet ADA4932-1/ADA4932-2
Rev. E | Page 27 of 27
OUTLINE DIMENSIONS
1.45
1.30 SQ
1.15
111808-A
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
0.50
0.40
0.30
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.30
0.23
0.18
COMPLIANT
TO
JEDEC STANDARDS MO-220-WEED.
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.80
0.75
0.70
Figure 69. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-21)
Dimensions shown in millimeters
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD-8.
BOTTOM VIEWTOP VIEW
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.203 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
7
12
13
18
19
6
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
01-18-2012-A
0.30
0.25
0.20
PIN 1
INDICATOR
0.20 MIN
2.40
2.30 SQ
2.20
EXPOSED
PAD
Figure 70. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Ordering Quantity Branding
ADA4932-1YCPZ-R2 −40°C to +105°C 16-Lead LFCSP CP-16-21 250 H1K
ADA4932-1YCPZ-RL −40°C to +105°C 16-Lead LFCSP CP-16-21 5,000 H1K
ADA4932-1YCPZ-R7 −40°C to +105°C 16-Lead LFCSP CP-16-21 1,500 H1K
ADA4932-2YCPZ-R2 −40°C to +105°C 24-Lead LFCSP CP-24-14 250
ADA4932-2YCPZ-RL −40°C to +105°C 24-Lead LFCSP CP-24-14 5,000
ADA4932-2YCPZ-R7 −40°C to +105°C 24-Lead LFCSP CP-24-14 1,500
1 Z = RoHS Compliant Part.
©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07752-0-5/16(E)
