FEATURES
40ns, 55ns, and 70ns maximum address access time
Asynchronous operation for compatibility with industry-
standard 32K x 8 SRAM
CMOS compatible inputs/outputs
Three-state bidirectional data bus
Low operating and standby current
Radiation-hardened process and design; total dose irradiation
testing to MIL-STD-883 Method 1019
- Total-dose: 1.0E6 rads(Si)
- Error Rate: 1.0E-10 errors/bit-day
- Latchup immune
QML Q and V compliant part
Packaging options:
- 36-pin 50-mil center flatpack (0.7 x 1.0)
- 28-pin 100-mil center DIP (0.600 x 1.4)
5-volt operation
Standard Microcircuit Drawing available 5962-92153
INTRODUCTION
The UT7156 SRAM is a high performance, asynchronous,
radiation-hardened, 32K x 8 random access memory
conforming to industry-standard fit, form, and function. The
UT7156 SRAM features fully static operation requiring no
external clocks or timing strobes. Implemented using an
advanced radiation-hardened process and a device enable/
disable function the UT7156 is a high performance, power-
saving SRAM. The combination of radiation-hardness, fast
access time, and low power consumption make UT7156
ideal for high-speed systems designed for operation in
radiation environments.
MEMORY
ARRAY
COLUMN
I/O
Figure 1. SRAM Functional Block Diagram
INPUT
DRIVERS
INPUT ROW
DECODER
OUTPUT ENABLE
E2
W
G
E1 CHIP ENABLE OUTPUT
DRIVERS
DATA
WRITE
CIRCUIT
DATA
READ
CIRCUIT
COLUMN
DECODER
WRITE ENABLE
INPUT
DRIVERS
INPUT
DRIVERS
TOP/BOTTOM
DECODER
BLOCK
DECODER
INPUT
DRIVERS
A(14:0)
INPUT
DRIVER
DQ(7:0)
Military Standard Products
UT7156 Radiation-Hardened 32K x 8 SRAM
Advanced Data Sheet
March 1997
2
PIN NAMES
1. 36-lead flatpack only.
DEVICE OPERATION
The UT7156 has four control inputs called Enable 1 (E1), Enable
2 (E2), Write Enable (W), and Output Enable ( G); 15 address
inputs, A(14:0); and eight bidirectional data lines, DQ(7:0). E1
and E2 are device enable inputs that control device selection,
active, and standby modes. Asserting both E1 and E2 enables
the device, causes IDD to rise to its active value, and decodes the
15 address inputs to select one of 32,768 words in the memory.
W controls read and write operations. During a read cycle, G
must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
3. Tied active (i.e., logic 1) in the 28-pin DIP package.
READ CYCLE
A combination of W greater than VIH (min), E1 less than VIL
(max), and E2 greater than VIH (min) defines a read cycle. Read
access time is measured from the latter of device enable, output
enable, or valid address to valid data output.
Read Cycle 1, the Address Access read in figure 3a, is initiated
by a change in address inputs while the chip is enabled with G
asserted and W deasserted. Valid data appears on data outputs
DQ(7:0) after the specified tAVQV is satisfied. Outputs remain
active throughout the entire cycle. As long as device enable and
output enable are active, the address inputs may change at a rate
equal to the minimum read cycle time (tAVAV).
Read Cycle 2, the Chip Enable-controlled Access in figure 3b,
is initiated by the latter of E1 and E2 going active while G
remains asserted, W remains deasserted, and the addresses
remain stable for the entire cycle. After the specified tETQV is
satisfied, the eight-bit word addressed by A(14:0) is accessed
and appears at the data outputs DQ(7:0).
Read Cycle 3, the Output Enable-controlled Access in figure 3c,
is initiated by G going active while E1 and E2 are asserted, W
is deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
A(14:0) Address WWrite
DQ(7:0) Data Input/Output GOutput Enable
E1 Enable 1 VDD Power
E21Enable 2 VSS Ground
136
235
334
433
532
631
730
829
928
10 27
11 26
12 25
13 24
14 23
15 22
16 21
17 20
18 19
Figure 2a. SRAM Pinout (36)
VSS
VDD
W
E2
A13
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
VSS
VDD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
NC
VDD
VSS
Figure 2b. SRAM Pinout (28)
128
227
326
425
524
623
722
821
920
10 19
11 18
12 17
13 16
14 15
VDD
W
A13
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
GWE1 E23I/O Mode Mode
X1 X X 03-state Standby
X X 1X3-state Standby
X001Data in Write
11013-state Read2
0101Data out Read
3
WRITE CYCLE
A combination of W less than VIL(max), E1 less than VIL(max),
and E2 greater than VIH(min) defines a write cycle. The state of
G is a “don’t care” for a write cycle. The outputs are placed in
the high-impedance state when either G is greater than
VIH(min), or when W is less than V IL(max).
Write Cycle 1, the Write Enable-controlled Access shown in
figure 4a, is defined by a write terminated by W going high, with
E1 and E2 still active. The write pulse width is defined by tWLWH
when the write is initiated by W, and by tETWH when the write
is initiated by the latter of E1 or E2. Unless the outputs have
been previously placed in the high-impedance state by G, the
user must wait tWLQZ before applying data to the eight
bidirectional pins DQ(7:0) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access shown in
figure 4b, is defined by a write terminated by the latter of E1 or
E2 going inactive. The write pulse width is defined by tWLEF
when the write is initiated by W, and by tETEF when the write
is initiated by the latter of E1 or E2 going active. For the W
initiated write, unless the outputs have been previously placed
in the high-impedance state by G, the user must wait tWLQZ
before applying data to the eight bidirectional pins DQ(7:0) to
avoid bus contention.
RADIATION HARDNESS
The UT7156 SRAM incorporates special design and layout
features which allow operation in high-level radiation
environments.
Table 2. Radiation Hardness
Design Specifications1
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 10% worst case particle environment, Geosynchronous orbit, 0.025 mils of
Aluminum.
Total Dose 1.0E6 rads(Si)
Error Rate21.0E-10 Errors/Bit-Day
4
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS
VDD DC supply voltage -0.5 to 7.0V
VI/O Voltage on any pin -0.5 to (VDD + 0.3)V
TSTG Storage temperature -65 to +150°C
PDMaximum power dissipation 2.0W
TJMaximum junction temperature2+150°C
ΘJC Thermal resistance, junction-to-case310°C/W
IIDC input current ±10 mA
SYMBOL PARAMETER LIMITS
VDD Positive supply voltage 4.5 to 5.5V
TCCase temperature range -55 to +125 °C
VIN DC input voltage 0V to VDD
5
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(VDD = 5.0V±10%) (-55 °C to +125°C)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 5.0E5 rads(Si).
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. V IH = 5.5V, VIL = 0V.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltage (CMOS) 3.5 V
VIL Low-level input voltage (CMOS) 1.5 V
VOL Low-level output voltage IOL = 200µA, VDD = 4.5V (CMOS) 0.05 V
VOH High-level output voltage IOH = -200µA, VDD = 4.5V (CMOS) VDD-0.05 V
VOH High-level output voltage IOH = -4mA, VDD = 4.5V (CMOS) 4.2 V
CIN1Input capacitance ƒ = 1MHz @ 0V 4pF
CIO1Bidirectional I/O capacitance ƒ = 1MHz @ 0V 7pF
IIN Input leakage current VIN = VDD and V SS -5 5µA
IOZ Three-state output leakage current VO = VDD and VSS
VDD = 5.5V
G = 5.5V
-10 10 µA
IOS2, 3 Short-circuit output current VDD = 5.5V, VO = VDD
VDD = 5.5V, VO = 0V
-90 +90 mA
mA
IDD(OP) Supply current operating @1MHz CMOS inputs (IOUT = 0)
VDD = 5.5V
50 mA
IDD1(OP) Supply current operating
@ 25MHz CMOS inputs (IOUT = 0)
VDD = 5.5V
120 mA
IDD3(SB)4Supply current standby
@ 0Hz CMOS inputs (IOUT = 0)
E1 = VDD - 0.5, VDD = 5.5V
1.2 mA
6
AC CHARACTERISTICS READ CYCLE (Post-Radiation)*
(VDD = 5.0V±10%) (-55 °C to +125°C)
Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test.
2. Three-state is defined as a 500mV change from steady-state output voltage.
3. The ET (enable true) notation refers to the rising edge of E2 or the falling edge of E1, whichever comes last. SEU immunity does not affect the read parameters.
4. The EF (enable false) notation refers to the falling edge of E2 or the rising edge of E1, whichever comes first. SEU immunity does not affect the read parameters.
SYMBOL PARAMETER 7156-40
MIN MAX
7156-55
MIN MAX
7156-70
MIN MAX
UNIT
tAVAV1Read cycle time 40 55 70 ns
tAVQV Read access time 40 55 70 ns
tAXQX2Output hold time 555ns
tGLQX2G-controlled output enable time 300ns
tGLQV G-controlled output enable time (Read Cycle 3) 15 15 15 ns
tGHQZ2G-controlled output three-state time 15 15 15 ns
tETQX2,3 E-controlled output enable time 300ns
tETQV3E-controlled access time 40 55 70 ns
tEFQZ1,4 E-controlled output three-state time215 20 20 ns
7
Assumptions:
1. E1 and G < VIL (max)
2. E2 and W > VIH (min)
A(14:0)
DQ(7:0)
Figure 3a. SRAM Read Cycle 1: Address Access
tAVAV
tAVQV
tAXQX
Assumptions:
1. G < VIL (max) and W > VIH (min)
A(14:0)
DQ(7:0)
Figure 3b. SRAM Read Cycle 2: Chip Enable Access
E2
E1
DATA VALID
tEFQZ
tETQV tETQX
Figure 3c. SRAM Read Cycle 3: Output Enable Access
A(14:0)
DQ(7:0)
G
tGHQZ
Assumptions:
1. E1 < VIL (max)
2. E2 and W > V IH (min)
tGLQV
tGLQX
tAVQV
DATA VALID
8
AC CHARACTERISTICS WRITE CYCLE (Post-Radiation)*
(VDD = 5.0V ±10%) (-55°C to +125°C)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test performed with outputs disabled (G high).
2. Three-state is defined as 500mV change from steady-state output voltage.
SYMBOL PARAMETER 7156-40
MIN MAX
7156-55
MIN MAX
7156-70
MIN MAX
UNIT
tAVAV1Write cycle time 40 55 70 ns
tETWH Device enable to end of write 35 50 65 ns
tAVET Address setup time for write (E1 or E2 -
controlled) 000ns
tAVWL Address setup time for write (W - controlled) 000ns
tWLWH Write pulse width 35 40 50 ns
tWHAX Address hold time for write (W - controlled) 000ns
tEFAX Address hold time for device enable (E1 or E2 -
controlled) 000ns
tWLQZ2W - controlled three-state time 15 20 25 ns
tWHQX2W - controlled output enable time 100ns
tETEF Device enable pulse width ( E1 or E2 - controlled) 35 50 65 ns
tDVWH Data setup time 30 40 50 ns
tWHDX Data hold time 350ns
tWLEF Device enable controlled write pulse width 35 40 65 ns
tDVEF Data setup time 35 40 50 ns
tEFDX Data hold time 000ns
tAVWH Address valid to end of write 35 40 50 ns
tWHWL1Write disable time 555ns
9
Assumptions:
1. G < VIL (max). If G > VIH (min) then Q(7:0) will be
in three-state for the entire cycle.
2. G high for tAVAV cycle.
W
E1
tAVWL
Figure 4a. SRAM Write Cycle 1: W - Controlled Access
A(14:0)
Q(7:0)
E2
tAVAV2
D(7:0) APPLIED DATA
tDVWH tWHDX
tETWH
tWLWH tWHAX
tWHQX
tWLQZ
tAVWH
tWHWL
tEFDX
Assumptions & Notes:
1. G < VIL (max). If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle.
2. Either E1/E2 scenario above can occur.
3. G high for tAVAV cycle.
A(14:0)
Figure 4b. SRAM Write Cycle 2: Enable - Controlled Access
W
E2
E1
D(7:0) APPLIED DATA
E1
E2
Q(7:0) tWLQZ
tETEF
tWLEF
tDVEF
tAVAV3
tAVET
tAVET
tETEF
tEFAX
tEFAX
10
DATA RETENTION CHARACTERISTICS (Pre-Radiation)
(TC = 25°C)
Notes:
1. E1 = VDR or E2 = VSS, all other inputs = V
DR or VSS.
2. Guaranteed but not tested.
SYMBOL PARAMETER MINIMUM MAXIMUM
VDD @
2.5V
UNIT
VDR VDD for data retention 2.5 -- V
IDDR 1 Data retention current -- .4 mA
tEFR1,2 Chip deselect to data retention time 0ns
tR1,2 Operation recovery time tAVAV ns
VDD
E1
DATA RETENTION MODE
tR
4.5V
4.5V VDR > 2.5V
Figure 5. Low VDD Data Retention Waveform
tEFR
E2
VDR
VSS
VIN < 1.5V CMOS
VIN > 3.5V CMOS
Notes:
1. 50pF including scope probe and test socket.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(i.e., CMOS input = V
DD/2).
90%
Figure 6. AC Test Loads and Input Waveforms
Input Pulses
10%
< 5ns < 5ns
2.8V
300 ohms
50pF
CMOS
0.5V
VDD-0.05V
11
PACKAGING
Figure 7a. 36-pin Ceramic FLATPACK
TOP VIEW
D
1.000 ± 0.025
E
0.700 ± 0.015 L
0.330 MIN.
b
0.016 ± 0.002
e
0.050
PIN 1 I.D.
(GEOMETRY OPTIONAL)
A
0.130 MAX.
Q
0.070 ± 0.010
(AT CERAMIC BODY)
END VIEW
c
0.007 +0.002
-0.001
Notes:
1. All package finishes are per MIL-PRF-38535.
2. It is recommended that package ceramic be mounted to a heat removal rail located on the printed
circuit board. A thermally conductive material such as MERECO XLN-589 or equivalent should be
used.
3. Letter designations are for cross-reference to MIL-STD-1835.
12
Figure 7b. 28-pin Ceramic DIP Package
Notes:
1. Seal ring to be electrically isolated.
2. All exposed metalized areas to be plated per MIL-PRF-38535.
3. Ceramic to be opaque.
4. Dimension letters refer to MIL-STD-1835.
D
1.40 ± 0.020
PIN NO. 1 ID.
S1
0.005 MIN.
S2
0.005 MIN.
E
0.595 ± 0.015 E1
0.600 + 0.020
- 0.010
C
0.010 + 0.002
- 0.001
A
0.175 MAX.
L1
0.150 MIN. L0.200
0.125
e
0.100
b
0.018 ± 0.002 Q
0.060
0.015
13
ORDERING INFORMATION
256K SRAM:
UT **** *** - * * * * *
Lead Finish:
(A) =Hot solder dipped
(C) = Gold
(X) =Factory option (gold or solder)
Screening:
(C) =Military Temperature Range flow
(P) =Prototype flow
Package Type:
(P) =28-lead ceramic side-brazed DIP
(W) =36-lead ceramic top-brazed dual-in-line flatpack
Access Time:
(40) =40ns access time
(55) =55ns access time
(70) = 70ns access time
Device Type Modifier:
(C) =CMOS-compatible I/O levels, 5.0V operation
Device Type:
(7156) = SEU of 1E-10 errors/bit-day
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
14
256K SRAM: SMD
5962 - 92153 **
Lead Finish:
(A) =Hot solder dipped
(C) =Gold
(X) =Factory Option (gold or solder)
Case Outline:
(M) =28-lead ceramic side-brazed DIP
(T) =36-lead ceramic top-brazed flatpack
Class Designator:
(V) =QML Class V, certification & qualification to MIL-PRF-38535
(Q) =QML Class Q, certification & qualification to MIL-PRF-38535
Device Type
(15) =70ns access time, CMOS I/O, DIP package, single chip enable
(17) =70ns access time, CMOS I/O, flatpack package, dual chip enable
(09) =55ns access time, CMOS I/O, DIP package, single chip enable
(11) =55ns access time, CMOS I/O, flatpack package, dual chip enable
(03) =40ns access time, CMOS I/O
Drawing Number: 92153
Total Dose:
(H) =1E6 rads(Si)
(G) =5E5 rads(Si)
(F) =3E5 rads(Si)
(R) =1E5 rads(Si)
Federal Stock Class Designator: No options
* * *
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering then the part marking is at the factory’s option and will match the lead finish “A” (solder) or “C” (gold).
15
Notes
