Military Standard Products UT7156 Radiation-Hardened 32K x 8 SRAM Advanced Data Sheet March 1997 FEATURES INTRODUCTION 40ns, 55ns, and 70ns maximum address access time Asynchronous operation for compatibility with industrystandard 32K x 8 SRAM CMOS compatible inputs/outputs Three-state bidirectional data bus Low operating and standby current Radiation-hardened process and design; total dose irradiation testing to MIL-STD-883 Method 1019 - Total-dose: 1.0E6 rads(Si) - Error Rate: 1.0E-10 errors/bit-day - Latchup immune QML Q and V compliant part Packaging options: - 36-pin 50-mil center flatpack (0.7 x 1.0) - 28-pin 100-mil center DIP (0.600 x 1.4) 5-volt operation Standard Microcircuit Drawing available 5962-92153 A(14:0) E1 E2 G W INPUT DRIVER TOP/BOTTOM DECODER INPUT DRIVERS BLOCK DECODER INPUT DRIVERS ROW DECODER INPUT DRIVERS COLUMN DECODER The UT7156 SRAM is a high performance, asynchronous, radiation-hardened, 32K x 8 random access memory conforming to industry-standard fit, form, and function. The UT7156 SRAM features fully static operation requiring no external clocks or timing strobes. Implemented using an advanced radiation-hardened process and a device enable/ disable function the UT7156 is a high performance, powersaving SRAM. The combination of radiation-hardness, fast access time, and low power consumption make UT7156 ideal for high-speed systems designed for operation in radiation environments. MEMORY ARRAY COLUMN I/O CHIP ENABLE DATA WRITE CIRCUIT DATA READ CIRCUIT OUTPUT ENABLE WRITE ENABLE Figure 1. SRAM Functional Block Diagram INPUT DRIVERS OUTPUT DRIVERS DQ(7:0) VSS VDD A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 NC VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VSS 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VDD W E2 A13 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Table 1. Device Operation Truth Table G W E1 E23 I/O Mode X1 X X 0 3-state Standby X X 1 X 3-state Standby X 0 0 1 Data in Write 1 1 0 1 3-state Read2 0 1 0 1 Data out Read VDD W A13 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 Figure 2b. SRAM Pinout (28) PIN NAMES A(14:0) Address W Write DQ(7:0) Data Input/Output G Output Enable E1 Enable 1 VDD Power E21 Enable 2 VSS 1. 36-lead flatpack only. The UT7156 has four control inputs called Enable 1 (E1), Enable 2 (E2), Write Enable (W), and Output Enable (G); 15 address inputs, A(14:0); and eight bidirectional data lines, DQ(7:0). E1 and E2 are device enable inputs that control device selection, active, and standby modes. Asserting both E1 and E2 enables the device, causes IDD to rise to its active value, and decodes the 15 address inputs to select one of 32,768 words in the memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs. VSS Figure 2a. SRAM Pinout (36) A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS DEVICE OPERATION Ground Mode Notes: 1. "X" is defined as a "don't care" condition. 2. Device active; outputs disabled. 3. Tied active (i.e., logic 1) in the 28-pin DIP package. READ CYCLE A combination of W greater than VIH (min), E1 less than VIL (max), and E2 greater than VIH (min) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output. Read Cycle 1, the Address Access read in figure 3a, is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV). Read Cycle 2, the Chip Enable-controlled Access in figure 3b, is initiated by the latter of E1 and E2 going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(14:0) is accessed and appears at the data outputs DQ(7:0). Read Cycle 3, the Output Enable-controlled Access in figure 3c, is initiated by G going active while E1 and E2 are asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied. 2 WRITE CYCLE A combination of W less than VIL(max), E1 less than VIL(max), and E2 greater than VIH(min) defines a write cycle. The state of G is a "don't care" for a write cycle. The outputs are placed in the high-impedance state when either G is greater than VIH(min), or when W is less than VIL(max). Write Cycle 1, the Write Enable-controlled Access shown in figure 4a, is defined by a write terminated by W going high, with E1 and E2 still active. The write pulse width is defined by tWLWH when the write is initiated by W, and by tETWH when the write is initiated by the latter of E1 or E2. Unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention. Write Cycle 2, the Chip Enable-controlled Access shown in figure 4b, is defined by a write terminated by the latter of E1 or E2 going inactive. The write pulse width is defined by tWLEF when the write is initiated by W, and by tETEF when the write is initiated by the latter of E1 or E2 going active. For the W initiated write, unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention. RADIATION HARDNESS The UT7156 SRAM incorporates special design and layout features which allow operation in high-level radiation environments. Table 2. Radiation Hardness Design Specifications 1 Total Dose 1.0E6 rads(Si) Error Rate2 1.0E-10 Errors/Bit-Day Notes: 1. The SRAM will not latchup during radiation exposure under recommended operating conditions. 2. 10% worst case particle environment, Geosynchronous orbit, 0.025 mils of Aluminum. 3 ABSOLUTE MAXIMUM RATINGS 1 (Referenced to VSS) SYMBOL PARAMETER LIMITS VDD DC supply voltage -0.5 to 7.0V VI/O Voltage on any pin -0.5 to (VDD + 0.3)V TSTG Storage temperature -65 to +150C PD Maximum power dissipation TJ Maximum junction temperature2 +150C Thermal resistance, junction-to-case3 10C/W DC input current 10 mA JC II 2.0W Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended.xposure E to absolute maximum rating conditions for extended periods may affect device reliability. 2. Maximum junction temperature may be increased to +175 C during burn-in and steady-static life. 3. Test per MIL-STD-883, Method 1012. RECOMMENDED OPERATING CONDITIONS SYMBOL 4 PARAMETER LIMITS VDD Positive supply voltage 4.5 to 5.5V TC Case temperature range -55 to +125C VIN DC input voltage 0V to VDD DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (VDD = 5.0V10%) (-55C to +125C) SYMBOL PARAMETER CONDITION MIN MAX 3.5 UNIT VIH High-level input voltage (CMOS) V VIL Low-level input voltage (CMOS) 1.5 V VOL Low-level output voltage IOL = 200A, VDD = 4.5V (CMOS) 0.05 V VOH High-level output voltage IOH = -200A, VDD = 4.5V (CMOS) VOH High-level output voltage IOH = -4mA, VDD = 4.5V (CMOS) CIN1 Input capacitance = 1MHz @ 0V 4 pF CIO1 Bidirectional I/O capacitance = 1MHz @ 0V 7 pF IIN Input leakage current VIN = VDD and VSS -5 5 A IOZ Three-state output leakage current VO = VDD and VSS -10 10 A -90 +90 mA mA 50 mA 120 mA 1.2 mA VDD-0.05 V 4.2 V VDD = 5.5V G = 5.5V IOS2, 3 Short-circuit output current VDD = 5.5V, VO = VDD VDD = 5.5V, VO = 0V IDD(OP) Supply current operating @1MHz CMOS inputs (IOUT = 0) VDD = 5.5V IDD1(OP) IDD3(SB)4 Supply current operating @ 25MHz CMOS inputs (IOUT = 0) VDD = 5.5V Supply current standby @ 0Hz E1 = VDD - 0.5, VDD = 5.5V CMOS inputs (IOUT = 0) Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019 at 5.0E5 rads(Si). 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 4. VIH = 5.5V, VIL = 0V. 5 AC CHARACTERISTICS READ CYCLE (Post-Radiation)* (VDD = 5.0V10%) (-55C to +125C) SYMBOL 7156-40 PARAMETER MIN MAX 7156-55 MIN MAX 7156-70 MIN UNIT MAX tAVAV1 Read cycle time tAVQV Read access time tAXQX2 Output hold time 5 5 5 ns tGLQX2 G-controlled output enable time 3 0 0 ns tGLQV G-controlled output enable time (Read Cycle 3) 15 15 15 ns tGHQZ2 G-controlled output three-state time 15 15 15 ns tETQX2,3 E-controlled output enable time 40 55 40 3 70 55 0 ns 70 0 ns ns tETQV3 E-controlled access time 40 55 70 ns tEFQZ1,4 E-controlled output three-state time2 15 20 20 ns Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Functional test. 2. Three-state is defined as a 500mV change from steady-state output voltage. 3. The ET (enable true) notation refers to the rising edge of E2 or the falling edge of E1, whichever comes last. SEU immunity does not affect the read parameters. 4. The EF (enable false) notation refers to the falling edge of E2 or the rising edge of E1, whichever comes first. SEU immunity does not affect the read parameters. 6 tAVAV A(14:0) DQ(7:0) tAVQV Assumptions: 1. E1 and G < VIL (max) 2. E2 and W > VIH (min) tAXQX Figure 3a. SRAM Read Cycle 1: Address Access A(14:0) E2 E1 tETQV tETQX DQ(7:0) tEFQZ DATA VALID Assumptions: 1. G < VIL (max) and W > VIH (min) Figure 3b. SRAM Read Cycle 2: Chip Enable Access tAVQV A(14:0) G tGHQZ tGLQX DATA VALID DQ(7:0) tGLQV Assumptions: 1. E1 < VIL (max) 2. E2 and W > VIH (min) Figure 3c. SRAM Read Cycle 3: Output Enable Access 7 AC CHARACTERISTICS WRITE CYCLE (Post-Radiation)* (VDD = 5.0V 10%) (-55C to +125C) SYMBOL PARAMETER 7156-40 MIN MAX 7156-55 MIN MAX 7156-70 MIN UNIT MAX tAVAV1 Write cycle time 40 55 70 ns tETWH Device enable to end of write 35 50 65 ns tAVET Address setup time for write (E1 or E2 controlled) 0 0 0 ns tAVWL Address setup time for write (W - controlled) 0 0 0 ns tWLWH Write pulse width 35 40 50 ns tWHAX Address hold time for write (W - controlled) 0 0 0 ns tEFAX Address hold time for device enable (E1 or E2 controlled) 0 0 0 ns tWLQZ2 W - controlled three-state time tWHQX2 W - controlled output enable time 1 0 0 ns tETEF Device enable pulse width (E1 or E2 - controlled) 35 50 65 ns tDVWH Data setup time 30 40 50 ns tWHDX Data hold time 3 5 0 ns tWLEF Device enable controlled write pulse width 35 40 65 ns tDVEF Data setup time 35 40 50 ns tEFDX Data hold time 0 0 0 ns tAVWH Address valid to end of write 35 40 50 ns tWHWL1 Write disable time 5 5 5 ns Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Functional test performed with outputs disabled G ( high). 2. Three-state is defined as 500mV change from steady-state output voltage. 8 15 20 25 ns A(14:0) tAVAV2 E2 tAVWH E1 tETWH tWHWL W tAVWL tWLWH Q(7:0) tWHAX tWLQZ tWHQX APPLIED DATA D(7:0) Assumptions: 1. G < VIL (max). If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle. 2. G high for tAVAV cycle. tDVWH tWHDX Figure 4a. SRAM Write Cycle 1: W - Controlled Access tAVAV3 A(14:0) tETEF tAVET E1 tEFAX E2 E1 tAVET E2 W tETEF APPLIED DATA D(7:0) tWLQZ Q(7:0) tEFAX tWLEF tDVEF tEFDX Assumptions & Notes: 1. G < VIL (max). If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle. 2. Either E1/E2 scenario above can occur. 3. G high for tAVAV cycle. Figure 4b. SRAM Write Cycle 2: Enable - Controlled Access 9 DATA RETENTION CHARACTERISTICS (Pre-Radiation) (TC = 25C) SYMBOL PARAMETER MINIMUM MAXIMUM VDD @ UNIT 2.5V VDR VDD for data retention 2.5 -- V IDDR 1 Data retention current -- .4 mA tEFR1,2 Chip deselect to data retention time 0 ns tAVAV ns tR1,2 Operation recovery time Notes: 1. E1 = VDR or E2 = VSS, all other inputs = VDR or VSS. 2. Guaranteed but not tested. DATA RETENTION MODE VDR > 2.5V VDD 4.5V VIN < 1.5V CMOS tEFR 4.5V tR VDR E1 VIN > 3.5V CMOS E2 VSS Figure 5. Low VDD Data Retention Waveform CMOS 90% VDD-0.05V 300 ohms 2.8V 10% 0.5V < 5ns 50pF < 5ns Input Pulses Notes: 1. 50pF including scope probe and test socket. 2. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = VDD/2). Figure 6. AC Test Loads and Input Waveforms 10 PACKAGING E 0.700 0.015 L 0.330 MIN. b 0.016 0.002 D 1.000 0.025 e 0.050 PIN 1 I.D. (GEOMETRY OPTIONAL) TOP VIEW c 0.007 +0.002 -0.001 A 0.130 MAX. Q 0.070 0.010 (AT CERAMIC BODY) END VIEW Notes: 1. All package finishes are per MIL-PRF-38535. 2. It is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. A thermally conductive material such as MERECO XLN-589 or equivalent should be used. 3. Letter designations are for cross-reference to MIL-STD-1835. Figure 7a. 36-pin Ceramic FLATPACK 11 D 1.40 0.020 E 0.595 0.015 + 0.020 E1 0.600 - 0.010 PIN NO. 1 ID. S1 0.005 MIN. A 0.175 MAX. + 0.002 C 0.010 - 0.001 S2 0.005 MIN. L1 0.200 0.150 MIN. L 0.125 e 0.100 b 0.018 0.002 Q 0.060 0.015 Notes: 1. Seal ring to be electrically isolated. 2. All exposed metalized areas to be plated per MIL-PRF-38535. 3. Ceramic to be opaque. 4. Dimension letters refer to MIL-STD-1835. Figure 7b. 28-pin Ceramic DIP Package 12 ORDERING INFORMATION 256K SRAM: UT **** *** - * * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow Package Type: (P) = 28-lead ceramic side-brazed DIP (W) = 36-lead ceramic top-brazed dual-in-line flatpack Access Time: (40) = 40ns access time (55) = 55ns access time (70) = 70ns access time Device Type Modifier: (C) = CMOS-compatible I/O levels, 5.0V operation Device Type: (7156) = SEU of 1E-10 errors/bit-day Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C"old). (g 13 256K SRAM: SMD 5962 - 92153 ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (M) = 28-lead ceramic side-brazed DIP (T) = 36-lead ceramic top-brazed flatpack Class Designator: (V) = QML Class V, certification & qualification to MIL-PRF-38535 (Q) = QML Class Q, certification & qualification to MIL-PRF-38535 Device Type (15) = 70ns access time, CMOS I/O, DIP package, single chip enable (17) = 70ns access time, CMOS I/O, flatpack package, dual chip enable (09) = 55ns access time, CMOS I/O, DIP package, single chip enable (11) = 55ns access time, CMOS I/O, flatpack package, dual chip enable (03) = 40ns access time, CMOS I/O Drawing Number: 92153 Total Dose: (H) = 1E6 rads(Si) (G) = 5E5 rads(Si) (F) = 3E5 rads(Si) (R) = 1E5 rads(Si) Federal Stock Class Designator: No options Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering then the part marking is at the factory's option and will match the lead finish "A" (sol der) or "C" (gold). 14 Notes 15