CY7C131-55JC - CYPRESS SEMICONDUCTOR

FAULT

ABSVAL

OUT

REF

IN+

IN-

RSENSE1 SHORT CIRCUIT FAULT

ISOLATION BOUNDARY

A/D

CONVERTER

MICRO

CONTROLLER

HCPL-788J

FAULT

ABSVAL

OUT

REF

IN+

IN-

RSENSE2

ISOLATION BOUNDARY

HCPL-788J

FAULT

ABSVAL

OUT

REF

IN+

IN-

RSENSE3

ISOLATION BOUNDARY

HCPL-788J

+5 V

OVERLOAD

FAULT

–

3 PHASE ABSOLUTE

VALUE OUTPUT

VREF

VTH

3 PHASE

MOTOR

Low Cost Three Phase Current Sensing with Short Circuit and Overload Detection

HCPL-788J

Isolation Amplier with Short Circuit and Overload Detection

Data Sheet

Description

Avago’s Isolation Amplier with Short Circuit and Over-

load Detection makes motor phase current sensing com-

pact, aordable and easy-to-implement while satisfying

worldwide safety and regulatory requirements.

Applications

x Motor phase and rail current sensing

x Power inverter current and voltage sensing

x Industrial process control

x Data acquisition systems

x General purpose current and voltage sensing

x Traditional current transducer replacements

CAUTION: It is advised that normal static precautions be taken in handling and assembly of

this component to prevent damage and/or degradation which may be induced by ESD.

Features

xOutput Voltage Directly Compatible with A/D

Converters (0 V to VREF)

xFast (3 µs) Short Circuit Detection with Transient Fault

Rejection

xAbsolute Value Signal Output for Overload Detection

x1 µV/°C Oset Change vs. Temperature

xSO-16 Package

x-40°C to +85°C Operating Temperature Range

x25 kV/µs Isolation Transient Immunity

xRegulatory Approvals: UL, CSA, IEC/EN/DIN EN 60747-

5-2 (1230 Vpeak Working Voltage)

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

Description

The HCPL-788J isolation ampli-er is designed for cur-

rent sensing in electronic motor drives. In a typical

implementa-tion, motor currents ow through an ex-

ternal resistor and the resulting analog voltage drop is

sensed by the HCPL-788J. A larger analog output volt-

age is created on the other side of the HCPL-788J’s opti-

cal isolation barrier. The output voltage is proportional

to the motor current and can be connected directly to a

single-supply A/D converter. A digital over-range output

(FAULT) and an analog rectied output (ABSVAL) are also

Figure 1. Current sensing circuit.

provided. The wire OR-able over-range output (FAULT)

is useful for quick detec tion of short circuit con ditions

on any of the motor phases. The wire-OR-able rectied

output (ABSVAL), simplies measure-ment of motor load

since it performs polyphase rectication. Since the com-

mon-mode voltage swings several hundred volts in tens

of nanoseconds in modern electronic motor drives, the

HCPL-788J was designed to ignore very high common-

mode transient slew rates (10 kV/µs).

GND2

VDD2

FAULT

ABSVAL

VOUT

VREF

VDD2

GND2

VIN+

VIN-

VDD1

VLED+

VDD1

GND1

RSHUNT

0.02 Ω

ISOLATED +5 V

4.7 kΩ

39 Ω

.01 μF

0.1 μF

ISOLATION BOUNDARY

INPUT

CURRENT

+5 V

A/D

VREF

GND

μC

TO OTHER

PHASE

OUTPUTS

0.1 μF

HCPL-788J

Symbol Description

FAULT Short circuit fault output. FAULT changes from a

high to low output voltage within 6 µs after VIN

exceeds the FAULT Detection Threshold. FAULT is an

open drain output which allows outputs from all

the HCPL-788Js in a circuit to be connected

together (“wired-OR”) forming a single fault signal

for interfacing directly to the micro-controller.

ABSVAL Absolute value of VOUT output. ABSVAL is 0 V

when VIN=0 and increases toward VREF as VIN

approaches +256 mV or -256 mV. ABSVAL is

“wired-OR” able and is used for detecting

overloads.

VOUT Voltage output. Swings from 0 to VREF.

The nominal gain is VREF /504 mV.

VREF Reference voltage input (4.0 V to VDD2). This

voltage establishes the full scale output ranges

and gains of VOUT and ABSVAL.

VDD2 Supply voltage input (4.5 V to 5.5 V).

GND2 Ground input.

Symbol Description

VIN+ Positive input voltage (±200 mV recommended).

VIN- Negative input voltage (normally connected to

GND1).

CH Internal Bias Node. Connections to or between CH

and CL other than the re quired 0.1 µF capacitor

shown, are not recommended.

VDD1 Supply voltage input (4.5 V to 5.5 V).

VLED+ LED anode. This pin must be left uncon nected for

guaranteed data sheet perfor mance. (For optical

coupling testing only.)

VDD1 Supply voltage input (4.5 V to 5.5 V).

GND1 Ground input.

GND2 Ground input.

VDD2 Supply voltage input (4.5 V to 5.5 V).

Pin Descriptions

Ordering Information

HCPL-788J is UL Recognized with 5000 Vrms for 1 minute per UL1577.

Part

Number

Option

Package

Surface

Mount

Tape

& Reel

IEC/EN/DIN EN

60747-5-2 Quantity

RoHS

Compliant

non RoHS

Compliant

HCPL-788J -000E no option SO-16 X X 45 per tube

-500E #500 X X X 850 per reel

To order, choose a part number from the part number column and combine with the desired option from the option

column to form an order entry.

Example 1:

HCPL-788J-500E to order product of 16-Lead Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN

60747-5-2 Safety Approval and RoHS compliant.

Example 2:

HCPL-788J to order product of 16-Lead Surface Mount package in Tube packaging and non RoHS compliant.

Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and

RoHS compliant will use ‘–XXXE.’

Note: Initial and continued variation in the color of the HCPL-788J’s white mold compound is normal and does not aect device performance or

reliability.

Note: Floating lead protrusion is 0.25 mm (10 mils) max.

Package Outline Drawings

16-Lead Surface Mount

Dimensions in inches (millimeters)

0.295 ± 0.010

(7.493 ± 0.254)

10111213141516

87654321

0.018

(0.457)

0.138 ± 0.005

(3.505 ± 0.127)

9°

0.406 ± 0.10

(10.312 ± 0.254)

0.408 ± 0.010

(10.160 ± 0.254)

0.025 MIN.

0.008 ± 0.003

(0.203 ± 0.076)

STANDOFF

0.345 ± 0.010

(8.986 ± 0.254)

0–8°

0.018

(0.457)

0.050

(1.270)

ALL LEADS

TO BE

COPLANAR

± 0.002

A 788J

YYWW

TYPE NUMBER

DATE CODE

0.458 (11.63)

0.085 (2.16)

0.025 (0.64)

LAND PATTERN RECOMMENDATION

Recommended Pb-Free IR Prole

Recommended reow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.

Package Characteristics

Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Notes

Input-Output Momentary

Withstand Voltage

VISO 5000 Vrms RH < 50%, t = 1 min.,

TA = 25°C

1,2,3

Resistance (Input-Output) RI-O >109V

I-O = 500 VDC 3

Capacitance (Input-Output) CI-O 1.3 pF f = 1 MHz 3

Input IC Junction-to-Case

Thermal Resistance

Tjci 120 °C/W TA = 85°C

Output IC Junction-to-Case

Thermal Resistance

Tjco 100 °C/W TA = 85°C

Regulatory Information

The HCPL-788J has been approved by the following organizations:

IEC/EN/DIN EN 60747-5-2

Approved under:

IEC 60747-5-2:1997 + A1:2002

EN 60747-5-2:2001 + A1:2002

DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01.

Recognized under UL 1577, component recognition

program, File E55361.

CSA

Approved under CSA Component Acceptance Notice

#5, File CA 88324.

Figure 2. Dependence of safety-limiting values on

temperature.

IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*

Description Symbol Characteristic Unit

Installation classication per DIN VDE 0110/1.89, Table 1

for rated mains voltage ≤ 300 Vrms

for rated mains voltage ≤ 600 Vrms

for rated mains voltage ≤ 1000 Vrms

I-IV

I-III

Climatic Classication 55/85/21

Pollution Degree (DIN VDE 0110/1.89) 2

Maximum Working Insulation Voltage VIORM 1230 VPEAK

Input to Output Test Voltage, Method b**

IORM x 1.875 = VPR, 100% Production Test with

tm = 1 sec, Partial discharge < 5 pC

VPR 2306 VPEAK

Input to Output Test Voltage, Method a**

IORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec,

Partial discharge < 5 pC

VPR 1968 VPEAK

Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 8000 VPEAK

Safety-limiting values — maximum values allowed in the

event of a failure, also see Figure 2.

Case Temperature

Input Power

Output Power

PS1, INPUT

PS1, OUTPUT

175

400

600

°C

Insulation Resistance at TSI, VIO = 500 V RS>109

– POWER – mW

– CASE TEMPERATURE – °C

20025

800

50 75 100

200

150 175

– OUTPUT

– INPUT

125

400

600

* Isolation characteristics are guaranteed only within the safety maximum ratings which must

be ensured by protective circuits within the application. Surface Mount Classication is class

A in accordance with CECC00802.

** Refer to the optocoupler section of the isolation and Control Components Designer’s

Catalog, under Product Safety Regulations section IEC/EN/DIN EN 6747-5-2, for a detailed

description of Method a and Method b partial discharge test proles.

Insulation and Safety Related Specications

Parameter Symbol Min. Max. Conditions

Minimum External Air Gap

(Clearance)

L(101) 8.3 mm Measured from input terminals to output terminals,

shortest distance through air.

Minimum External Tracking

(Creepage)

L(102) 8.3 mm Measured from input terminals to output terminals,

shortest distance path along body.

Minimum Internal Plastic Gap 0.5 mm Through insulation distance conductor to conductor,

usually the straight line distance thickness between the

emitter and detector.

Tracking Resistance CTI >175 Volts DIN IEC 112/VDE 0303 Part 1

Comparative Tracking Index)

Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Note

Storage Temperature TS-55 125 °C

Operating Temperature TA-40 100 °C

Supply Voltages VDD1, VDD2 0.0 5.5 V 4

Steady-State Input Voltage VIN+, VIN- -2.0 VDD1 + 0.5 V

2 Second Transient Input Voltage VIN+, VIN- -6.0 VDD1 + 0.5 V

Output Voltage VOUT -0.5 VDD2 + 0.5 V

Absolute Value Output Voltage ABSVAL -0.5 VDD2 + 0.5 V

Reference Input Voltage VREF 0V

DD2 + 0.5 V V 5

Reference Input Current IREF 20 mA

Output Current IVOUT 20 mA

Absolute Value Current IABSVAL 20 mA

FAULT Output Current IFAULT 20 mA

Input IC Power Dissipation PI200 mW

Output IC Power Dissipation PO200 mW

Recommended Operating Conditions

Parameter Symbol Min. Max. Units Note

Ambient Operating Temperature TA-40 85 °C

Supply Voltages VDD1, VDD2 4.5 5.5 V

Input Voltage (accurate and linear) VIN+, VIN- -200 200 mV

Input Voltage (functional) VIN+, VIN- -2 2 V

Reference Input Voltage VREF 4.0 VDD2 V

FAULT Output Current IFAULT 4mA

DC Electrical Specications

Unless otherwise noted, all typicals and gures are at the nominal operating conditions of VIN+ = 0, VIN- = 0 V, VREF =

4.0 V, VDD1 = VDD2 = 5 V and TA = 25°C; all Minimum/Maximum specications are within the Recommended Operating

Conditions.

Parameter Symbol Min. Typ. Max. Units

Test

Conditions Fig. Note

Input Oset

Voltage

VOS -3 0 3 mV VIN+ = 0 V,

TA = –40°C to +85°C

3, 4,

Magnitude of Input

Oset Change vs.

Temperature

|∆VOS/∆TA| 1 10 µV/°C VIN+ = 0 V,

TA = –40°C to +85°C

VOUT Gain G VREF/504

mV - 3%

VREF/504

mV + 3%

V/V |VIN+| < 200 mV,

TA = 25°C

6,7,

8,9

VOUT Gain G VREF/504

mV - 5%

VREF/504

mV + 5%

V/V |VIN+| < 200 mV,

TA = –40°C to +85°C

6,7,

8,9

Magnitude of VOUT

Gain Change vs.

Temperature

|∆G/∆TA| 50 300 ppm/°C |VIN+| < 200 mV,

TA = –40°C to +85°C

6,7,

8,9

VOUT 200 mV

Nonlinearity

NL200 0.06 0.4 % |VIN+| < 200 mV,

TA = –40°C to +85°C

6,7,

8,9

Maximum Input

Voltage Before

VOUT Clipping

|VIN+|MAX 256 mV

FAULT Detection

Threshold

|VTHF| 230 256 280 mV 10 9

FAULT Low

Output Voltage

VOLF 350 800 mV IOL = 4 mA

FAULT High

Output Current

IOHF 0.2 15 µA VFAULT = VDD2

ABSVAL Output

Error

eABS 0.6 2 % of

full scale

output

11 10

Input Supply

Current

IDD1 10.7 20 mA

Output Supply

Current

IDD2 10.4 20 mA

Reference Voltage

Input Current

IVREF 0.26 1 mA

Input Current IIN+ -350 nA VIN+ = 0 V

Input Resistance RIN 800 k VIN+ = 0 V

VOUT Output

Resistance

ROUT 0.2 

ABSVAL Output

Resistance

RABS 0.3 

Input DC Common-

Mode Rejection

Ratio

CMRRIN 85 dB 11

AC Electrical Specications

Unless otherwise noted, all typicals and gures are at the nominal operating conditions of VIN+ = 0, VIN- = 0 V, VREF =

4.0 V, VDD1 = VDD2 = 5 V and TA = 25°C; all Minimum/Maximum specications are within the Recommended Operating

Conditions.

Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note

VOUT Bandwidth (-3dB) BW 20 30 kHz VIN+ = 200 mVpk-pk

sine wave.

12,

VOUT Noise NOUT 2.2 4 mVrms VIN+ = 0 V 20 12

VIN to VOUT Signal Delay

(50 - 50%)

tDSIG 920µsV

IN+ = 50 mV to

200 mV step.

14,

VOUT Rise/Fall Time

(10–90)

tRFSIG 10 25 µs VIN+ = 50 mV to

200 mV step.

14,

ABSVAL Signal Delay tDABS 920µsV

IN+ = 50 mV to

200 mV step.

14,

ABSVAL Rise/Fall Time

(10–90%)

tRFABS 10 25 µs VIN+ = 50 mV to

200 mV step.

14,

FAULT Detection Delay tFHL 3 6 µs VIN+ = 0 mV to

±500 mV step.

15,

FAULT Release Delay tFLH 10 20 µs VIN+ = ±500 mV to

0 mV step.

16,

Transient Fault Rejection tREJECT 1 2 µs VIN+ = 0 mV to

±500 mV pulse.

17,

Common Mode Transient

Immunity

CMTI 10 25 kV/µs For VOUT, FAULT, and

ABSVAL outputs.

Common-Mode Rejection

Ratio at 60 Hz

CMRR >140 dB 18

Notes:

1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 600 Vrms for 1 second. This test is

performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-2 Insulation Characteristic Table,

if applicable.

2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output

continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specication or IEC/EN/DIN EN 60747-5-2

insulation characteristics table.

3. Device considered a two terminal device: pins 1-8 shorted together and pins 9-16 shorted together.

4. VDD1 must be applied to both pins 5 and 7. VDD2 must be applied to both pins 10 and 15.

5. If VREF exceeds VDD2 (due to power-up sequence, for example), the current into pin 11 (IREF) should be limited to 20 mA or less.

6. Input Oset voltage is dened as the DC Input voltage required to obtain an output voltage (at pin 12) of VREF/2.

7. This is the Absolute Value of Input Oset Change vs. Temperature.

8. This is the Absolute Value of VOUT Gain Change vs. Temperature.

9. |VIN+| must exceed this amount in order for the FAULT output to be activated.

10. ABSVAL is derived from VOUT (which has the gain and oset tolerances stated earlier). ABSVAL is 0 V when VIN = 0 V and increases toward VREF as

VIN approaches +256 mV or -256 mV. HABS is the dierence between the actual ABSVAL output and what ABSVAL should be, given the value of

VOUT. HABS is expressed in terms of percent of full scale and is dened as:

|ABSVAL - 2 x | VOUT - VREF / 2| | x 100.

REF

11. CMRRIN is dened as the ratio of the gain for dierential inputs applied between pins 1 and 2 to the gain for common mode inputs applied to

both pins 1 and 2 with respect to pin 8.

12. The signal-to-noise ratio of the HCPL-788J can be improved with the addition of an external low pass lter to the output. See Frequently Asked

Question #4.2 in the Applications Information Section at the end of this data sheet.

13. As measured from 50% of VIN to 50% of VOUT.

14. This is the amount of time from when the FAULT Detection Threshold (230 mV ≤ VTHF ≤ 280 mV) is exceeded to when the FAULT output goes

low.

15. This is the amount of time for the FAULT Output to return to a high state once the FAULT Detection Threshold (230 mV ≤ VTHF ≤ 280 mV) is no

longer exceeded.

16. Input pulses shorter than the fault rejection pulse width (tREJECT), will not activate the FAULT (pin 14) output. See Frequently Asked Question #2.3

in the Applications Information Section at the end of this data sheet for additional detail on how to avoid false tripping of the FAULT output due

to cable capacitance charging transients.

17. CMTI is also known as Common Mode Rejection or Isolation Mode Rejection. It is tested by applying an exponentially rising falling voltage

step on pin 8 (GND1) with respect to pin 9 (GND2). The rise time of the test waveform is set to approximately 50 ns. The amplitude of the step

is adjusted until VOUT (pin 12) exhibits more than 100 mV deviation from the average output voltage for more than 1µs. The HCPL-788J will

continue to function if more than 10 kV/µs common mode slopes are applied, as long as the break-down voltage limitations are observed. [The

HCPL-788J still functions with common mode slopes above 10 kV/µs, but output noise may increase to as much as 600 mV peak to peak.]

18. CMRR is dened as the ratio of dierential signal gain (signal applied dierentially between pins 1 and 2) to the common mode gain (input pins

tied to pin 8 and the signal applied between the input and the output of the isolation amplier) at 60 Hz, expressed in dB.

Figure 3. Input oset voltage change vs.

temperature.

Figure 4. Input oset voltage change vs. VDD1. Figure 5. Input oset voltage change vs. VDD2.

Figure 6. VOUT vs. VIN. Figure 7. Gain change vs. temperature. Figure 8. Gain change vs. VDD1.

ΔV

OFFSET CHANGE – μV

4.5

-800

INPUT SUPPLY VOLTAGE – V

DD1

– V

800

4.75 5.0 5.25 5.5

600

400

200

-200

-400

-600

ΔV

OFFSET CHANGE – μV

4.5

-800

OUTPUT SUPPLY VOLTAGE – V

DD2

– V

800

4.75 5.0 5.25 5.5

600

400

200

-200

-400

-600

OUT

– OUTPUT VOLTAGE – V

-300

INPUT VOLTAGE – V

– mV

4.0

-200 0 100 300

2.0

3.5

3.0

2.5

1.5

1.0

0.5

-100 200

ΔGAIN CHANGE-%

-40

-2.0

TEMPERATURE – °C

-20

2.0

020

-1.0

60 80

TYPICAL

WORST CASE

1.0

1.5

0.5

-0.5

-1.5

ΔGAIN CHANGE-%

4.5

-2.0

INPUT SUPPLY VOLTAGE – VDD1 – V

2.0

4.75 5.0 5.25 5.5

1.5

1.0

0.5

-0.5

-1.0

-1.5

Figure 9. Gain change vs. VDD2. Figure 10. FAULT output voltage vs. VIN. Figure 11. ABSVAL output voltage vs. VIN.

ΔGAIN CHANGE-%

4.5

-2.0

OUTPUT SUPPLY VOLTAGE – VDD2 – V

2.0

4.75 5.0 5.25 5.5

1.5

1.0

0.5

-0.5

-1.0

-1.5

FAULT OUTPUT VOLTAGE – FAULTBAR – V

-300

INPUT VOLTAGE – VIN – mV

5.0

-200 0 100 300

2.0

3.5

3.0

2.5

1.5

1.0

0.5

-100 200

4.0

4.5

ABSVAL – ABSOLUTE VALUE OUTPUT – V

-300

INPUT VOLTAGE – VIN – mV

4.0

-200 0 100 300

2.0

3.5

3.0

2.5

1.5

1.0

0.5

-100 200

INPUT OFFSET CHANGE - ΔVOS - uV

-40

-800.0

TEMPERATURE – DEG C

-20

800.0

020

-400.0

60 80

TYPICAL

MAX

400.0

600.0

200.0

-200.0

-600.0

Figure 15. FAULT detection, 0 to 300 mV input,

at VREF = 5 V.

Figure 12. Bandwidth vs. temperature. Figure 13. FAULT detection delay vs. tempera-

ture.

Figure 14. Step response, 0 to 200 mV input, at

VREF = 5 V.

Figure 16. FAULT release, 300 to 0 mV input, at

VREF = 5 V.

Figure 17. FAULT rejecting a 1 μs, 0 to 2 V to 0

input. Rejection is independent of amplitude.

Figure 18. Detection of 6 μs fault 0 to 2 V to

0 input, at VREF = 5 V.

Figure 19. Sine response 400 mV pk to pk 4 kHz

input, at VREF = 5 V.

BANDWIDTH – kHz

-40

TEMPERATURE – °C

-20

020 608040

FAULT DETECTION DELAY – μs

-40

2.5

TEMPERATURE – °C

-20

3.5

020 6080

3.0

2.75

3.25

0 V

2.5 V

5 V

0 V

2.5 V

5 V

0 V

2.5 V

5 V

-300 mV

0 mV

300 mV

5.00 μs/DIV

IN 300 mV/D

OUT

(PIN 12)

2.5 V/D

FAULT (PIN 14) 2.5 V/D

ABSVAL (PIN 13)

2.5 V/D

0 V

2.5 V

5 V

0 V

2.5 V

5 V

0 V

2.5 V

5 V

-300 mV

0 mV

300 mV

5.00 μs/DIV

IN 300 mV/D

OUT

(PIN 12) 2.5 V/D

ABSVAL (PIN 13)

2.5 V/D

FAULT (PIN 14)

2.5 V/D

0 V

2.5 V

5.0 V

0 V

2.5 V

5.0 V

0 V

2.5 V

5.0 V

-2 V

0 mV

2 V

5.00 μs/DIV

2.0 V/D

OUT

(PIN 12) 2.5 V/D

ABSVAL (PIN 13)

2.5 V/D

FAULT

(PIN 14)

2.5 V/D

0 V

2.5 V

5 V

0 V

2.5 V

5 V

0 V

2.5 V

5 V

-300 mV

0 mV

300 mV

100 μs/DIV

VIN 300 mV/D

VOUT (PIN 12) 2.5 V/D

ABSVAL (PIN 13) 2.5 V/D

FAULT (PIN 14) 2.5 V/D

0 V

2.5 V

5 V

0 V

2.5 V

5 V

0 V

2.5 V

5 V

-300 mV

0 mV

300 mV

5.00 μs/DIV

IN 300 mV/D

OUT

(PIN 12) 2.5 V/D

ABSVAL (PIN 13) 2.5 V/D

FAULT (PIN 14) 2.5 V/D

5.00 μs/DIV

0 V

2.5 V

5 V

0 V

2.5 V

5 V

0 V

2.5 V

5 V

-300 mV

0 mV

300 mV

FAULT (PIN 14) 2.5 V/D

300 mV/D

OUT

(PIN 12) 2.5 V/D

ABSVAL (PIN 13)

2.5 V/D

Figure 20. AC test circuit.

Figure 21. Internal block diagram.

10,15

9, 16

5, 7

2, 8

FAULT

ABSVAL

VOUT

VDD2

VIN+

VDD1

4.7 kΩ

50 Ω

0.01 μF

0.1 μF

HCPL-788J

VREF

10 Ω

0.1 μF

5 V

1VREF

VOUT

FAULT

ABSVAL

VDD2

GND2

VIN+

VIN-

VLED+

VDD1

GND1

ΣΔ

MODULATOR

256 mV

REFERENCE

FAULT

DETECT ENCODER

RECTIFIER

DECODER D/A LPF

HCPL-788J

Figure 24. ABSVAL with 1 phase.Figure 23. ABSVAL with 2 phases, wired-ORed

together.

Figure 22. ABSVAL with 3 phases, wired-ORed

together.

ABSVAL – V

TIME – SECONDS

4.0

0.01 0.02 0.03 0.04

2.0

3.0

1.0

Applications Information

Production Description

Figure 21 shows the internal block diagram of the HCPL-

788J. The analog input (VIN) is con verted to a digital signal

using a sigma-delta (∑-∆) analog to digital (A/D) convert-

er. This A/D samples the input 6 million times per second

and generates a high speed 1-bit output representing

the input very accurately. This 1 bit data stream is trans-

mitted via a light emitting diode (LED) over the optical

barrier after encoding. The detector converts the optical

signal back to a bit stream. This bit stream is decoded

and drives a 1 bit digital to analog (D/A) con verter. Finally

a low pass lter and output buer drive the output signal

(VOUT) which linearly rep re sents the analog input. The out-

put signal full-scale range is determined by the external

reference voltage (VREF). By sharing this reference voltage

(which can be the supply voltage), the full-scale range of

the HCPL-788J can precisely match the full-scale range of

an external A/D converter.

In addition, the HCPL-788J compares the analog input

(VIN) to both the negative and positive full-scale values.

If the input exceeds the full-scale range, the short-circuit

fault output (FAULT) is activated quickly. This feature op-

erates indepen dently of the ∑-∆ A/D converter in order

to provide the high-speed response (typically 3 µs) need-

ed to protect power tran sistors. The FAULT output is wire

OR-able so that a short circuit on any one motor phase

can be detected using only one signal.

One other output is provided — the rectied output

(ABSVAL). This output is also wire OR-able. The motor

phase having the highest instantaneous rectied out-

put pulls the common output high. When three sinu-

soidal motor phases are combined, the rectied output

(ABSVAL) is essentially a DC signal represent ing the rms

motor current. This single DC signal and a threshold

comparator can indicate motor overload conditions be-

fore dam age to the motor or drive occur. Figure 22 shows

the ABSVAL output when 3 HCPL-788Js are used to mon-

itor a sinusoidal 60 Hz current. Figures 23 and 24 show

the ABSVAL output when only 2 or 1 of the 3 phases are

monitored, respectively.

The HCPL-788J’s other main function is to provide gal-

vanic isolation between the analog input and the ana-

log output. An internal voltage reference determines the

full-scale analog input range of the modulator (approxi-

mately ±256 mV); an input range of ±200 mV is recom-

mended to achieve optimal performance.

ABSVAL – V

TIME – SECONDS

4.0

0.01 0.02 0.03 0.04

2.0

3.0

1.0

ABSVAL – V

TIME – SECONDS

4.0

0.01 0.02 0.03 0.04

2.0

3.0

1.0

Analog Interfacing

Power Supplies and Bypassing

The recommended supply con nec tions are shown in

Figure 26. A oating power supply (which in many ap-

plications could be the same supply that is used to drive

the high-side power transistor) is regulated to 5 V us-

ing a simple zener diode (D1); the value of resistor R4

should be chosen to supply sucient current from the

existing oating supply. The voltage from the current

sensing resistor (Rsense) is applied to the input of the

HCPL-788J through an RC anti-aliasing lter (R2 and C2).

Figure 25. Recommended applications circuit.

Figure 26. Recommended supply and sense resistor connections.

Although the application cir cuit is relatively simple, a few

re c ommendations should be followed to ensure optimal

performance.

The power supply for the HCPL-788J is most often ob-

tained from the same supply used to power the power

transistor gate drive circuit. If a dedicated supply is re-

quired, in many cases it is possible to add an additional

winding on an existing trans former. Otherwise, some

sort of simple isolated supply can be used, such as a line

powered transformer or a high-frequency DC-DC con-

verter.

GND2

VDD2

FAULT

ABSVAL

VOUT

VREF

VDD2

GND2

VIN+

VIN-

VDD1

VLED1+

VDD1

GND1

RSHUNT

0.02 Ω

ISOLATED +5 V

R3 4.7 kΩ

39 Ω

.01 μF

0.1 μF

HCPL-788J

INPUT

CURRENT

+5 V

A/D

VREF

GND

μC

TO OTHER

PHASE OUTPUTS

R1 C2 C6

0.1 μF

C4C8 C7 C5

C5 = C7 = C8 = 470 pF

C4 = 0.1 μF

GND2

DD2

FAULT

ABSVAL

OUT

REF

DD2

GND

DD1

IN+

IN-

GND

DD1

LED+

39 Ω

0.1 μF

0.01 μF

FLOATING

POWER

SUPPLY

HV+ +

–

SENSE

HV-

MOTOR

5.1 V

GATE DRIVE

CIRCUIT

HCPL-788J

An inexpensive 78L05 three-terminal regulator can also

be used to reduce the oating supply voltage to 5 V. To

help attenuate high-frequency power supply noise or

ripple, a resistor or inductor can be used in series with

the input of the regulator to form a low-pass lter with

the regulator’s input bypass capacitor.

As shown in Figure 25, 0.1 µF bypass capacitors (C1, C3,

C4, and C6) should be located as close as possible to the

pins of the HCPL-788J. The bypass capacitors are required

because of the high-speed digital nature of the signals

inside the HCPL-788J. A 0.01 µF bypass capacitor (C2) is

also recommended at the input due to the switched-ca-

pacitor nature of the input circuit. The input bypass ca-

pacitor also forms part of the anti-aliasing lter, which

is recommended to prevent high-frequency noise from

aliasing down to lower frequencies and interfering with

the input signal. The input lter also performs an impor-

tant reliability function — it reduces transient spikes

from ESD events owing through the current sensing

resistor.

Figure 27. Example printed circuit board layout.

PC Board Layout

The design of the printed circuit board (PCB) should fol-

low good layout practices, such as keeping bypass ca-

pacitors close to the supply pins, keeping output signals

away from input signals, the use of ground and power

planes, etc. In addition, the layout of the PCB can also af-

fect the isolation transient immunity (CMTI) of the HCPL-

788J, due primarily to stray capacitive coupling between

the input and the output circuits. To obtain optimal CMTI

performance, the layout of the PC board should mini-

mize any stray coupling by maintaining the maximum

possible distance between the input and output sides of

the circuit and ensuring that any ground or power plane

on the PC board does not pass directly below or extend

much wider than the body of the HCPL-788J.

TOP LAYER

BOTTOM LAYER

Current Sensing Resistors

The current sensing resistor should have low resistance

(to minimize power dissipation), low inductance (to min-

imize di/dt induced voltage spikes which could adversely

aect operation), and reasonable tolerance (to main tain

overall circuit accuracy). Choosing a particular value for

the resistor is usually a compro mise between minimiz-

ing power dissipation and maximizing ac curacy. Smaller

sense resistance decreases power dissipation, while larg-

er sense resistance can improve circuit accuracy by utiliz-

ing the full input range of the HCPL-788J.

The rst step in selecting a sense resistor is determin-

ing how much current the resistor will be sens ing. The

graph in Figure 28 shows the rms current in each phase

of a three-phase induction motor as a function of aver-

age motor output power (in horse power, hp) and motor

drive supply voltage. The maximum value of the sense

resistor is determined by the current being measured

and the maximum recommended input voltage of the

isolation amplier. The maxi mum sense resistance can

be calculated by taking the maxi mum recommended

input voltage and dividing by the peak current that the

sense resistor should see during normal operation. For

example, if a motor will have a maximum rms current

of 10 A and can experience up to 50% overloads during

normal operation, then the peak current is 21.1 A (=10

x 1.414 x 1.5). Assuming a maximum input voltage of 200

mV, the maximum value of sense resistance in this case

would be about 10 mΩ.

The maximum average power dissipation in the sense

resistor can also be easily calculated by multiplying the

sense resistance times the square of the maximum rms

current, which is about 1 W in the previous example.

If the power dissipation in the sense resistor is too

high, the resistance can be decreased below the

maximum value to decrease power dissipation.

The minimum value of the sense resistor is limited by

precision and accuracy requirements of the design. As

the resistance value is reduced, the output voltage across

the resistor is also reduced, which means that the oset

and noise, which are xed, become a larger percentage

of the signal amplitude. The selected value of the sense

resistor will fall somewhere between the minimum and

maximum values, depending on the particular require-

ments of a specic design.

When sensing currents large enough to cause signicant

heating of the sense resistor, the temperature coecient

(tempco) of the resistor can introduce nonlinearity due

to the signal dependent temperature rise of the resistor.

The eect increases as the resistor-to-ambient thermal

resistance increases. This eect can be minimized by

reducing the thermal resistance of the current sens-

ing resistor or by using a resistor with a lower tempco.

Lowering the thermal resistance can be accomplished

by reposi tion ing the current sensing resistor on the PC

board, by using larger PC board traces to carry away

more heat, or by using a heat sink.

For a two-terminal current sensing resistor, as the value of

resistance decreases, the resistance of the leads become

a signicant per centage of the total resistance. This has

two primary eects on resistor accuracy. First, the eec-

tive resistance of the sense resistor can become depen-

dent on factors such as how long the leads are, how they

are bent, how far they are inserted into the board, and

how far solder wicks up the leads during assembly (these

issues will be discussed in more detail shortly). Second,

the leads are typically made from a material, such as cop-

per, which has a much higher tempco than the material

from which the resis tive element itself is made, result ing

in a higher tempco overall.

Both of these eects are eliminated when a four-terminal

current sensing resistor is used. A four-terminal resistor

has two additional terminals that are Kelvin-connected

directly across the resistive element itself; these two ter-

minals are used to monitor the voltage across the resis-

tive element while the other two terminals are used to

carry the load current. Because of the Kelvin connection,

any voltage drops across the leads carrying the load cur-

rent should have no impact on the measured voltage.

Figure 28. Motor output horsepower vs. motor

phase current and supply voltage.

MOTOR OUTPUT POWER – HORSEPOWER

MOTOR PHASE CURRENT – A (rms)

5202535

10 15 30

440

380

220

120

Sense Resistor Connections

The recommended method for connecting the

HCPL-788J to the current sensing resistor is shown

in Figure 26. VIN+ (pin 1 of the HCPL-788J) is con-

nected to the positive terminal of the sense resis-

tor, while VIN- (pin 2) is shorted to GND1 (pin 8), with

the power-supply return path functioning as the sense line

to the negative terminal of the current sense

resistor. This allows a single pair of wires or

PC board traces to connect the HCPL-788J circuit to the

sense resistor. By referencing the input circuit to the neg-

ative side of the sense resistor, any load current induced

noise transients on the resistor are seen as a common-

mode signal and will not interfere with the current-sense

signal. This is important because the large load currents

owing through the motor drive, along with the para-

sitic inductances inherent in the wiring of the circuit, can

generate both noise spikes and osets that are rela tively

large compared to the small voltages that are being

measured across the current sensing resistor.

If the same power supply is used both for the gate drive circuit

and for the current sensing circuit, it is very important

that the connection from GND1 of the HCPL-788J to the

sense resistor be the only return path for supply current

to the gate drive power supply in order to eliminate po-

tential ground loop problems. The only direct connec-

tion between the HCPL-788J circuit and the gate drive

circuit should be the positive power supply line. Please

refer to Avago Technologies’ Applications Note 1078 for

additional information on using Isolation Ampliers.

When laying out a PC board for the current sensing

resistors, a couple of points should be kept in mind.

The Kelvin connections to the resistor should be

brought together under the body of the resistor and

then run very close to each other to the input of the

HCPL-788J; this minimizes the loop area of the con-

nection and reduces the possibility of stray magnetic

elds from interfering with the measured signal. If

the sense resistor is not located on the same PC board as

the HCPL-788J circuit, a tightly twisted pair of wires can

accomplish the same thing.

Also, multiple layers of the PC board can be used to

increase current carrying capacity. Numerous plated-

through vias should surround each non-Kelvin terminal

of the sense resistor to help distribute the current be-

tween the layers of the PC board. The PC board should

use 2 or 4 oz. copper for the layers, resulting in a current

carrying capacity in excess of 20 A. Making the current

carrying traces on the PC board fairly large can also im-

prove the sense resistor’s power dissipation capability

by acting as a heat sink. Liberal use of vias where the

load current enters and exits the PC board is also recom-

mended.

Frequently Asked Questions about the HCPL-788J

1. The Basics

1.1: Why should I use the HCPL-788J for

sensing current when Hall-eect

sensors are available which don’t

need an isolated supply voltage?

Historically, motor control current sense designs have required trade-os between

signal accuracy, response time, and the use of discrete components to detect short

circuit and overload conditions. The HCPL-788J greatly simplies current-sense designs

by providing an output voltage which can connect directly to an A/D converter as well

as integrated short circuit and overload detection (eliminating the need for external

circuitry). Available in an auto-insertable, SO-16 package, the HCPL-788J is smaller

than and has better linearity, oset vs. temperature and Common Mode Rejection

(CMR) performance than most Hall-eect sensors.

1.2: What is the purpose of the VREF

input?

The VREF input establishes the full scale output range. VREF can be connected to the

supply voltage (VDD2) or a voltage between 4 V and VDD2. The nominal gain of the HCPL-

788J is the output full scale range divided by 504 mV.

1.3: What is the purpose of the rectied

(ABSVAL) output on pin 13?

When 3 phases are wire-ORed together, the 3 phase AC currents are combined to

form a DC voltage with very little ripple on it. This can be simply ltered and used

to monitor the motor load. Moderate overload currents which don’t trip the FAULT

output can thus be detected easily.

2. Sense Resistor and Input Filter

2.1: Where do I get 10 mΩ resistors? I

have never seen one that low.

Although less common than values above 10 Ω, there are quite a few manufacturers

of resistors suitable for measuring currents up to 50 A when combined with the HCPL-

788J. Example product information may be found at Vishay’s web site (http://www.

vishay.com) and Isotek’s web site (http://www.isotekcorp.com).

2.2: Should I connect both inputs

across the sense resistor instead of

grounding VIN- directly to pin 8?

This is not necessary, but it will work. If you do, be sure to use an RC lter on both pin

1 (VIN+) and pin 2 (VIN-) to limit the input voltage at both pads.

2.3: How can I avoid false tripping of the

fault output due to cable capacitance

charging transients?

In PWM motor drives there are brief spikes of current owing in the wires leading to

the motor each time a phase voltage is switched between states. The amplitude and

duration of these current spikes is determined by the slew rate of the power transis-

tors and the wiring impedances. To avoid false tripping of the FAULT output (pin 14)

the HCPL-788J includes a blanking lter. This lter ignores over-range input conditions

shorter than 1 µs. For very long motor wires, it may be necessary to increase the time

constant of the input RC antialiasing lter to keep the peak value of the HCPL-788J

inputs below ±230 mV. For example, a 39 Ω, 0.047 µF RC lter on pin 1 will ensure that

2 µs wide 500 mV pulses across the sense resistor do not trip the FAULT output.

2.4: Do I really need an RC lter on the

input? What is it for? Are other values

of R and C okay?

This lter prevents damage from input spikes which may go beyond the absolute

maximum ratings of the HCPL-788J inputs during ESD and other transient events. The

lter also prevents aliasing of high frequency (above 3 MHz) noise at the sampled

input. Other RC values are certainly OK, but should be chosen to prevent the input

voltage (pin 1) from exceeding ±5 V for any conceivable current waveform in the sense

resistor. Remember to account for inductance of the sense resistor since it is possible

to momentarily have tens of volts across even a 1 mΩ resistor if di/dt is quite large.

2.5: How do I ensure that the HCPL-788J

is not destroyed as a result of short

circuit conditions which cause

voltage drops across the sense

resistor that exceed the ratings of

the HCPL-788J’s inputs?

Select the sense resistor so that it will have less than 5 V drop when short circuits

occur. The only other requirement is to shut down the drive before the sense resistor is

damaged or its solder joints melt. This ensures that the input of the HCPL-788J cannot

be damaged by sense resistors going open-circuit.

3. Isolation and Insulation

3.1: How many volts will the HCPL-788J

withstand?

The momentary (1 minute) withstand voltage is 5000 V rms per UL1577 and CSA

Component Acceptance Notice #5.

3.2: What happens if I don’t use the

470 pF output capacitors Avago

recommends?

These capacitors are to reduce the narrow output spikes caused by high common

mode slew rates. If your application does not have rapid common mode voltage

changes, these capacitors are not needed.

4. Accuracy

4.1: What is the meaning of the oset

errors and gain errors in terms of the

output?

For zero input, the output should ideally be 1/2 of VREF. The nominal slope of the input/

output relationship is VREF divided by 0.504 V. Oset errors change only the DC input

voltage needed to make the output equal to 1/2 of VREF. Gain errors change only the

slope of the input/output relationship. For example, if VREF is 4.0 V, the gain should be

7.937 V/V. For zero input, the output should be 2.000 V. Input oset voltage of ±3 mV

means the output voltage will be 2.000 V ±0.003*7.937 or 2.000 ±23.8 mV when the

input is zero. Gain tolerance of ±5% means that the slope will be 7.937 ±0.397. Over

the full range of ±3 mV input oset error and ±5% gain error, the output voltage will

be 2.000 ±25.0 mV when the input is zero.

4.2: Can the signal to noise ratio be

improved?

Yes. Some noise energy exists beyond the 30 kHz bandwidth of the HCPL-788J.

An external RC low pass lter can be used to improve the signal to noise ratio. For

example, a 680 Ω, 4700 pF RC lter will cut the rms output noise roughly by a factor

of 2. This lter reduces the -3dB signal bandwidth only by about 10%. In applications

needing only a few kHz bandwidth even better noise performance can be obtained.

The noise spectral density is roughly 400 nV/ Hz below 15 kHz (input referred). As an

example, a 2 kHz (680 Ω, 0.1 µF) RC low pass lter reduces output noise to a typical

value of 0.08 mVrms.

4.3: I need 1% tolerance on gain. Does

Avago sell a more precise version?

At present Avago does not have a standard product with tighter gain tolerance. A 100

Ω variable resistor divider can be used to adjust the input voltage at pin 1, if needed.

4.4: The output doesn’t go all the way

to VREF when the input is above full

scale. Why not?

Op-amps are used to drive VOUT (pin 12) and ABSVAL (pin 13). These op-amps can

swing nearly from rail to rail when there is no load current. The internal VDD2 is about

100 mV below the external VDD2. In addition, the pullup and pulldown output tran-

sistors are not identical in capability. The net result is that the output can typically

swing to within 20 mV of GND2 and to within 150 mV of VDD2. When VREF is tied to

VDD2, the output cannot reach VREF exactly. This limitation has no eect on gain — only

on maximum output voltage. The output remains linear and accurate for all inputs

between -200 mV and +200 mV. For the maximum possible swing range, separate VREF

and VDD2 voltages can be used. Since 5.0 V is normally recommended for VDD2, use of

4.5 V or 4.096 V references for VREF allow the outputs to swing all the way up to VREF (and

down to typically 20 mV).

4.5: Does the gain change if the internal

LED light output degrades with

time?

No. The LED is used only to transmit a digital pattern. Gain is determined by a bandgap

voltage reference and the user-provided VREF. Avago has accounted for LED degrada-

tion in the design of the product to ensure long life.

4.6: Why is gain dened as VREF/504 mV,

not VREF/512 mV as expected, based

on Figure 24?

Ideally gain would be VREF/512 mV, however, due to internal settling characteristics,

the average eective value of the internal 256 mV reference is 252 mV.

5. Power Supplies and Start-Up

5.1: What are the output voltages before

the input side power supply is turned

on?

VOUT (pin 12) is close to zero volts, ABSVAL (pin 13) is close to VREF and FAULT (pin 14) is

in the high (inactive) state when power to the input side is o. In fact, a self test can

be performed using this information. In a motor drive, it is possible to turn o all the

power transistors and thus cause all the sense resistor voltages to be zero. In this case,

nding VOUT less than 1/4 of VREF, ABSVAL more than 3/4 of VREF and FAULT in the high state

indicates that power to the input side is not on.

5.2: How long does the HCPL-788J take

to begin working properly after

power-up?

About 50 µs after a VDD2 power-up and 100 µs after a VDD1 power-up.

6. Miscellaneous

6.1: How does the HCPL-788J measure

negative signals with only a +5 V

supply?

The inputs have a series resistor for protection against large negative inputs. Normal

signals are no more than 200 mV in amplitude. Such signals do not forward bias any

junctions suciently to interfere with accurate operation of the switched capacitor

input circuit.

6.2: What load capacitance can the HCPL-

788J drive?

Typically, noticeable ringing and overshoot begins for CLOAD above 0.02 µF. Avago

recommends keeping the load capacitance under 5000 pF (at pin 12). ABSVAL (pin

13) typically exhibits no instability at any load capacitance, but speed of response

gradually slows above 470 pF load.

6.3: Can I use the HCPL-788J with a

bipolar input A/D converter?

Yes, with a compromise on oset accuracy. One way to do this is by connecting +2.5

V to pins 10, 11, and 15 and connecting -2.5 V to pins 9 and 16 with 0.1 µF bypass

capacitors from +2.5 V to -2.5 V and from -2.5 V to ground. Note that FAULT cannot

swing above 2.5 V in this case, so a level shifter may be needed. Alternately, a single 5

V supply could be power the HCPL-788J which could drive an op amp congured to

subtract 1/2 of VREF from VOUT.

For product information and a complete list of distributors, please go to our website: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.

AV02-1546EN - February 8, 2010