V62/04684-01XE - Texas Instruments High-Performance Analog

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SCLS551 − DECEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DControlled Baseline

− One Assembly/Test Site, One Fabrication

Site

DExtended Temperature Performance of

−40°C to 125°C

DEnhanced Diminishing Manufacturing

Sources (DMS) Support

DEnhanced Product-Change Notification

DQualification Pedigree†

†Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

DESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

DInputs Are TTL-Voltage Compatible

description

The SN74AHCT126 device is a quadruple bus buffer gate featuring independent line drivers with 3-state

outputs. Each output is disabled when the associated output-enable (OE) input is low. When OE is high, the

respective gate passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a

pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the

driver.

ORDERING INFORMATION

TAPACKAGE‡ORDERABLE

PART NUMBER TOP-SIDE

MARKING

−40°C to 125°C

SOIC − D Tape and reel SN74AHCT126QDREP AHCT126QEP

−40

C to 125

TSSOP − PW Tape and reel SN74AHCT126QPWREP HB126EP

‡Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

OE A

OUTPUT

H H H

HLL

L X Z

1OE

2OE

GND

VCC

4OE

3OE

D OR PW PACKAGE

(TOP VIEW)

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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SCLS551 − DECEMBER 2003

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1OE

1A 1Y

2OE

2A 2Y

3OE

3A 3Y

4OE

4A 4Y

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

MIN MAX UNIT

VCC Supply voltage 4.5 5.5 V

VIH High-level input voltage 2 V

VIL Low-level input voltage 0.8 V

VIInput voltage 0 5.5 V

VOOutput voltage 0 VCC V

IOH High-level output current −8 mA

IOL Low-level output current 8 mA

∆t/∆vInput transition rise or fall rate 20 ns/V

TAOperating free-air temperature −40 125 °C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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SCLS551 − DECEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

TA = 25°C

MIN

MAX

UNIT

PARAMETER

TEST CONDITIONS

CC MIN TYP MAX

MIN

MAX

UNIT

VOH

IOH = −50 mA

4.5 V

4.4 4.5 4.4

VOH IOH = −8 mA 4.5 V 3.94 3.8 V

VOL

IOL = 50 mA

4.5 V

0.1 0.1

VOL IOL = 8 mA 4.5 V 0.36 0.44 V

IIVI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1mA

IOZ VO = VCC or GND 5.5 V ±0.25 ±2.5 mA

ICC VI = VCC or GND, IO = 0 5.5 V 2 20 mA

∆ICC†One input at 3.4 V,

Other inputs at VCC or GND 5.5 V 1.35 1.5 mA

CiVI = VCC or GND 5 V 4 10 pF

CoVO = VCC or GND 5 V 15 pF

†This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.

switching characteristics over recommended operating free-air temperature range,

VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

LOAD

TA = 25°C

MIN

MAX

UNIT

PARAMETER

FROM

(INPUT)

(OUTPUT)

LOAD

CAPACITANCE MIN TYP MAX

MIN

MAX

UNIT

tPLH

CL = 15 pF

3.8 5.5 1 6.5

tPHL A Y CL = 15 pF 3.8 5.5 1 6.5 ns

tPZH

CL = 15 pF

3.6 5.1 1 6

tPZL

Y CL = 15 pF 3.6 5.1 1 6 ns

tPHZ

CL = 15 pF

4.6 6.8 1 8

tPLZ

= 15 pF

4.6 6.8 1 8

tPLH

CL = 50 pF

5.3 7.5 1 8.5

tPHL A Y CL = 50 pF 5.3 7.5 1 8.5 ns

tPZH

CL = 50 pF

5.1 7.1 1 8

tPZL

Y CL = 50 pF 5.1 7.1 1 8 ns

tPHZ

CL = 50 pF

6.1 8.8 1 10

tPLZ

Y CL = 50 pF 6.1 8.8 1 10 ns

tsk(o) CL = 50 pF 1 ns

noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4)

PARAMETER MIN MAX UNIT

VOL(P) Quiet output, maximum dynamic VOL 0.8 V

VOL(V) Quiet output, minimum dynamic VOL −0.8 V

VOH(V) Quiet output, minimum dynamic VOH 4.4 V

VIH(D) High-level dynamic input voltage 2 V

VIL(D) Low-level dynamic input voltage 0.8 V

NOTE 4: Characteristics are for surface-mount packages only.

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SCLS551 − DECEMBER 2003

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

Cpd Power dissipation capacitance No load, f = 1 MHz 14 pF

PARAMETER MEASUREMENT INFORMATION

50% VCC

3 V

0 V

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Data Input

tPLH

tPHL

tPLH

VOH

VOL

3 V

0 V

50% VCC

Input

Out-of-Phase

Output

In-Phase

Output

Timing Input

50% VCC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

Output

Control

Output

Waveform 1

S1 at VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

≈VCC

0 V

50% VCC VOL + 0.3 V

50% VCC ≈0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open Drain

Open

VCC

GND

VCC

TEST S1

3 V

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

Input

NOTES: A. CL includes probe and jig capacitance.

B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.

D. The outputs are measured one at a time with one input transition per measurement.

From Output

Under Test CL

(see Note A)

LOAD CIRCUIT FOR

3-STATE AND OPEN-DRAIN OUTPUTS

RL = 1 kΩ

GND

From Output

Under Test CL

(see Note A)

Test

Point

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

Open

VOH − 0.3 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V 1.5 V1.5 V 1.5 V

Figure 1. Load Circuit and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

SN74AHCT126QDREP ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74AHCT126QPWREP ACTIVE TSSOP PW 14 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

V62/04684-01XE ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

V62/04684-01YE ACTIVE TSSOP PW 14 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74AHCT126-EP :

•Catalog: SN74AHCT126

•Automotive: SN74AHCT126-Q1

•Military: SN54AHCT126

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•Military - QML certified for Military and Defense Applications

PACKAGE OPTION ADDENDUM

www.ti.com 18-Sep-2008

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SN74AHCT126QDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

SN74AHCT126QPWREP TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74AHCT126QDREP SOIC D 14 2500 333.2 345.9 28.6

SN74AHCT126QPWREP TSSOP PW 14 2000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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