0
10
20
30
40
50
60
70
80
100
0 0.5 1.0 1.5 2.0
I - Output Current - A
O
Efficiency - %
2.5 3.0
90
VIN=12V
VOUT=3.3V
fsw=300kHz
PH
VIN
GND
BOOT
VSENSE
COMP
TPS54240
EN
RT /CLK
SS /TR
PWRGD
TPS54240-Q1
www.ti.com
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
3.5V to 42V STEP DOWN SWIFTDC/DC CONVERTER WITH ECO-MODE
Check for Samples: TPS54240-Q1
1FEATURES 0.8-V Internal Voltage Reference
MSOP10 Package With PowerPAD
2Qualified for Automotive Applications
Supported by SwitcherProSoftware Tool
3.5V to 42V Input Voltage Range (http://focus.ti.com/docs/toolsw/folders/print/s
200-mHigh-Side MOSFET witcherpro.html)
High Efficiency at Light Loads with a Pulse For SWIFTDocumentation, See the TI
Skipping Eco-ModeWebsite at http://www.ti.com/swift
138μA Operating Quiescent Current
1.3μA Shutdown Current APPLICATIONS
100kHz to 2.5MHz Switching Frequency 12-V and 24-V Industrial and Commercial Low
Synchronizes to External Clock Power Systems
Adjustable Slow Start/Sequencing GSM, GPRS Modules in Fleet Management,
UV and OV Power Good Output E-Meters, and Security Systems
Adjustable UVLO Voltage and Hysteresis
DESCRIPTION
The TPS54240-Q1 device is a 42V, 2.5A, step down regulator with an integrated high side MOSFET. Current
mode control provides simple external compensation and flexible component selection. A low ripple pulse skip
mode reduces the no load, regulated output supply current to 138μA. Using the enable pin, shutdown supply
current is reduced to 1.3μA, when the enable pin is low.
Under voltage lockout is internally set at 2.5V, but can be increased using the enable pin. The output voltage
startup ramp is controlled by the slow start pin that can also be configured for sequencing/tracking. An open
drain power good signal indicates the output is within 94% to 107% of its nominal voltage.
A wide switching frequency range allows efficiency and external component size to be optimized. Frequency fold
back and thermal shutdown protects the part during an overload condition.
The TPS54240-Q1 is available in 10 pin thermally enhanced MSOP Power Padpackage.
SIMPLIFIED SCHEMATIC EFFICIENCY vs LOAD CURRENT
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Eco-Mode, PowerPAD, SwitcherPro, SWIFT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright ©20102011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS54240-Q1
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION
ORDERABLE
TAPACKAGE(1) TOP-SIDE MARKING
PART NUMBER
TPS54240QDGQ
40°C to 125°C MSOP-10-DGQ Reel of 2500 5424Q
RQ1
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating temperature range (unless otherwise noted). VALUE
VIN 0.3 V to 47 V
EN(2) 0.3 V to 5 V
BOOT 55 V
VSENSE 0.3 V to 3 V
Input voltage COMP 0.3 V to 3 V
PWRGD 0.3 V to 6 V
SS/TR 0.3 V to 3 V
RT/CLK 0.3 V to 3.6 V
BOOT-PH 8 V
0.6 V to 47 V
Output voltage 200 ns 1 V to 47 V
PH 30 ns 2 V to 47 V
Maximum dc voltage, Tj=40°C -0.85V
Voltage difference PAD to GND ±200 mV
EN 100 μA
BOOT 100 mA
Source current VSENSE 10 μA
PH Current Limit
RT/CLK 100 μA
VIN Current Limit
COMP 100 μA
Sink current PWRGD 10 mA
SS/TR 200 μA
Electrostatic discharge (HBM) QSS 009-105 (JESD22-A114A) 2 kV
Electrostatic discharge (CDM) QSS 009-147 (JESD22-C101B.01) 1000 V
Operating junction temperature 40°C to 150°C
Storage temperature 65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See the Enable and Adjusting Undervoltage Lockout section of this datasheet for details.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
TAOperating ambient temperature 40 125 °C
2Copyright ©20102011, Texas Instruments Incorporated
TPS54240-Q1
www.ti.com
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
THERMAL INFORMATION TPS54240-Q1
THERMAL METRIC(1)(2) DGQ UNITS
10 PINS
θJA Junction-to-ambient thermal resistance (standard board) 62.5
θJA Junction-to-ambient thermal resistance (custom board)(3) 57
θJCtop Junction-to-case (top) thermal resistance 83
θJB Junction-to-board thermal resistance 28 °C/W
ψJT Junction-to-top characterization parameter 1.7
ψJB Junction-to-board characterization parameter 20.1
θJCbot Junction-to-case (bottom) thermal resistance 21
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Power rating at a specific ambient temperature TAshould be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
(3) Test boards conditions:
(a) 3 inches x 3 inches, 2 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground plane, bottom layer
(d) 6 thermal vias (13mil) located under the device package
ELECTRICAL CHARACTERISTICS
TJ=40°C to 150°C, VIN = 3.5 to 42V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 3.5 42 V
Internal undervoltage lockout No voltage hysteresis, rising and falling 2.5 V
threshold
Shutdown supply current EN = 0 V, 25°C, 3.5 V VIN 42 V 1.3 4
μA
Operating : nonswitching supply VSENSE = 0.83 V, VIN = 12 V, 25°C 138 200
current
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling, 25°C 1.15 1.25 1.36 V
Enable threshold +50 mV 3.8
Input current μA
Enable threshold 50 mV 0.9
Hysteresis current 2.9 μA
VOLTAGE REFERENCE
TJ= 25°C 0.792 0.8 0.808
Voltage reference V
0.784 0.8 0.816
HIGH-SIDE MOSFET
VIN = 3.5 V, BOOT-PH = 3 V 300
On-resistance m
VIN = 12 V, BOOT-PH = 6 V 200 410
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gM)2μA<ICOMP <2μA, VCOMP = 1 V 310 μMhos
2μA<ICOMP <2μA, VCOMP = 1 V,
Error amplifier transconductance (gM)70 μMhos
during slow start VVSENSE = 0.4 V
Error amplifier dc gain VVSENSE = 0.8 V 10,000 V/V
Error amplifier bandwidth 2700 kHz
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±27 μA
COMP to switch current 10.5 A/V
transconductance
CURRENT LIMIT
Current limit threshold VIN = 12 V, TJ= 25°C 3.5 6.1 A
Copyright ©20102011, Texas Instruments Incorporated 3
TPS54240-Q1
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TJ=40°C to 150°C, VIN = 3.5 to 42V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THERMAL SHUTDOWN
Thermal shutdown 182 °C
4Copyright ©20102011, Texas Instruments Incorporated
TPS54240-Q1
www.ti.com
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
ELECTRICAL CHARACTERISTICS (continued)
TJ=40°C to 150°C, VIN = 3.5 to 42V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching Frequency Range using 100 2500 kHz
RT mode
fSW Switching frequency RT= 200 k450 581 720 kHz
Switching Frequency Range using 300 2200 kHz
CLK mode
Minimum CLK input pulse width 40 ns
RT/CLK high threshold 1.9 2.2 V
RT/CLK low threshold 0.5 0.7 V
RT/CLK falling edge to PH rising Measured at 500 kHz with RT resistor in series 60 ns
edge delay
PLL lock in time Measured at 500 kHz 100 μs
SLOW START AND TRACKING (SS/TR)
Charge current VSS/TR = 0.4 V 2 μA
SS/TR-to-VSENSE matching VSS/TR = 0.4 V 45 mV
SS/TR-to-reference crossover 98% nominal 1.15 V
SS/TR discharge current (overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 382 μA
SS/TR discharge voltage VSENSE = 0 V 54 mV
POWER GOOD (PWRGD PIN)
VSENSE falling 92%
VSENSE rising 94%
VVSENSE VSENSE threshold VSENSE rising 109%
VSENSE falling 107%
Hysteresis VSENSE falling 2%
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA
On resistance I(PWRGD) = 3 mA, VSENSE <0.79 V 50
Minimum VIN for defined output V(PWRGD) <0.5 V, II(PWRGD) = 100 μA 0.95 1.5 V
Copyright ©20102011, Texas Instruments Incorporated 5
1
2
3
4
56
7
9
8
10
Thermal
Pad
(11)
BOOT
VIN
EN
PH
GND
COMP
VSENSE
PWRGD
SS/TR
RT/CLK
MSOP10
(TOP VIEW)
TPS54240-Q1
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
www.ti.com
DEVICE INFORMATION
PIN CONFIGURATION
PIN FUNCTIONS
PIN I/O DESCRIPTION
NAME NO.
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
BOOT 1 O minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
COMP 8 O components to this pin.
Enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the input
EN 3 I undervoltage lockout with two resistors.
GND 9 Ground
PH 10 I The source of the internal high-side power MOSFET.
POWERPAD 11 GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or
PWRGD 6 O EN shut down.
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
RT/CLK 5 I a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is
re-enabled and the mode returns to a resistor set function.
Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the
SS/TR 4 I voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
VIN 2 I Input supply voltage, 3.5 V to 42 V.
VSENSE 7 I Inverting node of the transconductance ( gm) error amplifier.
6Copyright ©20102011, Texas Instruments Incorporated
ERROR
AMPLIFIER
Boot
Charge
Boot
UVLO
UVLO
Current
Sense
Oscillator
withPLL
Frequency
Shift
Logic
And
PWMLatch
Slope
Compensation
PWM
Comparator
Minimum
Clamp
Pulse
Skip
Maximum
Clamp
Voltage
Reference
Overload
Recovery
VSENSE
SS/TR
COMP
RT/CLK
PH
BOOT
VIN
Thermal
Shutdown
EN
Enable
Comparator
Shutdown
Logic
Shutdown
Enable
Threshold
TPS54240 BlockDiagram
Logic
Shutdown
PWRGD
Shutdown
OV
GND
POWERPAD
7
4
8
5
9
11
10
1
2
3
6
UV
TPS54240-Q1
www.ti.com
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
FUNCTIONAL BLOCK DIAGRAM
Copyright ©20102011, Texas Instruments Incorporated 7
0.784
0.792
0.800
0.808
0.816
-50 -25 0 25 50 75 100 125 150
V -VoltageReference-V
ref
T -JunctionTemperature-°C
J
V =12V
I
0
125
250
375
500
-50 -25 0 25 50 75 100 125 150
T -JunctionTemperature-°C
J
RDSON-StaticDrain-SourceOn-StateResistance-mW
BOOT-PH=3V
BOOT-PH=6V
V =12V
I
550
570
580
590
600
610
-50 -25 0 25 50 75 100 125 150
f -SwitchingFrequency-kHz
s
560
T -JunctionTemperature-°C
J
V =12V,
RT =200k
I
W
5.0
5.5
6.0
7.0
-50 -25 0 25 50 75 100 125 150
SwitchCurrent- A
T -JunctionTemperature-°C
J
6.5
V =12V
I
TPS54240-Q1
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
www.ti.com
TYPICAL CHARACTERISTICS
ON RESISTANCE vs JUNCTION TEMPERATURE VOLTAGE REFERENCE vs JUNCTION TEMPERATURE
Figure 1. Figure 2.
SWITCH CURRENT LIMIT vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs JUNCTION TEMPERATURE
Figure 3. Figure 4.
SWITCHING FREQUENCY vs RT/CLK RESISTANCE HIGH SWITCHING FREQUENCY vs RT/CLK RESISTANCE LOW
FREQUENCY RANGE FREQUENCY RANGE
Figure 5. Figure 6.
8Copyright ©20102011, Texas Instruments Incorporated
20
60
100
120
-50 -25 0 25 50 75 100 125 150
gm- A/Vm
T -JunctionTemperature-°C
J
V =12V
I
40
80
200
250
300
350
400
500
-50 -25 0 25 50 75 100 125 150
gm- A/Vm
T -JunctionTemperature-°C
J
V =12V
I
450
1.10
1.20
1.30
1.40
-50 -25 0 25 50 75 100 125 150
EN-Threshold-V
T -JunctionTemperature-°C
J
V =12V
I
-4.25
-4
-3.75
-3.5
-3.25
-50 -25 0 25 50 75 100 125 150
I - A
(EN) m
T -JunctionTemperature-°C
J
V =12V,
V = Threshold+50mV
I
I(EN)
-1
-0.95
-0.9
-0.85
-0.8
-50 -25 025 50 75 100 125 150
I - A
(EN) m
T -JunctionTemperature-°C
J
V =12V,
V = Threshold-50mV
I
I(EN)
-3
-2.5
-2
-1.5
-1
-50 -25 0 25 50 75 100 125 150
I - A
(SS/TR) m
T -JunctionTemperature-°C
J
V =12V
I
TPS54240-Q1
www.ti.com
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
TYPICAL CHARACTERISTICS (continued)
EA TRANSCONDUCTANCE DURING SLOW START vs
JUNCTION TEMPERATURE EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE
Figure 7. Figure 8.
EN PIN VOLTAGE vs JUNCTION TEMPERATURE EN PIN CURRENT vs JUNCTION TEMPERATURE
Figure 9. Figure 10.
EN PIN CURRENT vs JUNCTION TEMPERATURE SS/TR CHARGE CURRENT vs JUNCTION TEMPERATURE
Figure 11. Figure 12.
Copyright ©20102011, Texas Instruments Incorporated 9
200
275
350
425
575
-50 0 50 100 150
I - A
I(SS/TR) m
T -JunctionTemperature-°C
J
V =12V
I
500
0
20
40
60
80
100
0 0.2 0.4 0.6 0.8
V -V
SENSE
V =12V,
T =25°C
I
J
%ofNominalfsw
0
0.5
1
1.5
2
-50 -25 0 25 50 75 100 125 150
I - A
(VIN) m
T -JunctionTemperature-°C
J
V =12V
I
0
0.5
1
1.5
2
0 10 20 30 40
V -InputVoltage-V
I
I - A
(VIN) m
T =25°C
J
70
110
130
150
170
210
-50 0 50 100 150
I - A
(VIN) m
T -JunctionTemperature-°C
J
V =12V,
V =0.83V
I
I(VSENSE)
90
190
110
130
150
170
0 20 40
I - A
(VIN) m
V -InputVoltage-V
I
T =25 C,
V =0.83V
J
I(VSENSE)
o
TPS54240-Q1
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SS/TR DISCHARGE CURRENT vs JUNCTION
TEMPERATURE SWITCHING FREQUENCY vs VSENSE
Figure 13. Figure 14.
SHUTDOWN SUPPLY CURRENT vs JUNCTION
TEMPERATURE SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (Vin)
Figure 15. Figure 16.
VIN SUPPLY CURRENT vs JUNCTION TEMPERATURE VIN SUPPLY CURRENT vs INPUT VOLTAGE
Figure 17. Figure 18.
10 Copyright ©20102011, Texas Instruments Incorporated
85
90
95
100
105
110
115
-50 -25 0 25 50 75 100 125 150
PWRGDThreshold-%ofVref
VSENSEFalling
VSENSERising
VSENSEFalling
VSENSERising
V =12V
I
T -JunctionTemperature-°C
J
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125 150
RDSON- W
T -JunctionTemperature-°C
J
V =12V
I
2
2.25
2.50
2.75
3
-50 -25 0 25 50 75 100 125 150
V -V
I(VIN)
T -JunctionTemperature-°C
J
1.5
1.8
2
2.3
2.5
-50 -25 0 25 50 75 100 125 150
V -V
I(BOOT-PH)
T -JunctionTemperature-°C
J
0
10
20
30
40
50
60
-50 -25 0 25 50 75 100 125 150
Offset-mV
T -JunctionTemperature-°C
J
V =0.4V
(SS/TR)
V =12V
I
0 200 400 600 800
0
600
100
200
300
400
Voltage Sense (mV)
Offset Voltage Threshold (mV)
500
VIN = 12 V
TJ= 25°C
TPS54240-Q1
www.ti.com
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
TYPICAL CHARACTERISTICS (continued)
PWRGD ON RESISTANCE vs JUNCTION TEMPERATURE PWRGD THRESHOLD vs JUNCTION TEMPERATURE
Figure 19. Figure 20.
BOOT-PH UVLO vs JUNCTION TEMPERATURE INPUT VOLTAGE (UVLO) vs JUNCTION TEMPERATURE
Figure 21. Figure 22.
SS/TR TO VSENSE OFFSET vs VSENSE SS/TR TO VSENSE OFFSET vs TEMPERATURE
Figure 23. Figure 24.
Copyright ©20102011, Texas Instruments Incorporated 11
TPS54240-Q1
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
www.ti.com
OVERVIEW
The TPS54240-Q1 device is a 42-V, 2.5-A, step-down (buck) regulator with an integrated high side n-channel
MOSFET. To improve performance during line and load transients the device implements a constant frequency,
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency of 100kHz to 2500kHz allows for efficiency and size optimization when selecting
the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin.
The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power
switch turn on to a falling edge of an external system clock.
The TPS54240-Q1 has a default start up voltage of approximately 2.5V. The EN pin has an internal pull-up
current source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with two
external resistors. In addition, the pull up current provides a default condition. When the EN pin is floating the
device will operate. The operating current is 138μA when not switching and under no load. When the device is
disabled, the supply current is 1.3μA.
The integrated 200mhigh side MOSFET allows for high efficiency power supply designs capable of delivering
2.5 amperes of continuous current to a load. The TPS54240-Q1 reduces the external component count by
integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a
capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the
high side MOSFET off when the boot voltage falls below a preset threshold. The TPS54240-Q1 can operate at
high duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8V
reference.
The TPS54240-Q1 has a power good comparator (PWRGD) which asserts when the regulated output voltage is
less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output
which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage
allowing the pin to transition high when a pull-up resistor is used.
The TPS54240-Q1 minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power
good comparator. When the OV comparator is activated, the high side MOSFET is turned off and masked from
turning on until the output voltage is lower than 107%.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor
divider can be coupled to the pin for critical power supply sequencing requirements. The SS/TR pin is discharged
before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault,
UVLO fault or a disabled condition.
The TPS54240-Q1, also, discharges the slow start capacitor during overload conditions with an overload
recovery circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal
regulation voltage once a fault condition is removed. A frequency foldback circuit reduces the switching
frequency during startup and overcurrent fault conditions to help control the inductor current.
12 Copyright ©20102011, Texas Instruments Incorporated
TPS54240-Q1
www.ti.com
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
DETAILED DESCRIPTION
Fixed Frequency PWM Control
The TPS54240-Q1 uses an adjustable fixed frequency, peak current mode control. The output voltage is
compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier
which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error
amplifier output is compared to the high side power switch current. When the power switch current reaches the
level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease
as the output current increases and decreases. The device implements a current limit by clamping the COMP pin
voltage to a maximum level. The Eco-Modeis implemented with a minimum clamp on the COMP pin.
Slope Compensation Output Current
The TPS54240-Q1 adds a compensating ramp to the switch current signal. This slope compensation prevents
sub-harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.
Pulse Skip Eco-Mode
The TPS54240-Q1 operates in a pulse skip Eco mode at light load currents to improve efficiency by reducing
switching and gate drive losses. The TPS54240-Q1 is designed so that if the output voltage is within regulation
and the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the
device enters Eco mode. This current threshold is the current level corresponding to a nominal COMP voltage or
500mV.
When in Eco-mode, the COMP pin voltage is clamped at 500mV and the high side MOSFET is inhibited. Further
decreases in load current or in output voltage can not drive the COMP pin below this clamp voltage level.
Since the device is not switching, the output voltage begins to decay. As the voltage control loop compensates
for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high side MOSFET is enabled
and a switching pulse initiates on the next switching cycle. The peak current is set by the COMP pin voltage. The
output voltage re-charges the regulated value, then the peak switch current starts to decrease, and eventually
falls below the Eco mode threshold at which time the device again enters Eco mode.
For Eco mode operation, the TPS54240-Q1 senses peak current, not average or load current, so the load current
where the device enters Eco mode is dependent on the output inductor value. For example, the circuit in
Figure 50 enters Eco mode at about 5 mA of output current. When the load current is low and the output voltage
is within regulation, the device enters a sleep mode and draws only 138μA input quiescent current. The internal
PLL remains operating when in sleep mode. When operating at light load currents in the pulse skip mode, the
switching transitions occur synchronously with the external clock signal.
Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54240-Q1 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT
and PH pins to provide the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when
the high side MOSFET is off and the low side diode conducts. The value of this ceramic capacitor should be
0.1μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher is
recommended because of the stable characteristics overtemperature and voltage.
To improve drop out, the TPS54240-Q1 is designed to operate at 100% duty cycle as long as the BOOT to PH
pin voltage is greater than 2.1V. When the voltage from BOOT to PH drops below 2.1V, the high side MOSFET
is turned off using an UVLO circuit which allows the low side diode to conduct and refresh the charge on the
BOOT capacitor. Since the supply current sourced from the BOOT capacitor is low, the high side MOSFET can
remain on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the
switching regulator is high.
The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the
power MOSFET, inductor resistance, low side diode and printed circuit board resistance. During operating
conditions in which the input voltage drops and the regulator is operating in continuous conduction mode, the
high side MOSFET can remain on for 100% of the duty cycle to maintain output regulation, until the BOOT to PH
voltage falls below 2.1V.
Copyright ©20102011, Texas Instruments Incorporated 13
4.6
4.8
5
5.2
5.4
5.6
0 0.05 0.10 0.15 0.20
I -OutputCurrent- A
O
V -InputVoltage-V
I
V =5V
O
Start
Stop
3
3.2
3.4
3.6
3.8
4
0 0.05 0.10 0.15 0.20
I -OutputCurrent- A
O
V -InputVoltage-V
I
V =3.3V
O
Start
Stop
TPS54240-Q1
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
www.ti.com
DETAILED DESCRIPTION (continued)
Attention must be taken in maximum duty cycle applications which experience extended time periods with light
loads or no load. When the voltage across the BOOT capacitor falls below the 2.1V UVLO threshold, the high
side MOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the
BOOT capacitor. The high side MOSFET of the regulator stops switching because the voltage across the BOOT
capacitor is less than 2.1V. The output capacitor then decays until the difference in the input voltage and output
voltage is greater than 2.1V, at which point the BOOT UVLO threshold is exceeded, and the device starts
switching again until the desired output voltage is reached. This operating condition persists until the input
voltage and/or the load current increases. It is recommended to adjust the VIN stop voltage greater than the
BOOT UVLO trigger condition at the minimum load of the application using the adjustable VIN UVLO feature with
resistors on the EN pin.
The start and stop voltages for typical 3.3V and 5V output applications are shown in Figure 25 and Figure 26.
The voltages are plotted versus load current. The start voltage is defined as the input voltage needed to regulate
the output within 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops
switching.
During high duty cycle conditions, the inductor current ripple increases while the BOOT capacitor is being
recharged resulting in an increase in ripple voltage on the output. This is due to the recharge time of the boot
capacitor being longer than the typical high side off time when switching occurs every cycle.
Figure 25. 3.3V Start/Stop Voltage Figure 26. 5.0V Start/Stop Voltage
Error Amplifier
The TPS54240-Q1 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8V voltage reference. The
transconductance (gm) of the error amplifier is 310μA/V during normal operation. During the slow start operation,
the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below
0.8V and the device is regulating using the SS/TR voltage, the gm is 70μA/V.
The frequency compensation components (capacitor, series resistor and capacitor) are added to the COMP pin
to ground.
Voltage Reference
The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output
of a temperature stable bandgap circuit.
Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use 1% tolerance or better divider resistors. Start with a 10 kfor the R2 resistor and use the Equation 1 to
calculate R1. To improve efficiency at light loads consider using larger value resistors. If the values are too high
the regulator will be more susceptible to noise and voltage errors from the VSENSE input current will be
noticeable.
14 Copyright ©20102011, Texas Instruments Incorporated
Vout 0.8V
R1 = R2 0.8 V
-
æ ö
´ç ÷
è ø
EN
VIN
+
-
TPS54240
R1
R2
Ihys
I1
0.9 Am
1.25V
2.9 Am
START STOP
HYS
V V
R1 I
-
=
ENA
START ENA 1
V
R2 V V I
R1
=-+
EN
Ihys
VIN
+
-
TPS54240
R1
R2
VOUT
R3
I1
0.9 Am2.9 Am
1.25V
TPS54240-Q1
www.ti.com
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
DETAILED DESCRIPTION (continued)
(1)
Enable and Adjusting Undervoltage Lockout
The TPS54240-Q1 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher
undervoltage lockout (UVLO), use the EN pin as shown in Figure 27 to adjust the input voltage UVLO by using
the two external resistors. Though it is not necessary to use the UVLO adjust registers, for operation it is highly
recommended to provide consistent power up behavior. The EN pin has an internal pull-up current source, I1, of
0.9μA that provides the default condition of the TPS54240-Q1 operating when the EN pin floats. Once the EN pin
voltage exceeds 1.25V, an additional 2.9μA of hysteresis, Ihys, is added. This additional current facilitates input
voltage hysteresis. Use Equation 2 to set the external hysteresis for the input voltage. Use Equation 3 to set the
input start voltage.
Figure 27. Adjustable Undervoltage Lockout (UVLO)
(2)
(3)
Another technique to add input voltage hysteresis is shown in Figure 28. This method may be used, if the
resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3
sources additional hysteresis current into the EN pin.
Figure 28. Adding Additional Hysteresis
Copyright ©20102011, Texas Instruments Incorporated 15
START STOP
OUT
HYS
V V
R1 V
IR3
-
=
+
ENA
START ENA ENA
1
V
R2 V V V
I
R1 R3
=-+ -
VIN
R1
R2
Node
5.8V
10kohm
ENA
Tss(ms) Iss( A)
Css(nF) = Vref (V) 0.8
m´
´
TPS54240-Q1
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
www.ti.com
DETAILED DESCRIPTION (continued)
(4)
(5)
Do not place a low-impedance voltage source with greater than 5 V directly on the EN pin. Do not place a
capacitor directly on the EN pin if VEN >5 V when using a voltage divider to adjust the start and stop voltage.
The node voltage, (see Figure 29) must remain equal to or less than 5.8 V. The zener diode can sink up to 100
µA. The EN pin voltage can be greater than 5 V if the VIN voltage source has a high impedance and does not
source more than 100 µA into the EN pin.
Figure 29. Node Voltage
Slow Start/Tracking Pin (SS/TR)
The TPS54240-Q1 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage
as the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to
ground implements a slow start time. The TPS54240-Q1 has an internal pull-up current source of 2μA that
charges the external slow start capacitor. The calculations for the slow start time (10% to 90%) are shown in
Equation 6. The voltage reference (VREF) is 0.8 V and the slow start current (ISS) is 2μA. The slow start capacitor
should remain lower than 0.47μF and greater than 0.47nF.
(6)
At power up, the TPS54240-Q1 will not start switching until the slow start pin is discharged to less than 40 mV to
ensure a proper power up, see Figure 30.
Also, during normal operation, the TPS54240-Q1 will stop switching and the SS/TR must be discharged to 40
mV, when the VIN UVLO is exceeded, EN pin pulled below 1.25V, or a thermal shutdown event occurs.
The VSENSE voltage will follow the SS/TR pin voltage with a 45mV offset up to 85% of the internal voltage
reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as
the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see
Figure 23). The SS/TR voltage will ramp linearly until clamped at 1.7V.
16 Copyright ©20102011, Texas Instruments Incorporated
EN
SS/TR
VSENSE
VOUT
TPS54240-Q1
www.ti.com
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
DETAILED DESCRIPTION (continued)
Figure 30. Operation of SS/TR Pin when Starting
Overload Recovery Circuit
The TPS54240-Q1 has an overload recovery (OLR) circuit. The OLR circuit will slow start the output from the
overload voltage to the nominal regulation voltage once the fault condition is removed. The OLR circuit will
discharge the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pull down of
382μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is
removed, the output will slow start from the fault voltage to nominal output voltage.
Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins. The sequential method can be implemented using an open drain output of a power on reset pin of another
device. The sequential method is illustrated in Figure 31 using two TPS54240-Q1 devices. The power good is
coupled to the EN pin on the TPS54240-Q1 which will enable the second power supply once the primary supply
reaches regulation. If needed, a 1nF ceramic capacitor on the EN pin of the second power supply will provide a
1ms start up delay. Figure 32 shows the results of Figure 31.
Copyright ©20102011, Texas Instruments Incorporated 17
SS /TR
TPS54240
EN
PWRGD
SS /TR
EN PWRGD
EN1
PWRGD1
VOUT1
VOUT2
EN1,EN2
VOUT1
VOUT2
EN
TPS54160
3
SS/TR
4
PWRGD6
EN
TPS54160
3
SS/TR
4
PWRGD6
TPS54240
TPS54240
TPS54240-Q1
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
www.ti.com
DETAILED DESCRIPTION (continued)
Figure 31. Schematic for Sequential Start-Up Figure 32. Sequential Startup using EN and
Sequence PWRGD
Figure 33. Schematic for Ratiometric Start-Up Figure 34. Ratio-Metric Startup Using Coupled
Using Coupled SS/TR Pins SS/TR pins
Figure 33 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The
regulator outputs will ramp up and reach regulation at the same time. When calculating the slow start time the
pull up current source must be doubled in Equation 6.Figure 34 shows the results of Figure 33.
18 Copyright ©20102011, Texas Instruments Incorporated
SS/TR
TPS54240
EN
PWRGD
SS/ TR
EN
PWRGD
VOUT 1
VOUT 2
R1
R2
R3
R4
TPS54240
Vout2 + deltaV Vssoffset
R1 = VREF Iss
´
VREF R1
R2 = Vout2 + deltaV VREF
´
-
deltaV = Vout1 Vout2-
R1 > 2800 Vout1 180 deltaV´ - ´
TPS54240-Q1
www.ti.com
SLVSAQ4A DECEMBER 2010REVISED APRIL 2011
DETAILED DESCRIPTION (continued)
Figure 35. Schematic for Ratiometric and Simultaneous Start-Up Sequence
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 35 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 7 and Equation 8, the tracking resistors can be calculated to initiate the Vout2
slightly before, after or at the same time as Vout1. Equation 9 is the voltage difference between Vout1 and Vout2
at the 95% of nominal output regulation.
The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to
VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and
tracking resistors, the Vssoffset and Iss are included as variables in the equations.
To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2
reaches regulation, use a negative number in Equation 7 through Equation 9 for deltaV. Equation 9 will result in a
positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved.
Since the SS/TR pin must be pulled below 40mV before starting after an EN, UVLO or thermal shutdown fault,
careful selection of the tracking resistors is needed to ensure the device will restart after a fault. Make sure the
calculated R1 value from Equation 7 is greater than the value calculated in Equation 10 to ensure the device can
recover from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger
as the slow start circuits gradually handoff the<