PRELIMINARY MX98727BEC 3.3V SINGLE-CHIP 10/100 Mbps ETHERNET CARDBUS CONTROLLER Feature Cardbus Features 10/100 M Ethernet Interface * Compliant to CardBus specification of PC Card Standard 6.1 * Bus master architecture with linked host buffers delivers world class performance * 32-bit bus master DMA channel provides ultra low CPU utilization * Support CardBus Card Information Structure (CIS) body stored in a 4k-bit Serial EEPROM or Flash ROM. * Support CardBus unlimit burst, read line, read multiple, write and invalidate commands * Support CardBus clock control through CLKRUNB pin * Support CardBus CSTSCHG pin and Status Changed registers * Fully comply to IEEE 802.3 and ANSI 8802-3 Ethernet standards * Operates over 100 meters of STP and category 5 UTP cable * Support full duplex operation in both 100 Base-TX and 10 Base-T modes * Support 802.3x "Frame Based Flow Control" scheme in full duplex mode * Support network and communication device class OnNow requirements for Microsoft's PC99 specifications, including all wake-up events: 1. Magic PacketTM 2. Wake-up Frames 3. Link Change 4. Modem Phone Ring * Support 10 Mb/s and 100 Mb/s NWAY auto negotiation function * Support a variety of flexible address filtering modes with 16 CAM addresses and 64 bits hash * Support up to 5 LED output for various network activity indications * Support TX traffic prioritization for QoS feature * Support 802.1Q tagged frames Other Features * Large on chip FIFOs for both transmit and receive operations without external local memory * Support up to 128K bytes boot ROM interface * MicroWire interface to Serial EEPROM containing Subsystem ID, Card Information Structure (CIS) pointer, Ethernet address and so on * 3.3V operating power , 128-pin LQFP package with standard CMOS technology * Support dual Function Cardbus for 10/100 Mb/s Ethernet and Modem interface * Support early interrupt for transmit and receive Modem Interface ( Magic PacketTM Technology is a trademark of Advanced Micro Device Corp. ) * Provides an interface to a wide range of modem chipsets available in the market General Description The MX98727BEC, single chip 10/100M fast Ethernet controller, is designed to interface directly with 3.3V CardBus bus and 10/100 Base-T Fast Ethernet network without external transceiver. The MX98727BEC implements all Media Access Control (MAC) layer functions for transmission, reception, NWAY auto-negociation and 10/100M transceivers in accordance with the IEEE 802.3/802.3u standard. High speed CardBus master interface is implemented to support 100Mb/s fast Ethernet with fast packet buffer management. On chip control registers and CardBus configuration registers provide interface to host system for automatic bus master configuration and driver controls. As a CardBus bus master, MX98727BEC incorporates large on chip FIFOs which provides effective local packet buffers, therefore no external local buffer memory is needed. Full duplex and half duplex are both supported for different applications. A packet buffer is located in the host memory that is used by software driver for all incoming and outgoing packets. This buffer area is shared by both transmit process and receive process. During reception, the MX98727BEC stores packets in the receive buffer area, then indicates receive status and control information in the descriptor area. P/N:PM0669 REV. 0.1, AUG. 07, 2000 1 MX98727BEC Furthermore, advanced power management not only save electric energy but also network maintenance efficiency through the application of Wake-On-LAN and Remote-Power-On. This packet buffer is also used by transmit process which can transmit multiple packets from a single transmit command. Minimum-sized back-to-back packets at full line speed with interframe gap ( IPG ) of 0.96us in 100 BaseTX mode is effortless with MX98727BEC. RTX RTX2EQ GNDA TXOP TXON VDDA GNDA GNDR VDDR RXIP RXIN VDDR GNDR VDDA GNDA XO XI/CKREF VDDA RDA GNDA VDDA FOEB(LED3) BPA16(LED2) BPA15(LED1) BPA14(LED0) BPA13(LED4) GND VDD BPA12(MDMSPKEN) BPA11(MDMRSTB) BPA10(MDMRDB) BPA9(MDMADR3) FCSB(MDMCSB) FWEB(MDMWRB) BPA8(MDMDTA6) BPA7(MDMDTA5) BPA6(MDMDTA4) BPA5(MDMDTA3) 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 2.0 Pin Configuration VDDA 103 GNDA 104 VDDR 105 GNDR 106 CLKRUNB 107 NC 108 CSTSCHG 109 PMEB 110 INTAB 111 RSTB 112 CBCLK 113 GNTB 114 REQB 115 AD31 116 AD30 117 GND 118 AD29 119 AD28 120 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 AD20 VDD AD19 AD18 GND AD17 AD16 CBEB2 FRAMEB GND IRDYB TRDYB DEVSELB STOPB VDD PERRB SERRB PAR CBEB1 AD15 GND AD14 AD13 VDD AD12 AD11 AD10 GND AD9 AD8 CBEB0 AD7 128 6 127 AD21 AD24 CBEB3 5 126 GND GND 4 125 AD22 AD25 3 124 AD23 AD26 2 GND 123 1 122 GND 121 GND VDD AD27 MX98727BEC 64 BPA4(MDMDTA2) 63 BPA3(MDMDTA1) 62 BPA2(MDMDTA0) 61 BPA1(EEDI)(MDMADR2) 60 BPA0(EECK)(MDMADR1) 59 EECS 58 BPD0(EED0) 57 BPD1(MDMADR0) 56 BPD2(MDMPWRDN) 55 BPD3(MDMDTA7) 54 BPD4(MDMINT) 53 BPD5(MDMRING) 52 BPD6(MDMWAITB) 51 BPD7(MDMADR4) 50 GND 49 VDD 48 AD0 47 AD1 46 GND 45 AD2 44 AD3 43 VDD 42 AD4 41 AD5 40 GND 39 AD6 REV. 0.1, AUG. 07, 2000 P/N:PM0669 2 MX98727BEC 3.0.1 Pin Description T/S: tri-state, S/T/S : Sustained tri-state, I : input, O :output, O/D : open drain) PIN NAME AD[31:0] TYPE T/S CBEB[3:0] T/S PIN NO. 116,117,119, 120,122,124 125, 127, 3, 4, 6,7,9,10, 12,13,26,28, 29,31,32,33, 35,36,38,39 41,42,44,45, 47,48 128,14,25,37 FRAMEB S/T/S 15 TRDYB S/T/S 18 IRDYB S/T/S 18 DEVSELB S/T/S 19 CBCLK RSTB INTAB SERRB I I O/D O/D 113 112 111 23 PERRB S/T/S 22 DESCRIPTION CardBus address/data bus: shared CardBus address/data bus lines. Little or big endian byte ordering are supported. CardBus command and byte enable bus: shared CardBus command and byte enable bus, during the address phase of the transaction, these four bits provide the bus command. During the data phase, these four bits provide the byte enable. CardBus FRAME# signal: shared CardBus cycle start signal, asserted to indicate the beginning of a bus transaction. As long as FRAMEB is asserted, data transfers continue. CardBus Target ready: issued by the target agent, a data phase is completed on the rising edge of CBCLK when both IRDYB and TRDYB are asserted. CardBus Master ready: indicates the bus master's ability to complete the current data phase of the transaction. A data phase is completed on any rising edge of CBCLK when both IRDYB and TRDYB are asserted. CardBus slave device select: asserted by the target of the current bus access. When 98727BEC is the initiator of current bus access, the target must assert DEVSELB within 5 bus cycles, otherwise cycle is aborted. CardBus clock input: CardBus clock range from 16MHZ up to 33MHZ. CardBus reset: host system hardware reset. CardBus interrupt request signal: wired to INTA# line. CardBus system error signal: If an address parity error is detected and CFCS bit 8 is enabled, SERR# and CFCS's bit 30 will be asserted. CardBus data error signal: As a bus master, when a data parity error is detected and CFCS bit 8 is enabled, PERR# and CFCS bit 24 and CSR5 bit 13 will be asserted. As a bus target, a data parity error cause PERR# to be asserted. REV. 0.1, AUG. 07, 2000 P/N:PM0669 3 MX98727BEC PIN NAME PAR TYPE T/S PIN NO. 24 STOPB S/T/S 20 REQB GNTB T/S I 115 114 PMEB O/D 110 CSTSCHG CLKRUNB O I/O 109 107 FCSB/ MDMCSB O 70 EECS BPA0/EECK MDMADR1 O O 59 60 BPA1/EEDI MDMADR2 O 61 DESCRIPTION CardBus parity bit: shared CardBus bus even parity bit for 32 bits AD bus and CBE bus. CardBus Target requested transfer stop signal: as bus master, assertion of STOPB cause MX98727BEC either to retry, disconnect, or abort. CardBus request signal: to initiate a bus master cycle request. CardBus grant acknowledge signal: host asserts to inform MX98727BEC that access to the bus is granted Power Management event: Asserted low to wake up host system when the follow condition are met: (1) PMC<8> is set or both EVENTMR<14> and EVENTMR<4> are set. (2) The power state is not in D0. (3) One of the wake-up events occurred. Including a. A magic packet is received. b. A wake-up frame is received. c. Link speed change. d. MDMRING is asserted. Status Change pin CardBus clock run: indicates the CardBus clock status. When normal operation, the host system asserts the signal low. It is deasserted by the host system when the clock is going to be slowed down to another operational frequency. The MX98727BEC samples the signal. When it is found deasserted,the MX98727BEC asserts CLKRUNB, requesting normal clock operation to be maintained. BPCSB(MDMEN=0): Boot ROM or external latch chip select MDMCSB(MDMEN=1): Modem chip select. MDMEN is bit 0 of Func1_HW options in serial ROM, which is auto loaded during booting up. Serial ROM chip select. MDMEN=0: Boot ROM address line 0. MX98727BEC supports up to 32 KB boot ROM or serial PROM EECK pin MDMEN=1: Modem address line 1. Address lines that are not needed should be left unconnected. MDMEN=0: Boot ROM address line 1. MX98727BEC supports up to 32 KB boot ROM or serial PROM EEDI pin. MDMEN=1: Modem address line 2. Address lines that are not needed should be left unconnected. REV. 0.1, AUG. 07, 2000 P/N:PM0669 4 MX98727BEC PIN NAME BPA2/ MDMDTA0 TYPE O PIN NO. 62 BPA3/ MDMDTA1 O 63 BPA4/ MDMDTA2 O 64 BPA5/ MDMDTA3 O 65 BPA6/ MDMDTA4 O 66 BPA7/ MDMDTA5 O 67 BPA8/ MDMDTA6 O 68 BPA9/ MDMADR3 I/O 71 BPA10/ MDMRDB BPA11/ MDMRSTB I/O 72 O 73 BPA12/ MDMSPKEN O 74 DESCRIPTION MDMEN=0:Boot ROM address line 2. MX98727BEC supportsup to 32 KB boot ROM. MDMEN=1:Modem data line 0. MDMEN=0:Boot ROM address line 3. MX98727BEC supportsup to 32 KB boot ROM. MDMEN=1:Modem data line 1. MDMEN=0:Boot ROM address line 4. MX98727BEC supportsup to 32 KB boot ROM. MDMEN=1:Modem data line 2. MDMEN=0: Boot ROM address line 5. MX98727BEC supportsup to 32 KB boot ROM. MDMEN=1: Modem data line 3. MDMEN=0:Boot ROM address line 6. MX98727BEC supportsup to 32 KB boot ROM. MDMEN=1:Modem data line 4. MDMEN=0 : Boot ROM address line 7. MX98727BEC supportsup to 32 KB boot ROM. MDMEN=1: Modem data line 5. MDMEN=0 : Boot ROM address line 8. MX98727BEC supportsup to 32 KB boot ROM. MDMEN=1: Modem data line 6. MDMEN=0 : Boot ROM address 9/Serial ROM output data pin. MDMEN=1: Modem address line 3. Address lines that are not needed should be left unconnected. MDMEN=0 : Boot ROM address line10/Serial ROM input data pin. MDMEN=1 : Modem read line. This pin is active low. MDMEN=0 : Boot ROM address line 11/Serial ROM clock pin. MDMEN=1 : Modem reset. This pin is active low upon hardware reset. MDMEN=0 : Boot ROM address line12. MDMEN=1 : Modem speaker enable. This pin reflects the audio enable bits of the modem function Status Changed Registers. If Func1_HwOptions<7> bit in the Serial ROM is set, the value of the Function Event Mask Register<6> is driven on the MDMSPKEN pin. If Func1_HwOptions<7> is cleared, the value of Function Event Mask Register<5> is driven on this pin. REV. 0.1, AUG. 07, 2000 P/N:PM0669 5 MX98727BEC PIN NAME BPA13/ LED4 BPA14/ LED0 BPA15/ LED1 BPA16/ LED2 FOEB/ LED3 BPD0/EEDO BPD1/ MDMADR0 TYPE O PIN NO. 77 DESCRIPTION Boot ROM address line13 or LED4 pin. O 78 Boot ROM address line 14 or LED0 pin. O 79 Boot ROM address line 15 or LED1pin O 80 Boot ROM address line 16 or LED2 pin. O 81 Flash/Boot PROM Output Enable pin or LED3 pin O O 58 57 BPD2/ MDMPWRDN O 56 BPD3/ MDMDTA7 BPD4/ MDMINT O 55 I/O 54 BPD5/ MDMRING I/O 53 BPD6/ MDMWAITB I/O 52 Boot ROM data line 0 or Serial ROM EEDO pin. MDMEN=0 : Boot ROM data line 1. MDMEN=1 : Modem address line 0. Address lines that are not needed should be left unconnected. MDMEN=0 : Boot ROM data line 2. MDMEN=1 : Modem power down. This pin is asserted when the MX98727BEC is in D3 power state. It can be used by the modem chipset power control. The polarity of this pin is determined by the Func1_HwOption<5> bit is the Serial ROM. MDMEN=0 : Boot ROM data line 3. MDMEN=1 : Modem data line 7. MDMEN=0 : Boot ROM data line 4. MDMEN=1: Modem interrupt line . When asserted, MX98727BEC asserts the INTAB pin. This pin is active high. MDMEN=0 : Boot ROM data line 5. MDMEN=1: Modem ring indicator. The assertion of this pin in power down mode(D1, D2, D3) will assert PMEB to wake up the host. MDMEN=0 : Boot ROM data line 6. MDMEN=1: Modem wait pin. This pin's functionality is determined by the Func1_HwOption<3> bit in the serial ROM. When Func1_HwOption<3> is set, the modem can insert wait state in modem chipset read and write transactions. In this mode, MX98727BEC ignores this pin before starting the transactions and examine its value only during the transaction. When Func1_HwOption<3> is cleared, MX98727BEC examines the pin after modem reset and won't start any transactions to the modem chipsets before this pin is deasserted. This pin is active low . It is internally pulled up and can be left unconnected. BPD7/ MDMADR4 O 51 MDMEN=0 : Boot ROM data line 7. MDMEN=1: Modem address line 4. Address lines that are not needed should be left unconnected. REV. 0.1, AUG. 07, 2000 P/N:PM0669 6 MX98727BEC PIN NAME RTX RTX2EQ RXIP RXIN RDA TXOP TYPE O O I I O O PIN NO. 102 101 93 92 84 99 TXON O 98 XI/CKREF XO VDDA I O I GNDA I VDDR GNDR VDD I I I GND I 86 87 82,85,89, 97,103, 83,88, 96,100,104, 91,94,105 90,95,106 8,21,30, 43,49,75,121 1,2,5,11, 16,27,34,40, 46,50,76,118, 123,126 DESCRIPTION Connecting an external 1K ohm resistor to ground Test Pin Twisted pair receive differential input for 100BaseT Twitsed pair receive differential input for 100BaseT Connecting an external 10K ohm resistor to ground Twisted pair transmit differential output: Support both 10 BaseT and 100 Base-TX transmit differential output Twisted pair transmit differential output: Support both 10 BaseT and 100 Base-TX transmit differential output Reference clock: 25MHZ oscillator clock input or crystal input 25Mhz Crystal output pin Analog power pins. Analog Ground pins. RX analog Vdd RX analog ground Power for Core logic Ground for Core logic REV. 0.1, AUG. 07, 2000 P/N:PM0669 7 MX98727BEC 4. PROGRAMMING INTERFACE 4.1 NIC CARDBUS CONFIGURATION REGISTERS (Function 0 ) : 4.1.1 NIC CARDBUS ID REGISTER ( CBID ) ( Offset 03h-00h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Device ID (bit 31:16) Vendor ID (bit 15:0) This register can be loaded from external serial EEPROM or use a MXIC preset value of "10D9" and "0532" for vendor ID and device ID respectively. Word location 3Eh and 3Dh in serial EEPROM are used to configure customer's vendor ID and device ID respectively. If location 3Eh contains"FFFF" value then MXIC's vendor ID and device ID will be set in this register, otherwise both 3Eh and 3Dh will be loaded into this register from serial EEPROM. 4.1.2 NIC CARDBUS COMMAND AND STATUS REGISTER ( CBCS ) ( Offset 07h-04h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Detect Parity Error Signal System Error Receive Master Abort Receive Target Abort Deceive Select Timing Data Parity Report Fast Back-to-back New Capability System Error Enable Parity Error Response Master Operation Memory Space Access IO Space Access The bit content will be reset to 0 when a 1 is written to the corresponding bit location. bit 0 : IO Space Access, set to 1 enable IO access bit 1 : Memory Space Access, set to 1 to enable memory access bit 2 : Master Operation, set to 1 to support bus master mode bit 5-3 : not used bit 6 : Parity Error Response, set to 1 to enable assertion of CSR<13> bit if parity error detected. bit 7 : not used bit 8 : System Error Enable, set to 1 to enable SERRB when parity error is detected on address lines and CBEB[3:0]. bit 20 : New capability. Set to support CARDBUS power management. bit 22,bit21,bit19 : not used bit 23 : Fast Back-to back, always set to accept fast back-to-back transactions that are not sent to the same bus device. REV. 0.1, AUG. 07, 2000 P/N:PM0669 8 MX98727BEC bit 24:Data Parity Report, is set to 1 only if PERRB active and PFCS<6> is also set. bit 26-25:Device Select Timing of DEVSELB pin. bit 27:not used bit 28:Receive Target Abort, is set to indicate a transaction is terminated by a target abort. bit 29:Receive Master Abort, is set to indicate a master transaction with Master abort. bit 30:Signal System Error, is set to indicate assertion of SERRB. bit 31:Detected Parity Error, is set whenever a parity error detected regardless of PFCS<6>. 4.1.3 NIC CARDBUS REVISION REGISTER ( CBRV ) ( Offset 0Bh-08h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 5 4 3 2 4 3 1 0 Base Class Subclass Revision Number Step Number bit 3 - 0 : Step Number, range from 0 to Fh. bit 7 - 4 : Revision Number, fixed to 7h for MX98727BEC bit 15 - 8 : not used bit 23 - 16 : Subclass, fixed to 0h. bit 31 - 24 : Base Class, fixed to 2h. 4.1.4 NIC CARDBUS LATENCY TIMER REGISTER ( CBLT ) (Offset 0Fh-0Ch) PFLT Register (0Fh-0Ch) 6 5 2 1 0 Configuration Latency Timer System cache line size bit 0 - bit 7 : System cache line size in units of 32 bit word, device driver should use this value to program CSR0<15:14>. bit 8 - bit 15 : Configuration Latency Timer, when MX98727BEC assert FRAMEB, it enables its latency timer to count. If MX98727BEC desserts FRAMEB prior to timer expiration, then timer is ignored. Otherwise, after timer expires, MX98727BEC initiates transaction termination as soon as its GNTB is deserted. 4.1.5 NIC CARDBUS BASE IO ADDRESS REGISTER ( CBIO ) ( Offset 13h-10h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Configuration Base IO Address IO/Memory Spec Indicator bit 0 : IO/Memory Space Indicator, fixed to 1 in this field will map into the IO space. This is a read only field. bit 7 - 1 : not used, all 0 when read bit 31 - 8 : Defines the address assignment mapping of MX98727BEC CSR registers. REV. 0.1, AUG. 07, 2000 P/N:PM0669 9 MX98727BEC 4.1.6 NIC CARDBUS Base Memory Address Register ( CBMA ) ( Offset 17h-14h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Configuration Base Memory Address Memory Spec Indicator bit 0 : Memory Space Indicator, fixed to 0 in this field will map into the memory space. This is a read only field. bit 7 - 1 : not used, all 0 when read bit 31 - 7 : Defines the address assignment mapping of MX98727BEC CSR registers. 4.1.7 NIC CardBus Card Information Structure (CBCIS) ( Offset 2Bh-28h ) CBCIS Register( 28h-2Bh ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ROM Image Address Space Offset Address Space Indicator bit 31 - bit 28: ROM Image. The 4-bit ROM image field value when the CBCIS resides in an expansion ROM. bit 27 - bit 3: Address Space Offset. The field conatins the address offset which is loaded from EEPROM within the address space indicator field (CBCIS<2:0>). bit 2 - bit 0: Address Space Indicator. The field indicates the location of the CBCIS base address When the value is 7, the content of CIS is stored in the expansion ROM. Ohterwise, if the value is 2, the CIS content is stored in the serial ROM. The register is read only. It is loaded from the serial ROM after a hardware reset. 4.1.8 NIC CARDBUS SUBSYSTEM ID REGISTER ( CBSID ) ( Offset 2Fh-2Ch ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Subsystem device ID (31:16) Subsystem Vendor ID (bit 15:0) This register is used to uniquely identify the add-on board or subsystem where the NIC controller resides. Values in this register are loaded directly from external serial EEPROM after system reset automatically. Word location 00h of EEPROM is subsystem vendor ID and location 01h is subsystem device ID. REV. 0.1, AUG. 07, 2000 P/N:PM0669 10 MX98727BEC 4.1.9 NIC CARDBUS BASE EXPANSION ROM ADDRESS REGISTER ( CBROM ) ( Offset 33h-30h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Expansion ROM Base Address (upper 21 bit) Address Decode Enable bit 0 : Address Decode Enable, decoding will be enabled if only both enable bit in PFCS<1> and this expansion ROM register are 1. bit 16 - 1 : not use bit 31 - 17 : Defines the upper 21 bits of expansion ROM base address. 4.1.10 NIC CARDBUS CAPABILITY POINTER REGISTER ( CBCP ) ( Offset 37h-34h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Capability Pointer (Set to 44h) bit 7- 0 : Capability pointer (Cap_Ptr) is set to 44h. bit 31- 8 : reserved 4.1.11 NIC CARDBUS INTERRUPT REGISTER ( CBIT ) ( Offset 3Fh-3Ch ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 9 8 7 6 5 4 3 2 1 0 0 Max_Lat Min-Gnt Interrupt Pin Interrupt Line bit 7 - 0 : Interrupt Line, system BIOS will writes the routing information into this field, driver can use this information to determine priority and interrupt vector. bit 15 - 8 : Interrupt Pin, fixed to 01h which use INTA#. bit 31 - 24 : Max_Lat which is a maximum period for a access to CARDBUS bus. bit 23 - 16 : Min_Gnt which is the maximum period that MX98727BEC needs to finish a burst CARDBUS cycle. REV. 0.1, AUG. 07, 2000 P/N:PM0669 11 MX98727BEC 4.1.12 NIC CARDBUS DRIVER AREA REGISTER ( CBDA ) ( 43h-40h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 0 0 Board Type Driver Special Use bit 29 : board type bit 15 - 8 : driver is free to read and write this field for any purpose. bit 7 - 0 : not used. 4.1.13 NIC CARDBUS POWER MANAGEMENT CAPABILITY REGISTER ( CPMC ) ( 47h-44h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 7 6 5 4 3 2 0 PME_Support D2_Support D1_Support AUX_I DSI Auxiliary Power Source PME Clock Version Next Pointer Capability ID bit 31- 27 : PME_Support, read only indicates the power states in which the function may assert LANWAKE pin. bit 31 ---- PME_D3cold (value depending on Vaux / FCSB pin ) bit 30 ---- PME_D3hot bit 29 ---- PME_D2 bit 28 ---- PME_D1 bit 27 ---- PME_D0 bit 26 : D2 mode support, read only, set to 1. bit 25 : D1 mode support, read only, set to 1. bit 24-22 : AUX_I bits. Auxiliary current field, set to 000. bit 21 : DSI, read only, reset to 0. bit 20 : Auxiliary power source, supporting D3cold, set to 1. This bit is valid only when bit 31 is a '1'. bit 19 : PME Clock, read only, reset to 0. bit 18-16 : CARDBUS power management version1.1, set to 010, read only. bit 15-8 : Next Pointer, all bits reset to 0. bit 7-0 : Capability ID, read only, set to 1 indicates support of power management REV. 0.1, AUG. 07, 2000 P/N:PM0669 12 MX98727BEC 4.1.14 NIC CARDBUS POWER MANAGEMENT COMMAND AND STATUS REGISTER ( PMCSR ) ( 4Bh-48h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 0 0 0 0 0 0 1 0 Data Bridge Extension Support PME_Status Data_Scale Data_Select PME_EN Reserved Power State bit 1-0 : Power_State, read/write, D0 mode is 00, D1 mode is 01, D2 mode is 10, D3 hot mode is 11. bit7-2 : all 0. Reserved. bit8 : PME_EN, set 1 to enable PMEB and LANWAKE pins. Set 0 to disable PMEB and LANWAKE assertion. bit 12-9 : Data_Select for report in the Data register located at bit 31:24. Not supported, reset to 0. bit 14-13 : Data_Scale, read only, not supported, reset to 0. bit 15 : PME_Status independent of the state of PME_EN. Cleared during power up. When set, indicates a PME event. Write 1 to clear the PMEB and LANWAKE assertion, PME-Status become 0. Write 0, no effect. bit 21-16 : Reserved. bit 22 : B2_B3# = 0, BPCC_EN = 1, read only, not support. bit 23 : BPCC_EN = 0, Bus Power/Clock Control Enable, read only, not support. bit 31-24 : Data = 0, read only, not support. REV. 0.1, AUG. 07, 2000 P/N:PM0669 13 MX98727BEC 5.1 Modem Function Configuration Registers (Function 1) 5.1.1 Modem CardBus ID Register(CBID) CBID Register ( 0103h-0100h) bit 31-16 :Device ID. Provide the unique ID number. bit 15-0 :Vendor ID. Specifies the manufacture of the MX98727BEC. These two IDs must be loaded from external serial ROM. No default values are implemented in MX98727BEC. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 9 8 4 3 2 1 0 Device ID (bit 31:16) Vendor ID (bit 15:0) 5.1.2 Modem CardBus Command and Status Register (CBCS) CBCS Register ( 0107h-0104h) The bit content will be reset to 0 when a 1 is written to the corresponding bit location. bit 0 : IO Space Access, set to 1 to enable IO access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 7 6 5 4 3 2 1 0 Detected Parity Error Signal System Error Device Select Timing Data Parity Report Fast Back-to-back System Error Enable Parity Error Response Master Operation Memory Space Access IO Space Access bit 1: Memory Space Access, set to 1 to enable memory access bit 2: Master Operation, Tied to 0 and no master capability is provided in modem function. bit 3- bit 5 :not used bit 6: Parity Error Response, set to 1 to enable assertion of MX98727BEC's CSR5<13> bit if parity error detected. bit 7 : not used bit 8: System Error Enable, set to 1 to enable MX98727BEC to assert SERRB when parity error is detected on address lines and CBEB[3:0] . bit 22 - bit 9: not used bit 23 : Fast Back-to-back, always set by MX98727BEC to accept fast back-to-back transactions that are not sent to the same bus device. bit 24 : Data Parity Report, is set to 1 by MX98727BEC only if MX98727BEC is bus master, it sends or causes PERRB active and CBCS<6> is also set. bit 26 -25 : Device Select Timing, fixed at 01 which indicates a medium assertion of DEVSELB. bit 27- 29 : not used. bit 30 : Signal System Error, is set to indicate MX98727BEC asserted SERRB. bit 31 : Detected Parity Error, is set whenever a parity error detected regardless of CBCS<6>. REV. 0.1, AUG. 07, 2000 P/N:PM0669 14 MX98727BEC 5.1.3 Modem CardBus Revision Register (CBRV) CBRV Register ( 010Bh-0108h) bit 7 - bit 0 : Revision Number, Fix to 0/h. bit 15 - bit 8 : not used bit 23 - bit 16 : Subclass, auto loaded from serial ROM. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 8 7 6 5 4 4 3 2 1 1 0 0 Base Class Subclass Revision Number bit 31 - bit 24 : Base Class, fixed to 07/h. 5.1.4 Modem CardBus Latency Timer Register(CBLT) CBLT Register ( 010Fh-010Ch) bit 0 - bit 7 : System cache line size Not accessable in modem function. bit 8 - bit 15 : Configuration Latency Timer, Not accessible in modem function. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 3 2 Configuration Latency Timer System cache line size <Note> Cache line size and latency timer are only useful in master, so modem function doesn't allow to access these two fields. REV. 0.1, AUG. 07, 2000 P/N:PM0669 15 MX98727BEC 5.1.5 Modem CardBus I/O Address Register(CBIO) CBIO Register ( 0113h-0110h) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Configuration Base IO Address IO/Memory Space Indicator bit 0 : IO/Memory Space Indicator, fixed to 1 in this field will map into the IO space. This is a read only field. bit 4 - 1 : not used, all 0 when read bit 31- 5 : Defines the base address mapping to modem registers. 5.1.6 Modem CardBus Memory Address Register(CBMEM) CBMEM Register ( 0117h-0114h) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 Configuration Base IO Address Memory Space Indicator bit 0 : Memory Space Indicator, fixed to 0 in this field will map into the memory space. This is a read only field bit 6 - bit 1 : not used, all 0 when read bit 31 - bit 10 : Define the base address mapping to modem registers, and status changed registers. 5.1.7 Modem CardBus Card Information Structure(CBCIS) CBCIS Register( 012Bh-0128h ) It is read only and is loaded from serial ROM after a hardware reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ROM Image Address Space Offset Address Space Indicator REV. 0.1, AUG. 07, 2000 P/N:PM0669 16 MX98727BEC 5.1.8 Modem CardBus Subsystem ID Register(CBSID) CBSID Register ( 012Fh-012Ch) bit 15-0 :Subsystem ID. The value of this field is read from the serial ROM. bit 31-16 Subsystem Vendor ID. The value of this field is read from the serial ROM. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Subsystem ID Subsystem Vendor ID 5.1.9. Modem CardBus Base Expansion ROM Address Register(CBROM) CBROM Register ( 0133h- 0130h) bit 0 : Address Decode Enable, It is tied to 0, indicating expansion ROM is not supported in modem function. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Decode Enable 5.1.10 Modem CardBus Interrupt Register(CBIT) CBIT Register ( 013Fh - 013Ch) bit 7 - bit 0 : Interrupt Line, system BIOS will writes the routing information into this field, driver can use this information to determine priority and interrupt vector. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 1 1 1 0 0 0 0 0 0 0 1 0 9 8 7 6 5 4 3 2 1 0 0 Max_Lat Min-Gnt Interrupt Pin Interrupt Line bit 15 - bit 8 : Interrupt Pin, fixed to 01h which use INTAB. bit 23 - bit 16 : Min_Gnt which is the maximum period that MX98727BEC needs to finish a burst CardBus cycle. The value is 08h. bit 31 - bit 24 : Max_Lat which is a maximum of every 17us for a access to PCI bus. The value is 38h. REV. 0.1, AUG. 07, 2000 P/N:PM0669 17 MX98727BEC 5.2 HOST INTERFACE REGISTERS MX98727BEC CSRs are located in the host I/O or memory address space. The CSRs are double word aligned and 32 bits long. Definitions and address for all CSRs are as follows : CSR Mapping Register Meaning Offset from CSR Base Address ( CBIO and CBMA ) CSR0 Bus mode 00 CSR1 Transmit poll demand 08h CSR2 Receive poll demand 10h CSR3 Receive list base address 18h CSR4 Transmit list base address 20h CSR5 Interrupt status 28h CSR6 Operation mode 30h CSR7 Interrupt enable 38h CSR8 Missed frame counter 40h CSR9 Serial ROM and MII management 48h CSR10 Flash Memory Address Register 50h CSR11 General Purpose timer 58h CSR12 10 Base-T status port 60h CSR13 SIA Reset Register 68h CSR14 10 Base-T control port 70h CSR15 Watchdog timer 78h CSR16 ( Reserved ) Test Operation port 80h CSR17 ( Reserved ) IC Test Port-1 88h CSR18 ( Reserved ) IC Test Port-2 90h CSR19 ( Reserved ) IC test Port-3 98h CSR20 Auto compensation A0h CSR21 Flow control Register A4h CSR22 MAC ID Byte 3-0 A8h CSR23 Magic ID 5, 4 / MAC ID Byte 5, 4 ACh CSR24 Magic ID Byte 3-0 B0h CSR25 Filter 0 Byte Mask B4h CSR26 Filter 1 Byte Mask B8h CSR27 Filter 2 Byte Mask BCh CSR28 Filter 3 Byte mask C0h CRS29 Filter Offset C4h CSR30 Filter 1&0 CRC-16 C8h CSR31 Filter 3&2 CRC-16 CCh REV. 0.1, AUG. 07, 2000 P/N:PM0669 18 MX98727BEC CSR32 Reserved A Register 1 D0h CSR33 Reserved A Register 2 D4h CSR34 Reserved A Register 3 D8h CSR35 Reserved A Register 4 DCh CSR36 Reserved A Register 5 E0h CSR37 Reserved P Register E4h CSR38 Power Management Register E8h CSR39 VLAN Tag Register ECh CSR40 Function Event Register F0h CSR41 Function Event Mask Register F4h CSR42 Function Present State Register F8h CSR43 Function Force Event Register FCh REV. 0.1, AUG. 07, 2000 P/N:PM0669 19 MX98727BEC 5.2.1 BUS MODE REGISTER ( CSR0 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WIE-Write and Invalidate Enable RLE-Read Line Enable RME-Read Multiple Enable TAP-Transmit Automatic Polling BAR2 CAL-Cache Alignment PBL-Programmable Burst Length BLE-Big/Little Endian DSL-Descriptor Skip Length BAR0-Bus Arbitration bit 0 SWR-Software Reset Field 0 Name SWR 1 BAR0 6:2 DSL 7 BLE 13:8 PBL 15:14 CAL 16 BAR2 18:17 TAP 21 RME 23 RLE 24 WIE Description Software Reset, when set, MX98727BEC resets all internal hardware with the exception of the configuration area and port selection. Internal bus arbitration scheme between receive and transmit processes. The receive channel usually has higher priority over transmit channel when receive FIFO is partially full to a threshold. This threshold can be selected by programming this bit. Set for lower threshold, reset for normal threshold. Descriptor Skip Length, specifies the number of longwords to skip between two descriptors. Big/Little Ending, set for big ending byte ordering mode, reset for little ending byte ordering mode, this option only applies to data buffers Programmable Burst Length, specifies the maximum number of longwords to be transferred in one DMA transaction. default is 0 which means unlimited burst length, possible values can be 1,2,4,8,16,32 and unlimited . Cache Alignment, programmable address boundaries of data burst stop, MX98727BEC can handle non-cache- aligned fragment as well as cache-aligned fragment efficiently. Reset to use RX dominate arbitration. Set to use TX dominant arbitration in fast forward mode or round Robin in store/forward mode. Must be reset to zero for normal operation. Transmit Auto-Polling time interval, defines the time interval for MX98727BEC to performs transmit poll command automatically at transmit suspended state. CARDBUS Memory Read Multiple command enable, indicates bus master may intend to fetch more than one cache lines disconnecting. CARDBUS Memory Read Line command enable, indicating bus master intends to fetch a complete cache line. CARDBUS Memory Write and Invalidate command enable, guarantees a minimum transfer of one complete cache. REV. 0.1, AUG. 07, 2000 P/N:PM0669 20 MX98727BEC TABLE 5.2.0 TRANSMIT AUTO POLLING BITS CSR<18:17> Time Interval 00 No transmit auto-polling, a write to CSR1 is required to poll 01 auto-poll every 200 us 10 auto-poll every 800 us 11 auto-poll every 1.6 ms 5.2.2 TRANSMIT POLL COMMAND ( CSR1 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Transmit Poll command Field 31:0 Name TPC Description Write only, when written with any value, MX98727BEC read transmit descriptor list in host memory pointed by CSR4 and processes the list. 5.2.3 RECEIVE POLL COMMAND ( CSR2 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Receive Poll command Field 31:0 Name RPC Description Write only, when written with any value, MX98727BEC read receive descriptor list in host memory pointed by CSR3 and processes the list. REV. 0.1, AUG. 07, 2000 P/N:PM0669 21 MX98727BEC 5.2.4 DESCRIPTOR LIST ADDRESS ( CSR3, CSR4 ) CSR3 Receive List Base Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Start of Receive List Address CSR4 Transmit List Base Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Start of Transmit List Address REV. 0.1, AUG. 07, 2000 P/N:PM0669 22 MX98727BEC 5.2.5 INTERRUPT STATUS REGISTER ( CSR5 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKUPI-Wake Up event Interrupt LC-Link Change EB-Error Bits TS-Transmit Process State RS-Receive Process State NIS-Normal Interrupt Summary AIS-Abnormal Interrupt Summary ERI-Early Receive Interrupt FBE-Fatal Bus Error LF-Link Fail GTE-General Purpose Timer Expired ETI-Early Transmit Interrupt RWT-Receive Watchdog Timeout RPS-Receive Process Stopped RU-Receive Buffer Unavailable RI-Receive Interrupt UNF-Transmit Underflow LPANCI-Link Pass/Autonegotiation Completed Interrupt TJT-Transmit Jabber Timeout TU-Transmit Buffer Unavailable TPS-Transmit Process Stopped TI-Transmit Interrupt Field 28 27 Name WKUPI LC 25:23 22:20 19:17 16 EB TS RS NIS 15 AIS 14 ERI 13 FBE 12 LF Description Wake Up event interrupt. Set if wake-up event occurs in power-down mode. 100 Base-TX link status has changed either from pass to fail or fail to pass. Read CSR12<1> for 100 Base-TX link status. Error Bits, read only, indicating the type of error that caused fatal bus error. Transmit Process State, read only bits indicating the state of transmit process. Receive Process State, read only bits indicating the state of receive process. Normal Interrupt Summary, is the logical OR of CSR5<0>, CSR5<2> and CSR5<6> and CSR5<14>, CSR5<28>. Abnormal Interrupt Summary, is the logical OR of CSR5<1>, CSR5<3>, CSR5<4>, CSR5<5>,CSR5<7>, CSR5<8>, CSR5<9>, CAR5<10>, CSR5<11>, CSR5<12> and CSR5<13>, CSR5<27>. Early receive interrupt, indicating the first buffer has been filled in ring mode, or 64 bytes has been received in chain mode. Fatal Bus Error, indicating a system error occurred, MX98727BEC will disable all bus access. Link Fail, indicates a link fail state in 10 Base-T port. This bit is valid only when CSR6<18>=0, CSR14<8>=1. REV. 0.1, AUG. 07, 2000 P/N:PM0669 23 MX98727BEC Field 11 10 Name GTE ETI 9 RWT 8 7 RPS RU 6 5 RI UNF 4 LPANCI 3 TJT 2 TU 1 0 TPS TI Description General Purpose Timer Expired, indicating CSR11 counter has expired. Early Transmit Interrupt, indicating the packet to be transmitted was fully transferred to internal TX FIFO. CSR5<0> will automatically clears this bit. Receive Watchdog Time-out, reflects the network line status where receive watchdog timer has expired while the other node is still active on the network. Asserts when the receive process enters the stop state. Receive Buffer Unavailable, the receive process is suspended due to the next descriptor in the receive list is owned by host. If no receive poll command is issued, the reception process resumes when the next recognized incoming frame is received. Receive Interrupt, indicating the completion of a frame reception. Transmit Underflow, indicating transmit FIFO has run empty before the completion of a packet transmission. When autonegotiation is not enabled ( CSR14<7>=0 ), this bit indicates that the 10 Base-T link integrity test has completed successfully, after the link was down. This bit is also set as as a result of writing 0 to CSR14<12> ( Link Test Enable ). When Autonegotiation is enabled ( CSR14<7> =1 ) , this bit indicates that the autonegotiation has completed ( CSR12<14:12>=5 ). CSR12 should then be read for a link status report. This bit is only valid when CSR6<18>=0, i.e. 10 Base-T port is selected Link Fail interrupt ( CSR5<12> ) will automatically clears this bit. Transmit Jabber Timeout, indicating the MX98727BEC has been excessively active. The transmit process is aborted and placed in the stopped state. TDES0<14> is also set. Transmit Buffer Unavailable, transmit process is suspended due to the next descriptor in the transmit list is owned by host. Transmit Process Stopped. Transmit Interrupt. indicating a frame transmission was completed. REV. 0.1, AUG. 07, 2000 P/N:PM0669 24 MX98727BEC TABLE 5.2.1 FATAL BUS ERROR BITS CSR5<25:23> 000 001 010 011 1XX Process State parity error for either SERR# or PERR#, cleared by software reset. master abort target abort reserved reserved TABLE 5.2.2 TRANSMIT PROCESS STATE CSR5<22:20> 000 001 010 011 100 101 110 111 Process State Stopped- reset or transmit jabber expired. Fetching transmit descriptor Waiting for end of transmission filling transmit FIFO reserved Setup packet Suspended, either FIFO underflow or unavailable transmit descriptor closing transmit descriptor TABLE 5.2.3 RECEIVE PROCESS STATE CSR5<19:17> 000 010 011 100 101 110 111 Process State Stopped- reset or stop receive command. Fetching receive descriptor checking for end of receive packet Waiting for receive packet Suspended, receive buffer unavailable closing receive descriptor Purging the current frame from the receive FIFO due to unavailable receive buffer queuing the receive frame from the receive FIFO into host receive buffer REV. 0.1, AUG. 07, 2000 P/N:PM0669 25 MX98727BEC 5.2.6 OPERATION MODE REGISTER ( CSR6 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCR-Scrambler Mode PCS-PCS function TTM-Transmit Threshold Mode SF-Store and Forward HBD-Hearbeat Disable PS-Port Select COE-Collision Offset Enable TR-Threshold Control Bits ST-Start/Stop Transmission Command FC-Force collision mode LOM-Loopback Operation Mode FD-Full Duplex Mode FKD PM-Pass All Multicast PR-Promiscuous Mode SB-Start/Stop Backoff Counter IF-Inverse Filtering PB-Pass Bad Frame HO-Hash-Only Filtering Mode SR-Start/Stop Receive HP-Hash/Perfect Receive Filtering Mode Field 24 Name SCR 23 PCS 22 21 TTM SF 19 18 HBD PS 17 COE 15:14 TR Description Scrambler Mode, default is set to enable scrambler function. Not affected by software reset. Default is set to enable PCS functions. CSR6<18> must be set in order to operate in symbol mode. Transmit Threshold Mode, set for 10 Base-T and reset for 100 Base-TX. Store and Forward, when set, transmission starts only if a full packet is in transmit FIFO. the threshold values defined in CSR6<15:14> are ignored Heartbeat Disable, set to disable SQE function in 10 Base-T mode. Port Select, default is 0 which is 10 Base-T mode, set for 100 Base-TX mode. A software reset does not affect this bit. Collision Offset Enable, set to enable a modified backoff algorithm during low collision situation, reset for normal backoff algorithm. Threshold Control Bits, these bits controls the selected threshold level for MX98727BEC's transmit FIFO, transmission starts when frame size within the transmit FIFO is larger than the selected threshold. Full frames with a length less than the threshold are also transmitted. REV. 0.1, AUG. 07, 2000 P/N:PM0669 26 MX98727BEC Field 13 Name ST 12 FC 11:10 9 LOM FD 8 7 FKD PM 6 PR 5 SB 4 IF 3 PB 2 HO 1 SR 0 HP Description Start/Stop Transmission Command, set to place transmission process in running state and will try to transmit current descriptor in transmit list. When reset, transmit process is placed in stop state. Force Collision Mode, used in collision logic test in internal loopback mode, set to force collision during next transmission attempt. This can result in excessive collision reported in TDES0<8> if 16 or more collision. Loopback Operation Mode, see table 5.2.6. Full-Duplex Mode, set for simultaneous transmit and receive operation, heart beat check is disabled, TDES0<7> should be ignored, and internal loopback is not allowed. This bit controls the value of bit 6 of link code word . Reserved for internal test for back off speeding up Pass All Multicast, set to accept all incoming frames with a multicast destination address are received. Incoming frames with physical address are filtered according to the CSR6<0> bit. Promiscuous Mode, any incoming valid frames are accepted, default is reset and not affected by software reset. Start/Stop Backoff Counter, when reset, the backoff timer is not affected by the network carrier activity. Otherwise, timer will start counting when carrier drops. Inverse Filtering, read only bit, set to operate in inverse filtering mode, only valid during perfect filtering mode. Pass Bad Frames, set to pass bad frame mode, all incoming frames passed the address filtering are accepted including runt frames, collided fragments, truncated frames caused by FIFO overflow. Hash-Only Filtering Mode , read only bit, set to operate in imperfect filtering mode for both physical and multicast addresses. Start/Stop Receive, set to place receive process in running state where descriptor acquisition is attempted from current position in the receive list. Reset to place the receive process in stop state. Hash/Perfect Receive Filtering Mode, read only bit, set to use hash table to filter multicast incoming frames. If CSR6<2> is also set, then the physical addresses are imperfect address filtered too. If CSR6<2> is reset, then physical addresses are perfect address filtered, according to a single physical address as specified in setup frame. REV. 0.1, AUG. 07, 2000 P/N:PM0669 27 MX98727BEC TABLE 5.2.4 TRANSMIT THRESHOLD CSR6<21> CSR6<15:14> 0 0 0 0 1 00 01 10 11 XX CSR6<22>=0 (for 100 Base-TX) 128 256 512 1024 ( Store and Forward ) CSR6<22>=1 (Threshold bytes) (for 10 Base-T) 72 96 128 160 TABLE 5.2.5 DATA PORT SELECTION CSR14<7> 1 0 0 CSR6<18> 0 0 1 CSR6<22> X 1 0 CSR6<23> X X 1 CSR6<24> X X 1 Port Nway Auto-negotiation 10 Base-T 100 Base-TX TABLE 5.2.6 LOOPBACK OPERATION MODE CSR6<11:10> 00 01 11 10 Operation Mode Normal Internal loopback at FIFO port Internal loopback at the PHY level External loopback at the PMD level TABLE 5.2.7 FILTERING MODE CSR6<7> PM 0 0 CSR6<6> PR 0 0 CSR6<4> IF 0 0 CSR6<2> HO 0 0 CSR6<0> HP 0 1 0 0 X 1 0 0 1 0 0 1 X X 1 X X X 1 0 X X Filtering Mode CAM 16-entry perfect filtering 64-bit hash (mulitcast=1) + 1perfect (entry 0) filtering. (multicast=0) 64-bit hash for multicast Inverse filtering. Only valid with CSR6<0>=0 Promiscuous (Pass all kind) Pass All Multicast REV. 0.1, AUG. 07, 2000 P/N:PM0669 28 MX98727BEC 5.2.7 INTERRUPT MASK REGISTER ( CSR7 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WKUPIE-Wake Up event interrupt Enable LCE-Link Changed Enable NIE-Normal interrupt Summary Enable AIE-Abnormal Interrupt Summary Enable ERIE-Early Receive Interrupt Enable FBE-Fatal Bus Error Enable LFE-Link Fail Enable GPTE-General-Purpose Timer Enable ETIE-Early Transmit Interrupt Enable RWE-Receive Watchdog Enable RSE-Receive Stopped Enable RUE-Receive Buffer Unavailable Enable RIE-Receive Interrupt Enable UNE-Underflow Interrupt Enable LPANCIE-Link Pass /Nway Complete Interrupt Enable TJE-Transmit Jabber Timeout Enable TUE-Transmit Buffer Unavailable Enable TSE-Transmit Stopped Enable TIE-Transmit Interrupt Enable Field 28 27 16 Name WKUPIE LCE NIE 15 AIE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERIE FBE LFE GPTE ETIE RWE RSE RUE RIE UNE LPANCIE TJE TUE TSE TIE Description Wake Up Event Interrupt Enable, enables CSR5<28>. Link Changed Enable, enables CSR5<27>. Normal Interrupt Summary Enable, set to enable CSR5<0>, CSR5<2>, CSR5<6>, CSR5<14>, CSR5<28> Abnormal Interrupt Summary enable, set to enable CSR5<1>, CSR5<3>, CSR5<4>, CSR5<5>, CSR5<7>, CSR5<8>, CSR5<9>, CSR5<11>, CSR5<12> CSR5<13>, AND CSR5<27> Early Receive Interrupt Enable Fatal Bus Error Enable, set together with with CSR7<15> enables CSR5<13>. Link Fail Interrupt Enable, enables CSR5<12> General Purpose Timer Enable, set together with CSR7<15> enables CSR5<11>. Early Transmit Interrupt Enable, enables CSR5<10> Receive Watchdog Timeout Enable, set together with CSR7<15> enables CSR5<9>. Receive Stopped Enable, set together with CSR7<15> enables CSR5<8>. Receive Buffer Unavailable Enable, set together with CSR7<15> enables CSR5<7>. Receive Interrupt Enable, set together with CSR7<16> enables CSR5<6>. Underflow Interrupt Enable, set together with CSR7<15> enables CSR5<5>. Link Pass/Autonegotiation Completed Interrupt Enable Transmit Jabber Timeout Enable, set together with CSR7<15> enables CSR5<3>. Transmit Buffer Unavailable Enable, set together with CSR7<16> enables CSR5<2>. Transmit Stop Enable, set together with CSR7<15> enables CSR5<1>. Transmit Interrupt Enable, set together with CSR7<16> enables CSR5<0>. REV. 0.1, AUG. 07, 2000 P/N:PM0669 29 MX98727BEC 5.2.8 MISSED FRAME COUNTER ( CSR8 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Missed Frame Overflow Missed Frame Counter Field 16 Name MFO 15:0 MFC Description Missed Frame Overflow, set when missed frame counter overflows, reset when CSR8 is read. Missed Frame Counter, indicates the number of frames discarded because no host receive descriptors were available. 5.2.9 NONVOLATILE MEMORY CONTROL REGISTER ( CSR9 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LED3SEL LED2SEL LED1SEL LED0SEL WKFCAT LED4SEL RD-Read Operation Reload BR-Boot ROM Select SR-Serial ROM Select Data-Boot ROM data or Serial ROM control Field 31 30 29 28 24 Name Description LED3SEL 0:Default value. Set LED3 as RX LED. 1:Set LED3 as F/H duplex LED. LED2SEL 0: Default value. Set LED2 as SPEED LED. 1: Set LED2 as 100 Good LinkLED LED1SEL 0:Default value. Set LED1 as Good Link LED. 1: Set LED1 as Link/Activity LED. LED0SEL 0:Default value. Set LED0 as Activity LED. 1: Set LED0 as Link Speed (10/100) LED. LED4SEL 0: Default value. Set LED4 as PMEB LED. 1: Set LED4 as 10 Good Link LED. REV. 0.1, AUG. 07, 2000 P/N:PM0669 30 MX98727BEC Field 26:25 14 13 12 11 7:0 3 2 1 0 Name Description WKFACT Wake up frame catenation option bits. CRS21<4> CSR<26> CSR<25> Wake up event 0 X X CH0+CH1+CH2+CH3 1 0 0 (CH0*CH1)+(CH2*CH3) 1 0 1 (CH0*CH1)+CH2+CH3 1 1 0 (CH0*CH1*CH2)+CH3 1 1 1 CH0*CH1*CH2*CH3 RD Boot ROM/EEPROM read operation select bit WR EEPROM reload operation select bit. Operation definition: RD WR Operation 1 0 Boot ROM/EEPROM Read 0 1 Boot ROM/EEPROM write 1 1 EEPROM reload operation ( bit 11, SR=1) BR Boot ROM Select, set to select boot ROM only if CSR9<11>=0. SR Serial ROM Select, set to select serial ROM for either read or write operation. Data If boot ROM is selected ( CSR9<12> is set ), this field contains the data to be read from and written to the boot ROM. If serial ROM is selected , CSR9<3:0> are defined as follows : SDO Serial ROM data out from serial ROM into MX98727BEC. SDI Serial ROM data input to serial ROM from MX98727BEC. SCLK Serial clock output to serial ROM. SCS Chip select output to serial ROM. Notice : CSR9<11> and CSR9<12> should be mutually exclusive for correct operations. LED DISPLAY Option Summary Table LED0SEL LED1SEL LED2SEL LED3SEL LED4SEL* 0 ACT LINK SPEED RX PMEB 1 SPEED LINK/ACT 100 LINK FULL/HALF 10 LINK REV. 0.1, AUG. 07, 2000 P/N:PM0669 31 MX98727BEC 5.2.10 FLASH MEMORY PROGRAMMING ADDRESS REGISTER ( CSR10 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 3 2 2 1 0 MA Field 16:0 Name MA Description Flash Memory Address : Address bit 16 to 0. GENERAL PURPOSE TIMER ( CSR11 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 1 0 CON-Continuous Mode Timer Value Field 16 Name CON 15:0 Timer Description When set, the general purpose timer is in continuous operating mode. When reset, the timer is in one-shot mode. Value contains the timer value in a cycle time of 204.8us. REV. 0.1, AUG. 07, 2000 P/N:PM0669 32 MX98727BEC 5.2.11 10 BASE-T STATUS Port ( CSR12 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LPC-Link Partner's Link Code Word LPN-Link Partner Negotiable ANS-Autonegotiation Arbitration State TRF-Transmit Remote Fault APS-Autopolarity State LS10B-Link Status of 10 Base-T LS100B-Link Status of 100 Base-TX *Software reset has no effect on this register Field 31:16 Name LPC 15 LPN 14:12 ANS 11 3 TRF APS 2 LS10B 1 LS100B Description Link Partner's Link Code Word, where bit 16 is S0 ( selector field bit 0 ) and bit31 is NP ( Next Page ). Effective only when CSR12<15> is read as a logical 1. Link Partner Negotiable, set when link partner support NWAY algorithm and CSR14<7> is set. Autonegotiation Arbitration State, arbitration states are defined 000 = Autonegotiation disable 001 = Transmit disable 010 = ability detect 011 = Acknowledge detect 100 = Complete acknowledge detect 101 = FLP link good; autonegotiation complete 110 = Link check When autonegotiation is completed, an ANC interrupt ( CSR5<4>) is generated, write 001 into this field can restart the autonegotiation sequence if CSR14<7> is set. Otherwise, these bits should be 0. Transmit Remote Fault Autopolarity State, set when polarity is positive. When reset, the 10 Base-T polarity is negative. The received bit stream is inverted by the receiver. Set when link status of 10 Base-T port link test fail. Reset when 10 Base-T link test is in pass state. Link state of 100 Base-TX, this bit reflects the state of SD pin, effective only when CSR6<23>= 1 ( PCS is set ). Set to indicate a fail condition .i.e. SD=0. REV. 0.1, AUG. 07, 2000 P/N:PM0669 33 MX98727BEC 5.2.12 VLAN & HomeLAN Register (CSR13) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HPNA2EN Htxrise Hlinkb HPNA1EN VLANEN VLAN TX S/H VLAN RX S/H Nway ResetNway and 10 Base-T PHY level reset Field 11 10 9 8 7 6 Name HPNA2EN Htxrise Hlinkb HPNA1EN VLANEN VLAN TX S/H 5 VLAN RX S/H 0 Nway Reset Description Home PNA 2.0 MII Interface Enable, default=0 Reset to send signal in rising edge, set to send signal in falling edge, default=0. Home PNA Link status, low is good link, high is bad link, default=0. Home PNA 1.0 7-wire interface Enable, default=0. Set to enable VLAN function, reset to disable VLAN function, default=0. While VLANEN=1, reset this bit for software VLAN TX function, set this bit for hardware VLAN TX function, default=0. While VLANEN=1, reset this bit for software VLAN RX function, set this bit for hardware VLAN RX function, default=0. While writing 0 to this bit, resets the CSR12 & CSR14, default=0. 5.2.13 10 Base-T Control PORT (CSR14) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAUSE-Pause (link code word) T4-100 Base-T4 (link code word) TXF-100 Base-TX full duplex (link code word) TXH-100 Base-TX half duplex (link code word) LTE-Link Test Enable RSO-Receive Squelch Enable ANE-Autonegotiation Enable HDE-Half Duplex Enable) LBK-Loopback (MCC) *The software reset bit (bit0 of CSR0) has no effect to this register. REV. 0.1, AUG. 07, 2000 P/N:PM0669 34 MX98727BEC Field 19 18 17 16 Name PAUSE T4 TXF TXH 12 8 7 6 LTE RSQ ANE HDE 1 LBK Description Bit 10 of link code word for 100 Base-TX pause mode. Bit 9 of link code word for T4 mode. (allways 0 after reset) Bit 8 of link code word for 100 Base-TX full duplex mode. Bit 7 of link code word for 100 Base-TX half duplex mode. Meaningful only when CSR14<7> ( ANE ) is set. Link Test Enable, when set the 10 Base-T port link test function is enabled. Receive Squelch Enable for 10 Base-T port. Set to enable. Autonegotiation Enable, . Half-Duplex Enable, this is the bit 5 of link code word, only meaningful when CSR14<7> is set. Loop back enable for 10 Base-T MCC. 5.2.14 WATCHDOG TIMER ( CSR15) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBZ-Must Be Zero RWR-Receive Watchdog Release PWD-Receive Watchdog Disable JCK-Jabber Clock HUJ-Host Unjabber JAB-Jabber Disable Field 8 5 Name FJT RWR 4 RWD 2 JCK 1 HUJ 0 JBD Description Internal test for jabber timer. Must be zero. Default = 0 Defines the time interval no carrier from receive watchdog expiration until re-enabling the receive channel. When set, the receive watchdog is release 40-48 bit times from the last carrier desertion. When reset, the receive watchdog is released 16 to 24 bit times from the last carrier desertion. When set, the receive watchdog counter is disable. When reset, receive carriers longer than 2560 bytes are guaranteed to cause the watchdog counter to time out. Packets shorter than 2048 bytes are guaranteed to pass. When set, transmission is cut off after a range of 2048 bytes to 2560 bytes is transmitted, When reset, transmission for the 10 Base-T port is cut off after a range of 26 ms to 33ms. When reset, transmission for the 100 Base-TX port is cut off after a range of 2.6ms to 3.3ms. Defines the time interval between transmit jabber expiration until reenabling of the transmit channel. When set, the transmit channel is released immediately after the jabber expiration. When reset, the jabber is released 365ms to 420 ms after jabber expiration for 10 Base-T port. When reset, the jabber is released 36.5ms to 42ms after the jabber explo ration for 100 Base-TX port. Jabber Disable, set to disable transmit jabber function. REV. 0.1, AUG. 07, 2000 P/N:PM0669 35 MX98727BEC 5.2.15 NWAY Status Internal test Register (CSR20) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAUSE 100TXF 100TXH 10TXF 10TXH 100GLT LOCKT SYCM1INT RESERVED RXSIZE1 RESERVED BAR1 TXSIZE1 TXSIZE0 RXSIZE0 SELIDLE Field 31 30 Name PAUSE 100TXF 29 100TXH 28 10TXF 27 10TXH 26 25 24 19 17 16 15 100GLT LOCKT SYNM1INT RESERVED RXSIZE1 RESERVED BAR1 14 13 11 10 TXSIZE1 TXSIZE0 RXSIZE0 SELIDLE 8:0 RBCNT Description Flow Control PAUSE mode is accepted, read only. 100 base-T full duplex mode selection indication : After NWAY autonegotiation , a 1 in this bit indicate the IC has settled down in this mode. Otherwise 0. 100 base-T half duplex mode selection indication : After NWAY autonegotiation , a 1 in this bit indicate the IC has settled down in this mode. Otherwise 0. 10 base-T full duplex mode selection indication : After NWAY autonegotiation , a 1 in this bit indicate the IC has settled down in this mode. Otherwise 0. 10 base-T half duplex mode selection indication : After NWAY autonegotiation , a 1 in this bit indicate the IC has settled down in this mode. Otherwise 0. 100 TX NWAY good link test speed option, set for fast, reset for normal. Descrambler lock speed test, set for fast, reset for normal Sync. modem function 1 Interrupt Fixed to 1 by chip Must be 0 for normal operation Default is 0. RX FIFO arbitration option control bit 1, together with CSR0<1> BAR0 define a internal RX almost full threshold, definition as followed BAR0 BAR1 RX Near full threshold 0 0 1K bytes 0 1 256 1 0 512 1 1 128 Device driver can determine these values to reduce over-flow error rate, option 00 is least likely to have overflow but would reduce TX performance, while option 11 is near round-robin type of arbitration Must be zero for normal operation Must be zero for normal operation Must be zero for normal operation Set for 200-250 ns idle pulse width detection, reset for 175-225 ns idle pulse detection Default is 0. RX DMA Byte Count for driver's early interrupt assertion control REV. 0.1, AUG. 07, 2000 P/N:PM0669 36 MX98727BEC 5.2.16 Flow Control Register (CSR21) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMVAL-Flow Control timer Value TEST-Test Flow Counter Timer RESTART-Set Reset Mode RESTOP-Set Restop Mode TXFCEN-Transmit Flow Control Enable RXFCEN-Receive Flow Control RUFCEN-Receive Flow Control Enable while Receive Descriptor is Unavailable STOPTX-Indicate the transmit is stoped REJECTFC-Abort the Receive Flow Control Frame FCTH1-Flow Control Thresold 1 FCTH0-Flow Control Thresold 0 NFCEN-NWAY Flow Control WKFCATEN-Wake up Frame Catenation Enable LNKCHGDIS - Link change indication disable MPHITDIS - magic packet hit disable FSTEE Field 31:16 15 14 Name TMVAL TEST RESTART 13 RESTOP 12 11 10 TXFCEN RXFCEN RUFCEN 9 STOPTX 8 7 6 5 4 REJECTFC RXFCTH1 RXFCTH0 NFCEN WKFCATEN 3 LNKCHGDIS 2 1 MPHITDIS FSTEE Description Timer value in the flow control frame for receive flow control. Test the flow control timer. Set the receive flow control into the restart mode, the RXFCEN should be asserted. The default value is 0. Set the receive flow control into the restop mode, the RXFCEN should be asserted. The default value is 0. Transmit flow control enable. The default value is 1. Receive flow control enable. The default value is 0. Send flow control frame control when the receive descriptor is unavailable, the RXFCEN should be asserted. The default value is 0. Indicate the transmit status. If the receive flow control stop the transmission, this bit is set. After recovering transmission, this bit is clear. Abort the receive flow control frame when set. The default value is 1. Receive flow control threshold 1. Default = 0 Receive flow control threshold 0. Default = 1 Accept flow control from the auto-negotiation result. Default = 1 Enable the wake up frame concatenation feature. loadable from EEPROM offset 77h bit 3, See CSR9 for details Set to disable link change detection in power down mode, loadable from EEPROM offset 77h bit 1 Set to disable magic packet address matching, loadable from EEPROM offset 77h bit 0 Set to speed up EEPROM clk for test, reset for normal EEPROM clock. Receive Flow Control Threshold Table FCTH1 1 FCTH0 1 Threshold Value (Byte) 512 1 0 256 0 1 128 0 0 overflow REV. 0.1, AUG. 07, 2000 P/N:PM0669 37 MX98727BEC 5.2.17 MAC ID Byte 3-0 Register (CSR22) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 MAC ID byte 2 MAC ID byte 3 MAC ID byte 0 MAC ID byte 1 5.2.18 Magic ID Byte 5,4/ MAC ID Byte 5,4 (CSR23) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Magic ID byte 4 Magic ID byte 5 MAC ID byte 4 MAC ID byte 5 5.2.19 Magic ID Byte 3-0 (CSR24) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Magic ID byte 2 Magic ID byte 3 Magic ID byte 0 Magic ID byte 1 5.2.20 Filter 0 Byte Mask Register 0 (CSR25) Filter 1 Byte Mask Register 1 (CSR26) Filter 2 Byte Mask Register 2 (CSR27) Filter 3 Byte Mask Register 3 (CSR28) CSR25 to CSR28 are Filter N ( N=0 to 3 ) Byte Mask Register N ( N=0 to 3 ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte Mask Field 31:0 Name Byte Mask Description If bit number j of the byte mask is set, byte number (offset+j) of the incoming frame is checked. REV. 0.1, AUG. 07, 2000 P/N:PM0669 38 MX98727BEC 5.2.21 Filter Offset Register (CSR29) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Filter 3 Enable Filter 3 Offset Filter 2 Enable Filter 2 Offset Filter 1 Enable Filter 1 Offset Filter 0 Enable Filter 0 Offset Field 6:0 Name Pattern 0 Offset 7 Filter 0 Enable 14:8 Pattern 1 Offset 15 Filter 1 Enable 22:16 Pattern 2 Offset 23 Filter 2 Enable 30:24 Pattern 3 Offset 31 Filter 3 Enable Description The offset defines the location of first byte that should be checked by filter 0 in the frame. Offset is always greater than 12. This bit is set to enable the filter 0. If it is reset, filter 0 is disabled for the wake-up frame checking. The offset defines the location of first byte that should be checked by filter 1 in the frame. Offset is always greater than 12. This bit is set to enable the filter 1. If it is reset, filter 1 is disabled for the wake-up frame checking. The offset defines the location of first byte that should be checked by Filter 2 in the frame. Offset is always greater than 12. This bit is set to enable the filter 2. If it is reset, filter 2 is disabled for the wake-up frame checking. The offset defines the location of first byte that should be checked by Filter 3 in the frame. Offset is always greater than 12. This bit is set to enable the filter 3. If it is reset, filter 3 is disabled for the wake-up frame checking. REV. 0.1, AUG. 07, 2000 P/N:PM0669 39 MX98727BEC 5.2.22 Filter 1 and 0 CRC-16 Register (CSR30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Filter 1 CRC-16 Filter 0 CRC-16 Field 15:0 Name Filter 0 CRC-16 31:0 Filter 1 CRC-16 Description The 16-bit CRC value is programmed by the driver to be matched against the current result from the CRC-16's remainder at the location specified by Filter 0 offset and Filter 0 Byte Mask register. if matched, the incoming frame is a wakeup frame. Same description as Filter 0 CRC-16. 5.2.23 Filter 3 and 2 CRC-16 Register (CSR31) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Filter 3 CRC-16 Filter 2 CRC-16 Field 15:0 31:0 Name Filter 2 CRC-16 Filter 3 CRC-16 Description Same description as Filter 0 CRC-16. Same description as Filter 0 CRC-16 REV. 0.1, AUG. 07, 2000 P/N:PM0669 40 MX98727BEC 5.2.24 PMDCTRL1 Register (CSR32) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 1 0 1 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 0 0 1 0 1 0 0 0 0 1 1 0 1 1 FULLSCAL15M FULLSCAL16M FULLSCAL17M PMDB40[1:0]M PMDB60[1:0]M PMDB100[1:0]M PMDB120[1:0]M PMDGS3[2:0] PMDGS2[2:0] PMDGS1[2:0] PMDB2[1:0] PMDGS4[2:0] PMDB3[2:1] PMDB5[2:0] PMDPZ[1:0] Field 20:18 17:15 14:12 11:10 Name PMDGS3 PMDGS2 PMDGS1 PMDB2 Description Read only bits Read only bits Read only bits Read only bits 5.2.25 PMDCTRL2 Register (CSR33) 1 1 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 0 1 2 1 0 PMDUG40[1:0]M PMDUG60[1:0]M PMDUG100[1:0]M PMDUG120[1:0]M MLDTHRE3[5:0] MLDTHRE2[5:0] MLDTHRE1[5:0] MLENGTH[5:0] Field Name Description 5:0 MLENGTH Read only bits REV. 0.1, AUG. 07, 2000 P/N:PM0669 41 MX98727BEC 5.2.26 PMDCTRL3 Register (CSR34) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 1 0 1 1 1 1 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 PMDUG40[1:0]M PMDUG60[1:0]M PMDUG100[1:0]M PMDUG120[1:0]M MGCTHRE2[5:0] MGCTHRE1[5:0] MVCPTHRE2[5:0] MVCPTHRE1[5:0] 5.2.27 PMDCTRL4 Register (CSR35) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 1 0 9 8 7 6 5 4 3 2 1 0 1 UGDFT[1:0]M TDFT[1:0]M PMDB[2:0]P PMDGS[2:0] PMDBP2:0] MGAINCAL[5:0] MNORMAL[5:0] MPLLVCP[5:0] Field 26:24 23:21 20:18 17:12 11:6 5:0 Name PMDB PMDGS PMDBP MGAINCAL MNORMAL MPLLVCP Description Read only bits Read only bits Read only bits Read only bits Read only bits Read only bits REV. 0.1, AUG. 07, 2000 P/N:PM0669 42 MX98727BEC 5.2.28 PMDCTRL5 Register (CSR36) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 0 1 1 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 3 2 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1 BLBYPS CHECK_DISBM PMDGS40[2:0]M PMDGS60[2:0]M PMDGS100[2:0]M PMDGS120[2:0]M SDIS1M SDIS2M SCH1M SCH2M FLAGM TRFM[3:1] VPPGM[6:1] R1_10 R1_100 SDBPSB AUTOCALB 5.2.29 PLLCTRL Register (CSR37) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 CTU10[5:0] CTD10[5:0] CTU100[5:0] CTD100[5:0] 5.2.31 VLan Tag Register (CSR38) VLan Tag Register 4 1 0 QTga User Priority CFI VID Field 31:16 Name QTag 15:13 12 11:0 Priority CFI VID Description 802.1QTag header which is used in insertion of VLan tag in TX packet,default value is 8100h. Qos priority bit, 000 to 111 Counonical format lndicator, default=0 VLan ID, default value is 0h. REV. 0.1, AUG. 07, 2000 P/N:PM0669 43 MX98727BEC 5.2.32 Power Management Register (CSR39) Power Management Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AUTOPM ENRXCLK ENTXCLK LDD100 LDD10 PD100 PD10 RST100B RST10B FORCEPM Field 0 Name FORCEPM 1 RST10B 2 RST100B 3 PD10 4 PD100 5 LDD10 6 LDD100 7 ENTXCLK 8 ENRXCLK 9 AUTOPM Description Default is 0 after host hardware reset, which means NWAY autonegotiation is enabled. Set this bit to 1 will enable manual controls ( bit 8 :1 ) over chip power saving features. Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM) is set to 1. When FORCEPM=1 and write 0 followed by write 1 to RST10B will reset 10 base-T analog module. Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM) is set to 1. When FORCEPM=1 and write 0 followed by write 1 to RST100B will reset 100 base-TX analog module. Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM) is set to 1. When FORCEPM=1 and write 1 to PD10 will power down 10 base-T analog module's core except the 10 base-T line drivers. Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM) is set to 1. When FORCEPM=1 and write 1 to PD100 will power down 100 base-TX analog module's core except the 100 base-TX line drivers. Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM) is set to 1. When FORCEPM=1 and write 1 to LDD10 will power down 10 base-TX analog module's line drivers. Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM) is set to 1. When FORCEPM=1 then write 1 in LD100 will power down 100 base-TX analog module's line drivers. Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM) is set to 1. When FORCEPM=1 then write 0 in ENTXCLK will stop TXC 25/2.5 MHz clock in the MAC core. Default is 0 after host hardware reset, this bit is meaningful only if bit 0 ( FORCEPM) is set to 1. When FORCEPM=1 then write 0 in ENRXCLK will stop RXC 25/2.5 MHz clock in the MAC core. Default is 0 after host hardware reset, which means NWAY autonegotiation is enabled. Set this bit high will enable automatic power saving mode which depends on the status of PCI configuration's D0 - D3cold bits and will result in different level of power saving. REV. 0.1, AUG. 07, 2000 P/N:PM0669 44 MX98727BEC 5.2.33 NIC CardBus Status Changed Registers 5.2.33.1 Function Event Register (CSR40) Read / Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt General Wake-up Event Field 15 Name Interrupt 4 GEW Description The bit is set when there is an interrupt pending. This bit is cleared by write 1. General Wake-up Event. This bit is set when the MX98727 has detected a power management event. The bit is cleared upon power-up reset and by writing 1. When the PMCSR<15>, PME status, in the CardBus configuration is cleared, the bit is automatically cleared as well. 5.2.33.2 Function Event Mask Register (CSR41) Read / Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt Register Enable Wake-up Event Summary Enable General Wake-up Event Enable Field 15 Name IRE 14 WESEN 4 GWEN Description Interrupt Register Enable. If set, enables the assertion of the interrupt pin when the wake up events occur. Wake-up Event Summary Enable. When set together with the SCR1<4>, GWEN, enables the asertion of the PMEB pin. To disable the assertion of this pin, the PMCSR<8>, PME Enable, must be cleared as well. General Wake-up Event Enable. When set together with the SCR1<14>, WESEN, enables the asertion of the PMEB pin. To disable the assertion of this pin, the PMCSR<8>, PME Enable, must be cleared as well. The bit is cleared upon power-up reset and by writing1. When the PMCSR<15>, PME status, in the CradBus configuration is cleared, the bit is automatically cleared as well. REV. 0.1, AUG. 07, 2000 P/N:PM0669 45 MX98727BEC 5.2.33.3 Function Present State Register (CSR42) Read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt General Wake-up Event Field 15 Name Interrupt 4 GEW Description The bit reflects the internal state of a function specific interrupt. It is cleared when the event that caused the interrupt was either masked in CSR7, or cleared in CSR5. Reflects the current state of the wake-up event. This bit is cleared when either SCR0<4>, GWE, is cleared or when PMCSR<15>, PME status, is cleared. 5.2.33.4 Function Force Event Register (CSR43) Read / Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Force Interrupt Force Wake-up Event Field 15 Name FINT 4 FWU Description Force Interrupt. Writing 1 to this bit sets the Interrupt field in SCR0<15>, but not in SCR<2>. Force Wake-up. Writing 1 to this bit sets the wake-up field in SCR0<4>, but not in SCR2<4>. REV. 0.1, AUG. 07, 2000 P/N:PM0669 46 MX98727BEC If D1, D2 or D3hot state is set, the PC is still turned on and is commonly called entering the Remote Wake-up mode. Otherwise if the main power on a PC is totally shut off, we call that it is in the D3cold state or Remote Power-On mode. To sustain the operation of the LAN card, a 3.3V standby power is required. Once the PC is turned on, MX98727BEC loads the Magic ID from EEPROM and set it up automatically. No registers is needed to be programmed. After then, simply turn of PC to enter D3cold state. In either Remote Wake-up mode or Remote Power-On mode. The transceiver and the RX block are still alive to monitor the network activity. If one of the three wake-up events occurred, the following status is changed: 5.3 ACPI Power Management Support The Advanced Configuration and Power Interface (ACPI) Specification defines a flexible and abstract hardware interface for a wide variety of PC systems to implement power and thernal management functions. This chip is fully compliant with the OnNow Network Device Class Power Management spec. rev.1.0, the CARDBUS power management interface spec. rev.1.1 and the ACPI spec. rev.1.0. Four power states defined for a CARDBUS function are: * D0-Fully On. The device is completely active and responsive. * D1-Light Sleep. Save a little power than D0 state. The CARDBUS clock is running. * D2-Deeper Sleep: Save more power than D1 state. The CARDBUS clock can be stopped. * D3hot-Deepest Sleep: Save more power than D2 state. The CARDBUS clock is stopped. * D3cold-Power Down: In this state, the main system power is removed from the chip but will preserve their PME context when transition from the D3cold to the D0 state. Such function requires an auxiliary power source other than main system power plane. 1. PPMCSR[15] (PME status) is set to 1. 2. CRS5[28] (WKUPI) is set to 1. 3. CARDBUS interrupt pin INTA# is asserted low. 4. PMEB pin is asserted low. 5. In MX98727BEC, CSTSCHG are also asserted. 5.3.1 Magic Packet The Magic Packet(TM) technology, proposed by AMD, is used to remotely wake up a sleeping or powered off PC on a network. This is accomplished by sending a specific packet, called Magic Packet, to a node on the network. When a NIC capable of recognizing the specific frame goes to sleep (entering D1, D2 or D3 state), it scans all incoming frames addressed to the node for a specific data sequence, which indicates to the controller that this is a Magic Packet frame. The specific sequence consists of 16 duplications of the IEEE address of this node, with no breaks or interruptions. This sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The synchronization stream is defined as 6 bytes of FFh. For example, if the IEEE address for a particular node on the network was 11h 22h 33h 44h 55h 66h, then the Magic Packet for this node would be: This chip also supports the OnNow Network Device Class Specification based on the ACPI specification defines the power management requirements of a network device. It defines the following wake-up events: * Reception of a Magic Packet. * Reception of a Network wake-up frame. * Detection of change in the network link state. DA SA MISC. FF FF FF FF FF FF 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 MISC. CRC. To put MX98727BEC into the sleep mode and enable the wake-up events detection are done as following: 1. Write 1 to PPMCSR[8] to enable power management feature. 2. Write the value to PPMCSR[1:0] to determine which power state to enter. REV. 0.1, AUG. 07, 2000 P/N:PM0669 47 MX98727BEC This chip can automatically loads the IEEE address into the internal registers from EEPROM while booting up. the magic packet detection scheme is not active while chip is in normal running state (D0). After entering into the sleep mode(D1, D2, D3) by host, the chip begins to scan the incoming packet but does not load the packet into RX FIFO. If a magic packet is detected, the PMEB is asserted to notify the host. The chip implements imperfect pattern matching by calculating a CRC-16 on all bytes of the received frame that where specified by the pattern's offset and the byte mask and comparing to a programmable pre-calculated CRC-16 remainder value. The CRC calculation uses the following polynomial: G(X)=X16 + X15 + X2 +1 The calculated CRC-16 value is compared with four possible CRC-16 values stored in CSR30 and CSR31. if the result matches any one and the enable bit of the corresponding filter also set, then we call a Wakeup frame received. Magic packet event occurs when the following conditions are approved: * The destination address of the received packet matches. * The PMEN bit (PPMCSR[8]) is set to 1. * Not in D0 state. * The magic packet pattern matches, i.e., 6*FFh + 16* Destination ID. Table1 shows the wake-up frame register block. This block is accessed through CSR registers mapping. <Note>: The CRC value is not checked during magic packet detection. Filter 0 Byte Mask Filter 1 Byte Mask Filter 2 Byte Mask Filter 3 Byte Mask Filter 3 Filter 2 Filter 1 Filter 0 Filter 1 CRC-16 Filter 0 CRC-16 Filter 3 CRC-16 Filter 2 CRC-16 5.3.2 Wake-up Frames A network wake-up frame is typically a frame that is sent by existing network protocols, such as ARP requests or IP frames addressed to the machine. Before putting the network adapter into the wake-up state, the system passes to the adapter's driver a list of sample frames and corresponding byte masks. Each sample frame is an example of a frame that should wake up the system. Each byte mask defines which bytes of the incoming frames should be compared with corresponding sample frame in order to determine whether or not to accept the incoming frame as a wake-up event. CSR25 CSR26 CSR27 CSR28 CSR29 CSR30 CSR31 The four filters can operate independently to match four 32-byte wake up frames. They also can be programmed to catenate each other to support longer wake up frames, ranging from 32 bytes up to 128 bytes. The following table shows the possible combination. The on-chip Wake-up logic provides four programmable filters that allow support of many different receive packet patterns. Specifically, these filters allow support of IP and IPX protocols which currently are the only protocols targeted to be power manageable. Each filter relates to 32 contiguous bytes in the incoming frame. When a frame is received from the network, the chip examines its content to determine whether the pattern matches to a wake-up frame. To know which byte of the frame should be checked, a programmable byte-mask and a programmable pattern offset are used for each one of the four supported filters. The pattern offset defines the location of the first byte in the frame that should be checked. Beginning with the pattern offset, if bit j in the byte mask is set, byte offset+j in the frame is checked. CSR21.4 CSR9.26 CSR9.25 Wake up event WKFCATEN WKFCAT1 WKFCAT0 0 X X CH0+CH1+CH2+CH3 1 0 0 (CH0*CH1)+(CH2*CH3) 1 0 1 (CH0*CH1)+CH2+CH3 1 1 0 (CH0*CH1*CH2)+CH3 1 1 1 CH0*CH1*CH2*CH3 If WAKCATEN (CSR21.4) is not set, the four filters are independent and simultaneous to match the incoming frame. When WKFCATEN is set, the catenation options are determined by WKFCAT<1:0> (CSR<26:25>). For example, if WKFCAT<1:0>=00, wake up event is occurred only if either both of channel 0 and channel 1 match or both of channel 2 and channel 3 match. If the REV. 0.1, AUG. 07, 2000 P/N:PM0669 48 MX98727BEC driver sets filter 0 and filter 1 be contiguous and also sets filter 2 and filter 3 be contiguous by adjusting the offsets, then two 64-byte wake up frames are supported. Another example is that if WKFCAT<1:0>=11 and the driver sets filter 0,1,2,3 as contiguous, a 128-byte wake up frame is supported. 6. Modem Interface: The MX98727BEC implements an interface for modem which enables connection of a non-CardBus modem chipsets to a CardBus system. It could integrate the LAN and Modem functions on a single Cardbus card, reducing the slot requirement and cost of a notebook PC. Wakeup Frames event occurs when following conditions are met: * Not in D0 state. * The destination address of the received wakeup frame matches. * No CRC-32 error is detected in the wakeup frame. * The PMEN bit (PPMCSR[8]) is set to 1. * The enable bit in the wakeup frame register block must be set. * The CRC value calculated from the bytes in the pre-designated locations equals to the respectively stored CRC-16 value. * If catenation must be met. enable bit WKFCATEN is set, the condition in table 2. The modem function is enabled when Func1_HwOption<0> bit in the serial ROM is set. While CardBus is accessing the modem, the MX98727BEC acts as a bus slave, translating the address and data, and issuing a read/write cycle to the modem chipsets. A read or write cycle to the modem could only access one modem register of 8 bit-wide. The MX98727BEC can support up to 32 modem registers. The possible value of registers which can be accessed is determined by PCI configuration register CBIO[4:3]. A write access to the modem chipset is executed as following and the timing waveform is shown in Figure 6.1. 5.3.3 Link Change 1. The host initiates a write cycle on the CardBus and writes the data to the MX98727BEC. 2. The MX98727BEC drives the address on the MDMADR[4:0] lines. 3. The MX98727BEC drives the data on the MDMDTA[7:0] lines. 4. The MX98727BEC asserts the MDMCSB line. 5. The MX98727BEC asserts the MDMWRB line. 6. The modem chipset may assert the MDMWAITB line to insert wait states. 7. The MX98727BEC deasserts the MDMWRB line. 8. The MX98727BEC deasserts the MDMCSB line.Tcss Link change wakeup event occurs when the following conditions are met: * Not in D0 state. * The PMEN bit (PMCSR[8]) is set to 1. * The cable is reconnected. The Remote Power-on (RPO) feature is a mechanism can be used to remotely power up a sleeping station. When the PC turned on, MX98727BEC loads the network ID from serial ROM automatically. Once the PC is turned off, MX98727BEC enters the RPO mode. MX98727BEC monitors the network for receipt of a wakeup packet. If a magic packet or wake up frame is received, it asserts PMEB, signal to wake up the system. After main power is on, PMEB is deserted by CARDBUS RSTB signal. After the deser tion, MX98727BEC can enter RPO mode again if the main power is switched off. REV. 0.1, AUG. 07, 2000 P/N:PM0669 49 MX98727BEC Tcss Tcsh MDMCSB w/wh MDMWRB Tads Tadh MDMADR[4:0] Tcsh Tdss MDMADR[4:0] Twd Twpw MDMWAITB Fig 6.2 Modern Write Access Timing Diagram 6.1 Modem write access timing diagram A read access to the modem chipset is executed as following and the timing diagram is shown in Figure 6.2. 5. The modem chipset may assert the MDMWAITB line to insert wait states. 6. The modem chipset drives the data on the MDMDTA[7:0]. 7. The MX98727BEC samples the data on the MDMDTA[7:0] lines. 8. The MX98727BEC deasserts the MDMRDB line. 9. The MX98727BEC deasserts the MDMCSB line. 1. The host initiates a read cycle on the CardBus. 2.The MX98727BEC drives the address on the MDMADR[4:0] lines. 3. The MX98727BEC asserts the MDMCSB line. 4. The MX98727BEC asserts the MDMRDB line. Tcss Tcsh MDMCSB R/Wh MDMWRB Tads Tadh MDMADR[4:0] Tdd Tdss MDMADR[7:0] Twd Twpw MDMWAITB Fig 6.2 Modern Read Access Timing Diagram REV. 0.1, AUG. 07, 2000 P/N:PM0669 50 MX98727BEC Table 6.1 shows the timing parameters for modem interface. Table 6.1 Modem Interface Timing Parameter Symbol Parameter Minimum Tcss Chip Select Set_up 60 Tads Address Set_up 80 Tadh Address Hold 60 W/Wh Write Pulse Width 160 R/Wh Read Pulse Width 160 Tdss Data Set_up 80 Tdh Data Hold 40 Tdd Data Delay Tcsh Chip Select Hold 40 d Wait Delay Twpw Wait Pulse Width 10Base-T Link Pulse Timing Symbol Parameter tip Time between Link Output Pulses tipw Link Integrity Output Pulse Width Maximum 90 120 240 Unit ns ns ns ns ns ns ns ns ns ns ns Min 8 80 Max 24 130 Units ms ns 6.2 Modem Function Address mapping The MX98727BEC modem function supports 8,16, or 32 byte-wide CSRs that can be mapped to either the I/O space through CBIO or to the memory space through CBMA. These CSRs are the modem chipset registers. In addition, the modem function can access the four CardBus Status Changed Registers which defined in NIC function through the memory space CSR40(SCR0), CSR41(SCR1), CSR42(SCR2), CSR43(SCR3), and shared by both modem function & NIC function. However, there are still three(CSR41, bit5~bit7) bits in Function Event Mask Register that are useful only in modem function. Here we just present this register all other 3 registers are the same as defined in NIC function. Function Event Mask Register(SCR1) Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt Register Enable Wake-up Event Summary Enable MINTE-Modem Interrupt Enable Pulse Width Modulation Enable Binary Audio Enable General Wake-up Event Enable REV. 0.1, AUG. 07, 2000 P/N:PM0669 51 MX98727BEC Field 15 Name IRE 14 WESEN 6 PWME* 7 MINTE 5 BAE* 4 GWEN Description Interrupt Register Enable. If set, enables the assertion of the interrupt pin when the wakeup events occur. Wake-up Event Summary Enable. When set together with the SCR1<4> ,GWEN, enables the assertion of the PMEB pin. To disable the assertion of this pin, Enable, must be cleared as well. Pulse Width Modulation Enable. If Func1_HwOption<7> is set, the Pulse Width Modulation Enable bit is driven on the MDMSPKEN pin. This bit is cleared upon hardware or software reset. Modem interrupt enable. If the bit is set, the interrupt from modem will issue INTAB pin. The default value is set. Binary Audio Enable. If Func1_HwOption<7> is cleared, the Binary Audio Enable bit is driven on the MDMSPKEN pin. This bit is cleared upon hardware or software reset. General Wake-up Event Enable. When set together with the SCR1<14> WESEN, enables the assertion of the PMEB pin. To disable the assertion of this pin, the PMCSR<8>, PME Enable, must be cleared as well. The bit is cleared upon power-up reset and by writing 1 When the PMCSR<15>, PME status, in the CardBus configuration is cleared , the bit is automatically cleared as well. * These two bits are accessible only in modem function. Figure 6.3 shows a I/O-based and a memory-based address map of the modem function. The offset addresses from A0h to 3FFh are reserved for both I/O and memory mapping, and 80h to 98h are reserved only for I/O mapping. Memory based offset I/O based offest 0h Modem REG0 0h 01h Modem REG1 01h 02h : 02h : : : 1Fh Modem REG31 1Fh Reserved SCR0 80h SCR1 88h SCR2 90h SCR3 98h Reserved Reserved 200h Reserved EEPROM 3FF Fig 6.3 I/O and Memory based address map of the modern function REV. 0.1, AUG. 07, 2000 P/N:PM0669 52 MX98727BEC 7. AC/DC CHARACTERISTICS 7.1 BOOT ROM READ TIMING BPA 15-0 TRC FCEB FOEB TOES (CE&OE is typical shorted) TCE TOOLZ TOH TOH BPD 7:0 TCOLZ TACC 7.2 AC CHARACTERISTICS SYMBOL DESCRIPTION MINIMUM TYPICAL MAXIMUM UNITS TRC Read Cycle 8 - - CARDBUS Cycle TCE Chip Enable Access Time - - 7 CARDBUS Cycle TACC Address Access Time - - 7 CARDBUS Cycle TOES Output Enable Access Time - - 7 CARDBUS Cycle TOH Output Hold from Address, CEB, or OEB 0 - - ns CARDBUS cycle range:66ns (16MHz)~30ns (33MHz) REV. 0.1, AUG. 07, 2000 P/N:PM0669 53 MX98727BEC 7.3 ABSOLUTE OPERATION CONDITION Supply Voltage (VCC) DC Input Voltage (Vin) DC Output Voltage (Vout) Storage Temperature Range (Tstg) Operating Temperature Range Operating Surface Temperature(25C) Power Dissipation (PD) Lead Temp. (TL) (Soldering, 10 sec) ESD Rating (Rzap = 1.5k, Czap = 100pF) Clamp Diode Current -0.5V to +7.0V 3.15 V to 3.45 V -0.5V to VCC + 0.5V -55C to +150C 0C to 70C 48 C(TYP) 750 mW (Typ.) 260C 3kV 20mA 7.4 DC CHARACTERISTICS Symbol Parameter Conditions TTL/CARDBUS Input/Output Voh Minimum High Level Output Voltage Ioh = -3mA Vol Maximum Low Level Output Voltage Iol = +6mA Vih Minimum High Level Input Voltage ( 3.3V/5V tolerant ) Vil Maximum Low Level Input Voltage ( 3.3V/5V tolerant ) Iin Input Current Vi = VCC or GND Ioz Minimum TRI-STATE Output Leakage Current Vout = VCC or GND Min Max Units 0.4 2.0 0.8 + 1.0 +10 V V V V uA uA V 2.4 - 1.0 -10 LED output Driver Vlol Supply Idd Vdd LED turn on Output Voltage Iol = 16mA 0.4 Average Supply Current CKREF =25MHz CARDBUSCLK = 33MHz D0 (100Mbps) 150 D1 (100Mbps) 150 D2 (100Mbps) 150 D3 (100Mbps) 150 D0 (10Mbps) 170 D1 (10Mbps) 170 D2 (10Mbps) 170 D3 (10Mbps) 170 3.3V 185 mA 185 180 180 200 195 195 195 5% tolerant Average Supply Voltage REV. 0.1, AUG. 07, 2000 P/N:PM0669 54 MX98727BEC 8.0 PACKAGE INFORMATION 128-Pin Plastic Quad Flat Pack ITEM MILLIMETERS a 14.00.05 5.512.002 b .20 [Typ.] .08 [Typ.] c 20.00.05 7.87.002 d 1.346 .530 D c D3 INCHES e .50 [Typ.] .20 [Typ.] L1 1.60.1 .63.04 L .80.1 .31.04 ZE .75 [Typ.] .30 [Typ.] E3 12.50 [Typ.] 4.92 [Typ.] E 17.20.2 6.77.08 ZD .75 [Typ.] .30 [Typ.] D3 18.50 [Typ.] 7.28 [Typ.] D 23.20.2 9.13.08 A1 .25.1 min. .01.04 min. A 3.40.1 max. 1.34.04 max. Note Short Lead Short Lead NOTE: Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition. ZD 102 103 65 64 E3 128 a E 39 ZE 38 1 H I L1 d A A1 b e L REV. 0.1, AUG. 07, 2000 P/N:PM0669 55 MX98727BEC TOP SIDE MARKING MX98727BEC line 1 : MX98727B is MXIC parts No. "E" :PQFP "C" : commercial grade line 2 : Assembly Date Code. line 3 : Wafer Lot No. line 4 : State M0030 T63165C0B6 TAIWAN MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-6688 FAX:+886-3-563-2888 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.