LMK04800
LMK04800 Family Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
Literature Number: SNAS489H
LMK04800 Family
July 27, 2011
Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
1.0 General Description
The LMK04800 family is the industry's highest performance
clock conditioner with superior clock jitter cleaning, genera-
tion, and distribution with advanced features to meet next
generation system requirements. The dual loop PLLat-
inum™ architecture enables 111 fs rms jitter (12 kHz to 20
MHz) using a low noise VCXO module or sub-200 fs rms jitter
(12 kHz to 20 MHz) using a low cost external crystal and var-
actor diode.
The dual loop architecture consists of two high-performance
phase-locked loops (PLL), a low-noise crystal oscillator cir-
cuit, and a high-performance voltage controlled oscillator
(VCO). The first PLL (PLL1) provides a low-noise jitter cleaner
function while the second PLL (PLL2) performs the clock gen-
eration. PLL1 can be configured to either work with an exter-
nal VCXO module or the integrated crystal oscillator with an
external tunable crystal and varactor diode. When used with
a very narrow loop bandwidth, PLL1 uses the superior close-
in phase noise (offsets below 50 kHz) of the VCXO module
or the tunable crystal to clean the input clock. The output of
PLL1 is used as the clean input reference to PLL2 where it
locks the integrated VCO. The loop bandwidth of PLL2 can
be optimized to clean the far-out phase noise (offsets above
50 kHz) where the integrated VCO outperforms the VCXO
module or tunable crystal used in PLL1.
Device VCO Frequency
LMK04803B 1840 to 2030 MHz
LMK04805B 2148 to 2370 MHz
LMK04806B 2370 to 2600 MHz
LMK04808B 2750 to 3072 MHz
2.0 Features
■Ultra-Low RMS Jitter Performance
—111 fs RMS jitter (12 kHz to 20 MHz)
—123 fs RMS jitter (100 Hz to 20 MHz)
■Dual Loop PLLatinum PLL Architecture
—PLL1
■Integrated Low-Noise Crystal Oscillator Circuit
■Holdover mode when input clocks are lost
—Automatic or manual triggering/recovery
—PLL2
■Normalized [1 Hz] PLL noise floor of -227 dBc/Hz
■Phase detector rate up to 155 MHz
■OSCin frequency-doubler
■Integrated Low-Noise VCO
■2 redundant input clocks with LOS
—Automatic and manual switch-over modes
■50% duty cycle output divides, 1 to 1045 (even and odd)
■LVPECL, LVDS, or LVCMOS programmable outputs
■Precision digital delay, fixed or dynamically adjustable
■25 ps step analog delay control.
■14 differential outputs. Up to 26 single ended.
—Up to 6 VCXO/Crystal buffered outputs
■Clock rates of up to 1536 MHz
■0-delay mode
■Three default clock outputs at power up
■Multi-mode: Dual PLL, single PLL, and clock distribution
■Industrial Temperature Range: -40 to 85 °C
■3.15 V to 3.45 V operation
■Package: 64-pin LLP (9.0 x 9.0 x 0.8 mm)
3.0 Target Applications
■Data Converter Clocking / Wireless Infrastructure
■Networking, SONET/SDH, DSLAM
■Medical / Video / Military / Aerospace
■Test and Measurement
30102340
PLLatinum™ is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation 301023 www.national.com
LMK04800 Family Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
4.0 Device Configuration
Information
NSID Reference Inputs Dedicated Buffered/
Divided OSCin Clock
Programmable LVDS/
LVPECL/LVCMOS
Outputs (Note 1)
VCO
LMK04803BISQ 2 2 12 1840 to 2030 MHz
LMK04805BISQ 2 2 12 2148 to 2370 MHz
LMK04806BISQ 2 2 12 2370 to 2600 MHz
LMK04808BISQ 2 2 12 2750 to 3072 MHz
Note 1: Up to 4 of these outputs are also able to be driven by the OSCin clock.
5.0 Functional Block Diagrams and Operating Modes
The LMK048xx is a flexible device that can be configured for many different use cases. The following simplified block diagrams
help show the user the different use cases of the device.
5.1 Dual PLL
Figure 1 illustrates the typical use case of the LMK048xx in dual loop mode. In dual loop mode the reference to PLL1 is either
CLKin0 or CLKin1. An external VCXO or tunable crystal will be used to provide feedback for the first PLL and a reference to the
second PLL. This first PLL cleans the jitter with the VCXO or low cost tunable crystal by using a narrow loop bandwidth. The VCXO
or tunable crystal output may be buffered through the two OSCout ports and optionally on up to 4 of the CLKouts. The VCXO or
tunable crystal is used as the reference to PLL2 and may be doubled using the frequency doubler. The internal VCO drives up to
six divide/delay blocks which drive 12 clock outputs.
Holdover functionality is optionally available when the input reference clock is lost. Holdover works by fixing the tuning voltage of
PLL1 to the VCXO or tunable crystal.
It is also possible to use an external VCO in place of PLL2's internal VCO.
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FIGURE 1. Simplified Functional Block Diagram for Dual Loop Mode
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LMK04800 Family
5.2 0-Delay Dual PLL
Figure 2 illustrates the use case of 0-delay dual loop mode. This configuration is very similar to Section 5.1 Dual PLL except that
the feedback to the first PLL is driven by a clock output. This causes the clock outputs to have deterministic phase with the clock
input. Since all the clock outputs can be synchronized together, all the clock outputs can be in phase with the clock input signal.
The feedback to PLL1 can be connected internally as shown, or externally using FBCLKin (CLKin1) as an input port.
It is also possible to use an external VCO in place of PLL2's internal VCO.
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FIGURE 2. Simplified Functional Block Diagram for 0-delay Dual Loop Mode
5.3 Single PLL
Figure 3 illustrates the use case of single PLL mode. In single PLL mode only PLL2 is used and PLL1 is powered down. OSCin is
used as the reference input. The internal VCO drives up to 6 divide/delay blocks which drive 12 clock outputs. The reference at
OSCin can be used to drive up to 2 OSCout ports. OSCin can also optionally drive up to 4 of the clock outputs.
It is also possible to use an external VCO in place of PLL2's internal VCO.
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FIGURE 3. Simplified Functional Block Diagram for Single Loop Mode
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LMK04800 Family
5.4 0-delay Single PLL
Figure 4 illustrates the use case of 0-delay single PLL mode. This configuration is very similar to Section 5.3 Single PLL except
that the feedback to PLL2 comes from a clock output. This causes the clock outputs to be in phase with the reference input. Since
all the clock outputs can be synchronized together, all the clock outputs can be in phase with the clock input signal. The feedback
to PLL2 can be performed internally as shown, or externally using FBCLKin (CLKin1) as an input port.
It is also possible to use an external VCO in place of PLL2's internal VCO.
30102311
FIGURE 4. Simplified Functional Block Diagram for 0-delay Single Loop Mode
5.5 Clock Distribution
Figure 5 illustrates the LMK04800 used for clock distribution. CLKin1 is used to drive up to 6 divide/delay blocks which drive 12
outputs. OSCin can be used to drive up to 2 OSCout ports. OSCin can also optionally drive up to 4 of the clock outputs.
30102312
FIGURE 5. Simplified Functional Block Diagram for Mode Clock Distribution
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LMK04800 Family
Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Features ........................................................................................................................................ 1
3.0 Target Applications .......................................................................................................................... 1
4.0 Device Configuration Information ....................................................................................................... 2
5.0 Functional Block Diagrams and Operating Modes ................................................................................ 2
5.1 Dual PLL ................................................................................................................................. 2
5.2 0-Delay Dual PLL ..................................................................................................................... 3
5.3 Single PLL .............................................................................................................................. 3
5.4 0-delay Single PLL ................................................................................................................... 4
5.5 Clock Distribution ..................................................................................................................... 4
5.6 Detailed LMK0480x Block Diagram ............................................................................................. 5
6.0 Connection Diagram ...................................................................................................................... 10
7.0 Pin Descriptions (Note 2)................................................................................................................ 11
8.0 Absolute Maximum Ratings ............................................................................................................ 13
9.0 Package Thermal Resistance .......................................................................................................... 13
10.0 Recommended Operating Conditions ............................................................................................ 13
11.0 Electrical Characteristics ............................................................................................................... 14
12.0 Serial MICROWIRE Timing Diagram .............................................................................................. 22
12.1 ADVANCED MICROWIRE TIMING DIAGRAMS ....................................................................... 22
12.1.1 3 Extra Clocks or Double Program ................................................................................ 22
12.1.2 Three Extra Clocks with LEuWire High .......................................................................... 23
12.1.3 Readback .................................................................................................................. 23
13.0 Measurement Definitions .............................................................................................................. 24
13.1 CHARGE PUMP CURRENT SPECIFICATION DEFINITIONS .................................................... 24
13.1.1 Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage .......... 24
13.1.2 Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch ................. 24
13.1.3 Charge Pump Output Current Magnitude Variation Vs. Temperature ................................. 24
13.2 DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY (Note 28).................................... 25
14.0 Typical Performance Characteristics .............................................................................................. 26
14.2 CLOCK OUTPUT AC CHARACTERISTICS ............................................................................. 26
15.0 Features ..................................................................................................................................... 27
15.1 SYSTEM ARCHITECTURE ................................................................................................... 27
15.2 PLL1 REDUNDANT REFERENCE INPUTS (CLKin0/CLKin0* and CLKin1/CLKin1*) ..................... 27
15.3 PLL1 TUNABLE CRYSTAL SUPPORT ................................................................................... 27
15.4 VCXO/CRYSTAL BUFFERED OUTPUTS ................................................................................ 27
15.5 FREQUENCY HOLDOVER ................................................................................................... 27
15.6 INTEGRATED LOOP FILTER POLES ..................................................................................... 27
15.7 INTERNAL VCO ................................................................................................................... 27
15.8 EXTERNAL VCO MODE ....................................................................................................... 28
15.9 CLOCK DISTRIBUTION ....................................................................................................... 28
15.9.1 CLKout DIVIDER ........................................................................................................ 28
15.9.2 CLKout DELAY .......................................................................................................... 28
15.9.3 PROGRAMMABLE OUTPUT TYPE .............................................................................. 28
15.9.4 CLOCK OUTPUT SYNCHRONIZATION ........................................................................ 28
15.10 0-DELAY ........................................................................................................................... 28
15.11 DEFAULT STARTUP CLOCKS ............................................................................................ 28
15.12 STATUS PINS ................................................................................................................... 28
15.13 REGISTER READBACK ...................................................................................................... 28
16.0 Functional Description .................................................................................................................. 29
16.1 FUNCTIONAL OVERVIEW .................................................................................................... 29
16.2 MODE SELECTION .............................................................................................................. 29
16.3 INPUTS / OUTPUTS ............................................................................................................. 29
16.3.1 PLL1 Reference Inputs (CLKin0 and CLKin1) ................................................................. 29
16.3.2 PLL2 OSCin / OSCin* Port ........................................................................................... 29
16.3.3 CRYSTAL OSCILLATOR ............................................................................................. 29
16.4 INPUT CLOCK SWITCHING .................................................................................................. 30
16.4.1 Input Clock Switching - Manual Mode ............................................................................ 30
16.4.2 Input Clock Switching - Pin Select Mode ........................................................................ 30
16.4.3 Input Clock Switching - Automatic Mode ........................................................................ 30
16.4.4 Input Clock Switching - Automatic Mode with Pin Select ................................................... 31
16.5 HOLDOVER MODE .............................................................................................................. 31
16.5.1 Holdover Frequency Accuracy and DAC Performance ..................................................... 32
16.5.2 Holdover Mode - Automatic Exit of Holdover ................................................................... 32
16.6 PLLs ................................................................................................................................... 32
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LMK04800 Family
16.6.1 PLL1 ......................................................................................................................... 32
16.6.2 PLL2 ......................................................................................................................... 32
16.6.2.1 PLL2 FREQUENCY DOUBLER ......................................................................... 32
16.6.3 DIGITAL LOCK DETECT ............................................................................................. 33
16.7 STATUS PINS ..................................................................................................................... 33
16.7.1 Logic Low .................................................................................................................. 33
16.7.2 Digital Lock Detect ...................................................................................................... 33
16.7.3 Holdover Status .......................................................................................................... 33
16.7.4 DAC ......................................................................................................................... 33
16.7.5 PLL Divider Outputs .................................................................................................... 33
16.7.6 CLKinX_LOS ............................................................................................................. 33
16.7.7 CLKinX Selected ........................................................................................................ 33
16.7.8 MICROWIRE Readback .............................................................................................. 33
16.8 VCO ................................................................................................................................... 33
16.9 CLOCK DISTRIBUTION ........................................................................................................ 34
16.9.1 Fixed Digital Delay ...................................................................................................... 34
16.9.1.1 FIXED DIGITAL DELAY - EXAMPLE ................................................................... 34
16.9.2 Clock Output Synchronization (SYNC) ........................................................................... 34
16.9.2.1 DYNAMICALLY PROGRAMMING DIGITAL DELAY .............................................. 36
16.9.2.1.1 Absolute Dynamic Digital Delay ................................................................ 38
16.9.2.1.1.1 ABSOLUTE DYNAMIC DIGITAL DELAY - EXAMPLE ........................ 38
16.9.2.1.2 Relative Dynamic Digital Delay ................................................................. 40
16.9.2.1.2.1 RELATIVE DYNAMIC DIGITAL DELAY - EXAMPLE .......................... 40
16.9.3 0-Delay Mode ............................................................................................................ 42
17.0 General Programming Information ................................................................................................. 43
17.1 SPECIAL PROGRAMMING CASE FOR R0 to R5 for CLKoutX_Y_DIV & CLKoutX_Y_DDLY ......... 43
17.1.1 Example .................................................................................................................... 43
17.2 RECOMMENDED PROGRAMMING SEQUENCE .................................................................... 43
17.2.1 Overview ................................................................................................................... 43
17.3 READBACK ......................................................................................................................... 44
17.3.1 Readback - Example ................................................................................................... 44
17.4 REGISTER MAP AND READBACK REGISTER MAP ............................................................... 44
17.5 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON RESET .................................... 49
17.6 REGISTER R0 TO R5 ........................................................................................................... 53
17.6.1 CLKoutX_Y_PD, Powerdown CLKoutX_Y Output Path .................................................... 53
17.6.2 CLKoutX_Y_OSCin_Sel, Clock group source ................................................................. 53
17.6.3 CLKoutY_ADLY_SEL[29], CLKoutX_ADLY_SEL[28], Select Analog Delay ......................... 53
17.6.4 CLKoutX_Y_DDLY, Clock Channel Digital Delay ............................................................ 53
17.6.5 RESET ...................................................................................................................... 53
17.6.6 POWERDOWN .......................................................................................................... 54
17.6.7 CLKoutX_Y_HS, Digital Delay Half Shift ........................................................................ 54
17.6.8 CLKoutX_Y_DIV, Clock Output Divide ........................................................................... 54
17.7 REGISTERS R6 TO R8 ......................................................................................................... 54
17.7.1 CLKoutX_TYPE ......................................................................................................... 54
17.7.2 CLKoutX_Y_ADLY ...................................................................................................... 55
17.8 REGISTER R10 ................................................................................................................... 56
17.8.1 OSCout1_LVPECL_AMP, LVPECL Output Amplitude Control .......................................... 56
17.8.2 OSCout0_TYPE ......................................................................................................... 56
17.8.3 EN_OSCoutX, OSCout Output Enable ........................................................................... 56
17.8.4 OSCoutX_MUX, Clock Output Mux ............................................................................... 57
17.8.5 PD_OSCin, OSCin Powerdown Control ......................................................................... 57
17.8.6 OSCout_DIV, Oscillator Output Divide ........................................................................... 57
17.8.7 VCO_MUX ................................................................................................................ 57
17.8.8 EN_FEEDBACK_MUX ................................................................................................ 57
17.8.9 VCO_DIV, VCO Divider ............................................................................................... 57
17.8.10 FEEDBACK_MUX ..................................................................................................... 57
17.9 REGISTER R11 ................................................................................................................... 58
17.9.1 MODE: Device Mode .................................................................................................. 58
17.9.2 EN_SYNC, Enable Synchronization .............................................................................. 58
17.9.3 NO_SYNC_CLKoutX_Y ............................................................................................... 58
17.9.4 SYNC_MUX ............................................................................................................... 58
17.9.5 SYNC_QUAL ............................................................................................................. 59
17.9.6 SYNC_POL_INV ........................................................................................................ 59
17.9.7 SYNC_EN_AUTO ....................................................................................................... 59
17.9.8 SYNC_TYPE ............................................................................................................. 59
17.9.9 EN_PLL2_XTAL ......................................................................................................... 59
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LMK04800 Family
17.10 REGISTER R12 ................................................................................................................. 60
17.10.1 LD_MUX .................................................................................................................. 60
17.10.2 LD_TYPE ................................................................................................................ 60
17.10.3 SYNC_PLLX_DLD .................................................................................................... 60
17.10.4 EN_TRACK ............................................................................................................. 60
17.10.5 HOLDOVER_MODE ................................................................................................. 60
17.11 REGISTER R13 ................................................................................................................. 61
17.11.1 HOLDOVER_MUX .................................................................................................... 61
17.11.2 HOLDOVER_TYPE ................................................................................................... 61
17.11.3 Status_CLKin1_MUX ................................................................................................ 61
17.11.4 Status_CLKin0_TYPE ............................................................................................... 61
17.11.5 DISABLE_DLD1_DET ............................................................................................... 61
17.11.6 Status_CLKin0_MUX ................................................................................................ 61
17.11.7 CLKin_SELECT_MODE ............................................................................................ 62
17.11.8 CLKin_Sel_INV ........................................................................................................ 62
17.11.9 EN_CLKinX ............................................................................................................. 62
17.12 REGISTER 14 .................................................................................................................... 63
17.12.1 LOS_TIMEOUT ........................................................................................................ 63
17.12.2 EN_LOS .................................................................................................................. 63
17.12.3 Status_CLKin1_TYPE ............................................................................................... 63
17.12.4 CLKinX_BUF_TYPE, PLL1 CLKinX/CLKinX* Buffer Type ............................................... 63
17.12.5 DAC_HIGH_TRIP ..................................................................................................... 63
17.12.6 DAC_LOW_TRIP ...................................................................................................... 63
17.12.7 EN_VTUNE_RAIL_DET ............................................................................................. 63
17.13 REGISTER 15 .................................................................................................................... 64
17.13.1 MAN_DAC ............................................................................................................... 64
17.13.2 EN_MAN_DAC ......................................................................................................... 64
17.13.3 HOLDOVER_DLD_CNT ............................................................................................ 64
17.13.4 FORCE_HOLDOVER ................................................................................................ 64
17.14 REGISTER 16 .................................................................................................................... 64
17.14.1 XTAL_LVL ............................................................................................................... 64
17.15 REGISTER 23 .................................................................................................................... 64
17.15.1 DAC_CNT ............................................................................................................... 64
17.16 REGISTER 24 .................................................................................................................... 64
17.16.1 PLL2_C4_LF, PLL2 Integrated Loop Filter Component .................................................. 64
17.16.2 PLL2_C3_LF, PLL2 Integrated Loop Filter Component .................................................. 65
17.16.3 PLL2_R4_LF, PLL2 Integrated Loop Filter Component .................................................. 65
17.16.4 PLL2_R3_LF, PLL2 Integrated Loop Filter Component .................................................. 65
17.16.5 PLL1_N_DLY ........................................................................................................... 65
17.16.6 PLL1_R_DLY ........................................................................................................... 65
17.16.7 PLL1_WND_SIZE ..................................................................................................... 65
17.17 REGISTER 25 .................................................................................................................... 66
17.17.1 DAC_CLK_DIV ......................................................................................................... 66
17.17.2 PLL1_DLD_CNT ....................................................................................................... 66
17.18 REGISTER 26 .................................................................................................................... 66
17.18.1 PLL2_WND_SIZE ..................................................................................................... 66
17.18.2 EN_PLL2_REF_2X, PLL2 Reference Frequency Doubler ............................................... 66
17.18.3 PLL2_CP_POL, PLL2 Charge Pump Polarity ................................................................ 66
17.18.4 PLL2_CP_GAIN, PLL2 Charge Pump Current .............................................................. 66
17.18.5 PLL2_DLD_CNT ....................................................................................................... 66
17.18.6 PLL2_CP_TRI, PLL2 Charge Pump TRI-STATE ........................................................... 66
17.19 REGISTER 27 .................................................................................................................... 67
17.19.1 PLL1_CP_POL, PLL1 Charge Pump Polarity ................................................................ 67
17.19.2 PLL1_CP_GAIN, PLL1 Charge Pump Current .............................................................. 67
17.19.3 CLKinX_PreR_DIV .................................................................................................... 67
17.19.4 PLL1_R, PLL1 R Divider ............................................................................................ 67
17.19.5 PLL1_CP_TRI, PLL1 Charge Pump TRI-STATE ........................................................... 67
17.20 REGISTER 28 .................................................................................................................... 68
17.20.1 PLL2_R, PLL2 R Divider ............................................................................................ 68
17.20.2 PLL1_N, PLL1 N Divider ............................................................................................ 68
17.21 REGISTER 29 .................................................................................................................... 68
17.21.1 OSCin_FREQ, PLL2 Oscillator Input Frequency Register ............................................... 68
17.21.2 PLL2_FAST_PDF, High PLL2 Phase Detector Frequency .............................................. 68
17.21.3 PLL2_N_CAL, PLL2 N Calibration Divider .................................................................... 68
17.22 REGISTER 30 .................................................................................................................... 69
17.22.1 PLL2_P, PLL2 N Prescaler Divider .............................................................................. 69
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LMK04800 Family
17.22.2 PLL2_N, PLL2 N Divider ............................................................................................ 69
17.23 REGISTER 31 .................................................................................................................... 69
17.23.1 READBACK_LE ....................................................................................................... 69
17.23.2 READBACK_ADDR .................................................................................................. 69
17.23.3 uWire_LOCK ............................................................................................................ 69
18.0 Application Information ................................................................................................................. 70
18.1 FREQUENCY PLANNING WITH THE LMK04800 FAMILY (Note 36)........................................... 70
18.2 PLL PROGRAMMING ........................................................................................................... 71
18.2.1 Example PLL2 N Divider Programming .......................................................................... 71
18.3 LOOP FILTER ..................................................................................................................... 72
18.3.1 PLL1 ......................................................................................................................... 72
18.3.2 PLL2 ......................................................................................................................... 72
18.4 SYSTEM LEVEL DIAGRAM ................................................................................................... 73
18.5 PIN CONNECTION RECOMMENDATIONS ............................................................................. 75
18.5.1 Vcc Pins and Decoupling ............................................................................................. 75
18.5.1.1 Vcc2, Vcc3, Vcc10, Vcc11, Vcc12, Vcc13 (CLKout Vccs) ....................................... 75
18.5.1.2 Vcc1 (VCO), Vcc4 (Digital), and Vcc9 (PLL2) ........................................................ 75
18.5.1.3 Vcc6 (PLL1 Charge Pump) and Vcc8 (PLL2 Charge Pump) .................................... 75
18.5.1.4 Vcc5 (CLKin & OSCout1), Vcc7 (OSCin & OSCout0) ............................................. 75
18.5.2 LVPECL Outputs ........................................................................................................ 75
18.5.3 Unused Clock Outputs ................................................................................................ 75
18.5.4 Unused Clock Inputs ................................................................................................... 75
18.5.5 LDO Bypass .............................................................................................................. 75
18.6 DIGITAL LOCK DETECT FREQUENCY ACCURACY ............................................................... 76
18.6.1 Minimum Lock Time Calculation Example ...................................................................... 76
18.7 CALCULATING DYNAMIC DIGITAL DELAY VALUES FOR ANY DIVIDE .................................... 77
18.7.1 Example .................................................................................................................... 77
18.8 OPTIONAL CRYSTAL OSCILLATOR IMPLEMENTATION (OSCin/OSCin*) ................................. 79
18.9 DRIVING CLKin AND OSCin INPUTS ..................................................................................... 82
18.9.1 Driving CLKin Pins with a Differential Source .................................................................. 82
18.9.2 Driving CLKin Pins with a Single-Ended Source .............................................................. 82
18.10 TERMINATION AND USE OF CLOCK OUTPUT (DRIVERS) .................................................... 83
18.10.1 Termination for DC Coupled Differential Operation ........................................................ 83
18.10.2 Termination for AC Coupled Differential Operation ........................................................ 83
18.10.3 Termination for Single-Ended Operation ...................................................................... 84
18.11 POWER SUPPLY ............................................................................................................... 85
18.11.1 Current Consumption / Power Dissipation Calculations .................................................. 85
18.12 THERMAL MANAGEMENT .................................................................................................. 87
19.0 Physical Dimensions .................................................................................................................... 88
20.0 Ordering Information .................................................................................................................... 88
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LMK04800 Family
6.0 Connection Diagram
64-Pin LLP Package
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LMK04800 Family
7.0 Pin Descriptions (Note 2)
Pin Number Name(s) I/O Type Description
1, 2 CLKout0,
CLKout0* O Programmable Clock output 0 (clock group 0).
3, 4 CLKout1*,
CLKout1 O Programmable Clock output 1 (clock group 0).
6 SYNC I/O Programmable CLKout Synchronization input or programmable
status pin.
5, 7, 8, 9 NC No Connection. These pins must be left floating.
10 Vcc1 PWR Power supply for VCO LDO.
11 LDObyp1 ANLG LDO Bypass, bypassed to ground with 10 µF
capacitor.
12 LDObyp2 ANLG LDO Bypass, bypassed to ground with a 0.1 µF
capacitor.
13, 14 CLKout2,
CLKout2* O Programmable Clock output 2 (clock group 1).
15, 16 CLKout3*,
CLKout3 O Programmable Clock output 3 (clock group 1).
17 Vcc2 PWR Power supply for clock group 1: CLKout2 and
CLKout3.
18 Vcc3 PWR Power supply for clock group 2: CLKout4 and
CLKout5.
19, 20 CLKout4,
CLKout4* O Programmable Clock output 4 (clock group 2).
21, 22 CLKout5*,
CLKout5 O Programmable Clock output 5 (clock group 2).
23 GND PWR Ground
24 Vcc4 PWR Power supply for digital.
25, 26
CLKin1, CLKin1*
I ANLG
Reference Clock Input Port 1 for PLL1. AC or DC
Coupled.
FBCLKin,
FBCLKin*
Feedback input for external clock feedback input (0-
delay mode). AC or DC Coupled.
Fin/Fin* External VCO input (External VCO mode). AC or DC
Coupled.
27 Status_Holdover I/O Programmable
Programmable status pin, default readback output.
Programmable to holdover mode indicator. Other
options available by programming.
28, 29 CLKin0, CLKin0* I ANLG Reference Clock Input Port 0 for PLL1.
AC or DC Coupled.
30 Vcc5 PWR Power supply for clock inputs.
31, 32 OSCout1,
OSCout1* O LVPECL Buffered output 1 of OSCin port.
33 Status_LD I/O Programmable
Programmable status pin, default lock detect for
PLL1 and PLL2. Other options available by
programming.
34 CPout1 O ANLG Charge pump 1 output.
35 Vcc6 PWR Power supply for PLL1, charge pump 1.
36, 37 OSCin, OSCin* I ANLG Feedback to PLL1, Reference input to PLL2.
AC Coupled.
38 Vcc7 PWR Power supply for OSCin port.
39, 40 OSCout0,
OSCout0* O Programmable Buffered output 0 of OSCin port.
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LMK04800 Family
Pin Number Name(s) I/O Type Description
41 Vcc8 PWR Power supply for PLL2, charge pump 2.
42 CPout2 O ANLG Charge pump 2 output.
43 Vcc9 PWR Power supply for PLL2.
44 LEuWire I CMOS MICROWIRE Latch Enable Input.
45 CLKuWire I CMOS MICROWIRE Clock Input.
46 DATAuWire I CMOS MICROWIRE Data Input.
47 Vcc10 PWR Power supply for clock group 3: CLKout6 and
CLKout7.
48, 49 CLKout6,
CLKout6* O Programmable Clock output 6 (clock group 3).
50, 51 CLKout7*,
CLKout7 O Programmable Clock output 7 (clock group 3).
52 Vcc11 PWR Power supply for clock group 4: CLKout8 and
CLKout9.
53, 54 CLKout8,
CLKout8* O Programmable Clock output 8 (clock group 4).
55, 56 CLKout9*,
CLKout9 O Programmable Clock output 9 (clock group 4).
57 Vcc12 PWR Power supply for clock group 5: CLKout10 and
CLKout11.
58, 59 CLKout10,
CLKout10* O Programmable Clock output 10 (clock group 5).
60, 61 CLKout11*,
CLKout11 O Programmable Clock output 11 (clock group 5).
62 Status_CLKin0 I/O Programmable
Programmable status pin. Default is input for pin
control of PLL1 reference clock selection. CLKin0
LOS status and other options available by
programming.
63 Status_CLKin1 I/O Programmable
Programmable status pin. Default is input for pin
control of PLL1 reference clock selection. CLKin1
LOS status and other options available by
programming.
64 Vcc13 PWR Power supply for clock group 0: CLKout0 and
CLKout1.
DAP DAP GND DIE ATTACH PAD, connect to GND.
Note 2: See Application Information section for recommended connections.
www.national.com 12
LMK04800 Family
8.0 Absolute Maximum Ratings (Note 3, Note 4, Note 5)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors
for availability and specifications.
Parameter Symbol Ratings Units
Supply Voltage (Note 6)VCC -0.3 to 3.6 V
Input Voltage VIN -0.3 to (VCC + 0.3) V
Storage Temperature Range TSTG -65 to 150 °C
Lead Temperature (solder 4 seconds) TL+260 °C
Junction Temperature TJ125 °C
Differential Input Current (CLKinX/X*,
OSCin/OSCin*, FBCLKin/FBCLKin*, Fin/Fin*) IIN ± 5 mA
Moisture Sensitivity Level MSL 3
Note 3: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only to the test conditions listed.
Note 4: This device is a high performance RF integrated circuit with an ESD rating up to 2 kV Human Body Model, up to 150 V Machine Model, and up to 750 V
Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free workstations.
Note 5: Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only.
Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure
to absolute maximum ratings for extended periods can adversely affect device reliability.
Note 6: Never to exceed 3.6 V.
9.0 Package Thermal Resistance
64-Lead LLP
Parameter Symbol Ratings Units
Thermal resistance from junction to ambient on
4-layer JEDEC PCB (Note 7)θJA 19.5 ° C/W
Thermal resistance from junction to case
(Note 8)θJC 1.5 ° C/W
Note 7: Specification assumes 32 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC PCB. These vias play a key role
in improving the thermal performance of the LLP. Note that the JEDEC PCB is a standard thermal measurement PCB and does not represent best performance
a PCB can achieve. It is recommended that the maximum number of vias be used in the board layout. θJA is unique for each PCB.
Note 8: Case is defined as the DAP (die attach pad).
10.0 Recommended Operating Conditions
Parameter Symbol Condition Min Typical Max Unit
Ambient
Temperature TAVCC = 3.3 V -40 25 85 °C
Supply Voltage VCC 3.15 3.3 3.45 V
13 www.national.com
LMK04800 Family
11.0 Electrical Characteristics
(3.15 V ≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 °C,
at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol Parameter Conditions Min Typ Max Units
Current Consumption
ICC_PD Power Down Supply Current No DC path to ground on OSCout1/1*
(Note 9) 1 3 mA
ICC_CLKS
Supply Current with all clocks enabled
(Note 11)
All clock delays disabled,
CLKoutX_Y_DIV = 1045,
CLKoutX_TYPE = 1 (LVDS),
PLL1 and PLL2 locked.
505 590 mA
CLKin0/0* and CLKin1/1* Input Clock Specifications
fCLKin
Clock Input Frequency
(Note 12) 0.001 500 MHz
SLEWCLKin
Clock Input Slew Rate
(Note 26)20% to 80% 0.15 0.5 V/ns
VIDCLKin Clock Input
Differential Input Voltage
(Note 10)
Figure 11
AC coupled
CLKinX_BUF_TYPE = 0 (Bipolar)
0.25 1.55 |V|
VSSCLKin 0.5 3.1 Vpp
VIDCLKin AC coupled
CLKinX_BUF_TYPE = 1 (MOS)
0.25 1.55 |V|
VSSCLKin 0.5 3.1 Vpp
VCLKin
Clock Input
Single-ended Input Voltage
(Note 26)
AC coupled to CLKinX; CLKinX* AC
coupled to Ground
CLKinX_BUF_TYPE = 0 (Bipolar)
0.25 2.4 Vpp
AC coupled to CLKinX; CLKinX* AC
coupled to Ground
CLKinX_BUF_TYPE = 1 (MOS)
0.25 2.4 Vpp
VCLKin0-offset
DC offset voltage between CLKin0/
CLKin0*
CLKin0* - CLKin0 Each pin AC coupled
CLKin0_BUF_TYPE = 0 (Bipolar)
20 mV
VCLKin1-offset
DC offset voltage between CLKin1/
CLKin1*
CLKin1* - CLKin1
0 mV
VCLKinX-offset
DC offset voltage between CLKinX/
CLKinX*
CLKinX* - CLKinX
Each pin AC coupled
CLKinX_BUF_TYPE = 1 (MOS) 55 mV
VCLKin- VIH High input voltage DC coupled to CLKinX; CLKinX* AC
coupled to Ground
CLKinX_BUF_TYPE = 1 (MOS)
2.0 VCC V
VCLKin- VIL Low input voltage 0.0 0.4 V
FBCLKin/FBCLKin* and Fin/Fin* Input Specifications
fFBCLKin
Clock Input Frequency
(Note 26)
AC coupled
(CLKinX_BUF_TYPE = 0)
MODE = 2 or 8; FEEDBACK_MUX =
6
0.001 1000 MHz
fFin
Clock Input Frequency
(Note 26)
AC coupled
(CLKinX_BUF_TYPE = 0)
MODE = 3 or 11
0.001 3100 MHz
VFBCLKin/Fin
Single Ended
Clock Input Voltage
(Note 26)
AC coupled;
(CLKinX_BUF_TYPE = 0) 0.25 2.0 Vpp
SLEWFBCLKin/Fin
Slew Rate on CLKin
(Note 26)
AC coupled; 20% to 80%;
(CLKinX_BUF_TYPE = 0) 0.15 0.5 V/ns
www.national.com 14
LMK04800 Family
Symbol Parameter Conditions Min Typ Max Units
PLL1 Specifications
fPD1 PLL1 Phase Detector Frequency 40 MHz
ICPout1SOURCE
PLL1 Charge
Pump Source Current
(Note 14)
VCPout1 = VCC/2, PLL1_CP_GAIN = 0 100
µA
VCPout1 = VCC/2, PLL1_CP_GAIN = 1 200
VCPout1 = VCC/2, PLL1_CP_GAIN = 2 400
VCPout1 = VCC/2, PLL1_CP_GAIN = 3 1600
ICPout1SINK
PLL1 Charge
Pump Sink Current
(Note 14)
VCPout1=VCC/2, PLL1_CP_GAIN = 0 -100
µA
VCPout1=VCC/2, PLL1_CP_GAIN = 1 -200
VCPout1=VCC/2, PLL1_CP_GAIN = 2 -400
VCPout1=VCC/2, PLL1_CP_GAIN = 3 -1600
ICPout1%MIS Charge Pump
Sink / Source Mismatch VCPout1 = VCC/2, T = 25 °C 3 10 %
ICPout1VTUNE
Magnitude of Charge Pump Current
Variation vs. Charge Pump Voltage
0.5 V < VCPout1 < VCC - 0.5 V
TA = 25 °C 4 %
ICPout1%TEMP Charge Pump Current vs.
Temperature Variation 4 %
ICPout1 TRI Charge Pump TRI-STATE®Leakage
Current 0.5 V < VCPout < VCC - 0.5 V 5 nA
PN10kHz
PLL 1/f Noise at 10 kHz offset.
Normalized to 1 GHz Output
Frequency
PLL1_CP_GAIN = 400 µA -117
dBc/Hz
PLL1_CP_GAIN = 1600 µA -118
PN1Hz Normalized Phase Noise Contribution PLL1_CP_GAIN = 400 µA -221.5 dBc/Hz
PLL1_CP_GAIN = 1600 µA -223
PLL2 Reference Input (OSCin) Specifications
fOSCin
PLL2 Reference Input
(Note 15) 500 MHz
SLEWOSCin
PLL2 Reference Clock minimum slew
rate on OSCin(Note 26)20% to 80% 0.15 0.5 V/ns
VOSCin
Input Voltage for OSCin or OSCin*
(Note 26)
AC coupled; Single-ended (Unused
pin AC coupled to GND) 0.2 2.4 Vpp
VIDOSCin Differential voltage swing
Figure 11 AC coupled 0.2 1.55 |V|
VSSOSCin 0.4 3.1 Vpp
VOSCin-offset
DC offset voltage between OSCin/
OSCin*
OSCinX* - OSCinX
Each pin AC coupled 20 mV
fdoubler_max Doubler input frequency (Note 26)EN_PLL2_REF_2X = 1;
OSCin Duty Cycle 40% to 60% 155 MHz
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LMK04800 Family
Symbol Parameter Conditions Min Typ Max Units
Crystal Oscillator Mode Specifications
fXTAL
Crystal Frequency Range
(Note 26)RESR < 40 Ω 6 20.5 MHz
PXTAL Crystal Power Dissipation (Note 17)
Vectron VXB1 crystal, 20.48 MHz,
RESR < 40 Ω
XTAL_LVL = 0
100 µW
CIN
Input Capacitance of LMK0480x
OSCin port -40 to +85 °C 6 pF
PLL2 Phase Detector and Charge Pump Specifications
fPD2 Phase Detector Frequency 155 MHz
ICPoutSOURCE PLL2 Charge Pump Source Current
(Note 14)
VCPout2=VCC/2, PLL2_CP_GAIN = 0 100
µA
VCPout2=VCC/2, PLL2_CP_GAIN = 1 400
VCPout2=VCC/2, PLL2_CP_GAIN = 2 1600
VCPout2=VCC/2, PLL2_CP_GAIN = 3 3200
ICPoutSINK PLL2 Charge Pump Sink Current
(Note 14)
VCPout2=VCC/2, PLL2_CP_GAIN = 0 -100
µA
VCPout2=VCC/2, PLL2_CP_GAIN = 1 -400
VCPout2=VCC/2, PLL2_CP_GAIN = 2 -1600
VCPout2=VCC/2, PLL2_CP_GAIN = 3 -3200
ICPout2%MIS Charge Pump Sink/Source Mismatch VCPout2=VCC/2, TA = 25 °C 3 10 %
ICPout2VTUNE
Magnitude of Charge Pump Current
vs. Charge Pump Voltage Variation
0.5 V < VCPout2 < VCC - 0.5 V
TA = 25 °C 4 %
ICPout2%TEMP Charge Pump Current vs.
Temperature Variation 4 %
ICPout2TRI Charge Pump Leakage 0.5 V < VCPout2 < VCC - 0.5 V 10 nA
PN10kHz
PLL 1/f Noise at 10 kHz offset
(Note 18). Normalized to
1 GHz Output Frequency
PLL2_CP_GAIN = 400 µA -118
dBc/Hz
PLL2_CP_GAIN = 3200 µA -121
PN1Hz Normalized Phase Noise Contribution
(Note 19)
PLL2_CP_GAIN = 400 µA -222.5 dBc/Hz
PLL2_CP_GAIN = 3200 µA -227
www.national.com 16
LMK04800 Family
Symbol Parameter Conditions Min Typ Max Units
Internal VCO Specifications
fVCO VCO Tuning Range
LMK04803 1840 2030
MHz
LMK04805 2148 2370
LMK04806 2370 2600
LMK04808 2750 3072
KVCO
Fine Tuning Sensitivity
(The range displayed in the typical
column indicates the lower sensitivity
is typical at the lower end of the tuning
range, and the higher tuning
sensitivity is typical at the higher end
of the tuning range).
LMK04808 20 to 36 MHz/V
|ΔTCL|
Allowable Temperature Drift for
Continuous Lock
(Note 20, Note 26)
After programming R30 for lock, no
changes to output configuration are
permitted to guarantee continuous
lock
125 °C
CLKout Closed Loop Jitter Specifications using a Commercial Quality VCXO (Note 23)
L(f)CLKout
LMK04808
fCLKout = 245.76 MHz
SSB Phase Noise
Measured at Clock Outputs
Value is average for all output types
(Note 21)
Offset = 1 kHz -122.5
dBc/Hz
Offset = 10 kHz -132.9
Offset = 100 kHz -135.2
Offset = 800 kHz -143.9
Offset = 10 MHz; LVDS -156.0
Offset = 10 MHz; LVPECL 1600 mVpp -157.5
Offset = 10 MHz; LVCMOS -157.1
JCLKout
LVDS/LVPECL/
LVCMOS
LMK04803(Note 21)
fCLKout = 245.76 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 112
fs rms
BW = 100 Hz to 20 MHz 121
LMK04805(Note 21)
fCLKout = 245.76 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 113
BW = 100 Hz to 20 MHz 122
LMK04806(Note 21)
fCLKout = 245.76 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 115
BW = 100 Hz to 20 MHz 123
LMK04808(Note 21)
fCLKout = 245.76 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 111
BW = 100 Hz to 20 MHz 123
CLKout Closed Loop Jitter Specifications using the Integrated Low Noise Crystal Oscillator Circuit (Note 24)
LMK04808
fCLKout = 245.76 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz
XTAL_LVL = 3 192
BW = 100 Hz to 20 MHz
XTAL_LVL = 3 450
17 www.national.com
LMK04800 Family
Symbol Parameter Conditions Min Typ Max Units
Default Power On Reset Clock Output Frequency
fCLKout-startup
Default output clock frequency at
device power on
(Note 25)
CLKout8, LVDS, LMK04803 69 77 87
MHz
CLKout8, LVDS, LMK04805 90 80 99
CLKout8, LVDS, LMK04806 90 98 110
CLKout8, LVDS, LMK04808 90 110 130
Clock Skew and Delay
|TSKEW|
Maximum CLKoutX to CLKoutY
(Note 22, Note 26)
LVDS-to-LVDS, T = 25 °C,
FCLK = 800 MHz, RL= 100 Ω
AC coupled
30
ps
LVPECL-to-LVPECL,
T = 25 °C,
FCLK = 800 MHz, RL= 100 Ω
emitter resistors =
240 Ω to GND
AC coupled
30
Maximum skew between any two
LVCMOS outputs, same CLKout or
different CLKout (Note 22, Note 26)
RL = 50 Ω, CL = 5 pF,
T = 25 °C, FCLK = 100 MHz.
(Note 22)
100
MixedTSKEW LVDS or LVPECL to LVCMOS Same device, T = 25 °C,
250 MHz 750 ps
td0-DELAY
CLKin to CLKoutX delay
(Note 22)
MODE = 2
PLL1_R_DLY = 0; PLL1_N_DLY = 0 1850
ps
MODE = 2
PLL1_R_DLY = 0; PLL1_N_DLY = 0;
VCO Frequency = 2949.12 MHz
Analog delay select = 0;
Feedback clock digital delay = 11;
Feedback clock half step = 1;
Output clock digital delay = 5;
Output clock half step = 0;
0
LVDS Clock Outputs (CLKoutX), CLKoutX_TYPE = 1
fCLKout
Maximum Frequency
(Note 26, Note 27)RL = 100 Ω 1536 MHz
VOD Differential Output Voltage
Figure 12
T = 25 °C, DC measurement
AC coupled to receiver input
R = 100 Ω differential termination
250 400 450 |mV|
VSS 500 800 900 mVpp
ΔVOD
Change in Magnitude of VOD for
complementary output states -50 50 mV
VOS Output Offset Voltage 1.125 1.25 1.375 V
ΔVOS
Change in VOS for complementary
output states 35 |mV|
TR / TF
Output Rise Time 20% to 80%, RL = 100 Ω 200 ps
Output Fall Time 80% to 20%, RL = 100 Ω
ISA
ISB
Output short circuit current - single
ended
Single-ended output shorted to GND,
T = 25 °C -24 24 mA
ISAB
Output short circuit current -
differential Complimentary outputs tied together -12 12 mA
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LMK04800 Family
Symbol Parameter Conditions Min Typ Max Units
LVPECL Clock Outputs (CLKoutX)
fCLKout
Maximum Frequency
(Note 26, Note 27) 1536 MHz
TR / TF
20% to 80% Output Rise RL = 100 Ω, emitter resistors = 240
Ω to GND
CLKoutX_TYPE = 4 or 5
(1600 or 2000 mVpp)
150 ps
80% to 20% Output Fall Time
700 mVpp LVPECL Clock Outputs (CLKoutX), CLKoutX_TYPE = 2
VOH Output High Voltage
T = 25 °C, DC measurement
Termination = 50 Ω to
VCC - 1.4 V
VCC -
1.03 V
VOL Output Low Voltage VCC -
1.41 V
VOD Output Voltage
Figure 12
305 380 440 |mV|
VSS 610 760 880 mVpp
1200 mVpp LVPECL Clock Outputs (CLKoutX), CLKoutX_TYPE = 3
VOH Output High Voltage
T = 25 °C, DC measurement
Termination = 50 Ω to
VCC - 1.7 V
VCC -
1.07 V
VOL Output Low Voltage VCC -
1.69 V
VOD Output Voltage
Figure 12
545 625 705 |mV|
VSS 1090 1250 1410 mVpp
1600 mVpp LVPECL Clock Outputs (CLKoutX), CLKoutX_TYPE = 4
VOH Output High Voltage
T = 25 °C, DC Measurement
Termination = 50 Ω to
VCC - 2.0 V
VCC -
1.10 V
VOL Output Low Voltage VCC -
1.97 V
VOD Output Voltage
Figure 12
660 870 965 |mV|
VSS 1320 1740 1930 mVpp
2000 mVpp LVPECL (2VPECL) Clock Outputs (CLKoutX), CLKoutX_TYPE = 5
VOH Output High Voltage
T = 25 °C, DC Measurement
Termination = 50 Ω to
VCC - 2.3 V
VCC -
1.13 V
VOL Output Low Voltage VCC -
2.20 V
VOD Output Voltage
Figure 12
800 1070 1200 |mV|
VSS 1600 2140 2400 mVpp
19 www.national.com
LMK04800 Family
Symbol Parameter Conditions Min Typ Max Units
LVCMOS Clock Outputs (CLKoutX)
fCLKout
Maximum Frequency
(Note 26, Note 27)5 pF Load 250 MHz
VOH Output High Voltage 1 mA Load VCC -
0.1 V
VOL Output Low Voltage 1 mA Load 0.1 V
IOH Output High Current (Source) VCC = 3.3 V, VO = 1.65 V 28 mA
IOL Output Low Current (Sink) VCC = 3.3 V, VO = 1.65 V 28 mA
DUTYCLK
Output Duty Cycle
(Note 26)
VCC/2 to VCC/2, FCLK = 100 MHz, T =
25 °C 45 50 55 %
TROutput Rise Time 20% to 80%, RL = 50 Ω,
CL = 5 pF 400 ps
TFOutput Fall Time 80% to 20%, RL = 50 Ω,
CL = 5 pF 400 ps
Digital Outputs (Status_CLKinX, Status_LD, Status_Holdover, SYNC)
VOH High-Level Output Voltage IOH = -500 µA VCC -
0.4 V
VOL Low-Level Output Voltage IOL = 500 µA 0.4 V
Digital Inputs (Status_CLKinX, SYNC)
VIH High-Level Input Voltage 1.6 VCC V
VIL Low-Level Input Voltage 0.4 V
IIH
High-Level Input Current
VIH = VCC
Status_CLKinX_TYPE = 0
(High Impedance) -5 5
µA
Status_CLKinX_TYPE = 1
(Pull-up) -5 5
Status_CLKinX_TYPE = 2
(Pull-down) 10 80
IIL
Low-Level Input Current
VIL = 0 V
Status_CLKinX_TYPE = 0
(High Impedance) -5 5
µA
Status_CLKinX_TYPE = 1
(Pull-up) -40 -5
Status_CLKinX_TYPE = 2
(Pull-down) -5 5
Digital Inputs (CLKuWire, DATAuWire, LEuWire)
VIH High-Level Input Voltage 1.6 VCC V
VIL Low-Level Input Voltage 0.4 V
IIH High-Level Input Current VIH = VCC 5 25 µA
IIL Low-Level Input Current VIL = 0 -5 5 µA
www.national.com 20
LMK04800 Family
Symbol Parameter Conditions Min Typ Max Units
MICROWIRE Interface Timing
TECS LE to Clock Set Up Time See MICROWIRE Input Timing 25 ns
TDCS Data to Clock Set Up Time See MICROWIRE Input Timing 25 ns
TCDH Clock to Data Hold Time See MICROWIRE Input Timing 8 ns
TCWH Clock Pulse Width High See MICROWIRE Input Timing 25 ns
TCWL Clock Pulse Width Low See MICROWIRE Input Timing 25 ns
TCES Clock to LE Set Up Time See MICROWIRE Input Timing 25 ns
TEWH LE Pulse Width See MICROWIRE Input Timing 25 ns
TCR Falling Clock to Readback Time See MICROWIRE Readback Timing 25 ns
Note 9: If emitter resistors are placed on the OSCout1/1* pins, there will be a DC current to ground which will cause powerdown Icc to increase.
Note 10: See Section 13.2 DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY (Note 28) for definition of VID and VOD voltages.
Note 11: Load conditions for output clocks: LVDS: 100 Ω differential. See applications section Section 18.11.1 Current Consumption / Power Dissipation
Calculations for Icc for specific part configuration and how to calculate Icc for a specific design.
Note 12: CLKin0, CLKin1 maximum is guaranteed by characterization, production tested at 200 MHz.
Note 13: In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is
0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the
device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible
to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest
possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.
Note 14: This parameter is programmable
Note 15: FOSCin maximum frequency guaranteed by characterization. Production tested at 200 MHz.
Note 16: The EN_PLL2_REF_2X bit (Register 13) enables/disables a frequency doubler mode for the PLL2 OSCin path.
Note 17: See Application Section discussion of Crystal Power Dissipation. Section 18.8 OPTIONAL CRYSTAL OSCILLATOR IMPLEMENTATION (OSCin/
OSCin*)
Note 18: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10
dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker
(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade
slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f)
can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of
LPLL_flicker(f) and LPLL_flat(f).
Note 19: A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1HZ=LPLL_flat(f) -
20log(N) - 10log(fPDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fPDX is the phase detector
frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
Note 20: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that
the R30 register was last programmed, and still have the part stay in lock. The action of programming the R30 register, even to the same value, activates a
frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift
for continuous lock, then it will be necessary to reload the R30 register to ensure it stays in lock. Regardless of what temperature the part was initially programmed
at, the temperature can never drift outside the frequency range of -40 °C to 85 °C without violating specifications.
Note 21: fVCO = 2949.12 MHz, PLL1 parameters: FPD1 = 1.024 MHz, ICP1 = 100 μA, loop bandwidth = 10 Hz. A 122.88 MHz Crystek CVHD-950–122.880. PLL2
parameters: PLL2_R = 1, FPD2 = 122.88 MHz, ICP2 = 3200 μA, C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, PLL2_C3_LF = 0, PLL2_R3_LF = 0, PLL2_C4_LF = 0,
PLL2_R4_LF = 0, CLKoutX_Y_DIV = 12, and CLKoutX_ADLY_SEL = 0.
Note 22: Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid for delay mode.
Note 23: VCXO used is a 122.88 MHz Crystek CVHD-950-122.880.
Note 24: Crystal used is a 20.48 MHz Vectron VXB1-1150-20M480 and Skyworks varactor diode, SMV-1249-074LF.
Note 25: CLKout6 and OSCout0 also oscillate at start-up at the frequency of the VCXO attached to OSCin port.
Note 26: Guaranteed by characterization.
Note 27: Refer to typical performance charts for output operation performance at higher frequencies than the minimum maximum output frequency.
21 www.national.com
LMK04800 Family
12.0 Serial MICROWIRE Timing Diagram
Register programming information on the DATAuWire pin is clocked into a shift register on each rising edge of the CLKuWire signal.
On the rising edge of the LEuWire signal, the register is sent from the shift register to the register addressed. A slew rate of at least
30 V/µs is recommended for these signals. After programming is complete the CLKuWire, DATAuWire, and LEuWire signals should
be returned to a low state. If the CLKuWire or DATAuWire lines are toggled while the VCO is in lock, as is sometimes the case
when these lines are shared with other parts, the phase noise may be degraded during this programming.
30102303
FIGURE 7. MICROWIRE Timing Diagram
12.1 ADVANCED MICROWIRE TIMING DIAGRAMS
12.1.1 3 Extra Clocks or Double Program
Figure 8 shows the timing for the programming sequence for loading CLKoutX_Y_DIV > 25 or CLKoutX_Y_DDLY > 12 as described
in Section 17.1 SPECIAL PROGRAMMING CASE FOR R0 to R5 for CLKoutX_Y_DIV & CLKoutX_Y_DDLY.
30102307
FIGURE 8. MICROWIRE Timing Diagram: Extra CLKuWire Pulses for R0 to R5
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LMK04800 Family
12.1.2 Three Extra Clocks with LEuWire High
Figure 9 shows the timing for the programming sequence which allows SYNC_EN_AUTO = 1 when loading CLKoutX_Y_DIV > 25
or CLKoutX_Y_DDLY > 12. When SYNC_EN_AUTO = 1, a SYNC event is automatically generated on the falling edge of LEuWire.
See Section 17.1 SPECIAL PROGRAMMING CASE FOR R0 to R5 for CLKoutX_Y_DIV & CLKoutX_Y_DDLY.
30102327
FIGURE 9. MICROWIRE Timing Diagram: Extra CLKuWire Pulses for R0 to R5 with LEuWire Asserted
12.1.3 Readback
See Section 17.3 READBACK for more information on performing a readback operation. Figure 10 shows timing for LEuWire for
both READBACK_LE = 1 and 0.
The rising edges of CLKuWire during MICROWIRE readback continue to clock data on DATAuWire into the device during readback.
If after the readback, LEuWire transitions from low to high, this data will be latched to the decoded register. The decoded register
address consists of the last 5 bits clocked on DATAuWire as shown in the MICROWIRE Timing Diagrams.
30102306
FIGURE 10. MICROWIRE Readback Timing Diagram
23 www.national.com
LMK04800 Family
13.0 Measurement Definitions
13.1 CHARGE PUMP CURRENT SPECIFICATION DEFINITIONS
30102331
I1 = Charge Pump Sink Current at VCPout = VCC - ΔV
I2 = Charge Pump Sink Current at VCPout = VCC/2
I3 = Charge Pump Sink Current at VCPout = ΔV
I4 = Charge Pump Source Current at VCPout = VCC - ΔV
I5 = Charge Pump Source Current at VCPout = VCC/2
I6 = Charge Pump Source Current at VCPout = ΔV
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.
13.1.1 Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage
30102332
13.1.2 Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch
30102333
13.1.3 Charge Pump Output Current Magnitude Variation Vs. Temperature
30102334
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LMK04800 Family
13.2 DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY (Note 28)
The differential voltage of a differential signal can be described by two different definitions causing confusion when reading
datasheets or communicating with other engineers. This section will address the measurement and description of a differential
signal so that the reader will be able to understand and discern between the two different definitions when used.
The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and
non-inverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being
described.
The second definition used to describe a differential signal is to measure the potential of the non-inverting signal with respect to
the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this
signal exist with respect to ground, it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes
with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first description.
Figure 11 illustrates the two different definitions side-by-side for inputs and Figure 12 illustrates the two different definitions side-
by-side for outputs. The VID and VOD definitions show VA and VB DC levels that the non-inverting and inverting signals toggle
between with respect to ground. VSS input and output definitions show that if the inverting signal is considered the voltage potential
reference, the non-inverting signal voltage potential is now increasing and decreasing above and below the non-inverting reference.
Thus the peak-to-peak voltage of the differential signal can be measured.
VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP).
30102375
FIGURE 11. Two Different Definitions for Differential
Input Signals
30102374
FIGURE 12. Two Different Definitions for Differential
Output Signals
Note 28: Refer to application note AN-912 Common Data Transmission Parameters and their Definitions for more information.
25 www.national.com
LMK04800 Family
14.0 Typical Performance Characteristics
14.2 CLOCK OUTPUT AC CHARACTERISTICS
LVDS VOD vs. Frequency
0 500 1000 1500 2000 2500 3000
0
50
100
150
200
250
300
350
400
450
500
VOD (mV)
FREQUENCY (MHz)
30102341
LVPECL /w 240 ohm emitter resistors VOD vs. Frequency
0 500 1000 1500 2000 2500 3000
0
200
400
600
800
1000
1200
VOD (mV)
FREQUENCY (MHz)
2000 mVpp
1600 mVpp
1200 mVpp
700 mVpp
30102342
LVPECL /w 120 ohm emitter resistors VOD vs. Frequency
0 500 1000 1500 2000 2500 3000
0
200
400
600
800
1000
1200
VOD (mV)
FREQUENCY (MHz)
2000 mVpp
1600 mVpp
30102343
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LMK04800 Family
15.0 Features
15.1 SYSTEM ARCHITECTURE
The dual loop PLL architecture of the LMK048xx provides the
lowest jitter performance over the widest range of output fre-
quencies and phase noise integration bandwidths. The first
stage PLL (PLL1) is driven by an external reference clock and
uses an external VCXO or tunable crystal to provide a fre-
quency accurate, low phase noise reference clock for the
second stage frequency multiplication PLL (PLL2). PLL1 typ-
ically uses a narrow loop bandwidth (10 Hz to 200 Hz) to retain
the frequency accuracy of the reference clock input signal
while at the same time suppressing the higher offset frequen-
cy phase noise that the reference clock may have accumu-
lated along its path or from other circuits. This “cleaned”
reference clock provides the reference input to PLL2.
The low phase noise reference provided to PLL2 allows PLL2
to operate with a wide loop bandwidth (50 kHz to 200 kHz).
The loop bandwidth for PLL2 is chosen to take advantage of
the superior high offset frequency phase noise profile of the
internal VCO and the good low offset frequency phase noise
of the reference VCXO or tunable crystal.
Ultra low jitter is achieved by allowing the external VCXO or
Crystal’s phase noise to dominate the final output phase noise
at low offset frequencies and the internal VCO’s phase noise
to dominate the final output phase noise at high offset fre-
quencies. This results in best overall phase noise and jitter
performance.
The LMK048xx allows subsets of the device to be used to
increase the flexibility of device. These different modes are
selected using Section 17.9.1 MODE: Device Mode. For in-
stance:
•Dual Loop Mode - Typical use case of LMK04808. CLKinX
used as reference input to PLL1, OSCin port is connected
to VCXO or tunable crystal.
•Single Loop Mode - Powers down PLL1. OSCin port is
used as reference input.
•Clock Distribution Mode - Allows input of CLKin1 to be
distributed to output with division, digital delay, and analog
delay.
See Functional Description for more information on these
modes.
15.2 PLL1 REDUNDANT REFERENCE INPUTS (CLKin0/
CLKin0* and CLKin1/CLKin1*)
The LMK0480x has two reference clock inputs for PLL1,
CLKin0 and CLKin1. Ref Mux selects CLKin0 or CLKin1. Au-
tomatic or manual switching occurs between the inputs.
CLKin0 and CLKin1 each have input dividers. The input di-
vider allows different clock input frequencies to be normalized
so that the frequency input to the PLL1 R divider remains
constant during automatic switching. By programming these
dividers such that the frequency presented to the input of the
PLL1_R divider is the same prevents the user from needing
to reprogram the PLL1 R divider when the input reference is
changed to another CLKin port with a different frequency.
CLKin1 is shared for use as an external 0-delay feedback
(FBCLKin), or for use with an external VCO (Fin).
Fast manual switching between reference clocks is possible
with a external pins Status_CLKin0 and Status_CLKin1.
15.3 PLL1 TUNABLE CRYSTAL SUPPORT
The LMK048xx integrates a crystal oscillator on PLL1 for use
with an external crystal and varactor diode to perform jitter
cleaning.
The LMK048xx must be programmed to enable Crystal mode.
15.4 VCXO/CRYSTAL BUFFERED OUTPUTS
The LMK048xx provides 2 dedicated outputs which are a
buffered copy of the PLL2 reference input. This reference in-
put is typically a low noise VCXO or Crystal. When using a
VCXO, this output can be used to clock external devices such
as microcontrollers, FPGAs, CPLDs, etc. before the
LMK048xx is programmed.
The OSCout0 buffer output type is programmable to LVDS,
LVPECL, or LVCMOS. The OSCout1 buffer is fixed to
LVPECL.
The dedicated output buffers OSCout0 and OSCout1 can
output frequency lower than the VCXO or Crystal frequency
by programming the OSC Divider. The OSC Divider value
range is 1 to 8. Each OSCoutX can individually choose to use
the OSC Divider output or to bypass the OSC Divider.
Two clock output groups can also be programmed to be driv-
en by OSCin. This allows a total of 4 additional differential
outputs to be buffered outputs of OSCin. When programmed
in this way, a total of 6 differential outputs can be driven by a
buffered copy of OSCin.
VCXO/Crystal buffered outputs cannot be synchronized to
the VCO clock distribution outputs. The assertion of SYNC
will still cause these outputs to become low. Since these out-
puts will turn off and on asynchronously with respect to the
VCO sourced clock outputs during a SYNC, it is possible for
glitches to occur on the buffered clock outputs when SYNC is
asserted and unasserted. If the NO_SYNC_CLKoutX_Y bits
are set these outputs will not be affected by the SYNC event
except that the phase relationship will change with the other
synchronized clocks unless a buffered clock output is used as
a qualification clock during SYNC.
15.5 FREQUENCY HOLDOVER
The LMK048xx supports holdover operation to keep the clock
outputs on frequency with minimum drift when the reference
is lost until a valid reference clock signal is re-established.
15.6 INTEGRATED LOOP FILTER POLES
The LMK048xx features programmable 3rd and 4th order
loop filter poles for PLL2. These internal resistors and capac-
itor values may be selected from a fixed range of values to
achieve either a 3rd or 4th order loop filter response. The in-
tegrated programmable resistors and capacitors compliment
external components mounted near the chip.
These integrated components can be effectively disabled by
programming the integrated resistors and capacitors to their
minimum values.
15.7 INTERNAL VCO
The output of the internal VCO is routed to a mux which allows
the user to select either the direct VCO output or a divided
version of the VCO for the Clock Distribution Path. This same
selection is also fed back to the PLL2 phase detector through
a prescaler and N-divider.
The mux selectable VCO divider has a divide range of 2 to 8
with 50% output duty cycle for both even and odd divide val-
ues.
The primary use of the VCO divider is to achieve divides
greater than the clock output divider supports alone.
27 www.national.com
LMK04800 Family
15.8 EXTERNAL VCO MODE
The Fin/Fin* input allows an external VCO to be used with
PLL2 of the LMK048xx.
Using an external VCO reduces the number of available clock
inputs by one.
15.9 CLOCK DISTRIBUTION
The LMK048xx features a total of 12 outputs driven from the
internal or external VCO.
All VCO driven outputs have programmable output types.
They can be programmed to LVPECL, LVDS, or LVCMOS.
When all distribution outputs are configured for LVCMOS or
single ended LVPECL a total of 24 outputs are available.
If the buffered OSCin outputs OSCout0 and OSCout1 are in-
cluded in the total number of clock outputs the LMK048xx is
able to distribute, then up to 14 differential clocks or up to 28
single ended clocks may be generated with the LMK048xx.
The following sections discuss specific features of the clock
distribution channels that allow the user to control various as-
pects of the output clocks.
15.9.1 CLKout DIVIDER
Each clock group, which is a pair of outputs such as CLKout0
and CLKout1, has a single clock output divider. The divider
supports a divide range of 1 to 1045 (even and odd) with 50%
output duty cycle. When divides of 26 or greater are used, the
divider/delay block uses extended mode.
The VCO Divider may be used to reduce the divide needed
by the clock group divider so that it may operate in normal
mode instead of extended mode. This can result in a small
current saving if enabling the VCO Divider allows 3 or more
clock output divides to change from extended to normal
mode.
15.9.2 CLKout DELAY
The clock distribution section includes both a fine (analog)
and coarse (digital) delay for phase adjustment of the clock
outputs.
The fine (analog) delay allows a nominal 25 ps step size and
range from 0 to 475 ps of total delay. Enabling the analog
delay adds a nominal 500 ps of delay in addition to the pro-
grammed value. When adjusting analog delay, glitches may
occur on the clock outputs being adjusted.
The coarse (digital) delay allows a group of outputs to be de-
layed by 4.5 to 12 clock distribution path cycles in normal
mode, or from 12.5 to 522 VCO cycles in extended mode. The
delay step can be as small as half the period of the clock dis-
tribution path by using the CLKoutX_Y_HS bit. e.g. 2 GHz
VCO frequency without using the VCO divider results in 250
ps coarse tuning steps. The coarse (digital) delay value takes
effect on the clock outputs after a SYNC event.
There are 3 different ways to use the digital (coarse) delay.
1. Fixed Digital Delay
2. Absolute Dynamic Digital Delay
3. Relative Dynamic Digital Delay
These are further discussed in the Functional Description.
15.9.3 PROGRAMMABLE OUTPUT TYPE
For increased flexibility all LMK048xx clock outputs (CLK-
outX) and OSCout0 can be programmed to an LVDS,
LVPECL, or LVCMOS output type. OSCout1 is fixed as
LVPECL.
Any LVPECL output type can be programmed to 700, 1200,
1600, or 2000 mVpp amplitude levels. The 2000 mVpp
LVPECL output type is a National Semiconductor proprietary
configuration that produces a 2000 mVpp differential swing
for compatibility with many data converters and is also known
as 2VPECL.
15.9.4 CLOCK OUTPUT SYNCHRONIZATION
Using the SYNC input causes all active clock outputs to share
a rising edge. See Section 16.9.2 Clock Output Synchroniza-
tion (SYNC) for more information.
The SYNC event also causes the digital delay values to take
effect.
15.10 0-DELAY
The 0-delay mode synchronizes the input clock phase to the
output clock phase. The 0-delay feedback may performed
with an internal feedback loop from any of the clock groups
or with an external feedback loop into the FBCLKin port as
selected by the FEEDBACK_MUX.
Without using 0-delay mode there will be n possible fixed
phase relationships from clock input to clock output depend-
ing on the clock output divide value.
Using an external 0-delay feedback reduces the number of
available clock inputs by one.
15.11 DEFAULT STARTUP CLOCKS
Before the LMK048xx is programmed, CLKout8 is enabled
and operating at a nominal frequency and CLKout6 and OS-
Cout0 are enabled and operating at the OSCin frequency.
These clocks can be used to clock external devices such as
microcontrollers, FPGAs, CPLDs, etc. before the LMK048xx
is programmed.
For CLKout6 and OSCout0 to work before the LMK048xx is
programmed the device must not be using Crystal mode.
15.12 STATUS PINS
The LMK048xx provides status pins which can be monitored
for feedback or in some cases used for input depending upon
device programming. For example:
•The Status_Holdover pin may indicate if the device is in
hold-over mode.
•The Status_CLKin0 pin may indicate the LOS (loss-of-
signal) for CLKin0.
•The Status_CLKin0 pin may be an input for selecting the
active clock input.
•The Status_LD pin may indicate if the device is locked.
The status pins can be programmed to a variety of other out-
puts including analog lock detect, PLL divider outputs, com-
bined PLL lock detect signals, PLL1 Vtune railing, readback,
etc. Refer to the MICROWIRE programming section of this
datasheet for more information. Default pin programming is
captured in Table 16.
15.13 REGISTER READBACK
Programmed registers may be read back using the MI-
CROWIRE interface. For readback one of the status pins
must be programmed for readback mode.
At no time may registers be programed to values other than
the valid states defined in the datasheet.
www.national.com 28
LMK04800 Family
16.0 Functional Description
16.1 FUNCTIONAL OVERVIEW
In default mode of operation, dual PLL mode with internal
VCO, the Phase Frequency Detector in PLL1 compares the
active CLKinX reference divided by CLKinX_PreR_DIV and
PLL1 R divider with the external VCXO or crystal attached to
the PLL2 OSCin port divided by PLL1 N divider. The external
loop filter for PLL1 should be narrow to provide an ultra clean
reference clock from the external VCXO or crystal to the OS-
Cin/OSCin* pins for PLL2.
The Phase Frequency Detector in PLL2 compares the exter-
nal VCXO or crystal attached to the OCSin port divided by the
PLL2 R divider with the output of the internal VCO divided by
the PLL2 N divider and N2 pre-scaler and optionally the VCO
divider. The bandwidth of the external loop filter for PLL2
should be designed to be wide enough to take advantage of
the low in-band phase noise of PLL2 and the low high offset
phase noise of the internal VCO. The VCO output is also
placed on the distribution path for the clock distribution sec-
tion. The clock distribution consists of 6 groups of dividers and
delays which drive 12 outputs. Each clock group allows the
user to select a divide value, a digital delay value, and an
analog delay. The 6 groups drive programmable output
buffers. Two groups allow their input signal to be from the
OSCin port directly.
When a 0-delay mode is used, a clock output will be passed
through the feedback mux to the PLL1 N Divider for synchro-
nization and 0-delay.
When an external VCO mode is used, the Fin port will be used
to input an external VCO signal. PLL2 Phase comparison will
now be with this signal divided by the PLL2 N divider and N2
pre-scaler. The VCO divider may not be used. One less clock
input is available when using an external VCO mode.
When a single PLL mode is used, PLL1 is powered down.
OSCin is used as a reference to PLL2.
16.2 MODE SELECTION
The LMK04800 family is capable of operating in several dif-
ferent modes as programmed by Section 17.9.1 MODE: De-
vice Mode.
TABLE 1. Device Mode Selection
MODE
R11
[31:27]
PLL1 PLL2 PLL2
VCO 0-delay Clock
Dist
0 X X Internal X
2 X X Internal X X
3 X X External X
5 X X External X X
6 X Internal X
8 X Internal X X
11 X External X
16 X
In addition to selecting the device's mode of operation above,
some modes require additional configuration. Also there are
other features including holdover and dynamic digital delay
that can also be enabled.
TABLE 2. Registers to Further Configure Device Mode of
Operation
Register Holdover 0-Delay
Dynamic
Digital
Delay
HOLDOVER_MODE 2 — —
EN_TRACK User — —
DAC_CLK_DIV User — —
EN_MAN_DAC User — —
DISABLE_DLD1_DET User — —
EN_VTUNE_RAIL_
DET User — —
DAC_HIGH_TRIP User — —
DAC_LOW_TRIP User — —
FORCE_HOLDOVER 0 — —
SYNC_EN_AUTO — — User
SYNC_QUAL — — 1
EN_SYNC — — 1
CLKout4_5_PD — — 0
EN_
FEEDBACK_MUX —1 1
FEEDBACK_MUX —Feedback
Clock
Qualifying
Clock
NO_SYNC_
CLKoutX_Y — — User
16.3 INPUTS / OUTPUTS
16.3.1 PLL1 Reference Inputs (CLKin0 and CLKin1)
The reference clock inputs for PLL1 may be selected from
either CLKin0 or CLKin1. The user has the capability to man-
ually select one of the inputs or to configure an automatic
switching mode of operation. See Section 16.4 INPUT
CLOCK SWITCHING for more info.
CLKin0 and CLKin1 have dividers which allow the device to
switch between reference inputs of different frequencies au-
tomatically without needing to reprogram the PLL1 R divider.
The CLKin pre-divider values are 1, 2, 4, and 8.
CLKin1 input can alternatively be used for external feedback
in 0-delay mode (FBCLKin) or for an external VCO input port
(Fin).
16.3.2 PLL2 OSCin / OSCin* Port
The feedback from the external oscillator being locked with
PLL1 drives the OSCin/OSCin* pins. Internally this signal is
routed to the PLL1 N Divider and to the reference input for
PLL2.
This input may be driven with either a single-ended or differ-
ential signal and must be AC coupled. If operated in single
ended mode, the unused input must be connected to GND
with a 0.1 µF capacitor.
16.3.3 CRYSTAL OSCILLATOR
The internal circuitry of the OSCin port also supports the op-
tional implementation of a crystal based oscillator circuit. A
crystal, a varactor diode, and a small number of other external
components may be used to implement the oscillator. The in-
ternal oscillator circuit is enabled by setting the
EN_PLL2_XTAL bit. See Section 17.9.9 EN_PLL2_XTAL.
29 www.national.com
LMK04800 Family
16.4 INPUT CLOCK SWITCHING
Manual, pin select, and automatic are three different kinds
clock input switching modes can be set with the
CLKin_SELECT_MODE register.
Below is information about how the active input clock is se-
lected and what causes a switching event in the various clock
input selection modes.
16.4.1 Input Clock Switching - Manual Mode
When CLKin_SELECT_MODE is 0 or 1 then CLKin0 or
CLKin1 respectively is always selected as the active input
clock. Manual mode will also override the EN_CLKinX bits
such that the CLKinX buffer will operate even if CLKinX is is
disabled with EN_CLKinX = 0.
Entering Holdover
If holdover mode is enabled then holdover mode is entered if:
•Digital lock detect of PLL1 goes low and
DISABLE_DLD1_DET = 0.
Exiting Holdover
The active clock for automatic exit of holdover mode is the
manually selected clock input.
16.4.2 Input Clock Switching - Pin Select Mode
When CLKin_SELECT_MODE is 3, the pins Status_CLKin0
and Status_CLKin1 select which clock input is active.
Clock Switch Event: Pins
Changing the state of Status_CLKin0 or Status_CLKin1 pins
causes an input clock switch event.
Clock Switch Event: PLL1 DLD
To prevent PLL1 DLD high to low transition from causing a
input clock switch event and causing the device to enter
holdover mode, disable the PLL1 DLD detect by setting
DISABLE_DLD1_DET = 1. This is the preferred behavior for
Pin Select Mode.
Configuring Pin Select Mode
The Status_CLKin0_TYPE must be programmed to an input
value for the Status_CLKin0 pin to function as an input for pin
select mode.
The Status_CLKin1_TYPE must be programmed to an input
value for the Status_CLKin1 pin to function as an input for pin
select mode.
If the Status_CLKinX_TYPE is set as output, the input value
is considered "0."
The polarity of Status_CLKin1 and Status_CLKin0 input pins
can be inverted with the CLKin_SEL_INV bit.
Table 3 defines which input clock is active depending on
Status_CLKin0 and Status_CLKin1 state.
TABLE 3. Active Clock Input - Pin Select Mode
Status_CLKin1 Status_CLKin0 Active Clock
0 0 CLKin0
0 1 CLKin1
1 0 Reserved
1 1 Holdover
The pin select mode will override the EN_CLKinX bits such
that the CLKinX buffer will operate even if CLKinX is is dis-
abled with EN_CLKinX = 0. To switch as fast as possible,
keep the clock input buffers enabled (EN_CLKinX = 1) that
could be switched to.
Pin Select Mode and Host
When in the pin select mode, the host can monitor conditions
of the clocking system which could cause the host to switch
the active clock input. The LMK048xx device can also provide
indicators on the Status_LD and Status_HOLDOVER like
"DAC Rail," "PLL1 DLD", "PLL1 & PLL2 DLD" which the host
can use in determining which clock input to use as active clock
input.
Switch Event without Holdover
When an input clock switch event is triggered and holdover
mode is disabled, the active clock input immediately switches
to the selected clock. When PLL1 is designed with a narrow
loop bandwidth, the switching transient is minimized.
Switch Event with Holdover
When an input clock switch event is triggered and holdover
mode is enabled, the device will enter holdover mode and re-
main in holdover until a holdover exit condition is met as
described in Section 16.5 HOLDOVER MODE. Then the de-
vice will complete the reference switch to the pin selected
clock input.
16.4.3 Input Clock Switching - Automatic Mode
When CLKin_SELECT_MODE is 4, the active clock is select-
ed in priority order of enabled clock inputs starting upon an
input clock switch event. The priority order of the clocks is
CLKin0 → CLKin1 → CLKin0, etc.
For a clock input to be eligible to be switched through, it must
be enabled using EN_CLKinX.
Starting Active Clock
Upon programming this mode, the currently active clock re-
mains active if PLL1 lock detect is high. To ensure a particular
clock input is the active clock when starting this mode, pro-
gram CLKin_SELECT_MODE to the manual mode which
selects the desired clock input (CLKin0 or 1). Wait for PLL1
to lock PLL1_DLD = 1, then select this mode with
CLKin_SELECT_MODE = 4.
Clock Switch Event: PLL1 DLD
A loss of lock as indicated by PLL1’s DLD signal (PLL1_DLD
= 0) will cause an input clock switch event if
DISABLE_DLD1_DET = 0. PLL1 DLD must go high
(PLL1_DLD = 1) in between input clock switching events.
Clock Switch Event: PLL1 Vtune Rail
If Vtune_RAIL_DET_EN is set and the PLL1 Vtune voltage
crosses the DAC high or low threshold, holdover mode will be
entered. Since PLL1_DLD = 0 in holdover a clock input
switching event will occur.
Clock Switch Event with Holdover
If holdover is enabled and an input clock switch event occurs,
holdover mode is entered and the active clock is set to the
next enabled clock input in priority order. When the new active
clock meets the holdover exit conditions, holdover is exited
and the active clock will continue to be used as a reference
until another PLL1 loss of lock event. PLL1 DLD must go high
in between input clock switching events.
Clock Switch Event without Holdover
If holdover is not enabled and an input clock switch event oc-
curs, the active clock is set to the next enabled clock in priority
order. The LMK048xx will keep this new input clock as the
active clock until another input clock switching event. PLL1
DLD must go high in between input clock switching events.
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LMK04800 Family
16.4.4 Input Clock Switching - Automatic Mode with Pin
Select
When CLKin_SELECT_MODE is 6, the active clock is select-
ed using the Status_CLKinX pins upon an input clock switch
event according to Table 4.
Starting Active Clock
Upon programming this mode, the currently active clock re-
mains active if PLL1 lock detect is high. To ensure a particular
clock input is the active clock when starting this mode, pro-
gram CLKin_SELECT_MODE to the manual mode which
selects the desired clock input (CLKin0 or 1). Wait for PLL1
to lock PLL1_DLD = 1, then select this mode with
CLKin_SELECT_MODE = 6.
Clock Switch Event: PLL1 DLD
An input clock switch event is generated by a loss of lock as
indicated by PLL1's DLD signal (PLL1 DLD = 0).
Clock Switch Event: PLL1 Vtune Rail
If Vtune_RAIL_DET_EN is set and the PLL1 Vtune voltage
crosses the DAC threshold, holdover mode will be entered.
Since PLL1_DLD = 0 in holdover, a clock input switching
event will occur.
Clock Switch Event with Holdover
If holdover is enabled and an input clock switch event occurs,
holdover mode is entered and the active clock is set to the
clock input defined by the Status_CLKinX pins. When the new
active clock meets the holdover exit conditions, holdover is
exited and the active clock will continue to be used as a ref-
erence until another input clock switch event. PLL1 DLD must
go high in between input clock switching events.
Clock Switch Event without Holdover
If holdover is not enabled and an input clock switch event oc-
curs, the active clock is set to the clock input defined by the
Status_CLKinX pins. The LMK048xx will keep this new input
clock as the active clock until another input clock switching
event. PLL1 DLD must go high in between input clock switch-
ing events.
TABLE 4. Active Clock Input - Auto Pin Mode
Status_CLKin1 Status_CLKin0 Active Clock
X 1 CLKin0
1 0 CLKin1
0 0 Reserved
The polarity of Status_CLKin1 and Status_CLKin0 input pins
can be inverted with the CLKin_SEL_INV bit.
16.5 HOLDOVER MODE
Holdover mode causes PLL2 to stay locked on frequency with
minimal frequency drift when an input clock reference to PLL1
becomes invalid. While in holdover mode, the PLL1 charge
pump is TRI-STATED and a fixed tuning voltage is set on
CPout1 to operate PLL1 in open loop.
Enable holdover
Program Section 17.10.5 HOLDOVER_MODE to enable
holdover mode. Holdover mode can be manually enabled by
programming the FORCE_HOLDOVER bit.
The holdover mode can be set to operate in 2 different sub-
modes.
•Fixed CPout1 (EN_TRACK = 0 or 1, EN_MAN_DAC = 1).
•Tracked CPout1 (EN_TRACK = 1, EN_MAN_DAC = 0).
—Not valid when EN_VTUNE_RAIL_DET = 1.
Updates to the DAC value for the Tracked CPout1 sub-mode
occurs at the rate of the PLL1 phase detector frequency di-
vided by DAC_CLK_DIV. These updates occur any time
EN_TRACK = 1.
The DAC update rate should be programmed for <= 100 kHz
to ensure DAC holdover accuracy.
When tracking is enabled the current voltage of DAC can be
readback, see Section 17.15.1 DAC_CNT.
Entering holdover
The holdover mode is entered as described in Section 16.4
INPUT CLOCK SWITCHING. Typically this is because:
•FORCE_HOLDOVER bit is set.
•PLL1 loses lock according to PLL1_DLD, and
—HOLDOVER_MODE = 2
—DISABLE_DLD1_DET = 0
•CPout1 voltage crosses DAC high or low threshold, and
—HOLDOVER_MODE = 2
—EN_VTUNE_RAIL_DET = 1
—EN_TRACK = 1
—DAC_HIGH_TRIP = User Value
—DAC_LOW_TRIP = User Value
—EN_MAN_DAC = 1
—MAN_DAC = User Value
During holdover
PLL1 is run in open loop mode.
•PLL1 charge pump is set to TRI-STATE.
•PLL1 DLD will be unasserted.
•The HOLDOVER status is asserted
•During holdover If PLL2 was locked prior to entry of
holdover mode, PLL2 DLD will continue to be asserted.
•CPout1 voltage will be set to:
—a voltage set in the MAN_DAC register (fixed CPout1).
—a voltage determined to be the last valid CPout1
voltage (tracked CPout1).
•PLL1 DLD will attempt to lock with the active clock input.
The HOLDOVER status signal can be monitored on the
Status_HOLDOVER or Status_LD pin by programming the
HOLDOVER_MUX or LD_MUX register to "Holdover Status."
Exiting holdover
Holdover mode can be exited in one of two ways.
•Manually, by programming the device from the host.
•Automatically, By a clock operating within a specified ppm
of the current PLL1 frequency on the active clock input.
See Section 16.4 INPUT CLOCK SWITCHING for more
detail on which clock input is active.
31 www.national.com
LMK04800 Family
To exit holdover by programming, set HOLDOVER_MODE =
Disabled. HOLDOVER_MODE can then be re-enabled by
programming HOLDOVER_MODE = Enabled. Care should
be taken to ensure that the active clock upon exiting holdover
is as expected, otherwise the CLKin_SELECT_MODE regis-
ter may need to be re-programmed.
16.5.1 Holdover Frequency Accuracy and DAC
Performance
When in holdover mode PLL1 will run in open loop and the
DAC will set the CPout1 voltage. If Fixed CPout1 mode is
used, then the output of the DAC will be a voltage dependant
upon the MAN_DAC register. If Tracked CPout1 mode is
used, then the output of the DAC will be the voltage at the
CPout1 pin before holdover mode was entered. When using
Tracked mode and EN_MAN_DAC = 1, during holdover the
DAC value is loaded with the programmed value in
MAN_DAC, not the tracked value.
When in Tracked CPout1 mode the DAC has a worst case
tracking error of ±2 LSBs once PLL1 tuning voltage is ac-
quired. The step size is approximately 3.2 mV, therefore the
VCXO frequency error during holdover mode caused by the
DAC tracking accuracy is ±6.4 mV * Kv. Where Kv is the tun-
ing sensitivity of the VCXO in use. Therefore the accuracy of
the system when in holdover mode in ppm is:
30102359
Example: consider a system with a 19.2 MHz clock input, a
153.6 MHz VCXO with a Kv of 17 kHz/V. The accuracy of the
system in holdover in ppm is:
±0.71 ppm = ±6.4 mV * 17 kHz/V * 1e6 / 153.6 MHz
It is important to account for this frequency error when deter-
mining the allowable frequency error window to cause
holdover mode to exit.
16.5.2 Holdover Mode - Automatic Exit of Holdover
The LMK048xx device can be programmed to automatically
exit holdover mode when the accuracy of the frequency on
the active clock input achieves a specified accuracy. The pro-
grammable variables include PLL1_WND_SIZE and
DLD_HOLD_CNT.
See Section 18.6 DIGITAL LOCK DETECT FREQUENCY
ACCURACY to calculate the register values to cause
holdover to automatically exit upon reference signal recovery
to within a user specified ppm error of the holdover frequency.
It is possible for the time to exit holdover to vary because the
condition for automatic holdover exit is for the reference and
feedback signals to have a time/phase error less than a pro-
grammable value. Because it is possible for two clock signals
to be very close in frequency but not close in phase, it may
take a long time for the phases of the clocks to align them-
selves within the allowable time/phase error before holdover
exits.
16.6 PLLs
16.6.1 PLL1
PLL1's maximum phase detector frequency (fPD1) is 40 MHz.
Since a narrow loop bandwidth should be used for PLL1, the
need to operate at high phase detector rate to lower the in-
band phase noise becomes unnecessary. The maximum val-
ues for the PLL1 R and N dividers is 16,383. Charge pump
current ranges from 100 to 1600 µA. PLL1 N divider may be
driven by OSCin port at the OSCout0_MUX output (default)
or by internal or external feedback as selected by Feedback
Mux in 0-delay mode.
Low charge pump currents and phase detector frequencies
aid design of low loop bandwidth loop filters with reasonably
sized components to allow the VCXO or PLL2 to dominate
phase noise inside of PLL2 loop bandwidth. High charge
pump currents may be used by PLL1 when using VCXOs with
leaky tuning voltage inputs to improve system performance.
16.6.2 PLL2
PLL2's maximum phase detector frequency (fPD2) is 155 MHz.
Operating at highest possible phase detector rate will ensure
low in-band phase noise for PLL2 which in turn produces low-
er total jitter. The in-band phase noise from the reference
input and PLL is proportional to N2. The maximum value for
the PLL2 R divider is 4,095. The maximum value for the PLL2
N divider is 262,143. The N2 Prescaler in the total N feedback
path can be programmed for values 2 to 8 (all divides even
and odd). Charge pump current ranges from 100 to 3200 µA.
High charge pump currents help to widen the PLL2 loop
bandwidth to optimize PLL2 performance.
16.6.2.1 PLL2 FREQUENCY DOUBLER
The PLL2 reference input at the OSCin port may be routed
through a frequency doubler before the PLL2 R Divider. The
frequency doubler feature allows the phase comparison fre-
quency to be increased when a relatively low frequency os-
cillator is driving the OSCin port. By doubling the PLL2 phase
detector frequency, the in-band PLL2 noise is reduced by
about 3 dB.
When using the doubler take care to use the PLL2 R Divider
to reduce the phase detector frequency to the limit of the PLL2
maximum phase detector frequency.
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LMK04800 Family
16.6.3 DIGITAL LOCK DETECT
Both PLL1 and PLL2 support digital lock detect. Digital lock
detect compares the phase between the reference path (R)
and the feedback path (N) of the PLL. When the time error,
which is phase error, between the two signals is less than a
specified window size (ε) a lock detect count increments.
When the lock detect count reaches a user specified value
lock detect is asserted true. Once digital lock detect is true, a
single phase comparison outside the specified window will
cause digital lock detect to be asserted false. This is illustrated
in Figure 13.
The incremental lock detect count feature functions as a dig-
ital filter to ensure that lock detect isn't asserted for only a brief
time when the phases of R and N are within the specified tol-
erance for only a brief time during initial phase lock.
The digital lock detect signal can be monitored on the
Status_LD or Status_Holdover pin. The pin may be pro-
grammed to output the status of lock detect for PLL1, PLL2,
or both PLL1 and PLL2.
See Section 18.6 DIGITAL LOCK DETECT FREQUENCY
ACCURACY for more detailed information on programming
the registers to achieve a specified frequency accuracy in
ppm with lock detect.
The digital lock detect feature can also be used with holdover
to automatically exit holdover mode. See Section 16.5
HOLDOVER MODE for more info.
30102328
FIGURE 13. Digital Lock Detect Flowchart
16.7 STATUS PINS
The Status_LD, Status_HOLDOVER, Status_CLKin0,
Status_CLKin1, and SYNC pins can be programmed to out-
put a variety of signals for indicating various statuses like
digital lock detect, holdover, several DAC indicators, and sev-
eral PLL divider outputs.
16.7.1 Logic Low
This is a vary simple output. In combination with the output
_MUX register, this output can be toggled between high and
low. Useful to confirm MICROWIRE programming or as a
general purpose IO.
16.7.2 Digital Lock Detect
PLL1 DLD, PLL2 DLD, and PLL1 + PLL2 are selectable on
certain output pins. See Section 16.6.3 DIGITAL LOCK DE-
TECT for more information.
16.7.3 Holdover Status
Indicates if the device is in Holdover mode. See Section 16.5
HOLDOVER MODE for more information.
16.7.4 DAC
Various flags for the DAC can be monitored including DAC
Locked, DAC Rail, DAC Low, and DAC High.
When the PLL1 tuning voltage crosses the low threshold,
DAC Low is asserted. When PLL1 tuning voltage crosses the
high threshold, DAC High is asserted. When either DAC Low
or DAC High is asserted, DAC Rail will also be asserted.
DAC Locked is asserted when EN_Track = 1 and DAC is
closely tracking the PLL1 tuning voltage.
16.7.5 PLL Divider Outputs
The PLL divider outputs are useful for debugging failure to
lock issues. It allows the user to measure the frequency the
PLL inputs are receiving. The settings of PLL1_R, PLL1_N,
PLL2_R, and PLL2_N output pulses at the phase detector
rate. The settings of PLL1_R / 2, PLL1_N / 2, PLL2_R / 2, and
PLL2_N / 2 output a 50% duty cycle waveform at half the
phase detector rate.
16.7.6 CLKinX_LOS
The clock input loss of signal indicator is asserted when LOS
is enabled (Section 17.12.2 EN_LOS) and the clock no longer
detects an input as defined by the time-out threshold, Sec-
tion 17.12.1 LOS_TIMEOUT.
16.7.7 CLKinX Selected
If this clock is the currently selected/active clock, this pin will
be asserted.
16.7.8 MICROWIRE Readback
The readback data can be output on any pin programmable
to readback mode. For more information on readback see
Section 17.3 READBACK.
16.8 VCO
The integrated VCO uses a frequency calibration routine
when register R30 is programmed to lock VCO to target fre-
quency. Register R30 contains the PLL2_N register.
During the frequency calibration the PLL2_N_CAL value is
used instead of PLL2_N, this allows 0-delay modes to have
a separate PLL2 N value for VCO frequency calibration and
regular operation. See , , and for more information.
33 www.national.com
LMK04800 Family
16.9 CLOCK DISTRIBUTION
16.9.1 Fixed Digital Delay
This section discussing Fixed Digital delay and associated
registers is fundamental to understanding digital delay and
dynamic digital delay.
Clock outputs may be delayed or advanced from one another
by up to 517.5 clock distribution path periods. By program-
ming a digital delay value from 4.5 to 522 clock distribution
path periods, a relative clock output delay from 0 to 517.5
periods is achieved. The CLKoutX_Y_DDLY (5 to 522) and
CLKoutX_Y_HS (-0.5 or 0) registers set the digital delay as
shown in Table 5.
TABLE 5. Possible Digital Delay Values
CLKoutX_Y_DDLY CLKoutX_Y_HS Digital Delay
5 1 4.5
5 0 5
6 1 5.5
6 0 6
7 1 6.5
7 0 7
... ... ...
520 0 520
521 1 520.5
521 0 521
522 1 521.5
522 0 522
Note: Digital delay values only take effect during a SYNC
event and if the NO_SYNC_CLKoutX_Y bit is cleared for this
clock group. See Section 16.9.2 Clock Output Synchroniza-
tion (SYNC) for more information.
The resolution of digital delay is determined by the frequency
of the clock distribution path. The clock distribution path is the
output of Mode Mux1 (Figure 6). The best resolution of digital
delay is achieved by bypassing the VCO divider.
(1)
(2)
The digital delay between clock outputs can be dynamically
adjusted with no or minimum disruption of the output clocks.
See Section 16.9.2.1 DYNAMICALLY PROGRAMMING DIG-
ITAL DELAY for more information.
16.9.1.1 FIXED DIGITAL DELAY - EXAMPLE
Given a VCO frequency of 2949.12 MHz and no VCO divider,
by using digital delay the outputs can be adjusted in 1 / (2 *
2949.12 MHz) = ~169.54 ps steps.
To achieve quadrature (90 degree shift) between the 122.88
MHz outputs on CLKout4 and CLKout6 from a VCO frequency
of 2949.12 MHz and bypassing the VCO divider, consider the
following:
1. The frequency of 122.88 MHz has a period of ~8.14 ns.
2. To delay 90 degrees of a 122.88 MHz clock period
requires a ~2.03 ns delay.
3. Given a digital delay step of ~169.54 ps, this requires a
digital delay value of 12 steps (2.03 ns / 169.54 ns = 12).
4. Since the 12 steps are half period steps,
CLKout6_7_DDLY is programmed 6 full periods beyond
5 for a total of 11.
This result in the following programming:
•Clock output dividers to 24. CLKout4_5_DIV = 24 and
CLKout6_7_DIV = 24.
•Set first clock digital delay value. CLKout4_5_DDLY = 5,
CLKout4_5_HS = 0.
•Set second 90 degree shifted clock digital delay value.
CLKout6_7_DDLY = 11, CLKout6_7_HS = 0.
Table 6 shows some of the possible phase delays in degrees
achievable in the above example.
TABLE 6. Relative phase shift from
CLKout4 & 5 to CLKout6 & 7
CLKout4_5_DDLY = 5 and CLKout4_5_HS = 0
CLKout6_7
_DDLY
CLKout6_7
_HS
Relative
Digital
Delay
Degrees of
122.88 MHz
5 1 -0.5 -7.5°
5 0 0.0 0°
6 1 0.5 7.5°
6 0 1.0 15.0°
7 1 1.5 22.5°
7 0 2.0 30.0°
8 1 2.5 37.5°
8 0 3.0 45.0°
9 1 3.5 52.5°
9 0 4.0 60.0°
10 1 4.5 67.5°
10 0 5.0 75.0°
11 1 5.5 82.5°
11 0 6.0 90.0°
12 1 6.5 97.5°
12 0 7.0 105.0°
13 1 7.5 112.5°
13 0 8.0 120.0°
14 1 8.5 127.5°
... ... ... ...
Figure 15 illustrates clock outputs programmed with different
digital delay values during a SYNC event.
Refer to Section 16.9.2.1 DYNAMICALLY PROGRAMMING
DIGITAL DELAY for more information on dynamically adjust-
ing digital delay.
16.9.2 Clock Output Synchronization (SYNC)
The purpose of the SYNC function is to synchronize the clock
outputs with a fixed and known phase relationship between
each clock output selected for SYNC. SYNC can also be used
to hold the outputs in a low or 0 state. The
NO_SYNC_CLKoutX_Y bits can be set to disable synchro-
nization for a clock group.
To enable SYNC, EN_SYNC must be set. See Section 17.9.2
EN_SYNC, Enable Synchronization.
The digital delay value set by CLKoutX_Y_DDLY takes effect
only upon a SYNC event. The digital delay due to
CLKoutX_Y_HS takes effect immediately upon programming.
See Section 16.9.2.1 DYNAMICALLY PROGRAMMING DIG-
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LMK04800 Family
ITAL DELAY for more information on dynamically changing
digital delay.
During a SYNC event, clock outputs driven by the VCO are
not synchronized to clock outputs driven by OSCin. OSCout0
and OSCout1 are always driven by OSCin. CLKout6, 7, 8, or
9 may be driven by OSCin depending on the
CLKoutX_Y_OSCin_Sel bit value. While SYNC is asserted,
NO_SYNC_CLKoutX_Y operates normally for CLKout6, 7, 8,
and 9 under all circumstances. SYNC operates normally for
CLKout6, 7, 8, and 9 when driven by VCO.
Effect of SYNC
When SYNC is asserted, the outputs to be synchronized are
held in a logic low state. When SYNC is unasserted, the clock
outputs to be synchronized are activated and will transition to
a high state simultaneously with one another except where
different digital delay values have been programmed.
Refer to Section 16.9.2.1 DYNAMICALLY PROGRAMMING
DIGITAL DELAY for SYNC functionality when SYNC_QUAL
= 1.
TABLE 7. Steady State Clock Output Condition
Given Specified Inputs
SYNC_TYPE SYNC_POL
_INV
SYNC Pin Clock
Output State
0,1,2 (Input) 0 0 Active
0,1,2 (Input) 0 1 Low
0,1,2 (Input) 1 0 Low
0,1,2 (Input) 1 1 Active
3, 4, 5, 6
(Output) 0 0 or 1 Active
3, 4, 5, 6
(Output) 1 0 or 1 Low
Methods of Generating SYNC
There are five methods to generate a SYNC event:
•Manual:
—Asserting the SYNC pin according to the polarity set by
SYNC_POL_INV.
—Toggling the SYNC_POL_INV bit though MICROWIRE
will cause a SYNC to be asserted.
•Automatic:
—If PLL1_SYNC_DLD or PLL2_SYNC_DLD is set, the
SYNC pin will be asserted while DLD (digital lock
detect) is false for PLL1 or PLL2 respectively.
—Programming Register R30, which contains PLL2_N
will generate a SYNC event when using the internal
VCO.
—Programming Register R0 through R5 when
SYNC_EN_AUTO = 1.
Note: Due to the speed of the clock distribution path (as fast
as ~325 ps period) and the slow slew rate of the SYNC, the
exact VCO cycle at which the SYNC is asserted or unasserted
by the SYNC is undefined. The timing diagrams show a sharp
transition of the SYNC to clarify functionality.
Avoiding clock output interruption due to SYNC
Any CLKout groups that have their NO_SYNC_CLKoutX_Y
bits set will be unaffected by the SYNC event. It is possible to
perform a SYNC operation with the NO_SYNC_CLKoutX_Y
bits cleared, then set the NO_SYNC_CLKoutX_Y bits so that
the selected clocks will not be affected by a future SYNC. Fu-
ture SYNC events will not effect these clocks but will still
cause the newly synchronized clocks to be re-synchronized
using the currently programmed digital delay values. When
this happens, the phase relationship between the first group
of synchronized clocks and the second group of synchronized
clocks will be undefined unless the SYNC pulse is qualified
by an output clock. See Section 16.9.2.1 DYNAMICALLY
PROGRAMMING DIGITAL DELAY.
SYNC Timing
When discussing the timing of the SYNC function, one cycle
refers to one period of the clock distribution path.
30102304
FIGURE 14. Clock Output synchronization using the
SYNC pin (Active Low)
CLKout0_1_DIV = 1 (valid only for external VCO mode)
CLKout2_3_DIV = 2
CLKout4_5_DIV = 4
The digital delay for all clock outputs is 5
The digital delay half step for all clock outputs is 0
SYNC_QUAL = 0 (No qualification)
Refer to Figure 14 during this discussion on the timing of
SYNC. SYNC must be asserted for greater than one clock
cycle of the clock distribution path to latch the SYNC event.
After SYNC is asserted, the SYNC event is latched on the
rising edge of the distribution path clock, at time A. After this
event has been latched, the outputs will not reflect the low
state for 6 cycles, at time B. Due to the asynchronous nature
of SYNC with respect to the output clocks, it is possible that
a glitch pulse could be created when the clock output goes
low from the SYNC event. This is shown by CLKout4 in Figure
14 and CLKout2 in Figure 15. See Section 16.9.2.1.2 Relative
Dynamic Digital Delay for more information on synchronizing
relative to an output clock to eliminate or minimize this glitch
pulse.
After SYNC becomes unasserted the event is latched on the
following rising edge of the distribution path clock, time C. The
clock outputs will rise at time D, coincident with a rising dis-
tribution clock edge that occurs after 6 cycles plus as many
more cycles as programmed by the digital delay for that clock
output. Therefore, the soonest a clock output will become high
is 11 cycles after the SYNC unassertion event registration,
time C, when the smallest digital delay value of 5 is set. If
CLKoutX_Y_HS = 1 and CLKoutX_Y_DDLY = 5, then the
clock output will rise 10.5 cycles after SYNC is unassertion
event registration.
35 www.national.com
LMK04800 Family
30102305
FIGURE 15. Clock Output synchronization using the
SYNC pin (Active Low)
CLKout0_1_DIV = 2, CLKout0_1_DDLY = 5
CLKout2_3_DIV = 4, CLKout2_3_DDLY = 7
CLKout4_5_DIV = 4, CLKout4_5_DDLY = 8
CLKout0_1_HS = 1
CLKout2_3_HS = 0
CLKout4_5_HS = 0
SYNC_QUAL = 0 (No qualification)
Figure 15 illustrates the timing with different digital delays
programmed.
•Time A) SYNC assertion event is latched.
•Time B) SYNC unassertion latched.
•Time C) All outputs toggle and remain low. A glitch pulse
can occur at this time as shown by CLKout2.
•Time D) After 6 + 4.5 = 10.5 cycles CLKout0 rises. This is
the shortest time from SYNC unassertion registration to
clock rising edge possible.
•Time E) After 6 + 7 = 13 cycles CLKout2 rises. CLKout2
and CLKout4, 5 are programmed for quadrature operation.
•Time F) After 6 + 8 = 14 cycles CLKout4 and 5 rise. Since
CLKout4 and 5 are driven by the same clock divider and
delay circuit, their timing is always the same.
16.9.2.1 DYNAMICALLY PROGRAMMING DIGITAL
DELAY
To use dynamic digital delay synchronization qualification set
SYNC_QUAL = 1. This causes the SYNC pulse to be qualified
by a clock output so that the SYNC event occurs after a spec-
ified time from a clock output transition. This allows the rela-
tive adjustment of clock output phase in real-time with no or
minimum interruption of clock outputs. Hence the term dy-
namic digital delay.
Note that changing the phase of a clock output requires mo-
mentarily altering in the rate of change of the clock output
phase and therefore by definition results in a frequency dis-
tortion of the signal.
Without qualifying the SYNC with an output clock, the newly
synchronized clocks would have a random and unknown dig-
ital delay (or phase) with respect to clock outputs not currently
being synchronized.
Absolute vs. Relative Dynamic Digital Delay
The clock used for qualification of SYNC is selected with the
feedback mux (FEEDBACK_MUX).
If the clock selected by the feedback mux has its
NO_SYNC_CLKoutX_Y = 1, then an absolute dynamic dig-
ital delay adjustment will be performed during a SYNC event
and the digital delay of the feedback clock will not be adjust-
ed.
If the clock selected by the feedback mux has its
NO_SYNC_CLKoutX_Y = 0, then a self-referenced or rela-
tive dynamic digital delay adjustment will be performed
during a SYNC event and the digital delay of the feedback
clock will be adjusted.
Clocks with NO_SYNC_CLKoutX_Y = 1 always operate with-
out interruption.
Dynamic Digital Delay and 0-Delay Mode
When using a 0-delay mode absolute dynamic digital delay
is recommended. Using relative dynamic digital delay with a
0-delay mode may result in a momentary clock loss on the
adjusted clock also being used for 0-delay feedback that may
result in PLL1 DLD becoming low. This may result in
HOLDOVER mode being activated depending upon device
configuration.
SYNC and Minimum Step Size
The minimum step size adjustment for digital delay is half a
clock distribution path cycle. This is achieved by using the
CLKoutX_Y_HS bit. The CLKoutX_Y_HS bit change effect is
immediate without the need for SYNC. To shift digital delay
using CLKoutX_Y_DDLY a SYNC signal must be generated
for the change to take effect.
Programming Overview
To dynamically adjust the digital delay with respect to an ex-
isting clock output the device should be programmed as
follows:
•Set SYNC_QUAL = 1 for clock output qualification.
•Set CLKout4_5_PD = 0. Required for proper operation of
SYNC_QUAL = 1.
•Set EN_FEEDBACK_MUX = 1 to enable the feedback
buffer.
•Set FEEDBACK_MUX to the clock output that the newly
synchronized clocks will be qualified by.
•Set NO_SYNC_CLKoutX_Y = 1 for the output clocks that
will continue to operate during the SYNC event. There is
no interruption of output on these clocks.
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LMK04800 Family
—If FEEDBACK_MUX selects a clock output with
NO_SYNC_CLKoutX_Y = 1, then absolute dynamic
digital delay is performed.
—If FEEDBACK_MUX selects a clock output with
NO_SYNC_CLKoutX_Y = 0, then self-referenced or
relative dynamic digital delay is performed.
•The SYNC_EN_AUTO bit may be set to cause a SYNC
event to begin when register R0 to R5 is programmed. The
auto SYNC feature is a convenience since does not
require the application to manually assert SYNC by
toggling the SYNC_POL_INV bit or the SYNC pin when
changing digital delay. However, under the following
condition a special programming sequence is required if
SYNC_EN_AUTO = 1:
—The CLKoutX_Y_DDLY value being set in the
programmed register is 13 or more.
•Under the following condition a SYNC_EN_AUTO must =
0:
—If the application requires a digital delay resolution of
half a clock distribution path cycle in relative dynamic
digital delay mode because the HS bit must be fixed
per Table 8 for a qualifying clock.
Internal Dynamic Digital Delay Timing
To dynamically adjust digital delay a SYNC must occur. Once
the SYNC is qualified by an output clock, 3 cycles later an
internal one shot pulse will occur. The width of the one shot
pulse is 3 cycles. This internal one shot pulse will cause the
outputs to turn off and then back on with a fixed delay with
respect to the falling edge of the qualification clock. This al-
lows for dynamic adjustments of digital delay with respect to
an output clock.
The qualified SYNC timing is shown in Figure 16 for absolute
dynamic digital delay and Figure 17 for relative dynamic dig-
ital delay.
Other Timing Requirements
When adjusting digital delay dynamically, the falling edge of
the qualifying clock selected by the FEEDBACK_MUX must
coincide with the falling edge of the clock distribution path. For
this requirement to be met, program the CLKoutX_Y_HS val-
ue of the qualifying clock group according to Table 8.
TABLE 8. Half Step programming requirement of
qualifying clock during SYNC event
Distribution Path
Frequency
CLKoutX_Y_DIV
value CLKoutX_Y_HS
≥ 1.8 GHz
Even Must = 1 during
SYNC event.
Odd Must = 0 during
SYNC event.
< 1.8 GHz
Even Must = 0 during
SYNC event.
Odd Must = 1 during
SYNC event.
37 www.national.com
LMK04800 Family
16.9.2.1.1 Absolute Dynamic Digital Delay
Absolute dynamic digital delay can be used to program a
clock output to a specific phase offset from another clock out-
put.
Pros:
•Simple direct phase adjustment with respect to another
clock output.
•CLKoutX_Y_HS will remain constant for qualifying clock.
—Can easily use auto sync feature (SYNC_EN_AUTO =
1) when digital delay adjustment requires half step
digital delay requirements.
•Can be used with 0-delay mode.
Cons:
•For some phase adjustments there may be a glitch pulse
due to SYNC assertion.
—For example see CLKout4 in Figure 14 and CLKout2
in Figure 15.
16.9.2.1.1.1 ABSOLUTE DYNAMIC DIGITAL DELAY -
EXAMPLE
To illustrate the absolute dynamic digital delay adjust proce-
dure, consider the following example.
System Requirements:
•VCO Frequency = 2949.12 MHz
•CLKout0 = 983.04 MHz (CLKout0_1_DIV = 3)
•CLKout2 = 491.52 MHz (CLKout2_3_DIV = 6)
•CLKout4 = 245.76 MHz (CLKout4_5_DIV = 12)
•For all clock outputs during initial programming:
—CLKoutX_Y_DDLY = 5
—CLKoutX_Y_HS = 1
—NO_SYNC_CLKoutX_Y = 0
The application requires the 491.52 MHz clock to be stepped
in 30 degree steps (~169.5 ps), which is the minimum step
resolution allowable by the clock distribution path requiring
use of the half step bit (CLKoutX_Y_HS). That is 1 / 2949.52
MHz / 2 = ~169.5 ps. During the stepping of the 491.52 MHz
clock the 983.04 MHz and 245.76 MHz clock must not be in-
terrupted.
Step 1: The device is programmed from register R0 to R30
with values that result in the device being locked and operat-
ing as desired, see the system requirements above. The
phase of all the output clocks are aligned because all the dig-
ital delay and half step values were the same when the SYNC
was generated by programming register R30. The timing of
this is as shown in Figure 14.
Step 2: Now the registers will be programmed to prepare for
changing digital delay (or phase) dynamically.
TABLE 9. Register Setup for Absolute Dynamic Digital
Delay Example
Register Purpose
SYNC_QUAL = 1
Use a clock output for
qualifying the SYNC pulse for
dynamically adjusting digital
delay.
EN_SYNC = 1 (default) Required for SYNC
functionality.
Register Purpose
CLKout4_5_PD = 0
Required when
SYNC_QUAL = 1.
CLKout4 and/or CLKout5
outputs may be powered
down or in use.
EN_FEEDBACK_MUX = 1
Enable the feedback mux for
SYNC operation for
dynamically adjusting digital
delay.
FEEDBACK_MUX = 2
(CLKout4)
Use the fixed 245.76 MHz
clock as the SYNC
qualification clock.
NO_SYNC_CLKout0_1 = 1
This clock output (983.04
MHz) won't be affected by
SYNC. It will always operate
without interruption.
NO_SYNC_CLKout4_5 = 1
This clock output (245.76
MHz) won't be affected by
SYNC. It will always operate
without interruption.
This clock will also be the
qualifying clock in this
example.
CLKout4_5_HS = 1
Since CLKout4 is the
qualifying clock and
CLKoutX_Y_DIV is even, the
half step bit must be set to 1.
See Table 8.
SYNC_EN_AUTO = 1
Automatic generation of
SYNC is allowed for this
case.
After the registers in Table 9 have been programmed, the ap-
plication may now dynamically adjust the digital delay of
CLKout2 (491.52 MHz).
Step 3: Adjust digital delay of CLKout2.
Refer to Table 10 for the programming values to set a speci-
fied phase offset from the absolute reference clock. Table
10 is dependant upon the qualifying clock divide value of 12,
refer to Section 18.7 CALCULATING DYNAMIC DIGITAL
DELAY VALUES FOR ANY DIVIDE for information on creat-
ing tables for any divide value.
TABLE 10. Programming for
Absolute Digital Delay Adjustment
Degrees of Adjustment
from initial 491.52 MHz
phase
Programming
+/-0 or +/-360 degrees CLKout2_3_DDLY = 7;
CLKout2_3_HS = 1
30 degrees -330 degrees CLKout2_3_DDLY = 7;
CLKout2_3_HS = 0
60 degrees -300 degrees CLKout2_3_DDLY = 8;
CLKout2_3_HS = 1
90 degrees -270 degrees CLKout2_3_DDLY = 8;
CLKout2_3_HS = 0
120 degrees -240 degrees CLKout2_3_DDLY = 9;
CLKout2_3_HS = 1
www.national.com 38
LMK04800 Family
Degrees of Adjustment
from initial 491.52 MHz
phase
Programming
150 degrees -210 degrees CLKout2_3_DDLY = 9;
CLKout2_3_HS = 0
180 degrees -180 degrees CLKout2_3_DDLY = 10;
CLKout2_3_HS = 1
210 degrees -150 degrees CLKout2_3_DDLY = 10;
CLKout2_3_HS = 0
240 degrees -120 degrees CLKout2_3_DDLY = 5;
CLKout2_3_HS = 1
270 degrees -90 degrees CLKout2_3_DDLY = 5;
CLKout2_3_HS = 0
300 degrees -60 degrees CLKout2_3_DDLY = 6;
CLKout2_3_HS = 1
330 degrees -30 degrees CLKout2_3_DDLY = 6;
CLKout2_3_HS = 0
After setting the new digital delay values, the act of program-
ming R1 will start a SYNC automatically because
SYNC_EN_AUTO = 1.
If the user elects to reduce the number of SYNCs because
they are not required when only CLKout2_3_HS is set, then
SYNC_EN_AUTO is = 0 and the SYNC may now be gener-
ated by toggling the SYNC pin or by toggling the
SYNC_POL_INV bit. Because of the internal one shot pulse,
no strict timing of the SYNC pin or SYNC_POL_INV bit is re-
quired.
After the SYNC event, the clock output will adjust according
to Table 10. See Figure 16 for a detailed view of the timing
diagram. The timing diagram critical points are:
•Time A) SYNC assertion event is latched.
•Time B) First qualifying falling clock output edge.
•Time C) Second qualifying falling clock output edge.
•Time D) Internal one shot pulse begins. 5 cycles later clock
outputs will be forced low
•Time E) Internal one shot pulse ends. 5 cycles + digital
delay cycles later the synced clock outputs rise.
•Time F) Clock outputs are forced low. (CLKout2 is already
low).
•Time G) Beginning of digital delay cycles.
•Time H) For CLKout2_3_DDLY = 6; the clock output rises
now.
30102352
FIGURE 16. Absolute Dynamic Digital Delay Programming Example (SYNC_QUAL = 1, Qualify with clock output)
39 www.national.com
LMK04800 Family
16.9.2.1.2 Relative Dynamic Digital Delay
Relative dynamic digital delay can be used to program a clock
output to a specific phase offset from another clock output.
Pros:
•Simple direct phase adjustment with respect to same clock
output.
•The clock output will always behave the same during
digital delay adjustment transient. For some divide values
there will be no glitch pulse.
Cons:
•For some clock divide values there may be a glitch pulse
due to SYNC assertion.
•Adjustments of digital delay requiring the half step bit
(CLKoutX_Y_HS) for finer digital delay adjust is
complicated.
•Use with 0-delay mode may result in PLL1 DLD becoming
low and HOLDOVER mode becoming activated.
—DISABLE_DLD1_DET can be set to prevent
HOLDOVER from becoming activated due to PLL1
DLD becoming low.
16.9.2.1.2.1 RELATIVE DYNAMIC DIGITAL DELAY -
EXAMPLE
To illustrate the relative dynamic digital delay adjust proce-
dure, consider the following example.
System Requirements:
•VCO Frequency = 2949.12 MHz
•CLKout0 = 983.04 MHz (CLKout0_1_DIV = 3)
•CLKout2 = 491.52 MHz (CLKout2_3_DIV = 6)
•CLKout4 = 491.52 MHz (CLKout4_5_DIV = 6)
•For all clock outputs during initial programming:
—CLKoutX_Y_DDLY = 5
—CLKoutX_Y_HS = 0
—NO_SYNC_CLKoutX_Y = 0
The application requires the 491.52 MHz clock to be stepped
in 30 degree steps (~169.5 ps), which is the minimum step
resolution allowable by the clock distribution path. That is 1 /
2949.52 MHz / 2 = ~169.5 ps. During the stepping of the
491.52 MHz clocks the 983.04 MHz clock must not be inter-
rupted.
Step 1: The device is programmed from register R0 to R30
with values that result in the device being locked and operat-
ing as desired, see the system requirements above. The
phase of all the output clocks are aligned because all the dig-
ital delay and half step values were the same when the SYNC
was generated by programming register R30. The timing of
this is as shown in Figure 14.
Step 2: Now the registers will be programmed to prepare for
changing digital delay (or phase) dynamically.
Register Purpose
SYNC_QUAL = 1
Use clock output for
qualifying the SYNC pulse for
dynamically adjusting digital
delay.
EN_SYNC = 1 (default) Required for SYNC
functionality.
Register Purpose
CLKout4_5_PD = 0
Required when
SYNC_QUAL = 1.
CLKout4 and/or CLKout5
outputs may be powered
down or in use.
EN_FEEDBACK_MUX = 1
Enable the feedback mux for
SYNC operation for
dynamically adjusting digital
delay.
FEEDBACK_MUX = 1
(CLKout2)
Use the clock itself as the
SYNC qualification clock.
NO_SYNC_CLKout0_1 = 1
This clock output (983.04
MHz) won't be affected by
SYNC. It will always operate
without interruption.
NO_SYNC_CLKout4_5 = 1
CLKout3’s phase is not to
change with respect to
CLKout0.
SYNC_EN_AUTO = 0
(default)
Automatic generation of
SYNC is not allowed
because of the half step
requirement in relative
dynamic digital delay mode.
SYNC must be generated
manually by toggling the
SYNC_POL_INV bit or the
SYNC pin.
After the above registers have been programmed, the appli-
cation may now dynamically adjust the digital delay of the
491.52 MHz clocks.
Step 3: Adjust digital delay of CLKout2 by one step which is
30 degrees or ~169.5 ps.
Refer to Table 11 for the programming sequence to step one
half clock distribution period forward or backwards. Refer to
Section 18.7 CALCULATING DYNAMIC DIGITAL DELAY
VALUES FOR ANY DIVIDE for more information on how to
calculate digital delay and half step values for other cases.
To fulfill the qualifying clock output half step requirement in
Table 8 when dynamically adjusting digital delay, the
CLKoutX_Y_HS bit must be cleared for clocks with even di-
vides. So before any dynamic digital delay adjustment,
CLKoutX_Y_HS must be clear because the clock divide value
is even. To achieve the final required digital delay adjustment,
the CLKoutX_Y_HS bit may set after SYNC.
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LMK04800 Family
TABLE 11. Programming sequence for one step adjust
Step direction and
current HS state
Programming Sequence
Adjust clock output one step
forward.
CLKout2_3_HS is 0.
1. CLKout2_3_HS = 1.
Adjust clock output one step
forward.
CLKout2_3_HS is 1.
1. CLKout2_3_DDLY = 9.
2. Perform SYNC event.
3. CLKout2_3_HS = 0.
Adjust clock output one step
backward.
CLKout2_3_HS is 0.
1. CLKout2_3_HS = 1.
2. CLKout2_3_DDLY = 5.
3. Perform SYNC event.
Adjust clock output one step
backward.
CLKout2_3_HS is 1.
1. CLKout2_3_HS = 0.
After programing the updated CLKout2_3_DDLY and
CLKout2_3_HS values, perform a SYNC event. The SYNC
may be generated by toggling the SYNC pin or by toggling the
SYNC_POL_INV bit. Because of the internal one shot pulse,
no strict timing of the SYNC pin or SYNC_POL_INV bit is re-
quired. After the SYNC event, the clock output will be at the
specified phase. See Figure 17 for a detailed view of the tim-
ing diagram. The timing diagram critical points are:
•Time A) SYNC assertion event is latched.
•Time B) First qualifying falling clock output edge.
•Time C) Second qualifying falling clock output edge.
•Time D) Internal one shot pulse begins. 5 cycles later clock
outputs will be forced low.
•Time E) Internal one shot pulse ends. 5 cycles + digital
delay cycles later the synced clock outputs rise.
•Time F) Clock outputs are forced low. (CLKouts are
already low).
•Time G) Beginning of digital delay cycles.
•Time H) For CLKout2_3_DDLY = 9; the clock output rises
now.
30102355
FIGURE 17. Relative Dynamic Digital Delay Programming Example, 2nd adjust. (SYNC_QUAL = 1, Qualify with clock
output)
Starting condition is after half step is removed (CLKout2_3_HS = 0).
41 www.national.com
LMK04800 Family
16.9.3 0-Delay Mode
When 0-delay mode is enabled the clock output selected by
the Feedback Mux is connected to the PLL1 N counter to en-
sure a fixed phase relationship between the selected CLKin
and the fed back CLKout. When all the clock outputs are
synced together, all the clock outputs will share the same
fixed phase relationship between the selected CLKin and the
fed back CLKout. The feedback can be internal or external
using FBCLKin port.
When 0-delay mode is enabled the lowest frequency clock
output is fed back to the Feedback Mux to ensure a repeatable
fixed CLKin to CLKout phase relationship between all clock
outputs.
If a clock output that is not the lowest frequency output is se-
lected for feedback, then clocks with lower frequencies will
have an unknown phase relationship with respect the other
clocks and clock input. There will be a number of possible
phase relationships equal to Feedback_Clock_Frequency /
Lower_Clock_Frequency that may occur.
The Feedback Mux selects the even clock output of any clock
group for internal feedback or the FBCLKin port for external
0-delay feedback. The even clock can remain powered down
as long as the CLKoutX_Y_PD bit is = 0 for its clock group.
To use 0-delay mode, the bit EN_FEEDBACK_MUX must be
set (=1) to power up the feedback mux.
See Section 18.2 PLL PROGRAMMING for more information
on programming PLL1_N for 0-delay mode.
When using an external VCO mode, internal 0-delay feed-
back must be used since the FBCLKin port is shared with the
Fin input.
Table 12 outlines several registers to program for 0-delay
mode.
TABLE 12. Programming 0-Delay Mode
Register Purpose
MODE = 2 or 5 Select one of the 0-delay
modes for device.
EN_FEEDBACK_MUX = 1 Enable feedback mux.
FEEDBACK_MUX =
Application Specific
Select CLKout or FBCLKin
for 0-delay feedback.
CLKoutX_Y_DIV
The divide value of the clock
selected by
FEEDBACK_MUX is
important for PLL2 N value
calculation
PLL1_N PLL1_N value used with
CLKoutX_Y_DIV in loop.
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LMK04800 Family
17.0 General Programming
Information
LMK048xx devices are programmed using 32-bit registers.
Each register consists of a 5-bit address field and 27-bit data
field. The address field is formed by bits 0 through 4 (LSBs)
and the data field is formed by bits 5 through 31 (MSBs). The
contents of each register is clocked in MSB first (bit 31), and
the LSB (bit 0) last. During programming, the LEuWire signal
should be held low. The serial data is clocked in on the rising
edge of the CLKuWire signal. After the LSB (bit 0) is clocked
in the LEuWire signal should be toggled low-to-high-to-low to
latch the contents into the register selected in the address
field. It is recommended to program registers in numeric or-
der, for example R0 to R16, and R24 to R31 to achieve proper
device operation. Figure 7 illustrates the serial data timing
sequence.
To achieve proper frequency calibration, the OSCin port must
be driven with a valid signal before programming register R30.
Changes to PLL2 R divider or the OSCin port frequency re-
quire register R30 to be reloaded in order to activate the
frequency calibration process.
17.1 SPECIAL PROGRAMMING CASE FOR R0 to R5 for
CLKoutX_Y_DIV & CLKoutX_Y_DDLY
In some cases when programming register R0 to R5 to
change the CLKoutX_Y_DIV divide value or
CLKoutX_Y_DDLY delay value, 3 additional CLKuWire cy-
cles must occur after loading the register for the newly pro-
grammed divide or delay value to take effect. These special
cases include:
•When CLKoutX_Y_DIV is > 25.
•When CLKoutX_Y_DDLY is > 12. Note, loading the digital
delay value only prepares for a future SYNC event.
Also, since SYNC_EN_AUTO bit = 1 automatically generates
a SYNC on the falling edge of LE when R0 to R5 is pro-
grammed, further programming considerations must be made
when SYNC_EN_AUTO = 1.
These special programming cases requiring the additional
three clock cycles may be properly programmed by one of the
following methods shown in Table 13.
TABLE 13. R0 to R5 Special Case
CLKoutX_Y_DIV &
CLKoutX_Y_DDLY
SYNC
_EN_
AUTO
Programming
Method
CLKoutX_Y_DIV ≤ 25
and
CLKoutX_Y_DDLY ≤ 12
0 or 1 No Additional Clocks
Required (Normal)
CLKoutX_Y_DIV > 25 or
CLKoutX_Y_DDLY > 12 0
Three Extra
CLKuWire Clocks (Or
program another
register)
CLKoutX_Y_DIV > 25 or
CLKoutX_Y_DDLY > 12 1
Three Extra
CLKuWire Clocks
while LEuWire is High
Method: No Additional Clocks Required (Normal)
No special consideration to CLKuWire is required when
changing divide value to ≤ 25, digital delay value to ≤ 12, or
when the digital delay and divide value do not change. See
MICROWIRE timing Figure 7.
Method: Three Extra CLKuWire Clocks
Three extra clocks must be provided before CLKoutX_Y_DIV
> 25 or CLKoutX_Y_DDLY > 12 take effect. See MI-
CROWIRE timing Figure 8.
Also, by programming another register the three clock re-
quirement can be satisfied.
Method: Three Extra CLKuWire Clocks with LEuWire As-
serted
When SYNC_EN_AUTO = 1 the falling edge of LEuWire will
generate a SYNC event. CLKoutX_Y_DIV and
CLKoutX_Y_DDLY values must be updated before the SYNC
event occurs. So 3 CLKuWire rising edges must occur before
LEuWire goes low. See MICROWIRE timing Figure 9.
Initial Programming Sequence
During the recommended programming sequence the device
is programmed in order from R0 to R31, so it is expected at
least one additional register will be programmed after pro-
gramming the last CLKoutX_Y_DIV or CLKoutX_Y_DDLY
value in R0 to R5. This will result in the extra needed
CLKuWire rising edges, so this special note is of little concern.
If programming R0 to R5 to change CLKout frequency or dig-
ital delay or dynamic digital delay at a later time in the appli-
cation, care must be taken to provide these extra CLKuWire
cycles to properly load the new divide and/or delay values.
17.1.1 Example
In this example, all registers have been programmed, the
PLLs are locked. An LMK04808 has been generating a clock
output frequency of 61.44 MHz on CLKout4 using a VCO fre-
quency of 2949.12 MHz and a divide value of 48.
SYNC_EN_AUTO = 0. At a later time the application requires
a 30.72 MHz output on CLKout4. By reprogramming register
R4 with CLKout4_5_DIV = 96 twice, the divide value of 96 is
set for clock outputs 4 and 5 which results in an output fre-
quency of 30.72 MHz (2949.12 MHz / 96 = 30.72 MHz) on
CLKout4.
In this example the required 3 CLKuWire cycles were
achieved by reprogramming the R4 register with the same
value twice.
17.2 RECOMMENDED PROGRAMMING SEQUENCE
Registers are programmed in numeric order with R0 being the
first and R31 being the last register programmed. The rec-
ommended programming sequence involves programming
R0 with the reset bit (b17) set to 1 to ensure the device is in
a default state. If R0 is programmed again, the reset bit must
be cleared to 0 during the programming of R0.
17.2.1 Overview
•Program R0 with RESET bit = 1. This ensures that the
device is configured with default settings. When RESET =
1, all other R0 bits are ignored.
—If R0 is programmed again during the initial
configuration of the device, the RESET bit must be
cleared.
•R0 through R5: CLKouts.
—Program as necessary to configure the clock outputs,
CLKout0 to CLKout11 as desired. These registers
configure clock output controls such as powerdown,
digital delay and divider value, analog delay select, and
clock source select.
•R6 through R8: CLKouts.
—Program as necessary to configure the clock outputs,
CLKout0 to CLKout11 as desired. These registers
43 www.national.com
LMK04800 Family
configure the output format for each clock outputs and
the analog delay for the clock output groups.
•R9: Required programming
—Program this register as shown in the register map for
proper operation.
•R10: OSCouts, VCO divider, and 0-delay.
—Enable and configure clock outputs OSCout0/1.
—Set and select VCO divider (VCO bypass is
recommended).
—Set 0-delay feedback source if used.
•R11: Part mode, SYNC, and XTAL.
—Program to configure the mode of the part, to configure
SYNC functionality and pin, and to enable crystal
mode.
•R12: Pins, SYNC, and holdover mode.
—Status_LD pin, more SYNC options to generate a
SYNC upon PLL1 and/or PLL2 lock detect.
—Enable clock features such as holdover.
•R13: Pins, holdover mode, and CLKins.
—Status_HOLDOVER, Status_CLKin0, and
Status_CLKin1 pin controls.
—Enable clock inputs for use in specific part modes.
•R14: Pins, LOS, CLKins, and DAC.
—Status_CLKin1 pin control.
—Loss of signal detection, CLKin type, DAC rail detect
enable and high and low trip points.
•R15: DAC and holdover mode.
—Program to enable and set the manual DAC value.
—HOLDOVER mode options.
•R16: Crystal amplitude.
—Increasing XTAL_LVL can improve tunable crystal
phase noise performance.
•R24: PLL1 and PLL2.
—PLL1 N and R delay and PLL1 digital lock delay value.
—PLL2 integrated loop filter.
•R25: DAC and PLL1.
—Program to configure DAC update clock divider and
PLL1 digital lock detect count.
•R26: PLL2.
—Program to configure PLL2 options.
•R27: CLKins and PLL1.
—Clock input pre-dividers.
—Program to configure PLL1 options.
•R28: PLL1 and PLL2.
—Program to configure PLL2 R and PLL1 N.
•R29: OSCin and PLL2.
—Program to configure oscillator input frequency, PLL2
fast phase detector frequency mode, and PLL2 N
calibration value.
•R30: PLL2.
—Program to configure PLL2 prescaler and PLL2 N
value.
•R31: uWire lock.
—Program to set the uWire_LOCK bit.
17.3 READBACK
At no time should the MICROWIRE registers be programmed
to any value other than what is specified in the datasheet.
For debug of the MICROWIRE interface, it is recommended
to simply program an output pin mux to active low and then
toggle the output type register between output and inverting
output while observing the output pin for a low to high transi-
tion. For example, to verify MICROWIRE programming, set
the LD_MUX = 0 (Low) and then toggle the LD_TYPE register
between 3 (Output, push-pull) and 4 (Output inverted, push-
pull). The result will be that the Status_LD pin will toggle from
low to high.
Readback from the MICROWIRE programming registers is
available. The MICROWIRE readback function can be en-
abled on the Status_LD, Status_HOLDOVER,
Status_CLKin0, Status_CLKin1, or SYNC pin by program-
ming the corresponding MUX register to “uWire Readback”
and the corresponding TYPE register to "Output (push-pull)."
Power on reset defaults the Status_HOLDOVER pin to “uWire
Readback.”
Figure 10 illustrates the serial data timing sequence for a
readback operation for both cases of READBACK_LE = 0
(POR default) and READBACK_LE = 1.
To perform a readback operation first set the register to be
read back by programming the READBACK_ADDR register.
Then after any MICROWIRE write operation, with the
LEuWire pin held low continue to clock the CLKuWire pin. On
every rising edge of the CLKuWire pin a new data bit is
clocked onto the any pins programmed for uWire Readback.
If the READBACK_LE bit is set, the LEuWire pin should be
left high after LEuWire rising edge while continuing to clock
the CLKuWire pin.
It is allowable to perform a register read back in the same
MICROWIRE operation which set the READBACK_ADDR
register value.
Data is clocked out MSB first. After 27 clocks all the data val-
ues will have been read and the read operation is complete.
If READBACK_LE = 1, the LEuWire line may now be lowered.
It is allowable for the CLKuWire pin to be clocked additional
cycles, but the data on the readback pin will be invalid.
CLKuWire must be low before the falling edge of LEuWire.
17.3.1 Readback - Example
To readback register R3 perform the following steps:
•Write R31 with READBACK_ADDR = 3; READBACK_LE
= 0. DATAuWire and CLKuWire are toggled as shown in
Figure 7 with new data being clocked in on rising edges of
CLKuWire
•Toggle LEuWire high and then low as shown in Figure 7
and Figure 10. LEuWire is returned low because
READBACK_LE = 0.
•Toggle CLKuWire high and then low 27 times to read back
all 27 bits of register R3. Data is read MSB first. Data is
valid on falling edge of CLKuWire.
•Read operation is complete.
17.4 REGISTER MAP AND READBACK REGISTER MAP
Table 14 provides the register map for device programming.
Normally any register can be read from the same data ad-
dress it is written to. However, READBACK_LE has adiffer-
ent readback address. Also, the DAC_CNT register is a read
only register. Table 15 shows the address for
READBACK_LE and DAC_CNT. Bits marked as reserved are
undefined upon readback.
Observe that only the DATA bits are readback during a read-
back which can result in an offset of 5 bits between the two
register tables.
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LMK04800 Family
TABLE 14. Register Map
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data [26:0] Address [4:0]
R0
CLKout
0_1_PD
0
CLKout1_
ADLY_SEL
CLKout0_
ADLY_SEL
CLKout0_1_DDLY [27:18]
RESET
CLKout
0_1_HS
CLKout0_1_DIV [15:5] 0 0 0 0 0
R1
CLKout
2_3_PD
0
CLKout3_
ADLY_SEL
CLKout2_
ADLY_SEL
CLKout2_3_DDLY [27:18]
POWERDOWN
CLKout
2_3_HS
CLKout2_3_DIV [15:5] 0 0 0 0 1
R2
CLKout
4_5_PD
0
CLKout5_
ADLY_SEL
CLKout4_
ADLY_SEL
CLKout4_5_DDLY [27:18] 0
CLKout
4_5_HS
CLKout4_5_DIV [15:5] 0 0 0 1 0
R3
CLKout
6_7_PD
CLKout6_7_
OSCin_Sel
CLKout7_
ADLY_SEL
CLKout6_
ADLY_SEL
CLKout6_7_DDLY [27:18] 0
CLKout
6_7_HS
CLKout6_7_DIV [15:5] 0 0 0 1 1
R4
CLKout
8_9_PD
CLKout8_9_
OSCin_Sel
CLKout9_
ADLY_SEL
CLKout8_
ADLY_SEL
CLKout8_9_DDLY [27:18] 0
CLKout
8_9_HS
CLKout8_9_DIV [15:5] 0 0 1 0 0
R5
CLKout
10_11_PD
0
CLKout11_
ADLY_SEL
CLKout10_
ADLY_SEL
CLKout10_11_DDLY [27:18] 0
CLKout
10_11_HS
CLKout10_11_DIV [15:5] 0 0 1 0 1
R6 CLKout3_TYPE
[31:28]
CLKout2_TYPE
[27:24]
CLKout1_TYPE
[23:20]
CLKout0_TYPE
[19:16]
CLKout2_3_ADLY
[15:11] 0CLKout0_1_ADLY
[9:5] 00110
R7 CLKout7_TYPE
[31:28]
CLKout6_TYPE
[27:24]
CLKout5_TYPE
[23:20]
CLKout4_TYPE
[19:16]
CLKout6_7_ADLY
[15:11] 0CLKout4_5_ADLY
[9:5] 00111
R8 CLKout11_TYPE
[31:28]
CLKout10_TYPE
[27:24]
CLKout9_TYPE
[23:20]
CLKout8_TYPE
[19:16]
CLKout10_11_ADLY
[15:11] 0CLKout8_9_ADLY
[9:5] 01000
R9 0 1010101010101010101010101001001
45 www.national.com
LMK04800 Family
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data [26:0] Address [4:0]
R10
OSCout1
_LVPECL_AMP
[31:30]
01OSCout0_TYPE
[27:24]
EN_OSCout1
EN_OSCout0
OSCout1_MUX
OSCout0_MUX
PD_OSCin
OSCout_DIV
[18:16] 010
VCO_MUX
EN_
FEEDBACK_MUX
VCO_DIV
[10:8]
FEEDBACK
_MUX [7:5] 01010
R11 MODE [31:27]
EN_SYNC
NO_SYNC_CLKout10_11
NO_SYNC_CLKout8_9
NO_SYNC_CLKout6_7
NO_SYNC_CLKout4_5
NO_SYNC_CLKout2_3
NO_SYNC_CLKout0_1
SYNC
_MUX
[19:18]
SYNC_QUAL
SYNC_POL_INV
SYNC_EN_AUTO
SYNC
_TYPE
[14:12]
000000
EN_PLL2_XTAL
01011
R12 LD_MUX [31:27] LD_TYPE
[26:24]
SYNC_PLL2
_DLD
SYNC_PLL1
_DLD
0
(Note 29)
01 1 000000000
EN_TRACK
HOLDOVER
_MODE
[7:6]
101100
R13 HOLDOVER_MUX
[31:27]
HOLDOVER
_TYPE
[26:24]
0
Status_
CLKin1
_MUX
[22:20]
0
Status_
CLKin0
_TYPE
[18:16]
DISABLE_
DLD1_DET
Status_
CLKin0
_MUX
[14:12]
CLKin
_Select
_MODE
[11:8]
CLKin_Sel_INV
0
EN_CLKin1
EN_CLKin0
01101
R14
LOS_
TIMEOUT
[31:30]
0
EN_LOS
0
Status_
CLKin1
_TYPE
[26:24]
0 0
CLKin1_BUF_TYPE
CLKin0_BUF_TYPE
DAC_HIGH_TRIP
[19:14] 0 0 DAC_LOW_TRIP
[11:6]
EN_VTUNE_
RAIL_DET
01110
R15 MAN_DAC
[31:22] 0
EN_MAN_DAC
HOLDOVER_DLD_CNT
[19:6]
FORCE_
HOLDOVER
01111
www.national.com 46
LMK04800 Family
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data [26:0] Address [4:0]
R16 XTAL_
LVL 000001010101010000010000010000
R24 PLL2_C4_LF
[31:28]
PLL2_C3_LF
[27:24] 0PLL2_R4_LF
[22:20] 0PLL2_R3_LF
[18:16] 0PLL1_N_DLY
[14:12] 0PLL1_R_DLY
[10:8]
PLL1_
WND_
SIZE
011000
R25 DAC_CLK_DIV [31:22] 0 0 PLL1_DLD_CNT [19:6] 0 1 1 0 0 1
R26
PLL2_
WND_SIZE
[31:30]
EN_PLL2_
REF_2X
PLL2_
CP_POL
PLL2_CP
_GAIN
[27:26]
111010PLL2_DLD_CNT
[19:6]
PLL2_CP_TRI
11010
R27 0 0 0
PLL1_CP_POL
PLL1_CP_GAIN
0 0
CLKin1_
PreR_DIV
CLKin0_
PreR_DIV
PLL1_R
[19:6]
PLL1_CP_TRI
11011
R28 PLL2_R PLL1_N [19:6] 0 1 1 1 0 0
R29 0 0 0 0 0 OSCin_FREQ
[26:24]
PLL2_
FAST_PDF
PLL2_N_CAL [22:5] 1 1 1 0 1
R30 0 0 0 0 0 PLL2_P 0 PLL2_N [22:5] 1 1 1 1 0
R310000000000
READBACK
_LE
READBACK_ADDR
[20:16] 0000000000
uWire_LOCK
11111
47 www.national.com
LMK04800 Family
TABLE 15. Readback Register Map
Register
RD
26
RD
25
RD
24
RD
23
RD
22
RD
21
RD
20
RD
19
RD
18
RD
17
RD
16
RD
15
RD
14
RD
13
RD
12
RD
11
RD
10
RD
9
RD
8
RD
7
RD
6
RD
5
RD
4
RD
3
RD
2
RD
1
RD
0
Data [26:0]
RD
R12 LD_MUX [26:22] LD_TYPE [21:19]
SYNC_PLL2_DLD
SYNC_PLL1_DLD
READBACK_LE
011000000000
EN_TRACK
HOLDOVER_MODE
[2:1]
1
RD
R23
RESERVED
[26:24] DAC_CNT [23:14] RESERVED [13:0]
RD
R31 RESERVED [26:10]
uWire_LOCK
www.national.com 48
LMK04800 Family
Note 29: Although the value of 0 is written here, during readback the value
of READBACK_LE will be read at this location. See Section 17.4 REGISTER
MAP AND READBACK REGISTER MAP.
17.5 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON RESET
Table 16 illustrates the default register settings programmed in silicon for the LMK048xx after power on or asserting the reset bit.
Capital X and Y represent numeric values.
TABLE 16. Default Device Register Settings after Power On/Reset
Group
Field Name
Default
Value
(decimal)
Default State Field Description Register Bit Location
(MSB:LSB)
Clock Output Control
CLKout0_1_PD 1 PD
Powerdown control for analog and digital
delay, divider, and both output buffers
R0
31
CLKout2_3_PD 1 PD R1
CLKout4_5_PD 1 PD R2
CLKout6_7_PD 0 Normal R3
CLKout8_9_PD 0 Normal R4
CLKout10_11_PD 1 PD R5
CLKout6_7_OSCin_Sel 1 OSCin Selects the clock source for a clock
group from internal VCO or external
OSCin
R3 30
CLKout8_9_OSCin_Sel 0 VCO R4 30
CLKoutX_ADLY_SEL 0 None Add analog delay for clock output R0 to R5 28, 29
CLKoutX_Y_DDLY 0 5 Digital delay value R0 to R5 27:18 [10]
RESET 0 Not in reset Performs power on reset for device R0 17
POWERDOWN 0
Disabled
(device is
active)
Device power down control R1 17
CLKoutX_Y_HS 0 No shift Half shift for digital delay R0 to R5 16
CLKout0_1_DIV 25 Divide-by-25
Divide for clock outputs
R0
15:5 [11]
CLKout2_3_DIV 25 Divide-by-25 R1
CLKout4_5_DIV 25 Divide-by-25 R2
CLKout6_7_DIV 1 Divide-by-1 R3
CLKout8_9_DIV 25 Divide-by-25 R4
CLKout10_11_DIV 25 Divide-by-25 R5
CLKout3_TYPE 0 Powerdown
Individual clock output format. Select
from LVDS/LVPECL/LVCMOS.
R6
31:28 [4]CLKout7_TYPE 0 Powerdown R7
CLKout11_TYPE 0 Powerdown R8
CLKout2_TYPE 0 Powerdown R6
27:24 [4]CLKout6_TYPE 8 LVCMOS
(Norm/Norm) R7
CLKout10_TYPE 0 Powerdown R8
CLKout1_TYPE 0 Powerdown R6
23:20 [4]CLKout5_TYPE 0 Powerdown R7
CLKout9_TYPE 0 Powerdown R8
CLKout0_TYPE 0 Powerdown R6
19:16 [4]CLKout4_TYPE 0 Powerdown R7
CLKout8_TYPE 1 LVDS R8
CLKoutX_Y_ADLY 0 No delay Analog delay setting for clock group R6 to R8 15:11, 9:5 [5]
49 www.national.com
LMK04800 Family
Group
Field Name
Default
Value
(decimal)
Default State Field Description Register Bit Location
(MSB:LSB)
Osc Buffer Control
OSCout1_LVPECL
_AMP 21600 mVpp
LVPECL Set LVPECL amplitude R10 31:30 [2]
OSCout0_TYPE 1 LVDS OSCout0 default clock output R10 27:24 [4]
EN_OSCout1 0 Disabled Disable OSCout1 output buffer R10 23
EN_OSCout0 1 Enabled Enable OSCout0 output buffer R10 22
OSCout1_MUX 0 Bypass Divider Select OSCout divider for OSCout1 or
bypass R10 21
OSCout0_MUX 0 Bypass Divider Select OSCout divider for OSCout0 or
bypass R10 20
PD_OSCin 0 OSCin powered Allows OSCin to be powered down. For
use in clock distribution mode. R10 19
OSCout_DIV 0 Divide-by-8 OSCout divider value R10 18:16 [3]
Mode
VCO_MUX 0 VCO Select VCO or VCO Divider output R10 12
EN_FEEDBACK_MUX 0 Disabled Feedback MUX is powered down. R10 11
VCO_DIV 2 Divide-by-2 VCO Divide value R10 10:8 [3]
FEEDBACK_MUX 0 CLKout0 Selects CLKout to feedback into the
PLL1 N divider R10 7:5 [3]
MODE 0 Internal VCO Device mode R11 31:27 [5]
Clock Synchronization
EN_SYNC 1 Enabled Enables synchronization circuitry. R11 26
NO_SYNC_CLKout10_11 0 Will sync
Disable individual clock groups from
becoming synchronized.
R11 25
NO_SYNC_CLKout8_9 1 Will not sync R11 24
NO_SYNC_CLKout6_7 1 Will not sync R11 23
NO_SYNC_CLKout4_5 0 Will sync R11 22
NO_SYNC_CLKout2_3 0 Will sync R11 21
NO_SYNC_CLKout0_1 0 Will sync R11 20
SYNC_MUX 0 Logic Low Mux controlling SYNC pin when set to
output R11 19:18 [2]
SYNC_QUAL 0 Not qualified Allows SYNC operations to be qualified
by a clock output. R11 17
SYNC_POL_INV 1 Logic Low Sets the polarity of the SYNC pin when
input R11 16
SYNC_EN_AUTO 0 Manual SYNC is not started by programming a
register R0 to R5. R11 15
SYNC_TYPE 1 Input /w
Pull-up SYNC IO pin type R11 14:12 [3]
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LMK04800 Family
Group
Field Name
Default
Value
(decimal)
Default State Field Description Register Bit Location
(MSB:LSB)
Other Mode Control
EN_PLL2_XTAL 0 Disabled Enable Crystal oscillator for OSCin R11 5
LD_MUX 3 PLL1 & 2 DLD Lock detect mux selection when output R12 31:27 [5]
LD_TYPE 3 Output
(Push-Pull) LD IO pin type R12 26:24 [3]
SYNC_PLL2_DLD 0 Normal Force synchronization mode until PLL2
locks R12 23
SYNC_PLL1_DLD 0 Normal Force synchronization mode until PLL1
locks R12 22
EN_TRACK 1 Enable
Tracking DAC tracking of the PLL1 tuning voltage R12 8
HOLDOVER_MODE 2 Enable
Holdover
Causes holdover to activate when lock is
lost R12 7:6 [2]
HOLDOVER_MUX 7 uWire
Readback Holdover mux selection R13 31:27 [5]
HOLDOVER_TYPE 3 Output
(Push-Pull) HOLDOVER IO pin type R13 26:24 [3]
Status_CLKin1_MUX 0 Logic Low Status_CLKin1 pin MUX selection R13 22:20 [3]
Status_CLKin0_TYPE 2 Input /w Pull-
down Status_CLKin0 IO pin type R13 18:16 [3]
DISABLE_DLD1_DET 0 Not Disabled
Disables PLL1 DLD falling edge from
causing HOLDOVER mode to be
entered
R13 15
Status_CLKin0_MUX 0 Logic Low Status_CLKin0 pin MUX selection R13 14:12 [3]
CLKin_SELECT_MODE 3 Manual Select Mode to use in determining reference
CLKin for PLL1 R13 11:9 [3]
CLKin_Sel_INV 0 Active High Invert Status 0 and 1 pin polarity for input R13 8
CLKin Control
EN_CLKin1 1 Usable Set CLKin1 to be usable R13 6
EN_CLKin0 1 Usable Set CLKin0 to be usable R13 5
LOS_TIMEOUT 0 1200 ns, 420
kHz
Time until no activity on CLKin asserts
LOS R14 31:30 [2]
EN_LOS 1 Enabled Loss of Signal Detect at CLKin R14 28
Status_CLKin1_TYPE 2 Input /w Pull-
down Status_CLKin1 pin IO pin type R14 26:24 [3]
CLKin1_BUF_TYPE 0 Bipolar CLKin1 Buffer Type R14 21
CLKin0_BUF_TYPE 0 Bipolar CLKin0 Buffer Type R14 20
DAC Control
DAC_HIGH_TRIP 0 ~50 mV from
Vcc
Voltage from Vcc at which holdover
mode is entered if
EN_VTUNE_RAIL_DAC is enabled.
R14 19:14 [6]
DAC_LOW_TRIP 0 ~50 mV from
GND
Voltage from GND at which holdover
mode is entered if
EN_VTUNE_RAIL_DAC is enabled.
R14 11:6 [6]
EN_VTUNE_RAIL_DET 0 Disabled Enable PLL1 unlock state when DAC trip
points are achieved R14 5
MAN_DAC 512 3 V / 2
Writing to this register will set the value
for DAC when in manual override.
Readback from this register is DAC
value.
R15 31:22 [10]
EN_MAN_DAC 0 Disabled Set manual DAC override R15 20
51 www.national.com
LMK04800 Family
Group
Field Name
Default
Value
(decimal)
Default State Field Description Register Bit Location
(MSB:LSB)
HOLDOVER_DLD_CNT 512 512 counts
Lock must be valid n many clocks of
PLL1 PDF before holdover mode is
exited.
R15 19:6 [14]
FORCE_HOLDOVER 0 Holdover not
forced Forces holdover mode. R15 5
XTAL_LVL 0 1.65 Vpp Sets drive power level of Crystal R16 31:30 [2]
PLL Control
PLL2_C4_LF 0 10 pF PLL2 integrated capacitor C4 value R24 31:28 [4]
PLL2_C3_LF 0 10 pF PLL2 integrated capacitor C3 value R24 27:24 [4]
PLL2_R4_LF 0 200 Ω PLL2 integrated resistor R4 value R24 22:20 [3]
PLL2_R3_LF 0 200 Ω PLL2 integrated resistor R3 value R24 18:16 [3]
PLL1_N_DLY 0 No delay Delay in PLL1 feedback path to
decrease lag from input to output R24 14:12 [3]
PLL1_R_DLY 0 No delay Delay in PLL1 reference path to increase
lag from input to output R24 10:8 [3]
PLL1_WND_SIZE 3 40 ns Window size used for digital lock detect
for PLL1 R24 7:6 [2]
DAC_CLK_DIV 4 Divide-by-4 DAC update clock divisor. Divides PLL1
phase detector frequency. R25 31:22 [10]
PLL1_DLD_CNT 1024 1024 cycles Lock must be valid n many cycles before
LD is asserted R25 19:6 [14]
PLL2_WND_SIZE 0 Reserved
(Note 30)
Window size used for digital lock detect
for PLL2 R26 31:30 [2]
EN_PLL2_REF_2X 0 Disabled, 1x Doubles reference frequency of PLL2. R26 29
PLL2_CP_POL 0 Negative Polarity of PLL2 Charge Pump R26 28
PLL2_CP_GAIN 3 3.2 mA PLL2 Charge Pump Gain R26 27:26 [2]
PLL2_DLD_CNT 8192 8192 Counts
Number of PDF cycles which phase
error must be within DLD window before
LD state is asserted.
R26 19:6 [14]
PLL2_CP_TRI 0 Active PLL2 Charge Pump Active R26 5
PLL1_CP_POL 1 Positive Polarity of PLL1 Charge Pump R27 28
PLL1_CP_GAIN 0 100 uA PLL1 Charge Pump Gain R27 27:26 [2]
CLKin1_PreR_DIV 0 Divide-by-1 CLKin1 Pre-R divide value (1, 2, 4, or 8) R27 23:22 [2]
CLKin0_PreR_DIV 0 Divide-by-1 CLKin0 Pre-R divide value (1, 2, 4, or 8) R27 21:20 [2]
PLL1_R 96 Divide-by-96 PLL1 R Divider (1 to 16383) R27 19:6 [14]
PLL1_CP_TRI 0 Active PLL1 Charge Pump Active R27 5
PLL2_R 4 Divide-by-4 PLL2 R Divider (1 to 4095) R28 31:20 [12]
PLL1_N 192 Divide-by-192 PLL1 N Divider (1 to 16383) R28 19:6 [14]
OSCin_FREQ 7 448 to 511 MHz OSCin frequency range R29 26:24 [3]
PLL2_FAST_PDF 1 PLL2 PDF >
100 MHz
When set, PLL2 PDF of greater than 100
MHz may be used R29 23
PLL2_N_CAL 48 Divide-by-48 Must be programmed to PLL2_N value. R29 22:5 [18]
PLL2_P 2 Divide-by-2 PLL2 N Divider Prescaler (2 to 8) R30 26:24 [3]
PLL2_N 48 Divide-by-48 PLL2 N Divider (1 to 262143) R30 22:5 [18]
READBACK_LE 0 LEuWire Low
for Readback
State LEuWire pin must be in for
readback R31 21
READBACK_ADDR 31 Register 31 Register to read back R31 20:16 [5]
uWire_LOCK 0 Writable The values of registers R0 to R30 are
lockable R31 5
Note 30: This register must be reprogrammed to a value of 2 (3.7 ns) during user programming.
www.national.com 52
LMK04800 Family
17.6 REGISTER R0 TO R5
Registers R0 through R5 control the 12 clock outputs CLK-
out0 to CLKout11. Register R0 controls CLKout0 and CLK-
out1, Register R1 controls CLKout2 and CLKout3, and so on.
All functions of the bits in these six registers are identical ex-
cept the different registers control different clock outputs. The
X and Y in CLKoutX_Y_PD, CLKoutX_ADLY_SEL,
CLKoutY_ADLY_SEL, CLKoutX_Y_DDLY, CLKoutX_Y_HS,
CLKoutX_Y_DIV denote the actual clock output which may
be from 0 to 11 where X is even and Y is odd. Two clock
outputs CLKoutX and CLKoutY form a clock output group and
are often run together in bit names as CLKoutX_Y.
The RESET bit is only in register R0.
The POWERDOWN bit is only in register R1.
The CLKoutX_Y_OSCin_Sel bit is only in registers R3 and
R4.
17.6.1 CLKoutX_Y_PD, Powerdown CLKoutX_Y Output
Path
This bit powers down the clock group as specified by CLKoutX
and CLKoutY. This includes the divider, digital delay, analog
delay, and output buffers.
CLKoutX_Y_PD
R0-R5[31] State
0 Power up clock group
1 Power down clock group
17.6.2 CLKoutX_Y_OSCin_Sel, Clock group source
This bit sets the source for the clock output group CLKoutX_Y.
The selected source will be either from a VCO via Mode Mux1
or from the OSCin buffer.
This bit is valid only for registers R3 and R4, clock groups
CLKout6_7 and CLKout8_9 respectively. All other clock out-
put groups are driven by a VCO via Mode Mux1.
CLKoutX_Y_OSCin_Sel
R3-R4[30] Clock group source
0 VCO
1 OSCin
17.6.3 CLKoutY_ADLY_SEL[29], CLKoutX_ADLY_SEL
[28], Select Analog Delay
These bits individually select the analog delay block (Sec-
tion 17.7.2 CLKoutX_Y_ADLY) for use with CLKoutX or CLK-
outY. It is not required for both outputs of a clock output group
to use analog delay, but if both outputs do select the analog
delay block, then the analog delay will be the same for each
output, CLKoutX and CLKoutY. When neither clock output
uses analog delay, the analog delay block is powered down.
CLKoutY_ADLY_SEL[29], CLKoutX_ADLY_SEL[28]
R0-R5[29] R0-R5[28] State
0 0 Analog delay powered down
0 1 Analog delay on even
CLKoutX
1 0 Analog delay on odd
CLKoutY
1 1 Analog delay on both
CLKouts
17.6.4 CLKoutX_Y_DDLY, Clock Channel Digital Delay
CLKoutX_Y_DDLY and CLKoutX_Y_HS sets the digital delay
used for CLKoutX and CLKoutY. This value only takes effect
during a SYNC event and if the NO_SYNC_CLKoutX_Y bit is
cleared for this clock group. See Section 16.9.2 Clock Output
Synchronization (SYNC).
Programming CLKoutX_Y_DDLY can require special atten-
tion. See section Section 17.1 SPECIAL PROGRAMMING
CASE FOR R0 to R5 for CLKoutX_Y_DIV &
CLKoutX_Y_DDLY for more details.
Using a CLKoutX_Y_DDLY value of 13 or greater will cause
the clock group to operate in extended mode regardless of
the clock group's divide value or the half step value.
One clock cycle is equal to the period of the clock distribution
path. The period of the clock distribution path is equal to VCO
Divider value divided by the frequency of the VCO. If the VCO
divider is disabled or an external VCO is used, the VCO divide
value is treated as 1.
tclock distribution path = VCO divide value / fVCO
CLKoutX_Y_DDLY, 10 bits
R0-R5[27:18] Delay Power Mode
0 (0x00) 5 clock cycles
Normal Mode
1 (0x01) 5 clock cycles
2 (0x02) 5 clock cycles
3 (0x03) 5 clock cycles
4 (0x04) 5 clock cycles
5 (0x05) 5 clock cycles
6 (0x06) 6 clock cycles
7 (0x07) 7 clock cycles
... ...
12 (0x0C) 12 clock cycles
13 (0x0D) 13 clock cycles
Extended
Mode
... ...
520 (0x208) 520 clock cycles
521 (0x209) 521 clock cycles
522 (0x20A) 522 clock cycles
17.6.5 RESET
The RESET bit is located in register R0 only. Setting this bit
will cause the silicon default values to be loaded. When pro-
gramming register R0 with the RESET bit set, all other pro-
grammed values are ignored. After resetting the device, the
register R0 must be programmed again (with RESET = 0) to
set non-default values in register R0.
The reset occurs on the falling edge of the LEuWire pin which
loaded R0 with RESET = 1.
The RESET bit is automatically cleared upon writing any other
register. For instance, when R0 is written to again with default
values.
RESET
R0[17] State
0 Normal operation
1Reset (automatically cleared)
53 www.national.com
LMK04800 Family
17.6.6 POWERDOWN
The POWERDOWN bit is located in register R1 only. Setting
the bit causes the device to enter powerdown mode. Normal
operation is resumed by clearing this bit with MICROWIRE.
POWERDOWN
R1[17] State
0 Normal operation
1 Powerdown
17.6.7 CLKoutX_Y_HS, Digital Delay Half Shift
This bit subtracts a half clock cycle of the clock distribution
path period to the digital delay of CLKoutX and CLKoutY.
CLKoutX_Y_HS is used together with CLKoutX_Y_DDLY to
set the digital delay value.
When changing CLKoutX_Y_HS, the digital delay immedi-
ately takes effect without a SYNC event.
CLKoutX_Y_HS
R0-R5[16] State
0 Normal
1
Subtract half of a clock
distribution path period from
the total digital delay
17.6.8 CLKoutX_Y_DIV, Clock Output Divide
CLKoutX_Y_DIV sets the divide value for the clock group.
The divide may be even or odd. Both even and odd divides
output a 50% duty cycle clock.
Using a divide value of 26 or greater will cause the clock group
to operate in extended mode regardless of the clock group's
digital delay value.
Programming CLKoutX_Y_DIV can require special attention.
See section Section 17.1 SPECIAL PROGRAMMING CASE
FOR R0 to R5 for CLKoutX_Y_DIV & CLKoutX_Y_DDLY for
more details.
CLKoutX_Y_DIV, 11 bits
R0-R5[15:5] Divide Value Power Mode
0 (0x00) Reserved
Normal Mode
1 (0x01) 1 (Note 31)
2 (0x02) 2 (Note 32)
3 (0x03) 3
4 (0x04) 4 (Note 32)
5 (0x05) 5 (Note 32)
6 (0x06) 6
... ...
24 (0x18) 24
25 (0x19) 25
26 (0x1A) 26
Extended Mode
27 (0x1B) 27
... ...
1044 (0x414) 1044
1045 (0x415) 1045
Note 31: CLKoutX_Y_HS must = 0 for divide by 1.
Note 32: After programming PLL2_N value, a SYNC must occur on
channels using this divide value. Programming PLL2_N does generate a
SYNC event automatically which satisfies this requirement, but
NO_SYNC_CLKoutX_Y must be set to 0 for these clock groups.
17.7 REGISTERS R6 TO R8
Registers R6 to R8 set the clock output types and analog de-
lays.
17.7.1 CLKoutX_TYPE
The clock output types of the LMK048xx are individually pro-
grammable. The CLKoutX_TYPE registers set the output
type of an individual clock output to LVDS, LVPECL, LVC-
MOS, or powers down the output buffer. Note that LVPECL
supports four different amplitude levels and LVCMOS sup-
ports single LVCMOS outputs, inverted, and normal polarity
of each output pin for maximum flexibility.
The programming addresses table shows at what register and
address the specified clock output CLKoutX_TYPE register is
located.
The CLKoutX_TYPE table shows the programming definition
for these registers.
CLKoutX_TYPE Programming Addresses
CLKoutX Programming Address
CLKout0 R6[19:16]
CLKout1 R6[23:20]
CLKout2 R6[27:24]
CLKout3 R6[31:28]
CLKout4 R7[19:16]
CLKout5 R7[23:20]
CLKout6 R7[27:24]
CLKout7 R7[31:28]
CLKout8 R8[19:16]
CLKout9 R8[23:20]
CLKout10 R8[27:24]
CLKout11 R8[31:28]
CLKoutX_TYPE, 4 bits
R6-R8[31:28, 27:24, 23:20] Definition
0 (0x00) Power down
1 (0x01) LVDS
2 (0x02) LVPECL (700 mVpp)
3 (0x03) LVPECL (1200 mVpp)
4 (0x04) LVPECL (1600 mVpp)
5 (0x05) LVPECL (2000 mVpp)
6 (0x06) LVCMOS (Norm/Inv)
7 (0x07) LVCMOS (Inv/Norm)
8 (0x08) LVCMOS (Norm/Norm)
9 (0x09) LVCMOS (Inv/Inv)
10 (0x0A) LVCMOS (Low/Norm)
11 (0x0A) LVCMOS (Low/Inv)
12 (0x0C) LVCMOS (Norm/Low)
13 (0x0D) LVCMOS (Inv/Low)
14 (0x0E) LVCMOS (Low/Low)
www.national.com 54
LMK04800 Family
17.7.2 CLKoutX_Y_ADLY
These registers control the analog delay of the clock group
CLKoutX_Y. Adding analog delay to the output will increase
the noise floor of the output. For this analog delay to be active
for a clock output, it must be selected with CLKout(X or Y)
_ADL_SEL. If neither clock output in a clock group selects the
analog delay, then the analog delay block is powered down.
In addition to the programmed delay, a fixed 500 ps of delay
will be added by engaging the delay block.
The programming addresses table shows at what register and
address the specified clock output CLKoutX_Y_ADLY regis-
ter is located.
The CLKoutX_Y_ADLY table shows the programming defini-
tion for these registers.
CLKoutX_Y_ADLY Programming Addresses
CLKoutX_Y_ADLY Programming Address
CLKout0_1_ADLY R6[9:5]
CLKout2_3_ADLY R6[15:11]
CLKout4_5_ADLY R7[9:5]
CLKout6_7_ADLY R7[15:11]
CLKout8_9_ADLY R8[9:5]
CLKout10_11_ADLY R8[15:11]
CLKoutX_Y_ADLY, 5 bits
R6-R8[15:11, 9:5] Definition
0 (0x00) 500 ps + No delay
1 (0x01) 500 ps + 25 ps
R6-R8[15:11, 9:5] Definition
2 (0x02) 500 ps + 50 ps
3 (0x03) 500 ps + 75 ps
4 (0x04) 500 ps + 100 ps
5 (0x05) 500 ps + 125 ps
6 (0x06) 500 ps + 150 ps
7 (0x07) 500 ps + 175 ps
8 (0x08) 500 ps + 200 ps
9 (0x09) 500 ps + 225 ps
10 (0x0A) 500 ps + 250 ps
11 (0x0B) 500 ps + 275 ps
12 (0x0C) 500 ps + 300 ps
13 (0x0D) 500 ps + 325 ps
14 (0x0E) 500 ps + 350 ps
15 (0x0F) 500 ps + 375 ps
16 (0x10) 500 ps + 400 ps
17 (0x11) 500 ps + 425 ps
18 (0x12) 500 ps + 450 ps
19 (0x13) 500 ps + 475 ps
20 (0x14) 500 ps + 500 ps
21 (0x15) 500 ps + 525 ps
22 (0x16) 500 ps + 550 ps
23 (0x17) 500 ps + 575 ps
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LMK04800 Family
17.8 REGISTER R10
17.8.1 OSCout1_LVPECL_AMP, LVPECL Output
Amplitude Control
The OSCout1 clock output can only be used as an LVPECL
output type. OSCout1_LVPECL_AMP sets the LVPECL out-
put amplitude of the OSCout1 clock output.
OSCout1_LVPECL_AMP, 2 bits
R10[31:30] Output Format
0 (0x00) LVPECL (700 mVpp)
1 (0x01) LVPECL (1200 mVpp)
2 (0x02) LVPECL (1600 mVpp)
3 (0x03) LVPECL (2000 mVpp)
17.8.2 OSCout0_TYPE
The OSCout0 clock output has a programmable output type.
The OSCout0_TYPE register sets the output type to LVDS,
LVPECL, LVCMOS, or powers down the output buffer. Note
that LVPECL supports four different amplitude levels and
LVCMOS supports dual and single LVCMOS outputs with in-
verted, and normal polarity of each output pin for maximum
flexibility.
To turn on the output, the OSCout0_TYPE must be set to a
non-power down setting and enabled with Section 17.8.3
EN_OSCoutX, OSCout Output Enable.
OSCout0_TYPE, 4 bits
R10[27:24] Definition
0 (0x00) Powerdown
1 (0x01) LVDS
2 (0x02) LVPECL (700 mVpp)
3 (0x03) LVPECL (1200 mVpp)
R10[27:24] Definition
4 (0x04) LVPECL (1600 mVpp)
5 (0x05) LVPECL (2000 mVpp)
6 (0x06) LVCMOS (Norm/Inv)
7 (0x07) LVCMOS (Inv/Norm)
8 (0x08) LVCMOS (Norm/Norm)
9 (0x09) LVCMOS (Inv/Inv)
10 (0x0A) LVCMOS (Low/Norm)
11 (0x0B) LVCMOS (Low/Inv)
12 (0x0C) LVCMOS (Norm/Low)
13 (0x0D) LVCMOS (Inv/Low)
14 (0x0E) LVCMOS (Low/Low)
17.8.3 EN_OSCoutX, OSCout Output Enable
EN_OSCoutX is used to enable an oscillator buffered output.
EN_OSCout1
R10[23] Output State
0 OSCout1 Disabled
1 OSCout1 Enabled
EN_OSCout0
R10[22] Output State
0 OSCout0 Disabled
1 OSCout0 Enabled
OSCout0 note: In addition to enabling the output with EN_OS-
Cout0. The OSCout0_TYPE must be programmed to a non-
power down value for the output buffer to power up.
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LMK04800 Family
17.8.4 OSCoutX_MUX, Clock Output Mux
Sets OSCoutX buffer to output a divided or bypassed OSCin
signal. The divisor is set by Section 17.8.6 OSCout_DIV, Os-
cillator Output Divide.
OSCout1_MUX
R10[21] Mux Output
0 Bypass divider
1 Divided
OSCout0_MUX
R10[20] Mux Output
0 Bypass divider
1 Divided
17.8.5 PD_OSCin, OSCin Powerdown Control
Except in clock distribution mode, the OSCin buffer must al-
ways be powered up.
In clock distribution mode, the OSCin buffer must be powered
down if not used.
PD_OSCin
R10[19] OSCin Buffer
0 Normal Operation
1 Powerdown
17.8.6 OSCout_DIV, Oscillator Output Divide
The OSCout divider can be programmed from 2 to 8. Divide
by 1 is achieved by bypassing the divider with Section 17.8.4
OSCoutX_MUX, Clock Output Mux.
Note that OSCout_DIV will be in the PLL1 N feedback path if
OSCout0_MUX selects divided as an output. When
OSCout_DIV is in the PLL1 N feedback path, the
OSCout_DIV divide value must be accounted for when pro-
gramming PLL1 N.
See Section 18.2 PLL PROGRAMMING for more information
on programming PLL1 to lock.
OSCout_DIV, 3 bits
R10[18:16] Divide
0 (0x00) 8
1 (0x01) 2
2 (0x02) 2
3 (0x03) 3
4 (0x04) 4
5 (0x05) 5
6 (0x06) 6
7 (0x07) 7
17.8.7 VCO_MUX
When the internal VCO is used, the VCO divider can be se-
lected to divide the VCO output frequency to reduce the
frequency on the clock distribution path. It is recommended
to use the VCO directly unless:
•Very low output frequencies are required.
•If using the VCO divider results in three or more clock
output divider/delays changing from extended to normal
power mode, a small power savings may be achieved by
using the VCO divider.
A consequence of using the VCO divider is a small degrada-
tion in phase noise.
VCO_MUX
R10[12] Divide
0 VCO selected
1 VCO divider selected
17.8.8 EN_FEEDBACK_MUX
When using 0-delay or dynamic digital delay (SYNC_QUAL
= 1), EN_FEEDBACK_MUX must be set to 1 to power up the
feedback mux.
EN_FEEDBACK_MUX
R10[11] Divide
0Feedback mux powered
down
1 Feedback mux enabled
17.8.9 VCO_DIV, VCO Divider
Divide value of the VCO Divider.
See Section 18.2 PLL PROGRAMMING for more information
on programming PLL2 to lock.
VCO_DIV, 3 bits
R10[10:8] Divide
0 (0x00) 8
1 (0x01) 2
2 (0x02) 2
3 (0x03) 3
4 (0x04) 4
5 (0x05) 5
6 (0x06) 6
7 (0x07) 7
17.8.10 FEEDBACK_MUX
When in 0-delay mode, the feedback mux selects the clock
output to be fed back into the PLL1 N Divider.
FEEDBACK_MUX, 3 bits
R10[7:5] Divide
0 (0x00) CLKout0
1 (0x01) CLKout2
2 (0x02) CLKout4
3 (0x03) CLKout6
4 (0x04) CLKout8
5 (0x05) CLKout10
6 (0x06) FBCLKin/FBCLKin*
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LMK04800 Family
17.9 REGISTER R11
17.9.1 MODE: Device Mode
MODE determines how the LMK04800 operates from a high
level. Different blocks of the device can be powered up and
down for specific application requirements from a dual loop
architecture to clock distribution.
The LMK04800 can operate in:
•Dual PLL mode with the internal VCO or an external VCO.
•Single PLL mode uses PLL2 and powers down PLL1.
OSCin is used for PLL reference input.
•Clock Distribution mode allows use of CLKin1 to distribute
to clock outputs CLKout0 through CLKout11, and OSCin
to distribute to OSCout0, OSCout1, and optionally
CLKout6 through CLKout9.
For the PLL modes, 0-delay can be used have deterministic
phase with the input clock.
For the PLL modes it is also possible to use an external VCO.
MODE, 5 bits
R11[31:27] Value
0 (0x00) Dual PLL, Internal VCO
1 (0x01) Reserved
2 (0x02) Dual PLL, Internal VCO,
0-Delay
3 (0x03) Dual PLL, External VCO (Fin)
4 (0x04) Reserved
5 (0x05)
Dual PLL, External VCO
(Fin),
0-Delay
6 (0x06) PLL2, Internal VCO
7 (0x07) Reserved
8 (0x08) PLL2, Internal VCO,
0–Delay
9 (0x09) Reserved
10 (0x0A) Reserved
11 (0x0B) PLL2, External VCO (Fin)
12 (0x0C) Reserved
13 (0x0D) Reserved
14 (0x0E) Reserved
15 (0x0F) Reserved
16 (0x10) Clock Distribution
17.9.2 EN_SYNC, Enable Synchronization
The EN_SYNC bit (default on) must be enabled for synchro-
nization to work. Synchronization is required for dynamic
digital delay.
The synchronization enable may be turned off once the clocks
are operating to save current. If EN_SYNC is set after it has
been cleared (a transition from 0 to 1), a SYNC is generated
that can disrupt the active clock outputs. Setting the
NO_SYNC_CLKoutX_Y bits will prevent this SYNC pulse
from affecting the output clocks. Setting the EN_SYNC bit is
not a valid method for synchronizing the clock outputs. See
the section for more information on synchronization.
EN_SYNC
R11[26] Definition
0 Synchronization disabled
1 Synchronization enabled
17.9.3 NO_SYNC_CLKoutX_Y
The NO_SYNC_CLKoutX_Y bits prevent individual clock
groups from becoming synchronized during a SYNC event. A
reason to prevent individual clock groups from becoming syn-
chronized is that during synchronization, the clock output is
in a fixed low state or can have a glitch pulse.
By disabling SYNC on a clock group, it will continue to operate
normally during a SYNC event.
Digital delay requires a SYNC operation to take effect. If
NO_SYNC_CLKoutX_Y is set before a SYNC event, the dig-
ital delay value will be unused.
Setting the NO_SYNC_CLKoutX_Y bit has no effect on
clocks already synchronized together.
NO_SYNC_CLKoutX_Y Programming Addresses
NO_SYNC_CLKoutX_Y Programming Address
CLKout0 and 1 R11:20
CLKout2 and 3 R11:21
CLKout4 and 5 R11:22
CLKout6 and 7 R11:23
CLKout8 and 9 R11:24
CLKout10 and 11 R11:25
NO_SYNC_CLKoutX_Y
R11[25, 24, 23, 22, 21, 20] Definition
0 CLKoutX_Y will synchronize
1CLKoutX_Y will not
synchronize
17.9.4 SYNC_MUX
Mux controlling SYNC pin when type is an output.
All the outputs logic is active high when SYNC_TYPE = 3
(Output). All the outputs logic is active low when SYNC_TYPE
= 4 (Output Inverted). For example, when SYNC_MUX = 0
(Logic Low) and SYNC_TYPE = 3 (Output) then SYNC out-
puts a logic low. When SYNC_MUX = 0 (Logic Low) and
SYNC_TYPE = 4 (Output Inverted) then SYNC outputs a logic
high.
SYNC_MUX, 2 bits
R11[19:18] Sync pin output
0 (0x00) Logic Low
1 (0x01) Reserved
2 (0x02) Reserved
3 (0x03) uWire Readback
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LMK04800 Family
17.9.5 SYNC_QUAL
When SYNC_QUAL is set, clock outputs will be synchronized
to an existing clock output selected by FEEDBACK_MUX. By
using the NO_SYNC_CLKoutX_Y bits, selected clock outputs
will not be interrupted during the SYNC event.
Qualifying the SYNC by an output clock means that the pulse
which turns the clock outputs off and on will have a fixed time
relationship to the qualifying output clock.
SYNC_QUAL = 1 requires CLKout4_5_PD = 0 for proper op-
eration. CLKout4_TYPE and CLKout5_TYPE may be set to
Powerdown mode.
See Section 16.9.2 Clock Output Synchronization (SYNC) for
more information.
SYNC_QUAL
R11[17] Mode
0 No qualification
1
Qualification by clock output
from feedback mux
(Must set
CLKout4_5_PD = 0)
17.9.6 SYNC_POL_INV
Sets the polarity of the SYNC pin when input. When SYNC is
asserted the clock outputs will transition to a low state.
See Section 16.9.2 Clock Output Synchronization (SYNC) for
more information on SYNC. A SYNC event can be generated
by toggling this bit through the MICROWIRE interface.
SYNC_POL_INV
R11[16] Polarity
0 SYNC is active high
1 SYNC is active low
17.9.7 SYNC_EN_AUTO
When set, causes a SYNC event to occur when programming
register R0 to R5 to adjust digital delay values.
The SYNC event will coincide with the LEuWire pin falling
edge.
Refer to Section 17.1 SPECIAL PROGRAMMING CASE FOR
R0 to R5 for CLKoutX_Y_DIV & CLKoutX_Y_DDLY for more
information on possible special programming considerations
when SYNC_EN_AUTO = 1.
SYNC_EN_AUTO
R11[15] Mode
0 Manual SYNC
1 SYNC Internally Generated
17.9.8 SYNC_TYPE
Sets the IO type of the SYNC pin.
SYNC_TYPE, 3 bits
R11[14:12] Polarity
0 (0x00) Input
1 (0x01) Input /w pull-up resistor
2 (0x02) Input /w pull-down resistor
3 (0x03) Output (push-pull)
4 (0x04) Output inverted (push-pull)
5 (0x05) Output (open source)
6 (0x06) Output (open drain)
When in output mode the SYNC input is forced to 0 regardless
of the SYNC_MUX setting. A synchronization can then be
activated by uWire by programming the SYNC_POL_INV reg-
ister to active low to assert SYNC. SYNC can then be re-
leased by programming SYNC_POL_INV to active high.
Using this uWire programming method to create a SYNC
event saves the need for an IO pin from another device.
17.9.9 EN_PLL2_XTAL
If an external crystal is being used to implement a discrete
VCXO, the internal feedback amplifier must be enabled with
this bit in order to complete the oscillator circuit.
EN_PLL2_XTAL
R11[5] Oscillator Amplifier State
0 Disabled
1 Enabled
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LMK04800 Family
17.10 REGISTER R12
17.10.1 LD_MUX
LD_MUX sets the output value of the LD pin.
All the outputs logic is active high when LD_TYPE = 3 (Out-
put). All the outputs logic is active low when LD_TYPE = 4
(Output Inverted). For example, when LD_MUX = 0 (Logic
Low) and LD_TYPE = 3 (Output) then Status_LD outputs a
logic low. When LD_MUX = 0 (Logic Low) and LD_TYPE = 4
(Output Inverted) then Status_LD outputs a logic high.
LD_MUX, 5 bits
R12[31:27] Divide
0 (0x00) Logic Low
1 (0x01) PLL1 DLD
2 (0x02) PLL2 DLD
3 (0x03) PLL1 & PLL2 DLD
4 (0x04) Holdover Status
5 (0x05) DAC Locked
6 (0x06) Reserved
7 (0x07) uWire Readback
8 (0x08) DAC Rail
9 (0x09) DAC Low
10 (0x0A) DAC High
11 (0x0B) PLL1_N
12 (0x0C) PLL1_N/2
13 (0x0D) PLL2 N
14 (0x0E) PLL2 N/2
15 (0x0F) PLL1_R
16 (0x10) PLL1_R/2
17 (0x11) PLL2 R (Note 33)
18 (0x12) PLL2 R/2 (Note 33)
Note 33: Only valid when HOLDOVER_MUX is not set to 2 (PLL2_DLD) or
3 (PLL1 & PLL2 DLD).
17.10.2 LD_TYPE
Sets the IO type of the LD pin.
LD_TYPE, 3 bits
R12[26:24] Polarity
0 (0x00) Reserved
1 (0x01) Reserved
R12[26:24] Polarity
2 (0x02) Reserved
3 (0x03) Output (push-pull)
4 (0x04) Output inverted (push-pull)
5 (0x05) Output (open source)
6 (0x06) Output (open drain)
17.10.3 SYNC_PLLX_DLD
By setting SYNC_PLLX_DLD a SYNC mode will be engaged
(asserted SYNC) until PLL1 and/or PLL2 locks.
SYNC_QUAL must be 0 to use this functionality.
SYNC_PLL2_DLD
R12[23] Sync Mode Forced
0 No
1 Yes
SYNC_PLL1_DLD
R12[22] Sync Mode Forced
0 No
1 Yes
17.10.4 EN_TRACK
Enable the DAC to track the PLL1 tuning voltage. For optional
use in in holdover mode.
Tracking can be used to monitor PLL1 voltage by readback
of DAC_CNT register in any mode.
EN_TRACK
R12[8] DAC Tracking
0 Disabled
1 Enabled
17.10.5 HOLDOVER_MODE
Enable the holdover mode.
HOLDOVER_MODE, 2 bits
R12[7:6] Holdover Mode
0 Reserved
1 Disabled
2 Enabled
3 Reserved
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LMK04800 Family
17.11 REGISTER R13
17.11.1 HOLDOVER_MUX
HOLDOVER_MUX sets the output value of the
Status_Holdover pin.
The outputs are active high when HOLDOVER_TYPE = 3
(Output). The outputs are active low when
HOLDOVER_TYPE = 4 (Output Inverted).
HOLDOVER_MUX, 5 bits
R13[31:27] Divide
0 (0x00) Logic Low
1 (0x01) PLL1 DLD
2 (0x02) PLL2 DLD
3 (0x03) PLL1 & PLL2 DLD
4 (0x04) Holdover Status
5 (0x05) DAC Locked
6 (0x06) Reserved
7 (0x07) uWire Readback
8 (0x08) DAC Rail
9 (0x09) DAC Low
10 (0x0A) DAC High
11 (0x0B) PLL1 N
12 (0x0C) PLL1 N/2
13 (0x0D) PLL2 N
14 (0x0E) PLL2 N/2
15 (0x0F) PLL1 R
16 (0x10) PLL1 R/2
17 (0x11) PLL2 R (Note 34)
18 (0x12) PLL2 R/2 (Note 34)
Note 34: Only valid when LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1
& PLL2 DLD).
17.11.2 HOLDOVER_TYPE
Sets the IO mode of the Status_Holdover pin.
HOLDOVER_TYPE, 3 bits
R13[26:24] Polarity
0 (0x00) Reserved
1 (0x01) Reserved
2 (0x02) Reserved
3 (0x03) Output (push-pull)
4 (0x04) Output inverted (push-pull)
5 (0x05) Output (open source)
6 (0x06) Output (open drain)
17.11.3 Status_CLKin1_MUX
Status_CLKin1_MUX sets the output value of the
Status_CLKin1 pin. If Section 17.12.3
Status_CLKin1_TYPE is set to an input type, this register has
no effect. This MUX register only sets the output signal.
The outputs are active high when Status_CLKin1_TYPE = 3
(Output). The outputs are active low when
Status_CLKin1_TYPE = 4 (Output Inverted).
Status_CLKin1_MUX, 3 bits
R13[22:20] Divide
0 (0x00) Logic Low
1 (0x01) CLKin1 LOS
2 (0x02) CLKin1 Selected
3 (0x03) DAC Locked
4 (0x04) DAC Low
5 (0x05) DAC High
6 (0x06) uWire Readback
17.11.4 Status_CLKin0_TYPE
Status_CLKin0_TYPE sets the IO type of the Status_CLKin0
pin.
Status_CLKin0_TYPE, 3 bits
R13[18:16] Polarity
0 (0x00) Input
1 (0x01) Input /w pull-up resistor
2 (0x02) Input /w pull-down resistor
3 (0x03) Output (push-pull)
4 (0x04) Output inverted (push-pull)
5 (0x05) Output (open source)
6 (0x06) Output (open drain)
17.11.5 DISABLE_DLD1_DET
DISABLE_DLD1_DET disables the HOLDOVER mode from
being activated when PLL1 lock detect signal transitions from
high to low.
When using Pin Select Mode as the input clock switch mode,
this bit should normally be set.
DISABLE_DLD1_DET
R13[15] Holdover DLD1 Detect
0 PLL1 DLD causes clock
switch event
1 PLL1 DLD does not cause
clock switch event
17.11.6 Status_CLKin0_MUX
CLKin0_MUX sets the output value of the Status_CLKin0 pin.
If Section 17.11.4 Status_CLKin0_TYPE is set to an input
type, this register has no effect. This MUX register only sets
the output signal.
The outputs logic is active high when Status_CLKin0_TYPE
= 3 (Output). The outputs logic is active low when
Status_CLKin0_TYPE = 4 (Output Inverted).
Status_CLKin0_MUX, 3 bits
R13[14:12] Divide
0 (0x00) Logic Low
1 (0x01) CLKin0 LOS
2 (0x02) CLKin0 Selected
3 (0x03) DAC Locked
4 (0x04) DAC Low
5 (0x05) DAC High
6 (0x06) uWire Readback
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LMK04800 Family
17.11.7 CLKin_SELECT_MODE
CLKin_SELECT_MODE sets the mode used in determining
reference CLKin for PLL1.
CLKin_SELECT_MODE, 3 bits
R13[11:9] Mode
0 (0x00) CLKin0 Manual
1 (0x01) CLKin1 Manual
2 (0x02) Reserved
3 (0x03) Pin Select Mode
4 (0x04) Auto Mode
5 (0x05) Reserved
6 (0x06) Auto mode & next clock pin
select
7 (0x07) Reserved
17.11.8 CLKin_Sel_INV
CLKin_Sel_INV sets the input polarity of Status_CLKin0 and
Status_CLKin1 pins.
CLKin_Sel_INV
R13[8] Input
0 Active High
1 Active Low
17.11.9 EN_CLKinX
Each clock input can individually be enabled to be used during
auto-switching CLKin_SELECT_MODE. Clock input switch-
ing priority is always CLKin0 → CLKin1.
EN_CLKin1
R13[6] Valid
0 No
1 Yes
EN_CLKin0
R13[5] Valid
0 No
1 Yes
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LMK04800 Family
17.12 REGISTER 14
17.12.1 LOS_TIMEOUT
This bit controls the amount of time in which no activity on a
CLKin causes LOS (Loss-of-Signal) to be asserted.
LOS_TIMEOUT, 2 bits
R14[31:30] Timeout
0 (0x00) 1200 ns, 420 kHz
1 (0x01) 206 ns, 2.5 MHz
2 (0x02) 52.9 ns, 10 MHz
3 (0x03) 23.7 ns, 22 MHz
17.12.2 EN_LOS
Enables the LOS (Loss-of-Signal) timeout control.
EN_LOS
R14[28] LOS
0 Disabled
1 Enabled
17.12.3 Status_CLKin1_TYPE
Sets the IO type of the Status_CLKin1 pin.
Status_CLKin1_TYPE, 3 bits
R14[26:24] Polarity
0 (0x00) Input
1 (0x01) Input /w pull-up resistor
2 (0x02) Input /w pull-down resistor
3 (0x03) Output (push-pull)
4 (0x04) Output inverted (push-pull)
5 (0x05) Output (open source)
6 (0x06) Output (open drain)
17.12.4 CLKinX_BUF_TYPE, PLL1 CLKinX/CLKinX*
Buffer Type
There are two input buffer types for the PLL1 reference clock
inputs: either bipolar or CMOS. Bipolar is recommended for
differential inputs such as LVDS and LVPECL. CMOS is rec-
ommended for DC coupled single ended inputs.
When using bipolar, CLKinX and CLKinX* input pins must be
AC coupled when using a differential or single ended input.
When using CMOS, CLKinX and CLKinX* input pins may be
AC or DC coupled with a differential input.
When using CMOS in single ended mode, the unused clock
input pin (CLKinX or CLKinX*) must be AC grounded. The
used clock input pin (CLKinX* or CLKinX) may be AC or DC
coupled to the signal source.
The programming addresses table shows at what register and
address the specified CLKinX_BUF_TYPE bit is located.
The CLKinX_BUF_TYPE table shows the programming def-
inition for these registers.
CLKinX_BUF_TYPE Programming Addresses
CLKinX_BUF_TYPE Programming Address
CLKin1_BUF_TYPE R14[21]
CLKin0_BUF_TYPE R14[20]
CLKinX_BUF_TYPE
R14[21, 20] CLKinX Buffer Type
0 Bipolar
1 CMOS
17.12.5 DAC_HIGH_TRIP
Voltage from Vcc at which holdover mode is entered if
EN_VTUNE_RAIL_DAC is enabled. Will also set flags which
can be monitored out Status_LD/Status_Holdover pins.
Step size is ~51 mV
DAC_HIGH_TRIP, 6 bits
R14[19:14] Trip voltage from Vcc (V)
0 (0x00) 1 × Vcc / 64
1 (0x01) 2 × Vcc / 64
2 (0x02) 3 × Vcc / 64
3 (0x03) 4 × Vcc / 64
4 (0x04) 5 × Vcc / 64
... ...
61 (0x3D) 62 × Vcc / 64
62 (0x3E) 63 × Vcc / 64
63 (0x3F) 64 × Vcc / 64
17.12.6 DAC_LOW_TRIP
Voltage from GND at which holdover mode is entered if
EN_VTUNE_RAIL_DAC is enabled. Will also set flags which
can be monitored out Status_LD/Status_Holdover pins.
Step size is ~51 mV
DAC_LOW_TRIP, 6 bits
R14[11:6] Trip voltage from GND (V)
0 (0x00) 1 × Vcc / 64
1 (0x01) 2 × Vcc / 64
2 (0x02) 3 × Vcc / 64
3 (0x03) 4 × Vcc / 64
4 (0x04) 5 × Vcc / 64
... ...
61 (0x3D) 62 × Vcc / 64
62 (0x3E) 63 × Vcc / 64
63 (0x3F) 64 × Vcc / 64
17.12.7 EN_VTUNE_RAIL_DET
Enables the DAC Vtune rail detection. When the DAC
achieves a specified Vtune, if this bit is enabled, the current
clock input is considered invalid and an input clock switch
event is generated.
EN_VTUNE_RAIL_DET
R14[5] State
0 Disabled
1 Enabled
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LMK04800 Family
17.13 REGISTER 15
17.13.1 MAN_DAC
Sets the DAC value when in manual DAC mode in ~3.2 mV
steps.
MAN_DAC, 10 bits
R15[31:22] DAC Voltage
0 (0x00) 0 × Vcc / 1023
1 (0x01) 1 × Vcc / 1023
2 (0x02) 2 × Vcc / 1023
... ...
1023 (0x3FF) 1023 × Vcc / 1023
17.13.2 EN_MAN_DAC
This bit enables the manual DAC mode.
EN_MAN_DAC
R15[20] DAC Mode
0 Automatic
1 Manual
17.13.3 HOLDOVER_DLD_CNT
Lock must be valid for this many clocks of PLL1 PDF before
holdover mode is exited.
HOLDOVER_DLD_CNT, 14 bits
R15[19:6] Exit Counts
0 (0x00) Reserved
1 (0x01) 1
2 (0x02) 2
... ...
16,383 (0x3FFF) 16,383
17.13.4 FORCE_HOLDOVER
This bit forces the holdover mode.
When holdover is forced, if in fixed CPout1 mode, then the
DAC will set the programmed MAN_DAC value. If in tracked
CPout1 mode, then the DAC will set the current tracked DAC
value.
Setting FORCE_HOLDOVER does not constitute a clock in-
put switch event unless DISABLE_DLD1_DET = 0, since in
holdover mode, PLL1_DLD = 0 this will trigger the clock input
switch event.
FORCE_HOLDOVER
R15[5] Holdover
0 Disabled
1 Enabled
17.14 REGISTER 16
17.14.1 XTAL_LVL
Sets the peak amplitude on the tunable crystal.
Increasing this value can improve the crystal oscillator phase
noise performance at the cost of increased current and higher
crystal power dissipation levels.
XTAL_LVL, 2 bits
R15[31:22] Peak Amplitude(Note 35)
0 (0x00) 1.65 Vpp
1 (0x01) 1.75 Vpp
2 (0x02) 1.90 Vpp
3 (0x03) 2.05 Vpp
Note 35: At crystal frequency of 20.48 MHz
17.15 REGISTER 23
This register must not be programmed, it is a readback only
register.
17.15.1 DAC_CNT
The DAC_CNT register is 10 bits in size and located at read-
back bit position [23:14]. When using tracking mode for
holdover, the DAC value can be readback at this address.
17.16 REGISTER 24
17.16.1 PLL2_C4_LF, PLL2 Integrated Loop Filter
Component
Internal loop filter components are available for PLL2, en-
abling either 3rd or 4th order loop filters without requiring
external components.
Internal loop filter capacitor C4 can be set according to the
following table.
PLL2_C4_LF, 4 bits
R24[31:28] Loop Filter Capacitance (pF)
0 (0x00) 10 pF
1 (0x01) 15 pF
2 (0x02) 29 pF
3 (0x03) 34 pF
4 (0x04) 47 pF
5 (0x05) 52 pF
6 (0x06) 66 pF
7 (0x07) 71 pF
8 (0x08) 103 pF
9 (0x09) 108 pF
10 (0x0A) 122 pF
11 (0x0B) 126 pF
12 (0x0C) 141 pF
13 (0x0D) 146 pF
14 (0x0E) Reserved
15 (0x0F) Reserved
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LMK04800 Family
17.16.2 PLL2_C3_LF, PLL2 Integrated Loop Filter
Component
Internal loop filter components are available for PLL2, en-
abling either 3rd or 4th order loop filters without requiring
external components.
Internal loop filter capacitor C3 can be set according to the
following table.
PLL2_C3_LF, 4 bits
R24[27:24] Loop Filter Capacitance (pF)
0 (0x00) 10 pF
1 (0x01) 11 pF
2 (0x02) 15 pF
3 (0x03) 16 pF
4 (0x04) 19 pF
5 (0x05) 20 pF
6 (0x06) 24 pF
7 (0x07) 25 pF
8 (0x08) 29 pF
9 (0x09) 30 pF
10 (0x0A) 33 pF
11 (0x0B) 34 pF
12 (0x0C) 38 pF
13 (0x0D) 39 pF
14 (0x0E) Reserved
15 (0x0F) Reserved
17.16.3 PLL2_R4_LF, PLL2 Integrated Loop Filter
Component
Internal loop filter components are available for PLL2, en-
abling either 3rd or 4th order loop filters without requiring
external components.
Internal loop filter resistor R4 can be set according to the fol-
lowing table.
PLL2_R4_LF, 3 bits
R24[22:20] Resistance
0 (0x00) 200 Ω
1 (0x01) 1 kΩ
2 (0x02) 2 kΩ
3 (0x03) 4 kΩ
4 (0x04) 16 kΩ
5 (0x05) Reserved
6 (0x06) Reserved
7 (0x07) Reserved
17.16.4 PLL2_R3_LF, PLL2 Integrated Loop Filter
Component
Internal loop filter components are available for PLL2, en-
abling either 3rd or 4th order loop filters without requiring
external components.
Internal loop filter resistor R3 can be set according to the fol-
lowing table.
PLL2_R3_LF, 3 bits
R24[18:16] Resistance
0 (0x00) 200 Ω
1 (0x01) 1 kΩ
2 (0x02) 2 kΩ
3 (0x03) 4 kΩ
4 (0x04) 16 kΩ
5 (0x05) Reserved
6 (0x06) Reserved
7 (0x07) Reserved
17.16.5 PLL1_N_DLY
Increasing delay of PLL1_N_DLY will cause the outputs to
lead from CLKinX. For use in 0-delay mode.
PLL1_N_DLY, 3 bits
R24[14:12] Definition
0 (0x00) 0 ps
1 (0x01) 205 ps
2 (0x02) 410 ps
3 (0x03) 615 ps
4 (0x04) 820 ps
5 (0x05) 1025 ps
6 (0x06) 1230 ps
7 (0x07) 1435 ps
17.16.6 PLL1_R_DLY
Increasing delay of PLL1_R_DLY will cause the outputs to lag
from CLKinX. For use in 0-delay mode.
PLL1_R_DLY, 3 bits
R24[10:8] Definition
0 (0x00) 0 ps
1 (0x01) 205 ps
2 (0x02) 410 ps
3 (0x03) 615 ps
4 (0x04) 820 ps
5 (0x05) 1025 ps
6 (0x06) 1230 ps
7 (0x07) 1435 ps
17.16.7 PLL1_WND_SIZE
PLL1_WND_SIZE sets the window size used for digital lock
detect for PLL1. If the phase error between the reference and
feedback of PLL1 is less than specified time, then the PLL1
lock counter increments.
Refer to Section 18.6 DIGITAL LOCK DETECT FREQUEN-
CY ACCURACY for more information.
PLL1_WND_SIZE, 2 bits
R24[7:6] Definition
0 5.5 ns
1 10 ns
2 18.6 ns
3 40 ns
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LMK04800 Family
17.17 REGISTER 25
17.17.1 DAC_CLK_DIV
The DAC update clock frequency is the PLL1 phase detector
frequency divided by this divisor.
DAC_CLK_DIV, 10 bits
R25[31:22] Divide
0 (0x00) Reserved
1 (0x01) 1
2 (0x02) 2
3 (0x03) 3
... ...
1,022 (0x3FE) 1022
1,023 (0x3FF) 1023
17.17.2 PLL1_DLD_CNT
The reference and feedback of PLL1 must be within the win-
dow of phase error as specified by PLL1_WND_SIZE for this
many phase detector cycles before PLL1 digital lock detect is
asserted.
Refer to Section 18.6 DIGITAL LOCK DETECT FREQUEN-
CY ACCURACY for more information.
PLL1_DLD_CNT, 14 bits
R25[19:6] Divide
0 Reserved
1 1
2 2
3 3
... ...
16,382 (0x3FFE) 16,382
16,383 (0x3FFF) 16,383
17.18 REGISTER 26
17.18.1 PLL2_WND_SIZE
PLL2_WND_SIZE sets the window size used for digital lock
detect for PLL2. If the phase error between the reference and
feedback of PLL2 is less than specified time, then the PLL2
lock counter increments. This value must be programmed to
2 (3.7 ns).
Refer to Section 18.6 DIGITAL LOCK DETECT FREQUEN-
CY ACCURACY for more information.
PLL2_WND_SIZE, 2 bits
R26[31:30] Definition
0 Reserved
1 Reserved
2 3.7 ns
3 Reserved
17.18.2 EN_PLL2_REF_2X, PLL2 Reference Frequency
Doubler
Enabling the PLL2 reference frequency doubler allows for
higher phase detector frequencies on PLL2 than would nor-
mally be allowed with the given VCXO or Crystal frequency.
Higher phase detector frequencies reduces the PLL N values
which makes the design of wider loop bandwidth filters pos-
sible.
EN_PLL2_REF_2X
R26[29] Description
0 Reference frequency normal
1Reference frequency
doubled (2x)
17.18.3 PLL2_CP_POL, PLL2 Charge Pump Polarity
PLL2_CP_POL sets the charge pump polarity for PLL2. The
internal VCO requires the negative charge pump polarity to
be selected. Many VCOs use positive slope.
A positive slope VCO increases output frequency with in-
creasing voltage. A negative slope VCO decreases output
frequency with increasing voltage.
PLL2_CP_POL
R26[28] Description
0 Negative Slope VCO/VCXO
1 Positive Slope VCO/VCXO
17.18.4 PLL2_CP_GAIN, PLL2 Charge Pump Current
This bit programs the PLL2 charge pump output current level.
The table below also illustrates the impact of the PLL2 TRI-
STATE bit in conjunction with PLL2_CP_GAIN.
PLL2_CP_GAIN, 2 bits
R26[27:26] PLL2_CP_TRI
R27[5]
Charge Pump
Current (µA)
X 1 Hi-Z
0 (0x00) 0 100
1 (0x01) 0 400
2 (0x02) 0 1600
3 (0x03) 0 3200
17.18.5 PLL2_DLD_CNT
The reference and feedback of PLL2 must be within the win-
dow of phase error as specified by PLL2_WND_SIZE for
PLL2_DLD_CNT cycles before PLL2 digital lock detect is as-
serted.
Refer to Section 18.6 DIGITAL LOCK DETECT FREQUEN-
CY ACCURACY for more information
PLL2_DLD_CNT, 14 bits
R26[19:6] Divide
0 (0x00) Reserved
1 (0x01) 1
2 (0x02) 2
3 (0x03) 3
... ...
16,382 (0x3FFE) 16,382
16,383 (0x3FFF) 16,383
17.18.6 PLL2_CP_TRI, PLL2 Charge Pump TRI-STATE
This bit allows for the PLL2 charge pump output pin, CPout2,
to be placed into TRI-STATE.
PLL2_CP_TRI
R26[5] Description
0 PLL2 CPout2 is active
1PLL2 CPout2 is at TRI-
STATE
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LMK04800 Family
17.19 REGISTER 27
17.19.1 PLL1_CP_POL, PLL1 Charge Pump Polarity
PLL1_CP_POL sets the charge pump polarity for PLL1. Many
VCXOs use positive slope.
A positive slope VCXO increases output frequency with in-
creasing voltage. A negative slope VCXO decreases output
frequency with increasing voltage.
PLL1_CP_POL
R27[28] Description
0 Negative Slope VCO/VCXO
1 Positive Slope VCO/VCXO
17.19.2 PLL1_CP_GAIN, PLL1 Charge Pump Current
This bit programs the PLL1 charge pump output current level.
The table below also illustrates the impact of the PLL1 TRI-
STATE bit in conjunction with PLL1_CP_GAIN.
PLL1_CP_GAIN, 2 bits
R26[27:26] PLL1_CP_TRI
R27[5]
Charge Pump
Current (µA)
X 1 Hi-Z
0 (0x00) 0 100
1 (0x01) 0 200
2 (0x02) 0 400
3 (0x03) 0 1600
17.19.3 CLKinX_PreR_DIV
The pre-R dividers before the PLL1 R divider can be pro-
grammed such that when the active clock input is switched,
the frequency at the input of the PLL1 R divider will be the
same. This allows PLL1 to stay in lock without needing to re-
program the PLL1 R register when different clock input fre-
quencies are used. This is especially useful in the auto CLKin
switching modes.
CLKinX_PreR_DIV Programming Addresses
CLKinX_PreR_DIV Programming Address
CLKin1_PreR_DIV R27[23:22]
CLKin0_PreR_DIV R27[21:20]
CLKinX_PreR_DIV, 2 bits
R27[23:22, 21:20] Divide
0 (0x00) 1
1 (0x01) 2
2 (0x02) 4
3 (0x03) 8
17.19.4 PLL1_R, PLL1 R Divider
The reference path into the PLL1 phase detector includes the
PLL1 R divider. Refer to Section 18.2 PLL PROGRAMMING
for more information on how to program the PLL dividers to
lock the PLL.
The valid values for PLL1_R are shown in the table below.
PLL1_R, 14 bits
R27[19:6] Divide
0 (0x00) Reserved
1 (0x01) 1
2 (0x02) 2
3 (0x03) 3
... ...
16,382 (0x3FFE) 16,382
16,383 (0x3FFF) 16,383
17.19.5 PLL1_CP_TRI, PLL1 Charge Pump TRI-STATE
This bit allows for the PLL1 charge pump output pin, CPout1,
to be placed into TRI-STATE.
PLL1_CP_TRI
R27[5] Description
0 PLL1 CPout1 is active
1PLL1 CPout1 is at TRI-
STATE
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LMK04800 Family
17.20 REGISTER 28
17.20.1 PLL2_R, PLL2 R Divider
The reference path into the PLL2 phase detector includes the
PLL2 R divider.
Refer to Section 18.2 PLL PROGRAMMING for more infor-
mation on how to program the PLL dividers to lock the PLL.
The valid values for PLL2_R are shown in the table below.
PLL2_R, 12 bits
R28[31:20] Divide
0 (0x00) Not Valid
1 (0x01) 1
2 (0x02) 2
3 (0x03) 3
... ...
4,094 (0xFFE) 4,094
4,095 (0xFFF) 4,095
17.20.2 PLL1_N, PLL1 N Divider
The feedback path into the PLL1 phase detector includes the
PLL1 N divider.
Refer to Section 18.2 PLL PROGRAMMING for more infor-
mation on how to program the PLL dividers to lock the PLL.
The valid values for PLL1_N are shown in the table below.
PLL1_N, 14 bits
R28[19:6] Divide
0 (0x00) Not Valid
1 (0x01) 1
2 (0x02) 2
... ...
4,095 (0xFFF) 4,095
17.21 REGISTER 29
17.21.1 OSCin_FREQ, PLL2 Oscillator Input Frequency
Register
The frequency of the PLL2 reference input to the PLL2 Phase
Detector (OSCin/OSCin* port) must be programmed in order
to support proper operation of the frequency calibration rou-
tine which locks the internal VCO to the target frequency.
OSCin_FREQ, 3 bits
R29[26:24] OSCin Frequency
0 (0x00) 0 to 63 MHz
1 (0x01) >63 MHz to 127 MHz
2 (0x02) >127 MHz to 255 MHz
3 (0x03) Reserved
4 (0x04) >255 MHz to 400 MHz
17.21.2 PLL2_FAST_PDF, High PLL2 Phase Detector
Frequency
When PLL2 phase detector frequency is greater than 100
MHz, set the PLL2_FAST_PDF to ensure proper operation of
device.
PLL2_FAST_PDF
R29[23] PLL2 PDF
0Less than or
equal to 100 MHz
1 Greater than 100 MHz
17.21.3 PLL2_N_CAL, PLL2 N Calibration Divider
During the frequency calibration routine, the PLL uses the di-
vide value of the PLL2_N_CAL register instead of the divide
value of the PLL2_N register to lock the VCO to the target
frequency.
Refer to Section 18.2 PLL PROGRAMMING for more infor-
mation on how to program the PLL dividers to lock the PLL.
PLL2_N_CAL, 18 bits
R30[22:5] Divide
0 (0x00) Not Valid
1 (0x01) 1
2 (0x02) 2
... ...
262,143 (0x3FFFF) 262,143
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LMK04800 Family
17.22 REGISTER 30
If an internal VCO mode is used, programming Register 30
triggers the frequency calibration routine. This calibration rou-
tine will also generate a SYNC event. See Section 16.9.2
Clock Output Synchronization (SYNC) for more details on a
SYNC.
17.22.1 PLL2_P, PLL2 N Prescaler Divider
The PLL2 N Prescaler divides the output of the VCO as se-
lected by Mode_MUX1 and is connected to the PLL2 N di-
vider.
Refer to Section 18.2 PLL PROGRAMMING for more infor-
mation on how to program the PLL dividers to lock the PLL.
PLL2_P, 3 bits
R30[26:24] Divide Value
0 (0x00) 8
1 (0x01) 2
2 (0x02) 2
3 (0x03) 3
4 (0x04) 4
5 (0x05) 5
6 (0x06) 6
7 (0x07) 7
17.22.2 PLL2_N, PLL2 N Divider
The feeback path into the PLL2 phase detector includes the
PLL2 N divider.
Each time register 30 is updated via the MICROWIRE inter-
face, a frequency calibration routine runs to lock the VCO to
the target frequency. During this calibration PLL2_N is sub-
stituted with PLL2_N_CAL.
Refer to Section 18.2 PLL PROGRAMMING for more infor-
mation on how to program the PLL dividers to lock the PLL.
The valid values for PLL2_N are shown in the table below.
PLL2_N, 18 bits
R30[22:5] Divide
0 (0x00) Not Valid
1 (0x01) 1
2 (0x02) 2
...
262,143 (0x3FFFF) 262,143
17.23 REGISTER 31
17.23.1 READBACK_LE
Sets the required state of the LEuWire pin when performing
register readback.
Refer to Section 17.3 READBACK
READBACK_LE
R31[21] Register
0 (0x00) LE must be low for readback
1 (0x01) LE must be high for readback
17.23.2 READBACK_ADDR
Sets the address of the register to read back when performing
readback.
When reading register 12, the READBACK_ADDR will be
read back at R12[20:16].
When reading back from R31 bits 6 to 31 should be ignored.
Only uWire_LOCK is valid.
Refer to Section 15.13 REGISTER READBACK for more in-
formation on readback.
READBACK_ADDR, 5 bits
R31[20:16] Register
0 (0x00) R0
1 (0x01) R1
2 (0x02) R2
3 (0x03) R3
4 (0x04) R4
5 (0x05) R5
6 (0x06) R6
7 (0x07) R7
8 (0x08) R8
9 (0x09) Reserved
10 (0x0A) R10
11 (0x0B) R11
12 (0x0C) R12
13 (0x0D) R13
14 (0x0E) R14
15 (0x0F) R15
16 (0x10) Reserved
17 (0x11) Reserved
... ...
22 (0x16) Reserved
23 (0x17) Reserved
24 (0x18) R24
25 (0x19) R25
26 (0x1A) R26
27 (0x1B) R27
28 (0x1C) R28
29 (0x1D) R29
30 (0x1E) R30
31 (0x1F) R31
17.23.3 uWire_LOCK
Setting uWire_LOCK will prevent any changes to uWire reg-
isters R0 to R30. Only by clearing the uWire_LOCK bit in R31
can the uWire registers be unlocked and written to once more.
It is not necessary to lock the registers to perform a readback
operation.
uWire_LOCK
R31[5] State
0 Registers unlocked
1 Registers locked, Write-
protect
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LMK04800 Family
18.0 Application Information
18.1 FREQUENCY PLANNING WITH THE LMK04800
FAMILY (Note 36)
Calculating the value of the output dividers for use with the
LMK04800 family is simple due to the architecture of the
LMK04800. That is, the VCO divider may be bypassed and
the clock output dividers allow for even and odd output divide
values from 2 to 1045. For most applications it is recommend-
ed to bypass the VCO divider.
The procedure for determining the needed LMK048xx device
and clock output divider values for a set of clock output fre-
quencies is straightforward.
1. Calculate the least common multiple (LCM) of the clock
output frequencies.
2. Determine which VCO ranges will support the target
clock output frequencies given the LCM.
3. Determine the clock output divide values based on VCO
frequency.
4. Determine the PLL2_P, PLL2_N, and PLL2_R divider
values given the OSCin VCXO or crystal frequency and
VCO frequency.
For example, given the following target output frequencies:
200 MHz, 120 MHz, and 25 MHz with a VCXO frequency of
40 MHz:
First determine the LCM of the three frequencies. LCM(200
MHz, 120 MHz, 25 MHz) = 600 MHz. The LCM frequency is
the lowest frequency for which all of the target output fre-
quencies are integer divisors of the LCM. Note, if there is one
frequency which causes the LCM to be very large, greater
than 3 GHz for example, determine if there is a single fre-
quency requirement which causes this. It may be possible to
select the VCXO/crystal frequency to satisfy this frequency
requirement through OSCout or CLKout6/7/8/9 driven by OS-
Cin. In this way it is possible to get non-integer related fre-
quencies at the outputs.
Second, since the LCM is not in a VCO frequency range sup-
ported by the LMK04800 family, multiply the LCM frequency
by an integer which causes it to fall into a valid VCO frequency
range of an LMK048xx device. In this case 600 MHz * 5 =
3000 MHz which is valid for the LMK04808.
Third, continuing the example by using a VCO frequency of
3000 MHz and the LMK04808, the CLKout dividers can be
calculated by simply dividing the VCO frequency by the output
frequency. To output 200 MHz, 120 MHz, and 25 MHz the
output dividers will be 12, 20, and 96 respectively.
•3000 MHz / 200 MHz = 15
•3000 MHz / 120 MHz = 25
•3000 MHz / 25 MHz = 120
Fourth, PLL2 must be locked to its input reference. Refer to
Section 18.2 PLL PROGRAMMING for more information on
this topic. By programming the clock output dividers and the
PLL2 dividers the VCO can lock to the frequency of 3000 MHz
and the clock outputs dividers will each divide the VCO fre-
quency down to the target output frequencies of 200 MHz,
120 MHz, and 25 MHz.
Note 36: Refer to application note AN-1865 Frequency Synthesis and
Planning for PLL Architectures for more information on this topic and LCM
calculations.
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LMK04800 Family
18.2 PLL PROGRAMMING
To lock a PLL the divided reference and divided feedback from VCO or VCXO must result in the same phase detector frequency.
The tables below illustrate how the divides are structured for the reference path (R) and feedback path (N) depending on the MODE
of the device.
PLL1 Phase Detector Frequency — Reference Path (R)
MODE (R) PLL1 PDF =
All CLKinX Frequency / CLKinX_PreR_DIV / PLL1_R
PLL1 Phase Detector Frequency — Feedback Path (N)
MODE VCO_MUX OSCout0 PLL1 PDF (N) =
Internal VCO Dual PLL —Bypass VCXO Frequency / PLL1_N
—Divided VCXO Frequency / OSCin_DIV / PLL1_N
Internal VCO /w 0-delay
Bypass —VCO Frequency / CLKoutX_Y_DIV / PLL1_N (Note 37)
Divided —VCO Frequency / VCO_DIV / CLKoutX_Y_DIV / PLL1_N
(Note 37)
Note 37: The actual CLKoutX_Y_DIV used is selected by Section 17.8.10 FEEDBACK_MUX.
PLL2 Phase Detector Frequency — Reference Path (R)
EN_PLL2_REF_2X PLL2 PDF (R) =
Disabled OSCin Frequency / PLL2_R
Enabled OSCin Frequency * 2 / PLL2_R
PLL2 Phase Detector Frequency — Feedback Path (N)
MODE VCO_MUX PLL2 PDF (N) =
Dual PLL
VCO VCO Frequency / PLL2_P / PLL2_NDual PLL /w 0-delay
Single PLL
Dual PLL
VCO Divider VCO Frequency / VCO_DIV / PLL2_P / PLL2_NDual PLL /w 0-delay
Single PLL
Dual PLL External VCO —VCO Frequency / VCO_DIV / PLL2_P / PLL2_N
Dual PLL External VCO /w 0-delay
Single PLL /w 0-delay VCO VCO Frequency / CLKoutX_Y_DIV / PLL2_N
VCO Divider VCO Frequency / VCO_DIV / CLKoutX_Y_DIV / PLL2_N
PLL2 Phase Detector Frequency — Feedback Path (N) during VCO Frequency Calibration
MODE VCO_MUX PLL2 PDF (N_CAL) =
All Internal VCO Modes VCO VCO Frequency / PLL2_P / PLL2_N_CAL
VCO Divider VCO Frequency / VCO_DIV / PLL2_P / PLL2_N_CAL
18.2.1 Example PLL2 N Divider Programming
To program PLL2 to lock an LMK04808 using Dual PLL mode to a VCO frequency of 3000 MHz using a 40 MHz VCXO reference,
first determine the total PLL2 N divide value. This is VCO Frequency / PLL2 phase detector frequency. This example assumes a
PLL2 R divide value of 1 which results in PLL2 phase detector frequency the same as PLL2 reference frequency (40 MHz). 3000
MHz / 40 MHz = 75, so the total PLL2 N divide value is 75.
The dividers in the PLL2 N feedback path for Dual PLL mode include PLL2_P and PLL2_N. PLL2_P can be programmed from 2
to 8 even and odd. PLL2_N can be programmed from 1 to 263,143 even and odd. Since the total PLL2 N divide value of 75 contains
the factors 3, 3, and 5, it would be allowable to program PLL2_P to 3 or 5. It is simplest to use the smallest divide, so PLL2_P =
3, and PLL2_N = 25 which results in a Total PLL2 N = 75.
For this example and in most cases, PLL2_N_CAL will have the same value as PLL2_N. However when using Single PLL mode
with 0-delay, the values will differ. When using an external VCO, PLL2_N_CAL value is unused.
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LMK04800 Family
18.3 LOOP FILTER
Each PLL of the LMK04800 family requires a dedicated loop
filter.
18.3.1 PLL1
The loop filter for PLL1 must be connected to the CPout1 pin.
Figure 18shows a simple 2-pole loop filter. The output of the
filter drives an external VCXO module or discrete implemen-
tation of a VCXO using a crystal resonator and external
varactor diode. Higher order loop filters may be implemented
using additional external R and C components. It is recom-
mended the loop filter for PLL1 result in a total closed loop
bandwidth in the range of 10 Hz to 200 Hz. The design of the
loop filter is application specific and highly dependent on pa-
rameters such as the phase noise of the reference clock,
VCXO phase noise, and phase detector frequency for PLL1.
National’s Clock Conditioner Owner’s Manual covers this top-
ic in detail and National’s Clock Design Tool can be used to
simulate loop filter designs for both PLLs. These resources
may be found: http://www.national.com/timing/.
18.3.2 PLL2
As shown in Figure 18, the charge pump for PLL2 is directly
connected to the optional internal loop filter components,
which are normally used only if either a third or fourth pole is
needed. The first and second poles are implemented with ex-
ternal components. The loop must be designed to be stable
over the entire application-specific tuning range of the VCO.
The designer should note the range of KVCO listed in the table
of Electrical Characteristics and how this value can change
over the expected range of VCO tuning frequencies. Because
loop bandwidth is directly proportional to KVCO, the designer
should model and simulate the loop at the expected extremes
of the desired tuning range, using the appropriate values for
KVCO.
When designing with the integrated loop filter of the
LMK04800 family, considerations for minimum resistor ther-
mal noise often lead one to the decision to design for the
minimum value for integrated resistors, R3 and R4.
Both the integrated loop filter resistors (R3 and R4) and ca-
pacitors (C3 and C4) also restrict the maximum loop band-
width. However, these integrated components do have the
advantage that they are closer to the VCO and can therefore
filter out some noise and spurs better than external compo-
nents. For this reason, a common strategy is to minimize the
internal loop filter resistors and then design for the largest in-
ternal capacitor values that permit a wide enough loop band-
width. In situations where spur requirements are very
stringent and there is margin on phase noise, a feasible strat-
egy would be to design a loop filter with integrated resistor
values larger than their minimum value.
30102371
FIGURE 18. PLL1 and PLL2 Loop Filters
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LMK04800 Family
18.4 SYSTEM LEVEL DIAGRAM
Figure 19 and Figure 20 show an LMK04800 family device
with external circuitry for clocking and for power supply to
serve as a guideline for good practices when designing with
the LMK04800 family. Refer to Section 18.5 PIN CONNEC-
TION RECOMMENDATIONS for more details on the pin
connections and bypassing recommendations. Also refer to
the evaluation board. PCB design will also play a role in de-
vice performance.
30102378
FIGURE 19. Example Application – System Schematic Except for Power
Figure 19 shows the primary reference clock input is at
CLKin0/0*. A secondary reference clock is driving CLKin1/1*.
Both clocks are depicted as AC coupled differential drivers.
The VCXO attached to the OSCin/OSCin* port is configured
as an AC coupled single-ended driver. Any of the input ports
(CLKin0/0*, CLKin1/1*, or OSCin/OSCin*) may be configured
as either differential or single-ended. These options are dis-
cussed later in the data sheet.
See for more information on PLL1 and PLL2 loop filters.
The clock outputs are all AC coupled with 0.1 µF capacitors.
Some clock outputs are depicted as LVPECL with 240 Ω
emitter resistors and some clock outputs as LVDS. However,
the output format of the clock outputs will vary by user pro-
gramming, so the user should use the appropriate source
termination for each clock output. Later sections of this data
sheet illustrate alternative methods for AC coupling, DC cou-
pling and terminating the clock outputs.
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LMK04800 Family
PCB design will influence crosstalk performance. Tightly cou-
pled clock traces will have less crosstalk than loosely coupled
clock traces. Also proximity to other clocks traces will influ-
ence crosstalk.
30102377
FIGURE 20. Example Application – Power System Schematic
Figure 20 shows an example decouping and bypassing
scheme for the LMK048xx. Components drawn in dotted lines
are optional. Two power planes are used in this design, one
for the clock outputs and one for other PLL circuits.
PCB design will influence impedance to the supply. Vias and
traces will increase the impedance to the power supply. En-
sure good direct return current paths.
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LMK04800 Family
18.5 PIN CONNECTION RECOMMENDATIONS
18.5.1 Vcc Pins and Decoupling
All Vcc pins must always be connected.
Integrated capacitance on the LMK048xx makes external
high frequency decoupling capacitors (≤ 1 nF) unnecessary.
The internal capacitance is more effective at filtering high fre-
quency noise than off device bypass capacitance because
there is no bond wire inductance between the LMK048xx cir-
cuit and the bypass capacitor.
18.5.1.1 Vcc2, Vcc3, Vcc10, Vcc11, Vcc12, Vcc13 (CLKout
Vccs)
Each of these pins has an internal 200 pF of capacitance.
Ferrite beads may be used to reduce crosstalk between dif-
ferent clock output frequencies on the same LMK048xx de-
vice. Ferrite beads placed between the power supply and a
clock Vcc pin will reduce noise between the Vcc pin and the
power supply. When several output clocks share the same
frequency a single ferrite bead can be used between the pow-
er supply and each same frequency CLKout Vcc pin.
When using ferrite beads on CLKout Vcc pins, care must be
taken to ensure the power supply can source the needed
switching current.
•In most cases a ferrite bead may be placed and the internal
capacitance is sufficient.
•If a ferrite bead is used with a low frequency output
(typically ≤ 10 MHz) and a high current switching clock
output format such as non-complementary LVCMOS or
high swing LVPECL is used, then...
—the ferrite bead can be removed to the lower
impedance to the main power supply and bypass
capacitors, or
—localized capacitance can be placed between the
ferrite bead and Vcc pin to support the switching
current.
Note that decoupling capacitors used between the
ferrite bead and a CLKout Vcc pin can permit high
frequency switching noise to couple through the
capacitors into the ground plane and onto other CLKout
Vcc pins with decoupling capacitors. This can degrade
crosstalk performance.
18.5.1.2 Vcc1 (VCO), Vcc4 (Digital), and Vcc9 (PLL2)
Each of these pins has internal bypass capacitance.
Ferrite beads should not be used between these pins and the
power supply/large bypass capacitors because these Vcc
pins don’t produce much noise or a ferrite bead can cause
phase noise disturbances and resonances.
The typical application diagram in Figure 20 shows all these
Vccs connected to together to Vcc without a ferrite bead.
18.5.1.3 Vcc6 (PLL1 Charge Pump) and Vcc8 (PLL2
Charge Pump)
Each of these pins has an internal bypass capacitor.
Use of a ferrite bead between the power supply/large bypass
capacitors and PLL1 is optional. PLL1 charge pump can be
connected directly to Vcc along with Vcc1, Vcc4, and Vcc9.
Depending on the application, a 0.1 uF capacitor may be
placed close to PLL1 charge pump Vcc pin.
A ferrite bead should be placed between the power supply/
large bypass capacitors and Vcc8. Most applications have
high PLL2 phase detector frequencies and (> 50 MHz) such
that the internal bypassing is sufficient and a ferrite bead can
be used to isolate this switching noise from other circuits. For
lower phase detector frequencies a ferrite bead is optional
and depending on application a 0.1 uF capacitor may be
added on Vcc8.
18.5.1.4 Vcc5 (CLKin & OSCout1), Vcc7 (OSCin &
OSCout0)
Each of these pins has an internal 100 pF of capacitance. No
ferrite bead should be placed between the power supply/large
bypass capacitors and Vcc5 or Vcc7.
These pins are unique since they supply an output clock and
other circuitry.
Vcc5 supplies CLKin and OSCout1.
Vcc7 supplies OSCin, OSCout0, and PLL2 circuitry.
18.5.2 LVPECL Outputs
When using an LVPECL output it is not recommended to
place a capacitor to ground on the output as might be done
when using a capacitor input LC lowpass filter. The capacitor
will appear as a short to the LVPECL output drivers which are
able to supply large amounts of switching current. The effect
of the LVPECL sourcing large switching currents can result
in:
1. Large switching currents through the Vcc pin of the
LVPECL power supply resulting in more Vcc noise and
possible Vcc spikes.
2. Large switching currents injected into the ground plane
through the capacitor which could couple onto other Vcc
pins with bypass capacitors to ground resulting in more
Vcc noise and possible Vcc spikes.
18.5.3 Unused Clock Outputs
Leave unused clock outputs floating and powered down.
18.5.4 Unused Clock Inputs
Unused clock inputs can be left floating.
18.5.5 LDO Bypass
The LDObyp1 and LDObyp2 pins should be connected to
GND through external capacitors, as shown in the diagram.
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LMK04800 Family
18.6 DIGITAL LOCK DETECT FREQUENCY ACCURACY
The digital lock detect circuit is used to determine PLL1
locked, PLL2 locked, and holdover exit events. A window size
and lock count register are programmed to set a ppm fre-
quency accuracy of reference to feedback signals of the PLL
for each event to occur. When a PLL digital lock event occurs
the PLL's digital lock detect is asserted true. When the
holdover exit event occurs, the device will exit holdover mode.
TABLE 17.
Event PLL Window size Lock count
PLL1
Locked PLL1 PLL1_WND_SIZE PLL1_DLD_CNT
PLL2
Locked PLL2 PLL2_WND_SIZE PLL2_DLD_CNT
Holdover
exit PLL1 PLL1_WND_SIZE HOLDOVER_DLD_
CNT
For a digital lock detect event to occur there must be a “lock
count” number of phase detector cycles of PLLX during which
the time/phase error of the PLLX_R reference and PLLX_N
feedback signal edges are within the user programmable
"window size." Since there must be at least "lock count" phase
detector events before a lock event occurs, a minimum digital
lock event time can be calculated as "lock count" / fPDX where
X = 1 for PLL1 or 2 for PLL2.
By using Equation 3, values for a "lock count" and "window
size" can be chosen to set the frequency accuracy required
by the system in ppm before the digital lock detect event oc-
curs:
(3)
The effect of the "lock count" value is that it shortens the ef-
fective lock window size by dividing the "window size" by "lock
count".
If at any time the PLLX_R reference and PLLX_N feedback
signals are outside the time window set by "window size", then
the “lock count” value is reset to 0.
18.6.1 Minimum Lock Time Calculation Example
To calculate the minimum PLL2 digital lock time given a PLL2
phase detector frequency of 40 MHz and PLL2_DLD_CNT =
10,000. Then the minimum lock time of PLL2 will be 10,000 /
40 MHz = 250 µs.
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LMK04800 Family
18.7 CALCULATING DYNAMIC DIGITAL DELAY VALUES
FOR ANY DIVIDE
This section explains how to calculate the dynamic digital de-
lay for any divide value.
Dynamic digital delay allows the time offset between two or
more clock outputs to be adjusted with no or minimal inter-
ruption of clock outputs. Since the clock outputs are operating
at a known frequency, the time offset can also be expressed
as a phase shift. When dynamically adjusting the digital delay
of clock outputs with different frequencies the phase shift
should be expressed in terms of the higher frequency clock.
The step size of the smallest time adjustment possible is
equal to half the period of the Clock Distribution Path, which
is the VCO frequency (Equation 1) or the VCO frequency di-
vided by the VCO divider (Equation 2) if not bypassed. The
smallest degree phase adjustment with respect to a clock fre-
quency will be 360 * the smallest time adjustment * the clock
frequency. The total number of phase offsets that the
LMK04800 family is able to achieve using dynamic digital de-
lay is equal 1 / (higher clock frequency * the smallest phase
adjustment).
Equation 4 calculates the digital delay value that must be pro-
grammed for a synchronizing clock to achieve a 0 time/phase
offset from the qualifying clock. Once this digital delay value
is known, it is possible to calculate the digital delay value for
any phase offset. The qualifying clock for dynamic digital de-
lay is selected by the FEEDBACK_MUX. When dynamic
digital delay is engaged with same clock output used for the
qualifying clock and the new synchronized clock, it is termed
relative dynamic digital delay since causing another SYNC
event with the same digital delay value will offset the clock by
the same phase once again. The important part of relative
dynamic digital delay is that the CLKoutX_Y_HS must be pro-
grammed correctly when the SYNC event occurs (Table 8).
This can result in needing to program the device twice. Once
to set the new CLKoutX_Y_DDLY with CLKoutX_Y_HS as
required for the SYNC event, and again to set the
CLKoutX_Y_HS to its desired value.
Digital delay values are programmed using the
CLKoutX_Y_DDLY and CLKoutX_Y_HS registers as shown
in Equation 5. For example, to achieve a digital delay of 13.5,
program CLKoutX_Y_DDLY = 14 and CLKoutX_Y_HS = 1.
(4)
Equation 4 uses the ceiling operator. To find the ceiling of a
fractional number round up. An integer remains the same val-
ue.
Digital delay = CLKoutX_Y_DDLY - (0.5 *
CLKoutX_Y_HS) (5)
Note: since the digital delay value for 0 time/phase offset is a
function of the qualifying clock's divide value, the resulting
digital delay value can be used for any clock output operating
at any frequency to achieve a 0 time/phase offset from the
qualifying clock. Therefore the calculated time shift table will
also be the same as in Table 18
18.7.1 Example
Consider a system with:
•A VCO frequency of 2000 MHz.
•The VCO divider is bypassed, therefore the clock
distribution path frequency is 2000 MHz.
•CLKout0_1_DIV = 10 resulting in a 200 MHz frequency on
CLKout0.
•CLKout2_3_DIV = 20 resulting in a 100 MHz frequency on
CLKout2.
For this system the minimum time adjustment is 0.25 ns,
which is 0.5 / (2000 MHz). Since the higher frequency is 200
MHz, phase adjustments will be calculated with respect to the
200 MHz frequency. The 0.25 ns minimum time adjustment
results in a minimum phase adjustment of 18 degrees, which
is 360 degrees / 200 MHz * 0.25 ns.
To calculate the digital delay value to achieve a 0 time/phase
shift of CLKout2 when CLKout0 is the qualifying clock. Solve
Equation 4 using the divide value of 10. To solve the equation
16/10 = 1.6, the ceiling of 1.6 is 2. Then to finish solving the
equation solve (2 + 0.5) * 10 - 11.5 = 13.5. A digital delay value
of 13.5 is programmed by setting CLKout2_3_DDLY = 14 and
CLKout2_3_HS = 1.
To calculate the digital delay value to achieve a 0 time/phase
shift of CLKout0 when CLKout2 is the qualifying clock, solve
Equation 4 using the divide value of CLKout2, which is 20.
This results in a digital delay of 18.5 which is programmed as
CLKout0_1_DDLY = 19 and CLKout0_1_HS = 1.
Once the 0 time/phase shift digital delay programming value
is known a table can be constructed with the digital delay val-
ue to be programmed for any time/phase offset by decre-
menting or incrementing the digital delay value by 0.5 for the
minimum time/phase adjustment.
A complete filled out table for use of CLKout0 as the qualifying
clock is shown in Table 18. It was created by entering a digital
delay of 13.5 for 0 degree phase shift, then decrementing the
digital delay down to the minimum value of 4.5. Since this did
not result in all the possible phase shifts, the digital delay was
then incremented from 13.5 to 14.0 to complete all possible
phase shifts.
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LMK04800 Family
TABLE 18. Example Digital Delay Calculation
Digital delay
Calculated
time shift
(ns)
Relative time
shift to 200
MHz
(ns)
Phase shift
of 200 MHz
(degrees)
4.5 -4.5 0.5 36
5 -4.25 0.75 54
5.5 -4.0 1.0 72
6 -3.75 1.25 90
6.5 -3.5 1.5 108
7 -3.25 1.75 126
7.5 -3.0 2.0 144
8 -2.75 2.25 162
8.5 -2.5 2.5 180
9 -2.25 2.75 198
9.5 -2.0 3.0 216
10 -1.75 3.25 234
10.5 -1.5 3.5 252
11 -1.25 3.75 270
11.5 -1.0 4.0 288
Digital delay
Calculated
time shift
(ns)
Relative time
shift to 200
MHz
(ns)
Phase shift
of 200 MHz
(degrees)
12 -0.75 4.25 306
12.5 -0.5 4.5 324
13 -0.25 4.75 342
13.5 0 0 0
14 0.25 0.25 18
14.5 0.5 0.5 36
Observe that the digital delay value of 4.5 and 14.5 will
achieve the same relative time shift/phase delay. However
programming a digital delay of 14.5 will result in a clock off
time for the synchronizing clock to achieve the same phase
time shift/phase delay.
Digital delay value is programmed as CLKoutX_Y_DDLY -
(0.5 * CLKoutX_Y_HS). So to achieve a digital delay of 13.5,
program CLKoutX_Y_DDLY = 14 and CLKoutX_Y_HS = 1.
To achieve a digital delay of 14, program CLKoutX_Y_DDLY
= 14 and CLKoutX_Y_HS = 0.
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LMK04800 Family
18.8 OPTIONAL CRYSTAL OSCILLATOR
IMPLEMENTATION (OSCin/OSCin*)
The LMK04800 family features supporting circuitry for a dis-
cretely implemented oscillator driving the OSCin port pins.
Figure 21 illustrates a reference design circuit for a crystal
oscillator:
30102363
FIGURE 21. Reference Design Circuit for Crystal Oscillator Option
This circuit topology represents a parallel resonant mode os-
cillator design. When selecting a crystal for parallel reso-
nance, the total load capacitance, CL, must be specified. The
load capacitance is the sum of the tuning capacitance
(CTUNE), the capacitance seen looking into the OSCin port
(CIN), and stray capacitance due to PCB parasitics (CSTRAY),
and is given by Equation 6.
(6)
CTUNE is provided by the varactor diode shown in Figure 21,
Skyworks model SMV1249-074LF. A dual diode package
with common cathode provides the variable capacitance for
tuning. The single diode capacitance ranges from approxi-
mately 31 pF at 0.3 V to 3.4 pF at 3 V. The capacitance range
of the dual package (anode to anode) is approximately 15.5
pF at 3 V to 1.7 pF at 0.3 V. The desired value of VTUNE applied
to the diode should be VCC/2, or 1.65 V for VCC = 3.3 V. The
typical performance curve from the data sheet for the
SMV1249-074LF indicates that the capacitance at this volt-
age is approximately 6 pF (12 pF / 2).
The nominal input capacitance (CIN) of the LMK04800 family
OSCin pins is 6 pF. The stray capacitance (CSTRAY) of the
PCB should be minimized by arranging the oscillator circuit
layout to achieve trace lengths as short as possible and as
narrow as possible trace width (50 Ω characteristic
impedance is not required). As an example, assume that
CSTRAY is 4 pF. The total load capacitance is nominally:
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LMK04800 Family
(7)
Consequently the load capacitance specification for the crys-
tal in this case should be nominally 14 pF.
The 2.2 nF capacitors shown in the circuit are coupling ca-
pacitors that block the DC tuning voltage applied by the 4.7
kΩ and 10 kΩ resistors. The value of these coupling capaci-
tors should be large, relative to the value of CTUNE (CC1 =
CC2 >> CTUNE), so that CTUNE becomes the dominant capac-
itance.
For a specific value of CL, the corresponding resonant fre-
quency (FL) of the parallel resonant mode circuit is:
(8)
FS = Series resonant frequency
C1 = Motional capacitance of the crystal
CL = Load capacitance
C0 = Shunt capacitance of the crystal, specified on the crystal
datasheet
The normalized tuning range of the circuit is closely approxi-
mated by:
(9)
CL1, CL2 = The endpoints of the circuit’s load capacitance
range, assuming a variable capacitance element is one com-
ponent of the load. FCL1, FCL2 = parallel resonant frequencies
at the extremes of the circuit’s load capacitance range.
A common range for the pullability ratio, C0/C1, is 250 to 280.
The ratio of the load capacitance to the shunt capacitance is
~(n * 1000), n < 10. Hence, picking a crystal with a smaller
pullability ratio supports a wider tuning range because this
allows the scale factors related to the load capacitance to
dominate.
Examples of the phase noise and jitter performance of the
LMK04808 with a crystal oscillator are shown in Table 19.
This table illustrates the clock output phase noise when a
20.48 MHz crystal is paired with PLL1.
TABLE 19. Example RMS Jitter and Clock Output Phase Noise for LMK04808 with a
20.48 MHz Crystal Driving OSCin (T = 25 °C, VCC = 3.3 V) (Note 38)
RMS Jitter (ps)
Integration Bandwidth Clock Output Type
PLL2 PDF = 20.48 MHz
(EN_PLL2_REF2X = 0,
XTAL_LVL = 3)
PLL2 PDF = 40.96 MHz
(EN_PLL2_REF2X = 1, XTAL_LVL = 3)
fCLK = 245.76 MHz fCLK = 122.88 MHz fCLK = 245.76 MHz
100 Hz – 20 MHz
LVCMOS 374 412 382
LVDS 419 421 372
LVPECL 1.6 Vpp 460 448 440
10 kHz – 20 MHz
LVCMOS 226 195 190
LVDS 231 205 194
LVPECL 1.6 Vpp 226 191 188
Phase Noise (dBc/Hz)
Offset Clock Output Type
PLL2 PDF = 20.48 MHz
(EN_PLL2_REF2X = 0,
XTAL_LVL = 3)
PLL2 PDF = 40.96 MHz
(EN_PLL2_REF2X = 1, XTAL_LVL = 3)
fCLK = 245.76 MHz fCLK = 122.88 MHz fCLK = 245.76 MHz
100 Hz
LVCMOS -87 -93 -87
LVDS -86 -91 -86
LVPECL 1.6 Vpp -86 -92 -85
1 kHz
LVCMOS -115 -121 -115
LVDS -115 -123 -116
LVPECL 1.6 Vpp -114 -122 -116
10 kHz
LVCMOS -117 -128 -122
LVDS -117 -128 -122
LVPECL 1.6 Vpp -117 -128 -122
100 kHz
LVCMOS -130 -135 -129
LVDS -130 -135 -129
LVPECL 1.6 Vpp -129 -135 -129
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LMK04800 Family
1 MHz
LVCMOS -150 -154 -148
LVDS -149 -153 -148
LVPECL 1.6 Vpp -150 -154 -148
40 MHz
LVCMOS -159 -162 -159
LVDS -157 -159 -157
LVPECL 1.6 Vpp -159 -161 -159
Note 38: Performance data and crystal specifications contained in this section are based on Vectron model VXB1-1150-20M480, 20.48 MHz. PLL1 has a narrow
loop bandwidth, PLL2 loop parameters are: C1 = 150 pF, C2 = 120 nF, R2 = 470 Ω, Charge Pump current = 3.2 mA, Phase detector frequency = 20.48 MHz or
40.96 MHz, VCO frequency = 2949.12 MHz. Loop filter was optimized for 40.96 MHz phase detector performance.
Example crystal specifications are presented in Table 20.
TABLE 20. Example Crystal Specifications
Parameter Value
Nominal Frequency (MHz) 20.48
Frequency Stability, T = 25 °C ± 10 ppm
Operating temperature range -40 °C to +85 °C
Frequency Stability, -40 °C to +85 °C ± 15 ppm
Load Capacitance 14 pF
Shunt Capacitance (C0) 5 pF Maximum
Motional Capacitance (C1) 20 fF ± 30%
Equivalent Series Resistance 25 Ω Maximum
Drive level 2 mWatts Maximum
C0/C1 ratio 225 typical, 250 Maximum
See Figure 22 for a representative tuning curve.
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
-180
-140
-100
-60
-20
20
60
100
140
180
PPM
VTUNE (V)
30102393
FIGURE 22. Example Tuning Curve, 20.48 MHz Crystal
The tuning curve achieved in the user's application may differ
from the curve shown above due to differences in PCB layout
and component selection.
This data is measured on the bench with the crystal integrated
with the LMK04800 family. Using a voltmeter to monitor the
VTUNE node for the crystal, the PLL1 reference clock input
frequency is swept in frequency and the resulting tuning volt-
age generated by PLL1 is measured at each frequency. At
each value of the reference clock frequency, the lock state of
PLL1 should be monitored to ensure that the tuning voltage
applied to the crystal is valid.
The curve shows over the tuning voltage range of 0.3 VDC to
3.0 VDC, the frequency range is -140 to +91 ppm; or equiv-
alently, a tuning range of -2850 Hz to +1850 Hz. The mea-
sured tuning voltage at the nominal crystal frequency (20.48
MHz) is 1.7 V. Using the diode data sheet tuning character-
istics, this voltage results in a tuning capacitance of approxi-
mately 6.5 pF.
The tuning curve data can be used to calculate the gain of the
oscillator (KVCO). The data used in the calculations is taken
from the most linear portion of the curve, a region centered
on the crossover point at the nominal frequency (20.48 MHz).
For a well designed circuit, this is the most likely operating
range. In this case, the tuning range used for the calculations
is ± 1000 Hz (± 0.001 MHz), or ± 81.4 ppm. The simplest
method is to calculate the ratio:
(10)
ΔF2 and ΔF1 are in units of MHz. Using data from the curve
this becomes:
(11)
A second method uses the tuning data in units of ppm:
(12)
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LMK04800 Family
FNOM is the nominal frequency of the crystal and is in units of
MHz. Using the data, this becomes:
(13)
In order to ensure startup of the oscillator circuit, the equiva-
lent series resistance (ESR) of the selected crystal should
conform to the specifications listed in the table of Electrical
Characteristics.
It is also important to select a crystal with adequate power
dissipation capability, or drive level. If the drive level supplied
by the oscillator exceeds the maximum specified by the crys-
tal manufacturer, the crystal will undergo excessive aging and
possibly become damaged. Drive level is directly proportional
to resonant frequency, capacitive load seen by the crystal,
voltage and equivalent series resistance (ESR). For more
complete coverage of crystal oscillator design, see Applica-
tion Note AN-1939 at http://www.national.com/analog/timing/
clocking or http://www.national.com/appnotes.
18.9 DRIVING CLKin AND OSCin INPUTS
18.9.1 Driving CLKin Pins with a Differential Source
Both CLKin ports can be driven by differential signals. It is
recommended that the input mode be set to bipolar
(CLKinX_BUF_TYPE = 0) when using differential reference
clocks. The LMK04800 family internally biases the input pins
so the differential interface should be AC coupled. The rec-
ommended circuits for driving the CLKin pins with either
LVDS or LVPECL are shown in Figure 23 and Figure 24.
30102381
FIGURE 23. CLKinX/X* Termination for an LVDS
Reference Clock Source
30102387
FIGURE 24. CLKinX/X* Termination for an LVPECL
Reference Clock Source
Finally, a reference clock source that produces a differential
sine wave output can drive the CLKin pins using the following
circuit. Note: the signal level must conform to the require-
ments for the CLKin pins listed in the Electrical Characteristics
table.
30102324
FIGURE 25. CLKinX/X* Termination for a Differential
Sinewave Reference Clock Source
18.9.2 Driving CLKin Pins with a Single-Ended Source
The CLKin pins of the LMK04800 family can be driven using
a single-ended reference clock source, for example, either a
sine wave source or an LVCMOS/LVTTL source. Either AC
coupling or DC coupling may be used. In the case of the sine
wave source that is expecting a 50 Ω load, it is recommended
that AC coupling be used as shown in the circuit below with
a 50 Ω termination.
Note: The signal level must conform to the requirements for the CLKin pins
listed in the Electrical Characteristics table. CLKinX_BUF_TYPE in
Register 11 is recommended to be set to bipolar mode
(CLKinX_BUF_TYPE = 0).
30102322
FIGURE 26. CLKinX/X* Single-ended Termination
If the CLKin pins are being driven with a single-ended LVC-
MOS/LVTTL source, either DC coupling or AC coupling may
be used. If DC coupling is used, the CLKinX_BUF_TYPE
should be set to MOS buffer mode (CLKinX_BUF_TYPE = 1)
and the voltage swing of the source must meet the specifica-
tions for DC coupled, MOS-mode clock inputs given in the
table of Electrical Characteristics. If AC coupling is used, the
CLKinX_BUF_TYPE should be set to the bipolar buffer mode
(CLKinX_BUF_TYPE = 0). The voltage swing at the input pins
must meet the specifications for AC coupled, bipolar mode
clock inputs given in the table of Electrical Characteristics. In
this case, some attenuation of the clock input level may be
required. A simple resistive divider circuit before the AC cou-
pling capacitor is sufficient.
30102385
FIGURE 27. DC Coupled LVCMOS/LVTTL Reference
Clock
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LMK04800 Family
18.10 TERMINATION AND USE OF CLOCK OUTPUT
(DRIVERS)
When terminating clock drivers keep in mind these guidelines
for optimum phase noise and jitter performance:
•Transmission line theory should be followed for good
impedance matching to prevent reflections.
•Clock drivers should be presented with the proper loads.
For example:
—LVDS drivers are current drivers and require a closed
current loop.
—LVPECL drivers are open emitters and require a DC
path to ground.
•Receivers should be presented with a signal biased to
their specified DC bias level (common mode voltage) for
proper operation. Some receivers have self-biasing inputs
that automatically bias to the proper voltage level. In this
case, the signal should normally be AC coupled.
It is possible to drive a non-LVPECL or non-LVDS receiver
with an LVDS or LVPECL driver as long as the above guide-
lines are followed. Check the datasheet of the receiver or
input being driven to determine the best termination and cou-
pling method to be sure that the receiver is biased at its
optimum DC voltage (common mode voltage). For example,
when driving the OSCin/OSCin* input of the LMK04800 fam-
ily, OSCin/OSCin* should be AC coupled because OSCin/
OSCin* biases the signal to the proper DC level (See Figure
19) This is only slightly different from the AC coupled cases
described in Section 18.9.2 Driving CLKin Pins with a Single-
Ended Source because the DC blocking capacitors are
placed between the termination and the OSCin/OSCin* pins,
but the concept remains the same. The receiver (OSCin/OS-
Cin*) sets the input to the optimum DC bias voltage (common
mode voltage), not the driver.
18.10.1 Termination for DC Coupled Differential
Operation
For DC coupled operation of an LVDS driver, terminate with
100 Ω as close as possible to the LVDS receiver as shown in
Figure 28.
30102320
FIGURE 28. Differential LVDS Operation, DC Coupling,
No Biasing of the Receiver
For DC coupled operation of an LVPECL driver, terminate
with 50 Ω to VCC - 2 V as shown in Figure 29. Alternatively
terminate with a Thevenin equivalent circuit (120 Ω resistor
connected to VCC and an 82 Ω resistor connected to ground
with the driver connected to the junction of the 120 Ω and 82
Ω resistors) as shown in Figure 30 for VCC = 3.3 V.
30102318
FIGURE 29. Differential LVPECL Operation, DC Coupling
30102321
FIGURE 30. Differential LVPECL Operation, DC Coupling,
Thevenin Equivalent
18.10.2 Termination for AC Coupled Differential
Operation
AC coupling allows for shifting the DC bias level (common
mode voltage) when driving different receiver standards.
Since AC coupling prevents the driver from providing a DC
bias voltage at the receiver it is important to ensure the re-
ceiver is biased to its ideal DC level.
When driving non-biased LVDS receivers with an LVDS driv-
er, the signal may be AC coupled by adding DC blocking
capacitors, however the proper DC bias point needs to be
established at the receiver. One way to do this is with the ter-
mination circuitry in Figure 31.
30102319
FIGURE 31. Differential LVDS Operation, AC Coupling,
External Biasing at the Receiver
Some LVDS receivers may have internal biasing on the in-
puts. In this case, the circuit shown in Figure 31 is modified
by replacing the 50 Ω terminations to Vbias with a single 100
Ω resistor across the input pins of the receiver, as shown in
Figure 32. When using AC coupling with LVDS outputs, there
may be a startup delay observed in the clock output due to
capacitor charging. The previous figures employ a 0.1 µF ca-
83 www.national.com
LMK04800 Family
pacitor. This value may need to be adjusted to meet the
startup requirements for a particular application.
30102382
FIGURE 32. LVDS Termination for a Self-Biased Receiver
LVPECL drivers require a DC path to ground. When AC cou-
pling an LVPECL signal use 120 Ω emitter resistors close to
the LVPECL driver to provide a DC path to ground as shown
in Figure 33. For proper receiver operation, the signal should
be biased to the DC bias level (common mode voltage) spec-
ified by the receiver. The typical DC bias voltage for LVPECL
receivers is 2 V. A Thevenin equivalent circuit (82 Ω resistor
connected to VCC and a 120 Ω resistor connected to ground
with the driver connected to the junction of the 82 Ω and 120
Ω resistors) is a valid termination as shown in Figure 33 for
VCC = 3.3 V. Note this Thevenin circuit is different from the
DC coupled example in Figure 30.
30102317
FIGURE 33. Differential LVPECL Operation, AC Coupling,
Thevenin Equivalent, External Biasing at the Receiver
18.10.3 Termination for Single-Ended Operation
A balun can be used with either LVDS or LVPECL drivers to
convert the balanced, differential signal into an unbalanced,
single-ended signal.
It is possible to use an LVPECL driver as one or two separate
800 mVpp signals. When using only one LVPECL driver of a
CLKoutX/CLKoutX* pair, be sure to properly terminated the
unused driver. When DC coupling one of the LMK04800 fam-
ily clock LVPECL drivers, the termination should be 50 Ω to
VCC - 2 V as shown in Figure 34. The Thevenin equivalent
circuit is also a valid termination as shown in Figure 35 for Vcc
= 3.3 V.
30102315
FIGURE 34. Single-Ended LVPECL Operation, DC
Coupling
30102316
FIGURE 35. Single-Ended LVPECL Operation, DC
Coupling, Thevenin Equivalent
When AC coupling an LVPECL driver use a 120 Ω emitter
resistor to provide a DC path to ground and ensure a 50 Ω
termination with the proper DC bias level for the receiver. The
typical DC bias voltage for LVPECL receivers is 2 V (See
Section 18.9.2 Driving CLKin Pins with a Single-Ended
Source). If the companion driver is not used it should be ter-
minated with either a proper AC or DC termination. This latter
example of AC coupling a single-ended LVPECL signal can
be used to measure single-ended LVPECL performance us-
ing a spectrum analyzer or phase noise analyzer. When using
most RF test equipment no DC bias point (0 VDC) is required
for safe and proper operation. The internal 50 Ω termination
of the test equipment correctly terminates the LVPECL driver
being measured as shown in Figure 36.
30102314
FIGURE 36. Single-Ended LVPECL Operation, AC
Coupling
www.national.com 84
LMK04800 Family
18.11 POWER SUPPLY
18.11.1 Current Consumption / Power Dissipation
Calculations
From Table 21 the current consumption can be calculated for
any configuration.
For example, the current for the entire device with 1 LVDS
(CLKout0) and 1 LVPECL 1.6 Vpp /w 240 ohm emitter resis-
tors (CLKout1) output active with a clock output divide = 1,
and no other features enabled can be calculated by adding
up the following blocks: core current, clock buffer, one LVDS
output buffer current, and one LVPECL output buffer current.
There will also be one LVPECL output drawing emitter cur-
rent, which means some of the power from the current draw
of the device is dissipated in the external emitter resistors
which doesn't add to the power dissipation budget for the de-
vice but is important for LDO ICC calculations.
For total current consumption of the device, add up the sig-
nificant functional blocks. In this example, 228.1 mA =
•140 mA (core current)
•17.3 mA (base clock distribution)
•25.5 mA (CLKout0 & 1 divider)
•14.3 mA (LVDS buffer)
•31 mA (LVPECL 1.6 Vpp buffer /w 240 ohm emitter
resistors)
Once total current consumption has been calculated, power
dissipated by the device can be calculated. The power dissi-
pation of the device is equation to the total current entering
the device multiplied by the voltage at the device minus the
power dissipated in any emitter resistors connected to any of
the LVPECL outputs. If no emitter resistors are connected to
the LVPECL outputs, this power will be 0 watts. Continuing
the above example which has 228.1 mA total Icc and one
output with 240 ohm emitter resitors. Total IC power = 717.7
mW = 3.3 V * 228.1 mA - 35 mW.
TABLE 21. Typical Current Consumption for Selected Functional Blocks (TA = 25 °C, VCC = 3.3 V)
Block Condition Typical ICC
(mA)
Power
dissipated
in device
(mW)
Power
dissipated
externally
(Note 39)
(mW)
Core and Functional Blocks
Core
MODE = 0: Dual Loop,
Internal VCO PLL1 and PLL2 locked 140 462 -
MODE = 2: Dual Loop,
Internal VCO, 0-Delay
PLL1 and PLL2 locked; Includes
EN_FEEDBACK_MUX = 1 155 512 -
MODE = 3: Dual Loop,
External VCO PLL1 and PLL2 locked 127 419 -
MODE = 5: Dual Loop,
External VCO, 0-Delay
PLL1 and PLL2 locked; Includes
EN_FEEDBACK_MUX = 1 142 469 -
MODE = 6: Single Loop
(PLL2), Internal VCO PLL2 locked 116 383 -
MODE = 11: Single Loop
(PLL2), External VCO PLL2 locked 103 340 -
MODE = 16: Clock
Distribution
PD_OSCin = 0 42 139 -
PD_OSCin = 1 34.5 114 -
EN_TRACK Tracking is enabled (EN_TRACK = 1) 2 6.6 -
Base Clock
Distribution
At least 1 CLKoutX_Y_PD = 0 17.3 57.1 -
CLKout Group Each CLKout group (CLKout0/1 & 10/11, CLKout2/3 & 4/5, CLKout
6/7 & 8/9) 2.8 9.2 -
Clock Divider/
Digital Delay
When a clock output is enabled, this contributes the divider/delay
block 25.5 84.1 -
Divider / digital delay in extended mode 29.6 97.7 -
VCO Divider VCO Divider current 7.7 25.4 -
HOLDOVER
mode
When in holdover mode 2.2 7.2 -
Feedback Mux Feedback mux must be enabled for 0-delay modes and digital
delay mode (SYNC_QUAL = 1) 4.9 16.1 -
SYNC Asserted While SYNC is asserted, this extra current is drawn 1.7 5.6 -
EN_SYNC = 1 Required for SYNC functionality. May be turned off once SYNC is
complete to save power. 6 19.8 -
SYNC_QUAL = 1 Delay enabled, delay > 7 (CLKout_MUX = 2, 3) 8.7 28.7 -
85 www.national.com
LMK04800 Family
Block Condition Typical ICC
(mA)
Power
dissipated
in device
(mW)
Power
dissipated
externally
(Note 39)
(mW)
Crystal Mode Enabling the Crystal
Oscillator
XTAL_LVL = 0 1.8 5.9 -
XTAL_LVL = 1 2.7 9 -
XTAL_LVL = 2 3.6 12 -
XTAL_LVL = 3 4.5 15 -
OSCin Doubler EN_PLL2_REF_2X = 1 2.8 9.2 -
Analog Delay
Analog Delay Value
CLKoutX_Y_ANLG_DLY = 0 to 3 3.4 11.2 -
CLKoutX_Y_ANLG_DLY = 4 to 7 3.8 12.5 -
CLKoutX_Y_ANLG_DLY = 8 to 11 4.2 13.9 -
CLKoutX_Y_ANLG_DLY = 12 to 15 4.7 15.5 -
CLKoutX_Y_ANLG_DLY = 16 to 23 5.2 17.2 -
Only Single Output Of Clock Pair Has Analog Delay Selected.
Example:
CLKout0_ADLY_SEL = 1 and CLKout1_ADLY_SEL = 0, or
CLKout0_ADLY_SEL = 0 and CLKout1_ADLY_SEL = 1.
2.8 9.2 -
Clock Output Buffers
LVDS 100 ohm differential termination 14.3 47.2 -
LVPECL
LVPECL 2.0 Vpp, AC coupled using 240 ohm emitter resistors 32 70.6 35
LVPECL 1.6 Vpp, AC coupled using 240 ohm emitter resistors 31 67.3 35
LVPECL 1.6 Vpp, AC coupled using 120 ohm emitter resistors 46 91.8 60
LVPECL 1.2 Vpp, AC coupled using 240 ohm emitter resistors 30 59 40
LVPECL 0.7 Vpp, AC coupled using 240 ohm emitter resistors 29 55.7 40
LVCMOS
LVCMOS Pair
(CLKoutX_TYPE
= 6 to 9)
CL = 5 pF
3 MHz 24 79.2 -
30 MHz 26.5 87.5 -
150 MHz 36.5 120.5 -
LVCMOS Single
(CLKoutX_TYPE
= 10 to 13)
CL = 5 pF
3 MHz 15 49.5 -
30 MHz 16 52.8 -
150 MHz 21.5 71 -
Note 39: Power is dissipated externally in LVPECL emitter resistors. The externally dissipated power is calculated as twice the DC voltage level of one LVPECL
clock output pin squared over the emitter resistance. That is to say power dissipated in emitter resistors = 2 * Vem2 / Rem.
Note 40: Assuming θJA = 15 °C/W, the total power dissipated on chip must be less than (125 °C – 85 °C) / 16 °C/W = 2.5 W to guarantee a junction temperature
is less than 125 °C.
Note 41: Worst case power dissipation can be estimated by multiplying typical power dissipation with a factor of 1.15.
www.national.com 86
LMK04800 Family
18.12 THERMAL MANAGEMENT
Power consumption of the LMK04800 family of devices can
be high enough to require attention to thermal management.
For reliability and performance reasons the die temperature
should be limited to a maximum of 125 °C. That is, as an es-
timate, TA (ambient temperature) plus device power con-
sumption times θJA should not exceed 125 °C.
The package of the device has an exposed pad that provides
the primary heat removal path as well as excellent electrical
grounding to a printed circuit board. To maximize the removal
of heat from the package a thermal land pattern including
multiple vias to a ground plane must be incorporated on the
PCB within the footprint of the package. The exposed pad
must be soldered down to ensure adequate heat conduction
out of the package.
A recommended land and via pattern is shown in Figure 37.
More information on soldering LLP packages can be ob-
tained: http:// www.national.com/analog/packaging/.
A recommended footprint including recommended solder
mask and solder paste layers can be found at: http://
www.national.com/analog/packaging/gerber for the SQA64
package.
30102373
FIGURE 37. Recommended Land and Via Pattern
To minimize junction temperature it is recommended that a
simple heat sink be built into the PCB (if the ground plane
layer is not exposed). This is done by including a copper area
of about 2 square inches on the opposite side of the PCB from
the device. This copper area may be plated or solder coated
to prevent corrosion but should not have conformal coating (if
possible), which could provide thermal insulation. The vias
shown in Figure 37 should connect these top and bottom
copper layers and to the ground layer. These vias act as “heat
pipes” to carry the thermal energy away from the device side
of the board to where it can be more effectively dissipated.
87 www.national.com
LMK04800 Family
19.0 Physical Dimensions inches (millimeters) unless otherwise noted
20.0 Ordering Information
Order Number Ref
Inputs
Buffered
OSCin
Outputs
Programmable
Outputs VCO Packaging Package
Marking
LMK04803BISQE
2 2 12 1.9 GHz
250 Unit Tape and Reel
K4803LMK04803BISQ 1000 Unit Tape and Reel
LMK04803BISQX 2500 Unit Tape and Reel
LMK04805BISQE
2 2 12 2.2 GHz
250 Unit Tape and Reel
K4805LMK04805BISQ 1000 Unit Tape and Reel
LMK04805BISQX 2500 Unit Tape and Reel
LMK04806BISQE
2 2 12 2.5 GHz
250 Unit Tape and Reel
K4806LMK04806BISQ 1000 Unit Tape and Reel
LMK04806BISQX 2500 Unit Tape and Reel
LMK04808BISQE
2 2 12 2.9 GHz
250 Unit Tape and Reel
K4808LMK04808BISQ 1000 Unit Tape and Reel
LMK04808BISQX 2500 Unit Tape and Reel
www.national.com 88
LMK04800 Family
Notes
89 www.national.com
LMK04800 Family
Notes
LMK04800 Family Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
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