CY7C1011CV33
2-Mbit (128 K × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-05232 Rev. *L Revised June 7, 2011
2-Mbit (128 K × 16) Static RAM
Features
■Temperature ranges
❐Industrial: –40 °C to 85 °C
❐Automotive-A: –40 °C to 85 °C
❐Automotive-E: –40 °C to 125 °C
■Pin and function compatible with CY7C1011BV33
■High speed
❐tAA = 10 ns (Industrial and Automotive-A)
❐tAA = 12 ns (Automotive-E)
■Low active power
❐360 mW (max) (Industrial and Automotive-A)
■2.0 V data retention
■Automatic power down when deselected
■Independent control of upper and lower bits
■Easy memory expansion with Chip Enable (CE) and Output
Enable (OE) features
■Available in Pb-free 44-pin thin small outline package
(TSOP) II, 44-pin thin quad flat package (TQFP), and non
Pb-free 48-ball very fine-pitch ball grid array (VFBGA)
packages
Functional Description
The CY7C1011CV33 is a high performance complementary
metal oxide semiconductor (CMOS) static RAM organized as
131,072 words by 16 bits. This device has an automatic power
down feature that significantly reduces power consumption when
deselected.
To write to the device, take CE and Write Enable (WE) inputs
LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins
(I/O0 through I/O7), is written into the location specified on the
address pins (A0 through A16). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A16).
To read from the device, take CE and OE LOW while forcing the
Write Enable (WE) HIGH. If BLE is LOW, then data from the
memory location specified by the address pins appear on I/O0 to
I/O7. If Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. For more information, see the Truth
Table on page 10 for a complete description of Read and Write
modes.
The input and output pins (I/O0 through I/O15) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW
and WE LOW).
128 K x 16
RAM Array I/O0–I/O7
ROW DECODER
A0
A1
A2
A3
A6
COLUMN DECODER
A10
A11
A12
A13
A14
SENSE AMPS
INPUT BUFFER
OE
A4
A5
I/O8–I/O15
WE
BLE
BHE
A15
A8
A7
A16
CE
A9
Logic Block Diagram
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CY7C1011CV33
Document Number: 38-05232 Rev. *L Page 2 of 17
Contents
Pin Configuration .............................................................3
Selection Guide ................................................................4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
Electrical Characteristics ................................................. 5
Capacitance ...................................................................... 6
Thermal Resistance ..........................................................6
AC Test Loads and Waveforms .......................................6
Switching Characteristics ................................................7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC Solutions ......................................................... 17
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CY7C1011CV33
Document Number: 38-05232 Rev. *L Page 3 of 17
Pin Configuration
Figure 1. 44-pin TSOP II [1] Figure 2. 48-ball VFBGA Pinout [1]
Figure 3. 44-pin TQFP
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
14
A
15
A
8
A
9
A
10
A
11
A
12
A
13
NC
OE
BHE
BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
16
WE
A11
A10
A6
A0
A3CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
A7
I/O0
BHE
NC
NC
A2
A1
BLE
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
326
5
41
D
E
B
A
C
F
G
H
A16
NC
VCC
VCC VSS
WE
V
CC
A11
A10
A6
A0
A3
CE
I/O
10
I/O
8
I/O
9
NC
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A9
A8
OE
V
SS
A7
I/O
0
BHE
A2
A1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A15
A14
A13
A
12
A4
NC
1
A16
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
Note
1. NC pins are not connected on the die.
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CY7C1011CV33
Document Number: 38-05232 Rev. *L Page 4 of 17
Selection Guide
Description -10 -12 Unit
Maximum access time 10 12 ns
Maximum operating current Industrial 100 95 mA
Automotive-A 100 – mA
Automotive-E – 120 mA
Maximum CMOS standby current Industrial 10 10 mA
Automotive-A 10 – mA
Automotive-E – 15 mA
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CY7C1011CV33
Document Number: 38-05232 Rev. *L Page 5 of 17
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied .......................................... –55 C to +125 C
Supply voltage on VCC relative to GND[2].....–0.5 V to +4.6 V
DC voltage applied to outputs
in High Z state[2] .................................. –0.5 V to VCC+ 0.5 V
DC input voltage[2] ............................... –0.5 V to VCC+ 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage .......................................... > 2001 V
(MIL-STD-883, method 3015)
Latch up current ..................................................... > 200 mA
Operating Range
Range Ambient
Temperature (TA)VCC
Industrial –40 C to +85 C 3.3 V 10%
Automotive-A –40 C to +85 C
Automotive -E –40 C to +125 C
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions -10 -12 Unit
Min Max Min Max
VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA 2.4 – 2.4 – V
VOL Output LOW voltage VCC = Min, IOL = 8.0 mA –0.4–0.4V
VIH Input HIGH voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 V
VIL Input LOW voltage[2] –0.3 0.8 –0.3 0.8 V
IIX Input leakage current GND < VI < VCC Industrial –1 +1 –1 +1 A
Automotive-A –1 +1 – –
Automotive-E – – –20 +20
IOZ Output leakage current GND < VI < VCC,
Output disabled
Industrial –1 +1 –1 +1 A
Automotive-A –1 +1 – –
Automotive-E – – –20 +20
ICC VCC operating supply
current
VCC = Max, IOUT = 0 mA,
f = fMAX = 1/tRC
Industrial – 100 – 95 mA
Automotive-A – 100 – –
Automotive-E – – – 120
ISB1 Automatic CE power
down current —TTL
Inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
Industrial – 40 – 40 mA
Automotive-A – 40 – –
Automotive-E – – – 45
ISB2 Automatic CE power
down current — CMOS
inputs
Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or
VIN < 0.3 V, f = 0
Industrial – 10 – 10 mA
Automotive-A – 10 – –
Automotive-E – – – 15
Note
2. VIL (min) = –2.0 V for pulse durations of less than 20 ns.
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CY7C1011CV33
Document Number: 38-05232 Rev. *L Page 6 of 17
Capacitance
Parameter [3] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = 3.3 V 8 pF
COUT Output capacitance 8pF
Thermal Resistance
Parameter [3] Description Test Conditions 44-pin TSOP II 44-pin TQFP 48-ball VFBGA Unit
JA Thermal resistance
(Junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
44.56 42.66 46.98 C/W
JC Thermal resistance
(Junction to case)
10.75 14.64 9.63 C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms [4]
90%
10%
3.0 V
GND
90%
10%
ALL INPUT PULSES
3.3 V
OUTPUT
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
(b)
R 317
R2
351
Rise Time: 1 V/ns Fall Time: 1 V/ns
30 pF*
OUTPUT
Z = 50
50
1.5 V
(c)
(a)
3.3 V
OUTPUT
5 pF
(d)
R 317
R2
351
10-ns devices: 12-ns devices:
High-Z characteristics:
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) for 10-ns parts are tested using the load conditions shown in Figure 4 (a). All other speeds are tested using the Thevenin load shown
in Figure 4 (b). High Z characteristics are tested for all speeds using the test load shown in Figure 4 (d).
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CY7C1011CV33
Document Number: 38-05232 Rev. *L Page 7 of 17
Switching Characteristics
Over the Operating Range
Parameter [5] Description -10 -12 Unit
Min Max Min Max
Read Cycle
tpower[6] VCC (typical) to the first access 1 – 1 – s
tRC Read cycle time 10 – 12 – ns
tAA Address to data valid – 10 – 12 ns
tOHA Data hold from address change 3 – 3 – ns
tACE CE LOW to data valid – 10 – 12 ns
tDOE OE LOW to data valid Industrial/Automotive-A – 5 – 6 ns
Automotive-E – – – 8
tLZOE OE LOW to Low Z[7] 0–0–ns
tHZOE OE HIGH to High Z[7, 8] –5–6ns
tLZCE CE LOW to Low Z[7] 3–3–ns
tHZCE CE HIGH to High Z[7, 8] –5–6ns
tPU CE LOW to power up 0 – 0 – ns
tPD CE HIGH to power down – 10 – 12 ns
tDBE Byte enable to data valid Industrial/Automotive-A – 5 – 6 ns
Automotive-E – – – 8
tLZBE Byte enable to Low Z 0 – 0 – ns
tHZBE Byte disable to High Z – 5 – 6 ns
Write Cycle [9, 10]
tWC Write cycle time 10 – 12 – ns
tSCE CE LOW to write end 7 – 8 – ns
tAW Address setup to write end 7 – 8 – ns
tHA Address hold from write end 0 – 0 – ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 7 – 8 – ns
tSD Data setup to write end 5 – 6 – ns
tHD Data hold from write end 0 – 0 – ns
tLZWE WE HIGH to Low Z[7] 3–3–ns
tHZWE WE LOW to High Z[7, 8] –5–6ns
tBW Byte enable to end of write 7 – 8 – ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V.
6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
7. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of Figure 4 on page 6. Transition is measured 500 mV from steady state voltage
9. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.
The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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CY7C1011CV33
Document Number: 38-05232 Rev. *L Page 8 of 17
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) [11, 12]
Figure 6. Read Cycle No. 2 (OE Controlled) [12, 13]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
tDBE
tLZBE
tHZCE
HIGH
IMPEDANCE
ICC
ISB
OE
CE
ADDRESS
DATA OUT
VCC
SUPPLY
BHE,BLE
CURRENT
Notes
11. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
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CY7C1011CV33
Document Number: 38-05232 Rev. *L Page 9 of 17
Figure 7. Write Cycle No. 1 (CE Controlled) [14, 15]
Figure 8. Write Cycle No. 2 (BLE or BHE Controlled)
Switching Waveforms (continued)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
t
DATA IO
ADDRESS
CE
WE
BHE,BLE
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
DATA I/O
ADDRESS
BHE,BLE
CE
WE
Notes
14. Data I/O is high impedance if OE, BHE, and/or BLE = VIH.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
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CY7C1011CV33
Document Number: 38-05232 Rev. *L Page 10 of 17
Figure 9. Write Cycle No. 3 (WE Controlled, LOW)
Truth Table
CE OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
H X X X X High Z High Z Power down Standby (ISB)
L L H L L Data Out Data Out Read – all bits Active (ICC)
L L H L H Data Out High Z Read – lower bits only Active (ICC)
L L H H L High Z Data Out Read – upper bits only Active (ICC)
L X L L L Data In Data In Write – all bits Active (ICC)
L X L L H Data In High Z Write – lower bits only Active (ICC)
L X L H L High Z Data In Write – upper bits only Active (ICC)
L H H X X High Z High Z Selected, outputs disabled Active (ICC)
Switching Waveforms (continued)
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
tSA
tLZWE
tHZWE
DATA I/O
ADDRESS
CE
WE
BHE,BLE
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CY7C1011CV33
Document Number: 38-05232 Rev. *L Page 11 of 17
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating
Range
10 CY7C1011CV33-10ZSXA 51-85087 44-pin TSOP II (Pb-free) Automotive-A
12 CY7C1011CV33-12AXI 51-85064 44-pin TQFP (Pb-free) Industrial
CY7C1011CV33-12ZSXE 51-85087 44-pin TSOP II (Pb-free) Automotive-E
CY7C1011CV33-12BVXE 51-85150 48-ball (6 × 8 × 1 mm) VFBGA
Temperature range: X = A or I or E
A = Automotive-A; I = Industrial; E = Automotive-E
Pb-free
Package Type: XX = ZS or A or BV
ZS = 44-pin TSOP II
A = 44-pin TQFP
BV = 48-ball VFBGA
Speed grade: XX = 10 ns or 12 ns
V33 = 3.3 V
Process Technology: 150 nm
Bus Width: × 16 bits
Density: 2-Mbit
Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
7CY 1 -XX
XX X
CV33 X
101C
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CY7C1011CV33
Document Number: 38-05232 Rev. *L Page 15 of 17
Acronyms Document Conventions
Units of Measure
Acronym Description
BHE byte high enable
BLE byte low enable
CMOS complementary metal oxide semiconductor
CE chip enable
I/O input/output
OE output enable
SRAM static random access memory
TQFP thin quad flat pack
TSOP thin small outline package
TTL transistor-transistor logic
VFBGA very fine-pitch ball gird array
WE write enable
Symbol Unit of Measure
°C degree Celsius
MHz Mega Hertz
µA micro Amperes
µs micro seconds
mA milli Amperes
mm milli meter
ms milli seconds
mV milli Volts
mW milli Watts
ns nano seconds
% percent
pF pico Farad
VVolts
WWatts
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CY7C1011CV33
Document Number: 38-05232 Rev. *L Page 16 of 17
Document History Page
Document Title: CY7C1011CV33, 2-Mbit (128 K × 16) Static RAM
Document Number: 38-05232
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 117132 07/31/02 HGK New Data Sheet
*A 118057 08/19/02 HGK Pin configuration for 48-ball FBGA correction
*B 119702 10/11/02 DFP Updated FBGA to VFBGA; updated package code on page 8 to BV48A. Updated
address pinouts on page 1 to A0 to A16. Updated CMOS standby current on page 1
from 8 to 10 mA
*C 386106 See ECN PCI Added lead-free parts in Ordering Information Table
*D 498501 See ECN NXR Corrected typo in the Logic Block Diagram on page# 1
Included the Maximum Ratings for Static Discharge Voltage and Latch up Current on
page# 3
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Updated the Ordering Information Table
*E 522620 See ECN VKN Added Thermal Resistance Table
*F 1891366 See ECN VKN/AESA Added -10ZSXA part
Updated Ordering Information table
*G 2428606 See ECN VKN/PYRS Corrected typo in the 44-Pin TSOP and 48-Ball FBGA pinout
Removed Commercial parts
Removed 15 ns speed bin
Removed inactive parts from the Ordering Information table
*H 2664421 02/25/09 VKN/AESA Added Automotive-E specs for 12 ns speed
Updated Ordering Information table
*I 2898399 03/24/2010 KAO/AJU Updated Package Diagrams
*J 2950666 06/11/2010 VKN Included “CY7C1011CV33-12BVXE” in Ordering Information
Added Contents and Acronyms
Updated Sales, Solutions, and Legal Information
Added Ordering Code Definitions.
*K 3089939 11/13/2010 PRAS Removed inactive part from Ordering Information.
*L 3276463 06/07/2011 KAO Updated Functional Description (Removed “For best practice recommendations,
refer to the Cypress application note AN1064, SRAM System Guidelines.”).
Added Units of Measure.
Updated Package Diagrams.
Updated in new template.
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Document Number: 38-05232 Rev. *L Revised June 7, 2011 Page 17 of 17
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1011CV33
© Cypress Semiconductor Corporation, 2002-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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