THCV217-THCV218_Rev.2.20_E THCV217 and THCV218 V-by-One(R) HS High-speed Video Data Transmitter and Receiver General Description THCV217 and THCV218 are designed to support video data transmission between the host and display. One high-speed lane can carry up to 32bit data and 3 bits of synchronizing signals at a pixel clock frequency from 20MHz to 85MHz. The chipset, which has two high-speed data lanes, can transmit video data up to 1080p/10b/60Hz. The maximum serial data rate is 3.4Gbps/lane. Features Color depth selectable: 24(8x3)/32(10x3)bit Single-in/Single-out, Single-in/Dual-out, and Dual-in/Dual-out selectable for THCV217 Single-in/Single-out, Dual-in/Single-out, and Dual-in/Dual-out selectable for THCV218 AC coupling for high-speed lines CORE 1.8V, CMOS IO 3.3V Package: 217(TFBGA105), 218(TFBGA145) Wide frequency range CDR requires no external frequency reference Spread Spectrum Clocking tolerant Up to 30kHz / 0.5% (center spread) V-by-One(R) HS standard Version1.4 compliant. Product Link THCV217 Si/So Di/Do Si/Do Si/So Di/Do Di/So THCV218 Pixel Clock Frequency 20MHz to 85MHz 40MHz to 170MHz 20MHz to 85MHz 40MHz to 170MHz Si/So: Single-in/Single-out, Di/Do: Dual-in/Dual-out Di/So: Dual-in/Single-out, Si/Do: Single-in/Dual-out Block Diagram MODE DEMUX COL BET PRE R/F PDN RX1p RX1n Open Drain HTPDN LOCKN HTPDN LOCKN Controls Copyright(C)2017 THine Electronics,Inc. Controls DGLOCK CMOS CMOS Output TX1p TX1n R1[9:0] G1[9:0] B1[9:0] CONT1[2:1] Deskew & Formatter CML Deserializer RX0p RX0n PLL PLL CLKIN CMOS Input HSYNC VSYNC DE Formatter R2[9:0] G2[9:0] B2[9:0] CONT2[2:1] TX0p TX0n CDR CMOS Serializer Serializer R1[9:0] G1[9:0] B1[9:0] CONT1[2:1] THCV218 Deserializer THCV217 R2[9:0] G2[9:0] B2[9:0] CONT2[2:1] HSYNC VSYNC DE CLKOUT MODE1,0 COL PLL BET R/F DKEN,DK PDN,OE BETOUT 1 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Contents Page General Description................................................................................................................................................. 1 Features ................................................................................................................................................................... 1 Block Diagram ........................................................................................................................................................ 1 Pin Configuration .................................................................................................................................................... 3 Pin Description ........................................................................................................................................................ 5 Functional Description ............................................................................................................................................ 9 Absolute Maximum Ratings .................................................................................................................................. 17 Operating Conditions ............................................................................................................................................ 17 Electrical Specifications ........................................................................................................................................ 18 AC Timing Diagrams and Test Circuits................................................................................................................. 22 THCV217 Input Data Mapping ............................................................................................................................. 27 THCV217 Input Data Mapping (Continued)......................................................................................................... 28 THCV218 Output Data Mapping .......................................................................................................................... 29 THCV218 Output Data Mapping (Continued) ...................................................................................................... 30 Note ....................................................................................................................................................................... 31 Package.................................................................................................................................................................. 32 Notices and Requests............................................................................................................................................. 34 Copyright(C)2017 THine Electronics,Inc. 2 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Pin Configuration THCV217 TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 A B10 B11 G18 G16 G14 G12 G10 R18 R16 R14 R12 A B B12 B13 G19 G17 G15 G13 G11 R19 R17 R15 R13 B C B14 B15 DVDH GND GND VDL VDL HTPDN LOCKN R11 R10 C D B16 B17 DVDH CAVDL CONT11 CONT12 D E B18 B19 DVDH GND GND GND CAVDL TX0n TX0p E F R20 R21 R/F GND GND GND CAVDL TX1n TX1p F G R22 R23 PRE GND GND GND CPVDL CONT21 CONT22 G H R24 R25 COL PDN B29 B28 H J R26 R27 GND DVDH DEMUX Reserved 0 MODE DVDH BET CLKIN DE J K R28 R29 G23 G25 G27 G29 B21 B23 B25 B27 VSYNC K L G20 G21 G22 G24 G26 G28 B20 B22 B24 B26 HSYNC L 1 2 3 4 5 6 7 8 9 10 11 Copyright(C)2017 THine Electronics,Inc. 3 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E THCV218 TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 A HSYNC B19 B17 B15 B13 B11 G19 G17 G15 G13 G11 G10 R19 A B DE VSYNC B18 B16 B14 B12 B10 G18 G16 G14 G12 R18 R17 B C CONT11 CONT12 Reserved 4 Reserved 1 VDL VDL DVDH DVDH DVDH DVDH DVDH R16 R15 C D HTPDN LOCKN Reserved 3 DVDH R14 R13 D E BETOUT Reserved 5 CAVDL GND GND GND GND GND DVDH R12 R11 E F RX0n RX0p CAVDL GND GND GND GND GND DVDH DVDH R10 F G Reserved 6 Reserved 7 CAVDL GND GND GND GND GND GND GND CLKOUT G H RX1n RX1p CAVDL GND GND GND GND GND DVDH CONT22 CONT21 H J MODE1 BET CAVDL GND GND GND GND GND DVDH B29 B28 J K PLL MODE0 DK DVDH B27 B26 K L PDN OE COL DKEN VDL VDL DVDH DVDH DVDH DVDH DVDH B25 B24 L M R/F R21 R23 R25 R27 R29 G21 G23 G25 G27 G29 B23 B22 M N DGLOCK R20 R22 R24 R26 R28 G20 G22 G24 G26 G28 B21 B20 N 1 2 3 4 5 6 7 8 9 10 11 12 13 Copyright(C)2017 THine Electronics,Inc. 4 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Pin Description THCV217 THCV217 Pin Description Name Ball # TX0n,TX0p E10,E11 TX1n,TX1p F10,F11 B8,A8,B9,A9, R19-R10 B10,A10,B11, A11,C10,C11 B3,A3,B4,A4, G19-G10 B5,A5,B6, A6,B7,A7 E2,E1,D2,D1, B19-B10 C2,C1,B2, B1,A2,A1 CONT11,12 D10,D11 K2,K1,J2,J1, R29-R20 H2,H1,G2, G1,F2,F1 K6,L6,K5,L5, G29-G20 K4,L4,K3, L3,L2,L1 H10,H11,K10, B29-B20 L10,K9,L9, K8,L8,K7,L7 CONT21,22 G10,G11 DE J11 HSYNC L11 VSYNC K11 CLKIN J10 Type* Description CO CML output for Lane0 CO CML output for Lane1. Must be left OPEN when not used. I3 1st pixel data inputs I3 1st pixel data inputs I3 1st pixel data inputs I3 User defined data inputs, serialized with 1st pixel data. Active only in 10bit mode. I3 2nd pixel data inputs I3 2nd pixel data inputs I3 2nd pixel data inputs I3 I3 I3 I3 I3 User defined data inputs, serialized with 2nd pixel data. Active only in 10bit mode. DE input Hsync input Vsync input Pixel clock input Hot plug detect input. Must be connected to Rx HTPDN with a 10kW pull-up resistor. Lock detect input. Must be connected to Rx LOCKN with a 10kW pull-up resistor. HTPDN C8 I3L LOCKN C9 I3L *type symbol CO=CML Output I3=3.3V CMOS input, I3L=Low speed 3.3V CMOS input O3=3.3V CMOS output P=1.8V power supply, P3=3.3V power supply Copyright(C)2017 THine Electronics,Inc. 5 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E THCV217 Pin Description (Continued) Name Ball # Type* PDN H9 I3 COL H3 I3 PRE G3 I3 BET J9 I3L DEMUX J5 I3 MODE J7 I3L R/F F3 I3 Reserved0 VDL CAVDL CPVDL DVDH GND Description Power down input H: Normal operation L: Power Down Color depth select input H: 8bit mode L: 10bit mode Pre emphasis level select input H: 100% L: 0% Field BET enable H: Enable L: Normal Operation Operation mode select input DEMUX,MODE=HH: Reserved (Forbidden) HL: Single-in/Dual-out LH: Single-in/Single-out LL: Dual-in/Dual-out Input clock triggering edge select input for latching input data H: Rising edge L: Falling edge Reserved Inputs. Must be tied to GND 1.8V power supply pins for digital circuitry 1.8V power supply pins for CML outputs 1.8V power supply pins for PLL circuitry 3.3V power supply pins for TTL inputs J6 I3 C6,C7 P D9,E9,F9 P G9 P C3,D3,E3,J4,J8 P3 C4,C5,E5,E6,E7,F5, GND Ground pins F6,F7,G5,G6,G7,J3 *type symbol CO=CML Output I3=3.3V CMOS input, I3L=Low speed 3.3V CMOS input O3=3.3V CMOS output P=1.8V power supply, P3=3.3V power supply Copyright(C)2017 THine Electronics,Inc. 6 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E THCV218 THCV218 Pin Description PIN Name Ball # RX0n,RX0p F1,F2 RX1n,RX1p H1,H2 A13,B12,B13, R19-R10 C12,C13,D12, D13,E12,E13,F13 A7,B8,A8,B9, G19-G10 A9,B10,A10, B11,A11,A12 A2,B3,A3,B4, B19-B10 A4,B5,A5, B6,A6,B7 CONT11,12 C1,C2 M6,N6,M5,N5, R29-R20 M4,N4,M3, N3,M2,N2 M11,N11,M10, G29-G20 N10,M9,N9, M8,N8,M7,N7 J12,J13,K12, B29-B20 K13,L12,L13, M12,M13,N12,N13 CONT21,22 H13,H12 DE B1 VSYNC B2 HSYNC A1 CLKOUT G13 Type* Description CI CML input for Lane0 CI CML input for Lane1. Must be left OPEN when not used. O3 1st pixel data outputs O3 1st pixel data outputs O3 1st pixel data outputs O3 User defined data outputs. Active only in 10bit mode. O3 2nd pixel data outputs O3 2nd pixel data outputs O3 2nd pixel data outputs O3 O3 O3 O3 O3 User defined data outputs. Active only in 10bit mode. DE Output Vsync Output Hsync Output Pixel clock output Hot plug detect output. Must be connected to Tx HTPDN with a 10kW pull-up resistor. Hi-Z : when PDN=L, L: when PDN=H Lock detect output. Must be connected to Tx LOCKN with a 10kW pull-up resistor. It drives Low when the CDR locks to the incoming data. Power down input H: Normal operation L: Power Down Color depth select input H: 8bit mode L: 10bit mode Field BET enable H: Enable L: Normal Operation When BET=High, Reserved7 must be Low. Operation mode select input HH: Reserved (Forbidden) HL: Single-in/Single-out LH: Dual-in/Single-out LL: Dual-in/Dual-out HTPDN D1 OD3 LOCKN D2 OD3 PDN L1 I3 COL L3 I3 BET J2 I3L MODE1,0 J1,K2 I3 *type symbol CI=CML Input, OD3=3.3V Open drain output, O3=3.3V CMOS output I3=3.3V CMOS input, I3L=Low speed 3.3V CMOS input, I3PU=3.3V CMOS inout with an on-chip pullup resistor P=1.8v power supply, P3=3.3v power supply Copyright(C)2017 THine Electronics,Inc. 7 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E THCV218 Pin Description (Continued) PIN Name Ball # Type* PLL K1 I3 OE L2 I3 DGLOCK N1 I3PU R/F M1 I3 DKEN L4 I3 DK K3 I3 BETOUT E1 O3 Reserved7 G2 I3 D3 O3 Description PLL bandwidth select H: CLKIN<40MHz, when SiSo,DiDo L: Normal Operation Output enable input (See Table 1 for details) H: All CMOS outputs enabled L: All CMOS outputs disabled, except for LOCKN, HTPDN Connect all DGLOCK pins in multiple-chip configuration. Must be left OPEN for single-chip configuration. Output clock triggering edge select input H: Rising edge L: Falling edge DK enable H: DK enabled L: DK disabled (Default) Output clock delay timing select input. Enabled by DKEN. H: Late L: Early Refer to Figure 10 for details. Field BET result output. Must be left OPEN when NOT used. CTL bit transmission on DE=low blanking period enable H: CTL bit enabled (CTL are transmitted except the 1st and the last pixel of DE=Low) L: CTL bit disabled (CTL are Low fixed during DE=Low) When BET=High, Reserved7 must be Low. Reserved outputs. Must be left OPEN. C4,C3,E2,G1 I3 Reserved input. Must be tied to GND Reserved3 Reserved1, 4-6 VDL CAVDL DVDH GND C5,C6,L5,L6 P 1.8V power supply pins for digital circuitry E3,F3,G3,H3,J3 P 1.8V power supply pins for CML inputs and PLL circuitry C7,C8,C9,C10,C11, D11,E11,F11,F12, P3 3.3V power supply pins for TTL outputs H11,J11,K11,L7, L8,L9,L10,L11 E5,E6,E7,E8,E9,F5, F6,F7,F8,F9,G5,G6, G7,G8,G9,G11, GND Ground pins G12,H5,H6,H7,H8, H9,J5,J6,J7,J8,J9 *type symbol CI=CML Input, OD3=3.3V Open drain output, O3=3.3V CMOS output I3=3.3V CMOS input, I3L=Low speed 3.3V CMOS input, I3PU=3.3V CMOS inout with an on-chip pullup resistor P=1.8V power supply, P3=3.3V power supply PDN OE L L H H L H L H R/G/B/CONT H,Vsync,DE,CLKOUT Hi-Z All Low Hi-Z Data Out Table 1. Output Control Copyright(C)2017 THine Electronics,Inc. 8 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Functional Description Functional Overview With V-by-One(R)HS's proprietary encoding scheme and CDR (Clock and Data Recovery) architecture, THCV217 and THCV218 enable transmission of 8/10 bit RGB, 2bits of user-defined data (CONT), synchronizing signals HSYNC, VSYNC, and DE by single/dual differential pair cable with minimal external components. THCV217, the transmitter, inputs CMOS data (including video data, CONT, HSYNC, VSYNC, and DE) and serializes video data and synchronizing signals separately, depending on the polarity of DE. DE is a signal which indicates whether video or synchronizing data are active. When DE is high, it serializes video data inputs into differential data streams. And it transmits serialized synchronizing data when DE is low. Figure 1 is the conceptual diagram of the basic operation of the chipset. THCV218, the receiver, automatically extracts the clock from the incoming data streams and converts the serial data into video data with DE being high or synchronizing data with DE being low, recognizing which type of serial data is being sent by the transmitter. And it outputs the recovered data in the form of CMOS data. THCV218 can operate for a wide range of a serial bit rate from 600Mbps to 3.4Gbps/channel. Figure 2 shows the timing diagram of the basic operation of the chipset. It does not need any external frequency reference, such as a crystal oscillator. Data Enable There are some requirements for DE signal as described in Figure 1, Figure 2, and Table 18. If DE=Low, control data of same cycle and possibly particular assigned data bit `CTL' except the first and the last pixel are transmitted. Otherwise video data are transmitted during DE=High. Control data from receiver in DE=High period are previous data of DE transition. See Figure 2. The length of DE being low and high is at least 2 clock cycles long, as described in Table 18. Data Enable must be toggled like High -> Low -> High at regular interval. CTL bit transmission There are particular assigned data bit `CTL' which can be transmitted both on DE=High and on DE=Low except the first and the last pixel on DE=Low. This function is enabled by setting THCV218 Reserved7 pin to High. THCV217 THCV218 DE=H, R/G/B,CONT DE=L, CTL* except the 1st and the last pixel other R/G/B,CONT=Low Fixed Data bit : R/G/B, CONT H Control bit : V,HSYNC Data bit : CTL* R/G/B, CONT, CTL DE=H, V,HSYNC=Fixed DE=L, V,HSYNC L V,HSYNC DE DE *CTL are particular assigned bit among R/G/B, CONT that can carry arbitrary data during DE=Low period. *CTL bit transmission is activated by setting THCV218 Reserved7 pin to High. Figure 1. Conceptual diagram of the basic operation of the chipset Copyright(C)2017 THine Electronics,Inc. 9 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E tDEH THCV217 DE Low Blanking period H,V SYNC Valid Data R/G/B CONT tTCIP tDEL Low Blanking period High Active period Invalid Valid Data Invalid Valid Data DE Low Blanking period H,V SYNC Valid Data R/G/B CONT Low tRCP tDEL Low Blanking period High Active period Keep the last data of DE=Low period Valid Data Valid Data Valid Data tDEH THCV218 Low Blanking period High Active period Keep the last data of DE=Low period Valid Data Low Low Blanking period High Active period Low Valid Data Valid Data Low Particular assigned bits `CTL' are transmitted except the first and last pixel of blanking (DE=Low) period when THCV218 Reserved7 pin is set to High. /Others are Low fixed. Figure 2. Data and synchronizing signals transmission timing diagram tDEINT tTCIP CLKIN DE tDEH Note: tDEL The period between rising edges of DE(tDEINT),high time of DE(tDEH) should always satisfy following equations. tDEH = tTCIP x (2m) tDEINT = tTCIP x (2n) tDEL >= 4tTCIP (This tDEL rule is only in SiDo mode.) m,n = positive integer, mn Requirement for DE minimum length limitation is described in Table 18. Figure2-1. DE input timing Copyright(C)2017 THine Electronics,Inc. 10 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Operation Mode and Color Depth Mode function THCV217 and 218 support a variety of operation modes to optimize power consumption, number of PCB traces, or signal integrity. Refer to Table 2, Table 3, and Figure 3 for details. CMOS Input CLKIN Range # of data CML Output TX0/1 Range # of lanes 10bit Dual-in/Dual-out 20 to 85 MHz (32+3)x2 0.8 to 3.4Gbps 2 10bit Single-in/Single-out 20 to 85 MHz (32+3)x1 0.8 to 3.4Gbps 1 L H 10bit Single-in/Dual-out Reserved (Forbidden) 40 to 170 MHz - (32+3)x1 - 0.8 to 3.4Gbps - 2 - L L 8bit Dual-in/Dual-out 20 to 85 MHz (24+3)x2 0.6 to 2.55Gbps 2 L H 8bit Single-in/Single-out 20 to 85 MHz (24+3)x1 0.6 to 2.55Gbps 1 H H L 8bit Single-in/Dual-out 40 to 170 MHz (24+3)x1 0.6 to 2.55Gbps 2 H H H Reserved (Forbidden) - - - - COL DEMUX MODE L L L L L H L L H H H H Description Table 2. THCV217 operation mode select MODE0 Description CML Input RX0/1 Range # of lanes CMOS Output CLKOUT Range # of data COL MODE1 L L L 10bit Dual-in/Dual-out 0.8 to 3.4Gbps 2 20 to 85 MHz (32+3)x2 L L H 10bit Dual-in/Single-out 0.8 to 3.4Gbps 2 40 to 170 MHz (32+3)x1 L L H H L H 10bit Single-in/Single-out Reserved (Forbidden) 0.8 to 3.4Gbps - 1 - 20 to 85 MHz - (32+3)x1 - H L L 8bit Dual-in/Dual-out 0.6 to 2.55Gbps 2 20 to 85 MHz (24+3)x2 H L H 8bit Dual-in/Single-out 0.6 to 2.55Gbps 2 40 to 170 MHz (24+3)x1 H H L 8bit Single-in/Single-out 0.6 to 2.55Gbps 1 20 to 85 MHz (24+3)x1 H H H Reserved (Forbidden) - - - - Table 3. THCV218 operation mode select Copyright(C)2017 THine Electronics,Inc. 11 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E THCV217 217 85MHz THCV218 3.4/2.55Gbps 3.4/2.55Gbps 3.4/2.55Gbps 3.4/2.55Gbps 218 85MHz DiDo 85MHz 85MHz 85MHz 217 3.4/2.55Gbps 3.4/2.55Gbps 218 85MHz SiDo 170MHz 217 3.4/2.55Gbps DiSo 3.4/2.55Gbps 218 170MHz 3.4/2.55Gbps 3.4/2.55Gbps SiSo SiDo/ DiSo Figure 3. Operation modes of the chipset (10bit/8bit) CML Buffer THCV217 CAVDL THCV218 CAVDL 50 C=75 200nF TXn + C=75 200nF Zdiff=100 TXn n=0,1 RXn + RXn n=0,1 50 Vterm1.3v CAGND CML Transmitter CML Receiver Figure 4. CML buffer scheme Copyright(C)2017 THine Electronics,Inc. 12 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Lock Detect and Hot-Plug Function LOCKN and HTPDN of Rx must be connected with those of Tx as in Figure 5. LOCKN and HTPDN on THCV218 are both open drain outputs. Pull-up resistors are needed at Tx side. If THCV218 is not active (in the power down mode, powered off, or not connected), THCV218's HTPDN turns high-Z, and the pull-up resister at the Tx side makes the HTPDN input of THCV217 high. THCV217 then enters into the power down mode. When THCV218 is active, HTPDN is pulled down by THCV218. Then THCV217 starts up and transmits the "training pattern" for link training. LOCKN indicates whether THCV218 is in the lock state or not. If THCV218 is not the lock state, LOCKN turns high-Z. Otherwise (in the lock state), it's pulled down by THCV218. THCV217 keeps transmitting the "training pattern" until LOCKN turns low. And then THCV217 starts transmitting serialized input data. Power supply for HTPDN (Tx side) THCV217 THCV218 HTPDN 10k Power supply for LOCKN (Tx side) 10k LOCKN Figure 5. Hot-plug and Lock detect scheme HTPDN connection between THCV217 and THCV218 can be omitted as an application option. In this case, HTPDN at the Transmitter side should always be taken as Low. See Figure 6. THCV217 THCV218 HTPDN HTPDN Power supply for LOCKN (Tx side) 10k LOCKN Figure 6. HTPDN is not connected scheme Copyright(C)2017 THine Electronics,Inc. 13 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Pre-emphasis Pre-emphasis can equalize severe signal degradation caused by long-distance or high-speed transmission. The PRE pin selects the strength of pre-emphasis. See Table 4. PRE Description H w/ 100% Pre-emphasis L w/o Pre-emphasis Table 4. Pre-emphasis function table Power Down Function Setting the PDN pin low places THCV217 in the power-down mode. All the internal circuitry turns off and the TXmp/n (m=0, 1) outputs turn to CAVDL. Setting the PDN pin low places THCV218 in the power-down mode. All the internal circuitry turns off and the CMOS outputs drives low. Copyright(C)2017 THine Electronics,Inc. 14 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Field BET Operation In order to help users to debug high-speed serial links (CML lines), THCV217 and THCV218 have an operation mode in which they act as the bit error tester (BET). In this mode, THCV217 internally generates a test pattern, which is then serialized onto CML high-speed lines. THCV218 receives the data stream and checks the sampled data for bit errors. This "Field BET" mode is activated by setting BET= H on THCV217, and BET=H and Reserved7=L on THCV218. In the Field BET mode, the on-chip pattern generator on THCV217 is enabled and generates the test pattern as long as the clock is applied onto CLKIN. Other CMOS data inputs are ignored. The generated data pattern is then 8b/10b encoded, scrambled, and serialized onto CML channels. As for THCV218, the internal test pattern check circuit gets enabled and the pattern check result is output on BETOUT. The BETOUT pin goes LOW whenever bit errors occur, and it stays HIGH when there is no bit error. Please refer to Figure 7 and Figure 8. Table 5 shows possible combinations of Tx and Rx for normal operation and Field BET operation. THCV217 THCV218 TTL data inputs are ignored CLKIN Test Pattern Generator BET=H Test Pattern Checker BETOUT BET=H Reserved7=L Test Point for Field BET Figure 7. Field BET Configuration Normal Operation Field BET Operation THCV217,218 BET Bit Error Bit Error RXmp/n m=0,1 BETOUT Figure 8. Relationship between bit error and BETOUT Tx Rx 1 THCV217 THCV218 2 THCV215 THCV218 3 THCV217 THCV216 Table 5. Possible combinations of Tx and Rx for Field BET mode Copyright(C)2017 THine Electronics,Inc. 15 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E DGLOCK In order to reduce the number of cables needed for HTPDN and LOCKN in multiple-Rx chip configuration, THCV218 is equipped with the DGLOCK pin. When all the DGLOCK pins are connected as in Figure 9, the connected Rx chips can share the CDR lock status, making all the Rx chips in the same operation status. HTPDN HTPDN LOCKN LOCKN RX0p/n V-by-One Tx V-by-One Rx RX1p/n DGLOCK RX2p/n RX3p/n Open Open HTPDN LOCKN V-by-One Rx DGLOCK Figure 9. Usage of DGLOCK in multiple-Rx configuration PLL Frequency Range Select The THCV218's PLL input pin selects the operating frequency range of THCV218. Table 6 shows the selectable frequency ranges for operation modes. Operation Mode PLL CLKOUT H 20 to 40MHz L 40 to 85MHz H Forbidden L 40 to 170MHz H 20 to 40MHz L 40 to 85MHz Dual-in/Dual-out Dual-in/Single-out Single-in/Single-out Table 6. Frequency range select Copyright(C)2017 THine Electronics,Inc. 16 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Absolute Maximum Ratings Parameter 1.8V Supply Voltage VDL,CAVDL,CPVDL 3.3V Supply Voltage (DVDH) CMOS Intput Voltage CML Transmitter Output Voltage CML Output Current Storage Temperature Junction Temperature Reflow Peak Temperature/Time Maximum Power Dissipation @+25 Min. -0.3 -0.3 -0.3 -0.3 -50 -55 - Typ. 2.47 Max. +2.1 +4.0 DVDH+0.3 CAVDL+0.3 50 +125 +125 +260/10sec Units V V V V mA W Max. +2.1 +4.0 DVDH+0.3 DVDH+0.3 +4.0 CAVDL+0.3 +125 +125 +260/10sec Units V V V V V V W Typ. 1.80 3.30 - Max. 1.98 3.60 85 Units V V Typ. 1.80 3.30 - Max. 1.98 3.60 85 Units V V Table 7. THCV217 Absolute Maximum Ratings Parameter 1.8V Supply Voltage (VDL,CAVDL) 3.3V Supply Voltage (DVDH) CMOS Input Voltage CMOS Output Voltage CMOS Open drain Output Voltage CML Receiver Input Voltage Storage Temperature Junction Temperature Reflow Peak Temperature/Time Maximum Power Dissipation @+25 Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 - Typ. 2.7 Table 8. THCV218 Absolute Maximum Ratings Operating Conditions Prameter 1.8V Supply VoltageVDL,CAVDL,CPVDL 3.3V Supply Voltage(DVDH) Operating Temperature Min. 1.62 3.00 -20 Table 9. THCV217 Operating Conditions Parameter 1.8V Supply VoltageVDL,CAVDL,CPVDL 3.3V Supply Voltage(DVDH) Operating Temperature Min. 1.62 3.00 -20 Table 10. THCV218 Operating Conditions "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Copyright(C)2017 THine Electronics,Inc. 17 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Electrical Specifications 3.3V CMOS DC Specifications Symbol Parameter VIH High Level Input Voltage VIL Low Level Input Voltage VOH High Level Output Voltage VOL Low Level Output Voltage IIH IIL IOZH IOZL Input Leak Current High Input Leak Current Low Output Leak Current High in High-Z state Output Leak Current Low in High-Z state Conditions I3,I3PU I3L I3,I3PU I3L O3 IOH=-8mA O3 IOL=8mA OD3,I3PU IOL=4mA VIN=DVDH VIN=0V VIN=DVDH, OE=L VIN=0V, OE=L Min. 2.0 2.0 0 0 2.4 - Typ. - Max. DVDH DVDH 0.8 0.7 0.4 0.4 10 10 10 10 Units V V V V V V V uA uA uA uA Table 11. THCV217and THCV218 3.3V CMOS DC Specifications CML DC Specifications Symbol VTOD PRE VTOC ITOH ITOS Parameter CML Differential Mode Output Voltage CML Pre-emphasis Level CML Common Mode Output Voltage CML Output Leak Current High CML Output Short Circuit Current Conditions Min. Typ. Max. Units PRE=L 200 300 400 mV PRE=L PRE=H PRE=L PRE=H PDN=H CAVDL=1.8V 80 0 100 CAVDL-VTOD CAVDL-2xVTOD - 120 10 - % % mV mV uA mA -90 Table 12. THCV217 CML DC Specifications Symbol Parameter Conditions Min. Typ. Max. Units VRTH CML Differential Input High Threshold - - 50 mV VRTL CML Differential Input Low Threshold -50 - - mV IRIH CML Input Leak Current High PDN=L, RX0/1=CAVDL - - 10 uA IRIL CML Input Leak Current Low PDN=L,RX0/1=0V - - 10 uA IRRIH CML Input Current High RX0/1=CAVDL - - 2 mA IRRIL CML Input Current Low RX0/1=0V -6 - - mA RRIN CML Differential Input Resistance 80 100 120 Table 13. THCV218 CML DC Specifications Copyright(C)2017 THine Electronics,Inc. 18 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Supply Currents Symbol Parameter Transmitter Supply Current for ITCCW VDL, CAVDL, CPVDL (Worst Case Pattern) Transmitter Supply Current for ITCCW33 DVDH (Worst Case Pattern) Transmitter Power Down ITCCS Supply Current conditions DiDo 10bit PRE = H SiSo 10bit PRE = H SiDo 10bit PRE = H DiDo 10bit PRE = H SiSo 10bit PRE = H SiDo 10bit PRE = H PDN = L Input = Fixed L or H Min. - Typ. - Max. 185 115 180 10 7 10 200 Table 14. THCV217 Supply Currents Symbol Parameter Receiver Supply Current for IRCCW VDL, CAVDL (Worst Case Pattern) Receiver Supply Current for IRCCW33 DVDH (Worst Case Pattern) IRCCS Conditions DiDo 10bit SiSo 10bit DiSo 10bit DiDo 10bit CL=8pF SiSo 10bit CL=8pF DiSo 10bit CL=8pF PDN = L Input = Fixed L or H Receiver Power Down Supply Current Min. - Typ. - Max. 180 95 170 200 100 200 Unit mA mA mA mA mA mA - - 200 uA Table 15. THCV218 Supply Currents Copyright(C)2017 THine Electronics,Inc. 19 THine Electronics, Inc. Security E Units mA mA mA mA mA mA uA THCV217-THCV218_Rev.2.20_E Switching Characteristics Symbol tTRF tTOSK Parameter TX0/1 Rise and Fall Time (20%-80%) TX0/1 Output Inter Pair Skew SiSo, DiDo SiDo tTCIP CLKIN Period tTCH tTCL tTS tTH CLK IN High Time CLK IN Low Time CMOS Data Setup to CLK IN CMOS Data Hold to CLK IN tTCD Input Clock to Output Data Delay tTPD tTPLL0 tTPLL1 tTNP0 tTNP1 Conditions SiSo / DiDo 8bit SiSo / DiDo 10bit SiDo 8bit SiDo 10bit Min. Typ. Max. Units 50 - 150 ps -2 11.76 5.88 0.35xtTCIP 0.35txTCIP 2.0 0.5 2 50 25 0.65xtTCIP 0.65xtTCIP - UI ns ns ns ns ns ns 0 - 0.5xtTCIP 0.5xtTCIP (13+7/10)xtTCIP 13xtTCIP (21+4/10)xtTCIP 20xtTCIP - - typ.-10 typ.-10-tTCIP Power On to PDN High Delay PDN High to CML Output Delay PDN Low to CML Output High Fix Delay LOCKN High to Training Pattern Output Delay LOCKN Low to Data Pattern Output Delay typ.+10 ns typ.+10+tTCIP 10 ns ms - 20 ns - - 10 ms - - 10 ms Table 16. THCV217 Switching Characteristics Copyright(C)2017 THine Electronics,Inc. 20 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Symbol Parameter Conditions COL=L COL=H tRBIT Unit Interval tRISK tRCP RX0/1 Input Inter Pair Skew Margin CLKOUT Period tRCH tRCL tDOUT tRS tRH CLKOUT High Time CLKOUT Low Time CMOS Data OUT Period CMOS Data Setup to CLKOUT CMOS Data Hold to CLKOUT tDK CLKOUT Delay Time tTLH tTHL tRDC tRPD tRHPD0 tRHPD1 tRPLL0 tRPLL1 tRLCK0 tRLCK1 CMOS Low to High Transition Time CMOS High to Low Transition Time Input Data to Output Clock Delay SiSo, DiDo DiSo PLL=H PLL=L Clock Data Clock Data SiSo/DiDo 8bit PLL=L SiSo/DiDo 10bit PLL=L SiSo/DiDo 8bit PLL=H SiSo/DiDo 10bit PLL=H DiSo 8bit DiSo 10bit Power On to PDN High Delay PDN High to HTPDN Low Delay PDN Low to HTPDN High Delay Training Pattern Input to LOCKN Low Delay PDN Low to LOCKN High Delay Low to TTL Output LOCKN Delay LOCKN High to TTL Low-fixed Delay Min. 294 392 11.76 5.88 0.45xtRCP-0.45 0.45xtRCP-0.45 - Typ. T Max. 1250 1667 15 50.0 25.0 1.0 2.0 1.0 2.0 Units ps ps UI ns ns ns ns ns ns ns ns ns ns ns ns ns typ.+10 ns 1 1 ns us us 0 - T/2 T/2 T 3T/16 3T/32 0.7 1.4 0.7 1.4 (18+5/10)xtRCP 18xtRCP (16+4/10)xtRCP (15+7/10)xtRCP (39+5/10)xtRCP 38txRCP - - - 10 ms - - 10 5 0 us ms ns Typ. - Max. - Units sec sec sec typ.-10 Table 17. THCV218 Switching Characteristics Symbol Parameter tDEH DE=High Duration tDEL DE=Low Duration Conditions Min. 2xtTCIP 2xtTCIP 4xtTCIP SiSo, DiDo SiDo, DiSo Table 18. DE requirement Copyright(C)2017 THine Electronics,Inc. 21 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E AC Timing Diagrams and Test Circuits CMOS Input Switching Characteristics tTCIP tTCH R/F=L CLKIN DVDH/2 DVDH/2 DVDH/2 R/F=H tTCL tTS Rx.Gx,Bx x=29-20,19-10 HSYNC,VSYNC DE CONT11,12 CONT21,22 tTH DVDH/2 DVDH/2 Figure 10. CMOS Input Switching Timing Diagrams Copyright(C)2017 THine Electronics,Inc. 22 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E CMOS Output Switching Characteristics RD = 39 80% Test Point CL = 8pF 20% tTLH tTHL tRCL tRCH tRCP R/F=L CLKOUT DKEN=L DVDH/2 DVDH/2 DVDH/2 R/F=H R/F=H CLKOUT DKEN=H DK=L DVDH/2 R/F=L tDK R/F=L CLKOUT DKEN=H DK=H DVDH/2 R/F=H tDK Rx.Gx,Bx x=29-20,19-10 HSYNC,VSYNC DE CONT11,12 CONT21,22 tRS tRH DVDH/2 DVDH/2 tDOUT Figure 11. CMOS Output Switching Timing Diagrams and Test Circuit Copyright(C)2017 THine Electronics,Inc. 23 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E CML Output Switching Characteristics 75200nF 50 75200nF 50 TXmp TXmn m=0,1 < 5mm 80% Vdiff = (TXmp) - (TXmn) m=0,1 20% tTRF tTRF Vdiff = (TX0p) - (TX0n) Vdiff = 0V tTOSK Vdiff = 0V Vdiff = (TX1p) - (TX1n) Figure 12. CML Output Switching Timing Diagrams and Test Circuit CML Input Switching Characteristics Vdiff = 0V Vdiff = (RX0p) - (RX0n) tRISK Vdiff = (RX1p) - (RX1n) Vdiff = 0V Figure 13. CML Input Timing Diagrams Copyright(C)2017 THine Electronics,Inc. 24 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Latency Characteristics R/F=L CLKIN DVDH/2 R/F=H Rx.Gx,Bx x=29-20,19-10 HSYNC,VSYNC DE CONT11,12 CONT21,22 DVDH/2 DVDH/2 tTCD tTCIP Vdiff = (TX0p) - (TX0n) pixel 1st bit pixel 1st bit tTCIP Vdiff = (RX0p) - (RX0n) tRDC R/F=L CLKOUT DKEN=L DVDH/2 DVDH/2 R/F=H Rx.Gx,Bx x=29-20,19-10 HSYNC,VSYNC DE CONT11,12 CONT21,22 DVDH/2 Figure 14. THCV217 and THCV218 Latency Copyright(C)2017 THine Electronics,Inc. 25 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Lock and Unlock Sequence VDL CAVDL CPVDL DVDH 1.5v Power On CLKIN Rx/Gx/Bx CONTy HTPDN Data Pattern Low-level tTPD PDN LOCKN tTPLL0 TXn Fix to CAVDL tTNP0 tTNP1 CDR Training ALN Training pattern Pattern Normal pattern tTPLL1 CDR Training pattern Normal pattern x=29-20,19-10 y=22,21,12,11 n=1,0 VDL CAVDL DVDH PDN 1.5v Power On tRPD tRHPD0 tRHPD1 HTPDN CDR Training ALN Training Pattern Pattern RXn Normal pattern tRPLL0 tRPLL1 LOCKN tRLCK1 tRLCK0 CLKOUT Rx/Gx/Bx CONTy Low Low Valid Data Pattern Low Low Figure 15. THCV217 and THCV218 Lock and Unlock Sequence tTPD and tRPD minimum is 0sec; therefore, PDN can be applied at the same time as VDL, CAVDL, CPVDL and DVDH. tTPLL0 is the time from "both PDN=High and HTPDN=Low" moment to Training pattern ignition. HTPDN could transit from High to Low under PDN=High condition at THCV217, which is different from what Figure 15 indicates but is natural situation. Note: When change and discontinuation occur in the clock frequency to THCV217, in order to collateralize the operation after clock frequency change or return, please insert a Low pulse to the PDN pin of THCV218 to reset the internal PLL. Copyright(C)2017 THine Electronics,Inc. 26 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E THCV217 Input Data Mapping Data Signals Transm itter Input Pin Nam e 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) R0*1 R1*1 R2 R3 R4 R5 R6 R7 R8 R9 G0*1 G1*1 G2 G3 G4 G5 G6 G7 G8 G9 B0*1 B1*1 B2*1 B3*1 B4*1 B5*1 B6*1 B7*1 B8*1 B9*1 CONT1*1*2 CONT2*1*2 HSYNC VSYNC DE R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0*1 B1*1 B2*1 B3*1 B4*1 B5*1 B6*1 B7*1 HSYNC VSYNC DE R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 CONT11 CONT12 HSYNC VSYNC DE R12 R13 R14 R15 R16 R17 R18 R19 G12 G13 G14 G15 G16 G17 G18 G19 B12 B13 B14 B15 B16 B17 B18 B19 HSYNC VSYNC DE Sym bol defined by V-by-One(R) HS D30 D31 D0 D1 D2 D3 D4 D5 D6 D7 D28 D29 D8 D9 D10 D11 D12 D13 D14 D15 D26 D27 D16 D17 D18 D19 D20 D21 D22 D23 D25 D24 HSYNC VSYNC DE *1 CTL bits, which are carried during DE=Low except the 1st and the last pixel. *2 3D flags defined in the V-by-One(R) HS Standard are assigned to the following bit. V-by-One(R) HS Standard Packer/Unpacker D[24](3DLR) <=> CONT2 V-by-One(R) HS Standard Packer/Unpacker D[25](3DEN) <=> CONT1 Table 19. CMOS Input Data Mapping for Single-in/Single-out, Single-in/Dual-out mode Copyright(C)2017 THine Electronics,Inc. 27 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E THCV217 Input Data Mapping (Continued) 1st Pixel Data Data Signals 2nd Pixel Data Transm itter Input Pin Nam e Data Signals Transm itter Input Pin Nam e 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) R10*1 R11*1 R12 R13 R14 R15 R16 R17 R18 R19 G10*1 G11*1 G12 G13 G14 G15 G16 G17 G18 G19 B10*1 B11*1 B12*1 B13*1 B14*1 B15*1 B16*1 B17*1 B18*1 B19*1 CONT11*1*2 CONT12*1*2 HSYNC VSYNC DE R10 R11 R12 R13 R14 R15 R16 R17 G10 G11 G12 G13 G14 G15 G16 G17 B10*1 B11*1 B12*1 B13*1 B14*1 B15*1 B16*1 B17*1 HSYNC VSYNC DE R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 CONT11 CONT12 HSYNC VSYNC DE R12 R13 R14 R15 R16 R17 R18 R19 G12 G13 G14 G15 G16 G17 G18 G19 B12 B13 B14 B15 B16 B17 B18 B19 HSYNC VSYNC DE R20*1 R21*1 R22 R23 R24 R25 R26 R27 R28 R29 G20*1 G21*1 G22 G23 G24 G25 G26 G27 G28 G29 B20*1 B21*1 B22*1 B23*1 B24*1 B25*1 B26*1 B27*1 B28*1 B29*1 CONT21*1*2 CONT22*1*2 - R20 R21 R22 R23 R24 R25 R26 R27 G20 G21 G22 G23 G24 G25 G26 G27 B20*1 B21*1 B22*1 B23*1 B24*1 B25*1 B26*1 B27*1 - R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 CONT21 CONT22 - R22 R23 R24 R25 R26 R27 R28 R29 G22 G23 G24 G25 G26 G27 G28 G29 B22 B23 B24 B25 B26 B27 B28 B29 - Sym bol defined by V-by-One(R) HS D30 D31 D0 D1 D2 D3 D4 D5 D6 D7 D28 D29 D8 D9 D10 D11 D12 D13 D14 D15 D26 D27 D16 D17 D18 D19 D20 D21 D22 D23 D25 D24 HSYNC VSYNC DE *1 CTL bits, which are carried during DE=Low except the 1st and the last pixel. *2 3D flags defined in the V-by-One(R) HS Standard are assigned to the following bit. V-by-One(R) HS Standard Packer/Unpacker D[24](3DLR) <=> CONT12/CONT22 V-by-One(R) HS Standard Packer/Unpacker D[25](3DEN) <=> CONT11/CONT21 Table 20. CMOS Input Data Mapping for Dual-in/Dual-out mode Copyright(C)2017 THine Electronics,Inc. 28 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E THCV218 Output Data Mapping Receiver Output Pin Nam e Data Signals Sym bol defined by V-by-One(R) HS 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) R0*1 R1*1 R2 R3 R4 R5 R6 R7 R8 R9 R0 R1 R2 R3 R4 R5 R6 R7 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R12 R13 R14 R15 R16 R17 R18 R19 D30 D31 D0 D1 D2 D3 D4 D5 D6 D7 G0*1 G1*1 G2 G3 G4 G5 G6 G7 G8 G9 G0 G1 G2 G3 G4 G5 G6 G7 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G12 G13 G14 G15 G16 G17 G18 G19 D28 D29 D8 D9 D10 D11 D12 D13 D14 D15 B0*1 B1*1 B2*1 B3*1 B4*1 B5*1 B6*1 B7*1 B8*1 B9*1 B0*1 B1*1 B2*1 B3*1 B4*1 B5*1 B6*1 B7*1 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B12 B13 B14 B15 B16 B17 B18 B19 D26 D27 D16 D17 D18 D19 D20 D21 D22 D23 CONT1*1*2 CONT2*1*2 - CONT11 CONT12 - D25 D24 HSYNC VSYNC DE HSYNC VSYNC DE HSYNC VSYNC DE HSYNC VSYNC DE HSYNC VSYNC DE *1 CTL bits, which are carried during DE=Low except the 1st and the last pixel. *2 3D flags defined in the V-by-One(R) HS Standard are assigned to the following bit. V-by-One(R) HS Standard Packer/Unpacker D[24](3DLR) <=> CONT2 V-by-One(R) HS Standard Packer/Unpacker D[25](3DEN) <=> CONT1 Table 21. CMOS Output Data Mapping for Single-in/Single-out, Dual-in/Single-out mode Copyright(C)2017 THine Electronics,Inc. 29 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E THCV218 Output Data Mapping (Continued) 1st Pixel Data Receiver Output Pin Nam e Data Signals 10bit (30bpp) R10*1 R11*1 R12 R13 R14 R15 R16 R17 R18 R19 G10*1 G11*1 G12 G13 G14 G15 G16 G17 G18 G19 B10*1 B11*1 B12*1 B13*1 B14*1 B15*1 B16*1 B17*1 B18*1 B19*1 CONT11*1*2 CONT12*1*2 HSYNC VSYNC DE 2nd Pixel Data 8bit (24bpp) R10 R11 R12 R13 R14 R15 R16 R17 G10 G11 G12 G13 G14 G15 G16 G17 B10*1 B11*1 B12*1 B13*1 B14*1 B15*1 B16*1 B17*1 HSYNC VSYNC DE 10bit (30bpp) R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 CONT11 CONT12 HSYNC VSYNC DE 8bit (24bpp) R12 R13 R14 R15 R16 R17 R18 R19 G12 G13 G14 G15 G16 G17 G18 G19 B12 B13 B14 B15 B16 B17 B18 B19 HSYNC VSYNC DE Data Signals 10bit (30bpp) R20*1 R21*1 R22 R23 R24 R25 R26 R27 R28 R29 G20*1 G21*1 G22 G23 G24 G25 G26 G27 G28 G29 B20*1 B21*1 B22*1 B23*1 B24*1 B25*1 B26*1 B27*1 B28*1 B29*1 CONT21*1*2 CONT22*1*2 - 8bit (24bpp) R20 R21 R22 R23 R24 R25 R26 R27 G20 G21 G22 G23 G24 G25 G26 G27 B20*1 B21*1 B22*1 B23*1 B24*1 B25*1 B26*1 B27*1 - Receiver Output Pin Nam e 10bit (30bpp) R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 CONT21 CONT22 - 8bit (24bpp) R22 R23 R24 R25 R26 R27 R28 R29 G22 G23 G24 G25 G26 G27 G28 G29 B22 B23 B24 B25 B26 B27 B28 B29 - Sym bol defined by V-by-One(R) HS D30 D31 D0 D1 D2 D3 D4 D5 D6 D7 D28 D29 D8 D9 D10 D11 D12 D13 D14 D15 D26 D27 D16 D17 D18 D19 D20 D21 D22 D23 D25 D25 HSYNC VSYNC DE *1 CTL bits, which are carried during DE=Low except the 1st and the last pixel. *2 3D flags defined in the V-by-One(R) HS Standard are assigned to the following bit. V-by-One(R) HS Standard Packer/Unpacker D[24](3DLR) <=> CONT12/CONT22 V-by-One(R) HS Standard Packer/Unpacker D[25](3DEN) <=> CONT11/CONT21 Table 22. CMOS Output Data Mapping for Dual-in/Dual-out mode Copyright(C)2017 THine Electronics,Inc. 30 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Note 1)Power On Sequence Don't input clock nor data before THCV217 is on in order to keep absolute maximum ratings. 2)Cable Connection and Disconnection Don't connect and disconnect the CML cable, when the power is supplied to the system. 3)GND Connection Connect the each GND of the PCB which Transmitter, Receiver and THCV217-218 on it. It is better for EMI reduction to place GND cable as close to CML cable as possible. 4)Multiple device connection HTPDN and LOCKN signals are supposed to be connected proper for their purpose like the following figure. HTPDN should be from just one Rx to multiple Tx because its purpose is only ignition of all Tx. LOCKN should be connected so as to indicate that all Rx CDR become ready to receive normal operation data. LOCKN of Tx side can be simply split to multiple Tx. THCV218 DGLOCK connection is appropriate for multiple Rx use. Also possible time difference of internal processing time (p.19 THCV217 tTCD and p.20 THCV218 tRDC) on multiple data stream must be accommodated and compensated by the following destination device connected to multiple THCV218, which may have internal FIFO. THCV217 THCV218 HTPDN HTPDN LOCKN LOCKN clkin.1 clkout.1 FIFO DGLOCK Source Device Ex. synchronized Time diff. comes up THCV217 THCV218 HTPDN HTPDN LOCKN LOCKN Destination Device FIFO clkin.2 clkout.2 DGLOCK Internal processing time tTCD Copyright(C)2017 THine Electronics,Inc. Internal processing time tRDC 31 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Package THCV217 TFBGA 10x10 105L 0.12 C TOP VIEW PIN A1 CORNER 1.20 MAX. 0.270.37 1 2 3 4 5 6 7 8 9 10 11 -C- SEATING PLANE A B C D E F G H J K L BOTTOM VIEW 0.53 REF. 0.26 REF. A1 CORNER 11 10 9 8 7 6 5 4 3 2 1 0.8 8.0 10.0 A B C D E F G H J K L 0.8 8.0 10.0 UNIT : mm Ball Diameter: 0.4 Ball Width: 0.380.48 Copyright(C)2017 THine Electronics,Inc. 32 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E THCV218 TFBGA 12x12 145L 0.12 C PIN A1 CORNER TOP VIEW 1.20 MAX. 0.270.37 1 2 3 4 5 6 7 8 9 10 11 12 13 -C- SEATING PLANE A B C D E F G H J K L M N A1 CORNER BOTTOM VIEW 0.53 REF. 0.26 REF. 13 12 11 10 9 8 7 6 5 4 3 2 1 9.6 12.0 0.8 A B C D E F G H J K L M N 0.8 9.6 12.0 UNIT : mm Ball Diameter: 0.4 Ball Width: 0.380.48 Copyright(C)2017 THine Electronics,Inc. 33 THine Electronics, Inc. Security E THCV217-THCV218_Rev.2.20_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. Product Application 5.1 Application of this product is intended for and limited to the following applications: audio-video device, office automation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine device. This product must not be used for applications that require extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 This product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in this data sheet. THine Electronics, Inc. ("THine") accepts no liability whatsoever for any product other than the Specified Product for it not conforming to the aforementioned demands and specifications. 5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that the user and THine have been previously and explicitly agreed to each other. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user's request, testing of all functions and performance of the product is not necessarily performed. 9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. 10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. THine Electronics, Inc. sales@thine.co.jp http://www.thine.co.jp/ Copyright(C)2017 THine Electronics,Inc. 34 THine Electronics, Inc. Security E