TC3567CFSG
©2017 TOSHIBA Corporation 2017-06-26
1
TC3567CFSG
Bluetooth® lo w energy IC
Rev 1.1
The Bluetooth® word mark and logos are registered trademarks owned by the Bluetooth SIG, Inc. and any use of such
marks by Toshiba is under license. Other trademarks and trade names are those of their respective owners.
ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved.
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Contents
1. General Description ...............................................................................................................................................................................4
1.1. Product Concept ...............................................................................................................................................................................4
1.2. Features .............................................................................................................................................................................................4
2. Pin Function ...........................................................................................................................................................................................5
2.1. TC3567CFSG Pin Assignment (Top View)......................................................................................................................................5
2.2. Pin Function Descriptions .................................................................................................................................................................6
2.3. GPIO function list ...............................................................................................................................................................................9
2.4. Power Supply Pins ......................................................................................................................................................................... 10
3. System Configuration .......................................................................................................................................................................... 11
3.1. Block Diagram ................................................................................................................................................................................. 11
3.2. Boot Sequence ............................................................................................................................................................................... 12
4. Hardware Interfaces ........................................................................................................................................................................... 13
4.1. Reset Interface (Power up sequence) .......................................................................................................................................... 13
4.1.1. Features ............................................................................................................................................................................. 13
4.1.2. Connection Example ......................................................................................................................................................... 13
4.2. UART Interface ............................................................................................................................................................................... 14
4.2.1. Features ............................................................................................................................................................................. 14
4.2.2. Connection Example ......................................................................................................................................................... 14
4.2.3. Frame Format .................................................................................................................................................................... 15
4.2.4. Flow Control Function ........................................................................................................................................................ 15
4.2.5. TX message spacing function ........................................................................................................................................... 16
4.2.6. Error Detecting Functions .................................................................................................................................................. 17
4.2.7. Host Wake up Function ..................................................................................................................................................... 18
4.2.8. HCI mode ........................................................................................................................................................................... 18
4.2.8.1. HCI Reset ...................................................................................................................................................................... 18
4.3. SPI Interface ................................................................................................................................................................................... 19
4.3.1. Features ............................................................................................................................................................................. 19
4.3.2. Connection Example ......................................................................................................................................................... 19
4.3.3. Frame Format .................................................................................................................................................................... 20
4.4. I2C Interface .................................................................................................................................................................................... 21
4.4.1. Features ............................................................................................................................................................................. 21
4.4.2. Connection Example ......................................................................................................................................................... 21
4.4.3. Selection of External Pull-up Resistor Value .................................................................................................................... 22
4.4.4. Frame Format .................................................................................................................................................................... 23
4.5. PWM Interface ................................................................................................................................................................................ 24
4.5.1. Pulse Generation Function ................................................................................................................................................ 24
4.5.2. Rhythm Function (Output Masking) .................................................................................................................................. 25
4.6. ADC ................................................................................................................................................................................................ 26
4.6.1. Features ............................................................................................................................................................................. 26
4.6.2. Descriptions ....................................................................................................................................................................... 26
4.7. IC Reference Clock Interface ........................................................................................................................................................ 27
4.7.1. Features ............................................................................................................................................................................. 27
4.7.2. Connection Example ......................................................................................................................................................... 27
4.8. Sleep Clock Interface ..................................................................................................................................................................... 28
4.8.1. Sleep Clock Connection Example .................................................................................................................................... 28
4.8.2. External Oscillator Connection Example .......................................................................................................................... 28
5. Electric Characteristics ....................................................................................................................................................................... 29
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5.1. Absolute Maximum Ratings........................................................................................................................................................... 29
5.2. Operating Conditions ..................................................................................................................................................................... 30
5.3. DC electric characteristics .............................................................................................................................................................. 31
5.3.1. Current Consumption (Design value) ............................................................................................................................... 31
5.4. Built-in Regulator Characteristics .................................................................................................................................................. 33
5.5. ADC Characteristics ....................................................................................................................................................................... 33
5.6. RF Characteristics (Design value) ................................................................................................................................................. 34
5.7. AC Interface Characteristics (Design value) ................................................................................................................................. 36
5.7.1. UART Interface .................................................................................................................................................................. 36
5.7.2. I2C Interface........................................................................................................................................................................ 37
5.7.2.1. Normal Mode ................................................................................................................................................................. 37
5.7.2.2. Fast mode ...................................................................................................................................................................... 38
5.7.3. SPI Interface....................................................................................................................................................................... 39
5.8. Characteristics of Flash-ROM block .............................................................................................................................................. 40
6. System Configuration Example ......................................................................................................................................................... 41
6.1. In HCI mode ................................................................................................................................................................................... 41
6.2. In User-App mode .......................................................................................................................................................................... 42
7. Package outline .................................................................................................................................................................................. 43
7.1. Outline dimensional drawing TC3567CFSG (P-VQFN40-0505-0.40-005/F01) ......................................................................... 43
RESTRICTIONS ON PRODUCT USE ......................................................................................................................................................... 44
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1. General Description
1.1. Product Concept
TC3567CFSG (Later omitted TC3567C.) are compliant with Bluetooth® core specification 4.2. RF analog parts and baseband
digital parts are built in them, and TC3567C provides Bluetooth® HCI (Host Control Interface) functions and Bluetooth® low energy
GATT profile functions defined by Bluetooth® core specifications. Additionally, this IC works as an application using low power
Bluetooth® communication by storing the application program into built-in flash ROM.
1.2. Features
Compliant with Bluetooth® Ver4.2 low energy
Built-in Bluetooth® Baseband
Built-in Bluetooth® RF analog
Built-in ARM® Cortex®-M0 (13 MHz or 26 MHz function mode is able to select to run)
On-chip mask ROM for Bluetooth® program (216 KB)
On-chip work RAM for Bluetooth® Baseband process (128 KB)
On-chip NOR Flash Memory (128 KB, More than 100,000 erase and program cycles)
Supports patch program loader function
2 boot modes (HCI mode, User-App mode)
General Purpose IO ( 17 ports)
General Purpose Serial Interfaces
SPI interface (1 ch assigned to a General Purpose IO)
I2C interface (1 ch assigned to a General Purpose IO)
Host CPU Interface
UART interface (9600 bps to 921.6 kbps, 1ch - shared with GPIOs)
SPI interface
Emulator debug control interface
SWD(Serial Wire Debug)2-wire (1 ch)
Wake-up Interface (2 ch assigned to a General Purpose IO)
Wake-up input function from sleep and deep sleep
PWM Interface (4 ch assigned to General Purpose IOs)
Reference Clock Input (26 MHz)
Built-in oscillator for crystal oscillator connection
Sleep Clock Input (32.768 kHz)
External oscillator input supported
Built-in oscillator for crystal oscillator connection
Works as Standalone (In User-App mode, operating by standalone is possible)
Sleep and Deep Sleep Functions
Built-in DCDC converter and LDO
Wide range of input power supply voltages supported (Booting power supply voltage : 2.0 to 3.6 V, low battery voltage
detection)
Built-in general purpose ADC
External analog inputs assigned to GPIOs (5 ch)
Internal VDD monitoring (1 ch - connected inside)
Package:
TC3567CFSG: QFN Package [40 pin, 5 x5 mm, 0.4 mm pitch, 0.9 mm thickness]
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2. Pin Function
2.1. TC3567CFSG Pin Assignment (Top View)
31
32
33
34
35
36
37
38
39
40
12345678910
30 29 28 27 26 25 24 23 22 21
20
19
18
17
16
15
14
13
12
11
VDDIO1
GPIO25
RESETX
TMODE
VPGM
VSSRFIO
RFIO
VSSA
TRTEST1
TRTEST2
XOIN
XOOUT
VSSX
VDDCORE1
GPIO2
VDDCORE2
SWDIO
VBAT
LX
VSSDC
SLPXOIN
SLPXOOUT
VDDIO2
GPIO14
GPIO13
GPIO10
VDDIOFQ
GPIO9
GPIO4
GPIO0
SWDCLK
GPIO15
GPIO12
GPIO11
GPIO5
GPIO6
GPIO7
GPIO8
GPIO1
GPIO3
FIN
(VSSD)
Figure 2-1 Pin A ssignment (Top Vie w)
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2.2. Pin Function Descriptions
Table 2-1 shows attributes, input/output states for operating modes and descriptions for pin functions. Table 2-3 shows
descriptions about power supply pins.
Table 2-1 Pin F unctions
Pin name Pin No. Attribute Condition Functional description
VDD category
Direction
Type
Default
(during reset)
Reset interface
RESETX 3
VDDIO
IN
Schmitt trigger
— Hardware reset input pin.
Setting this pin to Low level put the system at reset
state.
Clock interface
XOIN 11
VDDCORE
IN
OSC
IN Reference clock input pin. Please use oscillator with
26 MHz and < 50 ppm accuracy.
A feedback resistor is built in between XOIN pin and
XOOUT pin and a capacity array which can set
parameters in the crystal oscillation circuit is built-in,
so that external feedback resistances and
capacities are unnecessary.
XOOUT 12
VDDCORE
OUT
OSC
OUT Oscillator output for Baseband and RF reference
clock (26 MHz) pin.
A feedback resistor is built in between XOIN pin and
XOOUT pin and a capacity array which can set
parameters in the crystal oscillation circuit is built-in,
so that external feedback resistances and
capacities are unnecessary.
SLPXOIN 21
VDDIO
IN
OSC
IN Sleep clock input pin from oscillator. Please use an
oscillator with 32.768 kHz and < 500 ppm accuracy.
A feedback resistor is built in between SLPXOIN pin
and SLPXOOUT pin and a capacity array which
can set parameters in the crystal oscillation circuit is
built-in, so that external feedback resistances and
capacities are unnecessary. An external clock can
be input from this pin. When the crystal oscillator is
not used and do not supply a clock from the
outside, this pin should be connected to the GND.
SLPXOOUT 22
VDDIO
IN/OUT
OSC
IN Oscillator output (feedback) pin for the oscillation of
32.768 kHz.
A feedback resistor is built in between SLPXOIN pin
and SLPXOOUT pin and a capacity array which
can set parameters in the crystal oscillation circuit is
built-in, so that external feedback resistances and
capacities are unnecessary.
When the crystal oscillator is not used, this pin
should be connected to the GND.
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Pin name Pin No. Attribute Condition Functional description
VDD category
Direction
Type
Default
(during reset)
RF interface
RFIO 7
VDDCORE
IN/OUT
Analog
— RF I/O pins.
This product incorporates the 50 Ω matching circuit,
so that external matching circuit is unnecessary.
The RF output pattern should wire with the 50 Ω
transmission line.
For details, refer to the hardware application note of
this product.
General purpose I/O port
GPIO0
GPIO15
31
33
VDDIO
IN/OUT
Pull-up
Pull-down
Schmitt trigger
Refer to Table 2-2 General purpose I/O pin.
During reset, the input will be disable state with
disconnecting the Pull-up/Pull-down resistor.
After the pin configuration by software processing, it
works as a GPIO pin of the input and output or
function pin.
Please refer to Table 2-2.
GPIO1
GPIO2
GPIO5
GPIO6
GPIO7
GPIO8
GPIO11
GPIO12
GPIO25
40
16
36
37
38
39
35
34
2
VDDIO
IN/OUT
Pull-up
Pull-down
Schmitt trigger
Refer to Table 2-2 General purpose I/O pin.
During reset, the input will be disable state with
connecting the Pull-up resistor.
After the pin configuration by software processing, it
works as a GPIO pin of the input and output or
function pin.
Please refer to Table 2-2.
In addition, GPIO1 and GPIO2 pin is used in the
case of switching operation modes.
GPIO3
GPIO4
GPIO9
GPIO10
GPIO14
30
29
28
26
24
VDDIO
IN/OUT
Pull-up
Pull-down
Schmitt trigger
Refer to Table 2-2 ADC input and general purpose I/O pin.
During reset, the input will be disable state with
disconnecting the Pull-up/Pull-down resistor.
After the pin configuration by software processing, it
works as a GPIO pin of the input and output or
function pin or general purpose ADC channel pin.
Please refer to Table 2-2.
GPIO13 25
VDDIO
IN/OUT
Pull-up
Pull-down
Schmitt trigger
Refer to Table 2-2 General purpose IO pin.
During reset, the input will be disable state with
connecting the Pull-up resistor.
After the pin configuration by software processing, it
works as a GPIO pin of the input and output or
function pin.
Please refer to Table 2-2.
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Pin name Pin No. Attribute Condition Functional description
VDD category
Direction
Type
Default
(during reset)
SWDCLK
32
VDDIO
IN
Pull-up
Pull-down
Schmitt trigger
Pull-down Serial Wire debugger clock pin.
During the reset, it remains in the input disable state
with connecting the Pull-down resistor. After the
reset is released, it will be the input of the Serial
Wire Debugger clock.
When not used, this pin should be open.
SWDIO 17
VDDIO
IN/OUT
Pull-up
Pull-down
Schmitt trigger
Pull-up Serial Wire Debugger data pin and operation
switching pin.
During the reset, it remains in the input disable state
with connecting the Pull-up resistor. After the reset
is released, it will be the input and output of the
Serial Wire Debugger data.
In addition, SWDIO pin is used in the case of
switching operation modes.
When not used, this pin should be open.
IC test interface
TMODE 4
VDDIO
IN
Schmitt trigger
— Test mode setting pins.
This pin is used for IC manufacturing test and need
to be connected to GND when assembled on a
board.
TRTEST1
TRTEST2
9
10
VDD12A
IN/OUT
Analog
— Analog test pins.
These pins are used for IC manufacturing test and
need to be connected to GND when assembled on
a board.
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2.3. GPIO function list
GPIO pins can be assigned to UART I/Fs, serial memory I/Fs and etc. by TC3567C firmware or command from external Hosts.
Table 2-2 shows available functions, during reset status and software controlling after reset release for each GPIO pin. About what
function name shown in Table 2-2 is assigned to a plurality of pins in the same, please note that it cannot be assigned to select a
plurality of pins at the same time.
Table 2-2 Av ailable functions for GPIO
Pin During reset
status
After reset release Function 1 Function 2 Function 3 Function 4 Analog
input
Pin state at
unused
GPIO0 Disable/ Hi-Z
Disable/
Disconnection:
Pull-up, Pull-down
WakeUp0
Input — — — — Open
GPIO1 Disable/ Pull-up Input/ Pull-up
(Note2)
PWM0
Output
— — — — Open
(Note1)
GPIO2 Disable/ Pull-up Input/ Pull-up
(Note2)
PWM1
Output
— — — — Open
(Note1)
GPIO3 Disable/ Hi-Z
Disable/
Disconnection:
Pull-up, Pull-down
PWM2
Output
SPI-DOUT
Output — — ADC1
Input Open
GPIO4 Disable/ Hi-Z
Disable/
Disconnection:
Pull-up, Pull-down
PWM3
Output
SPI-DIN
Input — — ADC2
Input Open
GPIO5 Disable/ Pull-up Input/ Pull-up
(Note3)
UART1-TX
Output
SPI-DOUT
Output
— — — Open
GPIO6 Disable/ Pull-up Input/ Pull-up
(Note3)
UART1-RX
Input
SPI-DIN
Input
— — — Open
GPIO7 Disable/ Pull-up Input/ Pull-up I2C-SCL
Output
— SPI-SCS
Output
UART1-RTSX
Output
— Open
GPIO8 Disable/ Pull-up Input/ Pull-up I2C-SDA
I/O
— SPI-SCLK
Output
UART1-CTSX
Input
— Open
GPIO9 Disable/ Hi-Z
Disable/
Disconnection:
Pull-up, Pull-down
— — — — ADC3
Input Open
GPIO10 Disable/ Hi-Z
Disable/
Disconnection:
Pull-up, Pull-down
— — — — ADC4
Input Open
GPIO11 Disable/ Pull-up Input/ Pull-up I2C-SCL
Output
SPI-DOUT
Output
— — — Open
GPIO12 Disable/ Pull-up Input/ Pull-up I2C-SDA
I/O
SPI-DIN
Input
— — — Open
GPIO13 Disable/ Pull-up Input/ Pull-up UART1-RTSX
Output
32 kHz
Output
— — — Open
GPIO14 Disable/ Hi-Z
Disable/
Disconnection:
Pull-up, Pull-down
UART1-CTSX
Input
32 kHz
Output — — ADC5
Input Open
GPIO15 Disable/ Hi-Z
Disable/
Disconnection:
Pull-up, Pull-down
WakeUp1
Input — — — — Open
GPIO25 Disable/ Pull-up Input/ Pull-up — — — — — Open
Note1: Handle with care because of using operation mode switching.
Note2: Except in User-App mode, it becomes Pull-down.
Note3: In the HCI mode, the pull-up / pull-down resistor is disconnected.
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2.4. Power Supply Pins
Table 2-3 shows the attributes and descriptions of power supply pins for normal operations.
Table 2-3 Po wer supply pins
Pin name Pin number
Attribute Description
Type
VDD/GND
VDD/GND
VPGM 5 TEST
—
Test pin
Please connect VPGM to GND.
VBAT 18
VBAT
VDD
Power supply pin for DCDC and sleep circuit.
Connect the external power source for DCDC and LDO built into the IC.
LX 19
VBAT
VDD
DCDC output pin.
Please connect to external inductor for DCDC.
VDDCORE1
14
—
VDD
DCDC for feedback input, analog circuit power supply pin.
Please connect to external inductor for DCDC.
VDDCORE2 15
—
VDD
DCDC for feedback input, digital circuit power supply pin.
Please connect to external inductor for DCDC.
VDDIO1
VDDIO2
1
23
VDDIO
VDD
IO power supply
Power supply pin for GPIO.
VDDIOFQ 27
VDDIOFQ
VDD
Flash ROM external capacitor connection pin.
It has been connected to the power supply of the internal flash ROM of the IC.
As the LDO load capacitor, a capacitor of 0.1 μF or more should be
connected at the operation temperature.
VSSA 8
Analog
GND
GND pin for analog, this pin needs to be connected to GND.
VSSRFIO 6
Analog
GND
GND pin for RFIO, this pin needs to be connected to GND.
VSSX 13
Analog
GND
GND pin for OSC, this pin needs to be connected to GND.
VSSDC 20
Digital
GND
GND pin for DCDC, this pin needs to be connected to GND.
VSSD FIN
Digital
GND
Die pad ground Fin. Connect the exposed Die Pad to GND because this pad
is digital ground as well.
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3. System Configuration
3.1. Block Diagram
Figure 3-1 shows block diagram of TC3567C.
TC3567C is powered by single voltage between 1.8 V and 3.6 V, especially 2.0 V of power supply is required in accessing to the
internal flash ROM and the booting process. The chip has built-in DCDC and LDO requiring external capacitors. It uses 26 MHz
reference clock and 32.768 kHz sleep clock. External memory interface is SPI or I2C, and host CPU interface is UART.
Figure 3-1 Example of TC3567C system configuration
RF Block
26MHz
X’tal
ClockGen/
Clock
Management
RF PLL
Power
Management
Controller
VBAT
1.8 to
3.6V
Baseband
Block
UART
2ch
HOST
I/F
SPI/
I
2
C
PWM
4ch GPIO ADC
6ch
Modem
ARM
®
Cortex
®
-M0
Mask
ROM
RAM
(Back Up )
Selector
Ref
VBAT
32kHz
X’tal
DCDC
LDO
Level
Detector
Flash
ROM
VDDCORE2
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3.2. Boot Sequence
The boot sequence of TC3567C is as shown below.
Depending on the pin state of GPIO1 at the time of reset release, it can be used to switch between User-App mode and HCI mode.
Figure 3-2 Boot Sequence of TC3567C
Reset release
GPIO1 check
Begin of firmware boot-up
Toshiba
Test mode
L
H: User-App mode
Load User-App
from NVM
to TC3567C RAM
Check word check
Read "Check Word"
in NVM
Checksum check
Start User-App
NG
OK
OK
NG
Error
(Hardware reset is required
to recovery.)
SWDIO check
GPIO2 check
L: Test mode
H: HCI mode
Reserved
mode
HCI mode
(UART)
H
L
See Flash-ROM(NVM) control section in
Programming Guide for detail
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4. Hardware Interfaces
4.1. Reset Interface (Power up sequence)
4.1.1. Features
Reset interface has the following features.
2.0 to 3.6 V operation
Level sensitive asynchronous reset (Low level: reset)
The reset signal should be at reset status (RESETX = Low) when the power is turned on. When the power supply has become over
2.0 V, to be disable the reset signal (RESETX = High). Then starts the X’tal oscillation after DCDC output has become stable If DCDC is
used, or after each LDO output has reached its target voltage from VBAT supplying voltage. Then, an internal timer releases the
internal reset after the X’tal oscillation has become stable.
4.1.2. Connection Example
Reset signal can be input by an RC time constant circuit or an asynchronous level sensitive reset IC. Figure 4-1 shows a connection
example where TC3567C is power-supplied by an RC time constant circuit. Reset signal can be given by RC time constant circuit.
Figure 4-2 shows the timings to reset and reset-release for the power supply.
Figure 4-1 Reset signal c onnection example
Figure 4-2 Power-on reset release sequence
V
BAT Power supply
Reset signal
DCDC / LDO
Output
Power off
OSC boo
t timer
Operation
Power ON
Voltage detection
R
C delay
Reference clock
Stable
Uns
table
VDDIO Power supply
TC3567C
Reset
Power Supply
Connection example is the RC circuit that was omitted or simplified.
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4.2. UART Interface
4.2.1. Features
TC3567C UART interface has the following features.
1.8 to 3.6 V operation
Full-duplex start-stop synchronization data transfer (RX, TX, CTSX, RTSX)
Two-wire start-stop synchronization data transfer (RX, TX) or four-wire start-stop synchronization data transfer (RX, TX,
CTSX, RTSX) are available depending on the settings.
Start bit field (1 bit), data bit field ( 8 bit, LSB first), stop bit field (1 bit), no parity bit
In HCI mode, UART TX/RX pins can be switched by commands.
Programmable baud rate: 9600 bps to 921.6 kbps.
More than 3 characters are inserted between TX messages. Interval can be changed on the command.
Error detection (receiver timeout error, receiver over run error, receiver frame error)
Host wake up function
TC3567C communicates commands, status, and data with a host CPU through UART interfaces. The UART interfaces are shared
with GPIO pins, and during boot process after a reset, TC3567C firmware assigns UART functions to the GPIOs. The UART
interfaces can operate at 1.8 to 3.6 V depending on the VDDIO power supply voltage. Sharing the power supply pin with other
hardware interfaces, they cannot operate at a different voltage from the one other hardware interfaces operate at.
4.2.2. Connection Example
TC3567C UART can be connected with an UART interface on a host CPU. Figure 4-3 shows an example of two-wire start-stop
synchronization data transfer connection with an external host CPU. Figure 4-4 shows the timing when UART is assigned to GPIO
and activated.
Figure 4-3 UA RT connection example
Figure 4-4 Timing for UART func tion assignment
R
eset
UART
TX data
UART
RX data
Reset
GPIO Configuration
(Pulled up to hi
gh)
UART
Communication
Output direction
Input direction
TC3567C
UART Received Data (RX)
UART Transmitted Data (TX)
HOST CPU
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4.2.3. Frame Format
TC3567C supports the following format:
Number of data bits: 8 bits (LSB first)
Parity bit: no parity
Stop bit: 1 stop bit
Flow control: RTSX/CTSX
Figure 4-5 shows UART data frame.
Figure 4-5 UA RT data frame
4.2.4. Flow Control Function
Hardware flow control is available when TC3567C UART interface is assigned to GPIO5 to GPIO8 (GPIO5, 6, 13, 14) as four-wire
start-stop synchronization data transfer. Transmit flow control (CTSX) and receive flow control (RTSX). Figure 4-6 shows signals
input and output direction.
Figure 4-6 UA RT connection e xample
CTSX (Clear to Send) input signal is used for UART transmitting. Low input indicates the peer device (for example, the host in the
Figure 4-6) is ready to receive data, and TC3567C sends data if it has data to transmit. On the other hand, TC3567C stops
transmitting on the basis of UART unit frame when CTSX input is high.
RTSX (Request to Send) output signal is used for UART receiving. Low output indicates TC3567C is ready to receive data and
requests data to the peer device. TC3567C outputs RTSX low when ready to receive data. When the UART becomes busy and
cannot receive data, TC3567C outputs RTSX high, and stops UART communication on the basis of UART unit frame.
Response time of UART transmitting and receiving to flow control signals is between 1 frame to 4 frames depending on the baud
rate and internal process status of frame.
TC3567C
UART Request To Send (RTSX)
UART Clear To Send (CTSX)
UART Received Data (RX)
UART Transmitted Data (TX)
HOST CPU
TX
CTSX
1
LSB
2 3 4 5 6 MSB
Start bit
Stop bit
RX
RTSX
1
LSB
2 3 4 5 6 MSB
Start bit
Stop bit
Over
Sampling (x 12 to 17) /bit
1
2
3
4
5
6
7
8
9
10
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4.2.5. TX message sp acing function
TC3567C spaces more than 12 time frames between different TX messages making less than 12 time frames between TX frames
in a TX message when several TX frames belong to one TX message. Host CPU is able to know the boundaries between TX
messages by measuring time frames between TX frames.
Figure 4-7 TX frames and TX messages
UART
TX data
UART TX massage UART TX message
< 12 time frames
< 12 time frames
< 12 time frames
> 12 time frames
1 time frame
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4.2.6. Error Detecting Functions
TC3567C UART interface has 3 kinds of error detecting functions.
Receiver timeout error
Receiver over run error
Receiver frame error
Receiver timeout error detection judges an error if an UART RX message made from several RX frames has an RX frame interval
longer than a certain value. The interval is counted by internal timer. Keep the interval between RX frames less than 12 time frames
that belong to an RX message. For UART1, keep intervals between different RX messages more than 12 time frames. For
example, 115200 bps has 0.087 ms for 1 frame, the interval between RX messages should be longer than 0.087 ms × 12 = 1.04
ms. RX messages that has intervals less than 12 time frames gives an error because TC3567C sees them as one UART RX
message. Interval of the received frame is the default in the 12 time frame, but it can be changed by the command.
Figure 4-8 RX frames and RX messages
Receiver over run error judges if UART receive frame buffer internal TC3567C is overflowed. Normally, this overflow does not
happen when the flow control mentioned in 4.2.4 is activated for data communication.
Receiver frame error judges if failing recognize the unit frame. A frame formation is judged as failure when its start bit is detected
and the corresponding stop bit is detected as “0”.
UART
RX data
UART RX message UART RX message
< 12 time frames
< 12 time frames
< 12 time frames
> 12 time frames
1 time frame
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4.2.7. Host W ake up Function
TC3567C can wakes up its host before sending UART data to the host. This function is disabled by default, but can be assigned to
GPIO by command. Host wake up time can be changed by command (10 ms by default).
Figure 4-9 Host wake up
4.2.8. HCI mode
When TC3567C is used in the HCI mode, UART is the host interface to receive HCI commands. The Bluetooth® wireless
performance can be tested in HCI mode by the measurement equipment which connects the UART directly.
4.2.8.1. HCI Reset
Sends a HCI reset command from the host, at least 150 μs from the command complete event can be processed the following
command successfully.
H
ost wake up
Host wake up time
(10 ms by default)
UART TX message
UART TX data
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4.3. SPI Interface
4.3.1. Features
TC3567C has the following main features for a serial memory interface
Operation voltage: 1.8 to 3.6 V
SPI interface
Chip select: 1 ch
Chip select polarity: Selectable: High-active and Low-active
Serial clock master operation: Polarity and phase are adjustable (4 combinations are selectable)
Serial clock frequency: 25 kHz to 6.5 MHz
Serial data transfer mode: MSB-first, LSB-first
SPI interface can operate at 1.8 to 3.6 V depending on VDDIO, however, cannot operate at different voltage from ones other
interfaces are operate at.
4.3.2. Connection Example
TC3567C SPI interface can be connected to serial EEPROMs and serial Flash-ROMs and has 1 chip select port. Figure 4-10
shows a connection example, where a serial Flash-ROM is connected to TC3567C SPI interface.
Figure 4-10 Connection example for serial Flash-ROM using SPI inte rface
Chip select (SPI-SCS)
Serial clock (SPI-SCLK)
Write data (SPI-DOUT)
Read data (SPI-DIN)
Serial
Flash-ROM
TC3567C
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4.3.3. Frame Format
When the SPI interface is connected to external ICs, the first 8 bit (X7 to X0) specifies the address and read or write mode. The
command recognition code type and the address bit width should be determined by the external IC in use. For more information in
detail, please refer to the technical documents for the external IC.
Figure 4-11 shows an example where 8-bit address is written and then 8-bit data is read. Figure 4-12 shows an example where
8-bit address is written and then 8-bit data is written.
Figure 4-11 SPI format (single byte read)
Figure 4-12 SPI format (single byte write)
Bit clock
X7
MSB
LSB
Serial data (write)
D7
D2
D0
LSB
Serial data (read)
Chip select
D1
MSB
X1
X0
Bit clock
X7
MSB
LSB
Serial data (write)
X1
X0
D7
-
2
D0
LSB
Serial data (read)
Chip select
D1
MSB
X1
D7
D1
X0
D0
MSB
X7
MSB
LSB
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4.4. I2C Interface
4.4.1. Features
I2C has the following main features for a serial interface.
Operation voltage: 1.8 to 3.6 V
I2C Interface
Operation mode: I2C bus master
Serial clock frequency: Standard mode (Max 100 kHz), Fast mode (Min 100 kHz to Max 400 kHz)
Output mode: Open-drain output, CMOS output
Device address format: 7-bit address (10-bit address is not supported)
I2C interface can operate at 1.8 to 3.6 V depending on VDDIO, however, cannot operate at different voltage from ones other
interfaces are operate at.
4.4.2. Connection Example
Figure 4-13 shows a connection example of a serial EEPROM using I2C bus interface of the open-drain mode. External pull-up
resistors (Rext) are necessary for both serial clock line and serial data line.
Figure 4-14 shows another connection example where I2C bus is in the CMOS output mode. Only the serial data line needs Rext
because this line can be driven by neither TC3567C nor a serial EEPROM.
Figure 4-13 Connection example for serial EEPROM with I2C-bus interface (Open-dra in output)
Figure 4-14 Connection example for serial EEPROM with I2C-bus interface (CMOS output)
TC3567C Serial clock output
Serial data input / output
Serial
EEPROM
Rext
VDDIO
Serial
EEPROM
TC3567C
Serial clock output
Serial data input / output
Serial
EEPROM
Rext Rext
VDDIO VDDIO
Serial
EEPROM
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4.4.3. Selection of External Pull-up Resistor Value
An external pull-up resistor value needs to be selected by the following equations in case of I2C bus interface. Its maximum value is
defined by equation (1), in which tr is rise time of serial clock and data and Cb is I2C bus capacity. Its minimum value is defined by
equation (2), in which VDDIO is a supply voltage for TC3567C, Vol_max is the maximum value of low level output voltage, and Iol is
the low level output current. Please set the pull-up resistor value between these lower and upper limits.
b
r
C
t
×
=
8473.0
Rext_max
(1)
ol
ol
IVVDDIO max_
ext_min
R−
=
(2)
TC3567C supports I2C bus standard mode (Max 100 kHz) and I2C bus fast mode (Min 100 kHz to Max 400 kHz). The rise time tr is
1000 ns for the standard mode and it is 300 ns for the fast mode. Cb can vary depending on the IC board and how it is
implemented. Table 4-1 and Table 4-2 show examples when I2C bus capacity is 20 pF.
Table 4-1 Ex ternal pull-up resistor value for I2C standard mode (Cb = 20 pF)
I
2
C bus frequency Max 100 kHz
tr [ns] 1000
Cb [pF] 20
VDDIO [V] 1.8 3.0 3.6
Vol_max [V] 0.3 0.4 0.4
Iol [mA] 1 2 4 1 2 4 1 2 4
Rext_min [kΩ] 1.50 0.75 0.38 2.60 1.30 0.65 3.20 1.60 0.80
Rext_max [kΩ] 59.01
Table 4-2 Ex ternal pull-up resistor value for I2C fast mode (Cb = 20 pF)
I
2
C bus frequency Min 100 to Max 400 kHz
tr [ns] 300
Cb [pF] 20
VDDIO [V] 1.8 3.0 3.6
Vol_max [V] 0.3 0.4 0.4
Iol [mA] 1 2 4 1 2 4 1 2 4
Rext_min [kΩ] 1.50 0.75 0.38 2.60 1.30 0.65 3.20 1.60 0.80
Rext_max [kΩ] 17.70
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4.4.4. Frame Format
For I2C format, TC3567C first generates start condition. Then, it sends device recognition address (7 bit: [A6:A0]) and the first byte
address ([B7:B0]) for the access target. Next, it goes for read or write sequence. For I2C, every data is sent as MSB first. How to
specify the value and byte address of the device identification address, and it has been determined in accordance with the device
to be connected. In order to be connected, it must match the device to be connected. For read operation, TC3567C returns to the
serial memory either receive acknowledge bit (ACK) or receive not acknowledge bit (NACK) every time it receives one byte. For
write operation, TC3567C receives either ACK or NACK from the serial memory every time it sends one byte. It can handle not only
one byte but also several bytes in a row. TC3567C generates stop condition when it has finished all the read or write of data.
Figure 4-15 shows an example where TC3567C reads two-byte data. Figure 4-16 shows an example where TC3567C writes
two-byte data. In these examples, gray texts and lines indicate signals that are given by the serial memory. For read operation, after
having read the final byte data, TC3567C returns NACK with which the serial memory gets to know the completion of the read
operation.
Figure 4-15 I2C format (Serial memory , read)
Figure 4-16 I2C format (Serial memory , write)
Serial
clock
A6
M
SB
LSB
Serial
data
Start condition
A0
B0
W
ACK
ACK
D7
D0
LSB
MSB
B7
MSB
LSB
ACK
Stop condition
D7
D0
LSB
MSB
ACK
Serial
clock
A6
MSB
LSB
Start condition
A0
B0
W
ACK
ACK
A6
D7
D0
LSB
MSB
A0
LSB
MSB
B7
MSB
LSB
R
ACK
NAC
Stop condition
D7
D0
LSB
MSB
ACK
Start condition
Serial
data
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4.5. PWM Interface
TC3567C has a PWM interface that can be used for LED, buzzer control, etc.
The PWM interface has the following features.
Arbitrary pulse generation function
It can select the source clock from 13 MHz and 32.768 kHz
It has 12-bit clock division setting up to 1/4096: 8 Hz to 16.384 kHz (32.768 kHz), 3.17 kHz to 6.5 MHz (13 MHz)
The pulse output can be masked by the regular pattern whose period is one second with 50 ms unit width (Rhythm function).
It can generate an interrupt which is synchronized to the rhythm pattern period 1 s.
It can switch the pulse output to Low / High active
It can adjust the duty cycle of the pulse output.
4.5.1. Pulse Generation Function
Figure 4-17 shows a brief explanation of the pulse generation. TC3567C can adjust output pulse frequency by changing its cycle.
Also it can adjust on/off ratio by changing its duty.
The cycle (frequency) can be set from 8 Hz to 16.384 kHz for 32.768 kHz clock, and from 3.17 kHz to 6.5 MHz for 13 MHz clock.
The duty can be set from 0% to 100%
Cycle
Duty
Figure 4-17 PWM pulse generation function
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4.5.2. Rhythm Function (Output Masking)
Figure 4-18 shows the brief explanation of PWM rhythm function. In addition to the one for pulse generation, TC3567C has another
timer that has 50 ms × 20 = 1 s (rhythm counter). That timer has 20-bit register (pattern register), each bit corresponds to the rhythm
counter that counts down in every 50 ms. When the pattern register is zero, the PWM output is masked to zero or one. Using this
function, LED or buzzer can be on with 1 s periodical pattern
1 0 1
50ms
Cycle time
10110101
19 18 17 16 15 1 0 19
Rhythm Counter
Pattern Register
PWM Output
50ms
1s (50ms*20)
Interrupt
PWM Generate
Note
If th e r hyt hm p at tern se t pe riod (50 ms) ÷ p ulse cycle time = no t an
inte gr al, at th e b ou nda ry of 0 to 1, 1 to 0 pattern register,
Duty ra tio o f t he pu lse will n ot be as set.
Pattern Register
PWM Output
PWM Generate
Figure 4-18 PWM Rhythm Func tion
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4.6. ADC
4.6.1. Features
TC3567C has 6 ch of 10-bit ADCs for battery monitoring, analog inputs from external sensors, for example. The ADC has the
following features.
5 ch for analog inputs Note: Analog inputs are shared with GPIO pins.
1 ch for VBAT voltage monitor
Note: The reference input is internally connected to VBAT, and the analog input is to built-in VDDCORE2 output. Please refer
to 4.6.2 for how to calculate voltage value.
Maximum conversion rate: 1 MS/s
4.6.2. Descriptions
The ADC has 10 bits conversion accuracy and can work for input voltages from 0 V to 3.6 V (VBAT). It has 6 ch of analog inputs, and
the ch0 is connected to VDDCORE2 output, and the ch1 to ch5 are shared with GPIO pins.
When a battery is used as power source, the reference voltage can slide over time because the battery is connected as reference
voltage. In that case, the VDDCORE2 output voltage connected to ch0 can be used as a reference voltage. The input voltage to ch1
to ch5 is converted by the reference voltage of ch0 and the converted value is used to calculate a correct digital value by the CPU.
The following shows the conversion method of the input voltage.
Voltage A at time T can be calculated as follows
(1) VDDCORE2 output voltage (VDDCORE2) on Ch0 should be converted by the ADC. The converted digital value is X.
(2) The analog signal on Ch1 is converted and the converted digital value is Y.
(3) When the absolute value of the analog signal on Ch1 is defined as Z (V), VDDCORE2 (V) / Z (V) = X / Y. So,
Z (V) = VDDCORE2 (V) × Y / X
Calculation example:
Suppose ch0 (for ex. VDDCORE2 output is 1.2 V) is converted to 0x0188, and ch1 (measurement target) is converted to
0x0134, the absolute voltage at ch1 Z (V) is given by 1.2 × 0x0188 / 0x0134 = 1.2 × 392 / 308 = 1.527 (V).
Figure 4-19 shows conceptual of voltage conversion.
3.3V
VDDCORE2
voltage
A[V]
(1)=X
(2)=Y
[t]
[V]
Time[T]
VREF
Figure 4-19 V olt age conv ersion concept
The ADC converts inputs from ch selected by register settings. When a conversion has finished, the CPU detects it by the interrupt or
register polling, and then returns the results. The maximum sampling rate depends on software load on the CPU.
Note: The numerical values are expressed as follows.
Hexadecimal number: 0xABC
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4.7. IC Reference Clock Interface
4.7.1. Features
TC3567C has the following features for IC reference clock interface.
Clock frequency: 26 MHz (please adjust the accuracy to < 50 ppm at the temperature in use)
TC3567C doesn’t require external feedback resistors and load capacitor because it has an internal feedback resistor and capacitor
array. Please adjust capacitor array, based on the specification of the used oscillator and PCB layout and assembly.
4.7.2. Connection Example
Figure 4-20 Crystal oscillator conne ction example
TC3567C
Control
Trimming
Input
XOIN
XOOUT
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4.8. Sleep Clock Interface
TC3567C has the following features for sleep clock interface.
Crystal oscillator can be connected.
Clock frequency: 32.768 kHz (please adjust the frequency accuracy to less than or equal to ±500 ppm at the temperature in
use.)
Crystal oscillator is connected between SLPXOIN pin and SLPXOOUT pin. TC3567C doesn’t require external feedback resistors
and load capacitor because it has an internal feedback resistor and capacitor array between SLPXOIN pin and SLPXOOUT pin.
Please adjust capacitor array based on PCB layout and assembly if necessary within the range of the X’tal’s specification.
When an external oscillator is connected, connect it to SLPXOIN and SLPXOOUT should be connected to the GND. When
oscillator is not used and do not supply a clock from the outside, this pin needs to be connected to the GND.
4.8.1. Sleep Clock Connection Example
Figure 4-21 Crystal oscillator connection example
4.8.2. External Oscillator Connection Example
Figure 4-22 External oscilla tor connection exam ple
TC3567C
External oscillator
Control
Trimming
Input
SLPXOIN
SLPXOOUT
TC3567C
SLPXOIN
SLPXOOUT
Control
Trimming
Input
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5. Electric Characteristics
5.1. Absolute Maximum Ratings
Absolute maximum ratings must not be exceeded even for a moment. Voltages, currents, and temperatures that exceed the
absolute maximum ratings can cause break-downs, degradations, and damages not only for ICs but also for other components
and boards. Please make sure application designs not to exceed the absolute maximum ratings in any situation.
Table 5-1 Absolute maximum ratings (VSSA = VSSRFIO = VSSDC = VSSD = VSSX = 0 V)
Note1: Do not connect VBAT to GND while VDDIO is powered. Current from VDDIO to VBAT through IC may cause damages,
break-downs, and degradations.
Note2: Please use VDDIO + 0.3 V not to exceed 3.9 V.
Items Symbols Ratings Units
Min Max
Power supply VBAT
VDDIO (Note1) -0.3 +3.9 V
Input voltage VIN -0.3 VDDIO + 0.3 (Note2) V
Output voltage VOUT -0.3 VDDIO + 0.3 (Note2) V
Input current IIN -10 +10 mA
Input power RFIO — +6 dBm
Storage temperature Tstg -40 +125 °C
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5.2. Operating Conditions
TC3567C can operate normally with proven quality under the operating ranges. Any diversion from the operating ranges may
cause false operation. Thus, please make sure application design to comply these operating ranges.
Table 5-2 Operating conditions (VSSA = VSSRFIO = VSSDC = VSSD = VSSX = 0 V)
Items Symbols Ratings Units
Min Typ. Max
Power
supply
VBAT Operating
Voltage1 (Note1) VBATopr1 1.60 3.00 3.60 V
VBAT Operating
Voltage2 (Note1) VBATopr2 1.79 3.00 3.60 V
VBAT Operating
Voltage3 (Note2) VBATopr3 2.00 3.00 3.60 V
VDDIO Operating
Voltage
(Note3)
VDDIOopr 1.80 3.00 3.60 V
VDDIOFQ
Output Voltage
(Note3)
VDDIOFQ — 1.7 — V
VDDCORE
Voltage
(Note3)
VDDCORE1/
VDDCORE2 — 1.2 — V
RF frequency Fc 2400 — 2483.5 MHz
Clock frequencies Reference clock Fck 25.99870 26.00000 26.00130 MHz
Sleep clock fslclk 32.751616 32.768000 32.784384 kHz
Ambient temp. Ta -40 +25 +85 °C
Note1: The low-voltage detection function is built in the VBAT pin. The IC operation is stop when the operating voltage falls to the
minimum value of the VBAT operating voltage 1 (VBATopr1). The low-voltage detection voltage has a hysteresis in order
not to start the IC repeatedly by the load variation after stopping. During voltage boosting, the internal CPU powers on when
the operating voltage rises to the minimum value of the VBAT operating voltage 2 (VBATopr2). However, please pay
attention that the minimum voltage of the VBAT operating voltage 3 (VBATopr3) is required for the reading and writing
operation of the flash ROM as indicated in the Note 2.
Note2: For reading and writing operation to the flash ROM in the digital block, the power in the range of VBAT operating voltage 3
should be supplied. In the booting process, please release RESET after the voltage rises to the minimum value (2.0 V)
because of accessing to the flash ROM to confirm the existence of applications. Moreover, in case of operating in the
User-App mode or driving till the under voltage detection turns off the operation, please pay attention to the relation between
R/W operation to the flash ROM and the voltage.
Note3: Please refer to other documents (application note) for our connection examples.
Please do not input external power supply and do connect external capacitors to VDDIOFQ because they are supplied by
the internal LDO.
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5.3. DC electric characteristics
5.3.1. Current Consumption (Design value)
This section shows current consumption. When the operating temperature (Ta) is 25°C, and the operation of each power supply
pin is in the recommendation connection state of our company, the current consumption is an average value.
Table 5-3 Current consumption (VBAT = VDDIO1 = VDDIO2 = 3.0 V, VSSA = VSSRFIO = VSSDC = VSSD = VSSX = 0 V)
Items Symbols Conditions Pins Ratings Unit
(Note) Min Typ. Max
Digital operation IDDDIG
(Active1) —
VBAT
— 0.8 —
mA
Flash read IDDRD
(Flash Read) — — 2.4 —
Flash write IDDWR
(Flash Write) — — 15.6 —
RX IDDRX
(Active2) — — 3.3 —
TX IDDTX
(Active3)
Output Power=
0 dBm — 3.3 —
Low power mode
With Connection
IDDS1
(Sleep)
26 MHz crystal oscillator disabled
32 kHz crystal oscillator enabled
VBAT
— 2.5 —
μA
Low power mode
Without Connection
IDDS2
(Backup)
26 MHz crystal oscillator disabled
32 kHz crystal oscillator enabled — 2.4 —
Low power mode
Without Connection
IDDS
(Deep Sleep)
26 MHz crystal oscillator disabled
32 kHz crystal oscillator disabled — 0.05 —
Note: Power consumption for IO depends on its settings.
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Table 5-4 shows DC electric characteristics for each pin under 25°C ambient temperature.
Table 5-4 DC Electric Characteristics (VBAT = VDDIO1 = VDDIO2 = 3.0 V, VSSD = VSSA = VSSRFIO = VSSDC = VSSX = 0 V)
Items Symbols
Condition Measuring Pin
(Note 1)
Rating
Unit
I/F Voltage Other
Condition Min Typ. Max
High Level
Input
Voltage
VIH 3.0 V LVCMOS VDDIO 0.8×VDDIO — —
V
Low Level
Input
Voltage
VIL 3.0 V LVCMOS VDDIO — — 0.2×VDDIO
High Level
Input
Current
IIH VDDIO =
Input Voltage
of each pin
Pull-down Off
VDDIO
-10 — 10
μA
Pull-down On 10 — 200
Low Level
Input
Current
IIL
Pull-up Off -10 — 10
Pull-up On -200 — -10
High Level
Output
Voltage
VOH 3.0 V IOH = 1 mA VDDIO VDDIO-0.6 — — V
Low Level
Output
Voltage
VOL 3.0 V IOL = 1 mA VDDIO — — 0.4 V
External
32 kHz
Clock Input
level (Note2)
VIH
SLPCLK 3.0 V — SLPXOIN 0.8×VDDIO — — V
VIL
SLPCLKL 3.0 V — SLPXOIN — — 0.2×VDDIO V
Note 1: Please refer to Table 2-3 for power supply line for each pin.
Note 2: External oscillator is used for this case instead of crystal oscillator.
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5.4. Built-in Regulator Characteristics
Table 5-5 Built-in regulator characteristics (VBAT = 1.8 to 3.6 V, VSSA = VSSRFIO = VSSDC = VSSD = VSSX = 0 V)
Items Symbols Pin names and conditions Ratings Units
Min Typ. Max
Output voltages Vout1 VDDCORE1/
VDDCORE2 — 1.2 — V
Table 5-6 Built-in regulator characteristics (VBAT = 1.8 to 3.6 V, VSSA = VSSRFIO = VSSDC = VSSD = VSSX = 0 V)
Items Symbols Pin names and conditions Ratings Units
Min Typ. Max
Output voltages Vout2 VDDIOFQ — 1.7 — V
5.5. ADC Characteristics
Table 5-7 ADC characteristics (VBAT = 1.8 to 3.6 V, VSSA = VSSRFIO = VSSDC = VSSD = VSSX = 0 V)
Items Symbols Condition Ratings Unit
Min Typ. Max
Analog reference voltage VREFH — 1.8 3.0 3.6 V
Analog input voltage VAIN — VSSD — VREFH V
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5.6. RF Characteristics (Design value)
The following conditions are applicable unless otherwise specified.
Ta = 25°C
VBAT = 3.0 V
fx’tal = 26 MHz (Frequency accuracy is adjusted to ±2 ppm at normal temperature)
PAOUT= 0 dBm
Table 5-8, Table 5-9 shows RF receiving characteristics and RF transmitting characteristics based on Bluetooth® Core Spec. V4.2
low energy.
About some the characteristics data here are design values.
Table 5-8 RF Characteristic
Test Item Packet bit ch. Condition
Spec.
Unit
Min Typ. Max
Output Power 255
octets PRBS9 0,12,
19,39
peak — — Pavg+
3 dB dBm
average — 0 —
In-band Emissions
255
octets PRBS9 0,12,
19,39
-5 MHz — -60 -30
dBm
-4 MHz — -55 -30
-3 MHz — -53 -30
-2 MHz — -48 -20
2 MHz — -50 -20
3 MHz — -53 -30
4 MHz — -56 -30
5 MHz — -60 -30
Modulation
Characteristics
255
octets
11110000
0,12,
19,39
Δf1avg (11110000) 225 249.3 275 kHz
10101010 Δf2max (99.9 %) 99.9 100 — %
— Δf2avg /Δf1avg 0.8 0.90 — Ratio
Carrier frequency
offset (CFO)
255
octets 10101010
0,12,
19,39
average — 4.4 —
kHz
worst -150 — 150
Carrier frequency
drift
255
octets
10101010 Absolute maximum — 4.9 50 kHz
Carrier frequency
drift Rate
255
octets
10101010 Absolute maximum — 4.9 20 kHz/50 μs
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Table 5-9 RF Characteristics
Test Item Sub Item Packet bit ch. Condition Min Typ. Max Unit
Rx Sensitivity — 37 octets — 0,12,
19,3
PER=30.8 %
at 1500 packets
with dirty
— -93.5 — dBm
C/I and Receiver
Selectivity
Performance
PER=30.8 %
at 1500
packets
with dirty
255 octets
D wave:
PRBS9
U wave:
GFSK
PRBS15
0,2,12,
19,37,
39
<=- -7 MHz — -38 or
less
—
dB
-6 MHz — -32 —
-5 MHz
—
-26
—
-4 MHz — -30 —
-3 MHz —
-32 —
-2 MHz — -35 —
-1 MHz —
-2 —
0 MHz
—
8
—
1 MHz —
-2 —
2 MHz
—
-30
—
3 MHz — -38 —
4 MHz
—
-40 —
5 MHz — -44 —
=> 6 MHz — -38 or
less
—
Blocking
Performance — 255 octets
D wave:
PRBS9
U wave: CW
12
30-2000 MHz -30 — —
dBm
2003-2399 MHz
-35
—
—
2484-2997 MHz -35 — —
3000 M-12.75 GHz -30 — —
Intermodulation
Performance 1500 packets 255 octets
f1=-50 dBm
with
un-modulati
on
f2=-50 dBm
with
PRBS15
0,12,
19,39
-4 MHz
30.8 0 — %
+4 MHz
Maximum input
signal level
PER 255 octets PRBS9 0,12,
19,39
-10 dBm 30.8 0 — %
PER Report
Integrity
PER 255 octets PRBS9 0,12,
19,39
-30 dBm 50 50 65.4 %
Note: C/I characteristic and blocking characteristic has the relief specs of the logo attestation test of Bluetooth® maybe applied. The
blocking characteristic measures D wave as 12 ch.
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5.7. AC Interface Characteristics (Design value)
5.7.1. UART Interface
Table 5-10 UART Interface AC characteristics
Symbols Items Min Typ. Max Unit
tCLDTDLY Transmit Data ON from CTSX Low level 192 — — ns
tCHDTDLY Transmit Data OFF from CTSX High level — — 2 byte
tRLDTDLY Received Data ON from RTSX Low level 0 — — ns
tRHDTDLY Received Data OFF from RTSX High level — — 8 byte
CTSX
TXD
tCLDTDLY
START BIT0BIT1BIT2BIT3BIT4BIT5BIT6BIT7STOP
tCHDTDLY
tTXDIV
RTSX
RXD
tRLDTDLY
START BIT0BIT1BIT2BIT3BIT4BIT5BIT6BIT7STOP
tRHDTDLY
tRXDIV
Figure 5-1 UART Interface T iming Diagram
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5.7.2. I2C Interface
5.7.2.1. Normal Mode
Table 5-11 I2C Interface Normal mode A C Characteristics
Symbols Items Min Typ. Max Unit
tDATS Data set-up time 250 — — ns
tDATH Data hold time 300 — — ns
tDATVD Data validity period — — 3450 ns
tACKVD ACK validity period — — 3450 ns
tSTAS Restart condition set-up time 4700 — — ns
tSTAH Restart condition hold time 4000 — — ns
tSTOS Stop condition set-up time 4000 — — ns
tBUF Bus open period from stop condition to start
condition 4700 — — ns
tr Rise up time — — 1000 ns
tf Fall down time — — 300 ns
tHIGH Serial clock period of High 4000 — — ns
tLOW Serial clock period of Low 4700 — — ns
Cb Bus load capacitance — — 400 pF
70%
30%
70%
30
%
tf
tLOW
tHIGH tD ATV D
tDATH
tDATS
1/fS CL
70%
30%
70%
30%
tACKVD
tS TO S
tB UF
tSTAH
S
Sr P S
1
st
clock
tr
tf tr
2
nd
clock 3
rd
clock 9
th
clock
9
th
clock
SDA
SCL
S :START condition
Sr : Repeated START Condition
P : STOP condition
tSTAH
tSTAS
SCL
SDA
Figure 5-2 I2C Interface Normal mode Timing diagram
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5.7.2.2. Fast mode
Table 5-12 I2C Interface Fast mode A C Characteristics
Symbols Items Min Typ. Max Unit
tDATS Data set-up time 100 — — ns
tDATH Data hold time 300 — — ns
tDATVD Datavalidity period — — 900 ns
tACKVD ACKvalidity period — — 900 ns
tSTAS Restart condition set-up time 600 — — ns
tSTAH Restart condition hold time 600 — — ns
tSTOS Stop condition set-up time 600 — — ns
tBUF Bus open period from stop condition to start
condition 1300 — — ns
tr Rise up time 20 + 0.1Cb — 300 ns
tf Fall down time 20 + 0.1Cb — 300 ns
tSP Spike pulse width that can be removed 0 — 50 ns
tHIGH Serial clock period of High — 1423 — ns
tLOW Serial clock period of Low — 1423 — ns
Cb Bus load capacitance — — 400 pF
70%
30%
70%
30
%
tf
tLOW
tHIGH tD ATV D
tDATH
tDATS
1/fS CL
70%
30%
70%
30%
tSP tACKVD
tS TO S
tB UF
tSTAH
S
Sr P S
1
st
clock
tr
tf tr
2
nd
clock 3
rd
clock 9
th
clock
9
th
clock
SDA
SCL
S : START condition
Sr : Repeated START Condition
P : STOP condition
tSTAH
tSTAS
SDA
SCL
Figure 5-3 I2C Interface Fast mode Timing diagr am
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5.7.3. SPI Interface
Table 5-13 SPI Interface
Symbols Items Min Typ. Max Unit
tSPICLKCYC SPI clock cycle 154 — — ns
tSPICLKHPW SPI clock high pulse width 77 — — ns
tSPICLKLPW SPI clock low pulse width 77 — — ns
tSPICSS SPI chip select setup time 38 — — ns
tSPICSH SPI chip select hold time 77 — — ns
tSPIIW SPI transfer idle pulse width 54 — — ns
tSPIAS SPI address setup time 38 — — ns
tSPIAH SPI address hold time 77 — — ns
tSPIDS SPI data setup time 38 — — ns
tSPIDH SPI data hold time 77 — — ns
Note: SPI Interface operates on the basis of 1/n frequency of half the frequency of ARM® Cortex®-M0 core clock (6.5 MHz for 13
MHz core clock)
Figure 5-4 SPI Interface timing diagram
SCLK
ｔSPICSS
ｔSPIAS
ｔSPIAH
A7
ｔSPICSH
A6 A5 A4WR A0 D15 D14 D1 D0 A7 A6
SCS
DOUT
Write
ｔSPICLKHPW
ｔSPICLKLPW
ｔSPIDS
ｔSPIDH
ｔSPIIW
SCLK
ｔSPICSS
ｔSPIAS
ｔSPIAH
A7
ｔSPICSH
A6 A5 A4WR A0 D15 A7 A6
SCS
DIN
Read
ｔSPICLKHPW
ｔSPICLKLPW
ｔSPIDS
ｔSPIDH
ｔSPIIW
ｔSPICL KCY C
ｔSPICL KCY C
D14 D0D1
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5.8. Characteristics of Flash-ROM block
Table 5-14 Characteristics of Flash-R OM block (VBAT=2.0 to 3.6 V, VSSA = VSSRFIO = VSSDC = VSSD = VSSX = 0 V)
Item Symbol Condition Ratings Unit
Min Typ. Max
Number of times of
erase and program — Ta=25°C 105 — — times
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6. System Configuration Example
An example of system configuration is shown in the following figures.
6.1. In HCI mode
Host interface=UART and 26 MHz Reference Clock= XOSC Connection.
XOSC (32.768 kHz) of the dotted line enclosure is unnecessary when the external input (HOST common use) is chosen.
GPIO and SWD of connection is the connection example of when not in use.
Figure 6-1 Example of TC3567CFSG system configuration (HCI mode)
HOST I /F
UART_RX
UART_TX
WakeUP 0
RESE TX
VDD
1µF
0.1µF
18 VB AT
1VDDIO1
19 LX
14 VDDCORE1
15 VDDCORE2
4TMODE
5VP GM
13 VS SX
20 VS SDC
FIN VS SD
7RFIO
6VS SRFIO
8VS SA
TRTEST1
10 TRTEST2
26
GPIO10
30
GPIO329
GPIO4
28
GPIO9
35
GPIO11 34
GPIO12
32
SW D CL K
17
SWDIO
25
GPIO13
2
GPIO25
31
GPIO0
39
38
37
36
GPIO5
3
RESE TX
21
SL PXO IN
22
SL PXO OUT
12
XO OUT
11
XO IN
26.00 0M Hz
2
3X2 4
1
X1
32.76 8KHz
2X2
1X1
ANT
Coa xial Con nect er
VDD
BA T_1
2 1
1µF
10µH
2
6
5
4
3
1
Sl e epCl ockI N
M LZ16 08 N10 0LT
27 VDDIOFQ
0.1µF
23 VDDIO2
VDD
GPIO6
GPIO7
GPIO8
WakeUP 1
33
GPIO15
24
GPIO14
9
40
GPIO116
GPIO2
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6.2. In User-App mode
XOSC (32.768 kHz) of the dotted line enclosure is unnecessary when the external input (HOST common use) is chosen.
GPIO and SWD of connection is the connection example of when not in use.
VDD
1µF
0.1µF
18 VB AT
1VDDIO1
19 LX
14 VDDCORE1
15 VDDCORE2
4TMODE
5VP GM
13 VS SX
20 VS SDC
FIN VS SD
7RFIO
6VS SRFIO
8VS SA
TRTEST1
10 TRTEST2
31
GPIO0
3
RESE TX
21
SL PXO IN
22
SL PXO OUT
12
XO OUT
11
XO IN
26.00 0M Hz
2
3X2 4
1
X1
32.76 8KHz
2X2
1X1
ANT
Coa xial Con nect er
VDD
BA T_1
2 1
1µF
10µH
2
6
5
4
3
1
Sl e epCl ockI N
M LZ16 08 N10 0LT
27 VDDIOFQ
0.1µF
23 VDDIO2
VDD
33
GPIO15
9
26
GPIO10
30
GPIO329
GPIO4
28
GPIO9
35
GPIO11 34
GPIO12
32
SW D CL K
17
SWDIO
25
GPIO13
2
GPIO25
39
38
GPIO7
GPIO8
24
GPIO14
40
GPIO116
GPIO2
37
36
GPIO5
GPIO6
Figure 6-2 Example of TC3567CFSG system configuration (User-App mode)
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7. Package outline
7.1. Outline dimensional drawing TC3567CFSG (P-VQFN40-0505-0.40-005/F01)
Figure 7-1 Package outline (P-VQFN40-0505-0.40-005/F01)
Unit: mm
Weight: 0.068 g (Typ.)
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RESTRICTIONS ON PRODUCT USE
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