ATA6612C/ATA6613C 8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog DATASHEET General Features Single-package fully-integrated Atmel(R) AVR(R) 8-bit microcontroller with LIN transceiver, 5V regulator (85mA current capability) and watchdog Very low current consumption in sleep mode 8Kbytes/16Kbytes flash memory for application program (Atmel ATA6612C/ATA6613C) Supply voltage up to 40V Operating voltage: 5V to 27V Temperature range: Tcase -40C to +125C QFN48, 7mm x 7mm package Description Atmel ATA6612C/ATA6613C is a system-in-package (SiP) product, which is particularly suited for complete LIN-bus slave-node applications. I consists of two ICs in one package supporting highly integrated solutions for in-vehicle LIN networks. The first chip is the LIN-system-basis-chip (LIN-SBC) Atmel ATA6624, which has an integrated LIN transceiver, a 5V regulator and a window watchdog. The second chip is an automotive microcontroller from Atmel series of Atmel AVR 8-bit microcontroller with advanced RISC architecture. The Atmel ATA6612C consists of the LIN-SBC Atmel ATA6624 and the Atmel ATmega88 with 8Kbytes flash. The Atmel ATA6613C consists of the LIN-SBC Atmel ATA6624 and the Atmel ATmega168 with 16Kbytes flash. All pins of the LIN system basis chip as well as all pins of the Atmel AVR microcontroller are bonded out to provide customers the same flexibility for their applications as they have when using discrete parts. In section 2 you will find the pin configuration for the complete SiP. In sections 3 to 5 the LIN SBC is described, and in sections 6 to 7 the Atmel AVR is described in detail. 9111L-AUTO-11/14 Figure 1. Application Diagram LIN Bus Atmel ATA6612C/ATA6613C MCU Atmel ATmega88 or ATmega168 2 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 LIN-SBC Atmel ATA6624 Pin Configuration PB4 PB3 PB2 PB1 PB0 PD7 PD6 PD5 PB7 PB6 MCUVCC GND2 Figure 1-1. Pinning QFN48, 7mm x 7mm 48 47 46 45 44 43 42 41 40 39 38 37 PB5 MCUAVCC ADC6 AREF 1 2 36 3 34 GND4 ADC7 PC0 PC1 PC2 PC3 PC4 PC5 5 35 4 6 7 8 33 Atmel ATA6612C/ ATA6613C 32 31 30 29 9 28 10 27 11 26 12 25 MCUVCC GND1 PD4 PD3 LIN GND WAKE NTRIG EN VS VCC PVCC 13 14 15 16 17 18 19 20 21 22 23 24 PC6 PD0 PD1 PD2 RXD INH TXD NRES WD_OSC TM MODE KL_15 1. Table 1-1. Pin Description Pin Symbol Function 1 PB5 2 MCUAVCC 3 ADC6 ADC input channel 6 4 AREF Analog reference voltage input 5 GND4 Ground 6 ADC7 ADC input channel 7 7 PC0 Port C 0 I/O line (ADC0/PCINT8) 8 PC1 Port C 1 I/O line (ADC1/PCINT9) 9 PC2 Port C 2 I/O line (ADC2/PCINT10) 10 PC3 Port C 3 I/O line (ADC3/PCINT11) 11 PC4 Port C 4 I/O line (ADC4/SDA/PCINT12) 12 PC5 Port C 5 I/O line (ADC5/SCL/PCINT13) 13 PC6 Port C 6 I/O line (RESET/PCINT14) 14 PD0 Port D 0 I/O line (RXD/PCINT16) 15 PD1 Port D 1 I/O line (TXD/PCINT17) Port B 5 I/O line (SCK / PCINT5) Microcontroller ADC-unit supply voltage (referred to as AVCC pin in Section 5. "Microcontroller Block" on page 27 and Section 6. "2-wire Serial Interface Characteristics" on page 276) 16 PD2 Port D 2 I/O line (INT0/PCINT18) 17(1) RXD Receive data output 18 (1) INH High side switch output for controlling an external voltage regulator 19 Note: (1) 1. TXD Transmit data input / active low output after a local wake up request This identifies the pins of the LIN SBC Atmel ATA6624 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 3 Table 1-1. Pin 20 Pin Description (Continued) Symbol (1) 21(1) NRES Watchdog and under voltage reset output (open drain) WD_OSC External resistor for adjustable watchdog timing 22(1) TM Tie to ground - for factory use only 23 (1) MODE Connect to GND for normal watchdog operation or connect to VCC for debug mode 24 (1) KL_15 Ignition detection (edge sensitive) 25(1) PVCC Voltage regulator sense input 26 (1) VCC 27 (1) VS Battery connection 28 (1) EN LIN-transceiver enable input Voltage regulator output 29(1) NTRIG Watchdog trigger input (negative edge) 30 (1) WAKE System-basis-chip external wake-up input 31 (1) GND Analog system GND 32 (1) LIN LIN-bus input/output 33 PD3 Port D 3 I/O line (INT1 OC2B/PCINT19) 34 PD4 Port D 4 I/O line (T0/XCK/PCINT20) 35 GND1 36 MCUVCC 37 GND2 38 MCUVCC 39 PB6 Port B 6 I/O line (TOSC1/XTAL1/PCINT6) 40 PB7 Port B 7 I/O line (TOSC2/XTAL2/PCINT7) 41 PD5 Port D 5 I/O line (T1/OC0B/PCINT21) 42 PD6 Port D 6 I/O line (AIN0/OC0A PCINT22) 43 PD7 Port D 7 I/O line (AIN1/PCINT23) 44 PB0 Port B 0 I/O line (ICP1/CLKO/PCINT0) 45 PB1 Port B 1 I/O line (OC1A/PCINT1) 46 PB2 Port B 2 I/O line (OC1B/SS/PCINT2) 47 PB3 Port B 3 I/O line (MOSI/OC2A/PCINT3) 48 PB4 Port B 4 I/O line (MISO/PCINT4) Backside Note: 1. 4 Function Ground Microcontroller supply voltage (referred to as VCC pin in Section 5. "Microcontroller Block" on page 27 and Section 6. "2-wire Serial Interface Characteristics" on page 276) Ground Microcontroller supply voltage (referred to as VCC pin in Section 5. "Microcontroller Block" on page 27 and Section 6. "2-wire Serial Interface Characteristics" on page 276) Heat slug is connected to GND This identifies the pins of the LIN SBC Atmel ATA6624 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 2. Absolute Maximum Ratings Table 2-1. Maximum Ratings of the SiP Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol HBM ESD ANSI/ESD -STM5.1 JESD22 -A114 AEC-Q100 (002) Min. Typ. Max. Unit 2 KV CDM ESD STM 5.3.1 Corner pins (1, 12, 13, 24, 25, 36, 37, 48) All other pins 750 500 V V Machine model ESD AEC-Q100-Rev.F (003) 100 V ESD according to IBEE LIN EMC Test Spec. 1.0 following IEC 61000-4-2 - Pin VS, LIN, KL_15 (47k/100nF) to GND - Pin WAKE (33 k serial resistor) to GND 6 5 KV KV 6 KV ESD HBM following STM5.1 with 1.5k 100pF - Pin VS, LIN, KL_15, WAKE to GND Storage temperature Operating temperature (1) Ts -55 +150 C Tcase -40 +125 C Thermal resistance junction to heat slug Rthjc 5 K/W Thermal resistance junctiion to ambient Rthja 25 K/W Thermal shutdown of VCC regulator 150 165 170 C Thermal shutdown of LIN output 150 165 170 C Thermal shutdown hysteresis 10 C Note: 1. Tcase means the temperature of the heat slug (backside). It is mandatory that this backside temperature is 125C in the application. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5 Table 2-2. Maximum Ratings of the LIN-SBC Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Supply voltage VS VS -0.3 Pulse time 500ms; Ta = 25C Output current IVCC 85mA Pulse time 2min; Ta = 25C Output current IVCC 85mA Max. Unit +40 V VS +40 V VS 27 V -1 -150 +40 +100 V V INH - DC voltage -0.3 VS + 0.3 V LIN - DC voltage -27 +40 V Logic pins (RxD, TxD, EN, NRES, NTRIG, WD_OSC, MODE, TM) -0.3 +5.5 WAKE (with 33k serial resistor) KL_15 (with 47k/100nF) DC voltage Transient voltage due to ISO7637 (coupling 1nF) Output current NRES INRES PVCC DC voltage VCC DC voltage Table 2-3. Typ. -0.3 -0.3 V +2 mA +5.5 +6.5 V V Maximum Ratings of the Microcontroller Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters 6 Symbol Min. Typ. Max. Unit Voltage on any pin except RESET with respect to ground -0.5 MCUVCC + 0.5 V Voltage on RESET with respect to ground -0.5 13.0 V Maximum operating voltage 6.0 V DC current per I/O pin 40.0 mA DC current MCUVCC and GND pins 200.0 mA Injection current at MCUVCC = 0V(1) 5.0 mA Injection current at MCUVCC = 5V Note: 1. Maximum current per port = 30mA 1.0 mA ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 3. LIN System-basis-chip Block 3.1 Features Master and slave operation possible Supply voltage up to 40V Operating voltage VS = 5V to 27V Typically 10A supply current during sleep mode Typically 57A supply current in silent mode Linear low-drop voltage regulator, 85mA current capability: Normal, fail-safe, and silent mode In sleep mode VCC is switched off VCC = 5.0V 2% VCC - undervoltage detection (4ms reset time) and watchdog reset logical combined at open drain output NRES Negative trigger input for watchdog Boosting the voltage regulator possible with an external NPN transistor LIN physical layer according to LIN 2.0, 2.1 specification and SAEJ2602-2 Wake-up capability via LIN-bus, wake pin, or Kl_15 pin INH output to control an external voltage regulator or to switch off the master pull Up resistor TXD time-out timer Bus pin is over temperature and short circuit protected versus GND and battery Adjustable watchdog time via external resistor Advanced EMC and ESD performance Fulfills the OEM "hardware requirements for LIN in automotive applications Rev.1.0" Interference and damage protection according ISO7637 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 7 3.2 Description The LIN-SBC ATA6624 is a fully integrated LIN transceiver, which complies with the LIN 2.0, 2.1 and SAEJ2602-2 specifications. It has a low-drop voltage regulator for 5V/85mA output and a window watchdog. The voltage regulator is able to source up to 85mA, but the output current can be boosted by using an external NPN transistor. The LIN-SBC is designed to handle the low-speed data communication in vehicles, e.g., in convenience electronics. Improved slope control at the LIN-driver ensures secure data communication up to 20kBaud. Sleep mode and silent mode guarantee very low current consumption. Figure 3-1. Block Diagram VS Normal and Fail-safe Mode INH PVCC Normal Mode Receiver RXD + RF Filter LIN WAKE KL_15 PVCC TXD Edge Detection Wake-up Bus Timer Slew Rate Control TXD Time-out Timer Control Unit EN Short Circuit and Overtemperature Protection Debounce Time Normal/Silent/ Fail-safe Mode 5V Undervoltage Reset OUT Watchdog GND PVCC 8 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 PVCC Mode Select Internal Testing Unit MODE VCC TM NTRIG NRES Adjustable Watchdog Oscillator WD_OSC 3.3 Functional Description 3.3.1 Physical Layer Compatibility Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer nodes, which are according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), without any restrictions. 3.3.2 Supply Pin (VS) The LIN operating voltage is VS = 5V to 27V. An under voltage detection is implemented to disable data transmission if VS falls below VSth < 4V in order to avoid false bus messages. After switching on VS, the IC starts in fail-safe mode, and the voltage regulator is switched on (i.e., output capability). The supply current is typically 10A in sleep mode and 57A in silent mode. 3.3.3 Ground Pin (GND) The IC does not affect the LIN bus in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of versus The mandatory system ground is pin 5. 3.3.4 Voltage Regulator Output Pin (VCC) The internal voltage regulator is capable of driving loads with up to 85mA. It is able to supply the microcontroller and other ICs on the PCB and is protected against overloads by means of current limitation and over temperature shut-down. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun. To boost up the maximum load current, an external NPN transistor may be used, with its base connected to the VCC pin and its emitter connected to PVCC. 3.3.5 Voltage Regulator Sense Pin (PVCC) The PVCC is the sense input pin of the voltage regulator. For normal applications (i.e., when only using the internal output transistor), this pin is connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must be connected to the output of this transistor, i.e., its emitter terminal. 3.3.6 Bus Pin (LIN) A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor compliant with the LIN 2.x specification are implemented. The allowed voltage range is between -27V and +40V. Reverse currents from the LIN bus to VS are suppressed, even in the event of GND shifts or battery disconnection. LIN receiver thresholds are compatible with the LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to recessive bus state are slope controlled. 3.3.7 Input/Output Pin (TXD) In normal mode the TXD pin is the microcontroller interface used to control the state of the LIN output. TXD must be pulled to ground in order to have a low LIN-bus. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is turned off, and the bus is in recessive state. During fail-safe mode, this pin is used as output. It is current-limited to < 8mA. and is latched to low if the last wake-up event was from pin WAKE or KL_15. 3.3.8 TXD Dominant Time-out Function The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in dominant state. If TXD is forced to low for longer than tDOM > 6ms, the LIN-bus driver is switched to recessive state. To reactivate the LIN bus driver, switch TXD to high (>10s). 3.3.9 Output Pin (RXD) The output pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typically 5k to VCC. The AC characteristics can be defined with an external load capacitor of 20pF. The output is short-circuit protected. RXD is switched off in Unpowered mode (i.e., VS = 0V). ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 9 3.3.10 Enable Input Pin (EN) The enable Input pin controls the operation mode of the device. If EN is high, the circuit is in normal mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 5V/85mA output capability. If EN is switched to low while TXD is still high, the device is forced to silent mode. No data transmission is then possible, and the current consumption is reduced to IVS typ. 57A. The VCC regulator has its full functionality. If EN is switched to low while TXD is low, the device is forced to sleep mode. No data transmission is possible, and the voltage regulator is switched off. 3.3.11 Wake Input Pin (WAKE) The wake input pin is a high-voltage input used to wake up the device from sleep mode or silent mode. It is usually connected to an external switch in the application to generate a local wake-up. A pull-up current source, typically 10A, is implemented. If a local wake-up is not needed for the application, connect the Wake pin directly to the VS pin. 3.3.12 Mode Input Pin (MODE) Connect the MODE pin directly or via an external resistor to GND for normal watchdog operation. To debug the software of the connected microcontroller, connect the MODE pin to VCC and the watchdog is switched off. 3.3.13 TM Input Pin The TM pin is used for final production measurements at Atmel(R). In normal application, it has to be always connected to GND. 3.3.14 KL_15 Pin The KL_15 pin is a high-voltage input used to wake up the device from sleep or silent mode. It is an edge sensitive pin (low-to-high transition). It is usually connected to ignition to generate a local wake-up in the application when the ignition is switched on. Although KL_15 pin is at high voltage (VBatt), it is possible to switch the IC into sleep or silent mode. Connect the KL_15 pin directly to GND if you do not need it. A debounce timer with a typical TdbKl_15 of 160s is implemented. The input voltage threshold can be adjusted by varying the external resistor due to the input current IKL_15. To protect this pin against voltage transients, a serial resistor of 47k and a ceramic capacitor of 100nF are recommended. With this RC combination you can increase the wake-up time TwKL_15 and, therefore, the sensitivity against transients on the ignition Kl.15. The wake-up time can also be increased by using external capacitors with higher values. 3.3.15 INH Output Pin The INH Output pin is used to switch on an external voltage regulator during normal or fail-safe mode. The INH pin is switched off in sleep or silent mode. It is possible to switch off the external 1k master resistor via the INH pin for master node applications. The INH pin is switched off during VCC under voltage reset. 3.3.16 Reset Output Pin (NRES) The reset output pin, an open drain output, switches to low during VCC under voltage or a watchdog failure. 3.3.17 WD_OSC Output Pin The WD_OSC output pin provides a typical voltage of 1.2V, which supplies an external resistor with values between 34k and 120k to adjust the watchdog oscillator time. 3.3.18 NTRIG Input Pin The NTRIG input pin is the trigger input for the window watchdog. A pull-up resistor is implemented. A negative edge triggers the watchdog. The trigger signal (low) must exceed a minimum time ttrigmin to generate a watchdog trigger. 10 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 3.3.19 Wake-up Events from Sleep or Silent Mode LIN-bus WAKE pin EN pin KL_15 3.3.20 Modes of Operation Figure 3-2. Modes of Operation a: VS > 5V Unpowered Mode VBatt = 0V b b: VS < 4V c: Bus wake-up event d: Wake up from WAKE or KL_15 pin a e: NRES switches to low b Fail-safe Mode VCC: 5V/85mA With undervoltage monitoring Communication: OFF Watchdog: ON b e EN = 1 b c+d+e EN = 1 c+d Go to silent command EN = 0 Silent Mode TXD = 1 VCC: 5V/85mA With undervoltage monitoring Communication: OFF Watchdog: OFF Local wake-up event Normal Mode EN = 1 VCC: 5V/85mA With undervoltage monitoring Go to sleep command EN = 0 Communication: ON Watchdog: ON Table 3-1. Sleep Mode TXD = 0 VCC: switched off Communication: OFF Watchdog: OFF Table of Modes Mode of Operation Transceiver VCC Watchdog WD_OSC INH RXD LIN Fail-safe Off 5V On 1.23V On High, except after wake-up Recessive Normal On 5V On 1.23V On LIN depending TXD depending Silent Off 5V Off 0V Off High Recessive Sleep Off 0V Off 0V Off 0V Recessive 3.3.20.1 Normal Mode This is the normal transmitting and receiving mode at the LIN interface in accordance with the LIN specification LIN 2.x. The voltage regulator is active and can source up to 85mA. The under voltage detection is activated. The watchdog needs a trigger signal from NTRIG to avoid resets at NRES. If NRES is switched to low, the IC changes its state to fail-safe mode. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 11 3.3.20.2 Silent Mode A falling edge at EN when TXD is high switches the IC into silent mode. The TXD signal has to be logic high during the mode select window (see Figure 3-3). The transmission path is disabled in silent mode. The overall supply current from VBatt is a combination of the IVSsi 57A plus the VCC regulator output current IVCC. The internal slave termination between the LIN pin and the VS pin is disabled in silent mode, only a weak pull-up current (typically 10A) between the LIN pin and the VS pin is present. silent mode can be activated independently from the actual level on the LIN, WAKE, or KL_15 pins. If an under voltage condition occurs, NRES is switched to low, and the IC changes its state to fail-safe mode. A voltage lower than the LIN pre_wake detection VLINL at the LIN pin activates the internal LIN receiver and switches on the internal slave termination between the LIN pin and the VS pin. Figure 3-3. Switch to Silent Mode Normal Mode Silent Mode EN TXD Mode select window td = 3.2s NRES VCC Delay time silent mode td_sleep = maximum 20s LIN LIN switches directly to recessive mode 12 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) and followed by a rising edge at the LIN pin (see Figure 3-4) result in a remote wake-up request. The device switches from silent mode to fail-safe mode. The remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (see Figure 3-4). EN high can be used to switch directly to normal mode. Figure 3-4. LIN Wake-up from Silent Mode Bus wake-up filtering time tbus Fail-safe mode Normal mode LIN Bus Node in silent mode RXD High Low High TXD Watchdog VCC Voltage Regulator Watchdog off Start watchdog lead time td Silent mode 5V Fail safe mode 5V Normal mode EN High EN NRES Undervoltage detection active ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 13 3.3.20.3 Sleep Mode A falling edge at EN when TXD is low switches the IC into sleep mode. The TXD signal has to be logic low during the mode select window (Figure 3-5). In order to avoid any influence to the LIN-pin during switching into sleep mode it is possible to switch the EN up to 3.2s earlier to LOW than the TXD. Therefore, the best and easiest way are two falling edges at TXD and EN at the same time.The transmission path is disabled in sleep mode. The supply current IVSsleep from VBatt is typically 10A. The VCC regulator and the INH output are switched off. NRES and RXD are low. The internal slave termination between the LIN pin and VS pin is disabled, only a weak pull-up current (typically 10A) between the LIN pin and the VS pin is present. sleep mode can be activated independently from the current level on the LIN, WAKE, or KL_15 pin. A voltage lower than the LIN pre_wake detection VLINL at the LIN pin activates the internal LIN receiver and switches on the internal slave termination between the LIN pin and the VS pin. A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) and followed by a rising edge at pin LIN results in a remote wake-up request. The device switches from sleep mode to fail-safe mode. The VCC regulator is activated, and the remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (see Figure 3-6 on page 15). EN high can be used to switch directly from sleep/silent to fail-safe mode. If EN is still high after VCC ramp up and under voltage reset time, the IC switches to the normal mode. Figure 3-5. Switch to Sleep Mode Normal Mode Sleep Mode EN Mode select window TXD td = 3.2s NRES VCC Delay time sleep mode td_sleep = maximum 20s LIN LIN switches directly to recessive mode 3.3.20.4 Fail-safe Mode The device automatically switches to fail-safe mode at system power-up and the voltage regulator is switched on (see Figure 3-7 on page 17). The NRES output switches to low for tres = 4ms and gives a reset to the microcontroller. LIN communication is switched off. The IC stays in this mode until EN is switched to high. The IC then changes to normal mode. A power down of VBatt (VS < 4V) during silent or sleep mode switches the IC into fail-safe mode. A low at NRES switches into fail-safe mode directly. During fail-safe mode the TXD pin is an output and signals the last wake-up source. 14 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 3.3.20.5 Unpowered Mode If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor (see Figure 3-7 on page 17). After VS is higher than the VS undervoltage threshold VSth, the IC mode changes from unpowered mode to fail-safe mode. The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends on the VCC capacitor and the load. The NRES is low for the reset time delay treset. During this time, treset, no mode change is possible. Figure 3-6. LIN Wake-up from Sleep Mode Bus wake-up filtering time tbus Fail-safe Mode Normal Mode LIN Bus RXD Low TXD VCC Voltage Regulator On state Off state Regulator wake-up time EN High EN Reset time NRES Microcontroller start-up time delay Watchdog Watchdog off Start watchdog lead time td 3.3.21 Wake-up Scenarios from Silent to Sleep Mode 3.3.21.1 Remote Wake-up via Dominant Bus State A voltage lower than the LIN pre_wake detection VLINL at the LIN pin activates the internal LIN receiver. A falling edge at the LIN pin followed by a dominant bus level VBUSdom maintained for a certain time period (> tBUS) and followed by a rising edge at pin LIN result in a remote wake-up request. The device switches from silent or sleep mode to fail-safe mode. The VCC voltage regulator is/remains activated, the INH pin is switched to high, and remote wake-up request is indicated by a low level at the RXD pin to generate an interrupt for the microcontroller. A low level at the LIN pin in the normal mode starts the bus wake-up filtering time, and if the IC is switched to silent or sleep mode, it will receive a wake-up after a positive edge at the LIN pin. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 15 3.3.21.2 Local Wake-up via Pin Wake A falling edge at the WAKE pin followed by a low level maintained for a certain time period (> tWAKE) results in a local wake-up request. The device switches to fail-safe mode. The local wake-up request is indicated by a low level at the RXD pin to generate an interrupt in the microcontroller and a strong pull down at TXD. When the wake pin is low, it is possible to switch to silent or sleep mode via pin EN. In this case, the wake-up signal has to be switched to high >10s before the negative edge at WAKE starts a new local wake-up request. 3.3.21.3 Local Wake-up via Pin KL_15 A positive edge at pin KL_15 followed by a high voltage level for a certain time period (>tKL_15) results in a local wake-up request. The device switches into the fail-safe mode. The extra long wake-up time ensures that no transients at KL_15 create a wake up. The local wake-up request is indicated by a low level at the RXD pin to generate an interrupt for the microcontroller and a strong pull down at TXD. During high-level voltage at pin KL_15, it is possible to switch to silent or sleep mode via pin EN. In this case, the wake-up signal has to be switched to low >250s before the positive edge at KL_15 starts a new local wake-up request. With external RC combination, the time is even longer. 3.3.21.4 Wake-up Source Recognition The device can distinguish between a local wake-up request (Wake or KL_15 pins) and a remote wake-up request (via LIN bus). The wake-up source can be read on the TXD pin in fail-safe mode. A high level indicates a remote wake-up request (weak pull up at the TXD pin); a low level indicates a local wake-up request (strong pull down at the TXD pin). The wake-up request flag (signalled on the RXD pin), as well as the wake-up source flag (signalled on the TXD pin), is immediately reset if the microcontroller sets the EN pin to high (see Figure 3-3 on page 12 and Figure 3-4 on page 13) and the IC is in normal mode. The last wake-up source flag is stored and signalled in fail-safe mode at the TXD pin. 3.3.22 Fail-safe Features 16 During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_LIM. Due to the power dissipation, the chip temperature exceeds TLINoff, and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. RXD stays on high because LIN is high. During LIN over temperature switch-off, the VCC regulator works independently. During a short-circuit from LIN to GND the IC can be switched into sleep or silent mode. If the short-circuit disappears, the IC starts with a remote wake-up. The reverse current is very low <15A at the LIN pin during loss of VBatt or GND. This is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. During a short circuit at VCC, the output limits the output current to IVCCn. Because of under voltage, NRES switches to low and sends a reset to the microcontroller. The IC switches into fail-safe mode. If the chip temperature exceeds the value TVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output on again. Because of the fail-safe mode, the VCC voltage will switch on again although EN is switched off from the microcontroller. The microcontroller can start with its normal operation. EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected. If the resistor at WO_OSC pin is disconnected, the watchdog runs with an internal oscillator and guarantees a reset after the second NTRIG signal at the latest. RXD pin is set floating if VBatt is disconnected. TXD pin provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected. If TXD is short-circuited to GND, it is possible to switch to sleep mode via ENABLE after tdom >20ms. If the WD_OSC pin has a short-circuit to GND and the NTRIG signal has a period time >27ms, the watchdog runs with an internal oscillator and guarantees a reset after the second NTRIG signal at the latest. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 3.3.23 Voltage Regulator The voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the microcontroller. It is recommended to use an electrolytic capacitor with C 1.8F and a ceramic capacitor with C = 100nF. The values of these capacitors can be varied by the customer, depending on the application. The main power dissipation of the IC is created from the VCC output current IVCC, which is needed for the application. In Figure 3-8 the safe operating area is shown. Figure 3-7. VCC Voltage Regulator: Ramp Up and Undervoltage Detection VS 12V 5.5V t VCC 5V Vthun tVCC tres_f tReset t NRES 5V t Figure 3-8. Power Dissipation: Safe Operating Area VCC Output Current versus Supply Voltage VS at Different Ambient Temperatures 90 80 Tamb = 100C IVCC (mA) 70 60 Tamb = 105C 50 Tamb = 110C 40 30 Tamb = 115C 20 10 0 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VS (V) For programming purposes of the microcontroller it is potentially necessary to supply the VCC output via an external power supply while the VS pin of the system basis chip is disconnected. This will not affect the system basis chip. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 17 3.3.24 Watchdog The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge) input within a time window of Twd. The trigger signal must exceed a minimum time ttrigmin > 200ns. If a triggering signal is not received, a reset signal will be generated at output NRES. After a watchdog reset the IC starts with the lead time. The timing basis of the watchdog is provided by the internal oscillator. Its time period, Tosc, is adjustable via the external resistor Rwd_osc (34k to 120k). During silent or sleep mode the watchdog is switched off to reduce current consumption. The minimum time for the first watchdog pulse is required after the under voltage reset at NRES disappears. It is defined as lead time td. After wake up from sleep or silent mode, the lead time td starts with the negative edge of the RXD output. 3.3.24.1 Typical Timing Sequence with RWD_OSC = 51k The trigger signal Twd is adjustable between 20ms and 64ms using the external resistor RWD_OSC. For example, with an external resistor of RWD_OSC = 51k 1%, the typical parameters of the watchdog are as follows: tosc = 0.405 x RWD_OSC - 0.0004 x (RWD_OSC)2 (RWD_OSC in k; tosc in s) tOSC = 19.6s due to 51k td = 7895 x 19.6s = 155ms t1 = 1053 x 19.6s = 20.6ms t2 = 1105 x 19.6s = 21.6ms tnres = constant = 4ms After ramping up the battery voltage, the 5V regulator is switched on. The reset output NRES stays low for the time treset (typically 4ms), then it switches to high, and the watchdog waits for the trigger sequence from the microcontroller. The lead time, td, follows the reset and is td = 155ms. In this time, the first watchdog pulse from the microcontroller is required. If the trigger pulse NTRIG occurs during this time, the time t1 starts immediately. If no trigger signal occurs during the time td, a watchdog reset with tNRES = 4ms will reset the microcontroller after td = 155ms. The times t1 and t2 have a fixed relationship between each other. A triggering signal from the microcontroller is anticipated within the time frame of t2 = 21.6ms. To avoid false triggering from glitches, the trigger pulse must be longer than tTRIG,min > 200ns. This slope serves to restart the watchdog sequence. If the triggering signal fails in this open window t2, the NRES output will be drawn to ground. A triggering signal during the closed window t1 immediately switches NRES to low. Figure 3-9. Timing Sequence with RWD_OSC = 51k VCC Undervoltage Reset NRES Watchdog Reset tnres = 4ms treset = 4ms td = 155ms t1 t1 = 20.6ms t2 = 21ms twd NTRIG ttrig > 200ns 18 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 t2 3.3.24.2 Worst Case Calculation with RWO_OSC = 51k The internal oscillator has a tolerance of 20%. This means that t1 and t2 can also vary by 20%. The worst case calculation for the watchdog period twd is calculated as follows. The ideal watchdog time twd is between the maximum t1 and the minimum t1 plus the minimum t2. t1,min = 0.8 x t1 = 16.5ms, t1,max = 1.2 x t1 = 24.8ms t2,min = 0.8 x t2 = 17.3ms, t2,max = 1.2 x t2 = 26ms twdmax = t1min + t2min = 16.5ms + 17.3ms = 33.8ms twdmin = t1max = 24.8ms twd = 29.3ms 4.5ms (15%) A microcontroller with an oscillator tolerance of 15% is sufficient to supply the trigger inputs correctly. Table 3-2. Typical Watchdog Timings RWD_OSC k Oscillator Period tosc/s Lead Time td/ms Closed Window t1/ms Open Window t2/ms Trigger Period from Microcontroller twd/ms Reset Time tnres/ms 34 13.3 105 14.0 14.7 19.9 4 51 19.61 154.8 20.64 21.67 29.32 4 91 33.54 264.80 35.32 37.06 50.14 4 120 42.84 338.22 45.11 47.34 64.05 4 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 19 4. Electrical Characteristics 5V < VS < 27V, -40C < Tcase < 125C, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins No. 1 1.1 1.2 1.3 Parameters Test Conditions Pin Symbol Min. VS VS 5 Sleep mode VLIN > VS - 0.5V VS < 14V (Tj = 25C) VS IVSsleep 3 Sleep mode VLIN > VS - 0.5V VS < 14V (Tj = 125C) VS IVSsleep Bus recessive VS < 14V (Tj = 25C) Without load at VCC VS Bus recessive VS < 14V (Tj = 125C) Without load at VCC Typ. Max. Unit Type* 27 V A 10 14 A B 5 11 16 A A IVSsi 47 57 67 A B VS IVSsi 56 66 76 A A VS Pin Nominal DC voltage range Supply current in sleep mode Supply current in silent mode 1.4 Bus recessive Supply current in normal VS < 14V mode Without load at VCC VS IVSrec 0.3 0.8 mA A 1.5 Bus dominant Supply current in normal VS < 14V mode VCC load current 50mA VS IVSdom 50 53 mA A 1.6 Supply current in fail-safe mode VS IVSfail 250 550 A A 1.7 VS undervoltage threshold VS VSth 3.7 5 V A 1.8 VS undervoltage threshold hysteresis VS VSth_hys V A RXD IRXD 8 mA A 0.4 V A 7 k A 2 Bus recessive VS < 14V Without load at VCC 4.4 0.2 RXD Output Pin Normal mode VLIN = 0V VRXD = 0.4V 2.1 Low-level output sink current 2.2 Low-level output voltage IRXD = 1mA RXD VRXDL 2.3 Internal resistor to VCC RXD RRXD 3 3 TXD Input/Output Pin TXD VTXDL -0.3 +0.8 V A VCC + 0.3V V A 400 k A +3 A A 8 mA A 3.1 Low-level voltage input 3.2 High-level voltage input 3.3 Pull-up resistor 3.4 High-level leakage current 3.5 Fail-safe mode Low-level output sink V = VS current at local wake-up LIN VWAKE = 0V request VTXD = 0.4V 1.3 TXD VTXDH 2 VTXD = 0V TXD RTXD 125 VTXD = VCC TXD ITXD -3 TXD ITXDwake 2 2.5 5 250 2.5 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 20 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 4. Electrical Characteristics (Continued) 5V < VS < 27V, -40C < Tcase < 125C, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins No. Parameters 4 EN Input Pin 4.1 Low-level voltage input 4.2 High-level voltage input 4.3 Pull-down resistor 4.4 Low-level input current 5 Test Conditions Pin Symbol Min. EN VENL Typ. Max. Unit Type* -0.3 +0.8 V A VCC + 0.3V V A 200 k A EN VENH 2 VEN = VCC EN REN 50 VEN = 0V EN IEN -3 +3 A A 125 NTRIG Watchdog Input Pin 5.1 Low-level voltage input NTRIG VNTRIGL -0.3 +0.8 V A 5.2 High-level voltage input NTRIG VNTRIGH 2 VCC + 0.3V V A 5.3 Pull-up resistor VNTRIG = 0V NTRIG RNTRIG 125 400 k A 5.4 High-level leakage current VNTRIG = VCC NTRIG INTRIG -3 +3 A A 6 250 Mode Input Pin 6.1 Low-level voltage input MODE VMODEL -0.3 +0.8 V A 6.2 High-level voltage input MODE VMODEH 2 VCC + 0.3V V A 6.3 High-level leakage current MODE IMODE -3 +3 A A INH VINHH VS - 0.75 VS V A INH RINH 50 A INH IINHL +3 A A VS V A 7 INH Output Pin 7.1 High-level voltage 7.2 Switch-on resistance between VS and INH 7.3 Leakage current 8 VMODE = VCC or VMODE = 0V IINH = -15mA Sleep mode VINH = 0V/27V, VS = 27V 30 -3 LIN Bus Driver: Bus Load Conditions: Load 1 (small): 1nF, 1k; Load 2 (large): 10nF, 500; Internal pull-up RRXD = 5k; CRXD = 20pF Load 3 (medium): 6.8nF, 660, characterized on samples 10.6 and 10.7 specifies the timing parameters for proper operation at 20kBit/s and 10.8 and 10.9 at 10.4kBit/s 8.1 Driver recessive output Load1/load2 voltage LIN VBUSrec 8.2 Driver dominant voltage VVS = 7V Rload = 500 LIN V_LoSUP 1.2 V A 8.3 Driver dominant voltage VVS = 18V Rload = 500 LIN V_HiSUP 2 V A 8.4 Driver dominant voltage VVS = 7.0V Rload = 1000 LIN V_LoSUP_1k 0.6 V A 8.5 Driver dominant voltage VVS = 18V Rload = 1000 LIN V_HiSUP_1k 0.8 V A 8.6 Pull-up resistor to VS The serial diode is mandatory LIN RLIN 20 60 k A 8.7 Voltage drop at the serial diodes In pull-up path with Rslave ISerDiode = 10mA LIN VSerDiode 0.4 1.0 V D 0.9 x VS 30 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 21 4. Electrical Characteristics (Continued) 5V < VS < 27V, -40C < Tcase < 125C, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins No. Parameters 8.8 LIN current limitation VBUS = VBatt_max 8.9 Input leakage current at the receiver including pull-up resistor as specified 8.10 8.11 8.12 Test Conditions Pin Symbol Min. Typ. Max. Unit Type* LIN IBUS_LIM 40 120 200 mA A Input leakage current Driver off VBUS = 0V VBatt = 12V LIN IBUS_PAS_do -1 -0.35 mA A Leakage current LIN recessive Driver off 8V < VBatt < 18V 8V < VBUS < 18V VBUS VBatt LIN Leakage current when control unit disconnected from ground. Loss of local ground must not affect communication in the residual network. GNDDevice = VS VBatt = 12V 0V < VBUS < 18V LIN Leakage current at a disconnected battery. Node has to sustain the VBatt disconnected current that can flow VSUP_Device = GND under this condition. 0V < VBUS < 18V Bus must remain operational under this condition. m IBUS_PAS_re 10 20 A A +0.5 +10 A A 0.1 2 A A 0.5 x VS 0.525 x VS V A 0.4 x VS V A V A 0.175 x VS V A c IBUS_NO_gn -10 d LIN IBUS_NO_bat LIN VBUS_CNT 9 LIN Bus Receiver 9.1 Center of receiver threshold 9.2 Receiver dominant state VEN = 5V LIN VBUSdom 9.3 Receiver recessive state VEN = 5V LIN VBUSrec 0.6 x VS 9.4 Receiver input hysteresis Vhys = Vth_rec - Vth_dom LIN VBUShys 0.028 x VS 9.5 Pre_Wake detection LIN High-level input voltage LIN VLINH VS - 2V VS + 0.3V V A 9.6 Pre_Wake detection LIN Activates the LIN receiver Low-level input voltage LIN VLINL -27 VS - 3.3V V A VBUS_CNT = (Vth_dom + Vth_rec)/2 0.475 x VS 0.1 x VS *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 22 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 4. Electrical Characteristics (Continued) 5V < VS < 27V, -40C < Tcase < 125C, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins No. Parameters 10 Internal Timers Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 10.1 Dominant time for wakeVLIN = 0V up via LIN bus LIN tbus 30 90 150 s A 10.2 Time delay for mode change from fail-safe into normal mode via EN pin VEN = 5V EN tnorm 5 15 20 s A 10.3 Time delay for mode change from normal V = 0V mode to sleep mode via EN EN pin EN tsleep 2 7 12 s A 10.4 TXD dominant time-out VTXD = 0V time TXD tdom 6 13 20 ms A 10.5 Time delay for mode change from silent V = 5V mode into normal mode EN via EN EN ts_n 5 15 40 s A Duty cycle 1 THRec(max) = 0.744 x VS THDom(max) = 0.581 x VS VS = 7.0V to 18V tBit = 50s D1 = tbus_rec(min)/(2 x tBit) LIN D1 0.396 Duty cycle 2 THRec(min) = 0.422 x VS THDom(min) = 0.284 x VS VS = 7.6V to 18V tBit = 50s D2 = tbus_rec(max)/(2 x tBit) LIN D2 Duty cycle 3 THRec(max) = 0.778 x VS THDom(max) = 0.616 x VS VS = 7.0V to 18V tBit = 96s D3 = tbus_rec(min)/(2 x tBit) LIN D3 10.9 Duty cycle 4 THRec(min) = 0.389 x VS THDom(min) = 0.251 x VS VS = 7.6V to 18V tBit = 96s D4 = tbus_rec(max)/(2 x tBit) LIN D4 10.10 Slope time falling and rising edge at LIN VS = 7.0V to 18V LIN tSLOPE_fall tSLOPE_rise 10.6 10.7 10.8 11 A 0.581 A 0.417 A 0.590 3.5 A 22.5 s A 6 s A +2 s A Receiver Electrical AC Parameters of the LIN Physical Layer LIN Receiver, RXD Load Conditions (CRXD): 20pF 11.1 Propagation delay of receiver (Figure 4-1 on page 26) 11.2 Symmetry of receiver V = 7.0V to 18V propagation delay rising S =t -t t edge minus falling edge rx_sym rx_pdr rx_pdf VS = 7.0V to 18V trx_pd = max(trx_pdr, trx_pdf) RXD trx_pd RXD trx_sym -2 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 23 4. Electrical Characteristics (Continued) 5V < VS < 27V, -40C < Tcase < 125C, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins No. Parameters Test Conditions 12 NRES Open Drain Output Pin Pin Symbol Min. Typ. Max. Unit Type* 12.1 Low-level output voltage VS 5.5V INRES = 1mA NRES VNRESL 0.14 V A 12.2 Low-level output low 10k to 5V VCC = 0V NRES VNRESLL 0.14 V A 12.3 Undervoltage reset time VS 5.5V CNRES = 20pF NRES treset 2 6 ms A 12.4 Reset debounce time for falling edge VS 5.5V CNRES = 20pF NRES tres_f 1.5 10 s A 13 Watchdog Oscillator 1.33 V A 120 k A 13.1 Voltage at WD_OSC in normal mode 13.2 Possible values of resistor 13.3 Oscillator period 13.4 IWD_OSC = -200A VVS 4V WD_OSC VWD_OSC 1.23 ROSC 34 ROSC = 34k tOSC 10.65 13.3 15.97 s A Oscillator period ROSC = 51k tOSC 15.68 19.6 23.52 s A 13.5 Oscillator period ROSC = 91k tOSC 26.83 33.5 40.24 s A 13.6 Oscillator period ROSC = 120k tOSC 34.2 42.8 51.4 s A 14 WD_OSC 1.13 4 Watchdog Timing Relative to tOSC 14.1 Watchdog lead time after reset td 7895 cycles A 14.2 Watchdog closed window t1 1053 cycles A 14.3 Watchdog open window t2 1105 cycles A 14.4 Watchdog reset time NRES 4.8 ms A 15 NRES tnres 3.2 4 KL_15 Pin 15.1 High-level input voltage Positive edge initializes a RV = 47 k wake-up KL_15 VKL_15H 4 VS + 0.3V V A 15.2 Low-level input voltage RV = 47 k KL_15 VKL_15L -1 +2 V A 15.3 KL_15 pull-down current VS < 27V VKL_15 = 27V KL_15 IKL_15 50 65 A A 15.4 Internal debounce time Without external capacitor KL_15 TdbKL_15 80 160 250 s A 15.5 KL_15 wake-up time RV = 47k, C = 100nF KL_15 TwKL_15 0.4 2 4.5 ms C WAKE VWAKEH VS - 1V VS + 0.3V V A VS - 3.3V V A A A A A 16 WAKE Pin 16.1 High-level input voltage 16.2 Low-level input voltage Initializes a wake-up signal WAKE VWAKEL -1 16.3 WAKE pull-up current VS < 27V VWAKE = 0V WAKE IWAKE -30 16.4 High-level leakage current VS = 27V VWAKE = 27V WAKE IWAKEL -5 -10 +5 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 24 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 4. Electrical Characteristics (Continued) 5V < VS < 27V, -40C < Tcase < 125C, -40C < Tj < 150C, unless otherwise specified. All values refer to GND pins No. Parameters Test Conditions 16.5 Time of low pulse for wake-up via WAKE pin VWAKE = 0V 17 17.1 Pin Symbol Min. Typ. Max. Unit Type* WAKE IWAKEL 30 70 150 s A 5.5V < VS < 18V (0mA to 50mA) VCC VCCnor 4.9 5.1 V A 6V < VS < 18V (0mA to 85mA) VCC VCCnor 4.9 5.1 V C VCC VCClow VS - VD 5.1 V A 250 mV A 600 mV A 200 mV A VCC Voltage Regulator, PVCC = VCC Output voltage VCC 17.2 Output voltage VCC at low VS 4V < VS < 5.5V 17.3 Regulator drop voltage VS > 4V IVCC = -20mA VS, VCC VD1 17.4 Regulator drop voltage VS > 4V IVCC = -50mA VS, VCC VD2 17.5 Regulator drop voltage VS > 3.3V IVCC = -15mA VS, VCC VD3 17.6 Line regulation 5.5V < VS < 18V VCC VCCline 0.1 0.2 % A 17.7 Load regulation 5mA < IVCC < 50mA VCC VCCload 0.1 0.5 % A 17.8 Power supply ripple rejection 10Hz to 100kHz CVCC = 10F VS = 14V, IVCC = -15mA VCC dB D 17.9 Output current limitation VS > 5.5V mA A F D V A mV A s A 17.10 External load capacity 0.2 < ESR < 5 at 100kHz for phase margin 60 400 50 VCC IVCClim -240 -130 VCC Cload 1.8 10 4.2 -85 ESR < 0.2 at 100kHz for phase margin 30 17.11 VCC undervoltage threshold Referred to VCC VS > 5.5V VCC VthunN 17.12 Hysteresis of undervoltage threshold Referred to VCC VS > 5.5V VCC Vhysthun 250 17.13 Ramp-up time VS > 5.5V to VCC = 5V CVCC = 2.2F Iload = -5mA at VCC VCC tVCC 130 4.8 300 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 25 Figure 4-1. Definition of Bus Timing Parameters tBit tBit tBit TXD (Input to transmitting node) tBus_dom(max) tBus_rec(min) Thresholds of THRec(max) VS (Transceiver supply of transmitting node) receiving node1 THDom(max) LIN Bus Signal Thresholds of THRec(min) receiving node2 THDom(min) tBus_dom(min) tBus_rec(max) RXD (Output of receiving node1) trx_pdf(1) trx_pdr(1) RXD (Output of receiving node2) trx_pdr(2) 26 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 trx_pdf(2) 5. Microcontroller Block 5.1 Features High performance, low power Atmel(R) AVR(R) 8-bit microcontroller Advanced RISC architecture 131 powerful instructions - most single clock cycle execution 32 x 8 general purpose working register Fully static operation Up to 16MIPS throughput at 16MHz On-chip 2-cycle multiplier Non-volatile program and data memories 8/16Kbytes of in-system self-programmable flash (Atmel ATA6612C/ATA6613C) Endurance: 75,000 write/erase cycles Optional boot code section with independent lock bits In-system programming by on-chip boot program True read-while-write operation 512bytes EEPROM Endurance: 100,000 write/erase cycles 1Kbyte internal SRAM Programming lock for software security Peripheral features Two 8-bit Timer/Counters with separate prescaler and compare mode One 16-bit Timer/Counter with separate prescaler, compare mode, and capture mode Real time counter with separate oscillator Six PWM channels 8-channel 10-bit ADC Programmable serial USART Master/slave SPI serial interface Byte-oriented 2-wire serial interface Programmable watchdog timer with separate on-chip oscillator On-chip analog comparator Interrupt and wake-up on pin change Special microcontroller features Power-on reset and programmable brown-out detection Internal calibrated oscillator External and internal interrupt sources Five sleep modes: idle, ADC noise reduction, power-save, power-down, and standby I/O Operating voltage Speed grade Low power consumption 23 programmable I/O lines 2.7V to 5.5V 0 to 8MHz at 2.7V to 5.5V, 0 to 16MHz at 4.5V to 5.5V Active mode: 4MHz, 3.0V: 1.8mA Power-down mode: 5A at 3.0V ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 27 5.2 Overview The Atmel(R) ATA6612C/ATA6613C uses a low-power CMOS 8-bit microcontroller based on the Atmel AVR(R) enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel ATA6612C/ATA6613C achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 5.2.1 Block Diagram Figure 5-1. Block Diagram GND Watchdog Timer Watchdog Oscillator Oscillator Circuits/ Clock Generation VCC Power Supervision POR/BOD and RESET debugWIRE Flash SRAM Program Logic AVR CPU EEPROM AVCC AREF DATA BUS GND 8-bit T/C 0 16-bit T/C 1 A/D Converter 8-bit T/C 2 Analog Compensation Internal Bandgap USART 0 SPI TWI PORT D (8) PORT B (8) PORT C (7) 2 6 RESET XTAL[1..2] PD[0..7] 28 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 PB[0..7] PC[0..6] ADC[6..7] The Atmel(R) AVR(R) core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Atmel ATA6612C/ATA6613C provides the following features: 8K/16K bytes of in-system programmable flash with read-while-write capabilities, 512 bytes EEPROM, 1Kbyte SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire serial interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN packages), a programmable watchdog timer with internal oscillator, and five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire serial interface, SPI port, and interrupt system to continue functioning. The power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC noise reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel's high density non-volatile memory technology. The on-chip ISP flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot program running on the Atmel AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the application flash section is updated, providing true read-while-write operation. By combining an 8-bit RISC CPU with in-system self-programmable flash on a monolithic chip, the Atmel ATA6612C/ATA6613C uses a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The Atmel ATA6612C/ATA6613C Atmel AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulator, and evaluation kits. 5.2.2 Automotive Quality Grade The Atmel ATA6612C and Atmel ATA6613C have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949 grade 1. This data sheet contains limit values extracted from the results of extensive characterization (temperature and voltage). The quality and reliability of the ATA6612C and ATA6613C have been verified during regular product qualification as per AEC-Q100. 5.2.3 Comparison Between Atmel ATA6612C/ATA6613C The Atmel ATA6612C and ATA6613C differ only in memory sizes, boot loader support, and interrupt vector sizes. Table 5-1 summarizes the different memory and interrupt vector sizes for the two devices. Table 5-1. Memory Size Summary Device Flash EEPROM RAM Interrupt Vector Size ATA6612C 8Kbytes 512Bytes 1Kbyte 1 instruction word/vector ATA6613C 16Kbytes 512Bytes 1Kbyte 2 instruction words/vector Atmel ATA6612C and ATA6613C support a real read-while-write self-programming mechanism. There is a separate boot loader section, and the SPM instruction can only execute from there. 5.2.4 Pin Descriptions 5.2.4.1 VCC Digital supply voltage. 5.2.4.2 GND Ground. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 29 5.2.4.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting oscillator amplifier. Depending on the clock selection fuse settings, PB7 can be used as input to the inverting oscillator amplifier. If the internal calibrated RC oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. The various special features of port B are elaborated in Section 5.10.3.2 "Alternate Functions of Port B" on page 84 and Section 5.6 "System Clock and Clock Options" on page 46. 5.2.4.4 Port C (PC5:0) Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5..0 output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, port C pins that are externally pulled low will source current if the pull-up resistors are activated. The port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. 5.2.4.5 PC6/RESET If the RSTDISBL fuse is unprogrammed, PC6 is used as a reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 5-3 on page 43. Shorter pulses are not guaranteed to generate a reset. The various special features of port C are elaborated in Section 5.10.3.3 "Alternate Functions of Port C" on page 87. 5.2.4.6 Port D (PD7:0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of Port D are elaborated in Section 5.10.3.4 "Alternate Functions of Port D" on page 89. 5.2.4.7 AVCC AVCC is the supply voltage pin for the A/D converter, PC3:0, and ADC7:6. I should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that PC6..4 use digital supply voltage, VCC. 5.2.4.8 AREF AREF is the analog reference pin for the A/D converter. 5.2.4.9 ADC7:6 (TQFP and QFN Package Only) In the TQFP and QFN package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. 30 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.3 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header file and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 5.4 AVR CPU Core 5.4.1 Introduction This section discusses the Atmel AVR(R) core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 5-2. Block Diagram of the Atmel AVR Architecture Data Bus 8 Bit Flash Program Memory Program Counter Status and Control 32 x 8 General Purpose Registers Instruction Decoder Control Lines Indirect Addressing Instruction Register Direct Addressing 5.4.2 ALU Interrupt Unit SPI Unit Watchdog Timer Analog Comparator I/O Module 1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 31 In order to maximize performance and parallelism, the Atmel AVR(R) uses a harvard architecture - with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system reprogrammable flash memory. The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle arithmetic logic unit (ALU) operation. In a typical ALU operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing - enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program flash memory space is divided in two sections, the boot program section and the application program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that writes into the application flash memory section must reside in the boot program section. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The stack pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5F. In addition, the Atmel(R) ATA6612C/ATA6613C has extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5.4.3 ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the "instruction set" section for a detailed description. 32 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.4.4 Status Register The status register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR(R) status register - SREG - is defined as: Bit 7 6 5 4 3 2 1 0 I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG * Bit 7 - I: Global Interrupt Enable The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. * Bit 6 - T: Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. * Bit 5 - H: Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. Half carry is useful in BCD arithmetic. See the "Instruction Set Description" for detailed information. * Bit 4 - S: Sign Bit, S = N V The S-bit is always an exclusive or between the negative flag N and the two's complement overflow flag V. See the "Instruction Set Description" for detailed information. * Bit 3 - V: Two's Complement Overflow Flag The two's complement overflow flag V supports two's complement arithmetics. See the "Instruction Set Description" for detailed information. * Bit 2 - N: Negative Flag The negative flag N indicates a negative result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 1 - Z: Zero Flag The zero flag Z indicates a zero result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 0 - C: Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 33 5.4.5 General Purpose Register File The register file is optimized for the AVR(R) enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the register file: One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input Two 8-bit output operands and one 16-bit result input One 16-bit output operand and one 16-bit result input Figure 5-3 shows the structure of the 32 general purpose working registers in the CPU. Figure 5-3. AVR CPU General Purpose Working Registers 7 0 Address R0 0x00 R1 0x01 R2 0x02 ... General Purpose Working Registers R13 0x0D R14 0x0E R15 0x0F R16 0x10 R17 0x11 ... R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte Most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 5-3, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 34 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.4.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5-4. Figure 5-4. The X-, Y-, and Z-registers 15 XH XL 0 7 0 7 0 X-register R27 (0x1B) R26 (0x1A) 15 YH YL 0 7 0 7 0 Y-register R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 7 0 7 0 Z-register R31 (0x1F) R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 5.4.6 Stack Pointer The stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The stack pointer register always points to the top of the stack. Note that the stack is implemented as growing from higher memory locations to lower memory locations. This implies that a stack PUSH command decreases the stack pointer. The stack pointer points to the data SRAM Stack area where the subroutine and interrupt stacks are located. This stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above 0x0100, preferably RAMEND. The stack pointer is decremented by one when data is pushed onto the stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the stack with subroutine call or interrupt. The stack pointer is incremented by one when data is popped from the stack with the POP instruction, and it is incremented by two when data is popped from the stack with return from subroutine RET or return from interrupt RETI. The AVR(R) stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH register will not be present. Bit Read/Write 15 14 13 12 11 10 9 8 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 35 5.4.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR(R) CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 5-5 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 5-5. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 5-6 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 5-6. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 5.4.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. Depending on the program counter value, interrupts may be automatically disabled when boot lock bits BLB02 or BLB12 are programmed. This feature improves software security. See Section 5.24 "Memory Programming" on page 253 for details. The lowest addresses in the program memory space are by default defined as the reset and Interrupt vectors. The complete list of vectors is shown in Section 5.9 "Interrupts" on page 70. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the external interrupt request 0. The interrupt vectors can be moved to the start of the boot flash section by setting the IVSEL bit in the MCU control register (MCUCR). Refer to Section 5.9 "Interrupts" on page 70 for more information. The reset vector can also be moved to the start of the boot flash section by programming the BOOTRST fuse (see Section 5.23 "Boot Loader Support - Read-While-Write Self-Programming, Atmel ATA6612C and ATA6613C" on page 240). When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a return from interrupt instruction - RETI - is executed. 36 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR(R) exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */ When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 5.4.8.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the program counter is pushed onto the stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the program counter (two bytes) is popped back from the stack, the stack pointer is incremented by two, and the I-bit in SREG is set. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 37 5.5 AVR Atmel ATA6612C/ATA6613C Memories This section describes the different memories in the Atmel(R) ATA6612C/ATA6613C. The AVR(R) architecture has two main memory spaces, the data memory and the program memory space. In addition, the Atmel ATA6612C/ATA6613C features an EEPROM memory for data storage. All three memory spaces are linear and regular. 5.5.1 In-System Reprogrammable Flash Program Memory The Atmel ATA6612C/ATA6613C contains 8/16Kbytes on-chip in-system reprogrammable flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the flash is organized as 2/4/8K x 16. For software security, the flash program memory space is divided into two sections, boot loader section and application program section in Atmel ATA6612C and ATA6613C. See SELFPRGEN description in section Section 5.23.5.1 "Store Program Memory Control and Status Register - SPMCSR" on page 244 for more details. The flash memory has an endurance of at least 75,000 write/erase cycles. The Atmel ATA6612C/ATA6613C program counter (PC) is 11/12/13 bits wide, thus addressing the 2/4/8K program memory locations. The operation of boot program section and associated boot lock bits for software protection are described in detail in Section 5.23 "Boot Loader Support - Read-While-Write Self-Programming, Atmel ATA6612C and ATA6613C" on page 240. Section 5.24 "Memory Programming" on page 253 contains a detailed description on flash programming in SPI- or parallel programming mode. Constant tables can be allocated within the entire program memory address space (see the LPM - load program memory instruction description). Timing diagrams for instruction fetch and execution are presented in Section 5.4.7 "Instruction Execution Timing" on page 36. Figure 5-7. Program Memory Map, Atmel ATA6612C/ATA6613C Program Memory 0x0000 Application Flash Section 0x7FF 38 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Figure 5-8. Program Memory Map, Atmel ATA6612C/ATA6613C Program Memory 0x0000 Application Flash Section Boot Flash Section 0x0FFF/0x1FFF 5.5.2 SRAM Data Memory Figure 5-9 shows how the Atmel(R) ATA6612C/ATA6613C SRAM memory is organized. The Atmel ATA6612C/ATA6613C is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The lower 768/1280/1280 data memory locations address both the register file, the I/O memory, extended I/O memory, and the internal data SRAM. The first 32 locations address the register file, the next 64 location the standard I/O memory, then 160 locations of extended I/O memory, and the next 512/1024/1024 locations address the internal data SRAM. The five different addressing modes for the data memory cover: Direct, indirect with displacement, indirect, indirect with pre-decrement, and indirect with post-increment. In the register file, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space. The indirect with displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O registers, 160 extended I/O registers, and the 512/1024/1024 bytes of internal data SRAM in the Atmel ATA6612C/ATA6613C are all accessible through all these addressing modes. The register file is described in Section 5.4.5 "General Purpose Register File" on page 34. Figure 5-9. Data Memory Map Data Memory 32 Registers 0x0000 - 0x001F 64 I/O Registers 0x0020 - 0x005F 160 Ext I/O Registers 0x0060 - 0x00FF 0x0100 Internal SRAM (512/1024/1024 x 8) 0x02FF/0x04FF/0x04FF ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 39 5.5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 5-10. Figure 5-10. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Data Write WR Data Read RD Memory Access Instruction 5.5.3 Next Instruction EEPROM Data Memory The Atmel(R) ATA6612C/ATA6613C contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM address registers, the EEPROM data register, and the EEPROM control register. The section Section 5.24 "Memory Programming" on page 253 contains a detailed description on EEPROM programming in SPI or parallel programming mode. 5.5.3.1 EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 5-3 on page 43. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See Section 5.5.3.5 "Preventing EEPROM Corruption" on page 44 for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM control register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. 40 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.5.3.2 The EEPROM Address Register - EEARH and EEARL Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 - - - - - - - EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 X X X X X X X X X * Bits 15..9 - Res: Reserved Bits These bits are reserved bits in the Atmel(R) ATA6612C/ATA6613C and will always read as zero. * Bits 8..0 - EEAR8..0: EEPROM Address The EEPROM address registers - EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 255/511/511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 5.5.3.3 The EEPROM Data Register - EEDR Bit 7 6 5 4 3 2 1 MSB 0 LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EEDR * Bits 7..0 - EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 5.5.3.4 The EEPROM Control Register - EECR Bit 7 6 5 4 3 2 1 0 Read/Write - - EEPM1 EEPM0 EERIE EEMPE EEPE EERE R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0 EECR * Bits 7..6 - Res: Reserved Bits These bits are reserved bits in the Atmel ATA6612C/ATA6613C and will always read as zero * Bits 5, 4 - EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the erase and write operations in two different operations. The programming times for the different modes are shown in Table 5-2 on page 42. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 41 Table 5-2. EEPROM Mode Bits EEPM1 EEPM0 Programming Time Operation 0 0 3.4ms Erase and write in one operation (atomic operation) 0 1 1.8ms Erase only 1 0 1.8ms Write only 1 1 - Reserved for future use * Bit 3 - EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM ready interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM ready interrupt generates a constant interrupt when EEPE is cleared. * Bit 2 - EEMPE: EEPROM Master Write Enable The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure. * Bit 1 - EEPE: EEPROM Write Enable The EEPROM write enable signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEPE becomes zero. 2. Wait until SELFPRGEN in SPMCSR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR. 6. Within four clock cycles after setting EEMPE, write a logical one to EEPE. The EEPROM can not be programmed during a CPU write to the flash memory. The software must check that the flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the flash. If the flash is never being updated by the CPU, step 2 can be omitted. See Section 5.23 "Boot Loader Support - Read-While-Write Self-Programming, Atmel ATA6612C and ATA6613C" on page 240 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM master write enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during all the steps to avoid these problems. When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. * Bit 0 - EERE: EEPROM Read Enable The EEPROM read enable signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. 42 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 5-3 lists the typical programming time for EEPROM access from the CPU. Table 5-3. EEPROM Programming Time Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time EEPROM write (from CPU) 26,368 3.3ms The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no flash boot loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<<EEPE)) ; /* Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 43 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from Data Register in r16,EEDR ret C Code Example unsigned char EEPROM_read(unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1<<EEPE)) ; /* Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; } 5.5.3.5 Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR(R) RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal brown-out detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 44 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.5.4 I/O Memory The I/O space definition of the Atmel(R) ATA6612C/ATA6613C is shown in Section 6.4 "Register Summary" on page 291. All Atmel ATA6612C/ATA6613C I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATA6612C/ATA6613C is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR(R)s, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. The I/O and peripherals control registers are explained in later sections. 5.5.4.1 General Purpose I/O Registers The Atmel ATA6612C/ATA6613C contains three general purpose I/O registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. General purpose I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions. 5.5.4.2 General Purpose I/O Register 2 - GPIOR2 Bit 7 6 5 4 3 2 1 MSB 0 LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 GPIOR2 5.5.4.3 General Purpose I/O Register 1 - GPIOR1 Bit 7 6 5 4 MSB 0 LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 GPIOR1 5.5.4.4 General Purpose I/O Register 0 - GPIOR0 Bit 7 6 5 4 MSB 0 LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 GPIOR0 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 45 5.6 System Clock and Clock Options 5.6.1 Clock Systems and their Distribution Figure 5-11 presents the principal clock systems in the AVR(R) and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in Section 5.7 "Power Management and Sleep Modes" on page 55. The clock systems are detailed below. Figure 5-11. Clock Distribution Asynchronous Timer/Counter General I/O Modules ADC CPU Core RAM Flash and EEPROM clkADC clkI/O AVR Clock Control Unit clkASY clkFLASH System Clock Prescaler Source clock External Clock Reset Logic Watchdog Timer Watchdog clock Watchdog Oscillator Clock Multiplexer Timer/Counter Oscillator clkCPU Crystal Oscillator Low Frequency Crystal Oscillator Calibrated RC Oscillator 5.6.1.1 CPU Clock - clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the general purpose register file, the status register and the data memory holding the stack pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. 5.6.1.2 I/O Clock - clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that start condition detection in the USI module is carried out asynchronously when clkI/O is halted, TWI address recognition in all sleep modes. 5.6.1.3 Flash Clock - clkFLASH The flash clock controls operation of the flash interface. The flash clock is usually active simultaneously with the CPU clock. 5.6.1.4 Asynchronous Timer Clock - clkASY The asynchronous timer clock allows the asynchronous Timer/Counter to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 46 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.6.1.5 ADC Clock - clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 5.6.2 Clock Sources The device has the following clock source options, selectable by flash fuse bits as shown below. The clock from the selected source is input to the AVR(R) clock generator, and routed to the appropriate modules. Table 5-4. Note: 1. Device Clocking Options Select(1) Device Clocking Option CKSEL3..0 Low power crystal oscillator 1111 - 1000 Full swing crystal oscillator 0111 - 0110 Low frequency crystal oscillator 0101 - 0100 Internal 128kHz RC oscillator 0011 Calibrated internal RC oscillator 0010 External clock 0000 Reserved For all fuses "1" means unprogrammed while "0" means programmed. 0001 5.6.2.1 Default Clock Source The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 programmed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that all users can make their desired clock source setting using any available programming interface. 5.6.2.2 Clock Startup Sequence Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating cycles before it can be considered stable. To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after the device reset is released by all other reset sources. The Section 5.8 "System Control and Reset" on page 60 describes the start conditions for the internal reset. The delay (tTOUT) is timed from the watchdog oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in Table 5-5. The frequency of the watchdog oscillator is voltage dependent as shown in Section 6.4 "Register Summary" on page 291. Table 5-5. Number of Watchdog Oscillator Cycles Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles 0ms 0ms 0 4.1ms 4.3ms 4K (4,096) 65ms 69ms 8K (8,192) Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum VCC. The delay will not monitor the actual voltage and it will be required to select a delay longer than the VCC rise time. If this is not possible, an internal or external brown-out detection circuit should be used. A BOD circuit will ensure sufficient VCC before it releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without utilizing a brown-out detection circuit is not recommended. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 47 The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal. The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When starting up from power-save or power-down mode, VCC is assumed to be at a sufficient level and only the start-up time is included. 5.6.3 Low Power Crystal Oscillator Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 5-12. Either a quartz crystal or a ceramic resonator may be used. This crystal oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. In these cases, refer to the Section 5.6.4 "Full Swing Crystal Oscillator" on page 49. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 5-6. For ceramic resonators, the capacitor values given by the manufacturer should be used. Figure 5-12. Crystal Oscillator Connections C2 XTAL2 C1 XTAL1 GND The low power oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 5-6. Table 5-6. Notes: 48 Low Power Crystal Oscillator Operating Modes(3) Frequency Range(1) (MHz) CKSEL3..1 Recommended Range for Capacitors C1 and C2 (pF) 0.4 - 0.9 100(2) - 0.9 - 3.0 101 12 - 22 3.0 - 8.0 110 12 - 22 1. 8.0 - 16.0 111 The frequency ranges are preliminary values. Actual values are TBD. 2. This option should not be used with crystals, only with ceramic resonators. 3. If 8MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 12 - 22 The CKSEL0 fuse together with the SUT1..0 fuses select the start-up times as shown in Table 5-7. Table 5-7. Start-up Times for the Low Power Crystal Oscillator Clock Selection Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1..0 Ceramic resonator, fast rising power 258CK 14CK + 4.1ms(1) 0 00 Ceramic resonator, slowly rising power 258CK 14CK + 65ms(1) 0 01 Ceramic resonator, BOD enabled 1KCK 14CK(2) 0 10 Ceramic resonator, fast rising power 1KCK 14CK + 4.1ms(2) 0 11 Ceramic resonator, slowly rising power 1KCK 14CK + 65ms(2) 1 00 Crystal oscillator, BOD enabled 16KCK 14CK 1 01 Crystal oscillator, fast rising power 16KCK 14CK + 4.1ms 1 10 Oscillator Source/ Power Conditions Crystal oscillator, slowly rising 16KCK 14CK + 65ms 1 11 power Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. 5.6.4 These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. Full Swing Crystal Oscillator Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 5-12 on page 48. Either a quartz crystal or a ceramic resonator may be used. This crystal oscillator is a full swing oscillator, with rail-to-rail swing on the XTAL2 output. This is useful for driving other clock inputs and in noisy environments. The current consumption is higher than the Section 5.6.3 "Low Power Crystal Oscillator" on page 48. Note that the full swing crystal oscillator will only operate for VCC = 2.7 to 5.5V. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 5-9 on page 50. For ceramic resonators, the capacitor values given by the manufacturer should be used. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 5-8. Table 5-8. Full Swing Crystal Oscillator Operating Modes(2) Frequency Range(1) (MHz) Notes: 1. 2. CKSEL3..1 Recommended Range for Capacitors C1 and C2 (pF) 0.4 - 20 011 The frequency ranges are preliminary values. Actual values are TBD. 12 - 22 If 8MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 49 Figure 5-13. Crystal Oscillator Connections C2 XTAL2 C1 XTAL1 GND Table 5-9. Start-up Times for the Full Swing Crystal Oscillator Clock Selection Oscillator Source/ Power Conditions Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1..0 Ceramic resonator, fast rising power 258CK 14CK + 4.1ms(1) 0 00 Ceramic resonator, slowly rising power 258CK 14CK + 65ms(1) 0 01 Ceramic resonator, BOD enabled 1KCK 14CK(2) 0 10 Ceramic resonator, fast rising power 1KCK 14CK + 4.1ms(2) 0 11 Ceramic resonator, slowly rising power 1KCK 14CK + 65ms(2) 1 00 Crystal oscillator, BOD enabled 16KCK 14CK 1 01 Crystal oscillator, fast rising power 16KCK 14CK + 4.1ms 1 10 Crystal oscillator, slowly rising 16KCK 14CK + 65ms 1 11 power Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. 50 These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.6.5 Low Frequency Crystal Oscillator The device can utilize a 32.768kHz watch crystal as clock source by a dedicated low frequency crystal oscillator. The crystal should be connected as shown in Figure 5-12. When this oscillator is selected, start-up times are determined by the SUT fuses and CKSEL0 as shown in Table 5-10. Table 5-10. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection Power Conditions Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) 5.6.6 SUT1..0 BOD enabled 1kCK 0 00 1kCK 14CK + 4.1ms(1) 0 01 1kCK (1) 0 10 0 11 14CK + 65ms Reserved Note: CKSEL0 Fast rising power Slowly rising power 14CK (1) BOD enabled 32kCK 14CK 1 00 Fast rising power 32kCK 14CK + 4.1ms 1 01 Slowly rising power 32kCK 14CK + 65ms 1 10 1. Reserved 1 11 These options should only be used if frequency stability at start-up is not important for the application. Calibrated Internal RC Oscillator The calibrated internal RC oscillator by default provides a 8.0MHz clock. The frequency is nominal value at 5V and 25C. The device is shipped with the CKDIV8 fuse programmed. See Section 5.6.11 "System Clock Prescaler" on page 54 for more details. This clock may be selected as the system clock by programming the CKSEL fuses as shown in Table 5-11. If selected, it will operate with no external components. During reset, hardware loads the calibration byte into the OSCCAL register and thereby automatically calibrates the RC oscillator. At 5V and 25C, this calibration gives a frequency of 8MHz 1%. The tolerance of the internal RC oscillator remains better than 10% within the whole automotive temperature and voltage ranges (4.5V to 5.5V, -40C to +125C). The oscillator can be calibrated to any frequency in the range 7.3 - 8.1MHz within 1% accuracy, by changing the OSCCAL register. When this oscillator is used as the chip clock, the watchdog oscillator will still be used for the watchdog timer and for the reset time-out. For more information on the pre-programmed calibration value (see Section 5.24.4 "Calibration Byte" on page 256). Table 5-11. Internal Calibrated RC Oscillator Operating Modes(1)(3) Notes: Frequency Range(2) (MHz) CKSEL3..0 7.3 - 8.1 The device is shipped with this option selected. 0010 1. 2. The frequency ranges are preliminary values. Actual values are TBD. 3. If 8MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 fuse can be programmed in order to divide the internal frequency by 8. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 51 When this oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 5-12. Table 5-12. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection Power Conditions Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) SUT1..0 BOD enabled 6CK 14CK(1) 00 Fast rising power 6CK 14CK + 4.1ms Slowly rising power Note: (2) 6CK 14CK + 65ms 1. Reserved If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4.1ms to ensure programming mode can be entered. 2. The device is shipped with this option selected. 01 10 11 5.6.6.1 Oscillator Calibration Register - OSCCAL Bit Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value * Bits 7..0 - CAL7..0: Oscillator Calibration Value The oscillator calibration register is used to trim the calibrated internal RC oscillator to remove process variations from the oscillator frequency. The factory-calibrated value is automatically written to this register during chip reset, giving an oscillator frequency of 8.0MHz at 25C. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to any frequency in the range 7.3 to 8.1MHz within 1% accuracy. Calibration outside that range is not guaranteed. Note that this oscillator is used to time EEPROM and flash write accesses, and these write times will be affected accordingly. If the EEPROM or flash are written, do not calibrate to more than 8.8MHz. Otherwise, the EEPROM or flash write may fail. The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80. The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2% in the frequency range 7.3 - 8.1MHz. 5.6.7 128kHz Internal Oscillator The 128kHz internal oscillator is a low power oscillator providing a clock of 128kHz. The frequency is nominal at 3V and 25C. This clock may be select as the system clock by programming the CKSEL fuses to "11" as shown in Table 5-13. Table 5-13. 128kHz Internal Oscillator Operating Modes Nominal Frequency Note: 52 1. 128kHz The frequency is preliminary value. Actual value is TBD. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 CKSEL3..0 0011 When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 5-14. Table 5-14. Start-up Times for the 128kHz Internal Oscillator Note: 5.6.8 Power Conditions Start-up Time from Power-down and Power-save Additional Delay from Reset SUT1..0 BOD enabled 6CK 14CK(1) 00 Fast rising power 6CK 14CK + 4ms 01 Slowly rising power 6CK 14CK + 64ms 10 1. Reserved If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4.1ms to ensure programming mode can be entered. 11 External Clock The device can utilize a external clock source as shown in Figure 5-14. To run the device on an external clock, the CKSEL fuses must be programmed as shown in Table 5-15. Table 5-15. Full Swing Crystal Oscillator Operating Modes(2) Frequency Range(1) (MHz) Notes: 1. 2. Recommended Range for Capacitors C1 and C2 (pF) CKSEL3..0 0 - 100 0000 The frequency ranges are preliminary values. Actual values are TBD. 12 - 22 If 8MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device. Figure 5-14. External Clock Drive Configuration NC XTAL2 EXTERNAL CLOCK SIGNAL XTAL1 GND When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 5-16. Table 5-16. Start-up Times for the External Clock Selection Power Conditions Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) SUT1..0 BOD enabled 6CK 14CK 00 Fast rising power 6CK 14CK + 4.1ms 01 Slowly rising power 6CK 14CK + 65ms 10 Reserved 11 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 53 When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in reset during the changes. Note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to Section 5.6.11 "System Clock Prescaler" on page 54 for details. 5.6.9 Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC oscillator, can be selected when the clock is output on CLKO. If the system clock prescaler is used, it is the divided system clock that is output. 5.6.10 Timer/Counter Oscillator The device can operate its Timer/Counter2 from an external 32.768kHz watch crystal or a external clock source. The Timer/Counter oscillator pins (TOSC1 and TOSC2) are shared with XTAL1 and XTAL2. This means that the Timer/Counter oscillator can only be used when an internal RC oscillator is selected as system clock source. See Figure 5-12 on page 48 for crystal connection. Applying an external clock source to TOSC1 requires EXTCLK in the ASSR register written to logic one. See Section 5.15.9 "Asynchronous Operation of the Timer/Counter" on page 153 for further description on selecting external clock as input instead of a 32kHz crystal. 5.6.11 System Clock Prescaler The Atmel(R) ATA6612C/ATA6613C has a system clock prescaler, and the system clock can be divided by setting the Section 5.6.11.1 "Clock Prescale Register - CLKPR" on page 54. This feature can be used to decrease the system clock frequency and the power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 5-20 on page 62. When switching between prescaler settings, the system clock prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 x T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the clock prescaler change enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 5.6.11.1Clock Prescale Register - CLKPR Bit 7 6 5 4 CLKPCE - - - Read/Write R/W R R R Initial Value 0 0 0 0 3 2 1 0 CLKPS3 CLKPS2 CLKPS1 CLKPS0 R/W R/W R/W CLKPR R/W See Bit Description * Bit 7 - CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. 54 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 * Bits 3..0 - CLKPS3..0: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in Table 5-17. The CKDIV8 fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to "0000". If CKDIV8 is programmed, CLKPS bits are reset to "0011", giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 fuse setting. The application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 fuse programmed. Table 5-17. Clock Prescaler Select 5.7 CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 0 0 1 1 8 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 Reserved 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR(R) provides various sleep modes allowing the user to tailor the power consumption to the application's requirements. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR register select which sleep mode (idle, ADC noise reduction, power-down, power-save, or standby) will be activated by the SLEEP instruction. See Table 5-18 on page 56 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the reset vector. Figure 5-11 on page 46 presents the different clock systems in the Atmel(R) ATA6612C/ATA6613C, and their distribution. The figure is helpful in selecting an appropriate sleep mode. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 55 5.7.1 Sleep Mode Control Register - SMCR The sleep mode control register contains control bits for power management. Bit 7 6 5 4 3 2 1 - - Read/Write R R Initial Value 0 0 0 0 - - SM2 SM1 SM0 SE R R R/W R/W R/W R/W 0 0 0 0 0 SMCR * Bits 7..4 Res: Reserved Bits These bits are unused bits in the Atmel(R) ATA6612C/ATA6613C, and will always read as zero. * Bits 3..1 - SM2..0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 5-18. Table 5-18. Sleep Mode Select Note: SM2 SM1 SM0 0 0 0 Idle 0 0 1 ADC noise reduction 0 1 0 Power-down 0 1 1 Power-save 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Standby(1) 1 1. Sleep Mode 1 1 Reserved Standby mode is only recommended for use with external crystals or resonators. * Bit 0 - SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer's purpose, it is recommended to write the sleep enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 5.7.2 Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter idle mode, stopping the CPU but allowing the SPI, USART, analog comparator, ADC, 2-wire serial interface, Timer/Counters, watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the timer overflow and USART transmit complete interrupts. If wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the ACD bit in the analog comparator control and status register - ACSR. This will reduce power consumption in idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 5.7.3 ADC Noise Reduction Mode When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC noise reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-wire serial interface address watch, Timer/Counter2, and the watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the ADC conversion complete interrupt, only an external reset, a watchdog system reset, a watchdog interrupt, a brown-out reset, a 2-wire serial interface address match, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or INT1 or a pin change interrupt can wake up the MCU from ADC noise reduction mode. 56 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.7.4 Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter power-down mode. In this mode, the external oscillator is stopped, while the external interrupts, the 2-wire serial interface address watch, and the watchdog continue operating (if enabled). Only an external reset, a watchdog system reset, a watchdog interrupt, a brown-out reset, a 2-wire serial interface address match, an external level interrupt on INT0 or INT1, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. Note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the MCU. Refer to Section 5.11 "External Interrupts" on page 92 for details. When waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL fuses that define the reset time-out period, as described in Section 5.6.2 "Clock Sources" on page 47. 5.7.5 Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter power-save mode. This mode is identical to power-down, with one exception. If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either timer overflow or output compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the global interrupt enable bit in SREG is set. If Timer/Counter2 is not running, power-down mode is recommended instead of power-save mode. The Timer/Counter2 can be clocked both synchronously and asynchronously in power-save mode. If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter oscillator is stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in power-save, this clock is only available for Timer/Counter2. Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter standby mode. This mode is identical to power-down with the exception that the oscillator is kept running. From standby mode, the device wakes up in six clock cycles. Table 5-19. Active Clock Domains and Wake-up Sources in the Different Sleep Modes TWI Address Match SPM/EEPROM Ready ADC WDT Other I/O X(2) ADC noise Reduction X X X X X X X X X X X(2) X(3) X X X X X X(3) X (3) X Power-down Power-save Standby(1) Notes: 1. X X X X X X X(3) X Only recommended with external crystal or resonator selected as clock source. X 2. If timer/Ccunter2 is running in asynchronous mode. 3. For INT1 and INT0, only level interrupt. X Timer2 INT1, INT0 and Pin Change X Main Clock Source Enabled X clkASY X Sleep Mode Idle Wake-up Sources Timer Oscillator Enabled Oscillators X clkADC clkIO clkFLASH Active Clock Domains clkCPU 5.7.6 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 57 5.7.7 Power Reduction Register The power reduction register, PRR, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. See Section 6.3.1.1 "Power-down Supply Current" on page 281 for examples. In all other sleep modes, the clock is already stopped. 5.7.7.1 Power Reduction Register - PRR Bit 7 6 5 4 3 2 1 0 PRTWI PRTIM2 PRTIM0 - PRTIM1 PRSPI PRUSART0 PRADC Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PRR * Bit 7 - PRTWI: Power Reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation. * Bit 6 - PRTIM2: Power Reduction Timer/Counter2 Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2 is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown. * Bit 5 - PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. * Bit 4 - Res: Reserved bit This bit is reserved in Atmel(R) ATA6612C/ATA6613C and will always read as zero. * Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. * Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface If using debugWIRE on-chip debug system, this bit should not be written to one. Writing a logic one to this bit shuts down the serial peripheral interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re-initialized to ensure proper operation. * Bit 1 - PRUSART0: Power Reduction USART0 Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking up the USART again, the USART should be re-initialized to ensure proper operation. * Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. 58 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.7.8 Minimizing Power Consumption There are several possibilities to consider when trying to minimize the power consumption in an AVR(R) controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device's functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 5.7.8.1 Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to Section 5.21 "Analog-to-Digital Converter" on page 224 for details on ADC operation. 5.7.8.2 Analog Comparator When entering Idle mode, the analog comparator should be disabled if not used. When entering ADC noise reduction mode, the analog comparator should be disabled. In other sleep modes, the analog comparator is automatically disabled. However, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. Otherwise, the internal voltage reference will be enabled, independent of sleep mode. Refer to Section 5.20 "Analog Comparator" on page 221 for details on how to configure the analog comparator. 5.7.8.3 Brown-out Detector If the brown-out detector is not needed by the application, this module should be turned off. If the brown-out detector is enabled by the BODLEVEL fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Section 5.8.5 "Brown-out Detection" on page 63 for details on how to configure the brown-out detector. 5.7.8.4 Internal Voltage Reference The internal voltage reference will be enabled when needed by the brown-out detection, the analog comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to Section 5.8.8 "Internal Voltage Reference" on page 65 for details on the start-up time. 5.7.8.5 Watchdog Timer If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Section 5.8.9 "Watchdog Timer" on page 66 for details on how to configure the watchdog timer. 5.7.8.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section Section 5.10.2.5 "Digital Input Enable and Sleep Modes" on page 81 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power. For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the digital input disable registers (DIDR1 and DIDR0). Refer to Section 5.20.3.1 "Digital Input Disable Register 1 - DIDR1" on page 223 and Section 5.21.6.5 "Digital Input Disable Register 0 - DIDR0" on page 238 for details. 5.7.8.7 On-chip Debug System If the on-chip debug system is enabled by the DWEN fuse and the chip enters sleep mode, the main clock source is enabled and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 59 5.8 System Control and Reset 5.8.1 Resetting the AVR During reset, all I/O registers are set to their initial values, and the program starts execution from the reset vector. For the Atmel(R) ATA6613C, the instruction placed at the reset vector must be a JMP - absolute jump - instruction to the reset handling routine. For the Atmel ATA6612C, the instruction placed at the reset vector must be an RJMP - relative jump - instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. This is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa (Atmel ATA6612C/ATA6613C only). The circuit diagram in Figure 5-15 on page 61 shows the reset logic. Table 5-20 on page 62 defines the electrical parameters of the reset circuitry. The I/O ports of the AVR(R) are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL fuses. The different selections for the delay period are presented in Section 5.6.2 "Clock Sources" on page 47. 5.8.2 Reset Sources The Atmel ATA6612C/ATA6613C has four sources of reset: Power-on reset: The MCU is reset when the supply voltage is below the power-on reset threshold (VPOT). 60 External reset: The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. Watchdog system reset: The MCU is reset when the watchdog timer period expires and the watchdog system reset mode is enabled. Brown-out reset: The MCU is reset when the supply voltage VCC is below the brown-out reset threshold (VBOT) and the brown-out detector is enabled. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Figure 5-15. Reset Logic DATA BUS WDRF BORF EXTRF PORF MCU Status Register (MCUSR) Power-on Reset Circuit VCC Pull-up Resistor Reset Circuit S RESET SPIKE FILTER COUNTER RESET R Watchdog Timer RSTDISBL Watchdog Oscillator Clock Generator Q INTERNAL RESET Brown-out Reset Circuit BODLEVEL [2..0] CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 5.8.3 Power-on Reset A power-on reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in Table 5-20 on page 62. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage. A power-on reset (POR) circuit ensures that the device is reset from power-on. Reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay, when VCC decreases below the detection level. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 61 Figure 5-16. MCU Start-up, RESET Tied to VCC VCCRR VCC VPORMAX VPORMIN RESET VRST tTOUT TIME-OUT INTERNAL RESET Figure 5-17. MCU Start-up, RESET Extended Externally V CC VPOR RESET VRST tTOUT TIME-OUT INTERNAL RESET Table 5-20. Power-on Reset Characteristics Parameter Symbol Power-on reset threshold voltage (rising) (1) Power-on reset threshold voltage (falling) Min VPOT Typ Max Unit 1.0 1.4 V 0.9 1.3 V 0.4 V VCC Max. start voltage to ensure internal power-on reset signal VPORMAX VCC Min. start voltage to ensure internal power-on reset signal VPORMIN -0.1 V VCCRR 0.01 V/ms VRST 0.1 VCC VCC rise rate to ensure power-on reset RESET pin threshold voltage Minimum pulse width on RESET pin tRST Note: 1. Before rising, the supply has to be between VPORMIN and VPORMAX to ensure a reset. 62 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 0.9 VCC V 5.8.4 External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 5-20 on page 62) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the reset threshold voltage - VRST - on its positive edge, the delay counter starts the MCU after the Time-out period - tTOUT - has expired. The external reset can be disabled by the RSTDISBL fuse, see Table 5-118 on page 255. Figure 5-18. External Reset During Operation VCC RESET V RST tTOUT TIME-OUT INTERNAL RESET 5.8.5 Brown-out Detection Atmel(R) ATA6612C/ATA6613C has an on-chip brown-out detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL fuses. The trigger level has a hysteresis to ensure spike free brown-out detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. Table 5-21. BODLEVEL Fuse Coding(1) BODLEVEL 2..0 Fuses 111 Min VBOT Typ VBOT Max VBOT Units BOD disabled 110 1.8 101 2.7 100 4.3 V 011 010 001 Note: 1. Reserved 000 VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a brown-out reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110 and BODLEVEL = 101 for Atmel ATA6612CV/ATA6613CV, and BODLEVEL = 101 and BODLEVEL = 101 for ATA6612C/ATA6613C. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 63 Table 5-22. Brown-out Characteristics Symbol Parameter Min VHYST Brown-out Detector Hysteresis tBOD Min Pulse Width on Brown-out Reset Typ 50 Max Units mV ns When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT- in Figure 5-19), the brown-out reset is immediately activated. When VCC increases above the trigger level (VBOT+ in Figure 5-19), the delay counter starts the MCU after the time-out period tTOUT has expired. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD given in Table 5-20 on page 62. Figure 5-19. Brown-out Reset During Operation V CC VBOT- VBOT+ RESET tTOUT TIME-OUT INTERNAL RESET 5.8.6 Watchdog System Reset When the watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the time-out period tTOUT. Refer to Section 5.8.9 "Watchdog Timer" on page 66 for details on operation of the watchdog timer. Figure 5-20. Watchdog System Reset During Operation V CC RESET 1 CK Cycle WD TIME-OUT RESET TIME-OUT INTERNAL RESET 64 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 tTOUT 5.8.7 MCU Status Register - MCUSR The MCU status register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 - - Read/Write R R - - WDRF BORF EXTRF PORF R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description * Bit 7..4: Res: Reserved Bits These bits are unused bits in the Atmel(R) ATA6612C/ATA6613C, and will always read as zero. * Bit 3 - WDRF: Watchdog System Reset Flag This bit is set if a watchdog system reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. * Bit 2 - BORF: Brown-out Reset Flag This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. * Bit 1 - EXTRF: External Reset Flag This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. * Bit 0 - PORF: Power-on Reset Flag This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. 5.8.8 Internal Voltage Reference Atmel ATA6612C/ATA6613C features an internal band gap reference. This reference is used for brown-out detection, and it can be used as an input to the analog comparator or the ADC. 5.8.8.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 5-23 on page 65. To save power, the reference is not always turned on. The reference is on during the following situations: 1. When the BOD is enabled (by programming the BODLEVEL [2..0] fuses). 2. When the bandgap reference is connected to the analog comparator (by setting the ACBG bit in ACSR). 3. When the ADC is enabled. Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the analog comparator or ADC is used. To reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. Table 5-23. Internal Voltage Reference Characteristics(1) Parameter Condition Symbol Min Typ Max Bandgap reference voltage TBD VBG 1.0 1.1 1.2 V Bandgap reference start-up time TBD tBG 40 70 s IBG 10 TBD A Bandgap reference current consumption TBD Note: 1. Values are guidelines only. Actual values are TBD. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Units 65 5.8.9 Watchdog Timer Atmel(R) ATA6612C/ATA6613C has an enhanced watchdog timer (WDT). The main features are: Clocked from separate on-chip oscillator 3 operating modes Interrupt System reset Interrupt and system reset Selectable time-out period from 16ms to 8s Possible hardware fuse watchdog always on (WDTON) for fail-safe mode Figure 5-21. Watchdog Timer WDE OSC/1024K OSC/256K OSC/512K OSC/64K OSC/128K OSC/32K OSC/8K OSC/4K OSC/2K WATCHDOG RESET OSC/16K Watchdog Prescaler 128kHz Oscillator WDP0 WDP1 WDP2 WDP3 MCU RESET WDIF WDIE INTERRUPT The watchdog timer (WDT) is a timer counting cycles of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode, it is required that the system uses the WDR - watchdog timer reset - instruction to restart the counter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued. In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, Interrupt and system reset mode, combines the other two modes by first giving an interrupt and then switch to system reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset. 66 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 The watchdog always on (WDTON) fuse, if programmed, will force the watchdog timer to system reset mode. With the fuse programmed the system reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows: 1. In the same operation, write a logic one to the watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. The following code example shows one assembly and one C function for turning off the watchdog timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. Assembly Code Example(1) WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & (0<<WDRF)) out MCUSR, r16 ; Write logical one to WDCE and WDE ; Keep old prescaler setting to prevent unintentional time-out lds r16, WDTCSR ori r16, (1<<WDCE) | (1<<WDE) sts WDTCSR, r16 ; Turn off WDT ldi r16, (0<<WDE) sts WDTCSR, r16 ; Turn on global interrupt sei ret C Code Example(1) void WDT_off(void) { __disable_interrupt(); __watchdog_reset(); /* Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional timeout */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); } Notes: 1. The example code assumes that the part specific header file is included. 2. If the watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the watchdog timer will stay enabled. If the code is not set up to handle the watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the watchdog system reset flag (WDRF) and the WDE control bit in the initialization routine, even if the watchdog is not in use. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 67 The following code example shows one assembly and one C function for changing the time-out value of the watchdog timer. Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCSR ori r16, (1<<WDCE) | (1<<WDE) sts WDTCSR, r16 ; -- Got four cycles to set the new values from here ; Set new prescaler(time-out) value = 64K cycles (~0.5 s) ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0) sts WDTCSR, r16 ; -- Finished setting new values, used 2 cycles ; Turn on global interrupt sei ret C Code Example(1) void WDT_Prescaler_Change(void) { __disable_interrupt(); __watchdog_reset(); /* Start timed equence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */ WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); } Notes: 1. The example code assumes that the part specific header file is included. 2. The watchdog timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period. 5.8.9.1 Watchdog Timer Control Register - WDTCSR Bit 7 6 5 4 3 2 1 0 WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0 WDTCSR * Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the watchdog timer and the watchdog timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the watchdog time-out interrupt is executed. * Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the status register is set, the watchdog interrupt is enabled. If WDE is cleared in combination with this setting, the watchdog timer is in interrupt mode, and the corresponding interrupt is executed if time-out in the watchdog timer occurs. If WDE is set, the watchdog timer is in interrupt and system reset mode. The first time-out in the watchdog timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the watchdog goes to system reset mode). This is useful for keeping the watchdog timer security while using the interrupt. To stay in interrupt and system reset mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the watchdog system reset mode. If the interrupt is not executed before the next time-out, a system reset will be applied. 68 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Table 5-24. Watchdog Timer Configuration WDTON WDE WDIE Mode Action on Time-out 0 0 0 Stopped None 0 0 1 Interrupt mode Interrupt 0 1 0 System reset mode Reset 0 1 1 Interrupt and system reset mode Interrupt, then go to system reset Mode 1 x x System reset mode Reset * Bit 4 - WDCE: Watchdog Change Enable This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set. Once written to one, hardware will clear WDCE after four clock cycles. * Bit 3 - WDE: Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. * Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0 The WDP3..0 bits determine the watchdog timer prescaling when the watchdog timer is running. The different prescaling values and their corresponding time-out periods are shown in Table 5-25. Table 5-25. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K (2048) cycles 16ms 0 0 0 1 4K (4096) cycles 32ms 0 0 1 0 8K (8192) cycles 64ms 0 0 1 1 16K (16384) cycles 0.125s 0 1 0 0 32K (32768) cycles 0.25s 0 1 0 1 64K (65536) cycles 0.5s 0 1 1 0 128K (131072) cycles 1.0s 0 1 1 1 256K (262144) cycles 2.0s 1 0 0 0 512K (524288) cycles 4.0s 1 0 0 1 1024K (1048576) cycles 8.0s 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Reserved ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 69 5.9 Interrupts This section describes the specifics of the interrupt handling as performed in Atmel(R) ATA6612C/ATA6613C. For a general explanation of the AVR(R) interrupt handling, refer to Section 5.4.8 "Reset and Interrupt Handling" on page 36. The interrupt vectors in Atmel ATA6612C and ATA6613C are generally the same, with the following differences: Each interrupt vector occupies two instruction words in ATA6613C, and one instruction word in Atmel ATA6612C. 5.9.1 In Atmel ATA6612C and ATA6613C, the reset vector is affected by the BOOTRST fuse, and the Interrupt vector start address is affected by the IVSEL bit in MCUCR. Interrupt Vectors in Atmel ATA6612C Table 5-26. Reset and Interrupt Vectors in Atmel ATA6612C 70 Vector No. Program Address(2) Source Interrupt Definition 1 0x000(1) RESET External pin, power-on reset, brown-out reset and watchdog system reset 2 0x001 INT0 External interrupt request 0 3 0x002 INT1 External interrupt request 1 4 0x003 PCINT0 Pin change interrupt request 0 5 0x004 PCINT1 Pin change interrupt request 1 6 0x005 PCINT2 Pin change interrupt request 2 7 0x006 WDT Watchdog time-out interrupt 8 0x007 TIMER2 COMPA Timer/Counter2 compare match A 9 0x008 TIMER2 COMPB Timer/Counter2 compare match B 10 0x009 TIMER2 OVF Timer/Counter2 overflow 11 0x00A TIMER1 CAPT Timer/Counter1 capture event 12 0x00B TIMER1 COMPA Timer/Counter1 compare match A 13 0x00C TIMER1 COMPB Timer/coutner1 compare match B 14 0x00D TIMER1 OVF Timer/Counter1 overflow 15 0x00E TIMER0 COMPA Timer/Counter0 compare match A 16 0x00F TIMER0 COMPB Timer/Counter0 compare match B 17 0x010 TIMER0 OVF Timer/Counter0 overflow 18 0x011 SPI, STC SPI serial transfer complete 19 0x012 USART, RX USART Rx complete 20 0x013 USART, UDRE USART, data register empty 21 0x014 USART, TX USART, Tx complete 22 0x015 ADC ADC conversion complete 23 0x016 EE READY EEPROM ready 24 0x017 ANALOG COMP Analog comparator 25 0x018 TWI 2-wire serial interface 26 Notes: 1. 0x019 SPM READY Store program memory ready When the BOOTRST fuse is programmed, the device will jump to the boot loader address at reset (see Section 5.23 "Boot Loader Support - Read-While-Write Self-Programming, Atmel ATA6612C and ATA6613C" on page 240). 2. When the IVSEL bit in MCUCR is set, Interrupt vectors will be moved to the start of the boot flash section. The address of each interrupt vector will then be the address in this table added to the start address of the boot flash section. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Table 5-27 shows reset and interrupt vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. This is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. Table 5-27. Reset and Interrupt Vectors Placement in Atmel ATA6612C(1) BOOTRST IVSEL 1 Note: Reset Address Interrupt Vectors Start Address 0 0x000 0x001 1 1 0x000 Boot reset address + 0x001 0 0 Boot reset address 0x001 0 1. 1 Boot reset address Boot reset address + 0x001 The Boot Reset Address is shown in Table 5-108 on page 251. For the BOOTRST Fuse "1" means unprogrammed while "0" means programmed. The most typical and general program setup for the reset and interrupt vector addresses in Atmel ATA6612C is: Address Labels Code Comments 0x000 rjmp RESET ; Reset Handler 0x001 rjmp EXT_INT0 ; IRQ0 Handler 0x002 rjmp EXT_INT1 ; IRQ1 Handler 0x003 rjmp PCINT0 ; PCINT0 Handler 0x004 rjmp PCINT1 ; PCINT1 Handler 0x005 rjmp PCINT2 ; PCINT2 Handler 0x006 rjmp WDT ; Watchdog Timer Handler 0x007 rjmp TIM2_COMPA ; Timer2 Compare A Handler 0X008 rjmp TIM2_COMPB ; Timer2 Compare B Handler 0x009 rjmp TIM2_OVF ; Timer2 Overflow Handler 0x00A rjmp TIM1_CAPT ; Timer1 Capture Handler 0x00B rjmp TIM1_COMPA ; Timer1 Compare A Handler 0x00C rjmp TIM1_COMPB ; Timer1 Compare B Handler 0x00D rjmp TIM1_OVF ; Timer1 Overflow Handler 0x00E rjmp TIM0_COMPA ; Timer0 Compare A Handler 0x00F rjmp TIM0_COMPB ; Timer0 Compare B Handler 0x010 rjmp TIM0_OVF ; Timer0 Overflow Handler 0x011 rjmp SPI_STC ; SPI Transfer Complete Handler 0x012 rjmp USART_RXC ; USART, RX Complete Handler 0x013 rjmp USART_UDRE ; USART, UDR Empty Handler 0x014 rjmp USART_TXC ; USART, TX Complete Handler 0x015 rjmp ADC ; ADC Conversion Complete Handler 0x016 rjmp EE_RDY ; EEPROM Ready Handler 0x017 rjmp ANA_COMP ; Analog Comparator Handler 0x018 rjmp TWI ; 2-wire Serial Interface Handler 0x019 rjmp SPM_RDY ; Store Program Memory Ready Handler ; 0x01A RESET: ldi r16, high(RAMEND); Main program start 0x01B out SPH,r16 ; Set Stack Pointer to top of RAM 0x01C ldi r16, low(RAMEND) 0x01D out SPL,r16 0x01E sei ; Enable interrupts 0x01F <instr> xxx ... ... ... ... ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 71 When the BOOTRST Fuse is unprogrammed, the boot section size set to 2Kbytes and the IVSEL bit in the MCUCR register is set before any interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses in Atmel(R) ATA6612C is: Address Labels Code Comments 0x000 RESET: ldi r16,high(RAMEND); Main program start 0x001 out SPH,r16 ; Set Stack Pointer to top of RAM 0x002 ldi r16,low(RAMEND) 0x003 out SPL,r16 0x004 sei ; Enable interrupts 0x005 <instr> xxx ; .org 0xC01 0xC01 rjmp EXT_INT0 ; IRQ0 Handler 0xC02 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0xC19 rjmp SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST fuse is programmed and the boot section size set to 2Kbytes, the most typical and general program setup for the reset and Interrupt vector Aadresses in Atmel ATA6612C is: Address Labels Code Comments .org 0x001 0x001 rjmp EXT_INT0 ; IRQ0 Handler 0x002 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x019 rjmp SPM_RDY ; Store Program Memory Ready Handler ; .org 0xC00 0xC00 RESET: ldi r16,high(RAMEND); Main program start 0xC01 out SPH,r16; Set Stack Pointer to top of RAM 0xC02 ldi r16,low(RAMEND) 0xC03 out SPL,r16 0xC04 sei ; Enable interrupts 0xC05 <instr> xxx When the BOOTRST fuse is programmed, the boot section size set to 2Kbytes and the IVSEL bit in the MCUCR register is set before any interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses in Atmel ATA6612C is: Address ; .org 0xC00 0xC00 0xC01 0xC02 ... 0xC19 ; 0xC1A 0xC1B 0xC1C 0xC1D 0xC1E 0xC1F 72 Labels Code rjmp rjmp rjmp ... rjmp ... RESET; Reset handler EXT_INT0; IRQ0 Handler EXT_INT1; IRQ1 Handler ; SPM_RDY; Store Program Memory Ready Handler RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ; Set Stack Pointer to top of RAM ldi r16,low(RAMEND) out SPL,r16 sei ; Enable interrupts <instr> xxx ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Comments 5.9.2 Interrupt Vectors in ATA6613C Table 5-28. Reset and Interrupt Vectors in ATA6613C Vector No. Program Address(2) Source Interrupt Definition 1 0x0000(1) RESET External pin, power-on reset, brown-out reset and watchdog system reset 2 0x0002 INT0 External interrupt request 0 3 0x0004 INT1 External interrupt request 1 4 0x0006 PCINT0 Pin change interrupt request 0 5 0x0008 PCINT1 Pin change interrupt request 1 6 0x000A PCINT2 Pin change interrupt request 2 7 0x000C WDT Watchdog time-out interrupt 8 0x000E TIMER2 COMPA Timer/Counter2 compare match A 9 0x0010 TIMER2 COMPB Timer/Counter2 compare match B 10 0x0012 TIMER2 OVF Timer/Counter2 overflow 11 0x0014 TIMER1 CAPT Timer/Counter1 capture event 12 0x0016 TIMER1 COMPA Timer/Counter1 compare match A 13 0x0018 TIMER1 COMPB Timer/coutner1 compare match B 14 0x001A TIMER1 OVF Timer/Counter1 overflow 15 0x001C TIMER0 COMPA Timer/Counter0 compare match A 16 0x001E TIMER0 COMPB Timer/Counter0 compare match B 17 0x0020 TIMER0 OVF Timer/Counter0 overflow 18 0x0022 SPI, STC SPI serial transfer complete 19 0x0024 USART, RX USART Rx complete 20 0x0026 USART, UDRE USART, data register empty 21 0x0028 USART, TX USART, Tx complete 22 0x002A ADC ADC conversion complete 23 0x002C EE READY EEPROM ready 24 0x002E ANALOG COMP Analog comparator 25 0x0030 TWI 2-wire serial interface 26 Notes: 1. 0x0032 SPM READY Store program memory ready When the BOOTRST Fuse is programmed, the device will jump to the boot loader address at reset (see Section 5.23 "Boot Loader Support - Read-While-Write Self-Programming, Atmel ATA6612C and ATA6613C" on page 240). 2. When the IVSEL bit in MCUCR is set, interrupt vectors will be moved to the start of the boot flash section. The address of each interrupt vector will then be the address in this table added to the start address of the boot flash section. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 73 Table 5-29 shows reset and interrupt vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. This is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. Table 5-29. Reset and Interrupt Vectors Placement in ATA6613C(1) BOOTRST IVSEL Reset Address Interrupt Vectors Start Address 1 0 0x000 0x001 1 1 0x000 Boot reset address + 0x0002 0 0 Boot reset address 0x001 Note: 0 1. 1 Boot reset address Boot reset address + 0x0002 The Boot Reset Address is shown in Table 5-108 on page 251. For the BOOTRST fuse "1" means unprogrammed while "0" means programmed. The most typical and general program setup for the reset and interrupt vector addresses in ATA6613C is: Address Labels Code Comments 0x0000 rjmp RESET ; Reset Handler 0x0002 rjmp EXT_INT0 ; IRQ0 Handler 0x0004 rjmp EXT_INT1 ; IRQ1 Handler 0x0006 rjmp PCINT0 ; PCINT0 Handler 0x0008 rjmp PCINT1 ; PCINT1 Handler 0x000A rjmp PCINT2 ; PCINT2 Handler 0x000C rjmp WDT ; Watchdog Timer Handler 0x000E rjmp TIM2_COMPA ; Timer2 Compare A Handler 0x0010 rjmp TIM2_COMPB ; Timer2 Compare B Handler 0x0012 rjmp TIM2_OVF ; Timer2 Overflow Handler 0x0014 rjmp TIM1_CAPT ; Timer1 Capture Handler 0x0016 rjmp TIM1_COMPA ; Timer1 Compare A Handler 0x0018 rjmp TIM1_COMPB ; Timer1 Compare B Handler 0x001A rjmp TIM1_OVF ; Timer1 Overflow Handler 0x001C rjmp TIM0_COMPA ; Timer0 Compare A Handler 0x001E rjmp TIM0_COMPB ; Timer0 Compare B Handler 0x0020 rjmp TIM0_OVF ; Timer0 Overflow Handler 0x0022 rjmp SPI_STC ; SPI Transfer Complete Handler 0x0024 rjmp USART_RXC ; USART, RX Complete Handler 0x0026 rjmp USART_UDRE ; USART, UDR Empty Handler 0x0028 rjmp USART_TXC ; USART, TX Complete Handler 0x002A rjmp ADC ; ADC Conversion Complete Handler 0x002C rjmp EE_RDY ; EEPROM Ready Handler 0x002E rjmp ANA_COMP ; Analog Comparator Handler 0x0030 rjmp TWI ; 2-wire Serial Interface Handler 0x0032 rjmp SPM_RDY ; Store Program Memory Ready Handler ; 0x0033 RESET: ldi r16, high(RAMEND); Main program start 0x0034 out SPH,r16 ; Set Stack Pointer to top of RAM 0x0035 ldi r16, low(RAMEND) 0x0036 out SPL,r16 0x0037 sei ; Enable interrupts 0x0038 <instr> xxx ... ... ... ... 74 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes and the IVSEL bit in the MCUCR register is set before any interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses in ATA6613C is: Address Labels Code Comments 0x0000 RESET: ldi r16,high(RAMEND); Main program start 0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM 0x0002 ldi r16,low(RAMEND) 0x0003 out SPL,r16 0x0004 sei ; Enable interrupts 0x0005 <instr> xxx ; .org 0xC02 0x1C02 rjmp EXT_INT0 ; IRQ0 Handler 0x1C04 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x1C32 rjmp SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST fuse is programmed and the boot section size set to 2Kbytes, the most typical and general program setup for the reset and interrupt vector addresses in ATA6613C is: Address Labels Code Comments .org 0x0002 0x0002 rjmp EXT_INT0 ; IRQ0 Handler 0x0004 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x0032 rjmp SPM_RDY ; Store Program Memory Ready Handler ; .org 0x1C00 0x1C00 RESET: ldi r16,high(RAMEND); Main program start 0x1C01 out SPH,r16 ; Set Stack Pointer to top of RAM 0x1C02 ldi r16,low(RAMEND) 0x1C03 out SPL,r16 0x1C04 sei ; Enable interrupts 0x1C05 <instr> xxx When the BOOTRST fuse is programmed, the boot section size set to 2Kbytes and the IVSEL bit in the MCUCR register is set before any interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses in ATA6613C is: Address Labels Code Comments ; .org 0x1C00 0x1C00 rjmp RESET ; Reset handler 0x1C02 rjmp EXT_INT0 ; IRQ0 Handler 0x1C04 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x1C32 rjmp SPM_RDY ; Store Program Memory Ready Handler ; 0x1C33 RESET: ldi r16,high(RAMEND); Main program start 0x1C34 out SPH,r16 ; Set Stack Pointer to top of RAM 0x1C35 ldi r16,low(RAMEND) 0x1C36 out SPL,r16 0x1C37 sei ; Enable interrupts 0x1C38 <instr> xxx ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 75 5.9.2.1 Moving Interrupts Between Application and Boot Space, Atmel ATA6612C and ATA6613C The MCU control register controls the placement of the interrupt vector table. 5.9.2.2 MCU Control Register - MCUCR Bit 7 6 5 4 3 2 1 0 - - - PUD - - IVSEL IVCE Read/Write R R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR * Bit 1 - IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the flash memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the boot loader section of the flash. The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. Refer to section Section 5.23 "Boot Loader Support - ReadWhile-Write Self-Programming, Atmel ATA6612C and ATA6613C" on page 240 for details. To avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to change the IVSEL bit: a. Write the interrupt vector change enable (IVCE) bit to one. b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the status register is unaffected by the automatic disabling. Note: If interrupt vectors are placed in the boot loader section and boot lock bit BLB02 is programmed, interrupts are disabled while executing from the application section. If interrupt vectors are placed in the application section and boot lock bit BLB12 is programed, interrupts are disabled while executing from the boot loader section. Refer to Section 5.23 "Boot Loader Support - Read-While-Write Self-Programming, Atmel ATA6612C and ATA6613C" on page 240 for details on boot lock bits. * Bit 0 - IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See code example below. Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret C Code Example void Move_interrupts(void) { /* Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL); } 76 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.10 I/O-Ports 5.10.1 Introduction All AVR(R) ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and ground as indicated in Figure 5-22. Refer to Section 5.25 "Electrical Characteristics" on page 271 for a complete list of parameters. Figure 5-22. I/O Pin Equivalent Schematic Rpu Pxn Logic Cpin See Figure "General Digital I/O" for Details All registers and bit references in this section are written in general form. A lower case "x" represents the numbering letter for the port, and a lower case "n" represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O registers and bit locations are listed in Section 5.10.4 "Register Description for I/O Ports" on page 91. Three I/O memory address locations are allocated for each port, one each for the data register - PORTx, data direction register - DDRx, and the port input pins - PINx. The port input Pins I/O location is read only, while the data register and the data direction register are read/write. However, writing a logic one to a bit in the PINx register, will result in a toggle in the corresponding bit in the data register. In addition, the pull-up disable - PUD bit in MCUCR disables the pull-up function for all pins in all ports when set. Using the I/O port as general digital I/O is described in Section 5.10.2 "Ports as General Digital I/O" on page 78. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in Section 5.10.3 "Alternate Port Functions" on page 81. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 77 5.10.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 5-23 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 5-23. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET RDx D 0 PORTxn Q CLR WPx RESET SLEEP DATA BUS 1 Q Pnx WRx RRx Synchronizer RPx D Q D Q PINxn L Q Q CLKI/O PUD: SLEEP: CLKI/O: Note: 1. PULLUP DISABLE SLEEP CONTROL I/O CLOCK WDx: RDx: WRx: RRx: RPx: WPx: WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. 5.10.2.1 Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in Section 5.10.4 "Register Description for I/O Ports" on page 91, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tristated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 78 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.10.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 5.10.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step. Table 5-30 summarizes the control signals for the pin value. Table 5-30. Port Pin Configurations DDxn PORTxn PUD (in MCUCR) I/O Pull-up 0 0 X Input No Tri-state (hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low. 0 1 1 Input No Tri-state (hi-Z) 1 0 X Output No Output low (sink) 1 1 X Output No Output high (source) Comment 5.10.2.4 Reading the Pin Value Independent of the setting of data direction bit DDxn, the port pin can be read through the PINxn register bit. As shown in Figure 5-23 on page 78, the PINxn register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 5-24 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively. Figure 5-24. Synchronization when Reading an Externally Applied Pin Value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF tpd, max tpd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the "SYNC LATCH" signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between 1/2 and 11/2 system clock period depending upon the time of assertion. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 79 When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 5-25. The out instruction sets the "SYNC LATCH" signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 5-25. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS 0xFF out PORTx, r16 nop in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF tpd The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) out PORTB,r16 out DDRB,r17 ; Insert nop for synchronization nop ; Read port pins in r16,PINB ... C Code Example unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0); DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0); /* Insert nop for synchronization*/ __no_operation(); /* Read port pins */ i = PINB; ... Note: 80 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.10.2.5 Digital Input Enable and Sleep Modes As shown in Figure 5-23 on page 78, the digital input signal can be clamped to ground at the input of the Schmitt trigger. The signal denoted SLEEP in the figure, is set by the MCU sleep controller in power-down mode, power-save mode, and standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in Section 5.10.3 "Alternate Port Functions" on page 81. If a logic high level ("one") is present on an asynchronous external interrupt pin configured as "interrupt on rising edge, falling edge, or any logic change on pin" while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sleep mode, as the clamping in these sleep mode produces the requested logic change. 5.10.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (reset, active mode and idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. 5.10.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 5-26 on page 82 shows how the port pin control signals from the simplified Figure 5-23 on page 78 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR(R) microcontroller family. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 81 Figure 5-26. Alternate Port Functions(1) PUOExn 1 PUOVxn PUD 0 DDOExn 1 DDOVxn 0 D Q DDxn Q CLR RESET WDx RDx PVOExn 1 PVOVxn Pnx 0 PORTxn Q DIEOExn 1 DIEOVxn 0 SLEEP DATA BUS 1 D Q 0 PTOExn CLR RESET WRx WPx RRx Synchronizer RPx D SET Q D Q PINxn L CLR Q CLR Q CLKI/O DIxn AIOxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: PTOExn: Note: 82 1. Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT ENABLE OVERRIDE VALUE SLEEP CONTROL Pxn, PORT TOGGLE OVERRIDE ENABLE PUD: WDx: RDx: RRx: WRx: RPx: WPx: CLK:I/O DIxn: AIOxn: PULL-UP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN WRITE PINx I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Table 5-31 summarizes the function of the overriding signals. The pin and port indexes from Figure 5-26 on page 82 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 5-31. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up override enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up override value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD register bits. DDOE Data direction override enable If this signal is set, the output driver enable is controlled by the DDOV signal. If this signal is cleared, the output driver is enabled by the DDxn register bit. DDOV Data direction override value If DDOE is set, the output driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn register bit. PVOE Port value override enable If this signal is set and the output driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the output driver is enabled, the port value is controlled by the PORTxn register bit. PVOV Port value override value If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn register bit. PTOE Port toggle override enable If PTOE is set, the PORTxn register bit is inverted. DIEOE Digital input enable override enable If this bit is set, the digital input enable is controlled by the DIEOV signal. If this signal is cleared, the digital input enable is determined by MCU state (normal mode, sleep mode). DIEOV Digital input enable override value If DIEOE is set, the digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (normal mode, sleep mode). DI Digital input This is the digital input to alternate functions. In the figure, the signal is connected to the output of the Schmitt trigger but before the synchronizer. Unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. AIO Analog input/output This is the analog input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally. The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. 5.10.3.1 MCU Control Register - MCUCR Bit 7 6 5 4 - Read/Write R Initial Value 0 0 3 2 1 0 - - PUD R R R/W - - IVSEL IVCE R R R/W R/W 0 0 0 0 0 0 MCUCR * Bit 4 - PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See Section 5.10.2.1 "Configuring the Pin" on page 78 for more details about this feature. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 83 5.10.3.2 Alternate Functions of Port B The port B pins with alternate functions are shown in Table 5-32. Table 5-32. Port B Pins Alternate Functions Port Pin Alternate Functions PB7 XTAL2 (chip clock oscillator pin 2) TOSC2 (timer oscillator pin 2) PCINT7 (pin change interrupt 7) PB6 XTAL1 (chip clock oscillator pin 1 or external clock input) TOSC1 (timer oscillator pin 1) PCINT6 (pin change interrupt 6) PB5 SCK (SPI bus master clock input) PCINT5 (pin change interrupt 5) PB4 MISO (SPI bus master input/slave output) PCINT4 (pin change interrupt 4) PB3 MOSI (SPI bus master output/slave input) OC2A (Timer/Counter2 output compare match A output) PCINT3 (pin change interrupt 3) PB2 SS (SPI bus master slave select) OC1B (Timer/Counter1 output compare match B output) PCINT2 (pin change interrupt 2) PB1 OC1A (Timer/Counter1 output compare match A output) PCINT1 (pin change interrupt 1) PB0 ICP1 (Timer/Counter1 input capture input) CLKO (divided system clock output) PCINT0 (pin change interrupt 0) The alternate pin configuration is as follows: * XTAL2/TOSC2/PCINT7 - Port B, Bit 7 XTAL2: Chip clock oscillator pin 2. Used as clock pin for crystal oscillator or low-frequency crystal oscillator. When used as a clock pin, the pin can not be used as an I/O pin. TOSC2: Timer oscillator pin 2. Used only if internal calibrated RC oscillator is selected as chip clock source, and the asynchronous timer is enabled by the correct setting in ASSR. When the AS2 bit in ASSR is set (one) and the EXCLK bit is cleared (zero) to enable asynchronous clocking of Timer/Counter2 using the crystal oscillator, pin PB7 is disconnected from the port, and becomes the inverting output of the oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin cannot be used as an I/O pin. PCINT7: Pin change interrupt source 7. The PB7 pin can serve as an external interrupt source. If PB7 is used as a clock pin, DDB7, PORTB7 and PINB7 will all read 0. * XTAL1/TOSC1/PCINT6 - Port B, Bit 6 XTAL1: Chip clock oscillator pin 1. Used for all chip clock sources except internal calibrated RC oscillator. When used as a clock pin, the pin can not be used as an I/O pin. TOSC1: Timer oscillator pin 1. Used only if internal calibrated RC oscillator is selected as chip clock source, and the asynchronous timer is enabled by the correct setting in ASSR. When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PB6 is disconnected from the port, and becomes the input of the inverting oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an I/O pin. PCINT6: Pin change interrupt source 6. The PB6 pin can serve as an external interrupt source. If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0. 84 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 * SCK/PCINT5 - Port B, Bit 5 SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit. PCINT5: Pin change interrupt source 5. The PB5 pin can serve as an external interrupt source. * MISO/PCINT4 - Port B, Bit 4 MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB4. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB4. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB4 bit. PCINT4: Pin change interrupt source 4. The PB4 pin can serve as an external interrupt source. * MOSI/OC2/PCINT3 - Port B, Bit 3 MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB3. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB3 bit. OC2, output compare match output: The PB3 pin can serve as an external output for the Timer/Counter2 compare match. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer function. PCINT3: Pin change interrupt source 3. The PB3 pin can serve as an external interrupt source. * SS/OC1B/PCINT2 - Port B, Bit 2 SS: Slave select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB2 bit. OC1B, output compare match output: The PB2 pin can serve as an external output for the Timer/Counter1 compare match B. The PB2 pin has to be configured as an output (DDB2 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT2: Pin change interrupt source 2. The PB2 pin can serve as an external interrupt source. * OC1A/PCINT1 - Port B, Bit 1 OC1A, output compare match output: The PB1 pin can serve as an external output for the Timer/Counter1 compare match A. The PB1 pin has to be configured as an output (DDB1 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. PCINT1: Pin change interrupt source 1. The PB1 pin can serve as an external interrupt source. * ICP1/CLKO/PCINT0 - Port B, Bit 0 ICP1, input capture pin: The PB0 pin can act as an input capture pin for Timer/Counter1. CLKO, divided system clock: The divided system clock can be output on the PB0 pin. The divided system clock will be output if the CKOUT fuse is programmed, regardless of the PORTB0 and DDB0 settings. It will also be output during reset. PCINT0: pin change interrupt source 0. The PB0 pin can serve as an external interrupt source. Table 5-33 on page 86 and Table 5-34 on page 86 relate the alternate functions of Port B to the overriding signals shown in Figure 5-26 on page 82. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 85 Table 5-33. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PB7/XTAL2/TOSC2/PCINT7(1) PB6/XTAL1/TOSC1/PCINT6(1) PB5/SCK/PCINT5 PB4/MISO/PCINT4 PUOE INTRC x EXTCK+ AS2 INTRC + AS2 SPE x MSTR SPE x MSTR PUOV 0 0 PORTB5 x PUD PORTB4 x PUD DDOE INTRC x EXTCK+ AS2 INTRC + AS2 SPE x MSTR SPE x MSTR DDOV 0 0 0 0 PVOE 0 0 SPE x MSTR SPE x MSTR PVOV 0 0 SCK OUTPUT SPI SLAVE OUTPUT DIEOE INTRC x EXTCK + AS2 + PCINT7 x PCIE0 INTRC + AS2 + PCINT6 x PCIE0 PCINT5 x PCIE0 PCINT4 x PCIE0 DIEOV (INTRC + EXTCK) x AS2 INTRC x AS2 1 1 PCINT7 INPUT PCINT6 INPUT PCINT5 INPUT SCK INPUT PCINT4 INPUT SPI MSTR INPUT DI AIO Note: 1. Oscillator output Oscillator/clock input - - INTRC means that one of the internal RC oscillators are selected (by the CKSEL fuses), EXTCK means that external clock is selected (by the CKSEL fuses). Table 5-34. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PB3/MOSI/OC2/PCINT3 PB2/SS/OC1B/PCINT2 PB1/OC1A/PCINT1 PB0/ICP1/PCINT0 PUOE SPE x MSTR SPE x MSTR 0 0 PUOV PORTB3 x PUD PORTB2 x PUD 0 0 DDOE SPE x MSTR SPE x MSTR 0 0 DDOV 0 0 0 0 PVOE SPE x MSTR + OC2A ENABLE OC1B ENABLE OC1A ENABLE 0 PVOV SPI MSTR OUTPUT + OC2A OC1B OC1A 0 DIEOE PCINT3 x PCIE0 PCINT2 x PCIE0 PCINT1 x PCIE0 PCINT0 x PCIE0 DIEOV 1 1 1 1 PCINT3 INPUT SPI SLAVE INPUT PCINT2 INPUT SPI SS PCINT1 INPUT PCINT0 INPUT ICP1 INPUT - - - - DI AIO 86 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.10.3.3 Alternate Functions of Port C The port C pins with alternate functions are shown in Table 5-35. Table 5-35. Port C Pins Alternate Functions Port Pin Alternate Function PC6 RESET (reset pin) PCINT14 (pin change interrupt 14) PC5 ADC5 (ADC input channel 5) SCL (2-wire serial bus clock line) PCINT13 (pin change interrupt 13) PC4 ADC4 (ADC input channel 4) SDA (2-wire serial bus data input/output line) PCINT12 (pin change interrupt 12) PC3 ADC3 (ADC input channel 3) PCINT11 (pin change interrupt 11) PC2 ADC2 (ADC input channel 2) PCINT10 (pin change interrupt 10) PC1 ADC1 (ADC input channel 1) PCINT9 (pin change interrupt 9) PC0 ADC0 (ADC input channel 0) PCINT8 (pin change interrupt 8) The alternate pin configuration is as follows: * RESET/PCINT14 - Port C, Bit 6 RESET, reset pin: When the RSTDISBL fuse is programmed, this pin functions as a normal I/O pin, and the part will have to rely on power-on reset and brown-out reset as its reset sources. When the RSTDISBL fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an I/O pin. If PC6 is used as a reset pin, DDC6, PORTC6 and PINC6 will all read 0. PCINT14: Pin change interrupt source 14. The PC6 pin can serve as an external interrupt source. * SCL/ADC5/PCINT13 - Port C, Bit 5 SCL, 2-wire serial interface clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire serial interface, pin PC5 is disconnected from the port and becomes the serial clock I/O pin for the 2-wire serial interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. PC5 can also be used as ADC input channel 5. Note that ADC input channel 5 uses digital power. PCINT13: Pin change interrupt source 13. The PC5 pin can serve as an external interrupt source. * SDA/ADC4/PCINT12 - Port C, Bit 4 SDA, 2-wire serial interface data: When the TWEN bit in TWCR is set (one) to enable the 2-wire serial interface, pin PC4 is disconnected from the port and becomes the serial data I/O pin for the 2-wire serial interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. PC4 can also be used as ADC input Channel 4. Note that ADC input channel 4 uses digital power. PCINT12: Pin change interrupt source 12. The PC4 pin can serve as an external interrupt source. * ADC3/PCINT11 - Port C, Bit 3 PC3 can also be used as ADC input Channel 3. Note that ADC input channel 3 uses analog power. PCINT11: Pin change interrupt source 11. The PC3 pin can serve as an external interrupt source. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 87 * ADC2/PCINT10 - Port C, Bit 2 PC2 can also be used as ADC input channel 2. Note that ADC input channel 2 uses analog power. PCINT10: Pin change interrupt source 10. The PC2 pin can serve as an external interrupt source. * ADC1/PCINT9 - Port C, Bit 1 PC1 can also be used as ADC input channel 1. Note that ADC input channel 1 uses analog power. PCINT9: Pin change interrupt source 9. The PC1 pin can serve as an external interrupt source. * ADC0/PCINT8 - Port C, Bit 0 PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog power. PCINT8: Pin change interrupt source 8. The PC0 pin can serve as an external interrupt source. Table 5-36 and Table 5-37 relate the alternate functions of port C to the overriding signals shown in Figure 5-26 on page 82. Table 5-36. Overriding Signals for Alternate Functions in PC6..PC4(1) Signal Name PC6/RESET/PCINT14 PC5/SCL/ADC5/PCINT13 PC4/SDA/ADC4/PCINT12 PUOE RSTDISBL TWEN TWEN PUOV 1 PORTC5 x PUD PORTC4 x PUD DDOE RSTDISBL TWEN TWEN DDOV 0 SCL_OUT SDA_OUT PVOE 0 TWEN TWEN 0 0 PVOV 0 DIEOE RSTDISBL + PCINT14 x PCIE1 PCINT13 x PCIE1 + ADC5D DIEOV RSTDISBL PCINT13 x PCIE1 PCINT12 x PCIE1 PCINT14 INPUT PCINT13 INPUT PCINT12 INPUT DI Note: AIO 1. PCINT12 x PCIE1 + ADC4D RESET INPUT ADC5 INPUT / SCL INPUT ADC4 INPUT / SDA INPUT When enabled, the 2-wire serial interface enables slew-rate controls on the output pins PC4 and PC5. This is not shown in the figure. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. Table 5-37. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PC3/ADC3/PCINT11 PC2/ADC2/PCINT10 PC1/ADC1/PCINT9 PC0/ADC0/PCINT8 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 DIEOE PCINT11 x PCIE1 + ADC3D PCINT10 x PCIE1 + ADC2D PCINT9 x PCIE1 + ADC1D PCINT8 x PCIE1 + ADC0D DIEOV PCINT11 x PCIE1 PCINT10 x PCIE1 PCINT9 x PCIE1 PCINT8 x PCIE1 PCINT11 INPUT PCINT10 INPUT PCINT9 INPUT PCINT8 INPUT ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT DI AIO 88 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.10.3.4 Alternate Functions of Port D The port D pins with alternate functions are shown in Table 5-38. Table 5-38. Port D Pins Alternate Functions Port Pin Alternate Function PD7 AIN1 (analog comparator negative input) PCINT23 (pin change interrupt 23) PD6 AIN0 (analog comparator positive input) OC0A (Timer/Counter0 output compare match A output) PCINT22 (pin change interrupt 22) PD5 T1 (Timer/Counter 1 external counter input) OC0B (Timer/Counter0 output compare match B output) PCINT21 (pin change interrupt 21) PD4 XCK (USART external clock input/output) T0 (Timer/Counter 0 external counter input) PCINT20 (pin change interrupt 20) PD3 INT1 (external interrupt 1 input) OC2B (Timer/Counter2 output compare match B output) PCINT19 (pin change interrupt 19) PD2 INT0 (external interrupt 0 input) PCINT18 (pin change interrupt 18) PD1 TXD (USART output pin) PCINT17 (pin change interrupt 17) PD0 RXD (USART input pin) PCINT16 (pin change interrupt 16) The alternate pin configuration is as follows: * AIN1/OC2B/PCINT23 - Port D, Bit 7 AIN1, analog comparator negative input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. PCINT23: Pin change interrupt source 23. The PD7 pin can serve as an external interrupt source. * AIN0/OC0A/PCINT22 - Port D, Bit 6 AIN0, analog comparator positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. OC0A, output compare match output: The PD6 pin can serve as an external output for the Timer/Counter0 compare match A. The PD6 pin has to be configured as an output (DDD6 set (one)) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function. PCINT22: Pin change interrupt source 22. The PD6 pin can serve as an external interrupt source. * T1/OC0B/PCINT21 - Port D, Bit 5 T1, Timer/Counter1 counter source. OC0B, output compare match output: The PD5 pin can serve as an external output for the Timer/Counter0 compare match B. The PD5 pin has to be configured as an output (DDD5 set (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function. PCINT21: Pin change interrupt source 21. The PD5 pin can serve as an external interrupt source. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 89 * XCK/T0/PCINT20 - Port D, Bit 4 XCK, USART external clock. T0, Timer/Counter0 counter source. PCINT20: Pin change interrupt source 20. The PD4 pin can serve as an external interrupt source. * INT1/OC2B/PCINT19 - Port D, Bit 3 INT1, external interrupt source 1: The PD3 pin can serve as an external interrupt source. OC2B, output compare match output: The PD3 pin can serve as an external output for the Timer/Counter0 compare match B. The PD3 pin has to be configured as an output (DDD3 set (one)) to serve this function. The OC2B pin is also the output pin for the PWM mode timer function. PCINT19: Pin change interrupt source 19. The PD3 pin can serve as an external interrupt source. * INT0/PCINT18 - Port D, Bit 2 INT0, external interrupt source 0: The PD2 pin can serve as an external interrupt source. PCINT18: Pin change interrupt source 18. The PD2 pin can serve as an external interrupt source. * TXD/PCINT17 - Port D, Bit 1 TXD, transmit data (Data output pin for the USART). When the USART Transmitter is enabled, this pin is configured as an output regardless of the value of DDD1. PCINT17: Pin change interrupt source 17. The PD1 pin can serve as an external interrupt source. * RXD/PCINT16 - Port D, Bit 0 RXD, receive data (Data input pin for the USART). When the USART receiver is enabled this pin is configured as an input regardless of the value of DDD0. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD0 bit. PCINT16: Pin change interrupt source 16. The PD0 pin can serve as an external interrupt source. Table 5-39 and Table 5-40 on page 91 relate the alternate functions of Port D to the overriding signals shown in Figure 5-26 on page 82. Table 5-39. Overriding Signals for Alternate Functions PD7..PD4 90 Signal Name PD7/AIN1/PCINT23 PD6/AIN0/OC0A/PCINT22 PD5/T1/OC0B/PCINT21 PD4/XCK/T0/PCINT20 PUOE 0 0 0 0 PUO 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 OC0A ENABLE OC0B ENABLE UMSEL PVOV 0 OC0A OC0B XCK OUTPUT DIEOE PCINT23 x PCIE2 PCINT22 x PCIE2 PCINT21 x PCIE2 PCINT20 x PCIE2 DIEOV 1 1 1 1 DI PCINT23 INPUT PCINT22 INPUT PCINT21 INPUT T1 INPUT PCINT20 INPUT XCK INPUT T0 INPUT AIO AIN1 INPUT AIN0 INPUT - - ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Table 5-40. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PD3/OC2B/INT1/PCINT19 PD2/INT0/PCINT18 PD1/TXD/PCINT17 PD0/RXD/PCINT16 PUOE 0 0 TXEN RXEN PUO 0 0 0 PORTD0 x PUD DDOE 0 0 TXEN RXEN DDOV 0 0 1 0 PVOE OC2B ENABLE 0 TXEN 0 PVOV OC2B 0 TXD 0 DIEOE INT1 ENABLE + PCINT19 x PCIE2 INT0 ENABLE + PCINT18 x PCIE1 PCINT17 x PCIE2 PCINT16 x PCIE2 DIEOV 1 1 1 1 DI PCINT19 INPUT INT1 INPUT PCINT18 INPUT INT0 INPUT PCINT17 INPUT PCINT16 INPUT RXD AIO - - - - 5.10.4 Register Description for I/O Ports 5.10.4.1 The Port B Data Register - PORTB Bit 7 6 5 4 3 2 1 0 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PORTB 5.10.4.2 The Port B Data Direction Register - DDRB Bit 7 6 5 4 3 2 1 0 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRB 5.10.4.3 The Port B Input Pins Address - PINB Bit 7 6 5 4 3 2 1 0 PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 Read/Write R R R R R R R R Initial Value N/A N/A N/A N/A N/A N/A N/A N/A 4 3 2 1 0 PINB 5.10.4.4 The Port C Data Register - PORTC Bit 7 - 6 5 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PORTC 5.10.4.5 The Port C Data Direction Register - DDRC Bit 7 6 5 4 3 2 1 0 - DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRC ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 91 5.10.4.6 The Port C Input Pins Address - PINC Bit 7 6 5 4 3 2 1 0 - PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 Read/Write R R R R R R R R Initial Value 0 N/A N/A N/A N/A N/A N/A N/A 4 3 2 1 0 PINC 5.10.4.7 The Port D Data Register - PORTD Bit 7 6 5 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PORTD 5.10.4.8 The Port D Data Direction Register - DDRD Bit 7 6 5 4 3 2 1 0 DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRD 5.10.4.9 The Port D Input Pins Address - PIND Bit 5.11 7 6 5 4 3 2 1 0 PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 Read/Write R R R R R R R R Initial Value N/A N/A N/A N/A N/A N/A N/A N/A PIND External Interrupts The external interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI2 will trigger if any enabled PCINT23..16 pin toggles. The pin change interrupt PCI1 will trigger if any enabled PCINT14..8 pin toggles. The pin change interrupt PCI0 will trigger if any enabled PCINT7..0 pin toggles. The PCMSK2, PCMSK1 and PCMSK0 registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT23..0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than idle mode. The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the external interrupt control register A - EICRA. When the INT0 or INT1 interrupts are enabled and are configured as level triggered, the interrupts will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 or INT1 requires the presence of an I/O clock, described in Section 5.6.1 "Clock Systems and their Distribution" on page 46. Low level interrupt on INT0 and INT1 is detected asynchronously. This implies that this interrupt can be used for waking the part also from sleep modes other than idle mode. The I/O clock is halted in all sleep modes except idle mode. Note that if a level triggered interrupt is used for wake-up from power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL fuses as described in Section 5.6 "System Clock and Clock Options" on page 46. 92 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.11.1 External Interrupt Control Register A - EICRA The external interrupt control register A contains control bits for interrupt sense control. Bit 7 6 5 4 3 2 1 0 - - Read/Write R R - - ISC11 ISC10 ISC01 ISC00 R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EICRA * Bit 7..4 - Res: Reserved Bits These bits are unused bits in the Atmel(R) ATA6612C/ATA6613C, and will always read as zero. * Bit 3, 2 - ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The external interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 5-41. The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 5-41. Interrupt 1 Sense Control ISC11 ISC10 Description 0 0 The low level of INT1 generates an interrupt request. 0 1 Any logical change on INT1 generates an interrupt request. 1 0 The falling edge of INT1 generates an interrupt request. 1 1 The rising edge of INT1 generates an interrupt request. * Bit 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The external interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 5-42. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 5-42. Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 93 5.11.2 External Interrupt Mask Register - EIMSK Bit 7 6 5 4 3 2 1 0 - - - - - - INT1 INT0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIMSK * Bit 7..2 - Res: Reserved Bits These bits are unused bits in the Atmel(R) ATA6612C/ATA6613C, and will always read as zero. * Bit 1 - INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the status register (SREG) is set (one), the external pin interrupt is enabled. The interrupt sense control1 bits 1/0 (ISC11 and ISC10) in the external interrupt control register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of external interrupt request 1 is executed from the INT1 interrupt vector. * Bit 0 - INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the status register (SREG) is set (one), the external pin interrupt is enabled. The interrupt sense control0 bits 1/0 (ISC01 and ISC00) in the external interrupt control register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of external interrupt request 0 is executed from the INT0 interrupt vector. 5.11.3 External Interrupt Flag Register - EIFR Bit 7 6 5 4 3 2 1 0 - - - - - - INTF1 INTF0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIFR * Bit 7..2 - Res: Reserved Bits These bits are unused bits in the Atmel ATA6612C/ATA6613C, and will always read as zero. * Bit 1 - INTF1: External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT1 is configured as a level interrupt. * Bit 0 - INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. 94 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.11.4 Pin Change Interrupt Control Register - PCICR Bit 7 6 5 4 3 2 1 0 - - - - - PCIE2 PCIE1 PCIE0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCICR * Bit 7..3 - Res: Reserved Bits These bits are unused bits in the Atmel(R) ATA6612C/ATA6613C, and will always read as zero. * Bit 2 - PCIE2: Pin Change Interrupt Enable 2 When the PCIE2 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an interrupt. The corresponding interrupt of pin change interrupt request is executed from the PCI2 interrupt vector. PCINT23..16 pins are enabled individually by the PCMSK2 register. * Bit 1 - PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT14..8 pin will cause an interrupt. The corresponding interrupt of pin change interrupt request is executed from the PCI1 interrupt vector. PCINT14..8 pins are enabled individually by the PCMSK1 register. * Bit 0 - PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of pin change interrupt request is executed from the PCI0 interrupt vector. PCINT7..0 pins are enabled individually by the PCMSK0 register. 5.11.5 Pin Change Interrupt Flag Register - PCIFR Bit 7 6 5 4 3 2 1 0 - - - Read/Write R R R - - PCIF2 PCIF1 PCIF0 R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCIFR * Bit 7..3 - Res: Reserved Bits These bits are unused bits in the Atmel ATA6612C/ATA6613C, and will always read as zero. * Bit 2 - PCIF2: Pin Change Interrupt Flag 2 When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. * Bit 1 - PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. * Bit 0 - PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 95 5.11.6 Pin Change Mask Register 2 - PCMSK2 Bit 7 6 5 4 3 2 1 0 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK2 * Bit 7..0 - PCINT23..16: Pin Change Enable Mask 23..16 Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23..16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 5.11.7 Pin Change Mask Register 1 - PCMSK1 Bit 7 Read/Write R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 - 6 5 4 3 2 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 1 0 PCINT9 PCINT8 R/W R/W 0 0 PCMSK1 * Bit 7 - Res: Reserved Bit This bit is an unused bit in the Atmel(R) ATA6612C/ATA6613C, and will always read as zero. * Bit 6..0 - PCINT14..8: Pin Change Enable Mask 14..8 Each PCINT14..8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT14..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT14..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 5.11.8 Pin Change Mask Register 0 - PCMSK0 Bit 7 6 5 4 3 2 1 0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK0 * Bit 7..0 - PCINT7..0: Pin Change Enable Mask 7..0 Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 5.12 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent output compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation. The main features are: Two independent output compare units 96 Double buffered output compare registers Clear timer on compare match (auto reload) Glitch free, phase correct pulse width modulator (PWM) Variable PWM period Frequency generator Three independent interrupt sources (TOV0, OCF0A, and OCF0B) ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.12.1 Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 5-27. The device-specific I/O register and bit locations are listed in the Section 5.12.8 "8-bit Timer/Counter Register Description" on page 107. The PRTIM0 bit in Section 5.7.7.1 "Power Reduction Register - PRR" on page 58 must be written to zero to enable Timer/Counter0 module. Figure 5-27. 8-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int. Req.) Control Logic clkTn TOSC1 T/C Oscillator Prescaler TOP TOSC2 BOTTOM clkI/O Timer/Counter TCNTn = = 0 OCnA (Int. Req.) Waveform Generation = OCnA DATA BUS OCRnA Fixed TOP Value OCnB (Int. Req.) Waveform Generation = OCnB OCRnB TCCRnA TCCRnB ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 97 5.12.1.1 Definitions Many register and bit references in this section are written in general form. A lower case "n" replaces the Timer/Counter number, in this case 0. A lower case "x" replaces the output compare unit, in this case compare unit A or compare unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. The definitions in Table 5-43 are also used extensively throughout the document. Table 5-43. General Counter Definitions Parameter Definition BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A register. The assignment is dependent on the mode of operation. 5.12.1.2 Registers The Timer/Counter (TCNT0) and output compare registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the timer interrupt flag register (TIFR0). All interrupts are individually masked with the timer interrupt mask register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The clock select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT0). The double buffered output compare registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the output compare pins (OC0A and OC0B). See Section 5.14.6.3 "Using the Output Compare Unit" on page 123 for details. The compare match event will also set the compare flag (OCF0A or OCF0B) which can be used to generate an output compare interrupt request. 5.12.2 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS02:0) bits located in the Timer/Counter control register (TCCR0B). For details on clock sources and prescaler (see Section 5.13 "Timer/Counter0 and Timer/Counter1 Prescalers" on page 112). 5.12.3 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 5-28 shows a block diagram of the counter and its surroundings. Figure 5-28. Counter Unit Block Diagram TOVn (Int. Req.) DATA BUS Clock Select Count TCNTn Clear Control Logic clkTn Edge Detector Direction (From Prescaler) Bottom 98 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Top Tn Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the clock select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter control register (TCCR0A) and the WGM02 bit located in the Timer/Counter control register B (TCCR0B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs OC0A and OC0B. For more details about advanced counting sequences and waveform generation (see Section 5.12.6 "Modes of Operation" on page 101). The Timer/Counter overflow flag (TOV0) is set according to the mode of operation selected by the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt. 5.12.4 Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the output compare registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the output compare flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. The output compare flag is automatically cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the WGM02:0 bits and compare output mode (COM0x1:0) bits. The max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see Section 5.12.6 "Modes of Operation" on page 101). Figure 5-29 shows a block diagram of the output compare unit. Figure 5-29. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator) OCFnx (Int. Req.) Top Bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 99 The OCR0x registers are double buffered when using any of the pulse width modulation (PWM) modes. For the normal and clear timer on compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x compare registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR0x register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x buffer register, and if double buffering is disabled the CPU will access the OCR0x directly. 5.12.4.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (FOC0x) bit. Forcing compare match will not set the OCF0x flag or reload/clear the timer, but the OC0x pin will be updated as if a real compare match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or toggled). 5.12.4.2 Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0 register will block any compare match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 5.12.4.3 Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the output compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. The setup of the OC0x should be performed before setting the data direction register for the port pin to output. The easiest way of setting the OC0x value is to use the force output compare (FOC0x) strobe bits in normal mode. The OC0x registers keep their values even when changing between waveform generation modes. Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately. 5.12.5 Compare Match Output Unit The compare output mode (COM0x1:0) bits have two functions. The waveform generator uses the COM0x1:0 bits for defining the output compare (OC0x) state at the next compare match. Also, the COM0x1:0 bits control the OC0x pin output source. Figure 5-30 on page 101 shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x state, the reference is for the internal OC0x register, not the OC0x pin. If a system reset occur, the OC0x register is reset to "0". 100 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Figure 5-30. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx Pin OCnx 0 DATA BUS D Q PORT D clkI/O Q DDR The general I/O port function is overridden by the output compare (OC0x) from the waveform generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the data direction register (DDR) for the port pin. The data direction register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visible on the pin. The port override function is independent of the waveform generation mode. The design of the output compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation (see Section 5.12.8 "8-bit Timer/Counter Register Description" on page 107). 5.12.5.1 Compare Output Mode and Waveform Generation The waveform generator uses the COM0x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the waveform generator that no action on the OC0x register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 5-44 on page 107. For fast PWM mode, refer to Table 5-45 on page 107, and for phase correct PWM refer to Table 5-46 on page 107. A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits. 5.12.6 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the waveform generation mode (WGM02:0) and compare output mode (COM0x1:0) bits. The compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. The COM0x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a compare match (see Section 5.12.5 "Compare Match Output Unit" on page 100). For detailed timing information refer to Section 5.12.7 "Timer/Counter Timing Diagrams" on page 105. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 101 5.12.6.1 Normal Mode The simplest mode of operation is the normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter overflow flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 flag, the timer resolution can be increased by software. There are no special cases to consider in the normal mode, a new counter value can be written anytime. The output compare unit can be used to generate interrupts at some given time. Using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the CPU time. 5.12.6.2 Clear Timer on Compare Match (CTC) Mode In clear timer on compare or CTC mode (WGM02:0 = 2), the OCR0A register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 5-31. The counter value (TCNT0) increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 5-31. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = ---------------------------------------------------2 x N x ( 1 + OCRnx ) The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the normal mode of operation, the TOV0 flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 102 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.12.6.3 Fast PWM Mode The fast pulse width modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-inverting compare output mode, the output compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x, and set at BOTTOM. In inverting compare output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 5-32. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. Figure 5-32. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter overflow flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows the OC0A pin to toggle on compare matches if the WGM02 bit is set. This option is not available for the OC0B pin (see Table 5-48 on page 108). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0x register at the compare match between OCR0x and TCNT0, and clearing (or setting) the OC0x register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 103 The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = ------------------N x 256 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. 5.12.6.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non-inverting compare output mode, the output compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x while upcounting, and set on the compare match while downcounting. In inverting output compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 5-33 on page 104. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. Figure 5-33. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 104 1 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 2 3 The Timer/Counter overflow flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on compare matches if the WGM02 bit is set. This option is not available for the OC0B pin (see Table 5-49 on page 108). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0x register at the compare match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x register at compare match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = ------------------N x 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 5-33 on page 104 OCnx has a transition from high to low even though there is no compare match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without compare match. OCRnx changes its value from MAX, like in Figure 5-33 on page 104. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting compare match. To ensure symmetry around BOTTOM the OCnx value at MAX must correspond to the result of an up-counting compare match. The timer starts counting from a value higher than the one in OCRnx, and for that reason misses the compare match and hence the OCnx change that would have happened on the way up. 5.12.7 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set. Figure 5-34 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 5-34. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O/1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 105 Figure 5-35 shows the same timing data, but with the prescaler enabled. Figure 5-35. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 5-36 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 5-36. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 5-37 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP. Figure 5-37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC) TOP - 1 OCRnx OCFnx 106 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 TOP BOTTOM TOP BOTTOM + 1 5.12.8 8-bit Timer/Counter Register Description 5.12.8.1 Timer/Counter Control Register A - TCCR0A Bit 7 6 5 4 COM0A1 COM0A0 COM0B1 COM0B0 3 2 1 0 - - WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A * Bits 7:6 - COM0A1:0: Compare Match Output A Mode These bits control the output compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver. When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting. Table 5-44 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM). Table 5-44. Compare Output Mode, non-PWM Mode COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected. 0 1 Toggle OC0A on compare match 1 0 Clear OC0A on compare match 1 1 Set OC0A on compare match Table 5-45 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 5-45. Compare Output Mode, Fast PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal port operation, OC0A disconnected. WGM02 = 1: Toggle OC0A on compare match. 1 0 Clear OC0A on compare match, set OC0A at TOP Note: 1 1. Description 1 Set OC0A on compare match, clear OC0A at TOP A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See Section 5.12.6.3 "Fast PWM Mode" on page 103 for more details. Table 5-46 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 5-46. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal port operation, OC0A disconnected. WGM02 = 1: Toggle OC0A on compare match. 1 0 Clear OC0A on compare match when up-counting. Set OC0A on compare match when down-counting. 1 Note: 1. Description Set OC0A on compare match when up-counting. Clear OC0A on compare match when down-counting. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See Section 5.14.8.4 "Phase Correct PWM Mode" on page 127 for more details. 1 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 107 * Bits 5:4 - COM0B1:0: Compare Match Output B Mode These bits control the output compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver. When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting. Table 5-47 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM). Table 5-47. Compare Output Mode, non-PWM Mode COM0B1 COM0B0 Description 0 0 Normal port operation, OC0B disconnected. 0 1 Toggle OC0B on compare match 1 0 Clear OC0B on compare match 1 1 Set OC0B on compare match Table 5-48 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM mode. Table 5-48. Compare Output Mode, Fast PWM Mode(1) COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on compare match, set OC0B at TOP Note: 1 1. Description 1 Set OC0B on compare match, clear OC0B at TOP A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See Section 5.12.6.3 "Fast PWM Mode" on page 103 for more details. Table 5-49 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 5-49. Compare Output Mode, Phase Correct PWM Mode(1) COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on compare match when up-counting. Set OC0B on compare match when down-counting. 1 Note: 1. Description Set OC0B on compare match when up-counting. Clear OC0B on compare match when down-counting. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See Section 5.12.6.4 "Phase Correct PWM Mode" on page 104 for more details. 1 * Bits 3, 2 - Res: Reserved Bits These bits are reserved bits in the Atmel(R) ATA6612C/ATA6613C and will always read as zero. * Bits 1:0 - WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used (see Table 5-50 on page 109). Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), clear timer on compare match (CTC) mode, and two types of pulse width modulation (PWM) modes (see Section 5.12.6 "Modes of Operation" on page 101). 108 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Table 5-50. Waveform Generation Mode Bit Description Timer/Counter Mode of Operation TOP Update of OCRx at TOV Flag Set on(1)(2) 0 Normal 0xFF Immediate MAX 0 1 PWM, phase correct 0xFF TOP BOTTOM 1 0 CTC OCRA Immediate MAX 0 1 1 Fast PWM 0xFF TOP MAX 4 1 0 0 Reserved - - - 5 1 0 1 PWM, phase correct OCRA TOP BOTTOM 6 1 1 0 Reserved - - - 1 1 Fast PWM OCRA TOP TOP Mode WGM02 WGM01 WGM00 0 0 0 1 0 2 0 3 7 Notes: 1. 1 MAX 2. BOTTOM = 0x00 = 0xFF 5.12.8.2 Timer/Counter Control Register B - TCCR0B Bit 7 6 5 4 3 2 1 0 FOC0A FOC0B - - WGM02 CS02 CS01 CS00 Read/Write W W R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B * Bit 7 - FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate compare match is forced on the waveform generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced compare. A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP. The FOC0A bit is always read as zero. * Bit 6 - FOC0B: Force Output Compare B The FOC0B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate compare match is forced on the waveform generation unit. The OC0B output is changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the forced compare. A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. * Bits 5:4 - Res: Reserved Bits These bits are reserved bits in the Atmel(R) ATA6612C/ATA6613C and will always read as zero. * Bit 3 - WGM02: Waveform Generation Mode See the description in the Section 5.12.8.1 "Timer/Counter Control Register A - TCCR0A" on page 107. * Bits 2:0 - CS02:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 109 Table 5-51. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(no prescaling) 0 1 0 clkI/O/8 (from prescaler) 0 1 1 clkI/O/64 (from prescaler) 1 0 0 clkI/O/256 (from prescaler) 1 0 1 clkI/O/1024 (from prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 5.12.8.3 Timer/Counter Register - TCNT0 Bit 7 6 5 4 Read/Write R/W R/W R/W R/W Initial Value 0 0 0 0 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 TCNT0[7:0] TCNT0 The Timer/Counter register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 and the OCR0x registers. 5.12.8.4 Output Compare Register A - OCR0A Bit 7 6 5 4 3 2 1 0 OCR0A[7:0] OCR0A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The output compare register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0A pin. 5.12.8.5 Output Compare Register B - OCR0B Bit 7 6 5 4 Read/Write R/W R/W R/W R/W Initial Value 0 0 0 0 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 OCR0B[7:0] OCR0B The output compare register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0B pin. 110 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.12.8.6 Timer/Counter Interrupt Mask Register - TIMSK0 Bit 7 6 5 4 3 2 1 0 - - - - - OCIE0B OCIE0A TOIE0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK0 * Bits 7..3 - Res: Reserved Bits These bits are reserved bits in the Atmel(R) ATA6612C/ATA6613C and will always read as zero. * Bit 2 - OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the status register is set, the Timer/Counter compare match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter interrupt flag register - TIFR0. * Bit 1 - OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the status register is set, the Timer/Counter0 compare match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 interrupt flag register - TIFR0. * Bit 0 - TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the status register is set, the Timer/Counter0 overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 interrupt flag Register - TIFR0r 5.12.8.7 Timer/Counter 0 Interrupt Flag Register - TIFR0 Bit 7 6 5 4 3 2 1 0 - - - - - OCF0B OCF0A TOV0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR0 * Bits 7..3 - Res: Reserved Bits These bits are reserved bits in the Atmel ATA6612C/ATA6613C and will always read as zero. * Bit 2 - OCF0B: Timer/Counter 0 Output Compare B Match Flag The OCF0B bit is set when a compare match occurs between the Timer/Counter and the data in OCR0B - output compare register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter compare B match interrupt enable), and OCF0B are set, the Timer/Counter compare match interrupt is executed. * Bit 1 - OCF0A: Timer/Counter 0 Output Compare A Match Flag The OCF0A bit is set when a compare match occurs between the Timer/Counter0 and the data in OCR0A - output compare register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 compare match interrupt enable), and OCF0A are set, the Timer/Counter0 compare match interrupt is executed. * Bit 0 - TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 overflow interrupt enable), and TOV0 are set, the Timer/Counter0 overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 5-50 on page 109 and Section 5-50 "Waveform Generation Mode Bit Description" on page 109. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 111 5.13 Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 5.13.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. 5.13.2 Prescaler Reset The prescaler is free running, i.e., operates independently of the clock select logic of the Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is not affected by the Timer/Counter's clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. 5.13.3 External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 5-38 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 5-38. T1/T0 Pin Sampling Tn D Q D Q D Tn_sync (To Clock Select Logic) Q LE clkI/O Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. 112 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Figure 5-39. Prescaler for Timer/Counter0 and Timer/Counter1(1) CK/256 CK/8 PSRSYNC Note: T0 Synchronization T1 Synchronization 1. 0 CK/1024 10-bit T/C Prescaler Clear CK/64 clkI/O 0 CS10 CS00 CS11 CS01 CS12 CS02 Timer/Counter1 Clock Source Timer/Counter0 Clock Source clkT1 clkT0 The synchronization logic on the input pins (T1/T0) is shown in Figure 5-38 on page 112. 5.13.4 General Timer/Counter Control Register - GTCCR Bit 7 6 5 4 3 2 1 0 TSM - - - - - PSRASY PSRSYNC Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR * Bit 7 - TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter synchronization mode. In this mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously. * Bit 0 - PSRSYNC: Prescaler Reset When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 5.14 16-bit Timer/Counter1 with PWM The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: True 16-bit design (i.e., allows 16-bit PWM) Two independent output compare units Double buffered output compare registers One input capture unit Input capture noise canceler Clear timer on compare match (auto reload) Glitch-free, phase correct pulse width modulator (PWM) ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 113 Variable PWM period Frequency generator External event counter Four independent interrupt sources (TOV1, OCF1A, OCF1B, and ICF1) 5.14.1 Overview Most register and bit references in this section are written in general form. A lower case "n" replaces the Timer/Counter number, and a lower case "x" replaces the output compare unit channel. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 5-40 on page 114. The device-specific I/O register and bit locations are listed in the Section 5.14.10 "16-bit Timer/Counter Register Description" on page 132. The PRTIM1 bit in Section 5.7.7.1 "Power Reduction Register - PRR" on page 58 must be written to zero to enable Timer/Counter1 module. Figure 5-40. 16-bit Timer/Counter Block Diagram(1) TOVn (Int. Req.) Count Clear Direction Clock Select Control Logic clkTn TOP BOTTOM = = Edge Detector Tn (from Prescaler) Timer/Counter TCNTn 0 OCnA (Int. Req.) Waveform Generation = OCnA OCRnA DATA BUS Fixed TOP Value OCnB (Int. Req.) Waveform Generation = OCnB (From Analog Comparator Output) OCRnB ICFn (Int. Req.) Edge Detector ICRn TCCRnA Note: 114 1. Noise Canceler ICPn TCCRnB Refer to Table 5-32 on page 84 and Table 5-38 on page 89 for Timer/Counter1 pin placement and description. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.14.1.1 Registers The Timer/Counter (TCNT1), output compare registers (OCR1A/B), and input capture register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the Section 5.14.2 "Accessing 16-bit Registers" on page 115. The Timer/Counter control registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the timer interrupt flag register (TIFR1). All interrupts are individually masked with the timer interrupt mask register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The clock select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT1). The double buffered output compare registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the output compare pin (OC1A/B), see Section 5.14.6 "Output Compare Units" on page 121. The compare match event will also set the compare match flag (OCF1A/B) which can be used to generate an output compare interrupt request. The input capture register can capture the Timer/Counter value at a given external (edge triggered) event on either the input capture pin (ICP1) or on the analog comparator pins (see Section 5.20 "Analog Comparator" on page 221). The input capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A register, the ICR1 register, or by a set of fixed values. When using OCR1A as TOP value in a PWM mode, the OCR1A register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 register can be used as an alternative, freeing the OCR1A to be used as PWM output. 5.14.1.2 Definitions The following definitions are used extensively throughout the section: Table 5-52. General Counter Definitions Parameter Definition BOTTOM The counter reaches the BOTTOM when it becomes 0x0000. MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 register. The assignment is dependent of the mode of operation. 5.14.2 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR(R) CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-bit registers does not involve using the temporary register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 115 The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 registers. Note that when using "C", the compiler handles the 16-bit access. Assembly Code Examples(1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Examples(1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ... Note: 1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". The assembly code example returns the TCNT1 value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. 116 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 The following code examples show how to do an atomic read of the TCNT1 register contents. Reading any of the OCR1A/B or ICR1 registers can be done by using the same principle. Assembly Code Example(1) TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 117 The following code examples show how to do an atomic write of the TCNT1 register contents. Writing any of the OCR1A/B or ICR1 registers can be done by using the same principle. Assembly Code Example(1) TIM16_WriteTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNT1(unsigned int i) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; } Note: 1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1. 5.14.2.1 Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. 5.14.3 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS12:0) bits located in the Timer/Counter control register B (TCCR1B). For details on clock sources and prescaler (see Section 5.13 "Timer/Counter0 and Timer/Counter1 Prescalers" on page 112). 118 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.14.4 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 5-41 shows a block diagram of the counter and its surroundings. Figure 5-41. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int. Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) TCNTnH (16-bit Counter) Clear Control Logic clkTn Edge Detector Tn Direction (From Prescaler) TOP BOTTOM Signal description (internal signals): Count Increment or decrement TCNT1 by 1. Direction Select between increment and decrement. Clear Clear TCNT1 (set all bits to zero). clkT1 Timer/Counter clock. TOP Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper eight bits of the counter, and counter low (TCNT1L) containing the lower eight bits. The TCNT1H register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1 register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the clock select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the waveform generation mode bits (WGM13:0) located in the Timer/Counter control registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs OC1x. For more details about advanced counting sequences and waveform generation (see Section 5.14.8 "Modes of Operation" on page 124). The Timer/Counter overflow flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 5.14.5 Input Capture Unit The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The input capture unit is illustrated by the block diagram shown in Figure 5-42 on page 120. The elements of the block diagram that are not directly a part of the input capture unit are gray shaded. The small "n" in register and bit names indicates the Timer/Counter number. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 119 Figure 5-42. Input Capture Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) WRITE + - ACO* Analog Comparator TCNTnL (8-bit) TCNTn (16-bit Counter) ACIC* ICNCn ICESn Noise Canceler Edge Detector ICFn (Int. Req.) ICPn When a change of the logic level (an event) occurs on the input capture pin (ICP1), alternatively on the analog comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the input capture register (ICR1). The input capture flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 register. If enabled (ICIE1 = 1), the input capture flag generates an input capture interrupt. The ICF1 flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the input capture register (ICR1) is done by first reading the low byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP register. The ICR1 register can only be written when using a waveform generation mode that utilizes the ICR1 register for defining the counter's TOP value. In these cases the waveform generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 register. When writing the ICR1 register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to Section 5.14.2 "Accessing 16-bit Registers" on page 115. 5.14.5.1 Input Capture Trigger Source The main trigger source for the input capture unit is the input capture pin (ICP1). Timer/Counter1 can alternatively use the analog comparator output as trigger source for the input capture unit. The analog comparator is selected as trigger source by setting the analog comparator input capture (ACIC) bit in the analog comparator control and status register (ACSR). Be aware that changing trigger source can trigger a capture. The input capture flag must therefore be cleared after the change. Both the input capture pin (ICP1) and the analog comparator output (ACO) inputs are sampled using the same technique as for the T1 pin (see Figure 5-38 on page 112). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a waveform generation mode that uses ICR1 to define TOP. An input capture can be triggered by software by controlling the port of the ICP1 pin. 120 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.14.5.2 Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the input capture noise canceler (ICNC1) bit in Timer/Counter control register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICR1 register. The noise canceler uses the system clock and is therefore not affected by the prescaler. 5.14.5.3 Using the Input Capture Unit The main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICR1 register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the input capture interrupt, the ICR1 register should be read as early in the interrupt handler routine as possible. Even though the input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the input capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal's duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 register has been read. After a change of the edge, the input capture flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 flag is not required (if an interrupt handler is used). 5.14.6 Output Compare Units The 16-bit comparator continuously compares TCNT1 with the output compare register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the output compare flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the output compare flag generates an output compare interrupt. The OCF1x flag is automatically cleared when the interrupt is executed. Alternatively the OCF1x flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the waveform generation mode (WGM13:0) bits and compare output mode (COM1x1:0) bits. The TOP and BOTTOM signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see Section 5.14.8 "Modes of Operation" on page 124). A special feature of output compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the waveform generator. Figure 5-43 on page 122 shows a block diagram of the output compare unit. The small "n" in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the "x" indicates output compare unit (A/B). The elements of the block diagram that are not directly a part of the output compare unit are gray shaded. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 121 Figure 5-43. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator) OCFnx (Int. Req.) TOP Waveform Generator OCnx BOTTOM WGMn3:0 COMnx1:0 The OCR1x register is double buffered when using any of the twelve pulse width modulation (PWM) modes. For the normal and clear timer on compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x compare register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x buffer register, and if double buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x (buffer or compare) register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 register). Therefore OCR1x is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCR1x registers must be done via the TEMP register since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP register will be updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x compare register in the same system clock cycle. For more information of how to access the 16-bit registers refer to Section 5.14.2 "Accessing 16-bit Registers" on page 115. 5.14.6.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (FOC1x) bit. Forcing compare match will not set the OCF1x flag or reload/clear the timer, but the OC1x pin will be updated as if a real compare match had occurred (the COM11:0 bits settings define whether the OC1x pin is set, cleared or toggled). 5.14.6.2 Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled. 122 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.14.6.3 Using the Output Compare Unit Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT1 when using any of the output compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting. The setup of the OC1x should be performed before setting the data direction register for the port pin to output. The easiest way of setting the OC1x value is to use the force output compare (FOC1x) strobe bits in normal mode. The OC1x register keeps its value even when changing between waveform generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 5.14.7 Compare Match Output Unit The compare output mode (COM1x1:0) bits have two functions. The waveform generator uses the COM1x1:0 bits for defining the output compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 5-44 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x register, not the OC1x pin. If a system reset occur, the OC1x register is reset to "0". Figure 5-44. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx Pin OCnx 0 DATA BUS D Q PORT D clkI/O Q DDR The general I/O port function is overridden by the output compare (OC1x) from the waveform generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the data direction register (DDR) for the port pin. The data direction register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function is generally independent of the waveform generation mode, but there are some exceptions. Refer to Table 5-53 on page 132, Table 5-54 on page 132 and Table 5-55 on page 133 for details. The design of the output compare pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation (see Section 5.14.10 "16-bit Timer/Counter Register Description" on page 132). The COM1x1:0 bits have no effect on the input capture unit. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 123 5.14.7.1 Compare Output Mode and Waveform Generation The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the waveform generator that no action on the OC1x register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 5-53 on page 132. For fast PWM mode refer to Table 5-54 on page 132, and for phase correct and phase and frequency correct PWM refer to Table 5-55 on page 133. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. 5.14.8 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the waveform generation mode (WGM13:0) and compare output mode (COM1x1:0) bits. The compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or toggle at a compare match (see Section 5.14.7 "Compare Match Output Unit" on page 123). For detailed timing information refer to Section 5.14.9 "Timer/Counter Timing Diagrams" on page 130. 5.14.8.1 Normal Mode The simplest mode of operation is the normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter overflow flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1 flag, the timer resolution can be increased by software. There are no special cases to consider in the normal mode, a new counter value can be written anytime. The input capture unit is easy to use in normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The output compare units can be used to generate interrupts at some given time. Using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the CPU time. 5.14.8.2 Clear Timer on Compare Match (CTC) Mode In clear timer on compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 5-45. The counter value (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 5-45. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period 124 (COMnA1:0 = 1) 1 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered. For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined by the following equation: f clk_I/O f OCnA = ----------------------------------------------------2 x N x ( 1 + OCRnA ) The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the normal mode of operation, the TOV1 flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. 5.14.8.3 Fast PWM Mode The fast pulse width modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting compare output mode, the output compare (OC1x) is set on the compare match between TCNT1 and OCR1x, and cleared at TOP. In inverting compare output mode output is cleared on compare match and set at TOP. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: log ( TOP + 1 ) R FPWM = --------------------------------log ( 2 ) In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 5-46 on page 126. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 125 Figure 5-46. Fast PWM Mode, Timing Diagram OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 The Timer/Counter overflow flag (TOV1) is set each time the counter reaches TOP. In addition the OC1A or ICF1 flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the compare registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x registers are written. The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR1A register however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A buffer register. The OCR1A compare register will then be updated with the value in the buffer register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 flag is set. Using the ICR1 register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (see Table 5-53 on page 132). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x register at the compare match between OCR1x and TCNT1, and clearing (or setting) the OC1x register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = -----------------------------------N x ( 1 + TOP ) The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COM1x1:0 bits). 126 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). This applies only if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. 5.14.8.4 Phase Correct PWM Mode The phase correct pulse width modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting compare output mode, the output compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the compare match while downcounting. In inverting output compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: log ( TOP + 1 ) R PCPWM = --------------------------------log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 5-47. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 5-47. Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 127 The Timer/Counter overflow flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag is set accordingly at the same timer clock cycle as the OCR1x registers are updated with the double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the compare registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR1x registers are written. As the third period shown in Figure 5-47 on page 127 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x register at compare match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = ------------------------------2 x N x TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 5.14.8.5 Phase and Frequency Correct PWM Mode The phase and frequency correct pulse width modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting compare output mode, the output compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the compare match while downcounting. In inverting compare output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCR1x register is updated by the OCR1x buffer register (see Figure 5-47 on page 127 and Figure 5-48 on page 129). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: log ( TOP + 1 ) R PFCPWM = --------------------------------log ( 2 ) 128 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 5-48. The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 5-48. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/ TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter overflow flag (TOV1) is set at the same timer clock cycle as the OCR1x registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag set when TCNT1 has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the compare registers, a compare match will never occur between the TCNT1 and the OCR1x. As Figure 5-48 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCR1x registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Using the ICR1 register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (see Table 5-55 on page 133). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x register at compare match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: f clk_I/O f OCnxPFCPWM = ------------------------------2 x N x TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 129 The extreme values for the OCR1x register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 5.14.9 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCR1x register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 5-49 shows a timing diagram for the setting of OCF1x. Figure 5-49. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling clkI/O clkTn (clkI/O/1) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 5-50 shows the same timing data, but with the prescaler enabled. Figure 5-50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn OCRnx - 1 OCRnx OCFnx 130 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 OCRnx OCRnx + 1 OCRnx Value OCRnx + 2 Figure 5-51 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at BOTTOM. Figure 5-51. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O/1) TCNTn (CTC and FPWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value Figure 5-52 shows the same timing data, but with the prescaler enabled. Figure 5-52. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 131 5.14.10 16-bit Timer/Counter Register Description 5.14.10.1 Timer/Counter1 Control Register A - TCCR1A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1A * Bit 7:6 - COM1A1:0: Compare Output Mode for Channel A * Bit 5:4 - COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the output compare pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits setting. Table 5-53 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). Table 5-53. Compare Output Mode, non-PWM COM1A1/COM1B1 COM1A0/COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 Toggle OC1A/OC1B on compare match. 1 0 Clear OC1A/OC1B on compare match (set output to low level). 1 1 Set OC1A/OC1B on compare match (set output to high level). Table 5-54 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 5-54. Compare Output Mode, Fast PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 14 or 15: Toggle OC1A on compare match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OC1A/OC1B on compare match, set OC1A/OC1B at TOP Note: 132 Description 1 1 Set OC1A/OC1B on compare match, clear OC1A/OC1B at TOP 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See Section 5.14.8.3 "Fast PWM Mode" on page 125 for more details. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Table 5-55 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 5-55. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 8, 9, 10 or 11: Toggle OC1A on compare match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OC1A/OC1B on compare match when up-counting. Set OC1A/OC1B on compare match when downcounting. Set OC1A/OC1B on compare match when up-counting. Clear OC1A/OC1B on compare match when downcounting. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See Section 5.14.8.4 "Phase Correct PWM Mode" on page 127 for more details. 1 Note: 1. Description 1 * Bit 1:0 - WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used (see Table 5-56 on page 133). Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), clear timer on compare match (CTC) mode, and three types of pulse width modulation (PWM) modes (see Section 5.14.8 "Modes of Operation" on page 124). Table 5-56. Waveform Generation Mode Bit Description(1) Mode WGM13 WGM12 (CTC1) WGM11 WGM10 Timer/Counter Mode of (PWM11) (PWM10) Operation TOP Update of OCR1x at TOV1 Flag Set on 0 0 0 0 0 Normal 0xFFFF Immediate MAX 1 0 0 0 1 PWM, phase correct, 8-bit 0x00FF TOP BOTTOM 2 0 0 1 0 PWM, phase correct, 9-bit 0x01FF TOP BOTTOM 3 0 4 0 0 1 1 PWM, phase correct, 10-bit 0x03FF TOP BOTTOM 1 0 0 CTC OCR1A Immediate MAX 5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP 6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP 7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP TOP BOTTOM BOTTOM 8 1 0 0 0 PWM, phase and frequency ICR1 correct 9 1 0 0 1 PWM, phase and frequency OCR1A correct BOTTOM BOTTOM 10 1 0 1 0 PWM, phase correct ICR1 TOP BOTTOM 11 1 0 1 1 PWM, phase correct OCR1A TOP BOTTOM 12 1 1 0 0 CTC ICR1 Immediate MAX 13 1 1 0 1 (Reserved) - - - 14 1 1 1 0 Fast PWM ICR1 TOP TOP 15 Note: 1. 1 1 1 1 Fast PWM OCR1A TOP TOP The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 133 5.14.10.2 Timer/Counter1 Control Register B - TCCR1B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1B * Bit 7 - ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the input capture noise canceler. When the noise canceler is activated, the input from the input capture pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. * Bit 6 - ICES1: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the input capture register (ICR1). The event will also set the input capture flag (ICF1), and this can be used to cause an input capture interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B register), the ICP1 is disconnected and consequently the input capture function is disabled. * Bit 5 - Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. * Bit 4:3 - WGM13:2: Waveform Generation Mode See TCCR1A register description. * Bit 2:0 - CS12:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see Figure 5-49 on page 130 and Figure 5-50 on page 130. Table 5-57. Clock Select Bit Description CS12 CS11 CS10 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/1 (no prescaling) 0 1 0 clkI/O/8 (from prescaler) 0 1 1 clkI/O/64 (from prescaler) 1 0 0 clkI/O/256 (from prescaler) 1 0 1 clkI/O/1024 (from prescaler) 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 134 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.14.10.3 Timer/Counter1 Control Register C - TCCR1C Bit 7 6 5 4 3 2 1 0 FOC1A FOC1B - - - - - - Read/Write R/W R/W R R R R R R Initial Value 0 0 0 0 0 0 0 0 TCCR1C * Bit 7 - FOC1A: Force Output Compare for Channel A * Bit 6 - FOC1B: Force Output Compare for Channel B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 5.14.10.4 Timer/Counter1 - TCNT1H and TCNT1L Bit 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers see Section 5.14.2 "Accessing 16-bit Registers" on page 115. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCR1x registers. Writing to the TCNT1 register blocks (removes) the compare match on the following timer clock for all compare units. 5.14.10.5 Output Compare Register 1 A - OCR1AH and OCR1AL Bit 7 6 5 4 3 2 1 0 OCR1A[15:8] OCR1AH OCR1A[7:0] OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 2 1 0 5.14.10.6 Output Compare Register 1 B - OCR1BH and OCR1BL Bit 7 6 5 4 3 OCR1B[15:8] OCR1BH OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 135 The output compare registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC1x pin. The output compare registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers (see Section 5.14.2 "Accessing 16-bit Registers" on page 115). 5.14.10.7 Input Capture Register 1 - ICR1H and ICR1L Bit 7 6 5 4 3 2 1 0 ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The input capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the analog comparator output for Timer/Counter1). The input capture can be used for defining the counter TOP value. The input capture register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers (see Section 5.14.2 "Accessing 16-bit Registers" on page 115). 5.14.10.8 Timer/Counter1 Interrupt Mask Register - TIMSK1 Bit 7 6 5 Read/Write Initial Value 0 4 3 2 1 0 - - ICIE1 R R R/W - - OCIE1B OCIE1A TOIE1 R R R/W R/W R/W 0 0 0 0 0 0 0 TIMSK1 * Bit 7, 6 - Res: Reserved Bits These bits are unused bits in the Atmel(R) ATA6612C/ATA6613C, and will always read as zero. * Bit 5 - ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the status register is set (interrupts globally enabled), the Timer/Counter1 input capture interrupt is enabled. The corresponding interrupt vector (see Section 5.9 "Interrupts" on page 70) is executed when the ICF1 flag, located in TIFR1, is set. * Bit 4, 3 - Res: Reserved Bits These bits are unused bits in the Atmel ATA6612C/ATA6613C, and will always read as zero. * Bit 2 - OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the status register is set (interrupts globally enabled), the Timer/Counter1 output compare B match interrupt is enabled. The corresponding interrupt vector (see Section 5.9 "Interrupts" on page 70) is executed when the OCF1B flag, located in TIFR1, is set. * Bit 1 - OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the status register is set (interrupts globally enabled), the Timer/Counter1 output compare A match interrupt is enabled. The corresponding interrupt vector (see Section 5.9 "Interrupts" on page 70) is executed when the OCF1A flag, located in TIFR1, is set. * Bit 0 - TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the status register is set (interrupts globally enabled), the Timer/Counter1 overflow interrupt is enabled. The corresponding interrupt vector (see Section 5.8.9 "Watchdog Timer" on page 66) is executed when the TOV1 flag, located in TIFR1, is set. 136 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.14.10.9 Timer/Counter1 Interrupt Flag Register - TIFR1 Bit 7 6 5 4 3 2 1 0 - - ICF1 - - OCF1B OCF1A TOV1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR1 * Bit 7, 6 - Res: Reserved Bits These bits are unused bits in the Atmel(R) ATA6612C/ATA6613C, and will always read as zero. * Bit 5 - ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the input capture register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the input capture interrupt vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. * Bit 4, 3 - Res: Reserved Bits These bits are unused bits in the Atmel ATA6612C/ATA6613C, and will always read as zero. * Bit 2 - OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the output compare register B (OCR1B). Note that a forced output compare (FOC1B) strobe will not set the OCF1B flag. OCF1B is automatically cleared when the output compare match B interrupt vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. * Bit 1 - OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the output compare register A (OCR1A). Note that a forced output compare (FOC1A) strobe will not set the OCF1A flag. OCF1A is automatically cleared when the output compare match A interrupt vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. * Bit 0 - TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGM13:0 bits setting. In normal and CTC modes, the TOV1 flag is set when the timer overflows. Refer to Table 5-56 on page 133 for the TOV1 flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 overflow interrupt vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 5.15 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: Single channel counter Clear timer on compare match (auto reload) Glitch-free, phase correct pulse width modulator (PWM) Frequency generator 10-bit clock prescaler Overflow and compare match interrupt sources (TOV2, OCF2A and OCF2B) Allows clocking from external 32kHz watch crystal independent of the I/O clock ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 137 5.15.1 Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 5-53. The device-specific I/O register and bit locations are listed in the Section 5.15.8 "8-bit Timer/Counter Register Description" on page 148. The PRTIM2 bit in Section 5.7.7.1 "Power Reduction Register - PRR" on page 58 must be written to zero to enable Timer/Counter2 module. Figure 5-53. 8-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int. Req.) Control Logic clkTn TOSC1 T/C Oscillator Prescaler TOP TOSC2 BOTTOM clkI/O Timer/Counter TCNTn = = 0 OCnA (Int. Req.) Waveform Generation = OCnA DATA BUS OCRnA Fixed TOP Value Waveform Generation = OCRnB TCCRnA 138 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 OCnB (Int. Req.) TCCRnB OCnB 5.15.1.1 Registers The Timer/Counter (TCNT2) and output compare register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the timer interrupt flag register (TIFR2). All interrupts are individually masked with the timer interrupt mask register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the asynchronous status register (ASSR). The clock select logic block controls which clock source he Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT2). The double buffered output compare register (OCR2A and OCR2B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the output compare pins (OC2A and OC2B). See Section 5.15.4 "Output Compare Unit" on page 140 for details. The compare match event will also set the compare flag (OCF2A or OCF2B) which can be used to generate an output compare interrupt request. 5.15.1.2 Definitions Many register and bit references in this document are written in general form. A lower case "n" replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2 counter value and so on. The definitions below are also used extensively throughout the section. Table 5-58. Definitions Parameter Definition BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2A register. The assignment is dependent on the mode of operation. 5.15.2 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR register is written to logic one, the clock source is taken from the Timer/Counter oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation (see Section 5.15.9.2 "Asynchronous Status Register - ASSR" on page 154). For details on clock sources and prescaler, see Section 5.15.10 "Timer/Counter Prescaler" on page 155. 5.15.3 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 5-54 shows a block diagram of the counter and its surrounding environment. Figure 5-54. Counter Unit Block Diagram TOVn (Int. Req.) DATA BUS TOSC1 T/C Oscillator Count TCNTn Clear Control Logic clkTn Prescaler TOSC2 Direction clkI/O Bottom Top ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 139 Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT2 in the following. top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter control register (TCCR2A) and the WGM22 located in the Timer/Counter control register B (TCCR2B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs OC2A and OC2B. For more details about advanced counting sequences and waveform generation (see Section 5.15.6 "Modes of Operation" on page 142). The Timer/Counter overflow flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt. 5.15.4 Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the output compare register (OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the output compare flag (OCF2A or OCF2B) at the next timer clock cycle. If the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. The output compare flag is automatically cleared when the interrupt is executed. Alternatively, the output compare flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the WGM22:0 bits and compare output mode (COM2x1:0) bits. The max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see Section 5.15.6 "Modes of Operation" on page 142). Figure 5-55 shows a block diagram of the output compare unit. Figure 5-55. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator) OCFnx (Int. Req.) Top Bottom Waveform Generator FOCn WGMn1:0 140 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 COMnX1:0 OCnx The OCR2x register is double buffered when using any of the pulse width modulation (PWM) modes. For the normal and clear timer on compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2x compare register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2x register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2x buffer register, and if double buffering is disabled the CPU will access the OCR2x directly. 5.15.4.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (FOC2x) bit. Forcing compare match will not set the OCF2x flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or toggled). 5.15.4.2 Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 5.15.4.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the output compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The setup of the OC2x should be performed before setting the data direction register for the port pin to output. The easiest way of setting the OC2x value is to use the force output compare (FOC2x) strobe bit in normal mode. The OC2x register keeps its value even when changing between waveform generation modes. Be aware that the COM2x1:0 bits are not double buffered together with the compare value. Changing the COM2x1:0 bits will take effect immediately. 5.15.5 Compare Match Output Unit The compare output mode (COM2x1:0) bits have two functions. The waveform generator uses the COM2x1:0 bits for defining the output compare (OC2x) state at the next compare match. Also, the COM2x1:0 bits control the OC2x pin output source. Figure 5-56 on page 142 shows a simplified schematic of the logic affected by the COM2x1:0 bit setting. The I/O registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the OC2x state, the reference is for the internal OC2x register, not the OC2x pin. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 141 Figure 5-56. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx Pin OCnx 0 DATA BUS D Q PORT D clkI/O Q DDR The general I/O port function is overridden by the output compare (OC2x) from the waveform generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output) is still controlled by the data direction register (DDR) for the port pin. The data direction register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visible on the pin. The port override function is independent of the waveform generation mode. The design of the output compare pin logic allows initialization of the OC2x state before the output is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of operation (see Section 5.15.8 "8-bit Timer/Counter Register Description" on page 148). 5.15.5.1 Compare Output Mode and Waveform Generation The waveform generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1:0 = 0 tells the waveform generator that no action on the OC2x register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 5-62 on page 149. For fast PWM mode, refer to Table 5-63 on page 149, and for phase correct PWM refer to Table 5-64 on page 149. A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2x strobe bits. 5.15.6 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the waveform generation mode (WGM22:0) and compare output mode (COM2x1:0) bits. The compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare match (see Section 5.15.5 "Compare Match Output Unit" on page 141). For detailed timing information refer to Section 5.15.7 "Timer/Counter Timing Diagrams" on page 146. 142 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.15.6.1 Normal Mode The simplest mode of operation is the normal mode (WGM22:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter overflow flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 flag, the timer resolution can be increased by software. There are no special cases to consider in the normal mode, a new counter value can be written anytime. The output compare unit can be used to generate interrupts at some given time. Using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the CPU time. 5.15.6.2 Clear Timer on Compare Match (CTC) Mode In clear timer on compare or CTC mode (WGM22:0 = 2), the OCR2A register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 5-57. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Figure 5-57. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCnx (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2A is lower than the current value of TCNT2, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = ---------------------------------------------------2 x N x ( 1 + OCRnx ) The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the normal mode of operation, the TOV2 flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 143 5.15.6.3 Fast PWM Mode The fast pulse width modulation or fast PWM mode (WGM22:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In non-inverting compare output mode, the output compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x, and set at BOTTOM. In inverting compare output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 5-58 on page 144. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. Figure 5-58. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter overflow flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (see Table 5-60 on page 148). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2x register at the compare match between OCR2x and TCNT2, and clearing (or setting) the OC2x register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = ------------------N x 256 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0 bits.) 144 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. 5.15.6.4 Phase Correct PWM Mode The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In non-inverting compare output mode, the output compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x while upcounting, and set on the compare match while downcounting. In inverting output compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 5-59. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. Figure 5-59. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter overflow flag (TOV2) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 145 In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (see Table 5-61 on page 148). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2x register at the compare match between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x register at compare match between OCR2x and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = ------------------N x 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 5-59 on page 145 OCnx has a transition from high to low even though there is no compare match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without compare match. OCR2A changes its value from MAX, like in Figure 5-59 on page 145. When the OCR2A value is MAX the OCn pin value is the same as the result of a down-counting compare match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting compare match. The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the compare match and hence the OCn change that would have happened on the way up. 5.15.7 Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter oscillator clock. The figures include information on when interrupt flags are set. Figure 5-60 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 5-60. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O/1) TCNTn MAX - 1 TOVn 146 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 MAX BOTTOM BOTTOM + 1 Figure 5-61 shows the same timing data, but with the prescaler enabled. Figure 5-61. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 5-62 shows the setting of OCF2A in all modes except CTC mode. Figure 5-62. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 5-63 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 5-63. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC) OCRnx TOP - 1 TOP BOTTOM BOTTOM + 1 TOP OCFnx ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 147 5.15.8 8-bit Timer/Counter Register Description 5.15.8.1 Timer/Counter Control Register A - TCCR2A Bit 7 6 5 4 COM2A1 COM2A0 COM2B1 COM2B0 3 2 1 0 - - WGM21 WGM20 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR2A * Bits 7:6 - COM2A1:0: Compare Match Output A Mode These bits control the output compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR) bit corresponding to the OC2A pin must be set in order to enable the output driver. When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting. Table 5-59 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Table 5-59. Compare Output Mode, non-PWM Mode COM2A1 COM2A0 Description 0 0 Normal port operation, OC0A disconnected. 0 1 Toggle OC2A on compare match 1 0 Clear OC2A on compare match 1 1 Set OC2A on compare match Table 5-60 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 5-60. Compare Output Mode, Fast PWM Mode(1) COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal port operation, OC0A disconnected. WGM22 = 1: Toggle OC2A on compare match. 1 0 Clear OC2A on compare match, set OC2A at TOP Note: 1 1. Description 1 Set OC2A on compare match, clear OC2A at TOP A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See Section 5.15.6.3 "Fast PWM Mode" on page 144 for more details. Table 5-61 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Table 5-61. Compare Output Mode, Phase Correct PWM Mode() COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal port operation, OC2A disconnected. WGM22 = 1: Toggle OC2A on compare match. 1 0 Clear OC2A on compare match when up-counting. Set OC2A on compare match when down-counting. 1 Note: 148 1. Description Set OC2A on compare match when up-counting. Clear OC2A on compare match when down-counting. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See Section 5.15.6.4 "Phase Correct PWM Mode" on page 145 for more details. 1 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 * Bits 5:4 - COM2B1:0: Compare Match Output B Mode These bits control the output compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR) bit corresponding to the OC2B pin must be set in order to enable the output driver. When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the WGM22:0 bit setting. Table 5-62 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Table 5-62. Compare Output Mode, non-PWM Mode COM2B1 COM2B0 0 0 Description Normal port operation, OC2B disconnected. 0 1 Toggle OC2B on compare match 1 0 Clear OC2B on compare match 1 1 Set OC2B on compare match Table 5-63 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM mode. Table 5-63. Compare Output Mode, Fast PWM Mode(1) COM2B1 COM2B0 0 0 Normal port operation, OC2B disconnected. 0 1 Reserved 1 0 Clear OC2B on compare match, set OC2B at TOP Note: 1 1. Description 1 Set OC2B on compare match, clear OC2B at TOP A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See Section 5.15.6.4 "Phase Correct PWM Mode" on page 145 for more details. Table 5-64 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Table 5-64. Compare Output Mode, Phase Correct PWM Mode(1) COM2B1 COM2B0 0 0 Normal port operation, OC2B disconnected. 0 1 Reserved 1 0 Clear OC2B on compare match when up-counting. Set OC2B on compare match when down-counting. 1 Note: 1. Description Set OC2B on compare match when up-counting. Clear OC2B on compare match when down-counting. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See Section 5.15.6.4 "Phase Correct PWM Mode" on page 145 for more details. 1 * Bits 3, 2 - Res: Reserved Bits These bits are reserved bits in the Atmel(R) ATA6612C/ATA6613C and will always read as zero. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 149 * Bits 1:0 - WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 5-65. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), clear timer on compare match (CTC) mode, and two types of pulse width modulation (PWM) modes (see Section 5.15.6 "Modes of Operation" on page 142). Table 5-65. Waveform Generation Mode Bit Description Timer/Counter Mode of Operation TOP Update of OCRx at TOV Flag Set on(1)(2) 0 Normal 0xFF Immediate MAX 0 1 PWM, phase correct 0xFF TOP BOTTOM 0 1 0 CTC OCRA Immediate MAX 3 0 1 1 Fast PWM 0xFF TOP MAX 4 1 0 0 Reserved - - - 5 1 0 1 PWM, phase correct OCRA TOP BOTTOM 6 1 1 0 Reserved - - - 1 1 Fast PWM OCRA TOP TOP Mode WGM2 WGM1 WGM0 0 0 0 1 0 2 7 Notes: 1. 1 MAX = 0xFF 2. BOTTOM = 0x00 5.15.8.2 Timer/Counter Control Register B - TCCR2B Bit 7 6 5 4 3 2 1 0 FOC2A FOC2B - - WGM22 CS22 CS21 CS20 Read/Write W W R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR2B * Bit 7 - FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate compare match is forced on the waveform generation unit. The OC2A output is changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the value present in the COM2A1:0 bits that determines the effect of the forced compare. A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2A as TOP. The FOC2A bit is always read as zero. * Bit 6 - FOC2B: Force Output Compare B The FOC2B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B bit, an immediate compare match is forced on the waveform generation unit. The OC2B output is changed according to its COM2B1:0 bits setting. Note that the FOC2B bit is implemented as a strobe. Therefore it is the value present in the COM2B1:0 bits that determines the effect of the forced compare. A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2B as TOP. The FOC2B bit is always read as zero. 150 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 * Bits 5:4 - Res: Reserved Bits These bits are reserved bits in the Atmel(R) ATA6612C/ATA6613C and will always read as zero. * Bit 3 - WGM22: Waveform Generation Mode See the description in Section 5.15.8.1 "Timer/Counter Control Register A - TCCR2A" on page 148. * Bit 2:0 - CS22:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter (see Table 5-66). Table 5-66. Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkT2S/(no prescaling) 0 1 0 clkT2S/8 (from prescaler) 0 1 1 clkT2S/32 (from prescaler) 1 0 0 clkT2S/64 (from prescaler) 1 0 1 clkT2S/128 (from prescaler) 1 1 0 clkT2S/256 (from prescaler) 1 1 1 clkT2S/1024 (from prescaler) If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 5.15.8.3 Timer/Counter Register - TCNT2 Bit 7 6 5 4 3 2 1 0 TCNT2[7:0] TCNT2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a compare match between TCNT2 and the OCR2x registers. 5.15.8.4 Output Compare Register A - OCR2A Bit 7 6 5 4 3 2 1 0 OCR2A[7:0] OCR2A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The output compare register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2A pin. 5.15.8.5 Output Compare Register B - OCR2B Bit 7 6 5 4 3 2 1 0 OCR2B[7:0] OCR2B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The output compare register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2B pin. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 151 5.15.8.6 Timer/Counter2 Interrupt Mask Register - TIMSK2 Bit 7 6 5 4 3 2 1 0 - - - - - OCIE2B OCIE2A TOIE2 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK2 * Bit 2 - OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the status register is set (one), the Timer/Counter2 compare match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Counter 2 interrupt flag register - TIFR2. * Bit 1 - OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I-bit in the status register is set (one), the Timer/Counter2 compare match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Counter 2 interrupt flag register - TIFR2. * Bit 0 - TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the status register is set (one), the Timer/Counter2 overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 interrupt flag register - TIFR2. 5.15.8.7 Timer/Counter2 Interrupt Flag Register - TIFR2 Bit 7 6 5 4 3 2 1 0 - - - Read/Write R R R - - OCF2B OCF2A TOV2 R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR2 * Bit 2 - OCF2B: Output Compare Flag 2 B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B - Output compare register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 compare match interrupt enable), and OCF2B are set (one), the Timer/Counter2 compare match interrupt is executed. * Bit 1 - OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A - Output compare register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 compare match interrupt enable), and OCF2A are set (one), the Timer/Counter2 compare match interrupt is executed. * Bit 0 - TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 overflow interrupt enable), and TOV2 are set (one), the Timer/Counter2 overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 152 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.15.9 Asynchronous Operation of the Timer/Counter 5.15.9.1 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2. b. Select clock source by setting AS2 as appropriate. c. Write new values to TCNT2, OCR2x, and TCCR2x. d. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB. e. Clear the Timer/Counter2 interrupt flags. f. Enable interrupts, if needed. The CPU main clock frequency must be more than four times the oscillator frequency. When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the five mentioned registers have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2x write in progress. To detect that a transfer to the destination register has taken place, the asynchronous status register - ASSR has been implemented. When entering power-save or ADC noise reduction mode after having written to TCNT2, OCR2x, or TCCR2x, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if any of the output compare2 interrupt is used to wake up the device, since the output compare function is disabled during writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the corresponding OCR2xUB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. If Timer/Counter2 is used to wake the device up from power-save or ADC noise reduction mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering power-save or ADC noise reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: a. Write a value to TCCR2x, TCNT2, or OCR2x. b. Wait until the corresponding update busy flag in ASSR returns to zero. c. Enter power-save or ADC noise reduction mode. When the asynchronous operation is selected, the 32.768kHz oscillator for Timer/Counter2 is always running, except in power-down and standby modes. After a power-up reset or wake-up from power-down or standby mode, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from power-down or standby mode. The contents of all Timer/Counter2 registers must be considered lost after a wake-up from power-down or standby mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use or a clock signal is applied to the TOSC1 pin. Description of wake up from power-save or ADC noise reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 153 Reading of the TCNT2 register shortly after wake-up from power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: a. Write any value to either of the registers OCR2x or TCCR2x. b. Wait for the corresponding update busy flag to be cleared. c. Read TCNT2. During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. The output compare pin is changed on the timer clock and is not synchronized to the processor clock. 5.15.9.2 Asynchronous Status Register - ASSR Bit 7 6 5 4 3 2 1 0 - EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 ASSR * Bit 6 - EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on timer oscillator 1 (TOSC1) pin instead of a 32kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal oscillator will only run when this bit is zero. * Bit 5 - AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal oscillator connected to the timer oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted. * Bit 4 - TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. * Bit 3 - OCR2AUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value. * Bit 2 - OCR2BUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value. * Bit 1 - TCR2AUB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value. 154 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 * Bit 0 - TCR2BUB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value. If a write is performed to any of the five Timer/Counter2 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 5.15.10 Timer/Counter Prescaler Figure 5-64. Prescaler for Timer/Counter2 clkT2S/1024 clkT2S/256 clkT2S/128 clkT2S/64 AS2 10-bit T/C Prescaler Clear clkT2S/32 TOSC1 clkT2S clkT2S/8 clkI/O PSRASY 0 CS20 CS21 CS22 Timer/Counter2 Clock Source clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a real time counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The oscillator is optimized for use with a 32.768kHz crystal. Applying an external clock source to TOSC1 is not recommended. For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a predictable prescaler. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 155 5.15.10.1 General Timer/Counter Control Register - GTCCR Bit 7 6 5 4 3 2 TSM - - - - - 1 0 Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 PSRASY PSRSYNC GTCCR * Bit 1 - PSRASY: Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the "Bit 7 - TSM: Timer/Counter Synchronization Mode" for a description of the Timer/Counter synchronization mode. 5.16 Serial Peripheral Interface - SPI The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the Atmel(R) ATA6612C/ATA6613C and peripheral devices or between several AVR(R) devices. The Atmel ATA6612C/ATA6613C SPI includes the following features: Full-duplex, three-wire synchronous data transfer Master or slave operation LSB first or MSB first data transfer Seven programmable bit rates End of transmission interrupt flag Write collision flag protection Wake-up from idle mode Double speed (CK/2) master SPI mode The USART can also be used in master SPI mode (see Section 5.18 "USART in SPI Mode" on page 186). The PRSPI bit in Section 5.7.7.1 "Power Reduction Register - PRR" on page 58 must be written to zero to enable SPI module. 156 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Figure 5-65. SPI Block Diagram(1) MISO S clkI/O MSB M M LSB 8-Bit Shift Register Read Data Buffer Pin Control Logic Divider /2/4/8/16/32/64/128 Clock SPI Clock (Master) SPR0 DORD SPR0 SPR1 CPHA CPOL SPI Control Register 8 SPI Interrupt Request MSTR SPIE SPI Status Register DORD SPI2X 8 SPE MSTR SPE WCOL SPIF SPE MSTR SPR1 SPI2X M SS SPI Control 1. SCK S Clock Logic Select Note: MOSI S 8 Internal Data Bus Refer to Table 5-32 on page 84 for SPI pin placement. The interconnection between master and slave CPUs with SPI is shown in Figure 5-66 on page 158. The system consists of two shift registers, and a master clock generator. The SPI master initiates the communication cycle when pulling low the slave select SS pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from master to slave on the master out - slave In, MOSI, line, and from slave to master on the master in - slave out, MISO, line. After each data packet, the master will synchronize the slave by pulling high the slave select, SS, line. When configured as a master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI data register starts the SPI clock generator, and the hardware shifts the eight bits into the slave. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR register is set, an interrupt is requested. The master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the slave select, SS line. The last incoming byte will be kept in the buffer register for later use. When configured as a slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI data register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of transmission flag, SPIF is set. If the SPI interrupt enable bit, SPIE, in the SPCR register is set, an interrupt is requested. The slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the buffer register for later use. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 157 Figure 5-66. SPI Master-slave Interconnection MSB MASTER LSB MISO MISO 8 Bit Shift Register SPI Clock Generator MSB SLAVE LSB 8 Bit Shift Register MOSI MOSI SCK SCK SS Shift Enable SS The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI data register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI data register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed fosc/4. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 5-67. For more details on automatic port overrides, refer to Section 5.10.3 "Alternate Port Functions" on page 81. Table 5-67. SPI Pin Overrides(1) Pin Direction, Master SPI Direction, Slave SPI MOSI User defined Input MISO Input User defined SCK User defined Input SS Note: 1. 158 User defined Input See Section 5.10.3.2 "Alternate Functions of Port B" on page 84 for a detailed description of how to define the direction of the user defined SPI pins. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 The following code examples show how to initialize the SPI as a master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual data direction register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) out SPCR,r17 ret SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; Wait for transmission complete sbis SPSR,SPIF rjmp Wait_Transmit ret C Code Example(1) void SPI_MasterInit(void) { /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void SPI_MasterTransmit(char cData) { /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; } Note: 1. The example code assumes that the part specific header file is included. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 159 The following code examples show how to initialize the SPI as a slave and how to perform a simple reception. Assembly Code Example(1) SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) out SPCR,r17 ret SPI_SlaveReceive: ; Wait for reception complete sbis SPSR,SPIF rjmp SPI_SlaveReceive ; Read received data and return in r16,SPDR ret C Code Example(1) void SPI_SlaveInit(void) { /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void) { /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; } Note: 1. The example code assumes that the part specific header file is included. 5.16.1 SS Pin Functionality 5.16.1.1 Slave Mode When the SPI is configured as a slave, the slave select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the shift register. 160 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.16.1.2 Master Mode When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the direction of the SS pin. If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically, the pin will be driving the SS pin of the SPI slave. If SS is configured as an input, it must be held high to ensure master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as a master with the SS pin defined as an input, the SPI system interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions: 1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the SPI becoming a slave, the MOSI and SCK pins become inputs. 2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt routine will be executed. Thus, when interrupt-driven SPI transmission is used in master mode, and there exists a possibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI master mode. 5.16.1.3 SPI Control Register - SPCR Bit 7 6 5 4 3 2 1 0 SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR * Bit 7 - SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the if the global interrupt enable bit in SREG is set. * Bit 6 - SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. * Bit 5 - DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. * Bit 4 - MSTR: Master/Slave Select This bit selects master SPI mode when written to one, and slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode. * Bit 3 - CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 5-67 on page 163 and Figure 5-68 on page 164 for an example. The CPOL functionality is summarized below: Table 5-68. CPOL Functionality CPOL Leading Edge Trailing Edge 0 Rising Falling 1 Falling Rising ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 161 * Bit 2 - CPHA: Clock Phase The settings of the clock phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to Figure 5-67 on page 163 and Figure 5-68 on page 164 for an example. The CPOL functionality is summarized below: Table 5-69. CPHA Functionality CPHA Leading Edge Trailing Edge 0 Sample Setup 1 Setup Sample * Bits 1, 0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the oscillator clock frequency fosc is shown in the following table: Table 5-70. Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 SPR0 SCK Frequency 0 0 0 fosc/4 0 0 1 fosc/16 0 1 0 fosc/64 0 1 1 fosc/128 1 0 0 fosc/2 1 0 1 fosc/8 1 1 0 fosc/32 1 1 1 fosc/64 5.16.1.4 SPI Status Register - SPSR Bit 7 6 5 4 3 2 1 0 SPIF WCOL - - - - - SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 SPSR * Bit 7 - SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register with SPIF set, then accessing the SPI data register (SPDR). * Bit 6 - WCOL: Write COLlision Flag The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI status register with WCOL set, and then accessing the SPI data register. * Bit 5..1 - Res: Reserved Bits These bits are reserved bits in the Atmel(R) ATA6612C/ATA6613C and will always read as zero. 162 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 * Bit 0 - SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK frequency) will be doubled when the SPI is in master mode (see Table 5-70 on page 162). This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as slave, the SPI is only guaranteed to work at fosc/4 or lower. The SPI interface on the Atmel(R) ATA6612C/ATA6613C is also used for program memory and EEPROM downloading or uploading. See Section 5.24.8 "Serial Downloading" on page 267 for serial programming and verification. 5.16.1.5 SPI Data Register - SPDR Bit 7 6 5 4 3 2 1 0 MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI data register is a read/write register used for data transfer between the register file and the SPI shift register. Writing to the register initiates data transmission. Reading the register causes the shift register receive buffer to be read. 5.16.2 Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 5-67 and Figure 5-68 on page 164. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 5-68 on page 161 and Table 5-69 on page 162, as done below. Table 5-71. CPOL Functionality Leading Edge Trailing eDge SPI Mode CPOL = 0, CPHA = 0 Sample (rising) Setup (falling) 0 CPOL = 0, CPHA = 1 Setup (rising) Sample (falling) 1 CPOL = 1, CPHA = 0 Sample (falling) Setup (rising) 2 CPOL = 1, CPHA = 1 Setup (falling) Sample (rising) 3 Figure 5-67. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) Mode 0 SCK (CPOL = 1) Mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD =1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 163 Figure 5-68. SPI Transfer Format with CPHA = 1 SCK (CPOL = 0) Mode 1 SCK (CPOL = 1) Mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD =1) 5.17 MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB USART0 The universal synchronous and asynchronous serial receiver and transmitter (USART) is a highly flexible serial communication device. The main features are: Full duplex operation (independent serial receive and transmit registers) Asynchronous or synchronous operation Master or slave clocked synchronous operation High resolution baud rate generator Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits Odd or even parity generation and parity check supported by hardware Data overrun detection Framing error detection Noise filtering includes false start bit detection and digital low pass filter Three separate interrupts on TX complete, TX data register empty and RX complete Multi-processor communication mode Double speed asynchronous communication mode The USART can also be used in master SPI mode (see Section 5.18 "USART in SPI Mode" on page 186. The power reduction USART bit, PRUSART0, in Section 5.7.7.1 "Power Reduction Register - PRR" on page 58 must be disabled by writing a logical zero to it. 164 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.17.1 Overview A simplified block diagram of the USART transmitter is shown in Figure 5-69. CPU accessible I/O registers and I/O pins are shown in bold. Figure 5-69. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC Baud Rate Generator Sync Logic Pin Control XCKn Transmitter TX Control DATA BUS UDRn (Transmit) Parity Generator 1. TxDn Receiver Clock Recovery RX Control Receive Shift Register Data Recovery Pin Control UDR (Receive) Parity Checker UCSRnA Note: Pin Control Transmit Shift Register UCSRnB RxDn UCSRnC Refer to Table 5-38 on page 89 for USART0 pin placement. The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock generator, transmitter and receiver. Control registers are shared by all units. The clock generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCKn (transfer clock) pin is only used by synchronous transfer mode. The transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames. The receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the receiver includes a parity checker, control logic, a shift register and a two level receive buffer (UDRn). The receiver supports the same frame formats as the transmitter, and can detect frame error, data overrun and parity errors. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 165 5.17.2 Clock Generation The clock generation logic generates the base clock for the transmitter and receiver. The USART supports four modes of clock operation: Normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode. The UMSELn bit in USART control and status register C (UCSRnC) selects between asynchronous and synchronous operation. Double speed (asynchronous mode only) is controlled by the U2Xn found in the UCSRnA register. When using synchronous mode (UMSELn = 1), the data direction register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (master mode) or external (slave mode). The XCKn pin is only active when using synchronous mode. Figure 5-70 shows a block diagram of the clock generation logic. Figure 5-70. Clock Generation Logic, Block Diagram UBRRn U2Xn foscn Prescaling Down-Counter UBRRn+1 /2 /4 /2 0 1 0 OSC DDR_XCKn xcki XCKn Pin Sync Register Edge Detector 0 UCPOLn txclk UMSELn 1 xcko DDR_XCKn 1 0 1 rxclk Signal description: txclk Transmitter clock (internal signal). rxclk Receiver base clock (internal signal). xcki Input from XCK pin (internal signal). Used for synchronous slave operation. xcko Clock output to XCK pin (internal signal). Used for synchronous master operation. fosc XTAL pin frequency (system clock). 5.17.2.1 Internal Clock Generation - The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section refers to Figure 5-70. The USART baud rate register (UBRRn) and the down-counter connected to it function as a programmable prescaler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRRn value each time the counter has counted down to zero or when the UBRRnL register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRRn+1)). The transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator output is used directly by the receiver's clock and data recovery units. However, the recovery units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSELn, U2Xn and DDR_XCKn bits. 166 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Table 5-72 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn value for each mode of operation using an internally generated clock source. Table 5-72. Equations for Calculating Baud Rate Register Setting Equation for Calculating Baud Rate(1) Operating Mode Asynchronous normal mode (U2Xn = 0) f OSC BAUD = --------------------------------------16 ( UBRRn + 1 ) Asynchronous double speed mode (U2Xn = 1) f OSC BAUD = -----------------------------------8 ( UBRRn + 1 ) Synchronous master mode f OSC BAUD = -----------------------------------2 ( UBRRn + 1 ) Note: 1. Equation for Calculating UBRRn Value f OSC UBRRn = ----------------------- - 1 16BAUD f OSC UBRRn = -------------------- - 1 8BAUD f OSC UBRRn = -------------------- - 1 2BAUD The baud rate is defined to be the transfer rate in bit per second (bps) BAUD Baud rate (in bits per second, bps) fOSC System Oscillator clock frequency UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095) Some examples of UBRRn values for some system clock frequencies are found in Table 5-80 on page 184 (see Section 5-80 "Examples of UBRRn Settings for Commonly Used Oscillator Frequencies" on page 184). 5.17.2.2 Double Speed Operation (U2Xn) The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation.Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. Note however that the receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. For the transmitter, there are no downsides. 5.17.2.3 External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 5-70 on page 166 for details. External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the transmitter and receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCKn clock frequency is limited by the following equation: f OSC f XCK < ----------4 Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 167 5.17.2.4 Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (slave) or clock output (master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxDn) is sampled at the opposite XCKn clock edge of the edge the data output (TxDn) is changed. Figure 5-71. Synchronous Mode XCKn Timing UCPOL = 1 XCK RxD/TxD Sample UCPOL = 0 XCK RxD/TxD Sample The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for data change. As Figure 5-71 shows, when UCPOLn is zero the data will be changed at rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed at falling XCKn edge and sampled at rising XCKn edge. 5.17.3 Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: 1 start bit 5, 6, 7, 8, or 9 data bits no, even or odd parity bit 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 5-72 illustrates the possible combinations of the frame formats. Bits inside brackets are optional. Figure 5-72. Frame Formats FRAME (IDLE) ST 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St/IDLE) St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line must be high. The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The receiver and transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. 168 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 The USART character size (UCSZn2:0) bits select the number of data bits in the frame. The USART parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART stop bit select (USBSn) bit. The Receiver ignores the second stop bit. An FE (frame error) will therefore only be detected in the cases where the first stop bit is zero. 5.17.3.1 Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted. The relation between the parity bit and data bits is as follows: P even = d n - 1 ... d 3 d 2 d 1 d 0 0 P odd = d n - 1 ... d 3 d 2 d 1 d 0 1 Peven odd Parity bit using even parity P Parity bit using odd parity dn Data bit n of the character If used, the parity bit is located between the last data bit and first stop bit of a serial frame. 5.17.4 USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the transmitter or the receiver depending on the usage. For interrupt driven USART operation, the global interrupt flag should be cleared (and interrupts globally disabled) when doing the initialization. Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXCn flag can be used to check that the transmitter has completed all transfers, and the RXC flag can be used to check that there are no unread data in the receive buffer. Note that the TXCn flag must be cleared before each transmission (before UDRn is written) if it is used for this purpose. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 169 The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. Assembly Code Example(1) USART_Init: ; Set baud rate out UBRRnH, r17 out UBRRnL, r16 ; Enable receiver and transmitter ldi r16, (1<<RXENn)|(1<<TXENn) out UCSRnB,r16 ; Set frame format: 8data, 2stop bit ldi r16, (1<<USBSn)|(3<<UCSZn0) out UCSRnC,r16 ret C Code Example(1) void USART_Init(unsigned int baud) { /* Set baud rate */ UBRRnH = (unsigned char)(baud>>8); UBRRnL = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRnB = (1<<RXENn)|(1<<TXENn); /* Set frame format: 8data, 2stop bit */ UCSRnC = (1<<USBSn)|(3<<UCSZn0); } Note: 1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". More advanced initialization routines can be made that include frame format as parameters, disable interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine, or be combined with initialization code for other I/O modules. 5.17.5 Data Transmission - The USART Transmitter The USART transmitter is enabled by setting the transmit enable (TXEN) bit in the UCSRnB register. When the transmitter is enabled, the normal port operation of the TxDn pin is overridden by the USART and given the function as the transmitter's serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If synchronous operation is used, the clock on the XCKn pin will be overridden and used as transmission clock. 5.17.5.1 Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the transmit buffer will be moved to the shift register when the shift register is ready to send a new frame. The shift register is loaded with new data if it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted. When the shift register is loaded with new data, it will transfer one complete frame at the rate given by the baud register, U2Xn bit or by XCKn depending on mode of operation. 170 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 The following code examples show a simple USART transmit function based on polling of the data register empty (UDREn) flag. When using frames with less than eight bits, the most significant bits written to the UDRn are ignored. The USART has to be initialized before the function can be used. For the assembly code, the data to be sent is assumed to be stored in register R16. Assembly Code Example(1) USART_Transmit: ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDRn,r16 ret C Code Example(1) void USART_Transmit (unsigned char data) { /* Wait for empty transmit buffer */ while (!(UCSRnA & (1<<UDREn))) ; /* Put data into buffer, sends the data */ UDRn = data; } Note: 1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". The function simply waits for the transmit buffer to be empty by checking the UDREn flag, before loading it with new data to be transmitted. If the data register empty interrupt is utilized, the interrupt routine writes the data into the buffer. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 171 5.17.5.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16. Assembly Code Example(1)(2) USART_Transmit: ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ; Copy 9th bit from r17 to TXB8 cbi UCSRnB,TXB8 sbrc r17,0 sbi UCSRnB,TXB8 ; Put LSB data (r16) into buffer, sends the data out UDRn,r16 ret C Code Example(1)(2) void USART_Transmit (unsigned int data) { /* Wait for empty transmit buffer */ while (!(UCSRnA & (1<<UDREn)))) ; /* Copy 9th bit to TXB8 */ UCSRnB &= ~(1<<TXB8); if (data & 0x0100) UCSRnB |= (1<<TXB8); /* Put data into buffer, sends the data */ UDRn = data; } Notes: 1. These transmit functions are written to be general functions. They can be optimized if the contents of the UCSRnB is static. For example, only the TXB8 bit of the UCSRnB register is used after initialization. 2. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". The ninth bit can be used for indicating an address frame when using multi processor communication mode or for other protocol handling as for example synchronization. 5.17.5.3 Transmitter Flags and Interrupts The USART transmitter has two flags that indicate its state: USART data register empty (UDREn) and transmit complete (TXCn). Both flags can be used for generating interrupts. The data register empty (UDREn) flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the shift register. For compatibility with future devices, always write this bit to zero when writing the UCSRnA register. When the data register empty interrupt enable (UDRIEn) bit in UCSRnB is written to one, the USART data register empty interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data transmission is used, the data register empty interrupt routine must either write new data to UDRn in order to clear UDREn or disable the data register empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The transmit complete (TXCn) flag bit is set one when the entire frame in the transmit shift register has been shifted out and there are no new data currently present in the transmit buffer. The TXCn flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn flag is useful in half-duplex communication interfaces (like the RS-485 standard), where a transmitting application must enter receive mode and free the communication bus immediately after completing the transmission. 172 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 When the transmit compete interrupt enable (TXCIEn) bit in UCSRnB is set, the USART transmit complete interrupt will be executed when the TXCn flag becomes set (provided that global interrupts are enabled). When the transmit complete interrupt is used, the interrupt handling routine does not have to clear the TXCn flag, this is done automatically when the interrupt is executed. 5.17.5.4 Parity Generator The parity generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPMn1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent. 5.17.5.5 Disabling the Transmitter The disabling of the transmitter (setting the TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the transmit shift register and transmit buffer register do not contain data to be transmitted. When disabled, the transmitter will no longer override the TxDn pin. 5.17.6 Data Reception - The USART Receiver The USART receiver is enabled by writing the receive enable (RXENn) bit in the UCSRnB register to one. When the receiver is enabled, the normal pin operation of the RxDn pin is overridden by the USART and given the function as the receiver's serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCKn pin will be used as transfer clock. 5.17.6.1 Receiving Frames with 5 to 8 Data Bits The receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCKn clock, and shifted into the receive shift register until the first stop bit of a frame is received. A second stop bit will be ignored by the receiver. When the first stop bit is received, i.e., a complete serial frame is present in the receive shift register, the contents of the shift register will be moved into the receive buffer. The receive buffer can then be read by reading the UDRn I/O location. The following code example shows a simple USART receive function based on polling of the receive complete (RXCn) flag. When using frames with less than eight bits the most significant bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive(void) { /* Wait for data to be received */ while (!(UCSRnA & (1<<RXCn))) ; /* Get and return received data from buffer */ return UDRn; } Note: 1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". The function simply waits for data to be present in the receive buffer by checking the RXCn flag, before reading the buffer and returning the value. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 173 5.17.6.2 Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZn=7) the ninth bit must be read from the RXB8n bit in UCSRnB before reading the low bits from the UDRn. This rule applies to the FEn, DORn and UPEn status flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn, DORn and UPEn bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA in r17, UCSRnB in r16, UDRn ; If error, return -1 andi r18,(1<<FEn)|(1<<DORn)|(1<<UPEn) breq USART_ReceiveNoError ldi r17, HIGH(-1) ldi r16, LOW(-1) USART_ReceiveNoError: ; Filter the 9th bit, then return lsr r17 andi r17, 0x01 ret C Code Example(1) unsigned int USART_Receive( void ) { unsigned char status, resh, resl; /* Wait for data to be received */ while (!(UCSRnA & (1<<RXCn))) ; /* Get status and 9th bit, then data */ /* from buffer */ status = UCSRnA; resh = UCSRnB; resl = UDRn; /* If error, return -1 */ if (status & (1<<FEn)|(1<<DORn)|(1<<UPEn)) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << 8) | resl); } Note: 1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". The receive function example reads all the I/O registers into the register file before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. 174 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.17.6.3 Receive Compete Flag and Interrupt The USART receiver has one flag that indicates the receiver state. The receive complete (RXCn) flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero. When the receive complete Interrupt enable (RXCIEn) in UCSRnB is set, the USART receive complete interrupt will be executed as long as the RXCn flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDRn in order to clear the RXCn flag, otherwise a new interrupt will occur once the interrupt routine terminates. 5.17.6.4 Receiver Error Flags The USART receiver has three error flags: Frame error (FEn), data overrun (DORn) and parity error (UPEn). All can be accessed by reading UCSRnA. Common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location. Another equality for the error flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRnA is written for upward compatibility of future USART implementations. None of the error flags can generate interrupts. The frame error (FEn) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FEn flag is zero when the stop bit was correctly read (as one), and the FEn flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn flag is not affected by the setting of the USBSn bit in UCSRnC since the receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. The data overrun (DORn) flag indicates data loss due to a receiver buffer full condition. A data overrun occurs when the receive buffer is full (two characters), it is a new character waiting in the receive shift register, and a new start bit is detected. If the DORn flag is set there was one or more serial frame lost between the frame last read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always write this bit to zero when writing to UCSRnA. The DORn flag is cleared when the frame received was successfully moved from the shift register to the receive buffer. The parity error (UPEn) flag indicates that the next frame in the receive buffer had a parity error when received. If parity check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see Section 5.17.3.1 "Parity Bit Calculation" on page 169 and Section 5.17.6.5 "Parity Checker" on page 175. 5.17.6.5 Parity Checker The parity checker is active when the high USART parity mode (UPMn1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The parity error (UPEn) flag can then be read by software to check if the frame had a parity error. The UPEn bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 5.17.6.6 Disabling the Receiver In contrast to the transmitter, disabling of the receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the receiver will no longer override the normal function of the RxDn port pin. The receiver buffer FIFO will be flushed when the receiver is disabled. Remaining data in the buffer will be lost. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 175 5.17.6.7 Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the receiver is disabled, i.e., the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDRn I/O location until the RXCn flag is cleared. The following code example shows how to flush the receive buffer. Assembly Code Example(1) USART_Flush: sbis UCSRnA, RXCn ret in r16, UDRn rjmp USART_Flush C Code Example(1) void USART_Flush (void) { unsigned char dummy; while (UCSRnA & (1<<RXCn)) dummy = UDRn; } Note: 1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 5.17.7 Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 5.17.7.1 Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 5-73 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for normal mode, and eight times the baud rate for double speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the double speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (i.e., no communication activity). Figure 5-73. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) Sample (U2X = 1) 0 0 0 1 1 2 3 2 4 5 3 6 7 4 8 9 5 10 11 6 12 13 7 14 15 8 16 1 1 2 3 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The clock recovery logic then uses samples 8, 9, and 10 for normal mode, and samples 4, 5, and 6 for double speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the receiver starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recovery logic is synchronized and the data recovery can begin. The synchronization process is repeated for each start bit. 176 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.17.7.2 Asynchronous Data Recovery When the receiver clock is synchronized to the start bit, the data recovery can begin. The data recovery unit uses a state machine that has 16 states for each bit in normal mode and eight states for each bit in double speed mode. Figure 5-74 shows the sampling of the data bits and the parity bit. Each of the samples is given a number that is equal to the state of the recovery unit. Figure 5-74. Sampling of Data and Parity Bit RxD Bit n Sample (U2X = 0) Sample (U2X = 1) 1 2 1 3 4 2 5 6 3 7 8 4 9 10 5 11 12 6 13 7 14 15 8 16 1 1 The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the received bit. The center samples are emphasized on the figure by having the sample number inside boxes. The majority voting process is done as follows: If two or all three samples have high levels, the received bit is registered to be a logic 1. If two or all three samples have low levels, the received bit is registered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the receiver only uses the first stop bit of a frame. Figure 5-75 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 5-75. Stop Bit Sampling and Next Start Bit Sampling RxD (A) STOP 1 (B) (C) Sample (U2X = 0) Sample (U2X = 1) 1 1 2 3 2 4 5 3 6 7 4 8 9 5 10 0/1 6 0/1 0/1 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the frame error (FEn) flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. For normal speed mode, the first low level sample can be at point marked (A) in Figure 5-75. For double speed mode the first low level must be delayed to (B). (C) marks a stop bit of full length. The early start bit detection influences the operational range of the receiver. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 177 5.17.7.3 Asynchronous Operational Range The operational range of the receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If the transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see Table 5-73) base frequency, the receiver will not be able to synchronize the frames to the start bit. The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. ( D + 1 )S R slow = --------------------------------------------S - 1 + D x S + SF ( D + 2 )S R fast = -----------------------------------( D + 1 )S + S M D Sum of character size and parity size (D = 5 to 10 bit) S Samples per bit. S = 16 for normal speed mode and S = 8 for double speed mode. SF First sample number used for majority voting. SF = 8 for normal speed and SF = 4 for double speed mode. SM Middle sample number used for majority voting. SM = 9 for normal speed and SM = 5 for double speed mode. Rslow is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate. Rfast is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate. Table 5-73 and Table 5-74 on page 178 list the maximum receiver baud rate error that can be tolerated. Note that normal speed mode has higher toleration of baud rate variations. Table 5-73. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 Table 5-74. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = 1) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104,35 +4.35/-4.48 1.5 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0 The recommendations of the maximum receiver baud rate error was made under the assumption that the receiver and transmitter equally divides the maximum total error. 178 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 There are two possible sources for the receivers baud rate error. The receiver's system clock (XTAL) will always have some minor instability over the supply voltage range and the temperature range. When using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. The second source for the error is more controllable. The baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case an UBRRn value that gives an acceptable low error can be used if possible. 5.17.8 Multi-processor Communication Mode Setting the multi-processor communication mode (MPCMn) bit in UCSRnA enables a filtering function of incoming frames received by the USART receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus. The transmitter is unaffected by the MPCMn setting, but has to be used differently when it is a part of a system utilizing the multi-processor communication mode. If the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indicates if the frame contains data or address information. If the receiver is set up for frames with nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The multi-processor communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed. If a particular slave MCU has been addressed, it will receive the following data frames as normal, while the other slave MCUs will ignore the received frames until another address frame is received. 5.17.8.1 Using MPCMn For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZn = 7). The ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared when a data frame (TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character frame format. The following procedure should be used to exchange data in multi-processor communication mode: 1. All slave MCUs are in multi-processor communication mode (MPCMn in UCSRnA is set). 2. The master MCU sends an address frame, and all slaves receive and read this frame. In the slave MCUs, the RXCn flag in UCSRnA will be set as normal. 3. Each slave MCU reads the UDRn register and determines if it has been selected. If so, it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and keeps the MPCMn setting. 4. The addressed MCU will receive all data frames until a new address frame is received. The other slave MCUs, which still have the MPCMn bit set, will ignore the data frames. 5. When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCMn bit and waits for a new address frame from master. The process then repeats from 2. Using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver must change between using n and n+1 character frame formats. This makes full-duplex operation difficult since the transmitter and receiver uses the same character size setting. If 5- to 8-bit character frames are used, the transmitter must be set to use two stop bit (USBSn = 1) since the first stop bit is used for indicating the frame type. Do not use read-modify-write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn flag and this might accidentally be cleared when using SBI or CBI instructions. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 179 5.17.9 USART Register Description 5.17.9.1 USART I/O Data Register n- UDRn Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART transmit data buffer register and USART receive data buffer registers share the same I/O address referred to as USART data register or UDRn. The transmit data buffer register (TXB) will be the destination for data written to the UDRn register location. Reading the UDRn register location will return the contents of the receive data buffer register (RXB). For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the transmitter and set to zero by the receiver. The transmit buffer can only be written when the UDREn flag in the UCSRnA register is set. Data written to UDRn when the UDREn flag is not set, will be ignored by the USART transmitter. When data is written to the transmit buffer, and the transmitter is enabled, the transmitter will load the data into the transmit shift register when the shift register is empty. Then the data will be serially transmitted on the TxDn pin. The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use read-modify-write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the FIFO. 5.17.9.2 USART Control and Status Register n A - UCSRnA Bit 7 6 5 4 3 2 1 0 RXCn TXCn UDREn FEn DORn UPEn U2Xn MPCMn Read/Write R R/W R R R R R/W R/W Initial Value 0 0 1 0 0 0 0 0 UCSRnA * Bit 7 - RXCn: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). If the receiver is disabled, the receive buffer will be flushed and consequently the RXCn bit will become zero. The RXCn flag can be used to generate a receive complete interrupt (see description of the RXCIEn bit). * Bit 6 - TXCn: USART Transmit Complete This flag bit is set when the entire frame in the transmit shift register has been shifted out and there are no new data currently present in the transmit buffer (UDRn). The TXCn flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn flag can generate a transmit complete interrupt (see description of the TXCIEn bit). * Bit 5 - UDREn: USART Data Register Empty The UDREn flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn flag can generate a data register empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready. * Bit 4 - FEn: Frame Error This bit is set if the next character in the receive buffer had a frame error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA. * Bit 3 - DORn: Data OverRun This bit is set if a data overrun condition is detected. A data overrun occurs when the receive buffer is full (two characters), it is a new character waiting in the receive shift register, and a new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA. 180 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 * Bit 2 - UPEn: USART Parity Error This bit is set if the next character in the receive buffer had a parity error when received and the parity checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA. * Bit 1 - U2Xn: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. * Bit 0 - MPCMn: Multi-processor Communication Mode This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCMn setting. For more detailed information see Section 5.17.8 "Multi-processor Communication Mode" on page 179. 5.17.9.3 USART Control and Status Register n B - UCSRnB Bit 7 6 5 4 3 2 1 0 RXCIEn TXCIEn UDRIEn RXENn TXENn UCSZn2 RXB8n TXB8n Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 UCSRnB * Bit 7 - RXCIEn: RX Complete Interrupt Enable n Writing this bit to one enables interrupt on the RXCn flag. A USART receive complete interrupt will be generated only if the RXCIEn bit is written to one, the global interrupt flag in SREG is written to one and the RXCn bit in UCSRnA is set. * Bit 6 - TXCIEn: TX Complete Interrupt Enable n Writing this bit to one enables interrupt on the TXCn flag. A USART transmit complete interrupt will be generated only if the TXCIEn bit is written to one, the global interrupt flag in SREG is written to one and the TXCn bit in UCSRnA is set. * Bit 5 - UDRIEn: USART Data Register Empty Interrupt Enable n Writing this bit to one enables interrupt on the UDREn flag. A data register empty interrupt will be generated only if the UDRIEn bit is written to one, the global interrupt flag in SREG is written to one and the UDREn bit in UCSRnA is set. * Bit 4 - RXENn: Receiver Enable n Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxDn pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FEn, DORn, and UPEn flags. * Bit 3 - TXENn: Transmitter Enable n Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxDn pin when enabled. The disabling of the transmitter (writing TXENn to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the transmit shift register and transmit buffer register do not contain data to be transmitted. When disabled, the transmitter will no longer override the TxDn port. * Bit 2 - UCSZn2: Character Size n The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits (Character SiZe) in a frame the receiver and transmitter use. * Bit 1 - RXB8n: Receive Data Bit 8 n RXB8n is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDRn. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 181 * Bit 0 - TXB8n: Transmit Data Bit 8 n TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDRn. 5.17.9.4 USART Control and Status Register n C - UCSRnC Bit 7 6 5 4 3 2 1 0 UMSELn1 UMSELn0 UPMn1 UPMn0 USBSn UCSZn1 UCSZn0 UCPOLn Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 1 1 0 UCSRnC * Bits 7:6 - UMSELn1:0 USART Mode Select These bits select the mode of operation of the USARTn as shown in Table 5-75. Table 5-75. UMSELn Bits Settings Note: UMSELn1 UMSELn0 Mode 0 0 Asynchronous USART 0 1 Synchronous USART 1 0 (Reserved) 1 1 Master SPI (MSPIM)(1) 1. See Section 5.18 "USART in SPI Mode" on page 186 for full description of the Master SPI Mode (MSPIM) operation * Bits 5:4 - UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPMn setting. If a mismatch is detected, the UPEn flag in UCSRnA will be set. Table 5-76. UPMn Bits Settings UPMn1 UPMn0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, even parity 1 1 Enabled, odd parity * Bit 3 - USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the transmitter. The receiver ignores this setting. Table 5-77. USBS Bit Settings USBSn Stop Bit(s) 0 1-bit 1 2-bit * Bit 2:1 - UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe) in a frame the receiver and transmitter use. 182 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Table 5-78. UCSZn Bits Settings UCSZn2 UCSZn1 UCSZn0 Character Size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit * Bit 0 - UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). Table 5-79. UCPOLn Bit Settings UCPOLn Transmitted Data Changed (Output of TxDn Pin) Received Data Sampled (Input on RxDn Pin) 0 Rising XCKn edge Falling XCKn edge 1 Falling XCKn edge Rising XCKn edge 5.17.9.5 USART Baud Rate Registers - UBRRnL and UBRRnH Bit 15 14 13 12 - - - - 7 6 5 11 10 9 8 UBRRn[11:8] UBRRnH UBRRn[7:0] Read/Write Initial Value UBRRnL 4 3 2 1 0 R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * Bit 15:12 - Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRnH is written. * Bit 11:0 - UBRR11:0: USART Baud Rate Register This is a 12-bit register which contains the USART baud rate. The UBRRnH contains the four most significant bits, and the UBRRnL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler. 5.17.10 Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRRn settings in Table 5-80 on page 184. UBRRn values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table. Higher error ratings are acceptable, but the receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see Section 5.17.7.3 "Asynchronous Operational Range" on page 178). The error values are calculated using the following equation: BaudRate Closes Match Error [ % ] = ------------------------------------------------- - 1 x 100% BaudRate ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 183 Table 5-80. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies Baud Rate (bps) fosc = 1.0000MHz U2Xn = 0 UBRRn Error fosc = 1.8432MHz U2Xn = 1 UBRRn Error U2Xn = 0 UBRRn Error fosc = 2.0000MHz U2Xn = 1 UBRRn Error U2Xn = 0 UBRRn Error U2Xn = 1 UBRRn Error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k - - 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k - - 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k - - - - - - 0 0.0% - - - - 250k - - - - - - - - - - 0 0.0% (1) Max. Note: 1. 62.5kbps 125kbps UBRRn = 0, Error = 0.0% 115.2kbps 230.4kbps 125kbps 250kbps Table 5-81. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) Baud Rate (bps) fosc = 3.6864MHz fosc = 7.3728MHz U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 0.5M - - 0 -7.8% - - 0 0.0% 0 -7.8% 1 -7.8% 1M - - - - - - - - - - 0 -7.8% (1) Max. Note: 184 fosc = 4.0000MHz 1. 230.4kbps 460.8kbps UBRRn = 0, Error = 0.0% ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 250kbps 0.5Mbps 460.8kbps 921.6kbps Table 5-82. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) Baud Rate (bps) fosc = 8.0000MHz U2Xn = 0 UBRRn Error fosc = 11.0592MHz U2Xn = 1 UBRRn Error U2Xn = 0 UBRRn Error fosc = 14.7456MHz U2Xn = 1 UBRRn Error U2Xn = 0 UBRRn Error U2Xn = 1 UBRRn Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0% 28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0% 38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0% 57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0% 76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0% 115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0% 230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0% 250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3% 0.5M 0 0.0% 1 0.0% - - 2 -7.8% 1 -7.8% 3 -7.8% 1M - - 0 0.0% - - - - 0 -7.8% 1 -7.8% (1) Max. Note: 1. 0.5Mbps 1Mbps UBRRn = 0, Error = 0.0% 691.2kbps 1.3824Mbps 921.6kbps 1.8432Mbps Table 5-83. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) Baud Rate (bps) fosc = 16.0000MHz U2Xn = 0 UBRRn Error fosc = 18.4320MHz U2Xn = 1 UBRRn Error U2Xn = 0 UBRRn Error fosc = 20.0000MHz U2Xn = 1 UBRRn Error U2Xn = 0 UBRRn Error U2Xn = 1 UBRRn Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2% 28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2% 38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2% 57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9% 76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4% 115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4% 230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4% 250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0% 0.5M 1 0.0% 3 0.0% - - 4 -7.8% - - 4 0.0% 1M 0 0.0% 1 0.0% - - - - - - - - (1) Max. Note: 1. 1Mbps 2Mbps UBRRn = 0, Error = 0.0% 1.152Mbps 2.304Mbps 1.25Mbps 2.5Mbps ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 185 5.18 USART in SPI Mode The universal synchronous and asynchronous serial receiver and transmitter (USART) can be set to a master SPI compliant mode of operation. The master SPI mode (MSPIM) has the following features: Full duplex, three-wire synchronous data transfer Master operation Supports all four SPI modes of operation (mode 0, 1, 2, and 3) LSB first or MSB first data transfer (configurable data order) Queued operation (double buffered) High resolution baud rate generator High speed operation (fXCKmax = fCK/2) Flexible interrupt generation 5.18.1 Overview Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of operation the SPI master control logic takes direct control over the USART resources. These resources include the transmitter and receiver shift register and buffers, and the baud rate generator. The parity generator and checker, the data and clock recovery logic, and the RX and TX control logic is disabled. The USART RX and TX control logic is replaced by a common SPI transfer control logic. However, the pin control logic and interrupt generation logic is identical in both modes of operation. The I/O register locations are the same in both modes. However, some of the functionality of the control registers changes when using MSPIM. 5.18.2 Clock Generation The clock generation logic generates the base clock for the transmitter and receiver. For USART MSPIM mode of operation only internal clock generation (i.e. master operation) is supported. The data direction register for the XCKn pin (DDR_XCKn) must therefore be set to one (i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one). The internal clock generation used in MSPIM mode is identical to the USART synchronous master mode. The baud rate or UBRRn setting can therefore be calculated using the same equations (see Table 5-84). Table 5-84. Equations for Calculating Baud Rate Register Setting Equation for Calculating Baud Rate(1) Operating Mode Synchronous master mode Note: 186 1. f OSC BAUD = -----------------------------------2 ( UBRRn + 1 ) Equation for Calculating UBRRn Value f OSC UBRRn = -------------------- - 1 2BAUD The baud rate is defined to be the transfer rate in bit per second (bps) BAUD Baud rate (in bits per second, bps) fOSC System oscillator clock frequency UBRRn Contents of the UBRRnH and UBRRnL registers, (0-4095) ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.18.3 SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 5-76. Data bits are shifted out and latched in on opposite edges of the XCKn signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn functionality is summarized in Table 5-85. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. Table 5-85. UCPOLn and UCPHAn FunctionalityUCPOLn UCPHAn SPI Mode Leading Edge Trailing Edge 0 0 0 Sample (rising) Setup (falling) 0 1 1 Setup (rising) Sample (falling) 1 0 2 Sample (falling) Setup (rising) 1 1 3 Setup (falling) Sample (rising) Figure 5-76. UCPHAn and UCPOLn Data Transfer Timing Diagrams UCPHA=0 UCPHA=1 UCPOL=0 UCPOL=1 XCK XCK Data setup (TXD) Data setup (TXD) Data sample (RXD) Data sample (RXD) XCK XCK Data setup (TXD) Data setup (TXD) Data sample (RXD) Data sample (RXD) 5.18.4 Frame Formats A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two valid frame formats: 8-bit data with MSB first 8-bit data with LSB first A frame starts with the least or most significant data bit. Then the next data bits, up to a total of eight, are succeeding, ending with the most or least significant bit accordingly. When a complete frame is transmitted, a new frame can directly follow it, or the communication line can be set to an idle (high) state. The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The receiver and transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. 16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit complete interrupt will then signal that the 16-bit value has been shifted out. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 187 5.18.4.1 USART MSPIM Initialization The USART in MSPIM mode has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting master mode of operation (by setting DDR_XCKn to one), setting frame format and enabling the transmitter and the receiver. Only the transmitter can operate independently. For interrupt driven USART operation, the global interrupt flag should be cleared (and thus interrupts globally disabled) when doing the initialization. Note: To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be zero at the time the transmitter is enabled. Contrary to the normal mode USART operation the UBRRn must then be written to the desired value after the transmitter is enabled, but before the first transmission is started. Setting UBRRn to zero before enabling the transmitter is not necessary if the initialization is done immediately after a reset since UBRRn is reset to zero. Before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that there is no ongoing transmissions during the period the registers are changed. The TXCn flag can be used to check that the transmitter has completed all transfers, and the RXCn flag can be used to check that there are no unread data in the receive buffer. Note that the TXCn flag must be cleared before each transmission (before UDRn is written) if it is used for this purpose. The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume polling (no interrupts enabled). The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. Assembly Code Example(1) USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn) out UCSRnC,r18 ; Enable receiver and transmitter. ldi r18, (1<<RXENn)|(1<<TXENn) out UCSRnB,r18 ; Set baud rate. ; IMPORTANT: The Baud Rate must be set after the transmitter is enabled! out UBRRnH, r17 out UBRRnL, r18 ret C Code Example(1) void USART_Init(unsigned int baud) { UBRRn = 0; /* Setting the XCKn port pin as output, enables master mode. */ XCKn_DDR |= (1<<XCKn); /* Set MSPI mode of operation and SPI data mode 0. */ UCSRnC = (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn); /* Enable receiver and transmitter. */ UCSRnB = (1<<RXENn)|(1<<TXENn); /* Set baud rate. */ /* IMPORTANT: The Baud Rate must be set after the transmitter is enabled */ UBRRn = baud; } Note: 188 1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.18.5 Data Transfer Using the USART in MSPI mode requires the transmitter to be enabled, i.e. the TXENn bit in the UCSRnB register is set to one. When the transmitter is enabled, the normal port operation of the TxDn pin is overridden and given the function as the transmitter's serial output. Enabling the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one. When the receiver is enabled, the normal pin operation of the RxDn pin is overridden and given the function as the Receiver's serial input. The XCKn will in both cases be used as the transfer clock. After initialization the USART is ready for doing data transfers. A data transfer is initiated by writing to the UDRn I/O location. This is the case for both sending and receiving data since the transmitter controls the transfer clock. The data written to UDRn is moved from the transmit buffer to the shift register when the shift register is ready to send a new frame. Note: To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must be read once for each byte transmitted. The input buffer operation is identical to normal USART mode, i.e. if an overflow occurs the character last received will be lost, not the first data in the buffer. This means that if four bytes are transferred, byte 1 first, then byte 2, 3, and 4, and the UDRn is not read before all transfers are completed, then byte 3 to be received will be lost, and not byte 1. The following code examples show a simple USART in MSPIM mode transfer function based on polling of the data register empty (UDREn) flag and the receive complete (RXCn) flag. The USART has to be initialized before the function can be used. For the assembly code, the data to be sent is assumed to be stored in register R16 and the data received will be available in the same register (R16) after the function returns. The function simply waits for the transmit buffer to be empty by checking the UDREn flag, before loading it with new data to be transmitted. The function then waits for data to be present in the receive buffer by checking the RXCn flag, before reading the buffer and returning the value. Assembly Code Example(1) USART_MSPIM_Transfer: ; Wait for empty transmit buffer sbis UCSRnA, UDREn rjmp USART_MSPIM_Transfer ; Put data (r16) into buffer, sends the data out UDRn,r16 ; Wait for data to be received USART_MSPIM_Wait_RXCn: sbis UCSRnA, RXCn rjmp USART_MSPIM_Wait_RXCn ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive(void) { /* Wait for empty transmit buffer */ while (!(UCSRnA & (1<<UDREn))); /* Put data into buffer, sends the data */ UDRn = data; /* Wait for data to be received */ while (!(UCSRnA & (1<<RXCn))); /* Get and return received data from buffer */ return UDRn; } Note: 1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 189 5.18.5.1 Transmitter and Receiver Flags and Interrupts The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in function to the normal USART operation. However, the receiver error status flags (FE, DOR, and PE) are not in use and is always read as zero. 5.18.5.2 Disabling the Transmitter or Receiver The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normal USART operation. 5.18.6 USART MSPIM Register Description The following section describes the registers used for SPI operation using the USART. 5.18.6.1 USART MSPIM I/O Data Register - UDRn The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART operation (see Section 5.17.9.1 "USART I/O Data Register n- UDRn" on page 180). 5.18.6.2 USART MSPIM Control and Status Register n A - UCSRnA Bit 7 6 5 4 3 2 1 0 RXCn TXCn UDREn - - - - - Read/Write R/W R/W R/W R R R R R Initial Value 0 0 0 0 0 1 1 0 UCSRnA * Bit 7 - RXCn: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). If the receiver is disabled, the receive buffer will be flushed and consequently the RXCn bit will become zero. The RXCn flag can be used to generate a receive complete interrupt (see description of the RXCIEn bit). * Bit 6 - TXCn: USART Transmit Complete This flag bit is set when the entire frame in the transmit shift register has been shifted out and there are no new data currently present in the transmit buffer (UDRn). The TXCn flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn flag can generate a transmit complete interrupt (see description of the TXCIEn bit). * Bit 5 - UDREn: USART Data Register Empty The UDREn flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn flag can generate a data register empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to indicate that the transmitter is ready. * Bit 4:0 - Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnA is written. 5.18.6.3 USART MSPIM Control and Status Register n B - UCSRnB Bit 7 6 5 4 3 2 1 0 RXCIEn TXCIEn UDRIE RXENn TXENn - - - Read/Write R/W R/W R/W R/W R/W R R R Initial Value 0 0 0 0 0 1 1 0 UCSRnB * Bit 7 - RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn flag. A USART receive complete interrupt will be generated only if the RXCIEn bit is written to one, the global interrupt flag in SREG is written to one and the RXCn bit in UCSRnA is set. 190 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 * Bit 6 - TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn flag. A USART transmit complete interrupt will be generated only if the TXCIEn bit is written to one, the global interrupt flag in SREG is written to one and the TXCn bit in UCSRnA is set. * Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn flag. A data register empty interrupt will be generated only if the UDRIE bit is written to one, the global interrupt flag in SREG is written to one and the UDREn bit in UCSRnA is set. * Bit 4 - RXENn: Receiver Enable Writing this bit to one enables the USART receiver in MSPIM mode. The receiver will override normal port operation for the RxDn pin when enabled. Disabling the receiver will flush the receive buffer. Only enabling the receiver in MSPI mode (i.e. setting RXENn=1 and TXENn=0) has no meaning since it is the transmitter that controls the transfer clock and since only master mode is supported. * Bit 3 - TXENn: Transmitter Enable Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxDn pin when enabled. The disabling of the transmitter (writing TXENn to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the transmit shift register and transmit buffer register do not contain data to be transmitted. When disabled, the transmitter will no longer override the TxDn port. * Bit 2:0 - Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnB is written. 5.18.6.4 USART MSPIM Control and Status Register n C - UCSRnC Bit 7 6 5 4 3 2 1 0 UMSELn1 UMSELn0 - - - UDORDn UCPHAn UCPOLn Read/Write R/W R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 1 1 0 UCSRnC * Bit 7:6 - UMSELn1:0: USART Mode Select These bits select the mode of operation of the USART as shown in Table 5-86. See Section 5.17.9.4 "USART Control and Status Register n C - UCSRnC" on page 182 for full description of the normal USART operation. The MSPIM is enabled when both UMSELn bits are set to one. The UDORDn, UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is enabled. Table 5-86. UMSELn Bits Settings UMSELn1 UMSELn0 Mode 0 0 Asynchronous USART 0 1 Synchronous USART 1 0 (Reserved) 1 1 Master SPI (MSPIM) * Bit 5:3 - Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnC is written. * Bit 2 - UDORDn: Data Order When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted first. Refer to the Section 5.17.3 "Frame Formats" on page 168 for details. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 191 * Bit 1 - UCPHAn: Clock Phase The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of XCKn. Refer to the section Section 5.18.3 "SPI Data Modes and Timing" on page 187 for details. * Bit 0 - UCPOLn: Clock Polarity The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and UCPHAn bit settings determine the timing of the data transfer. Refer to the section Section 5.18.3 "SPI Data Modes and Timing" on page 187 for details. USART MSPIM baud rate registers - UBRRnL and UBRRnH The function and bit description of the baud rate registers in MSPI mode is identical to normal USART operation (see Section 5.17.9.5 "USART Baud Rate Registers - UBRRnL and UBRRnH" on page 183). 5.18.7 AVR USART MSPIM versus AVR SPI The USART in MSPIM mode is fully compatible with the AVR(R) SPI regarding: Master mode timing diagram. The UCPOLn bit functionality is identical to the SPI CPOL bit. The UCPHAn bit functionality is identical to the SPI CPHA bit. The UDORDn bit functionality is identical to the SPI DORD bit. However, since the USART in MSPIM mode reuses the USART resources, the use of the USART in MSPIM mode is somewhat different compared to the SPI. In addition to differences of the control register bits, and that only master operation is supported by the USART in MSPIM mode, the following features differ between the two modules: The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no buffer. The USART in MSPIM mode receiver includes an additional buffer level. Interrupt timing is not compatible. The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode. The SPI double speed mode (SPI2X) bit is not included. However, the same effect is achieved by setting UBRRn accordingly. Pin control differs due to the master only operation of the USART in MSPIM mode. A comparison of the USART in MSPIM mode and the SPI pins is shown in Table 5-87. Table 5-87. Comparison of USART in MSPIM Mode and SPI Pins. 192 USART_MSPIM SPI Comment TxDn MOSI Master out only RxDn MISO Master in only XCKn SCK (Functionally identical) (N/A) SS ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Not supported by USART in MSPIM 5.19 2-wire Serial Interface 5.19.1 Features Simple yet powerful and flexible communication interface, only two bus lines needed Both master and slave operation supported Device can operate as transmitter or receiver 7-bit Address space allows up to 128 different slave addresses Multi-master arbitration support Up to 400kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up When AVR is in sleep mode 5.19.2 2-wire Serial Interface Bus Definition The 2-wire serial interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol. Figure 5-77. TWI Bus Interconnection VCC Device 1 Device 2 Device 3 ........ Device n R1 R2 SDA SCL 5.19.2.1 TWI Terminology The following definitions are frequently encountered in this section. Table 5-88. TWI Terminology Term Description Master The device that initiates and terminates a transmission. The master also generates the SCL clock. Slave The device addressed by a Master. Transmitter The device placing data on the bus. Receiver The device reading data from the bus. The PRTWI bit in Section 5.7.7.1 "Power Reduction Register - PRR" on page 58 must be written to zero to enable the 2-wire serial interface. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 193 5.19.2.2 Electrical Interconnection As depicted in Figure 5-77 on page 193, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero. A high level is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line high. Note that all AVR(R) devices connected to the TWI bus must be powered in order to allow any bus operation. The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400pF and the 7-bit slave address space. A detailed specification of the electrical characteristics of the TWI is given in Section 6. "2-wire Serial Interface Characteristics" on page 276. Two different sets of specifications are presented there, one relevant for bus speeds below 100kHz, and one valid for bus speeds up to 400kHz. 5.19.3 Data Transfer and Frame Format 5.19.3.1 Transferring Bits Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high. The only exception to this rule is for generating start and stop conditions. Figure 5-78. Data Validity SDA SCL Data Stable Data Stable Data Change 5.19.3.2 START and STOP Conditions The master initiates and terminates a data transmission. The transmission is initiated when the master issues a START condition on the bus, and it is terminated when the master issues a STOP condition. Between a START and a STOP condition, the bus is considered busy, and no other master should try to seize control of the bus. A special case occurs when a new START condition is issued between a START and STOP condition. This is referred to as a REPEATED START condition, and is used when the master wishes to initiate a new transfer without relinquishing control of the bus. After a REPEATED START, the bus is considered busy until the next STOP. This is identical to the START behavior, and therefore START is used to describe both START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. Figure 5-79. START, REPEATED START and STOP Conditions SDA SCL START 194 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 STOP START REPEATED START STOP 5.19.3.3 Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed. When a slave recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the master's request, the SDA line should be left high in the ACK clock cycle. The master can then transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively. The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK cycle. A general call is used when a master wishes to transmit the same message to several slaves in the system. When the general call address followed by a Write bit is transmitted on the bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle. The following data packets will then be received by all the slaves that acknowledged the general call. Note that transmitting the general call address followed by a read bit is meaningless, as this would cause contention if several slaves started transmitting different data. All addresses of the format 1111 xxx should be reserved for future purposes. Figure 5-80. Address Packet Format Addr MSB Addr LSB R/W 7 8 ACK SDA SCL 1 2 9 START 5.19.3.4 Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the master generates the clock and the START and STOP conditions, while the receiver is responsible for acknowledging the reception. An acknowledge (ACK) is signalled by the receiver pulling the SDA line low during the ninth SCL cycle. If the receiver leaves the SDA line high, a NACK is signalled. When the receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first. Figure 5-81. Data Packet Format Data MSB Data LSB ACK Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 SLA + R/W 2 8 7 Data Byte 9 STOP, REPEATED START or next Data Byte ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 195 5.19.3.5 Combining Address and Data Packets into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement handshaking between the master and the slave. The slave can extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the master is too fast for the slave, or the slave needs extra time for processing between the data transmissions. The slave extending the SCL low period will not affect the SCL high period, which is determined by the master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle. Figure 5-82 shows a typical data transmission. Note that several data bytes can be transmitted between the SLA+R/W and the STOP condition, depending on the software protocol implemented by the application software. Figure 5-82. Typical Data Transmission Addr MSB Addr LSB R/W 7 8 ACK Data MSB Data LSB ACK 8 9 SDA SCL 1 START 2 9 1 SLA + R/W 2 7 Data Byte STOP 5.19.4 Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: An algorithm must be implemented allowing only one of the masters to complete the transmission. All other masters should cease transmission when they discover that they have lost the selection process. This selection process is called arbitration. When a contending master discovers that it has lost the arbitration process, it should immediately switch to Slave mode to check whether it is being addressed by the winning master. The fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on the bus must not be corrupted. Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration process. The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one from the master with the shortest high period. The low period of the combined clock is equal to the low period of the master with the longest low period. Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods when the combined SCL line goes high or low, respectively. 196 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Figure 5-83. SCL Synchronization Between Multiple Masters TAhigh TAlow SCL from Master A SCL from Master B SCL Bus Line TBlow Masters Start Counting Low Period TBhigh Masters Start Counting High Period Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the master had output, it has lost the arbitration. Note that a master can only lose arbitration when it outputs a high SDA value while another master outputs a low value. The losing master should immediately go to slave mode, checking if it is being addressed by the winning master. The SDA line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. Arbitration will continue until only one master remains, and this may take many bits. If several masters are trying to address the same slave, arbitration will continue into the data packet. Figure 5-84. Arbitration Between Two Masters START Master A Loses Arbitration, SDAA SDA SDA from Master A SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: A REPEATED START condition and a data bit. A STOP condition and a data bit. A REPEATED START and a STOP condition. It is the user software's responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 197 5.19.5 Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 5-85. All registers drawn in a thick line are accessible through the AVR(R) data bus. Figure 5-85. Overview of the TWI Module SCL Spike Filter Slew-rate Control Spike Filter Bus Interface Unit Bit Rate Generator START/STOP Control Spike Suppression Arbitration Detection Address/Data Shift Register (TWDR) Prescaler Bit Rate Register (TWBR) Ack Address Match Unit Address Register (TWAR) Address Comparator Control Unit Status Register (TWSR) Control Register (TWCR) State Machine and Status Control TWI Unit Slew-rate Control SDA 5.19.5.1 SCL and SDA Pins These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50ns. Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O port section. The internal pull-ups can in some systems eliminate the need for external ones. 5.19.5.2 Bit Rate Generator Unit This unit controls the period of SCL when operating in a master mode. The SCL period is controlled by settings in the TWI Bit rate register (TWBR) and the prescaler bits in the TWI status register (TWSR). Slave operation does not depend on bit rate or prescaler settings, but the CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. The SCL frequency is generated according to the following equation: CPU Clock frequency SCL frequency = -------------------------------------------------------------------------------------16 + 2 ( TWBR ) x ( Prescaler Value ) Note: 198 TWBR = Value of the TWI Bit rate register. Prescaler value = Value of the prescaler (see Table 5-89 on page 201). TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than 10, the master may produce an incorrect output on SDA and SCL for the reminder of the byte. The problem occurs when operating the TWI in Master mode, sending Start + SLA + R/W to a slave (a slave does not need to be connected to the bus for the condition to happen). ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.19.5.3 Bus Interface Unit This unit contains the data and address shift register (TWDR), a START/STOP controller and arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes received. In addition to the 8-bit TWDR, the bus interface unit also contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK register is not directly accessible by the application software. However, when receiving, it can be set or cleared by manipulating the TWI control register (TWCR). When in transmitter mode, the value of the received (N)ACK bit can be determined by the value in the TWSR. The START/STOP controller is responsible for generation and detection of START, REPEATED START, and STOP conditions. The START/STOP controller is able to detect START and STOP conditions even when the AVR(R) MCU is in one of the sleep modes, enabling the MCU to wake up if addressed by a master. If the TWI has initiated a transmission as master, the arbitration detection hardware continuously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost an arbitration, the control unit is informed. Correct action can then be taken and appropriate status codes generated. 5.19.5.4 Address Match Unit The address match unit checks if received address bytes match the seven-bit address in the TWI address register (TWAR). If the TWI general call recognition enable (TWGCE) bit in the TWAR is written to one, all incoming address bits will also be compared against the general call address. Upon an address match, the control unit is informed, allowing correct action to be taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR. The address match unit is able to compare addresses even when the AVR MCU is in sleep mode, enabling the MCU to wake up if addressed by a Master. If another interrupt (e.g., INT0) occurs during TWI power-down address match and wakes up the CPU, the TWI aborts operation and return to it's idle state. If this cause any problems, ensure that TWI address match is the only enabled interrupt when entering power-down. 5.19.5.5 Control Unit The control unit monitors the TWI bus and generates responses corresponding to settings in the TWI control register (TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI interrupt flag (TWINT) is asserted. In the next clock cycle, the TWI status register (TWSR) is updated with a status code identifying the event. The TWSR only contains relevant status information when the TWI interrupt flag is asserted. At all other times, the TWSR contains a special status code indicating that no relevant status information is available. As long as the TWINT flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue. The TWINT flag is set in the following situations: After the TWI has transmitted a START/REPEATED START condition. After the TWI has transmitted SLA+R/W. After the TWI has transmitted an address byte. After the TWI has lost arbitration. After the TWI has been addressed by own slave address or general call. After the TWI has received a data byte. After a STOP or REPEATED START has been received while still addressed as a slave. When a bus error has occurred due to an illegal START or STOP condition. 5.19.6 TWI Register Description 5.19.6.1 TWI Bit Rate Register - TWBR Bit 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TWBR * Bits 7..0 - TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the master modes. See Section 5.19.5.2 "Bit Rate Generator Unit" on page 198 for calculating bit rates. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 199 5.19.6.2 TWI Control Register - TWCR Bit 7 6 5 4 3 2 1 0 TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE Read/Write R/W R/W R/W R/W R R/W R R/W Initial Value 0 0 0 0 0 0 0 0 TWCR The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible. * Bit 7 - TWINT: TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI address register (TWAR), TWI status register (TWSR), and TWI data register (TWDR) must be complete before clearing this flag. * Bit 6 - TWEA: TWI Enable Acknowledge Bit The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions are met: The device's own slave address has been received. A general call has been received, while the TWGCE bit in the TWAR is set. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire serial bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again. * Bit 5 - TWSTA: TWI START Condition Bit The application writes the TWSTA bit to one when it desires to become a master on the 2-wire serial bus. The TWI hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus master status. TWSTA must be cleared by software when the START condition has been transmitted. * Bit 4 - TWSTO: TWI STOP Condition Bit Writing the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire serial bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state. * Bit 3 - TWWC: TWI Write Collision Flag The TWWC bit is set when attempting to write to the TWI data register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high. * Bit 2 - TWEN: TWI Enable Bit The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation. 200 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 * Bit 1 - Res: Reserved Bit This bit is a reserved bit and will always read as zero. * Bit 0 - TWIE: TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high. 5.19.6.3 TWI Status Register - TWSR Bit 7 6 5 4 3 2 1 0 TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 Read/Write R R R R R R R/W R/W Initial Value 1 1 1 1 1 0 0 0 TWSR * Bits 7..3 - TWS: TWI Status These 5 bits reflect the status of the TWI logic and the 2-wire serial bus. The different status codes are described later in this section. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should mask the prescaler bits to zero when checking the status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. * Bit 2 - Res: Reserved Bit This bit is reserved and will always read as zero. * Bits 1..0 - TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. Table 5-89. TWI Bit Rate Prescaler TWPS1 TWPS0 Prescaler Value 0 0 1 0 1 4 1 0 16 1 1 64 To calculate bit rates, see Section 5.19.5.2 "Bit Rate Generator Unit" on page 198. The value of TWPS1..0 is used in the equation. 5.19.6.4 TWI Data Register - TWDR Bit 7 6 5 4 3 2 1 0 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 TWDR In transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transition from master to slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly. * Bits 7..0 - TWD: TWI Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire serial bus. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 201 5.19.6.5 TWI (Slave) Address Register - TWAR Bit 7 6 5 4 3 2 1 0 TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 0 TWAR The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In multi master systems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generated. * Bits 7..1 - TWA: TWI (Slave) Address Register These seven bits constitute the slave address of the TWI unit. * Bit 0 - TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus. 5.19.6.6 TWI (Slave) Address Mask Register - TWAMR Bit 7 6 5 4 3 2 1 TWAM[6:0] 0 - Read/Write R/W R/W R/W R/W R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0 TWAMR * Bits 7..1 - TWAM: TWI Address Mask The TWAMR can be loaded with a 7-bit Slave address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bits in the TWI address register (TWAR). If the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR. Figure 5-86 shown the address match logic in detail. Figure 5-86. TWI Address Match Logic, Block Diagram TWAR0 Address Match Address Bit 0 TWAMR0 Address Bit Comparator 0 Address Bit Comparator 6..1 * Bit 0 - Res: Reserved Bit This bit is an unused bit in the Atmel(R) ATA6612C/ATA6613C, and will always read as zero. 202 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.19.7 Using the TWI The AVR(R) TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer. Note that the TWI interrupt enable (TWIE) bit in TWCR together with the global interrupt enable bit in SREG allow the application to decide whether or not assertion of the TWINT flag should generate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT flag in order to detect actions on the TWI bus. When the TWINT flag is asserted, the TWI has finished an operation and awaits application response. In this case, the TWI status register (TWSR) contains a value indicating the current state of the TWI bus. The application software can then decide how the TWI should behave in the next TWI bus cycle by manipulating the TWCR and TWDR registers. Figure 5-87 is a simple example of how the application can interface to the TWI hardware. In this example, a master wishes to transmit a single data byte to a slave. This description is quite abstract, a more detailed explanation follows later in this section. A simple code example implementing the desired behavior is also presented. Application Action Figure 5-87. Interfacing the Application to the TWI in a Typical Transmission 1. Application writes to TWCR to initiate transmission of START TWI Hardware Action TWI bus 3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, makin sure that TWINT is written to one, and TWSTA is written to zero. START 2. TWINT set. Status code indicates START condition sent SLA+W 5. Check TWSR to see if SLA+W was sent and ACK received. Application loads data intoTWDR, and loads appropriate control signals into TWCR, makin sure that TWINT is written to one A 4. TWINT set. Status code indicates SLA+W sent, ACK received Data 7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, makin sure that TWINT is written to one A 6. TWINT set. Status code indicates data sent, ACK received STOP Indicates TWINT set 1. The first step in a TWI transmission is to transmit a START condition. This is done by writing a specific value into TWCR, instructing the TWI hardware to transmit a START condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the START condition. 2. When the START condition has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the START condition has successfully been sent. 3. The application software should now examine the value of TWSR, to make sure that the START condition was successfully transmitted. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load SLA+W into TWDR. Remember that TWDR is used both for address and data. After TWDR has been loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the address packet. 4. When the address packet has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the address packet has successfully been sent. The status code will also reflect whether a slave acknowledged the packet or not. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 203 5. The application software should now examine the value of TWSR, to make sure that the address packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load a data packet into TWDR. Subsequently, a specific value must be written to TWCR, instructing the TWI hardware to transmit the data packet present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the data packet. 6. When the data packet has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the data packet has successfully been sent. The status code will also reflect whether a slave acknowledged the packet or not. 7. The application software should now examine the value of TWSR, to make sure that the data packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must write a specific value to TWCR, instructing the TWI hardware to transmit a STOP condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the STOP condition. Note that TWINT is NOT set after a STOP condition has been sent. Even though this example is simple, it shows the principles involved in all TWI transmissions. These can be summarized as follows: When the TWI has finished an operation and expects application response, the TWINT flag is set. The SCL line is pulled low until TWINT is cleared. When the TWINT flag is set, the user must update all TWI registers with the value relevant for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus cycle. After all TWI register updates and other pending application software tasks have been completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting. In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made, for example by using include-files. Table 5-90. Assembly Code Example Assembly Code Example C Example Comments ldi TWCR = (1<<TWINT)|(1<<TWSTA)| (1<<TWEN) Send START condition 1 out wait1: in 2 sbrs rjmp 3 r16,TWCR r16,TWINT wait1 while (!(TWCR & (1<<TWINT))) ; Wait for TWINT flag set. This indicates that the START condition has been transmitted in andi cpi `brne r16,TWSR r16, 0xF8 r16, START ERROR if ((TWSR & 0xF8) != START) ERROR(); Check value of TWI status register. Mask prescaler bits. If status different from START go to ERROR ldi out ldi out r16, SLA_W TWDR, r16 r16, (1<<TWINT) | (1<<TWEN) TWCR, r16 TWDR = SLA_W; TWCR = (1<<TWINT) | (1<<TWEN); Load SLA_W into TWDR register. Clear TWINT bit in TWCR to start transmission of address while (!(TWCR & (1<<TWINT))) ; Wait for TWINT flag set. This indicates that the SLA+W has been transmitted, and ACK/NACK has been received. wait2: in 4 sbrs rjmp 204 r16, (1<<TWINT)|(1<<TWSTA)| (1<<TWEN) TWCR, r16 r16,TWCR r16,TWINT wait2 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Table 5-90. Assembly Code Example (Continued) 5 Assembly Code Example C Example Comments in andi cpi brne r16,TWSR r16, 0xF8 r16, MT_SLA_ACK ERROR if ((TWSR & 0xF8) != MT_SLA_ACK) ERROR(); Check value of TWI status register. Mask prescaler bits. If status different from MT_SLA_ACK go to ERROR ldi out ldi out r16, DATA TWDR, r16 r16, (1<<TWINT) | (1<<TWEN) TWCR, r16 TWDR = DATA; TWCR = (1<<TWINT) | (1<<TWEN); wait3: in 6 sbrs rjmp in andi cpi 7 brne ldi out Load DATA into TWDR register. Clear TWINT bit in TWCR to start transmission of data while (!(TWCR & (1<<TWINT))) ; Wait for TWINT flag set. This indicates that the DATA has been transmitted, and ACK/NACK has been received. r16,TWSR r16, 0xF8 r16, MT_DATA_ACK ERROR if ((TWSR & 0xF8) != MT_DATA_ACK) ERROR(); Check value of TWI status register. Mask prescaler bits. If status different from MT_DATA_ACK go to ERROR r16, (1<<TWINT)|(1<<TWEN)| (1<<TWSTO) TWCR, r16 TWCR = (1<<TWINT)|(1<<TWEN)| (1<<TWSTO); r16,TWCR r16,TWINT wait3 Transmit STOP condition 5.19.8 Transmission Modes The TWI can operate in one of four major modes. These are named master transmitter (MT), master receiver (MR), slave transmitter (ST) and slave receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used. It is the application software that decides which modes are legal. The following sections describe each of these modes. Possible status codes are described along with figures detailing data transmission in each of the modes. These figures contain the following abbreviations: S: START condition Rs: REPEATED START condition R: Read bit (high level at SDA) W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P: STOP condition SLA: Slave Address In Figure 5-89 on page 208 to Figure 5-95 on page 218, circles are used to indicate that the TWINT flag is set. The numbers in the circles show the status code held in TWSR, with the prescaler bits masked to zero. At these points, actions must be taken by the application to continue or complete the TWI transfer. The TWI transfer is suspended until the TWINT flag is cleared by software. When the TWINT flag is set, the status code in TWSR is used to determine the appropriate software action. For each status code, the required software action and details of the following serial transfer are given in Table 5-91 on page 207 to Table 5-94 on page 217. Note that the prescaler bits are masked to zero in these tables. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 205 5.19.8.1 Master Transmitter Mode In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 5-88). In order to enter a master mode, a START condition must be transmitted. The format of the following address packet determines whether master transmitter or master receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 5-88. Data Transfer in Master Transmitter Mode VCC Device 1 Device 2 Master Transmitter Slave Receiver Device 3 ........ Device n R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE value 1 X 1 0 X 1 0 X TWEN must be set to enable the 2-wire serial interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT flag. The TWI will then test the 2-wire serial bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT flag is set by hardware, and the status code in TWSR will be 0x08 (see Table 5-91 on page 207). In order to enter MT mode, SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE value 1 X 0 0 X 1 0 X When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in master mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes is detailed in Table 5-91 on page 207. When SLA+W has been successfully transmitted, a data packet should be transmitted. This is done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not, the access will be discarded, and the write collision bit (TWWC) will be set in the TWCR register. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE value 1 X 0 0 X 1 0 X This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR: 206 TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE value 1 X 0 1 X 1 0 X ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 A REPEATED START condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE value 1 X 1 0 X 1 0 X After a repeated START condition (state 0x10) the 2-wire serial interface can access the same slave again, or a new slave without transmitting a STOP condition. Repeated START enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control of the bus. Table 5-91. Status codes for Master Transmitter Mode Status Code (TWSR) Status of the 2-wire Prescaler Serial Bus and 2-wire Serial Interface Bits Hardware are 0 0x08 0x10 To/from TWDR STA Load SLA+W 0 A repeated START condition has been transmitted Load SLA+W or 0 Load SLA+R SLA+W has been transmitted; ACK has been received SLA+W has been transmitted; NOT ACK has been received 0x20 Data byte has been transmitted; ACK has been received 0x28 Data byte has been transmitted; NOT ACK has been received 0x38 To TWCR A START condition has been transmitted 0x18 0x30 Application Software Response STO TWINT TWEA Next Action Taken by TWI Hardware 1 X SLA+W will be transmitted; ACK or NOT ACK will be received 0 1 X 0 0 1 X SLA+W will be transmitted; ACK or NOT ACK will be received SLA+R will be transmitted; logic will switch to master receiver mode Load data byte or 0 0 1 X No TWDR action or No TWDR action or 1 0 0 1 1 1 X X No TWDR action 1 1 1 X Load data byte or 0 0 1 X No TWDR action or No TWDR action or 1 0 0 1 1 1 X X No TWDR action 1 1 1 X Load data byte or 0 0 1 X No TWDR action or No TWDR action or 1 0 0 1 1 1 X X No TWDR action 1 1 1 X Load data byte or 0 0 1 X No TWDR action or No TWDR action or 1 0 0 1 1 1 X X No TWDR action 1 1 1 X 0 0 1 X 1 0 1 X Arbitration lost in SLA+W No TWDR action or or data bytes No TWDR action 0 Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset 2-wire serial bus will be released and not addressed Slave mode entered A START condition will be transmitted when the bus becomes free ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 207 Figure 5-89. Formats and States in the Master Transmitter Mode MT Successfull transmission to a slave receiver S SLA W $08 A DATA $18 A P $28 Next transfer started with a repeated start condition RS SLA W $10 Not acknowledge received after the slave address A P R $20 MR Not acknowledge received after a data byte A P $30 Arbitration lost in slave address or data byte A or A Other master continues A or A $38 Arbitration lost and addressed as slave A $68 From master to slave From slave to master 208 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Other master continues $38 Other master continues $78 To corresponding states in slave mode $B0 DATA A n Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the 2-wire serial bus. The prescaler bits are zero or masked to zero 5.19.8.2 Master Receiver Mode In the master receiver mode, a number of data bytes are received from a slave transmitter (slave see Figure 5-90). In order to enter a master mode, a START condition must be transmitted. The format of the following address packet determines whether master transmitter or master receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 5-90. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 Master Receiver Slave Transmitter Device 3 ........ Device n R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE value 1 X 1 0 X 1 0 X TWEN must be written to one to enable the 2-wire serial interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT flag. The TWI will then test the 2-wire serial bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT flag is set by hardware, and the status code in TWSR will be 0x08 (see Table 5-91 on page 207). In order to enter MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE value 1 X 0 0 X 1 0 X When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in master mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes is detailed in Table 5-92 on page 210. Received data can be read from the TWDR register when the TWINT flag is set high by hardware. This scheme is repeated until the last byte has been received. After the last byte has been received, the MR should inform the ST by sending a NACK after the last received data byte. The transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE value 1 X 0 1 X 1 0 X A REPEATED START condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE value 1 X 1 0 X 1 0 X ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 209 After a repeated START condition (state 0x10) the 2-wire serial interface can access the same slave again, or a new slave without transmitting a STOP condition. Repeated START enables the Master to switch between slaves, master transmitter mode and master receiver mode without losing control over the bus. Table 5-92. Status codes for Master Receiver Mode Status Code (TWSR) Status of the 2-wire Prescaler Serial Bus and 2-wire Serial Interface Bits Hardware are 0 0x08 0x10 0x38 0x40 0x48 0x50 0x58 210 Application Software Response To TWCR To/from TWDR STA STO TWINT TWEA Next Action Taken by TWI Hardware A START condition has been transmitted Load SLA+R 0 0 1 X SLA+R will be transmitted ACK or NOT ACK will be received A repeated START condition has been transmitted Load SLA+R or 0 0 1 X Load SLA+W 0 0 1 X SLA+R will be transmitted ACK or NOT ACK will be received SLA+W will be transmitted logic will switch to master transmitter mode Arbitration lost in SLA+R No TWDR action or or NOT ACK bit No TWDR action 0 0 1 X 1 0 1 X SLA+R has been transmitted; ACK has been received No TWDR action or 0 0 1 0 No TWDR action 0 0 1 1 SLA+R has been transmitted; NOT ACK has been received No TWDR action or No TWDR action or 1 0 0 1 1 1 X X No TWDR action 1 1 1 X Data byte has been Read data byte or received; ACK has been returned Read data byte 0 0 1 0 0 0 1 1 Data byte has been Read data byte or received; NOT ACK has Read data byte or been returned Read data byte 1 0 0 1 1 1 X X 1 1 1 X ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 2-wire serial bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Repeated START will be transmitted STOP condition will be transmitted and TWSTO flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Repeated START will be transmitted STOP condition will be transmitted and TWSTO flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset Figure 5-91. Formats and States in the Master Receiver Mode MR Successfull reception from a slave receiver S SLA $08 R A DATA $40 A DATA $50 A P $58 Next transfer started with a repeated start condition RS SLA R $10 Not acknowledge received after the slave address A P W $48 MT Arbitration lost in slave address or data byte A or A Other master continues A or A $38 Arbitration lost and addressed as slave A $68 From master to slave From slave to master Other master continues $38 Other master continues $78 To corresponding states in slave mode $B0 DATA A n Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the 2-wire serial bus. The prescaler bits are zero or masked to zero ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 211 5.19.8.3 Slave Receiver Mode In the slave receiver mode, a number of data bytes are received from a Master Transmitter (see Figure 5-92). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 5-92. Data Transfer in Slave Receiver Mode VCC Device 1 Device 2 Slave Receiver Master Transmitter Device 3 ........ Device n R1 R2 SDA SCL To initiate the slave receiver mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device's Own Slave Address The upper 7 bits are the address to which the 2-wire serial interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE value 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device's own slave address or the general call address. TWSTA and TWSTO must be written to zero. When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is "0" (write), the TWI will operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received, the TWINT flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 5-93 on page 213. The slave receiver mode may also be entered if arbitration is lost while the TWI is in the master mode (see states 0x68 and 0x78). If the TWEA bit is reset during a transfer, the TWI will return a "Not Acknowledge" ("1") to SDA after the next received data byte. This can be used to indicate that the slave is not able to receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave address. However, the 2-wire serial bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire serial bus. In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the 2-wire serial bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock low during the wake up and until the TWINT flag is cleared (by writing it to one). Further data reception will be carried out as normal, with the AVR(R) clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note that the 2-wire serial interface data register - TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. 212 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Table 5-93. Status Codes for Slave Receiver Mode Status Code (TWSR) Prescaler Bits are 0 Application Software Response To TWCR Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware To/from TWDR STA STO TWINT TWEA Next Action Taken by TWI Hardware No TWDR action or X 0 1 0 No TWDR action X 0 1 1 X 0 1 0 0x68 Arbitration lost in SLA+R/W No TWDR action or as master; own SLA+W has been received; ACK has No TWDR action been returned X 0 1 1 No TWDR action or X 0 1 0 0x70 General call address has been received; ACK has been returned No TWDR action X 0 1 1 X 0 1 0 0x78 Arbitration lost in SLA+R/W No TWDR action or as Master; General call address has been received; No TWDR action ACK has been returned X 0 1 1 Read data byte or X 0 1 0 0x80 Previously addressed with own SLA+W; data has been received; ACK has been returned Read data byte X 0 1 1 Previously addressed with own SLA+W; data has been received; NOT ACK has been returned Read data byte or 0 0 1 0 Read data byte or 0 0 1 1 Read data byte or 1 0 1 0 Read data byte 1 0 1 1 Read data byte or X 0 1 0 Read data byte X 0 1 1 0x60 Own SLA+W has been received; ACK has been returned 0x88 0x90 Previously addressed with general call; data has been received; ACK has been returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 213 Table 5-93. Status Codes for Slave Receiver Mode (Continued) Status Code (TWSR) Prescaler Bits are 0 Application Software Response To TWCR Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Previously addressed with general call; data has been received; NOT ACK has been returned To/from TWDR STA STO TWINT TWEA Next Action Taken by TWI Hardware Read data byte or 0 0 1 0 Read data byte or 0 0 1 1 Read data byte or 1 0 1 0 Read data byte 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 0 1 1 0x98 A STOP condition or repeated START condition has been received while still addressed as Slave 0xA0 214 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 No action Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1";a START condition will be transmitted when the bus becomes free Figure 5-93. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes. All are acknowledged S SLA W A DATA $60 A DATA $80 Last data byte received is not acknowledged A P or S $80 $A0 A P or S $88 Arbitration lost as master and addressed as slave A $68 Reception of the general call address and one or more data bytes General Call A DATA A $90 $70 Last data byte received is not acknowledged DATA A P or S $90 $A0 A P or S $98 Arbitration lost as master and as slave by general call A $78 From master to slave From slave to master DATA A n Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the 2-wire serial bus. The prescaler bits are zero or masked to zero ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 215 5.19.8.4 Slave Transmitter Mode In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 5-94). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 5-94. Data Transfer in Slave Transmitter Mode VCC Device 1 Device 2 Slave Transmitter Master Receiver Device 3 ........ Device n R1 R2 SDA SCL To initiate the slave transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device's Own Slave Address The upper seven bits are the address to which the 2-wire serial interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE value 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device's own slave address or the general call address. TWSTA and TWSTO must be written to zero. When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is "1" (read), the TWI will operate in ST mode, otherwise SR mode is entered. After its own slave address and the write bit have been received, the TWINT flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 5-94 on page 217. The slave transmitter mode may also be entered if arbitration is lost while the TWI is in the master mode (see state 0xB0). If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the transfer. State 0xC0 or state 0xC8 will be entered, depending on whether the master receiver transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed Slave mode, and will ignore the master if it continues the transfer. Thus the master receiver receives all "1" as serial data. state 0xC8 is entered if the master demands additional data bytes (by transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero and expecting NACK from the master). While TWEA is zero, the TWI does not respond to its own slave address. However, the 2-wire serial bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire serial bus. In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the 2-wire serial bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake up and until the TWINT flag is cleared (by writing it to one). Further data transmission will be carried out as normal, with the AVR(R) clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note that the 2-wire serial Interface data register - TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. 216 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Table 5-94. Status Codes for Slave Transmitter Mode Status Code (TWSR) Prescaler Bits are 0 Application Software Response To TWCR Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware To/from TWDR STA Own SLA+R has been received; ACK has been returned Load data byte or X 0 1 0 Load data byte X 0 1 1 Load data byte or X 0 1 0 0xB0 Arbitration lost in SLA+R/W as Master; own SLA+R has been received; ACK has been returned Load data byte X 0 1 1 Load data byte or X 0 1 0 0xB8 Data byte in TWDR has been transmitted; ACK has been received Load data byte X 0 1 1 No TWDR action or 0 0 1 0 No TWDR action or 0 0 1 1 No TWDR action or 1 0 1 0 No TWDR action 1 0 1 1 No TWDR action or 0 0 1 0 No TWDR action or 0 0 1 1 No TWDR action or 1 0 1 0 No TWDR action 1 0 1 1 0xA8 0xC0 0xC8 Data byte in TWDR has been transmitted; NOT ACK has been received Last data byte in TWDR has been transmitted (TWEA = "0"); ACK has been received STO TWINT TWEA Next Action Taken by TWI Hardware Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode; no recognition of own SLA or GCA Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 217 Figure 5-95. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA A $A8 Arbitration lost as master and addressed as slave DATA $B8 A P or S $C0 A $B0 Last data byte transmitted. Switched to not adressed slave (TWEA = "0") A All 1's P or S $C8 From master to slave DATA From slave to master Any number of data bytes and their associated acknowledge bits A This number (contained in TWSR) corresponds to a defined state of the 2-wire serial bus. The prescaler bits are zero or masked to zero n 5.19.8.5 Miscellaneous States There are two status codes that do not correspond to a defined TWI state (see Table 5-95). Status 0xF8 indicates that no relevant information is available because the TWINT flag is not set. This occurs between other states, and when the TWI is not involved in a serial transfer. Status 0x00 indicates that a bus error has occurred during a 2-wire serial bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the TWSTO flag must set and TWINT must be cleared by writing a logic one to it. This causes the TWI to enter the not addressed slave mode and to clear the TWSTO flag (no other bits in TWCR are affected). The SDA and SCL lines are released, and no STOP condition is transmitted. Table 5-95. Miscellaneous States Status Code (TWSR) Prescaler Bits are 0 218 Application Software Response Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware To TWCR To/from TWDR 0xF8 No relevant state information available; TWINT = "0" 0x00 Bus error due to an illegal No TWDR action START or STOP condition No TWDR action ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 STA STO TWINT TWEA Next Action Taken by TWI Hardware No TWCR action 0 1 1 Wait or proceed current transfer X Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released and TWSTO is cleared. 5.19.8.6 Combining Several TWI Modes In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated. 2. The EEPROM must be instructed what location should be read. 3. The reading must be performed. 4. The transfer must be finished. Note that data is transmitted both from master to slave and vice versa. The master must instruct the slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation. If this principle is violated in a multi master system, another master can alter the data pointer in the EEPROM between steps 2 and 3, and the master will read the wrong data location. Such a change in transfer direction is accomplished by transmitting a REPEATED START between the transmission of the address byte and reception of the data. After a REPEATED START, the master keeps ownership of the bus. The following figure shows the flow in this transfer. Figure 5-96. Combining Several TWI Modes to Access a Serial EEPROM Master Transmitter S SLA + W A ADDRESS S = START A Master Receiver RS SLA + R A DATA RS = REPEATED START Transmitted from master to slave A P P = STOP Transmitted from slave to master 5.19.9 Multi-master Systems and Arbitration If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them. The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. An example of an arbitration situation is depicted below, where two masters are trying to transmit data to a slave receiver. Figure 5-97. An Arbitration Example VCC Device 1 Device 2 Device 3 Master Transmitter Master Transmitter Slave Receiver ........ Device n R1 R2 SDA SCL ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 219 Several different scenarios may arise during arbitration, as described below: Two or more masters are performing identical communication with the same slave. In this case, neither the slave nor any of the masters will know about the bus contention. Two or more masters are accessing the same slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on SDA while another master outputs a zero will lose the arbitration. Losing masters will switch to not addressed slave mode or wait until the bus is free and transmit a new START condition, depending on application software action. Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to slave mode to check if they are being addressed by the winning master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit. If they are not being addressed, they will switch to not addressed slave mode or wait until the bus is free and transmit a new START condition, depending on application software action. This is summarized in Figure 5-98. Possible status values are given in circles. Figure 5-98. Possible Status Codes Caused by Arbitration START SLA DATA Arbitration lost in SLA Own Address/General Call received No STOP Arbitration lost in DATA 38 TWI Bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free Yes Direction Write 68/78 Read B0 220 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received 5.20 Analog Comparator The analog comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the analog comparator output, ACO, is set. The comparator's output can be set to trigger the Timer/Counter1 input capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the analog comparator. The user can select interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 5-99. The power reduction ADC bit, PRADC, in Section 5.7.7.1 "Power Reduction Register - PRR" on page 58 must be disabled by writing a logical zero to be able to use the ADC input MUX. Figure 5-99. Analog Comparator Block Diagram(2) VCC Bandgap Reference ACBG ACD ACIE AIN0 + Analog Comparator IRQ Interrupt Select - ACI AIN1 ACIS1 ACIS0 ACIC ACME ADEN To T/C1 Capture Trigger MUX ACO ADC Multiplexer Output(1) Notes: 1. See Table 5-97 on page 223. 2. Refer to Table 5-38 on page 89 for analog comparator pin placement. 5.20.1 ADC Control and Status Register B - ADCSRB Bit 7 6 5 4 3 2 1 0 - ACME - Read/Write R R/W R - - ADTS2 ADTS1 ADTS0 R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB * Bit 6 - ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the analog comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the analog comparator. For a detailed description of this bit (see Section 5.20.3 "Analog Comparator Multiplexed Input" on page 223). ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 221 5.20.2 Analog Comparator Control and Status Register - ACSR Bit 7 6 5 4 3 2 1 0 ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 N/A 0 0 0 0 0 ACSR * Bit 7 - ACD: Analog Comparator Disable When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the analog comparator interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. * Bit 6 - ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the analog comparator. When this bit is cleared, AIN0 is applied to the positive input of the analog comparator (see Section 5.8.8 "Internal Voltage Reference" on page 65). * Bit 5 - ACO: Analog Comparator Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles. * Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The analog comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. * Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the status register is set, the analog comparator interrupt is activated. When written logic zero, the interrupt is disabled. * Bit 2 - ACIC: Analog Comparator Input Capture Enable When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 input capture interrupt. When written logic zero, no connection between the analog comparator and the input capture function exists. To make the comparator trigger the Timer/Counter1 input capture interrupt, the ICIE1 bit in the timer interrupt mask register (TIMSK1) must be set. * Bits 1, 0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the analog comparator interrupt. The different settings are shown in Table 5-96 on page 222. Table 5-96. ACIS1/ACIS0 Settings ACIS1 ACIS0 0 0 Interrupt Mode Comparator interrupt on output toggle. 0 1 Reserved 1 0 Comparator interrupt on falling output edge. 1 1 Comparator interrupt on rising output edge. When changing the ACIS1/ACIS0 bits, the analog comparator interrupt must be disabled by clearing its interrupt enable bit in the ACSR register. Otherwise an interrupt can occur when the bits are changed. 222 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.20.3 Analog Comparator Multiplexed Input It is possible to select any of the ADC7..0 pins to replace the negative input to the analog comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the analog comparator multiplexer enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..0 in ADMUX select the input pin to replace the negative input to the analog comparator, as shown in Table 5-97. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the analog comparator. Table 5-97. Analog Comparator Multiplexed Input ACME ADEN MUX2..0 Analog Comparator Negative Input 0 x xxx AIN1 1 1 xxx AIN1 1 0 000 ADC0 1 0 001 ADC1 1 0 010 ADC2 1 0 011 ADC3 1 0 100 ADC4 1 0 101 ADC5 1 0 110 ADC6 1 0 111 ADC7 5.20.3.1 Digital Input Disable Register 1 - DIDR1 Bit 7 6 5 4 3 2 1 0 - - - - - - AIN1D AIN0D Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 DIDR1 * Bit 7..2 - Res: Reserved Bits These bits are unused bits in the Atmel(R) ATA6612C/ATA6613C, and will always read as zero. * Bit 1, 0 - AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 223 5.21 Analog-to-Digital Converter 5.21.1 Features 10-bit resolution 0.5LSB integral non-linearity 2LSB absolute accuracy 13 - 260s conversion time Up to 15kSPS at maximum resolution 6 multiplexed single ended input channels 2 additional multiplexed single ended input channels (TQFP and QFN package only) Optional left adjustment for ADC result readout 0 to VCC ADC input voltage range Selectable 1.1V ADC reference voltage Free running or single conversion mode Interrupt on ADC conversion complete Sleep mode noise canceler The Atmel(R) ATA6612C/ATA6613C features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel analog multiplexer which allows eight single-ended voltage inputs constructed from the pins of Port A. The single-ended voltage inputs refer to 0V (GND). The ADC contains a sample and hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 5-100 on page 225. The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than 0.3V from VCC. See the paragraph Section 5.21.5 "ADC Noise Canceler" on page 231 on how to connect this pin. Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. The voltage reference may be externally decoupled at the AREF pin by a capacitor for better noise performance. The power reduction ADC bit, PRADC, in Section 5.7.7.1 "Power Reduction Register - PRR" on page 58 must be disabled by writing a logical zero to enable the ADC. 224 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Figure 5-100.Analog to Digital Converter Block Schematic Operation ADC Conversion Complete IRQ ADC[9:0] ADPS0 ADPS1 ADPS2 Conversion Logic Sample and Hold Comparator 10-bit DAC AREF 0 ADC Data Register (ADCH/ADCL) Prescaler Channel Selection Internal 1.1V Reference ADIF ADFR ADSC ADEN MUX0 MUX Decoder AVCC 15 ADC CTRL and Status Register (ADCSRA) MUX1 MUX2 MUX3 REFS0 ADLAR REFS1 ADC Multiplexer Select (ADMUX) ADIE ADIF 8-bit Data Bus + GND Bandgap Reference ADC7 ADC6 ADC5 Input MUX ADC Multiplexer Output ADC4 ADC3 ADC2 ADC1 ADC0 The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1LSB. Optionally, AVCC or an internal 1.1V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity. The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. The ADC is enabled by setting the ADC enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 225 The ADC generates a 10-bit result which is presented in the ADC data registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. 5.21.2 Starting a Conversion A single conversion is started by disabling the power reduction ADC bit, PRADC, in Section 5.7.7.1 "Power Reduction Register - PRR" on page 58 by writing a logical zero to it and writing a logical one to the ADC start conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. Alternatively, a conversion can be triggered automatically by various sources. Auto triggering is enabled by setting the ADC auto trigger enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC trigger select bits, ADTS in ADCSRB (See description of the ADTS bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. Figure 5-101. ADC Auto Trigger Logic ADTS[2:0] Prescaler ADIF ADATE START CLKADC SOURCE 1 . . . . SOURCE n Conversion Logic Edge Detector ADSC Using the ADC interrupt flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in free running mode, constantly sampling and updating the ADC data register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC interrupt flag, ADIF is cleared or not. If auto triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. 226 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.21.3 Prescaling and Conversion Timing Figure 5-102. ADC Prescaler Reset CK/64 CK/128 CK/32 CK/8 CK/16 CK/4 7-bit ADC Prescaler CK/2 ADEN START CKIO ADPS0 ADPS1 ADPS2 ADC Clock Source By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz to get maximum resolution. If a lower resolution than 10bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate. The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC data registers, and ADIF is set. In single conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. When auto triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. In free running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times (see Table 5-98 on page 229). ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 227 Figure 5-103. ADC Timing Diagram, First Conversion (Single Conversion Mode) Next Conversion First Conversion Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result MUX and REFS Update Conversion Complete Sample and Hold MUX and REFS Update Figure 5-104. ADC Timing Diagram, Single Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 9 Next Conversion 10 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample and Hold MUX and REFS Update 228 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Conversion Complete MUX and REFS Update Figure 5-105. ADC Timing Diagram, Auto Triggered Conversion Next Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample and Hold Prescaler Reset Prescaler Reset Conversion Complete MUX and REFS Update Figure 5-106. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 13 Next Conversion 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample and Hold Conversion Complete MUX and REFS Update Table 5-98. ADC Conversion Time Sample and Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 2 13.5 Condition Auto triggered conversions ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 229 5.21.4 Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written. If auto triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: a. When ADATE or ADEN is cleared. b. During conversion, minimum one ADC clock cycle after the trigger event. c. After a conversion, before the Interrupt Flag used as trigger source is cleared. When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. 5.21.4.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. In free running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. 5.21.4.2 ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 1.1V reference, or external AREF pin. AVCC is connected to the ADC through a passive switch. The internal 1.1V reference is generated from the internal bandgap reference (VBG) through an internal amplifier. In either case, the external AREF pin is directly connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground. VREF can also be measured at the AREF pin with a high impedant voltmeter. Note that VREF is a high impedant source, and only a capacitive load should be connected in a system. If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user may switch between AVCC and 1.1V as reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. 230 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.21.5 ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC noise reduction and Idle mode. To make use of this feature, the following procedure should be used: a. Make sure that the ADC is enabled and is not busy converting. Single conversion mode must be selected and the ADC conversion complete interrupt must be enabled. b. Enter ADC noise reduction mode (or idle mode). The ADC will start a conversion once the CPU has been halted. c. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC conversion complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC conversion complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note that the ADC will not be automatically turned off when entering other sleep modes than idle mode and ADC noise reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption. 5.21.5.1 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 5-107 An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately 10 k or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. Signal components higher than the nyquist frequency (fADC/2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 5-107. Analog Input Circuitry IIH ADCn 1 to 100k IIL CS/H = 14pF VCC/2 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 231 5.21.5.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b. The AVCC pin on the device should be connected to the digital VCC supply voltage via an LC network as shown in Figure 5-108. c. Use the ADC noise canceler function to reduce induced noise from the CPU. d. If any ADC [3..0] port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. However, using the 2-wire interface (ADC4 and ADC5) will only affect the conversion on ADC4 and ADC5 and not the other ADC channels. Analog Ground Plane PC2 (ADC2) PC3 (ADC3) PC4 (ADC4/SDA) PC5 (ADC5/SCL) VCC GND Figure 5-108. ADC Power Connections PC1 (ADC1) PC0 (ADC0) ADC7 ADC6 AVCC PB5 232 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 100nF AREF 10mH GND 5.21.5.3 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5LSB). Ideal value: 0 LSB. Figure 5-109. Offset Error Output Code Ideal ADC Actual ADC Offset Error VREF Input Voltage Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5LSB below maximum). Ideal value: 0LSB Figure 5-110. Gain Error Output Code Gain Error Ideal ADC Actual ADC VREF Input Voltage ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 233 Integral non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0LSB. Figure 5-111. Integral Non-linearity (INL) INL Output Code Ideal ADC Actual ADC VREF Input Voltage Differential non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1LSB). Ideal value: 0LSB. Figure 5-112. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 234 VREF Input Voltage Quantization error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1LSB wide) will code to the same value. Always 0.5LSB. Absolute accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: 0.5LSB. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.21.6 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC result registers (ADCL, ADCH). For single ended conversion, the result is V IN x 1024 ADC = --------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 5-99 and Table 5-100 on page 236). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB. 5.21.6.1 ADC Multiplexer Selection Register - ADMUX Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR - MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADMUX * Bit 7:6 - REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 5-99. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. Table 5-99. Voltage Reference Selections for ADC REFS1 REFS0 Voltage Reference Selection 0 0 AREF, internal Vref turned off 0 1 AVCC with external capacitor at AREF pin 1 0 Reserved 1 1 Internal 1.1V voltage reference with external capacitor at AREF pin * Bit 5 - ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit (see Section 5.21.6.3 "The ADC Data Register - ADCL and ADCH" on page 237). * Bit 4 - Res: Reserved Bit This bit is an unused bit in the Atmel(R) ATA6612C/ATA6613C, and will always read as zero. * Bits 3:0 - MUX3:0: Analog Channel Selection Bits The value of these bits selects which analog inputs are connected to the ADC. See Table 5-100 on page 236 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 235 Table 5-100. Input Channel Selections MUX3..0 Single Ended Input 0000 ADC0 0001 ADC1 0010 ADC2 0011 ADC3 0100 ADC4 0101 ADC5 0110 ADC6 0111 ADC7 1000 (reserved) 1001 (reserved) 1010 (reserved) 1011 (reserved) 1100 (reserved) 1101 (reserved) 1110 1.1V (VBG) 1111 0V (GND) 5.21.6.2 ADC Control and Status Register A - ADCSRA Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRA * Bit 7 - ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. * Bit 6 - ADSC: ADC Start Conversion In single conversion mode, write this bit to one to start each conversion. In free running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. * Bit 5 - ADATE: ADC Auto Trigger Enable When this bit is written to one, auto triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC trigger select bits, ADTS in ADCSRB. * Bit 4 - ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated. The ADC conversion complete interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. 236 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 * Bit 3 - ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated. * Bits 2:0 - ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. Table 5-101. ADC Prescaler Selections ADPS2 ADPS1 ADPS0 Division Factor 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 5.21.6.3 The ADC Data Register - ADCL and ADCH ADLAR = 0 Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 - - - - - - ADC9 ADC8 ADCH ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADLAR = 1 Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH ADC1 ADC0 - - - - - - ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC data register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. * ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in Section 5.21.6 "ADC Conversion Result" on page 235. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 237 5.21.6.4 ADC Control and Status Register B - ADCSRB Bit 7 6 5 4 3 2 1 0 - ACME - - - ADTS2 ADTS1 ADTS0 Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB * Bit 7, 5:3 - Res: Reserved Bits These bits are reserved for future use. To ensure compatibility with future devices, these bits must be written to zero when ADCSRB is written. * Bit 2:0 - ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected interrupt flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to free running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC interrupt flag is set. Table 5-102. ADC Auto Trigger Source Selections ADTS2 ADTS1 ADTS0 Trigger Source 0 0 0 Free running mode 0 0 1 Analog comparator 0 1 0 External interrupt request 0 0 1 1 Timer/Counter0 compare match A 1 0 0 Timer/Counter0 overflow 1 0 1 Timer/Counter1 compare match B 1 1 0 Timer/Counter1 overflow 1 1 1 Timer/Counter1 capture event 5.21.6.5 Digital Input Disable Register 0 - DIDR0 Bit 7 6 5 4 3 2 1 0 - - ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DIDR0 * Bits 7:6 - Res: Reserved Bits These bits are reserved for future use. To ensure compatibility with future devices, these bits must be written to zero when DIDR0 is written. * Bit 5..0 - ADC5D..ADC0D: ADC5..0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC5..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. Note that ADC pins ADC7 and ADC6 do not have digital input buffers, and therefore do not require digital input disable bits. 238 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.22 debugWIRE On-chip Debug System 5.22.1 Features Complete program flow control Emulates all on-chip functions, both digital and analog, except RESET pin Real-time operation Symbolic debugging support (both at C and assembler source level, or for other HLLs) Unlimited number of program break points (using software break points) Non-intrusive operation Electrical characteristics identical to real device Automatic configuration system High-speed operation Programming of non-volatile memories 5.22.2 Overview The debugWIRE on-chip debug system uses a one-wire, bi-directional interface to control the program flow, execute AVR(R) instructions in the CPU and to program the different non-volatile memories. 5.22.3 Physical Interface When the debugWIRE enable (DWEN) fuse is programmed and lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. Figure 5-113. The debugWIRE Setup 2.7 - 5.5V VCC dW dW (RESET) GND Figure 5-113 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL fuses. When designing a system where debugWIRE will be used, the following observations must be made for correct operation: Pull-up resistors on the dW/(RESET) line must not be smaller than 10k. The pull-up resistor is not required for debugWIRE functionality. Connecting the RESET pin directly to VCC will not work. Capacitors connected to the RESET pin must be disconnected when using debugWire. All external reset sources must be disconnected. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 239 5.22.4 Software Break Points debugWIRE supports program memory break points by the AVR(R) break instruction. Setting a break point in AVR Studio(R) will insert a BREAK instruction in the program memory. The instruction replaced by the BREAK instruction will be stored. When program execution is continued, the stored instruction will be executed before continuing from the program memory. A break can be inserted manually by putting the BREAK instruction in the program. The flash must be re-programmed each time a break point is changed. This is automatically handled by AVR studio through the debugWIRE interface. The use of break points will therefore reduce the flash data retention. Devices used for debugging purposes should not be shipped to end customers. 5.22.5 Limitations of debugWIRE The debugWIRE communication pin (dW) is physically located on the same pin as external reset (RESET). An external reset source is therefore not supported when the debugWIRE is enabled. The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e., when the program in the CPU is running. When the CPU is stopped, care must be taken while accessing some of the I/O registers via the debugger (AVR Studio). A programmed DWEN fuse enables some parts of the clock system to be running in all sleep modes. This will increase the power consumption while in sleep. Thus, the DWEN fuse should be disabled when debugWire is not used. 5.22.6 debugWIRE Related Register in I/O Memory The following section describes the registers used with the debugWire. 5.22.6.1 debugWire Data Register - DWDR Bit 7 6 5 4 Read/Write R/W R/W R/W R/W Initial Value 0 0 0 0 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 DWDR[7:0] DWDR The DWDR register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. 5.23 Boot Loader Support - Read-While-Write Self-Programming, Atmel ATA6612C and ATA6613C In Atmel(R) ATA6612C and ATA6613C, the boot loader support provides a real read-while-write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a flash-resident boot loader program. The boot loader program can use any available data interface and associated protocol to read code and write (program) that code into the flash memory, or read the code from the program memory. The program code within the boot loader section has the capability to write into the entire flash, including the boot loader memory. The boot loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the boot loader memory is configurable with fuses and the boot loader has two separate sets of boot lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. 5.23.1 Boot Loader Features Note: 240 Read-while-write self-programming Flexible boot memory size High security (separate boot lock bits for a flexible protection) Separate fuse to select reset vector Optimized page(1) size Code efficient algorithm Efficient read-modify-write support 1. A page is a section in the flash consisting of several bytes (see Table 5-124 on page 258) used during programming. The page organization does not affect normal operation. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.23.2 Application and Boot Loader Flash Sections The flash memory is organized in two main sections, the application section and the boot loader section (see Figure 5-115 on page 242). The size of the different sections is configured by the BOOTSZ fuses as shown in Table 5-108 on page 251 and Figure 5-115 on page 242. These two sections can have different level of protection since they have different sets of lock bits. 5.23.2.1 Application Section The Application section is the section of the flash that is used for storing the application code. The protection level for the application section can be selected by the application boot lock bits (boot lock bits 0), see Table 5-104 on page 243. The application section can never store any boot loader code since the SPM instruction is disabled when executed from the application section. 5.23.2.2 BLS - Boot Loader Section While the application section is used for storing the application code, the The boot loader software must be located in the BLS since the SPM instruction can initiate a programming when executing from the BLS only. The SPM instruction can access the entire flash, including the BLS itself. The protection level for the boot loader section can be selected by the boot loader lock bits (boot lock bits 1), see Table 5-105 on page 243. 5.23.3 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports read-while-write or if the CPU is halted during a boot loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ fuses as described above, the flash is also divided into two fixed sections, the read-while-write (RWW) section and the No read-whilewrite (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 5-109 on page 251 and Figure 5115 on page 242. The main difference between the two sections is: When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation. When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation. Note that the user software can never read any code that is located inside the RWW section during a boot loader software operation. The syntax "read-while-write section" refers to which section that is being programmed (erased or written), not which section that actually is being read during a boot loader software update. 5.23.3.1 RWW - Read-While-Write Section If a boot loader software update is programming a page inside the RWW section, it is possible to read code from the flash, but only code that is located in the NRWW section. During an on-going programming, the software must ensure that the RWW section never is being read. If the user software is trying to read code that is located inside the RWW section (i.e., by a call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown state. To avoid this, the interrupts should either be disabled or moved to the boot loader section. The boot loader section is always located in the NRWW section. The RWW section busy bit (RWWSB) in the store program memory control and status register (SPMCSR) will be read as logical one as long as the RWW section is blocked for reading. After a programming is completed, the RWWSB must be cleared by software before reading code located in the RWW section. See Section 5.23.5.1 "Store Program Memory Control and Status Register - SPMCSR" on page 244 for details on how to clear RWWSB. 5.23.3.2 NRWW - No Read-While-Write Section The code located in the NRWW section can be read when the boot loader software is updating a page in the RWW section. When the boot loader code updates the NRWW section, the CPU is halted during the entire page erase or page write operation. Table 5-103. Read-While-Write Features Which Section does the Z-pointer Address Which Section Can be Read During the Programming? During Programming? Is the CPU Halted? Read-While-Write Supported? RWW section NRWW section No Yes NRWW section None Yes No ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 241 Figure 5-114. Read-While-Write versus No Read-While-Write Read While Write (RWW) Section Z-Pointer Addresses NRWW Section Z-Pointer Addresses RWW Section No Read-While-Write (RWW) Section CPU is Halted During the Operation Code located in NRWW Section can be Read During the Operation Figure 5-115. Memory Sections Program Memory BOOTSZ = '11' Program Memory BOOTSZ = '10' Read-While-Write Section Application Flash Section End RWW Start NRWW Application Flash Section Boot Loader Flash Section 0x0000 End Application Start Boot Loader Flashend No Read-WhileWrite Section No Read-WhileWrite Section Read-While-Write Section 0x0000 Program Memory BOOTSZ = '01' Application Flash Section End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend Program Memory BOOTSZ = '00' Note: 242 1. Read-While-Write Section 0x0000 Application Flash Section End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend No Read-WhileWrite Section No Read-WhileWrite Section Read-While-Write Section 0x0000 Application Flash Section End RWW, End Application Start NRWW, Start Boot Loader Boot Loader Flash Section The parameters in the figure above are given in Table 5-108 on page 251. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Flashend 5.23.4 Boot Loader Lock Bits If no boot loader capability is needed, the entire flash is available for application code. The boot loader has two separate sets of boot lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. The user can select: To protect the entire flash from a software update by the MCU. To protect only the boot loader flash section from a software update by the MCU. To protect only the application flash section from a software update by the MCU. Allow software update in the entire flash. See Table 5-104 and Table 5-105 for further details. The boot lock bits can be set in software and in serial or parallel programming mode, but they can be cleared by a chip erase command only. The general write lock (Lock bit mode 2) does not control the programming of the flash memory by SPM instruction. Similarly, the general read/write lock (Lock bit mode 1) does not control reading nor writing by LPM/SPM, if it is attempted. Table 5-104. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the application section. 2 1 0 SPM is not allowed to write to the application section. 0 SPM is not allowed to write to the application section, and LPM executing from the boot loader section is not allowed to read from the application section. If interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 3 4 Note: 1. 0 Protection LPM executing from the boot loader section is not allowed to read from the application section. If interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. "1" means unprogrammed, "0" means programmed 0 1 Table 5-105. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1) BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the boot loader section. 2 1 0 SPM is not allowed to write to the boot loader section. 0 SPM is not allowed to write to the boot loader section, and LPM executing from the application section is not allowed to read from the boot loader section. If interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 3 4 Note: 1. 0 Protection LPM executing from the application section is not allowed to read from the boot loader section. If interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. "1" means unprogrammed, "0" means programmed 0 1 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 243 5.23.5 Entering the Boot Loader Program Entering the boot loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively, the boot reset fuse can be programmed so that the reset vector is pointing to the boot flash start address after a reset. In this case, the boot loader is started after a reset. After the application code is loaded, the program can start executing the application code. Note that the fuses cannot be changed by the MCU itself. This means that once the boot reset fuse is programmed, the reset vector will always point to the boot loader reset and the fuse can only be changed through the serial or parallel programming interface. Table 5-106. Boot Reset Fuse(1) BOOTRST Reset Address 1 0 1. Note: Reset vector = application reset (address 0x0000) Reset vector = boot loader reset (see Table 5-108 on page 251) "1" means unprogrammed, "0" means programmed 5.23.5.1 Store Program Memory Control and Status Register - SPMCSR The store program memory control and status register contains the control bits needed to control the boot loader operations. Bit 7 6 SPMIE RWWSB 5 - 4 3 2 1 0 RWWSRE BLBSET PGWRT PGERS SELFPRGEN SPMCSR Read/Write R/W R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 * Bit 7 - SPMIE: SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the status register is set (one), the SPM ready interrupt will be enabled. The SPM ready interrupt will be executed as long as the SELFPRGEN bit in the SPMCSR register is cleared. * Bit 6 - RWWSB: Read-While-Write Section Busy When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated. * Bit 5 - Res: Reserved Bit This bit is a reserved bit in the Atmel(R) ATA6612C/ATA6613C and always read as zero. * Bit 4 - RWWSRE: Read-While-Write Section Read Enable When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SELFPRGEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while the flash is busy with a page erase or a page write (SELFPRGEN is set). If the RWWSRE bit is written while the flash is being loaded, the flash load operation will abort and the data loaded will be lost. * Bit 3 - BLBSET: Boot Lock Bit Set If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles sets boot lock bits and memory lock bits, according to the data in R0. The data in R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the SPMCSR register, will read either the lock bits or the fuse bits (depending on Z0 in the Z-pointer) into the destination register. See Section 5.23.7.9 "Reading the Fuse and Lock Bits from Software" on page 248 for details. 244 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 * Bit 2 - PGWRT: Page Write If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. * Bit 1 - PGERS: Page Erase If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. * Bit 0 - SELFPRGEN: Self Programming Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SELFPRGEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SELFPRGEN bit remains high until the operation is completed. Writing any other combination than "10001", "01001", "00101", "00011" or "00001" in the lower five bits will have no effect. 5.23.6 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. Bit 15 14 13 12 11 10 9 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 7 6 5 4 3 2 1 0 Since the flash is organized in pages (see Table 5-124 on page 258), the program counter can be treated as having two different sections. One section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. This is1 shown in Figure 5-116 on page 246. Note that the page erase and page write operations are addressed independently. Therefore it is of major importance that the boot loader software addresses the same page in both the page erase and page write operation. Once a programming operation is initiated, the address is latched and the Z-pointer can be used for other operations. The only SPM operation that does not use the Z-pointer is setting the boot loader lock bits. The content of the Z-pointer is ignored and will have no effect on the operation. The LPM instruction does also use the Z-pointer to store the address. Since this instruction addresses the flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 245 Figure 5-116. Addressing the Flash During SPM(1) BIT 15 ZPCMSB ZPAGEMSB 1 0 0 Z-REGISTER PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PAGE ADDRESS WITHIN THE FLASH PCWORD WORD ADDRESS WITHIN A PAGE Program Memory Page Page Instruction Word PCWORD[PAGEMSB:0] 00 01 02 PAGEEND Note: 1. The different variables used in Figure 5-116 are listed in Table 5-110 on page 251. 5.23.7 Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the page erase command or between a page erase and a page write operation: Alternative 1, fill the buffer before a page erase Fill temporary page buffer Perform a page erase Perform a page write Alternative 2, fill the buffer after page erase Perform a page erase Fill temporary page buffer Perform a page write If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1, the boot loader provides an effective read-modifywrite feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the page erase and page write operation is addressing the same page. See Section 5.23.7.12 "Simple Assembly Code Example for a Boot Loader" on page 249 for an assembly code example. 5.23.7.1 Performing Page Erase by SPM To execute page erase, set up the address in the Z-pointer, write "X0000011" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. Page erase to the RWW section: The NRWW section can be read during the page erase. 246 Page erase to the NRWW section: The CPU is halted during the operation. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.23.7.2 Filling the Temporary Buffer (Page Loading) To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write "00000001" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used to address the data in the temporary buffer. The temporary buffer will auto-erase after a page write operation or by writing the RWWSRE bit in SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM page load operation, all data loaded will be lost. 5.23.7.3 Performing a Page Write To execute page write, set up the address in the Z-pointer, write "X0000101" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. Page write to the RWW section: The NRWW section can be read during the page write. Page write to the NRWW section: The CPU is halted during the operation. 5.23.7.4 Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SELFPRGEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR register in software. When using the SPM interrupt, the interrupt vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in Section 5.8.9 "Watchdog Timer" on page 66. 5.23.7.5 Consideration While Updating BLS Special care must be taken if the user allows the boot loader section to be updated by leaving boot lock bit11 unprogrammed. An accidental write to the boot loader itself can corrupt the entire boot loader, and further software updates might be impossible. If it is not necessary to change the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader software from any internal software changes. 5.23.7.6 Prevent Reading the RWW Section During Self-Programming During self-programming (either page erase or page write), the RWW section is always blocked for reading. The user software itself must prevent that this section is addressed during the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW section is busy. During self-programming the interrupt vector table should be moved to the BLS as described in Section 5.8.9 "Watchdog Timer" on page 66, or the interrupts must be disabled. Before addressing the RWW section after the programming is completed, the user software must clear the RWWSB by writing the RWWSRE. See Section 5.23.7.12 "Simple Assembly Code Example for a Boot Loader" on page 249 for an example. 5.23.7.7 Setting the Boot Loader Lock Bits by SPM To set the boot loader lock bits, write the desired data to R0, write "X0001001" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only accessible lock bits are the boot lock bits that may prevent the application and boot loader section from any software update by the MCU. Bit 7 6 5 4 3 2 1 0 R0 1 1 BLB12 BLB11 BLB02 BLB01 1 1 See Table 5-104 on page 243 and Table 5-105 on page 243 for how the different settings of the boot loader bits affect the flash access. If bits 5..2 in R0 are cleared (zero), the corresponding boot lock bit will be programmed if an SPM instruction is executed within four cycles after BLBSET and SELFPRGEN are set in SPMCSR. The Z-pointer is don't care during this operation, but for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the lOck bits). For future compatibility it is also recommended to set bits 7, 6, 1, and 0 in R0 to "1" when writing the lock bits. When programming the lock bits the entire flash can be read during the operation. 5.23.7.8 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to flash. Reading the fuses and lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR register and verifies that the bit is cleared before writing to the SPMCSR register. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 247 5.23.7.9 Reading the Fuse and Lock Bits from Software It is possible to read both the fuse and lock bits from software. To read the lock bits, load the Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set in SPMCSR, the value of the lock bits will be loaded in the destination register. The BLBSET and SELFPRGEN bits will auto-clear upon completion of reading the lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the Instruction set Manual. Bit 7 6 5 4 3 2 1 0 Rd - - BLB12 BLB11 BLB02 BLB01 LB2 LB1 The algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. To read the fuse low byte, load the Z-pointer with 0x0000 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the fuse low byte (FLB) will be loaded in the destination register as shown below. Refer to Table 5-117 on page 254 for a detailed description and mapping of the fuse low byte. Bit 7 6 5 4 3 2 1 0 Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0 Similarly, when reading the fuse high byte, load 0x0003 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the fuse high byte (FHB) will be loaded in the destination register as shown below. Refer to Table 5-118 on page 255 for detailed description and mapping of the fuse high byte. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 When reading the extended fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the extended fuse byte (EFB) will be loaded in the destination register as shown below. Refer to Table 5-117 on page 254 for detailed description and mapping of the extended fuse byte. Bit 7 6 5 4 3 2 1 0 Rd - - - - EFB3 EFB2 EFB1 EFB0 Fuse and lock bits that are programmed, will be read as zero. Fuse and lock bits that are unprogrammed, will be read as one. 5.23.7.10 Preventing Flash Corruption During periods of low VCC, the flash program can be corrupted because the supply voltage is too low for the CPU and the flash to operate properly. These issues are the same as for board level systems using the flash, and the same design solutions should be applied. A flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. If there is no need for a boot loader update in the system, program the boot loader lock bits to prevent any boot loader software updates. 248 2. Keep the AVR(R) RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal brown-out detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 3. Keep the AVR core in power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR register and thus the flash from unintentional writes. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.23.7.11 Programming Time for Flash when Using SPM The calibrated RC oscillator is used to time flash accesses. Table 5-107 shows the typical programming time for flash accesses from the CPU. Table 5-107. SPM Programming Time Symbol Min Programming Time Max Programming Time 3.7ms 4.5ms Flash write (page erase, page write, and write lock bits by SPM) 5.23.7.12 Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-It is assumed that either the interrupt table is moved to the Boot ; loader section or that the interrupts are disabled. .equ PAGESIZEB = PAGESIZE*2;PAGESIZEB is page size in BYTES, not words .org SMALLBOOTSTART Write_page: ; Page Erase ldi spmcrval, (1<<PGERS) | (1<<SELFPRGEN) call Do_spm ; ldi call ; ldi ldi Wrloop: ld ld ldi call adiw sbiw brne re-enable the RWW section spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN) Do_spm transfer data from RAM to Flash page buffer looplo, low(PAGESIZEB) ;init loop variable loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 r0, Y+ r1, Y+ spmcrval, (1<<SELFPRGEN) Do_spm ZH:ZL, 2 loophi:looplo, 2 Wrloop ;use subi for PAGESIZEB<=256 ; subi sbci ldi call execute Page Write ZL, low(PAGESIZEB) ;restore pointer ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 spmcrval, (1<<PGWRT) | (1<<SELFPRGEN) Do_spm ; ldi call re-enable the RWW section spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN) Do_spm ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 249 ; ldi ldi subi sbci Rdloop: lpm ld cpse jmp sbiw brne read back and check, optional looplo, low(PAGESIZEB) ;init loop variable loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 YL, low(PAGESIZEB) ;restore pointer YH, high(PAGESIZEB) ; ; Return: in sbrs ready yet ret ; ldi call rjmp return to RWW section verify that RWW section is safe to read Do_spm: ; Wait_spm: in sbrc rjmp ; ; in cli ; Wait_ee: sbic rjmp ; out spm ; out ret 250 r0, Z+ r1, Y+ r0, r1 Error loophi:looplo, 1 Rdloop temp1, SPMCSR temp1, RWWSB ; If RWWSB is set, the RWW section is not re-enable the RWW section spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN) Do_spm Return check for previous SPM complete temp1, SPMCSR temp1, SELFPRGEN Wait_spm input: spmcrval determines SPM action disable interrupts if enabled, store status temp2, SREG check that no EEPROM write access is present EECR, EEPE Wait_ee SPM timed sequence SPMCSR, spmcrval restore SREG (to enable interrupts if originally enabled) SREG, temp2 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 ;use subi for PAGESIZEB<=256 5.23.7.13 Atmel ATA6612C Boot Loader Parameters In Table 5-108 through Table 5-110, the parameters used in the description of the self programming are given. Table 5-108. Boot Size Configuration, Atmel ATA6612C BOOTSZ1 BOOTSZ0 Boot Size Pages Application Flash Section Boot Loader Flash Section End Application Section Boot Reset Address (Start Boot Loader Section) 1 1 128 words 4 0x000 - 0xF7F 0xF80 - 0xFFF 0xF7F 0xF80 1 0 256 words 8 0x000 - 0xEFF 0xF00 - 0xFFF 0xEFF 0xF00 0 1 512 words 16 0x000 - 0xDFF 0xE00 - 0xFFF 0xDFF 0xE00 0 1024 words 32 0x000 - 0xBFF 0xC00 - 0xFFF 0xBFF The different BOOTSZ fuse configurations are shown in Figure 5-115 on page 242. 0xC00 0 Note: Table 5-109. Read-While-Write Limit, Atmel ATA6612C Section Pages Address Read-while-write section (RWW) 96 0x000 - 0xBFF No read-while-write section (NRWW) 32 0xC00 - 0xFFF For details about these two section, see Section 5.23.3.2 "NRWW - No Read-While-Write Section" on page 241 and Section 5.23.3.1 "RWW - Read-While-Write Section" on page 241. Table 5-110. Explanation of Different Variables used in Figure 5-116 on page 246 and the Mapping to the Z-pointer, Atmel ATA6612C Corresponding Z-value(1) Variable Description PCMSB 11 Most significant bit in the program counter. (the program counter is 12 bits PC[11:0]) PAGEMSB 4 Most significant bit which is used to address the words within one page (32 words in a page requires 5 bits PC [4:0]). ZPCMSB Z12 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1. ZPAGEMSB Z5 Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not used, the ZPAGEMSB equals PAGEMSB + 1. PCPAGE PC[11:5] Z12:Z6 Program counter page address: Page select, for page erase and page write PCWORD PC[4:0] Z5:Z1 Program counter word address: Word select, for filling temporary buffer (must be zero during page write operation) Note: 1. Z15:Z13: always ignored Z0: should be zero for all SPM commands, byte select for the LPM instruction. See Section 5.23.6 "Addressing the Flash During Self-Programming" on page 245 for details about the use of Z-pointer during Self-Programming. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 251 5.23.7.14 ATA6613C Boot Loader Parameters In Table 5-111 through Table 5-113, the parameters used in the description of the self programming are given. Table 5-111. Boot Size Configuration, ATA6613C BOOTSZ1 BOOTSZ0 Boot Size Pages Application Flash Section Boot Loader Flash Section End Application Section Boot Reset Address (Start Boot Loader Section) 1 1 128 words 2 0x0000 - 0x1F7F 0x1F80 - 0x1FFF 0x1F7F 0x1F80 1 0 256 words 4 0x0000 - 0x1EFF 0x1F00 - 0x1FFF 0x1EFF 0x1F00 0 1 512 words 8 0x0000 - 0x1DFF 0x1E00 - 0x1FFF 0x1DFF 0x1E00 0 1024 words 16 0x0000 - 0x1BFF 0x1C00 - 0x1FFF 0x1BFF The different BOOTSZ fuse configurations are shown in Figure 5-115 on page 242. 0x1C00 0 Note: Table 5-112. Read-While-Write Limit, ATA6613C Section Pages Address Read-while-write section (RWW) 112 0x0000 - 0x1BFF No read-while-write section (NRWW) 16 0x1C00 - 0x1FFF For details about these two section, see Section 5.23.3.2 "NRWW - No Read-While-Write Section" on page 241 and Section 5.23.3.1 "RWW - Read-While-Write Section" on page 241. Table 5-113. Explanation of Different Variables used in Figure 5-116 on page 246 and the Mapping to the Z-pointer, ATA6613C Corresponding Z-value(1) Variable PCMSB 12 Most significant bit in the program counter. (The program counter is 12 bits PC[11:0]) PAGEMSB 5 Most significant bit which is used to address the words within one page (64 words in a page requires 6 bits PC [5:0]) ZPCMSB Z13 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1. ZPAGEMSB Z6 Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not used, the ZPAGEMSB equals PAGEMSB + 1. PCPAGE PC[12:6] Z13:Z7 Program counter page address: Page select, for page erase and page write PCWORD PC[5:0] Z6:Z1 Program counter word address: Word select, for filling temporary buffer (must be zero during page write operation) Note: 252 Description 1. Z15:Z14: always ignored Z0: should be zero for all SPM commands, byte select for the LPM instruction. See Section 5.23.6 "Addressing the Flash During Self-Programming" on page 245 for details about the use of Z-pointer during self-programming. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.24 Memory Programming 5.24.1 Program And Data Memory Lock Bits The Atmel(R) ATA6612C/ATA6613C provides six lock bits which can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional features listed in Table 5-115. The lock bits can only be erased to "1" with the chip erase command. The SPM instruction is enabled for the whole flash if the SELFPRGEN fuse is programmed ("0"), otherwise it is disabled. Table 5-114. Lock Bit Byte(1) Lock Bit Byte Description Default Value 7 - 1 (unprogrammed) 6 - 1 (unprogrammed) (2) 5 Boot lock bit 1 (unprogrammed) (2) 4 Boot lock bit 1 (unprogrammed) BLB02(2) 3 Boot lock bit 1 (unprogrammed) (2) 2 Boot lock bit 1 (unprogrammed) 1 Lock bit 1 (unprogrammed) LB1 0 Lock bit "1" means unprogrammed, "0" means programmed 1 (unprogrammed) 1. 2. Only on Atmel ATA6612C/ATA6613C BLB12 BLB11 BLB01 LB2 Notes: Bit No Table 5-115. Lock Bit Protection Modes(1)(2) Memory Lock Bits Protection Type LB Mode LB2 LB1 1 1 1 No memory lock features enabled. 2 1 0 Further programming of the flash and EEPROM is disabled in parallel and serial programming mode. The fuse bits are locked in both serial and parallel programming mode.(1) 1. Further programming and verification of the flash and EEPROM is disabled in parallel and serial programming mode. The boot lock bits and fuse bits are locked in both serial and parallel programming mode.(1) Program the fuse bits and boot lock bits before programming the LB1 and LB2. 2. "1" means unprogrammed, "0" means programmed 3 Notes: 0 0 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 253 Table 5-116. Lock Bit Protection Modes(1)(2). Only Atmel ATA6612C/ATA6613C. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the application section. 2 1 0 SPM is not allowed to write to the application section. 3 0 0 SPM is not allowed to write to the application section, and LPM executing from the boot loader section is not allowed to read from the application section. If interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 4 0 1 LPM executing from the boot loader section is not allowed to read from the application section. If interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the boot loader section. 2 1 0 SPM is not allowed to write to the boot loader section. 0 SPM is not allowed to write to the boot loader section, and LPM executing from the application section is not allowed to read from the boot loader section. If interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 3 0 1. LPM executing from the application section is not allowed to read from the boot loader section. If interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2. 2. "1" means unprogrammed, "0" means programmed 4 Notes: 0 1 5.24.2 Fuse Bits The Atmel ATA6612C/ATA6613C has three Fuse bytes. Table 5-117 to Table 5-119 on page 255 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, "0", if they are programmed. Table 5-117. Extended Fuse Byte for Atmel ATA6612C/ATA6613C Extended Fuse Byte Bit No Description Default Value - 7 - 1 - 6 - 1 - 5 - 1 - 4 - 1 - 3 - 1 BOOTSZ1 2 Select boot size (see Table 113 for details) 0 (programmed)(1) BOOTSZ0 1 Select boot size (see Table 113 for details) 0 (programmed)(1) Note: 254 BOOTRST 0 Select reset vector 1 (unprogrammed) 1. The default value of BOOTSZ1..0 results in maximum boot size. See Table 5-120 on page 257 for details. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Table 5-118. Fuse High Byte High Fuse Byte Description Default Value 7 External reset disable 1 (unprogrammed) DWEN 6 debugWIRE enable 1 (unprogrammed) SPIEN(2) 5 Enable serial program and data downloading 0 (programmed, SPI programming enabled) WDTON(3) 4 Watchdog timer always on 1 (unprogrammed) EESAVE 3 EEPROM memory is preserved through the chip erase 1 (unprogrammed), EEPROM not reserved BODLEVEL2(4) 2 Brown-out detector trigger level 1 (unprogrammed) (4) 1 Brown-out detector trigger level 1 (unprogrammed) RSTDISBL Bit No (1) BODLEVEL1 (4) BODLEVEL0 0 Brown-out detector trigger level 1 (unprogrammed) Notes: 1. See Section 5.10.3.3 "Alternate Functions of Port C" on page 87 for description of RSTDISBL fuse. 2. The SPIEN fuse is not accessible in serial programming mode. 3. See Section 5.8.9.1 "Watchdog Timer Control Register - WDTCSR" on page 68 for details. 4. See Table 5-21 on page 63 for BODLEVEL fuse decoding. Table 5-119. Fuse Low Byte Low Fuse Byte Bit No Description Default Value (4) 7 Divide clock by 8 0 (programmed) (3) CKDIV8 CKOUT Notes: 6 Clock output 1 (unprogrammed) SUT1 5 Select start-up time 1 (unprogrammed)(1) SUT0 4 Select start-up time 0 (programmed)(1) CKSEL3 3 Select clock source 0 (programmed)(2) CKSEL2 2 Select clock source 0 (programmed)(2) CKSEL1 1 Select clock source 1 (unprogrammed)(2) CKSEL0 0 Select clock source 0 (programmed)(2) 1. The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 5-12 on page 52 for details. 2. The default setting of CKSEL3..0 results in internal RC Oscillator at 8 MHz. See Table 5-11 on page 51 for details. 3. The CKOUT fuse allows the system clock to be output on PORTB0. See Section 5.6.9 "Clock Output Buffer" on page 54 for details. 4. See Section 5.6.11 "System Clock Prescaler" on page 54 for details. The status of the fuse bits is not affected by chip erase. Note that the fuse bits are locked if lock bit1 (LB1) is programmed. program the fuse bits before programming the lock bits. 5.24.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE fuse which will take effect once it is programmed. The fuses are also latched on power-up in normal mode. 5.24.3 Signature Bytes All Atmel(R) microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 255 5.24.3.1 Atmel ATA6612C Signature Bytes 1. 0x000: 0x1E (indicates manufactured by Atmel). 2. 0x001: 0x93 (indicates 8KB Flash memory). 3. 0x002: 0x0A (indicates Atmel ATA6612C device when 0x001 is 0x93). 5.24.3.2 ATA6613C Signature Bytes 1. 0x000: 0x1E (indicates manufactured by Atmel). 2. 0x001: 0x94 (indicates 16KB Flash memory). 3. 0x002: 0x06 (indicates ATA6613C device when 0x001 is 0x94). 5.24.4 Calibration Byte The Atmel(R) ATA6612C/ATA6613C has a byte calibration value for the internal RC oscillator. This byte resides in the high byte of address 0x000 in the signature address space. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator. 5.24.5 Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify flash program memory, EEPROM data memory, memory lock bits, and fuse bits in the Atmel ATA6612C/ATA6613C. Pulses are assumed to be at least 250ns unless otherwise noted. 5.24.5.1 Signal Names In this section, some pins of the Atmel ATA6612C/ATA6613C are referenced by signal names describing their functionality during parallel programming (see Figure 5-117 and Table 5-120 on page 257). Pins not described in the following table are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 5-122 on page 257. When pulsing WR or OE, the command loaded determines the action executed. The different commands are shown in Table 5-123 on page 257. Figure 5-117. Parallel Programming + 5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 VCC + 5V AVCC +12V BS2 RESET PC2 XTAL1 GND 256 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 PC[1:0]:PB[5:0] DATA Table 5-120. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O Function RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command OE PD2 I Output enable (active low) WR PD3 I Write pulse (active low) BS1 PD4 I Byte select 1 ("0" selects Low byte, "1" selects high byte) XA0 PD5 I XTAL action Bit 0 XA1 PD6 I XTAL action Bit 1 PAGEL PD7 I Program memory and EEPROM data page load BS2 PC2 I Byte select 2 ("0" selects low byte, "1" selects 2'nd high byte) DATA {PC[1:0]: PB[5:0]} I/O Bi-directional data bus (output when OE is low) Table 5-121. Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 5-122. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load flash or EEPROM address (high or low address byte determined by BS1). 0 1 Load data (high or low data byte for flash determined by BS1). 1 0 Load command 1 1 No action, idle Table 5-123. Command Byte Bit Coding Command Byte Command Executed 1000 0000 Chip erase 0100 0000 Write fuse bits 0010 0000 Write lock bits 0001 0000 Write flash 0001 0001 Write EEPROM 0000 1000 Read signature bytes and calibration byte 0000 0100 Read fuse and lock bits 0000 0010 Read flash 0000 0011 Read EEPROM ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 257 Table 5-124. No. of Words in a Page and No. of Pages in the Flash Device Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB ATA6612C 4Kwords (8Kbytes) 32 words PC[4:0] 128 PC[11:5] 11 64 words PC[5:0] 128 PC[12:6] 12 8Kwords ATA6613C (16Kbytes) Table 5-125. No. of Words in a Page and No. of Pages in the EEPROM Device EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB ATA6612C 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8 ATA6613C 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8 5.24.6 Serial Programming Pin Mapping Table 5-126. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB3 I Serial data in MISO PB4 O Serial data out SCK PB5 I Serial clock 5.24.7 Parallel Programming 5.24.7.1 Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET to "0" and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 5-121 on page 257 to "0000" and wait at least 100ns. 4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100ns after +12V has been applied to RESET, will cause the device to fail entering programming mode. 5. Wait at least 50s before sending a new command. 5.24.7.2 Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. The command needs only be loaded once when writing or reading multiple memory locations. 258 Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE fuse is programmed) and flash after a chip erase. Address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte EEPROM. This consideration also applies to signature bytes reading. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.24.7.3 Chip Erase The chip erase will erase the flash and EEPROM(1) memories plus lock bits. The lock bits are not reset until the program memory has been completely erased. The fuse bits are not changed. A chip erase must be performed before the flash and/or EEPROM are reprogrammed. Note: 1. The EEPRPOM memory is preserved during chip erase if the EESAVE fuse is programmed. Load command "chip erase" 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS1 to "0". 3. Set DATA to "1000 0000". This is the command for chip erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the chip erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. 5.24.7.4 Programming the Flash The flash is organized in pages (see Table 5-124 on page 258). When programming the flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire flash memory: A. Load command "write flash" 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS1 to "0". 3. Set DATA to "0001 0000". This is the command for write flash. 4. Give XTAL1 a positive pulse. This loads the command. B. Load address low byte 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS1 to "0". This selects low address. 3. Set DATA = address low byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load data low byte 1. Set XA1, XA0 to "01". This enables data loading. 2. Set DATA = data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. D. Load data high byte 1. Set BS1 to "1". This selects high data byte. 2. Set XA1, XA0 to "01". This enables data loading. 3. Set DATA = data high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the data byte. E. Latch data 1. Set BS1 to "1". This selects high data byte. 2. Give PAGEL a positive pulse. This latches the data bytes (see Figure 5-119 on page 261 for signal waveforms). F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded. While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in Figure 5-118 on page 260. Note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 259 G. Load address high byte 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS1 to "1". This selects high address. 3. Set DATA = address high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. H. Program page 1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 2. Wait until RDY/BSY goes high (see Figure 5-119 on page 261 for signal waveforms). I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End page programming 1. 1. Set XA1, XA0 to "10". This enables command loading. 2. Set DATA to "0000 0000". This is the command for No operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 5-118. Addressing the Flash Which is Organized in Pages(1) PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PAGE ADDRESS WITHIN THE FLASH PCWORD WORD ADDRESS WITHIN A PAGE Program Memory Page Page Instructions Word PCWORD [PAGEMSB:0] 00 01 02 PAGEEND Note: 260 1. PCPAGE and PCWORD are listed in Table 5-124 on page 258. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Figure 5-119. Programming the Flash Waveforms(1) F DATA A B C D E B C D E G 0x10 ADDR. LOW DATA LOW DATA HIGH XX ADDR. LOW DATA LOW DATA HIGH XX ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: 1. "XX" is do not care. The letters refer to the programming description above. 5.24.7.5 Programming the EEPROM The EEPROM is organized in pages (see Table 5-125 on page 258). When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to Section 5.24.7.4 "Programming the Flash" on page 259 for details on command, address and data loading): 1. A: Load command "0001 0001". 2. G: Load address high byte (0x00 - 0xFF). 3. B: Load address low byte (0x00 - 0xFF). 4. C: Load data (0x00 - 0xFF). 5. E: Latch data (give PAGEL a positive pulse). K: Repeat 3 through 5 until the entire buffer is filled. L: Program EEPROM page 1. Set BS1 to "0". 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page (see Figure 5-120 on page 262 for signal waveforms). ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 261 Figure 5-120.Programming the EEPROM Waveforms K DATA A G B C E B C E 0x11 ADDR. HIGH ADDR. LOW DATA XX ADDR. LOW DATA XX L XA1 XA0 BS1 XTAL1 WR RDY/ BSY RESET +12V OE PAGEL BS2 5.24.7.6 Reading the Flash The algorithm for reading the flash memory is as follows (refer to Section 5.24.7.4 "Programming the Flash" on page 259 for details on command and address loading): 1. A: Load command "0000 0010". 2. G: Load address high byte (0x00 - 0xFF). 3. B: Load address low byte (0x00 - 0xFF). 4. Set OE to "0", and BS1 to "0". The flash word low byte can now be read at DATA. 5. Set BS1 to "1". The flash word high byte can now be read at DATA. 6. Set OE to "1". 5.24.7.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to Section 5.24.7.4 "Programming the Flash" on page 259 for details on command and address loading): 1. A: Load Command "0000 0011". 2. G: Load address high byte (0x00 - 0xFF). 3. B: Load address Low Byte (0x00 - 0xFF). 4. Set OE to "0", and BS1 to "0". The EEPROM Data byte can now be read at DATA. 5. Set OE to "1". 5.24.7.8 Programming the Fuse Low Bits The algorithm for programming the fuse low bits is as follows (refer to Section 5.24.7.4 "Programming the Flash" on page 259 for details on command and data loading): 1. A: Load command "0100 0000". 262 2. C: Load data low byte. Bit n = "0" programs and bit n = "1" erases the fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.24.7.9 Programming the Fuse High Bits The algorithm for programming the fuse High bits is as follows (refer to Section 5.24.7.4 "Programming the Flash" on page 259 for details on command and data loading): 1. A: Load command "0100 0000". 2. C: Load data low byte. Bit n = "0" programs and bit n = "1" erases the fuse bit. 3. Set BS1 to "1" and BS2 to "0". This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to "0". This selects low data byte. 5.24.7.10 Programming the Extended Fuse Bits The algorithm for programming the extended Fuse bits is as follows (refer to Section 5.24.7.4 "Programming the Flash" on page 259 for details on command and data loading): 1. 1. A: Load command "0100 0000". 2. 2. C: Load Data low byte. Bit n = "0" programs and bit n = "1" erases the fuse bit. 3. 3. Set BS1 to "0" and BS2 to "1". This selects extended data byte. 4. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. 5. Set BS2 to "0". This selects low data byte. Figure 5-121.Programming the FUSES Waveforms Write Fuse Low Byte DATA A C 0x40 DATA XX Write Fuse High Byte A C 0x40 DATA XX Write Extended FuseByte A C 0x40 DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/ BSY RESET +12V OE PAGEL 5.24.7.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to "Programming the Flash" on page 259 for details on Command and Data loading): 1. A: Load Command "0010 0000". 2. C: Load Data Low Byte. Bit n = "0" programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode. 3. Give WR a negative pulse and wait for RDY/BSY to go high. The Lock bits can only be cleared by executing Chip Erase. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 263 5.24.7.12 Reading the Fuse and Lock Bits The algorithm for reading the fuse and lock bits is as follows (refer to Section 5.24.7.4 "Programming the Flash" on page 259 for details on command loading): 1. A: Load command "0000 0100". 2. Set OE to "0", BS2 to "0" and BS1 to "0". The status of the fuse low bits can now be read at DATA ("0" means programmed). 3. Set OE to "0", BS2 to "1" and BS1 to "1". The status of the fuse high bits can now be read at DATA ("0" means programmed). 4. Set OE to "0", BS2 to "1", and BS1 to "0". The status of the extended fuse bits can now be read at DATA ("0" means programmed). 5. Set OE to "0", BS2 to "0" and BS1 to "1". The status of the lock bits can now be read at DATA ("0" means programmed). 6. Set OE to "1". Figure 5-122. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fuse Low Byte 0 Extended Fuse Byte 1 BS2 DATA 0 Lock Bits 1 1 Fuse High Byte BS1 BS2 5.24.7.13 Reading the Signature Bytes The algorithm for reading the signature bytes is as follows (refer to Section 5.24.7.4 "Programming the Flash" on page 259 for details on command and address loading): 1. A: Load command "0000 1000". 2. B: Load Address low byte (0x00 - 0x02). 3. Set OE to "0", and BS1 to "0". The selected signature byte can now be read at DATA. 4. Set OE to "1". 5.24.7.14 Reading the Calibration Byte The algorithm for reading the calibration byte is as follows (refer to Section 5.24.7.4 "Programming the Flash" on page 259 for details on command and Address loading): 1. A: Load command "0000 1000". 264 2. B: Load address low byte, 0x00. 3. Set OE to "0", and BS1 to "1". The calibration byte can now be read at DATA. 4. Set OE to "1". ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.24.7.15 Parallel Programming Characteristics Figure 5-123. Parallel Programming Timing, Including some General Timing Requirements tXLWL XTAL1 tXHXL tDVXH tXLDX Data and Control (DATA, XA0/1, BS1, BS2) tBVPH PAGEL tPLBX tBVWL tWLBX tPHPL tWLWH WR tPLWL tWLRL RDY/BSY tWLRH Figure 5-124. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) Load Address (Low Byte) Load Data (Low Byte) Load Data (High Byte) tXLXH Load Address (Low Byte) Load Data tXLPH tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 5-123 on page 265 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 265 Figure 5-125. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) Load Address (Low Byte) Read Data (Low Byte) Read Data (High Byte) Load Address (Low Byte) tXLOL XTAL1 tBVDV BS1 tOLDV OE tOHDZ DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 5-123 on page 265 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 5-127. Parallel Programming Characteristics, VCC = 5V 10% Parameter Programming enable voltage Programming enable current Min VPP 11.5 IPP Typ Max Units 12.5 V 250 A Data and control valid before XTAL1 high tDVXH 67 ns XTAL1 low to XTAL1 high tXLXH 200 ns XTAL1 pulse width high tXHXL 150 ns Data and control hold after XTAL1 low tXLDX 67 ns XTAL1 low to WR low tXLWL 0 ns XTAL1 low to PAGEL high tXLPH 0 ns PAGEL low to XTAL1 high tPLXH 150 ns BS1 valid before PAGEL high tBVPH 67 ns PAGEL pulse width high tPHPL 150 ns BS1 hold after PAGEL low tPLBX 67 ns BS2/1 hold after WR low tWLBX 67 ns PAGEL low to WR low tPLWL 67 ns BS1 valid to WR low tBVWL 67 ns WR pulse width low tWLWH 150 ns tWLRL 0 1 s WR low to RDY/BSY low WR low to RDY/BSY high (1) tWLRH 3.7 4.5 ms tWLRH_CE 7.5 9 ms XTAL1 low to OE low tXLOL 0 BS1 valid to DATA valid tBVDV 0 OE low to DATA valid tOLDV WR low to RDY/BSY high for chip erase(2) ns 250 ns 250 ns OE high to DATA tri-stated tOHDZ 250 Notes: 1. tWLRH is valid for the write flash, write EEPROM, write fuse bits and write lock bits commands. ns 2. 266 Symbol tWLRH_CE is valid for the chip erase command. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.24.8 Serial Downloading Both the flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 5-126 on page 258, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface. Figure 5-126. Serial Programming and Verify(1) +2.7V to 5.5V VCC +2.7V to 5.5V(2) MOSI AVCC MISO SCK XTAL1 RESET GND Notes: 1. If the device is clocked by the internal oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8V - 5.5V When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the serial mode ONLY) and there is no need to first execute the chip erase instruction. The chip erase operation turns the content of every memory location in both the program and EEPROM arrays into 0xFF. Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck 12MHz High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck 12MHz 5.24.8.1 Serial Programming Algorithm When writing serial data to the Atmel(R) ATA6612C/ATA6613C, data is clocked on the rising edge of SCK. When reading data from the Atmel ATA6612C/ATA6613C, data is clocked on the falling edge of SCK. See Figure 5-127 on page 269 for timing details. To program and verify the Atmel ATA6612C/ATA6613C in the serial programming mode, the following sequence is recommended (see four byte instruction formats in Table 5-129 on page 269): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to "0". 2. Wait for at least 20ms and enable serial programming by sending the programming enable serial instruction to pin MOSI. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 267 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the programming enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new programming enable command. 4. The flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the load program memory page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The program memory page is stored by loading the write program memory page instruction with the 8 MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page (see Table 5-128 on page 268). Accessing the serial programming interface before the flash write operation completes can result in incorrect programming. 5. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte (see Table 5-128 on page 268). In a chip erased device, no 0xFFs in the data file(s) need to be programmed. 6. Any memory location can be verified by using the read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to "1". Turn VCC power off. 5.24.8.2 Data Polling Flash When a page is being programmed into the flash, reading an address location within the page being programmed will give the value 0xFF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the flash will not work for the value 0xFF, so when programming this value, the user will have to wait for at least tWD_FLASH before programming the next page. As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. See Table 5-128 on page 268 for tWD_FLASH value. 5.24.8.3 Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value 0xFF, but the user should have the following in mind: As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is re-programmed without chip erasing the device. In this case, data polling cannot be used for the value 0xFF, and the user will have to wait at least tWD_EEPROM before programming the next byte. See Table 5-128 for tWD_EEPROM value. Table 5-128. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location 268 Symbol Minimum Wait Delay tWD_FLASH 4.5ms tWD_EEPROM 3.6ms tWD_ERASE 9.0ms ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Figure 5-127. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Table 5-129. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable serial programming after RESET goes low. Chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip erase EEPROM and flash. Read program memory 0010 H000 000a aaaa Read H (high or low) data o from bbbb bbbb oooo oooo Program memory at word address a:b. Load program memory page 0100 H000 000x xxxx xxbb bbbb iiii iiii Write H (high or low) data i to program memory page at word address b. Data low byte must be loaded before data high byte is applied within the same address. Write program memory page 0100 1100 000a aaaa bbxx xxxx xxxx xxxx Read EEPROM memory 1010 0000 000x xxaa bbbb bbbb oooo oooo Read data o from EEPROM memory at address a:b. Write EEPROM memory 1100 0000 000x xxaa bbbb bbbb iiii iiii Write data i to EEPROM memory at address a:b. Load EEPROM memory Page (page access) 1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page buffer. After data is loaded, program EEPROM page. Write EEPROM memory Page (page access) 1100 0010 00xx xxaa bbbb bb00 xxxx xxxx Read lock bits 0101 1000 0000 0000 xxxx xxxx Write lock bits 1010 1100 111x xxxx xxxx xxxx Read signature byte 0011 0000 000x xxxx xxxx xxbb Write fuse bits 1010 1100 1010 0000 xxxx xxxx Write program memory page at address a:b. Write EEPROM page at address a:b. Read Lock bits. "0" = programmed, xxoo oooo "1" = unprogrammed. See Table 5114 on page 253 for details. 11ii iiii Write lock bits. Set bits = "0" to program lock bits. See Table 5-114 on page 253 for details. oooo oooo Read signature byte o at address b. iiii iiii Set bits = "0" to program, "1" to unprogram. See Table XXX on page XXX for details. Set bits = "0" to program, "1" to unprogram. See Table 5-98 on page 229 for details. a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = do not care Write fuse high bits Note: Operation 1010 1100 1010 1000 xxxx xxxx iiii iiii ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 269 Table 5-129. Serial Programming Instruction Set (Continued) Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Write extended fuse bits 1010 1100 1010 0100 xxxx xxxx xxxx xxii Read fuse bits 0101 0000 0000 0000 xxxx xxxx Read fuse bits. "0" = programmed, "1" oooo oooo = unprogrammed. See Table XXX on page XXX for details. xxxx xxxx Read fuse high bits. "0"=programmed, oooo oooo "1" = unprogrammed. See Table 5-98 on page 229 for details. Read fuse high bits 0101 1000 0000 1000 Operation Set bits = "0" to program, "1" to unprogram. See Table 5-117 on page 254 for details. Read extended fuse bits 0101 0000 0000 1000 xxxx xxxx Read extended fuse bits. "0" = programmed, "1" = unprogrammed. oooo oooo See Table 5-117 on page 254 for details. Read calibration byte 0011 1000 000x xxxx 0000 0000 oooo oooo Read calibration byte If o = "1", a programming operation is still busy. Wait until this bit returns to Poll RDY/BSY 1111 0000 0000 0000 xxxx xxxx xxxx xxxo "0" before applying another command. Note: a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = do not care 5.24.8.4 SPI Serial Programming Characteristics For characteristics of the SPI module see Section 6.1 "SPI Timing Characteristics" on page 278. 270 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.25 Electrical Characteristics 5.25.1 DC Characteristics Tcase = -40C to +125C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Min.(5) Max.(5) Units VCC = 2.7V to 5.5V VIL -0.5 0.3VCC(1) V Input low voltage, XTAL1 pin VCC = 2.7V to 5.5V VIL1 -0.5 0.1VCC(1) V Input low voltage, RESET pin VCC = 2.7V to 5.5V VIL2 -0.5 0.1VCC(1) V Input high voltage, except XTAL1 and RESET pins VCC = 2.7V to 5.5V VIH 0.6VCC(2) VCC + 0.5 V Input high voltage, XTAL1 pin VCC = 2.7V to 5.5V VIH1 0.7VCC(2) VCC + 0.5 V Input high voltage, RESET VCC = 2.7V to 5.5V pin VIH2 0.9VCC(2) VCC + 0.5 V 0.8 0.5 V Parameter Condition Input low voltage, except XTAL1 and reset pin Typ. Output low voltage(3) IOL = 20mA, VCC = 5V IOL = 5mA, VCC = 3V VOL Output high voltage(4) IOH = -20mA, VCC = 5V IOH = -10mA, VCC = 3V VOH Input leakage Current I/O pin VCC = 5.5V, pin low (absolute value) IIL 50 nA Input leakage Current I/O pin VCC = 5.5V, pin high (absolute value) IIH 50 nA Reset pull-up resistor VCC = 5.0V, VIN = 0V RRST 60 k 50 k 4.1 2.3 V 30 I/O pin pull-up resistor RPU 20 Notes: 1. "Max" means the highest value where the pin is guaranteed to be read as low 2. "Min" means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: Atmel ATA6612C/ATA6613C: 1] The sum of all IOL, for ports C0 - C5, should not exceed 100mA. 2] The sum of all IOL, for ports C6, D0 - D4, should not exceed 100mA. 3] The sum of all IOL, for ports B0 - B7, D5 - D7, should not exceed 100mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: Atmel ATA6612C/ATA6613C: 1] The sum of all IOH, for ports C0 - C5, should not exceed 100mA. 2] The sum of all IOH, for ports C6, D0 - D4, should not exceed 100mA. 3] The sum of all IOH, for ports B0 - B7, D5 - D7, should not exceed 100mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. All DC Characteristics contained in this datasheet are based on actual Atmel ATA6612C microcontrollers characterization. 6. Values with "Power Reduction REgister - PRR" enabled (0xEF). ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 271 5.25.1 DC Characteristics (Continued) Tcase = -40C to +125C, VCC = 2.7V to 5.5V (unless otherwise noted) Parameter Typ. Max.(5) Units Active 4MHz, VCC = 3V (ATA6612C/ATA6613CL) 1.8 3.0 mA Active 8MHz, VCC = 5V (ATA6612C/ATA6613C) 6.0 10 mA Active 15MHz, VCC = 5V (ATA6612C/ATA6613C) 10.0 16 mA Idle 4MHz, VCC = 3V (ATA6612C/ATA6613CV) 0.4 1 mA 1.4 2.4 mA 2.8 4 mA WDT enabled, VCC = 3V 8 30 A WDT enabled, VCC = 5V 12.6 50 A WDT disabled, VCC = 3V 5 24 A WDT disabled, VCC = 5V 6.6 36 A 10 40 mV 50 nA Condition Power supply current (2) Idle 8MHz, VCC = 5V (ATA6612C/ATA6613CL) Symbol Min.(5) ICC Idle 15MHz, VCC = 5V (ATA6612C/ATA6613C) Power-down mode Analog comparator Input offset voltage VCC = 5V Vin = VCC/2 VACIO Analog comparator Input leakage current VCC = 5V Vin = VCC/2 IACLK -50 Analog comparator VCC = 4.5V tACID 140 propagation delay Notes: 1. "Max" means the highest value where the pin is guaranteed to be read as low 272 ns 2. "Min" means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: Atmel ATA6612C/ATA6613C: 1] The sum of all IOL, for ports C0 - C5, should not exceed 100mA. 2] The sum of all IOL, for ports C6, D0 - D4, should not exceed 100mA. 3] The sum of all IOL, for ports B0 - B7, D5 - D7, should not exceed 100mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: Atmel ATA6612C/ATA6613C: 1] The sum of all IOH, for ports C0 - C5, should not exceed 100mA. 2] The sum of all IOH, for ports C6, D0 - D4, should not exceed 100mA. 3] The sum of all IOH, for ports B0 - B7, D5 - D7, should not exceed 100mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. All DC Characteristics contained in this datasheet are based on actual Atmel ATA6612C microcontrollers characterization. 6. Values with "Power Reduction REgister - PRR" enabled (0xEF). ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 5.25.2 External Clock Drive Waveforms Figure 5-128. External Clock Drive Waveforms tCHCX tCLCH tCHCX tCHCL VIH1 VIL1 tCLCX tCLCL 5.25.3 External Clock Drive Table 5-130. External Clock Drive VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V Symbol Min. Max. Min. Max. Units 1/tCLCL 0 8 0 16 MHz Clock period tCLCL 125 62.5 ns High time tCHCX 50 25 ns Low time tCLCX 50 Rise time tCLCH 1.6 0.5 s Fall time tCHCL 1.6 0.5 s Change in period from one clock cycle to the next tCLCL 2 2 % Parameter Oscillator frequency 25 ns 5.25.4 Maximum Speed versus VCC Maximum frequency is dependent on VCC. As shown in Figure 5-129, the maximum frequency versus VCC curve is linear between 2.7V < VCC < 4.5V. Figure 5-129. Maximum Frequency versus VCC, Atmel ATA6612C/ATA6613C 16MHz 8MHz Safe Operating Area 2.7V 4.5V 5.5V ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 273 5.26 LIN Re-synchronization Algorithm 5.26.1 Synchronization Algorithm The possibility to change the value of OSCCAL during the oscillator operation allows for in-situ calibration of the slave node to entering master frames. The principle of operation is to measure the TBit during the SYNCH byte and to change the calibration value of OSCCAL to recover from local frequency drifts due to local voltage or temperature deviation. The algorithm used for the synchronization of the internal RC oscillator is depicted in Figure 5-130. Figure 5-130. Dichotomic Algorithm Used for LIN Slave Clock Re-synchronization Measuring actual TBit -2% < Delta(TBit) < 2% N Decrement OSCCAL Delta(TBit) > 2% N Increment OSCCAL 274 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Delta(TBit) < -2% Y STOP: Oscillator Calibrated 5.26.2 Precaution Against OSCCAL Discontinuity The Figure 6-26 on page 288 illustrates the on-purpose discontinuity of RC frequency versus OSCCAL value. For one correct re-synchronization, the frequency change must be kept on the same side of the discontinuity (no change of OSCCAL[7]). Since there will be no device having frequency changed by more than 10% (see Figure 6-24 on page 287), thus no reason to change the frequency value by more than 10%. Therefore, when calibration tries to cross the border because of subsequent increase (or decrease) in OSCCAL values, then the routine must be stopped. Example: For parts operating in the lower part of the curve, if New_OSCCAL > 127 then New_OSCCAL = 127. Similar for parts operating on the high side of the discontinuity. 5.26.2.1 RC Oscillator Precision for LIN Slave implementation For LIN slave devices, the precision of the RC oscillator before and after re-synchronization are described in the Table 5-131. Table 5-131. Oscillator Tolerance Before and After Re-synchronization Algorithm (2.7V < VCC < 5.5V, -40C to +125C) F/FMaster Parameter Clock Tolerance FTOL_UNSYNCH Deviation of slave node clock from the nominal clock rate before synchronization; relevant for nodes making use of synchronization and direct SYNCH BREAK detection. FTOL_SYNCH Deviation of slave node clock relative to the master node clock after synchronization; relevant for nodes making use of synchronization; any slave node must stay within this tolerance for all fields of a frame which follow the SYNCH FIELD. Note: 14.0% 2.0% For communication between any two nodes their bit rate must not differ by more than 2%. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 275 6. 2-wire Serial Interface Characteristics Table 6-1 describes the requirements for devices connected to the 2-wire serial bus. The Atmel(R) ATA6612C/ATA6613C 2-wire serial interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 6-1 on page 277. Table 6-1. 2-wire Serial Bus Requirements Parameter Condition Input low-voltage Input high-voltage Hysteresis of schmitt trigger inputs Output low-voltage 3mA sink current 10pF < Cb < 400pF 0.1VCC < Vi < 0.9VCC Capacitance for each I/O pin SCL clock frequency Max Units VIL -0.5 0.3 VCC V VIH 0.7 VCC VCC + 0.5 V Vhys(1) 0.05 VCC(2) - V 0 0.4 V 300 ns tr (3) Spikes suppressed by input filter Input current each I/O pin Min VOL Rise time for both SDA and SCL Output fall time from VIHmin to VILmax Symbol (1) (1) tof fCK > max(16fSCL, 250kHz)(5) 250 ns 0 50(2) ns Ii -10 10 A - 10 pF fSCL 0 400 kHz V CC - 0,4V --------------------------3mA 1000ns ----------------Cb V CC - 0,4V --------------------------3mA 300ns -------------Cb 4.0 - s 0.6 - s 4.7 - s 1.3 - s 4.0 - s 0.6 - s 4.7 - s 0.6 - s 0 3.45 s 0 0.9 s 250 - ns - ns Rp fSCL > 100kHz Hold time (repeated) START condition Low period of the SCL clock High period of the SCL clock Set-up time for a repeated START condition Data hold time Data setup time Notes: 276 1. fSCL 100kHz tHD;STA fSCL > 100kHz fSCL 100kHz(6) fSCL > 100kHz fSCL 100kHz fSCL > 100kHz fSCL 100kHz fSCL > 100kHz fSCL 100kHz fSCL > 100kHz fSCL 100kHz (7) 20 + (1) fSCL 100kHz Value of pull-up resistor 20 + 0.1Cb(2,3) 0.1Cb(2,3) tSP(1) Ci (4) (1) tLOW tHIGH tSU;STA tHD;DAT tSU;DAT fSCL > 100kHz 100 In Atmel ATA6612C/ATA6613C, this parameter is characterized and not 100% tested. 2. Required only for fSCL > 100kHz. 3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency 5. This requirement applies to all Atmel ATA6612C/ATA6613C 2-wire serial interface operation. Other devices connected to the 2-wire serial bus need only obey the general fSCL requirement. 6. The actual low period generated by the Atmel ATA6612C/ATA6613C 2-wire serial interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6MHz for the low time requirement to be strictly met at fSCL = 100kHz. 7. The actual low period generated by the Atmel ATA6612C/ATA6613C 2-wire serial interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308kHz when fCK = 8MHz. Still, Atmel ATA6612C/ATA6613C devices connected to the bus may communicate at full speed (400kHz) with other Atmel ATA6612C/ATA6613C devices, as well as any other device with a proper tLOW acceptance margin. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Table 6-1. 2-wire Serial Bus Requirements (Continued) Parameter Condition fSCL 100kHz Setup time for STOP condition 1. tSU;STO fSCL > 100kHz fSCL 100kHz Bus free time between a STOP and START condition Notes: Symbol tBUF Min Max Units 4.0 - s 0.6 - s 4.7 - s - s fSCL > 100kHz 1.3 In Atmel ATA6612C/ATA6613C, this parameter is characterized and not 100% tested. 2. Required only for fSCL > 100kHz. 3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency 5. This requirement applies to all Atmel ATA6612C/ATA6613C 2-wire serial interface operation. Other devices connected to the 2-wire serial bus need only obey the general fSCL requirement. 6. The actual low period generated by the Atmel ATA6612C/ATA6613C 2-wire serial interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6MHz for the low time requirement to be strictly met at fSCL = 100kHz. 7. The actual low period generated by the Atmel ATA6612C/ATA6613C 2-wire serial interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308kHz when fCK = 8MHz. Still, Atmel ATA6612C/ATA6613C devices connected to the bus may communicate at full speed (400kHz) with other Atmel ATA6612C/ATA6613C devices, as well as any other device with a proper tLOW acceptance margin. Figure 6-1. 2-wire Serial Bus Timing tof tHIGH tLOW tr tLOW SCL tSU,STA tHD,STA tHD,DAT tSU,DAT tSU,STO SDA tBUF ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 277 6.1 SPI Timing Characteristics See Figure 6-2 and Figure 6-3 on page 279 for details. Table 6-2. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 5-70 on page 162 2 SCK high/low Master 50% duty cycle 3 Rise/fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 x tsck 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave 15 10 SCK period Slave 4 x tck 11 SCK high/low(1) Slave 2 x tck 12 Rise/fall time Slave 13 Setup Slave 10 14 Hold Slave tck 15 SCK to out Slave 16 SCK to SS high Slave 17 SS high to tri-state Slave ns 1600 15 20 10 18 SS low to SCK Slave 20 Note: 1. In SPI programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12MHz - 3 tCLCL for fCK > 12MHz Figure 6-2. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 ... MSB LSB 8 7 MOSI (Data Output) 278 MSB ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 ... LSB Figure 6-3. SPI Interface Timing Requirements (Slave Mode) SS 16 10 9 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 ... MSB LSB 17 15 MISO (Data Output) 6.2 ... MSB LSB X ADC Characteristics Table 6-3. ADC Characteristics Parameter Condition Symbol Min Resolution Typ Max Units 10 Bits VREF = 4V, VCC = 4V, ADC clock = 200kHz 2 3.5 LSB VREF = 4V, VCC = 4V, ADC clock = 200kHz Noise reduction mode 2 3.5 LSB Integral non-linearity (INL) VREF = 4V, VCC = 4V, ADC clock = 200kHz 0.6 2.5 LSB Differential non-linearity (DNL) VREF = 4V, VCC = 4V, ADC clock = 200kHz 0.40 1.0 LSB Gain error VREF = 4V, VCC = 4V, ADC clock = 200kHz -1.3 3.5 LSB Offset error VREF = 4V, VCC = 4V, ADC clock = 200kHz 1.8 3.5 LSB Conversion time Free running conversion 50 200 kHz Absolute accuracy (including INL, DNL, quantization error, gain and offset error) -3.5 13 cycles Clock frequency s Analog supply voltage AVCC VCC - 0.3 VCC + 0.3 V Reference voltage VREF 1.0 AVCC V Input voltage VIN GND VREF V Internal voltage reference VINT 1.0 1.1 1.2 V Reference input resistance RREF 22.4 32 41.6 k Analog input resistance RAIN 100 M ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 279 6.3 Atmel ATA6612C/ATA6613C Typical Characteristics Note: 6.3.1 Values of temp refer to Tcase. Active Supply Current Figure 6-4. Active Supply Current versus Frequency (1MHz to 20MHz), Temp = 125C 20 18 16 5.5V ICC (mA) 14 5.0V 12 4.5V 10 8 3.3V 3.0V 6 2.7V 4 2 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 6-5. Idle Supply Current versus Frequency (1MHz to 20MHz), Temp = 125C 6 4 ICC (mA) 5.5V 5.0V 4.5V 3.3V 3.0V 2.7V 2 0 0 2 4 6 8 10 12 Frequency (MHz) 280 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 14 16 18 20 6.3.1.1 Power-down Supply Current Figure 6-6. Power-down Supply Current versus VCC (Watchdog Timer Disabled) 8 7 ICC (A) 6 125 5 85 4 25 -40 3 2 1 0 3 3.5 4 4.5 5 5.5 VCC (V) Figure 6-7. Power-down Supply Current versus VCC (Watchdog Timer Enabled) 8 7 ICC (A) 6 125 5 85 4 25 -40 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 281 6.3.1.2 Pin Pull-up Figure 6-8. I/O Pin Pull-up Resistor Current versus Input Voltage (VCC = 5V) 160 125 140 -40 IOP (A) 120 100 80 60 40 20 0 0 1 2 3 4 5 6 VOP (V) Figure 6-9. Output Low Voltage versus Output Low Current (VCC = 5V) 0.8 0.7 125C 0.6 85C VOL (V) 0.5 25C 0.4 -40C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 6-10. Output Low Voltage versus Output Low Current (VCC = 3V) 1.2 125C 1.0 85C IOL (mA) 0.8 25C 0.6 -40C 0.4 0.2 0 0 2 4 6 8 10 VOL (V) 282 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 12 14 16 18 20 Figure 6-11. Output High Voltage versus Output High Current (VCC = 5V) 5.2 5 VOH (V) 4.8 4.6 -40C 25C 85C 125C 4.4 4.2 4 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 6-12. Output High Voltage versus Output High Current (VCC = 3V) 3.5 3 Current (V) 2.5 -40C 25C 85C 125C 2 1.5 1 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 6-13. Reset Pull-Up Resistor Current versus Reset Pin Voltage (VCC = 5V) 160 125 140 120 -40 IOP (A) 100 80 60 40 20 0 0 1 2 3 4 5 6 VOP (V) ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 283 6.3.1.3 Pin Driver Strength Figure 6-14. Output Low Voltage versus Output Low Current (VCC = 5V) 0.8 0.7 125C 0.6 85C VOL (V) 0.5 25C 0.4 -40C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 6-15. Output Low Voltage versus Output Low Current (VCC = 3V) 1.2 125C 1.0 85C IOL (mA) 0.8 25C 0.6 -40C 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 VOL (V) Figure 6-16. Output High Voltage versus Output High Current (VCC = 5V) 5.2 5 VOH (V) 4.8 4.6 -40C 25C 85C 125C 4.4 4.2 4 0 2 4 6 8 10 IOH (mA) 284 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 12 14 16 18 20 Figure 6-17. Output High Voltage versus Output High Current (VCC = 3V) 3.5 3 Current (V) 2.5 -40C 25C 85C 125C 2 1.5 1 0.5 0 0 2 4 6 8 10 14 12 16 18 20 IOH (mA) 6.3.1.4 Pin Thresholds and Hysteresis Figure 6-18. I/O Pin Input Threshold versus VCC (VIH, I/O Pin Read as 1) 3.5 Vih (V) 3 125 2.5 85 25 2 -40 1.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 6-19. I/O Pin Input Threshold versus VCC (VIL, I/O Pin Read as 0) 3 125 C -40 C 2.5 Vil (V) 2 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 285 Figure 6-20. Reset Input Threshold Voltage versus VCC (VIH, Reset Pin Read as 1) 4 3.5 Threshold (V) 3 -40C 25C 85C 125C 2.5 2 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 6-21. Reset Input Threshold Voltage versus VCC (VIL, Reset Pin Read as 0) 2.5 125C 85C 25C -40C Threshold (V) 2 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 6.3.1.5 Internal Oscillator Speed Figure 6-22. Watchdog Oscillator Frequency versus VCC 130 128 -40C 126 FRC (kHz) 124 25C 122 120 85C 125C 118 116 114 112 110 2.5 3 3.5 4 VCC (V) 286 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 4.5 5 5.5 Figure 6-23. Calibrated 8MHz RC Oscillator Frequency versus Temperature 8.4 8.3 FRC (MHz) 8.2 5.0V 8.1 2.7V 8.0 7.9 7.8 7.7 7.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature Figure 6-24. Calibrated 8MHz RC Oscillator Frequency versus VCC 8.4 FRC (MHz) 8.2 8 125C 85C 25C 7.8 -40C 7.6 7.4 7.2 7 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 6-25. Calibrated 8MHz RC Oscillator Frequency versus OSCAL Value (for ATA6613C) 16 125C 85C 25C -40C 14 FRC (MHz) 12 10 8 6 4 2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 287 Figure 6-26. Calibrated 8MHz RC Oscillator Frequency versus OSCAL Value (for Atmel ATA6612C only) 14 125C 85C 25C -40C 12 FRC (MHz) 10 8 6 4 2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) 6.3.1.6 BOD Thresholds and Analog Comparator Offset Figure 6-27. BOD Threshold versus Temperature (BODLEVEL is 4.0V) 4.6 4.5 Threshold (V) Rising VCC 4.4 Falling VCC 4.3 4.2 4.1 4 -55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 Temperature (C) Figure 6-28. BOD Threshold versus Temperature (BODLEVEL is 2.7V) 3 Threshold (V) 2.9 2.8 Rising VCC 2.7 Falling VCC 2.6 2.5 2.4 -50 -40 -30 -20 -10 0 10 20 30 40 50 Temperature (C) 288 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 60 70 80 90 100 110 120 Figure 6-29. Bandgap Voltage versus VCC 1.1 Bandgap Voltage (V) 1.095 1.09 85C 25C 125C 1.085 1.08 -40C 1.075 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 6.3.1.7 Peripheral Units Figure 6-30. Analog to Digital Converter GAIN versus VCC 0 -0.2 Error (LSB) -0.4 -0.6 4V IDLE -0.8 4V STD -1.0 -1.2 -1.4 -1.6 -50 0 50 100 150 Temperature Figure 6-31. Analog to Digital Converter OFFSET versus VCC 2.5 Error (LSB) 2.0 1.5 4V IDLE 4V STD 1.0 0.5 0 -50 0 50 100 150 Temperature ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 289 Figure 6-32. Analog to Digital Converter DNL versus VCC 0.40 0.35 Error (LSB) 0.30 0.25 4V IDLE 0.20 4V STD 0.15 0.10 0.05 0 -50 0 50 100 150 Temperature Figure 6-33. Analog to Digital Converter INL versus VCC 0.7 0.6 Error (LSB) 0.5 0.4 4V IDLE 4V STD 0.3 0.2 0.1 0 -50 0 50 Temperature 290 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 100 150 6.4 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xFF) Reserved - - - - - - - - (0xFE) Reserved - - - - - - - - (0xFD) Reserved - - - - - - - - (0xFC) Reserved - - - - - - - - (0xFB) Reserved - - - - - - - - (0xFA) Reserved - - - - - - - - (0xF9) Reserved - - - - - - - - (0xF8) Reserved - - - - - - - - (0xF7) Reserved - - - - - - - - (0xF6) Reserved - - - - - - - - (0xF5) Reserved - - - - - - - - (0xF4) Reserved - - - - - - - - (0xF3) Reserved - - - - - - - - (0xF2) Reserved - - - - - - - - (0xF1) Reserved - - - - - - - - (0xF0) Reserved - - - - - - - - (0xEF) Reserved - - - - - - - - (0xEE) Reserved - - - - - - - - (0xED) Reserved - - - - - - - - (0xEC) Reserved - - - - - - - - (0xEB) Reserved - - - - - - - - (0xEA) Reserved - - - - - - - - (0xE9) Reserved - - - - - - - - (0xE8) Reserved - - - - - - - - (0xE7) Reserved - - - - - - - - (0xE6) Reserved - - - - - - - - (0xE5) Reserved - - - - - - - - (0xE4) Reserved - - - - - - - - (0xE3) Reserved - - - - - - - - (0xE2) Reserved - - - - - - - - (0xE1) Reserved - - - - - - - - (0xE0) Reserved - - - - - - - - Reserved - - - - - - - - (0xDF) Notes: Page 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATA6612C/ATA6613C is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. Only valid for Atmel ATA6612C/ATA6613C ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 291 6.4 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xDE) Reserved - - - - - - - - (0xDD) Reserved - - - - - - - - (0xDC) Reserved - - - - - - - - (0xDB) Reserved - - - - - - - - (0xDA) Reserved - - - - - - - - (0xD9) Reserved - - - - - - - - (0xD8) Reserved - - - - - - - - (0xD7) Reserved - - - - - - - - (0xD6) Reserved - - - - - - - - (0xD5) Reserved - - - - - - - - (0xD4) Reserved - - - - - - - - (0xD3) Reserved - - - - - - - - (0xD2) Reserved - - - - - - - - (0xD1) Reserved - - - - - - - - (0xD0) Reserved - - - - - - - - (0xCF) Reserved - - - - - - - - (0xCE) Reserved - - - - - - - - (0xCD) Reserved - - - - - - - - (0xCC) Reserved - - - - - - - - (0xCB) Reserved - - - - - - - - (0xCA) Reserved - - - - - - - - (0xC9) Reserved - - - - - - - - (0xC8) Reserved - - - - - - - - (0xC7) Reserved - - - - - - - - (0xC6) UDR0 (0xC5) UBRR0H (0xC4) UBRR0L (0xC3) Reserved Page USART I/O data register 180 USART baud rate register high 183 USART baud rate register low - - - - 183 - - - - UCSZ00 / UCPHA0 UCPOL0 182/191 (0xC2) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 /UDORD0 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 181 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 180 (0xBF) Reserved - - - - - - - - Reserved - - - - - - - - (0xBE) Notes: 292 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATA6612C/ATA6613C is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. Only valid for Atmel ATA6612C/ATA6613C ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 6.4 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 - 202 (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE 200 (0xBB) TWDR 2-wire serial interface data register 201 (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 202 (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 201 - - (0xB8) TWBR (0xB7) Reserved - 2-wire serial interface bit rate register (0xB6) ASSR - (0xB5) Reserved - - - EXCLK AS2 TCN2UB - - - - - 199 OCR2AUB OCR2BUB TCR2AUB - - - TCR2BUB 154 - (0xB4) OCR2B Timer/counter2 output compare register B 151 (0xB3) OCR2A Timer/counter2 output compare register A 151 (0xB2) TCNT2 (0xB1) TCCR2B FOC2A FOC2B - Timer/counter2 (8-bit) - WGM22 CS22 CS21 CS20 151 150 (0xB0) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0 - - WGM21 WGM20 148 (0xAF) Reserved - - - - - - - - (0xAE) Reserved - - - - - - - - (0xAD) Reserved - - - - - - - - (0xAC) Reserved - - - - - - - - (0xAB) Reserved - - - - - - - - (0xAA) Reserved - - - - - - - - (0xA9) Reserved - - - - - - - - (0xA8) Reserved - - - - - - - - (0xA7) Reserved - - - - - - - - (0xA6) Reserved - - - - - - - - (0xA5) Reserved - - - - - - - - (0xA4) Reserved - - - - - - - - (0xA3) Reserved - - - - - - - - (0xA2) Reserved - - - - - - - - (0xA1) Reserved - - - - - - - - (0xA0) Reserved - - - - - - - - (0x9F) Reserved - - - - - - - - (0x9E) Reserved - - - - - - - - (0x9D) Reserved - - - - - - - - Reserved - - - - - - - - (0x9C) Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATA6612C/ATA6613C is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. Only valid for Atmel ATA6612C/ATA6613C ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 293 6.4 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x9B) Reserved - - - - - - - - (0x9A) Reserved - - - - - - - - (0x99) Reserved - - - - - - - - (0x98) Reserved - - - - - - - - (0x97) Reserved - - - - - - - - (0x96) Reserved - - - - - - - - (0x95) Reserved - - - - - - - - (0x94) Reserved - - - - - - - - (0x93) Reserved - - - - - - - - (0x92) Reserved - - - - - - - - (0x91) Reserved - - - - - - - - (0x90) Reserved - - - - - - - - (0x8F) Reserved - - - - - - - - (0x8E) Reserved - - - - - - - - (0x8D) Reserved - - - - - - - - (0x8C) Reserved - - - - - - - - (0x8B) OCR1BH Page Timer/counter1 - output compare register B high byte 135 (0x8A) OCR1BL Timer/counter1 - output compare register B low byte 135 (0x89) OCR1AH Timer/counter1 - output compare register A high byte 135 (0x88) OCR1AL Timer/counter1 - output compare register A low byte 135 (0x87) ICR1H Timer/counter1 - input capture register high byte 136 (0x86) ICR1L Timer/counter1 - input capture register low byte 136 (0x85) TCNT1H Timer/counter1 - counter register high byte 135 (0x84) TCNT1L (0x83) Reserved - - - (0x82) TCCR1C FOC1A FOC1B - - - - - - 135 (0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 134 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 132 (0x7F) DIDR1 - - - - - - AIN1D AIN0D 223 (0x7E) DIDR0 - - ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 238 (0x7D) Reserved - - - - - - - - (0x7C) ADMUX REFS1 REFS0 ADLAR - MUX3 MUX2 MUX1 MUX0 235 (0x7B) ADCSRB - ACME - - - ADTS2 ADTS1 ADTS0 238 ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 236 (0x7A) Notes: 294 Timer/counter1 - counter register low byte - - - 135 - - 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATA6612C/ATA6613C is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. Only valid for Atmel ATA6612C/ATA6613C ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 6.4 Register Summary (Continued) Address Name (0x79) ADCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page ADC data register high byte 237 (0x78) ADCL (0x77) Reserved - - - ADC data register low byte - - - - - 237 (0x76) Reserved - - - - - - - - (0x75) Reserved - - - - - - - - (0x74) Reserved - - - - - - - - (0x73) Reserved - - - - - - - - (0x72) Reserved - - - - - - - - (0x71) Reserved - - - - - - - - (0x70) TIMSK2 - - - - - OCIE2B OCIE2A TOIE2 152 (0x6F) TIMSK1 - - ICIE1 - - OCIE1B OCIE1A TOIE1 136 (0x6E) TIMSK0 - - - - - OCIE0B OCIE0A TOIE0 111 (0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 96 (0x6C) PCMSK1 - PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 96 (0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 96 (0x6A) Reserved - - - - - - - - (0x69) EICRA - - - - ISC11 ISC10 ISC01 ISC00 (0x68) PCICR - - - - - PCIE2 PCIE1 PCIE0 (0x67) Reserved - - - - - - - - Oscillator Calibration Register 93 (0x66) OSCCAL (0x65) Reserved - - - - - - - - 52 (0x64) PRR PRTWI PRTIM2 PRTIM0 - PRTIM1 PRSPI PRUSAR0 PRADC (0x63) Reserved - - - - - - - - (0x62) Reserved - - - - - - - - (0x61) CLKPR CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 54 (0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 68 0x3F (0x5F) SREG I T H S V N Z C 33 (5) 58 0x3E (0x5E) SPH - - - - - (SP10) SP9 SP8 35 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 35 0x3C (0x5C) Reserved - - - - - - - - 0x3B (0x5B) Reserved - - - - - - - - 0x3A (0x5A) Reserved - - - - - - - - 0x39 (0x59) Reserved - - - - - - - - 0x38 (0x58) Reserved - - - - - - - - Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATA6612C/ATA6613C is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. Only valid for Atmel ATA6612C/ATA6613C ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 295 6.4 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 5. Bit 4 (5) - (RWWSRE) Bit 3 Bit 2 Bit 1 Bit 0 Page BLBSET PGWRT PGERS SELFPRGEN 244 0x37 (0x57) SPMCSR SPMIE (RWWSB) 0x36 (0x56) Reserved - - - - - - - - 0x35 (0x55) MCUCR - - - PUD - - IVSEL IVCE 0x34 (0x54) MCUSR - - - - WDRF BORF EXTRF PORF 0x33 (0x53) SMCR - - - - SM2 SM1 SM0 SE 0x32 (0x52) Reserved - - - - - - - - 0x31 (0x51) Reserved - - - - - - - - 56 0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 0x2F (0x4F) Reserved - - - - - - - - 0x2E (0x4E) SPDR 0x2D (0x4D) SPSR SPIF WCOL - - - - - SPI2X 162 0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 161 0x2B (0x4B) GPIOR2 SPI data register 163 General purpose I/O register 2 45 0x2A (0x4A) GPIOR1 0x29 (0x49) Reserved 0x28 (0x48) OCR0B Timer/counter0 output compare register B 0x27 (0x47) OCR0A Timer/counter0 output compare register A General purpose I/O register 1 - - - - 45 - - - - CS01 CS00 0x26 (0x46) TCNT0 0x25 (0x45) TCCR0B FOC0A FOC0B - - WGM02 CS02 0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 - - WGM01 WGM00 0x23 (0x43) GTCCR TSM - - - - - PSRASY PSRSYNC Timer/counter0 (8-bit) 0x22 (0x42) EEARH (EEPROM address register high byte) 0x21 (0x41) EEARL EEPROM address register low byte 0x20 (0x40) EEDR 0x1F (0x3F) EECR 0x1E (0x3E) GPIOR0 0x1D (0x3D) 222 113/156 5. 41 41 EEPROM data register - EEPM1 EIMSK - - - - - 0x1C (0x3C) EIFR - - - - - - 0x1B (0x3B) PCIFR - - - - - PCIF2 0x1A (0x3A) Reserved - - - - - - - - 0x19 (0x39) Reserved - - - - - - - - 0x18 (0x38) Reserved - - - - - - - - 0x17 (0x37) TIFR2 - - - - - OCF2B OCF2A TOV2 152 TIFR1 - - ICF1 - - OCF1B OCF1A TOV1 137 0x16 (0x36) Notes: 296 EEPM0 EERIE 41 - EEMPE EEPE EERE 41 INT1 INT0 94 INTF1 INTF0 94 PCIF1 PCIF0 General purpose I/O register 0 45 - 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATA6612C/ATA6613C is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. Only valid for Atmel ATA6612C/ATA6613C ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 6.4 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x15 (0x35) TIFR0 - - - - - OCF0B OCF0A TOV0 0x14 (0x34) Reserved - - - - - - - - 0x13 (0x33) Reserved - - - - - - - - 0x12 (0x32) Reserved - - - - - - - - 0x11 (0x31) Reserved - - - - - - - - 0x10 (0x30) Reserved - - - - - - - - 0x0F (0x2F) Reserved - - - - - - - - Page 0x0E (0x2E) Reserved - - - - - - - - 0x0D (0x2D) Reserved - - - - - - - - 0x0C (0x2C) Reserved - - - - - - - - 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 92 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 92 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 92 0x08 (0x28) PORTC - PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 91 0x07 (0x27) DDRC - DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 91 0x06 (0x26) PINC - PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 92 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 91 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 91 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 91 0x02 (0x22) Reserved - - - - - - - - 0x01 (0x21) Reserved - - - - - - - - Reserved - - - - - - - - 0x0 (0x20) Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATA6612C/ATA6613C is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. Only valid for Atmel ATA6612C/ATA6613C ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 297 6.5 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks Arithmetic and Logic Instructions ADD Rd, Rr Add two registers Rd Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with carry two registers Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add immediate to word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two registers Rd Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract constant from register Rd Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with carry two registers Rd Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with carry constant from reg. Rd Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract immediate from word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND registers Rd Rd x Rr Z,N,V 1 ANDI Rd, K Logical AND register and constant Rd Rd x K Z,N,V 1 OR Rd, Rr Logical OR registers Rd Rd v Rr Z,N,V 1 ORI Rd, K Logical OR register and constant Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR registers Rd Rd Rr Z,N,V 1 COM Rd One's complement Rd 0xFF - Rd Z,C,N,V 1 NEG Rd Two's complement Rd 0x00 - Rd Z,C,N,V,H 1 SBR Rd,K Set bit(s) in register Rd Rd v K Z,N,V 1 CBR Rd,K Clear bit(s) in register Rd Rd x (0xFF - K) Z,N,V 1 INC Rd Increment Rd Rd + 1 Z,N,V 1 DEC Rd Decrement Rd Rd - 1 Z,N,V 1 TST Rd Test for zero or minus Rd Rd x Rd Z,N,V 1 CLR Rd Clear register Rd Rd Rd Z,N,V 1 SER Rd Set register Rd 0xFF None 1 MUL Rd, Rr Multiply unsigned R1:R0 Rd x Rr Z,C 2 MULS Rd, Rr Multiply signed R1:R0 Rd x Rr Z,C 2 MULSU Rd, Rr Multiply signed with unsigned R1:R0 Rd x Rr Z,C 2 FMUL Rd, Rr Fractional multiply unsigned R1:R0 (Rd x Rr) << 1 Z,C 2 FMULS Rd, Rr Fractional multiply signed R1:R0 (Rd x Rr) << 1 Z,C 2 FMULSU Rd, Rr Fractional multiply signed with unsigned R1:R0 (Rd x Rr) << 1 Z,C 2 Branch Instructions RJMP k IJMP Relative jump PC PC + k + 1 None 2 Indirect jump to (Z) PC Z None 2 (1) JMP k Direct jump PC k None 3 RCALL k Relative subroutine call PC PC + k + 1 None 3 Indirect call to (Z) PC Z None 3 Direct subroutine call PC k None 4 RET Subroutine return PC STACK None 4 RETI Interrupt return PC STACK I 4 None 1/2/3 ICALL CALL (1) CPSE Rd,Rr Compare, skip if equal if (Rd = Rr) PC PC + 2 or 3 CP Rd,Rr Compare Rd - Rr Z, N,V,C,H 1 Rd - Rr - C Z, N,V,C,H 1 CPC Note: 1. 298 k Rd,Rr Compare with carry These instructions are only available in ATA6613C ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 6.5 Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clocks CPI Rd,K Compare register with immediate Rd - K Z, N,V,C,H 1 SBRC Rr, b Skip if bit in register cleared if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3 SBRS Rr, b SBIC P, b Skip if bit in register is set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3 Skip if bit in I/O register cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3 SBIS P, b Skip if bit in I/O register is set if (P(b)=1) PC PC + 2 or 3 None 1/2/3 BRBS s, k Branch if status flag set if (SREG(s) = 1) then PC PC + k+1 None 1/2 BRBC s, k Branch if status flag cleared if (SREG(s) = 0) then PC PC + k+1 None 1/2 BREQ k Branch if equal if (Z = 1) then PC PC + k + 1 None 1/2 BRNE k Branch if not equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if carry set if (C = 1) then PC PC + k + 1 None 1/2 BRCC k Branch if carry cleared if (C = 0) then PC PC + k + 1 None 1/2 BRSH k Branch if same or higher if (C = 0) then PC PC + k + 1 None 1/2 BRLO k Branch if lower if (C = 1) then PC PC + k + 1 None 1/2 BRMI k Branch if minus if (N = 1) then PC PC + k + 1 None 1/2 BRPL k Branch if plus if (N = 0) then PC PC + k + 1 None 1/2 BRGE k Branch if greater or equal, signed if (N V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if less than zero, signed if (N V= 1) then PC PC + k + 1 None 1/2 BRHS k Branch if half carry flag set if (H = 1) then PC PC + k + 1 None 1/2 BRHC k Branch if half carry flag cleared if (H = 0) then PC PC + k + 1 None 1/2 BRTS k Branch if T flag set if (T = 1) then PC PC + k + 1 None 1/2 BRTC k Branch if T flag cleared if (T = 0) then PC PC + k + 1 None 1/2 BRVS k Branch if overflow flag is set if (V = 1) then PC PC + k + 1 None 1/2 BRVC k Branch if overflow flag is cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if interrupt enabled if (I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if interrupt disabled if (I = 0) then PC PC + k + 1 None 1/2 Bit and Bit- Test Instructions SBI P,b Set bit in I/O register I/O (P, b) 1 None 2 CBI P,b Clear bit in I/O register I/O (P, b) 0 None 2 LSL Rd Logical shift left Rd(n+1) Rd (n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical shift right Rd (n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate left through carry Rd(0) C, Rd(n+1) Rd (n), C Rd(7) Z,C,N,V 1 ROR Rd Rotate right through carry Rd(7) C, Rd(n) Rd(n+1), C Rd(0) Z,C,N,V 1 ASR Rd Arithmetic shift right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap nibbles Rd(3..0) Rd(7..4), Rd(7..4) Rd(3..0) None 1 BSET s Flag set SREG(s) 1 SREG(s) 1 BCLR s Flag clear SREG(s) 0 SREG(s) 1 T 1 BST Note: 1. Rr, b Bit store from register to T These instructions are only available in ATA6613C T Rr(b) ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 299 6.5 Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clocks BLD Rd, b Bit load from T to register Rd(b) T None 1 SEC Set carry C1 C 1 CLC Clear carry C0 C 1 SEN Set negative flag N1 N 1 CLN Clear negative flag N0 N 1 SEZ Set zero flag Z1 Z 1 CLZ Clear zero flag Z0 Z 1 SEI Global interrupt enable I1 I 1 CLI Global interrupt disable I0 I 1 SES Set signed test flag S1 S 1 CLS Clear signed test flag S0 S 1 SEV Set twos complement overflow. V1 V 1 CLV Clear twos complement overflow V0 V 1 SET Set T in SREG T1 T 1 CLT Clear T in SREG T0 T 1 SEH Set half carry flag in SREG H1 H 1 CLH Clear half carry flag in SREG H0 H 1 Data Transfer Instructions MOV Rd, Rr Move between registers Rd Rr None 1 MOVW Rd, Rr Copy register word Rd+1:Rd Rr+1:Rr None 1 LDI Rd, K Load immediate Rd K None 1 LD Rd, X Load indirect Rd (X) None 2 LD Rd, X+ Load indirect and post-inc. Rd (X), X X + 1 None 2 LD Rd, - X Load indirect and pre-dec. X X - 1, Rd (X) None 2 LD Rd, Y Load indirect Rd (Y) None 2 LD Rd, Y+ Load indirect and post-inc. Rd (Y), Y Y + 1 None 2 Load indirect and pre-dec. Y Y - 1, Rd (Y) None 2 Load indirect with displacement Rd (Y + q) None 2 LD Rd, - Y LDD Rd, Y+ q LD Rd, Z Load indirect Rd (Z) None 2 LD Rd, Z+ Load indirect and post-inc. Rd (Z), Z Z+1 None 2 Load indirect and pre-dec. Z Z - 1, Rd (Z) None 2 Load indirect with displacement Rd (Z + q) None 2 LD Rd, -Z LDD Rd, Z+q LDS Rd, k Load direct from SRAM Rd (k) None 2 ST X, Rr Store indirect (X) Rr None 2 ST X+, Rr Store indirect and post-inc. (X) Rr, X X + 1 None 2 ST - X, Rr Store indirect and pre-dec. X X - 1, (X) Rr None 2 ST Y, Rr Store indirect (Y) Rr None 2 ST Y+, Rr Store indirect and post-inc. (Y) Rr, Y Y + 1 None 2 ST - Y, Rr Store indirect and pre-dec. Y Y - 1, (Y) Rr None 2 STD Y+q,Rr Store indirect with displacement (Y + q) Rr None 2 (Z) Rr None 2 ST Z, Rr Store indirect These instructions are only available in ATA6613C Note: 1. 300 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 6.5 Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clocks ST Z+, Rr Store indirect and post-inc. (Z) Rr, Z Z + 1 None 2 ST -Z, Rr Store indirect and pre-dec. Z Z - 1, (Z) Rr None 2 STD Z+q,Rr Store indirect with displacement (Z + q) Rr None 2 STS k, Rr Store direct to SRAM (k) Rr None 2 Load program memory R0 (Z) None 3 LPM LPM Rd, Z Load program memory Rd (Z) None 3 LPM Rd, Z+ Load program memory and post-inc Rd (Z), Z Z+1 None 3 Store program memory (Z) R1:R0 None - SPM IN Rd, P In port Rd P None 1 OUT P, Rr Out port P Rr None 1 PUSH Rr Push register on stack STACK Rr None 2 POP Rd Pop register from stack Rd STACK None 2 None 1 MCU Control Instructions NOP SLEEP WDR BREAK Note: 1. No operation Sleep (see specific descr. for sleep function) None 1 Watchdog reset (see specific descr. for WDR/timer) None 1 For on-chip debug only None N/A Break These instructions are only available in ATA6613C ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 301 7. Application Figure 7-1. Typical LIN Slave Application C1 100nF 37 GND2 38 39 PB6 MCUVCC 40 PB7 41 PD5 42 PD6 43 PD7 44 PB0 45 PB1 46 PB2 47 PB3 VCC LIN 32 31 30 29 28 VBAT 27 26 PVCC 25 GND PVCC + 24 23 14 13 22 PC5 KL_15 PC4 MODE VS TM PC3 WD_OSC EN NRES PC2 PC6 12 33 GND NTRIG 220pF 34 WAKE PC1 21 11 PC0 TDX 10 Atmel ATA6612C/ATA6613C ADC7 20 9 LIN INH 8 PD3 GND4 19 7 AREF RXD 6 PD4 18 5 ADC6 C2 100nF 35 GND1 PD2 4 36 MCUVCC MCUAVCC 17 3 PB5 PD1 2 16 1 PD0 PB5 15 100nF PB4 48 PB4 PB3 100nF 22F + 100nF 100nF 10F PC6 10k 47k INH KL_15 MODE* 51k 10k* PB4 1 PVCC PB5 PB3 PC6 ISP * The MODE pin can be connected directly to GND, if it is not needed to disable the Watchdog Note: 302 All open pins of the SiP can be used for application-specific purposes. AVR: Internal clock, no ADC application, TXD, RXD, NRES, EN and NTRIG connected for LIN Slave. The connection between the LIN-SBC and the AVR(R) requires the software being programmed correspondingly. SBC: LIN slave operation with watchdog, 5V regulator and KL15 wake up RF emissions: Best results for RF emissions will be achieved by connecting the blocking capacitors of the microcontroller supply (C1 and C2) between the microcontroller pins and the GND/PVCC line. See also Figure 7-1. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Figure 7-2. Typical LIN Master Application 1 PB4 22pF 22pF PVCC PB5 XTAL PB3 PC6 C1 100nF ISP 37 GND2 38 39 PB6 MCUVCC 40 PB7 41 PD5 42 PD6 43 PD7 44 PB0 45 PB1 46 PB2 47 PB3 ADC7 GND ATA6612C/ATA6613C PC0 WAKE PC1 NTRIG PC2 EN PC3 VS VCC KL_15 MODE PVCC C2 100nF 35 560pF 34 33 LIN 32 31 33k 30 WAKE 29 10k 28 VBAT 27 26 PVCC 25 GND 1k + 24 TM 23 WD_OSC 22 14 13 21 PC5 NRES PC4 PC6 12 LIN Atmel TDX 11 GND4 20 9 10 PD3 INH 8 AREF 19 7 PD4 RXD 6 ADC6 18 5 GND1 PD2 4 36 MCUVCC MCUAVCC 17 3 PB5 PD1 2 16 1 PD0 PB5 15 100nF PB4 48 PB4 PB3 100nF 22F + 51k PC6 100nF 10F MODE* 10k 10k* * The MODE pin can be connected directly to GND, if it is not needed to disable the Watchdog Note: All open pins of the SiP can be used for application-specific purposes. AVR: TXD, RXD, NRES and EN connected for LIN Master. The connection between the LIN-SBC and the AVR requires the software being programmed correspondingly. Analog digital converter not active; system clock from external crystal. LIN-SBC: Master application with 5V regulator and watchdog, 1k master resistance connected via diode to VBAT, local wake up via pin WAKE. RF emissions: Best results for RF emissions will be achieved by connecting the blocking capacitors of the microcontroller supply (C1 and C2) between the microcontroller pins and the GND/PVCC line. See also Figure 7-2. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 303 Figure 7-3. Typical LIN Master Application LIN Master Pull-up Switched Off during Sleep Mode 1 PB4 22pF 22pF PVCC PB5 XTAL PB3 PC6 C1 100nF ISP 37 GND2 38 39 PB6 MCUVCC 40 PB7 41 PD5 42 PD6 43 PD7 44 PB0 45 PB1 46 PB2 47 PB3 Atmel ATA6612C/ATA6613C ADC7 PC0 GND WAKE PC1 NTRIG PC2 EN PC3 VS VCC KL_15 MODE PVCC C2 100nF 35 34 10k 560pF 33 LIN 32 31 33k 30 WAKE 29 10k 28 VBAT 27 26 PVCC 25 GND 1k + 24 TM 23 WD_OSC 22 14 13 21 PC5 NRES PC4 PC6 12 LIN TDX 11 GND4 20 9 10 PD3 INH 8 AREF 19 7 PD4 RXD 6 ADC6 18 5 GND1 PD2 4 36 MCUVCC MCUAVCC 17 3 PB5 PD1 2 16 1 PD0 PB5 15 100nF PB4 48 PB4 PB3 100nF 22F + 51k 100nF 10F PC6 MODE* 10k 10k* * The MODE pin can be connected directly to GND, if it is not needed to disable the Watchdog Note: 304 All open pins of the SiP can be used for application-specific purposes. AVR: TXD, RXD, NRES and EN connected for LIN Master. The connection between the LIN-SBC and the AVR requires the software being programmed correspondingly. Analog digital converter not active; system clock from external crystal. LIN-SBC: Master application with 5V regulator and watchdog, 1k master resistance connected via diode and INH output to VBAT, local wake up via pin WAKE. RF emissions: Best results for RF emissions will be achieved by connecting the blocking capacitors of the microcontroller supply (C1 and C2) between the microcontroller pins and the GND/PVCC line. See also Figure 7-3. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Figure 7-4. LIN Slave Application with Minimum External Components C1 100nF 37 GND2 38 MCUVCC 39 PB6 40 PB7 41 42 PD6 43 PD7 44 PB0 45 PB1 46 PB2 47 PB3 PD5 GND ATA6612C/ATA6613C PC0 WAKE PC1 NTRIG PC2 EN PC3 VS VCC KL_15 MODE C2 100nF 35 34 220pF 33 LIN 32 31 30 29 28 VBAT 27 26 PVCC 25 GND PVCC + 24 TM 23 WD_OSC 22 14 13 21 PC5 NRES PC4 PC6 12 ADC7 TDX 11 LIN Atmel 20 10 GND4 INH 9 PD3 19 8 AREF RXD 7 PD4 18 6 ADC6 PD2 5 GND1 17 4 36 MCUVCC MCUAVCC PD1 3 PB5 16 2 PD0 PB5 1 15 100nF PB4 48 PB4 PB3 100nF 22F + 100nF PC6 10F 10k PB4 1 PVCC PB5 PB3 PC6 ISP Note: All open pins of the SiP can be used for application-specific purposes. AVR: Internal clock, no ADC application, TXD, RXD, NRES and EN connected for LIN Slave. The connection between the LIN-SBC and the AVR requires the software being programmed correspondingly. SBC: LIN slave operation with 5V regulator, no watchdog, no local wake-up. RF emissions: Best results for RF emissions will be achieved by connecting the blocking capacitors of the microcontroller supply (C1 and C2) between the microcontroller pins and the GND/PVCC line. See also Figure 7-4. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 305 8. 9. Ordering Information Extended Type Number Program Memory Package MOQ ATA6612C-PLQW-1 8kB flash QFN48, 7x7 4,000 pieces ATA6613C-PLQW-1 16kB flash QFN48, 7x7 4,000 pieces Package Information Top View D 48 1 technical drawings according to DIN specifications E PIN 1 ID Dimensions in mm A Side View A3 A1 12 Bottom View D2 13 24 25 12 E2 COMMON DIMENSIONS 1 A 36 48 37 e L A (10:1) (Unit of Measure = mm) Symbol MIN NOM MAX A 0.8 0.85 0.9 A1 0 0.035 0.05 A3 0.16 0.21 0.26 D 6.9 7 7.1 D2 5.5 5.6 5.7 E 6.9 7 7.1 E2 5.5 5.6 5.7 L 0.35 0.4 0.45 b e 0.2 0.25 0.5 0.3 NOTE b 05/20/14 TITLE Package Drawing Contact: packagedrawings@atmel.com 306 Package: QFN_7x7_48L Exposed pad 5.6x5.6 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 GPC DRAWING NO. REV. 6.543-5188.03-4 1 10. Errata 10.1 Atmel ATA6612C Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before an overflow interrupt occurs, the interrupt may be lost. Problem Fix/Workaround Always check that the timer2 timer/counter register, TCNT2, does not have the value 0xFF before writing the timer2 control register, TCCR2, or output compare register, OCR2. 10.2 Atmel ATA6613C Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before an overflow interrupt occurs, the interrupt may be lost. Problem Fix/Workaround Always check that the timer2 timer/counter register, TCNT2, does not have the value 0xFF before writing the timer2 control register, TCCR2, or output compare register, OCR2. ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 307 11. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History * Put datasheet in the latest template 9111L-AUTO-11/14 * Section 8 "Ordering Information" on page 306 updated * Section 9 "Package Information" on page 306 updated * Section 2 "Pin Configuration" on pages 2 to 3 updated * Table 3-1 "Maximum Ratings of the SIP" on page 4 updated * Table 3-2 "Maximum Ratings of the LIN-SBC" on pages 4 to 5 added * Table 3-3 "Maximum Ratings of the Microcontroller" on page 5 added 9111K-AUTO-03/13 * Figure 8-1 "Typical LIN Slave Application" on page 351 updated * Figure 8-2 "Typical LIN Master Application" on page 352 updated * Figure 8-3 "LIN Slave Application with Minimum External Components" on page 353 updated * Figure 8-4 "Typical LIN Master Application LIN Master Pull-up Switched Off during Sleep Mode" on page 354 updated 9111J-AUTO-11/12 * ATA6612P/ATA6613P renamed in ATA6612C/ATA6613C * General Features on page 1 changed * Section 3.1 "Features" on page 5 changed 9111I-AUTO-02/12 * Section 3.3 "Functional Description" on pages 7 to 19 changed * Section 4 "Absolute Maximum Ratings" on page 20 changed * Section 5 "Electrical Characteristics" on page 21 changed * Section 8 "Application" on pages 355 to 358 changed * Section 3.1 "Features" on page 5 changed * Section 3.3.3 "Ground Pin" on page 7 changed * Section 3.3.12 "Mode Input Pin (Mode)" on page 8 changed 9111H-AUTO-01/11 * Figure 3.2 "Modes of Operation" on page 10 changed * Section 3.3.20.4 "Fail-safe Mode" on page 13 changed * Section 3.3.23 "Voltage Regulator" on pages 16 to 17 changed * Section 6 "Electrical Characteristics" on pages 21 to 26 changed * Table 2-2 "Maximum Ratings of the SiP" on page 4 changed * Section 3.1 "Features" on page 5 changed * Section 3.2 "Description" on page 5 changed * Section 3.3.1 "Physical Layer Compatibility" on page 7 changed * Section 3.3.6 "Bus Pin LIN" on page 7 changed * Section 3.3.8 "TX Dominant Time-out Function" on page 8 changed 9111G-AUTO-05/10 * Section 3.3.10 "Enable Input Pin (EN)" on page 8 changed * Section 3.3.14 "KL_15 Pin" on page 9 changed * Section 3.3.20 "Modes of Operation" on pages 10 to 14 changed * Section 3.3.21 "Wake-up Scenarios from Silent to Sleep Mode on page 15 changed * Section 3.3.23 "Voltage Regulator" on page 16 changed * Section 6 "Electrical Characteristics" on page 23 changed * Section 7.7.7.1 "Power Reduction Register" on page 66 changed 308 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9111F-AUTO-12/08 * Section 11 "Errata" on page 360 changed * Table 2-2 "Maximum Ratings of the SiP" on page 4 changed * Section 4 "Absolute Maximum Ratings" on page 20 changed * Figure 8-1 "Typical LIN Slave Application" on page 355 changed 9111E-AUTO-07/08 * Figure 8-2 "Typical LIN Master Application" on page 356 changed * Figure 8-3 "LIN Slave Application with Minimum External Components" on page 357 changed * Figure 8-4 "Typical LIN Master Application LIN Master Pull-up Switched Off during Sleep Mode" on page 358 added * Figure 3-1 "Block Diagram" on page 6 changed 9111D-AUTO-06/08 9111C-AUTO-02/08 * Section 3.3 "Functional Description" on pages 7 to 18 changed * Section 6.5.3.2 "The EEPROM Address Register - EEARH and EEARL" on page 45 changed * Figure 8-2 "Typical LIN Master Application" on page 356 changed * Section 5 "Electrical Characteristics" on pages 21 to 26 changed 9111B-AUTO-11/07 * Section 6.6.6 "Calibrated Internal RC Oscillator" on page 57 changed * Figure 8-3 "LIN Slave Application with Minimum External Components on page 357 added ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 309 12. Table of Contents General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. LIN System-basis-chip Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 3.2 3.3 4. 5. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Microcontroller Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25 5.26 6. Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 About Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AVR CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AVR Atmel ATA6612C/ATA6613C Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 System Clock and Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 I/O-Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8-bit Timer/Counter0 with PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Timer/Counter0 and Timer/Counter1 Prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 16-bit Timer/Counter1 with PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8-bit Timer/Counter2 with PWM and Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . 137 Serial Peripheral Interface - SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 USART0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 USART in SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 2-wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 debugWIRE On-chip Debug System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Boot Loader Support - Read-While-Write Self-Programming, Atmel ATA6612C and ATA6613C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Memory Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 LIN Re-synchronization Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 2-wire Serial Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 6.1 6.2 6.3 6.4 6.5 310 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SPI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Atmel ATA6612C/ATA6613C Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7. Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 8. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 278 279 280 291 298 9. 10. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 10.1 10.2 Atmel ATA6612C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Atmel ATA6613C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 11. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 12. Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 ATA6612C/ATA6613C [DATASHEET] 9111L-AUTO-11/14 311 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com (c) 2014 Atmel Corporation. / Rev.: 9111L-AUTO-11/14 Atmel(R), Atmel logo and combinations thereof, Enabling Unlimited Possibilities(R), AVR(R), and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. 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