  
  
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D2-V to 6-V VCC Operation (’HC4511)
D4.5-V to 5.5-V VCC Operation
(CD74HCT4511)
DHigh-Output Sourcing Capability
− 7.5 mA at 4.5 V (CD74HCT4511)
− 10 mA at 6 V (’HC4511)
DInput Latches for BCD Code Storage
DLamp Test and Blanking Capability
DBalanced Propagation Delays and
Transition Times
DSignificant Power Reduction Compared to
LSTTL Logic ICs
D’HC4511
− High Noise Immunity,
NIL or NIH = 30% of VCC at VCC = 5 V
DCD74HCT4511
− Direct LSTTL Input Logic Compatibility,
VIL = 0.8 V Maximum, VIH = 2 V Minimum
− CMOS Input Compatibility, II ≤1 µA
at VOL, VOH
description/ordering information
The CD54HC4511, CD74HC4511, and CD74HCT4511 are BCD-to-7 segment latch/decoder/drivers with four
address inputs (D0−D3), an active-low blanking (BL) input, lamp-test (LT) input, and a latch-enable (LE) input
that, when high, enables the latches to store the BCD inputs. When LE i s lo w, the latches are disabled, making
the outputs transparent to the BCD inputs.
These devices have standard-size output transistors, but are capable of sourcing (at standard VOH levels) up
to 7.5 mA at 4.5 V. The HC types can supply up to 10 mA at 6 V.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − E
Tube of 25
CD74HC4511E CD74HC4511E
PDIP − E Tube of 25 CD74HCT4511E CD74HCT4511E
Tube of 40 CD74HC4511M
−55°C to 125°C
SOIC − M Reel of 2500 CD74HC4511M96 HC4511M
−55°C to 125°C
SOIC − M
Reel of 250 CD74HC4511MT
HC4511M
TSSOP − PW
Reel of 2000 CD74HC4511PWR
HJ4511
TSSOP − PW Reel of 250 CD74HC4511PWT HJ4511
CDIP − F Tube of 25 CD54HC4511F3A CD54HC4511F3A
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
  !" # $%&" !#  '%()$!" *!"&+
*%$"# $ " #'&$$!"# '& ",& "&#  &-!# #"%&"#
#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0  !)) '!!&"&#+
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D1
D2
LT
BL
LE
D3
D0
GND
VCC
f
g
a
b
c
d
e
BCD
Inputs
BCD
Inputs
7-Segment
Outputs
CD54HC4511 ...F PACKAGE
CD74HC4511 . . . E, M, OR PW PACKAGE
CD74HCT4511 ...E PACKAGE
(TOP VIEW)
01 23 456789
DISPLAY
a
b
c
d
e
fg
 '*%$"# $')!" " 1232 !)) '!!&"&# !& "&#"&*
%)&## ",&.#& "&*+  !)) ",& '*%$"# '*%$"
'$&##0 *&# " &$&##!)/ $)%*& "&#"0  !)) '!!&"&#+
  
  
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS OUTPUTS
LE BL LT D3D2D1D0a b c d e f g DISPLAY
X X L X X X X H H H H H H H 8
XLHXXXXLL L L L L L Blank
LHHLLLLHHHHHHL 0
LHHLLLHLHHLLLL 1
LHHLLHLHHLHHLH 2
LHHLLHHHHHHLLH 3
LHHLHLLLHHLLHH 4
LHHLHLHHLHHLHH 5
LHHLHHLLLHHHHH 6
LHHLHHHHHHLLLL 7
LHHHLLLHHHHHHH 8
LHHHLLHHHHLLHH 9
LHHHLHLLL L L L L L Blank
LHHHLHHLL L L L L L Blank
LHHHHLLLL L L L L L Blank
LHHHHLHLL L L L L L Blank
LHHHHHLLL L L L L L Blank
LHHHHHHLL L L L L L Blank
H H H X X X X † † † † † † † †
X = Don’t care
†Depends on BCD code previously applied when LE = L
NOTE: Display is blank for all illegal input codes (BCD > HLLH).
function diagram
7
1
2
6
5
4
D0
D1
D2
D3
LE
BL
LT 3
VSS = 8
VDD = 16
13
12
11
10
9
15
14
a
b
c
d
e
f
g
Latch
Decoder
Driver
7-Segment
Outputs
BCD
Inputs
  
  
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram
15
f
BL 4
6
2
1
7
5
14
9
11
12
13
a
b
c
e
g
3
LT
D3
D2
D1
D0
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Latch
Latch
Latch
Latch
LE
LE
10
d
  
  
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input diode current, IIK (VI < −0.5 V or VI > VCC + 0.5 V) ) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . .
Output diode current, IOK (VO < −0.5 V or VO > VCC + 0.5V) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . .
Continuous output source or sink current per output, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): E package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature (during soldering):
At distance 1/16 ±1/32 in (1.59 ±0.79 mm) from case for 10 s maximum 265°C. . . . . . . . . . . . . . . . . . . . .
Unit inserted into a PC board (minimum thickness 1/16 in, 1.59 mm),
with solder contacting lead tips only 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, Tstg −65 to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions for ’HC4511 (see Note 3)
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
VCC Supply voltage 2 6 2 6 2 6 V
VCC = 2 V 1.5 1.5 1.5
V
IH
High-level input voltage VCC = 4.5 V 3.15 3.15 3.15 V
VIH
High-level input voltage
VCC = 6 V 4.2 4.2 4.2
V
VCC = 2 V 0.5 0.5 0.5
V
IL
Low-level input voltage VCC = 4.5 V 1.35 1.35 1.35 V
VIL
Low-level input voltage
VCC = 6 V 1.8 1.8 1.8
V
VIInput voltage 0 VCC 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC 0 VCC V
VCC = 2 V 1000 1000 1000
t
t
Input transition (rise and fall) time VCC = 4.5 V 500 500 500 ns
tt
Input transition (rise and fall) time
VCC = 6 V 400 400 400
ns
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
  
  
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions for CD74HCT4511 (see Note 4)
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 2 V
VIL Low-level input voltage 0.8 0.8 0.8 V
VIInput voltage VCC VCC VCC V
VOOutput voltage VCC VCC VCC V
ttInput transition (rise and fall) time 500 500 500 ns
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
’HC4511
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS
VCC
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
TEST CONDITIONS
VCC
MIN MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.9 1.9
I
OH
= −20 µA4.5 V 4.4 4.4 4.4
V
V
I
= V
IH
or V
IL
IOH = −20 µA
6 V 5.9 5.9 5.9 V
VI = VIH or VIL
IOH = −7.5 mA 4.5 V 3.98 3.7 3.84
V
IOH = −10 mA 6 V 5.48 5.2 5.34
2 V 0.1 0.1 0.1
I
OL
= 20 µA4.5 V 0.1 0.1 0.1
V
V
I
= V
IH
or V
IL
IOL = 20 µA
6 V 0.1 0.1 0.1 V
VI = VIH or VIL
IOL = 4 mA 4.5 V 0.26 0.4 0.33
V
IOL = 5.2 mA 6 V 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±1±1µA
ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA
Ci10 10 10 pF
  
  
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD74HCT4511
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN TYP MAX MIN MAX MIN MAX
UNIT
VOH
VI = VIH or VIL
IOH = −20 µA
4.5 V
4.4 4.4 4.4
V
VOH VI = VIH or VIL IOH = −4 mA 4.5 V 3.98 3.7 3.84 V
VOL
VI = VIH or VIL
IOL = 20 µA
4.5 V
0.1 0.1 0.1
V
VOL VI = VIH or VIL IOL = 4 mA 4.5 V 0.26 0.4 0.33 V
IIVI = VCC to GND 5.5 V ±0.1 ±1±1µA
ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA
∆ICC†One input at VCC − 2.1 V,
Other inputs at 0 or VCC 4.5 V to 5.5 V 100 360 490 450 µA
Ci10 10 10 pF
†Additional quiescent supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case
(VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
HCT INPUT LOADING TABLE
INPUT UNIT LOADS‡
LT, LE 1.5
BL, Dn 0.3
‡Unit load is ∆ICC limit specified in electrical
characteristics table, e.g., 360 µA maximum at
25°C.
’HC4511 timing requirements over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
VCC
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
VCC
MIN MAX MIN MAX MIN MAX
UNIT
2 V 80 120 100
t
w
Pulse duration, LE low 4.5 V 16 24 20 ns
tw
Pulse duration, LE low
6 V 14 20 17
ns
2 V 60 90 75
t
su
Setup time, BCD inputs before LE↑4.5 V 12 18 15 ns
tsu
Setup time, BCD inputs before LE↑
6 V 10 15 13
ns
2 V 3 3 3
t
h
Hold time, BCD inputs before LE↑4.5 V 3 3 3 ns
th
Hold time, BCD inputs before LE↑
6 V 3 3 3
ns
  
  
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
’HC4511
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
VCC
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
VCC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 300 450 375
Dn
Output
C
L
= 50 pF 4.5 V 60 90 75
DnOutput
CL = 50 pF
6 V 51 77 64
CL = 15 pF 5 V 25
2 V 270 405 340
LE
Output
C
L
= 50 pF 4.5 V 54 81 68
LE Output
CL = 50 pF
6 V 46 69 58
tpd
CL = 15 pF 5 V 23
ns
tpd 2 V 220 330 275 ns
BL
Output
C
L
= 50 pF 4.5 V 44 66 55
BL Output
CL = 50 pF
6 V 37 56 47
CL = 15 pF 5 V 18
2 V 160 240 200
LT
Output
C
L
= 50 pF 4.5 V 32 48 40
LT Output
CL = 50 pF
6 V 27 41 34
CL = 15 pF 5 V 13
2 V 75 110 95
t
t
Any C
L
= 50 pF 4.5 V 15 22 19 ns
tt
Any
CL = 50 pF
6 V 13 19 16
ns
  
  
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD74HCT4511
timing requirements over recommended operating free-air temperature range VCC = 4.5 V (unless
otherwise noted) (see Figure 2)
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
twPulse duration, LE low 16 24 20 ns
tsu Setup time, BCD inputs before LE↑16 24 20 ns
thHold time, BCD inputs before LE↑5 5 5 ns
CD74HCT4511
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
VCC
TA = 25°CTA = −55°C
TO 125°CTA = −40°C
TO 85°C
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
VCC
MIN TYP MAX MIN MAX MIN MAX
UNIT
Dn
Output
CL = 50 pF 4.5 V 60 90 75
DnOutput CL = 15 pF 5 V 25
LE
Output
CL = 50 pF 4.5 V 54 81 68
tpd
LE Output CL = 15 pF 5 V 23
ns
tpd
BL
Output
CL = 50 pF 4.5 V 44 66 55 ns
BL Output CL = 15 pF 5 V 18
LT
Output
CL = 50 pF 4.5 V 33 50 41
LT Output CL = 15 pF 5 V 13
ttAny CL = 50 pF 4.5 V 15 22 19 ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TYP UNIT
Cpd†
Power dissipation capacitance
’HC4511 114
pF
C
pd
†
Power dissipation capacitance CD74HCT4511 110 pF
†Cpd is used to determine the dynamic power consumption, per package.
PD = Cpd VCC2 fi + ∑CL VCC2 fo
where: fi = input frequency
fo = output frequency
CL = output load capacitance
VCC = supply voltage
  
  
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION − ’HC4511
Test
Point
From Output
Under TestCL
(see Note A)
VCC
S1
S2
LOAD CIRCUIT
PARAMETER
tPZH
tpd or tt
tdis
ten tPZL
tPHZ
tPLZ
Open Closed
S1
Closed Open
S2
Open Closed
Closed Open
Open Open
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
RL = 1 kΩ
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
th
tsu
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50% VCC
tPLH tPHL
50% VCC 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input 50% VCC
50% VCC
VCC
Output
Control
Output
Waveform 1
(see Note B)
Output
Waveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VC
C
0 V
50% VCC 10%
50% VCC ≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
50% VCC 50% VCC
90%
VCC
VOLTAGE WAVEFORMS
RECOVERY TIME
50% VCC VCC
0 V
CLR
Input
CLK 50% VCC VCC
trec
0 V
Figure 1. Load Circuit and Voltage Waveforms
  
  
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION − CD74HCT4511
Test
Point
From Output
Under Test
CL
(see Note A)
V
CC
S1
S2
LOAD CIRCUIT
PARAMETER
tPZH
tpd or tt
tdis
ten tPZL
tPHZ
tPLZ
Open Closed
S1
Closed Open
S2
Open Closed
Closed Open
Open Open
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. t
PLH
and t
PHL
are the same as t
pd
.
RL = 1 kΩ
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
th
tsu
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
50% VCC
50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50% VCC
tPLH tPHL
50% VCC 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input 50% VCC
50% VCC
VCC
Output
Control
Output
Waveform 1
(see Note B)
Output
Waveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VC
C
0 V
50% VCC 10%
50% VCC ≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
50% VCC 50% VCC
90%
VCC
VOLTAGE WAVEFORMS
RECOVERY TIME
50% VCC VCC
0 V
CLR
Input
CLK 50% VCC VCC
trec
0 V
Figure 2. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8773301EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8773301EA
CD54HC4511F3A
CD54HC4511F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8773301EA
CD54HC4511F3A
CD74HC4511E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4511E
CD74HC4511EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4511E
CD74HC4511M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4511M
CD74HC4511M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4511M
CD74HC4511M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4511M
CD74HC4511M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4511M
CD74HC4511ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4511M
CD74HC4511MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4511M
CD74HC4511MT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4511M
CD74HC4511MTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4511M
CD74HC4511MTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4511M
CD74HC4511PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4511
CD74HC4511PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4511
CD74HC4511PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4511
CD74HC4511PWT ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4511
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD74HC4511PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4511
CD74HC4511PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4511
CD74HCT4511E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4511E
CD74HCT4511EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4511E
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC4511, CD74HC4511 :
•Catalog: CD74HC4511
•Military: CD54HC4511
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC4511M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4511PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4511PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC4511M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HC4511PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC4511PWT TSSOP PW 16 250 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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