Z8038018FSC - Zilog - Datasheet.Live

DC-8297-03

PREFACE

Thank you for your interest in the Z380

™

Central Processing Unit (CPU) and its

associated family of products. This Technical Manual describes programming

and operation of the Z380

™

Superintegration

™

Core CPU, which is found in the

Z380 Microprocessor Unit (MPU), and products built around Z380

™

CPU core.

This Z380 User's Manual consists of the following Sections:

1. Z380™ Architectural Overview

Chapter 1 is an introductory section covering the key features and

giving an overview of the architecture of the device.

2. Address Spaces

Chapter 2 explains the address spaces the Z380 CPU can handle.

Also, this chapter includes a brief description of the on-chip regis-

ters.

3. Native/Extended Mode, Word/Long Word Mode of Operation,

and Decoder Directives

This chapter provides a detailed explanation on the Z380’s unique

features, operation modes, and the Decoder Directives.

4. Addressing Modes and Data Types

Chapter 4 describes the Addressing mode and data types which the

Z380 can handle.

5. Instruction Set

Chapter 5 contains an overview of the instruction set; as well as a

detailed instruction-by-instruction description in alphabetical order.

6. Interrupts and Traps

Chapter 6 explains the interrupts and traps features of the Z380.

7. Reset

Chapter 7 describes the Reset function.

8. Z380 Benchmark Appnote

9. Z380 Questions & Answers

Z80380 CPU

USER'S MANUAL

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Appendix A

Appendix A covers the Z380’s instruction format.

Appendix B

Appendix B contains all Z380 instructions sorted in Alphabetical

Order.

Appendix C

Appendix C contains all Z380 instructions sorted in Numerical

Order.

Appendix D

The Tables in Appendix D lists all the Z380 instructions in instruction

affected by Native/Extended mode and Word/Long Word mode.

Appendix E

The Tables in Appendix E lists all the Z380 instructions in instruction

affected by DDIR IM (Immediate Decoder Directives) mode.

Index

A to Z listing of Z380™ User's Manual key words and phrases.

This manual assumes the reader has a basic knowledge of CPU-

based system architectures and software development systems,

such as the use of the text editor, and invoking the assembler/

compiler. Also, knowledge of the Z80

CPU architecture is desirable.

Zilog’s products are not authorized for use as critical compo-

nents in life support devices or systems unless a specific written

agreement pertaining to such intended use is executed between

the customer and Zilog prior to use. Life support devices or

systems are those which are intended for surgical implantation

into the body, or which sustains life whose failure to perform,

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result in

significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave.

Campbell, CA 95008-6600

Telephone (408) 370-8000

Telex 910-338-7621

FAX 408 370-8056

Internet: http://www.zilog.com

part of this document may be copied or reproduced in any form

or by any means without the prior written consent of Zilog, Inc.

The information in this document is subject to change without

notice. Devices sold by Zilog, Inc. are covered by warranty and

patent indemnification provisions appearing in Zilog, Inc. Terms

and Conditions of Sale only.

ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY,

IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMA-

TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF

THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY

INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MER-

CHANTABILITY OR FITNESS FOR ANY PURPOSE.

Zilog, Inc. shall not be responsible for any errors that may appear

in this document. Zilog, Inc. makes no commitment to update or

keep current the information contained in this document.

SER

ANUAL

ILOG

1.1 INTRODUCTION

USER’s MANUAL

CHAPTER 1

Z380™ ARCHITECTURAL OVERVIEW

The Z380 CPU incorporates advanced architectural fea-

tures that allow fast and efficient throughput and increased

memory addressing capabilities while maintaining Z80®

CPU and Z180® MPU object-code compatibility. The Z380

CPU core provides a continuing growth path for present

Z80- or Z180®-based designs and offers the following key

features:

■Full Static CMOS Design with Low Power Standby

Mode Support

■DC to 18 MHz Operating Frequency @ 5 Volts VCC

■DC to 10 MHz Operating Frequency @ 33 Volts VCC

■Enhanced Instruction Set that Maintains Object-Code

Compatibility with Z80 and Z180 Microprocessors

■16-Bit (64K) or 32-Bit (4G) Linear Address Space

■16-Bit Internal Data Bus

■Two Clock Cycle Instruction Execution (Minimum)

■Multiple On-Chip Register Files (Z380 MPU has Four

Banks)

■BC/DE/HL/IX/IY Registers are Augmented by 16-Bit

Extended Registers (BCz/DEz/HLz/IXz/IYz), PC/SP/I

Registers are Augmented by Extended Registers (PCz/

SPz/Iz) for 32-Bit Addressing Capability.

■Newly Added IX’ and IY’ Registers with Extended

Registers (IXz’/IYz’)

■Enhanced Interrupt Capabilities, Including 16-Bit

Vector

■Undefined Opcode Trap for Full Z380 CPU Instruction

Set

The Z380 CPU, an enhanced version of the Z80 CPU,

retains the Z80 CPU instruction set to maintain complete

binary-code compatiblity with present Z80 and Z180 codes.

The basic addressing modes of the Z80 microprocessor

have been augmented with Stack Pointer Relative loads

and stores, 16-bit and 24-bit Indexed offsets, and in-

creased Indirect register addressing flexibility, with all of

the addressing modes allowing access to the entire 32-bit

address space. Significant additions have been made to

the instruction set iincorporating16-bit arithmetic and logi-

cal operations, 16-bit I/O operations, multiply and divide,

a complete set of register-to-register loads and exchanges,

plus 32-bit load and exchange, and 32-bit arithmetic

operation for address calculation.

The basic register file of the Z80 microprocessor is ex-

panded to include alternate register versions of the IX and

IY registers. There are four sets of this basic Z80 micropro-

cessor register file present in the Z380 MPU, along with the

necessary resources to manage switching between the

different register sets. All of the register pairs and index

registers in the basic Z80 microprocessor register file are

expanded to 32 bits.

The Z380 CPU expands the basic 64 Kbyte Z80 and Z180

address space to a full 4 Gbyte (32-bit) address space.

This address space is linear and completely accessible to

the user program. The external I/O address space is

similarly expanded to a full 4 Gbyte (32-bit) range, and 16-

bit I/O, both simple and block move are included. A 256

byte-wide internal I/O space has been added. This space

will be used to access on-chip I/O resources on future

Superintegration implementation of this CPU core.

Figure 1-1 provides a detailed description of the basic

architecture allows future expansion of up to 128 sets of

each.

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1.1 INTRODUCTION (Continued)

IXU IXL

IYU IYL

A' F'

B' C'

D' E'

H' L'

IXU' IXL'

IYU' IYL'

BCz'

DEz'

HLz'

IXz'

IYz'

BCz

DEz

HLz

IXz

IYz

SPz

PCz

4 Sets of Registers

Figure 1-1. Z380™ CPU Register Architecture

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1.2 CPU ARCHITECTURE

The Z380 CPU is a binary-compatible extension of the Z80

CPU and the Z180 CPU architecture. High throughput

rates are achieved by a high clock rate, high bus band-

width, and instruction fetch/execute overlap. Communi-

cating to the external world through an 8-bit or 16-bit data

bus, the Z380 CPU is a full 32-bit machine internally, with

a 32-bit ALU and 32-bit registers.

1.2.1 Modes of Operation

To maintain compatibility with the Z80/Z180 CPU while

having the capability to manipulate 4 Gbytes of memory

address range, the Z380 CPU has two bits in the Select

controls the address manipulation mode: Native mode or

Extended mode; and the other bit controls the data ma-

nipulation mode: Word mode or Long Word mode. In

result, the Z380 CPU has four modes of operation. On

reset, the Z380 CPU is in Native/Word mode, which is

compatible to the Z80/Z180’s operation mode. For details

on this subject, refer to Chapter 3, “Native/Extended Mode,

Word/Long Word Mode of Operation, and Decoder Direc-

tive Instructions.”

1.2.1.1 Native Mode and Extended Mode

The Z380 CPU can operate in either Native or Extended

mode, as controlled by a bit in the Select Register (SR). In

Native mode (the Reset configuration), all address ma-

nipulations are performed modulo 65536 (216). In this

mode, the Program Counter (PC) only increments across

16 bits, all address manipulation instructions (increment,

decrement, add, subtract, indexed, stack relative, and PC

relative) only operate on 16 bits, and the Stack Pointer (SP)

only increments and decrements across 16 bits. The PC

high-order word is left at all zeros, as the high-order words

of the SP and the I register. Thus, Native mode is fully

compatible with the Z80 CPU’s 64 Kbyte address mode. It

is still possible to address memory outside of 64 Kbyte

address space for data storage and retrieval in Native

mode, however, since direct addresses, indirect addresses,

and the high-order word of the SP, I, and the IX and IY

registers may be loaded with non-zero values. Executed

code and interrupt service routines must reside in the

lowest 64 Kbytes of the address space.

In Extended mode, however, all address manipulation

instructions operate on 32 bits, allowing access to the

entire 4 Gbyte address space of the Z380 CPU. In both

Native and Extended modes, the Z380 drives all 32 bits of

the address onto the external address bus; only the width

of the manipulated addresses distinguishes Native from

Extended mode. The Z380 CPU implements one instruc-

tion to allow switching from Native to Extended mode

(SETC XM); however, once in Extended mode, only Reset

will return the Z380 CPU to Native mode. This restriction

applies because of the possibility of “misplacing” interrupt

service routines or vector tables during the transition from

Extended mode back to Native mode.

1.2.1.2 Word or Long Word Mode

In addition to Native and Extended mode, which are

specific to memory space addressing, the Z380 CPU can

operate in either Word or Long Word mode specific to data

load and exchange operations. In Word mode (the Reset

configuration), all word load and exchange operations

manipulate 16-bit quantities. For example, only the low-

order words of the source and destination are exchanged

in an exchange operation, with the high-order words

unaffected.

In the Long Word mode, all 32 bits of the source and

destination are exchanged. The Z380 CPU implements

two instructions plus decoder directives to allow switching

between Word and Long Word mode; SETC LW (Set

Control Long Word) and RESC LW (Reset Control Long

Word) perform a global switch, while DDIR W, DDIR LW

and their variants are decoder directives that select a

particular mode only for the instruction that they precede.

Note that all word data arithmetic (as opposed to address

manipulation arithmetic), rotate, shift, and logical opera-

tions are always in 16-bit quantities. They are not con-

trolled by either the Native/Extended or Word/Long Word

selections. The exceptions to the 16-bit quantities are, of

course, those multiply and divide operations with 32-bit

products or dividends.

All word Input/Output operations are performed on 16-bit

values, regardless of Word/Long Word operation.

1.2.2 Address Spaces

Addressing spaces in the Z380 CPU include the CPU

on-chip I/O address, and the external I/O address. The

CPU register space is a superset of the Z80 CPU register

set, and consists of all of the registers in the CPU register

file. These CPU registers are used for data and address

manipulation, and are an extension of the Z80 CPU register

set, with four sets of this extended Z80 CPU register set

present in the Z380 CPU. Access to these registers is

specified in the instruction, with the active register set

selected by bits in the Select Register (SR) in the CPU

control register space.

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1.2.2 Address Spaces (Continued)

Each register set includes the primary registers A, F, B, C,

D, E, H, L, IX, and IY, as well as the alternate registers A’,

F’, B’, C’, D’, E’, H’, L’, IX’, and IY’. Also, IX, IX’, IY, and IY’

registers are accessible as two byte registers, each named

as IXU, IXL, IXU’ IXL’, IYU, IYL, IYU’, and IYL’. These byte

registers can be paired B with C, D with E, H with L, B’ with

C’, D’ with E’, and H’ with L’ to form word registers, and

these word registers are extended to 32 bits with the “z”

extension to the register. This register extension is only

accessible when using the register as a 32-bit register (in

the Long Word mode) or when swapping between the

most-significant and least-significant word of a 32-bit

refers to a word register, the implicit size is controlled by

Word or Long Word mode. Also included are the R, I, and

SP registers, as well as the PC.

The Select Register (SR) determines the operation of the

Z380 CPU. The contents of this register determine the CPU

operating mode, which register bank will be used, the

interrupt mode in effect, and so on.

The Z380 CPU’s memory address space is linear 4 Gbytes.

To keep compatibility with the Z80 CPU memory address-

ing model, it has two control bits to change its operation

modes—Native or Extended, Word or Long Word.

The Z380 CPU architecture also distinguishes between

the memory and I/O addressing space and, therefore,

requires specific I/O instructions. Furthermore, I/O ad-

dressing space is subdivided into the on-chip I/O address

space and the external I/O addressing space. External

I/O addressing space in the Z380 CPU is 32 bits long, and

internal I/O addressing space is 8-bits long. There are

separate sets of I/O instructions for each I/O addressing

space.

Some of the Internal I/O registers are used to control the

functionality of the device, such as to program/read status

of Trap, Assigned Vector Base address, enabling of inter-

rupts, and to get Chip version ID.

For details on this topic, refer to Chapter 2, “Address

Spaces.”

1.2.3 Data Types

Many data types are supported by the Z380 CPU architec-

ture. The basic data type is the 8-bit byte, which is also the

basic addressable memory element. The architecture also

supports operations on bits, BCD (Binary Coded Decimal)

digits, words (16 bits or 32 bits), byte strings and word

strings. For details on this topic, refer to Section 4.3, “Data

Types.”

1.2.4. Addressing Modes

Addressing modes are used by the Z380 CPU to calculate

the effective address of an operand needed for execution

of an instruction. Seven addressing modes are supported

by the Z380 CPU. Of these seven, one is an addition to the

Z80 CPU addressing modes (Stack Pointer Relative) and

the remaining six modes are either existing or extensions

to Z80 CPU addressing modes.

■Register

■Immediate

■Indirect Register

■Direct Address

■Indexed

■Program Counter Relative

■Stack Pointer Relative

All addressing modes are available on the 8-bit load,

arithmetic, and logical instructions; the 8-bit shift, rotate,

and bit manipulation instructions are limited to the regis-

ters and Indirect register addressing modes. The 16-bit

loads on the addressing registers support all addressing

modes except Index, while other 16-bit operations are

limited to the Register, Immediate, Indirect Register, In-

dex, Direct Address, and PC Relative addressing modes.

For details on this subject, refer to Chapter 4, “Addressing

Modes and Data Types.”

1.2.5. Instruction Set

The Z380 CPU instruction set is an expansion of the Z80

instruction set; the enhancements include support for

additional addressing modes for the Z80 instructions as

well as the addition of new instructions. The Z380 CPU

instruction set provides a full complement of 8-bit, 16-bit,

and 32-bit operation, including multiplication and division.

For details on this subject, refer to Chapter 5, “Instruction

Set.”

1.2.6 Exception Conditions

The Z380 CPU supports three types of exceptions (condi-

tions that alter the normal flow of program execution);

interrupts, traps, and resets.

Interrupts are asynchronous events typically triggered by

peripherals requiring attention. The Z380 CPU interrupt

structure has been significantly enhanced by increasing

the number of interrupt request lines and by adding an

efficient means for handling nested interrupts. The Z380

CPU has five interrupt lines. These are: Nonmaskable

Interrupt line (/NMI) and Maskable interrupt lines (/INT0,

/INT1, /INT2, and /INT3). Interrupt requests on /INT3-/INT1

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are handled by a newly added interrupt handing mode,

“Assigned Vectored Mode,” which is a fixed vectored

interrupt mode similar in interrupt handling to the Z180’s

interrupts from on-chip peripherals. For handling interrupt

requests on the /INT0 line, there are four modes available:

■8080 compatible (Mode 0), in which the interrupting

device provides the first instruction of the interrupt

routine.

■Dedicated interrupts (Mode 1), in which the CPU

jumps to a dedicated address when an interrupt

occurs.

■Vectored interrupt mode (Mode 2), in which the

interrupting peripheral device provides a vector into a

table of jump address.

■Enhanced vectored interrupt mode (Mode 3), wherein

the CPU expects 16-bit vector, instead of 8-bit interrupt

vectors in Mode 2.

The first three modes are compatible with Z80 interrupt

modes; the fourth mode provides more flexibility.

Traps are synchronous events that trigger a special CPU

response when an undefined instruction is executed. It

can be used to increase system reliability, or used as a

“software trap instruction.”

Hardware resets occur when the /RESET line is activated

and override all other conditions. A /RESET causes certain

CPU control registers to be initialized.

For details on this subject, refer to Chapter 6, “Interrupts

and Traps.”

1.3 BENEFITS OF THE ARCHITECTURE

The Z380 CPU architecture provides several significant

benefits, including increased program throughput achieved

by higher bus bandwidth (16-bit wide bus), reduction to

two clocks/basic machine cycle (vs four clocks/cycle on

the Z80 CPU), prefetch cue, access to the larger linear

addressing space, enhanced instructions/new address-

ing mode, data/address manipulation in 16/32 bits, and

faster context switching by utilizing multiple register banks.

1.3.1 High Throughput

Very high throughput rates can be achieved with the Z380

CPU, due to the basic machine cycle’s reduction to two

clocks/cycle from four clocks/cycle on the Z80 CPU, fine

tuned four staged pipeline with prefetch cue. This well

designed pipeline and prefetch cue are both totally trans-

parent to the user, thus maximizing the efficiency of the

pipeline all the time. The Z380 CPU implemented onto the

Z380 MPU is configured with a 16-bit wide data bus, which

doubles the bus bandwidth. These architectural features

result in two clocks/instructions execution minimum, three

clocks/instruction on average. The high clock rates (up to

40 MHz) achievable with this processor. Make the overall

performance of the Z380 CPU more than ten times that of

the Z80.

1.3.2 Linear Memory Address Space

Z380 CPU architecture has 4 Gbytes of linear memory

address space. The Z80 CPU architecture allows 64

Kbytes of memory addressing space. This was more than

sufficient when the Z80 CPU was first developed. But as

the technology improved over time, applications started to

demand more complicated processing, multitasking, faster

processing, etc., with the high level language needed to

develop software. As a result, 64 Kbytes of memory ad-

dressing space is not enough for some Z80 CPU based

applications. In order to handle more than 64 Kbytes of

memory, the Z80 CPU requires a Memory Banking scheme,

or MMU (Memory Management Unit), like the Z180 MPU or

Z280 MPU. These provide the overhead to access more

than 64 Kbytes of memory.

The Z380 CPU architecture allows access to a full 4 Gbytes

(232) of memory addressing space as well as 4 Gbytes of

I/O addressing area, without using a Memory Banking

scheme, or MMU.

1.3.3. Enhanced Instruction Set with 16-Bit

and 32-Bit Manipulation Capability

The Z380 CPU instruction set is 100% upward compatible

to the Z80 CPU instruction set; that is all the Z80 instruc-

tions have been preserved at the binary level. New instruc-

tions added to the Z380 CPU include:

■Less restricted operand source/destination

combinations.

■More flexible register exchange instructions.

■Stack Pointer Relative addressing mode.

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1.3.3. Enhanced Instruction Set with 16-Bit

and 32-Bit Manipulation Capability

(Continued)

■DDIR (Decoder Directive Instructions) to enhance

addressing capability to cover 4 Gbytes of memory

space, as well as data manipulation capability.

■Jump relative/Call relative instructions with 8-bit,

16-bit, or 24-bit displacement.

■Full complements of 16-bit arithmetic instructions.

■32-bit manipulate instructions for address manipulation.

These new instructions help to compact the code, as well

as shorten the program’s overall execution speed.

For details on this subject, refer to Chapter 5, “Instruction

Set.”

1.3.4 Faster Context Switching

The Z380 CPU architecture allows multiple sets of register

banks for AF/AF’, BC/DE/HL, BC’/DE’/HL’, IX/IX’, IY/IY’

When doing context switching, by exceptional condition

(trap or interrupts) or by subroutine/procedure calls, the

CPU has to save the contents of the registers currently in

use, along with the current CPU status.

Traditionally in the Z80 CPU architecture, this is done by

saving the contents of the register into memory, usually

using push/pop instructions or the auxiliary register file.

finished.

With the Z380 CPU’s multiple register banks, saving the

contents of the working register set currently in use is just

a matter of an instruction to change the field in the Select

1.4 SUMMARY

The Z380 CPU is a high-performance 16-bit Central Pro-

cessing Unit Superintegration™ core. Code-compatible

with the Z80 CPU, the Z380 CPU architecture has been

expanded to include features such as multiple register

banks, 4 Gbytes of linear memory addressing space, and

efficient handling of nested interrupts. The benefits of this

architecture, including high throughput rates, code den-

sity, and compiler efficiency, greatly enhance the power

and versatility of the Z380 CPU. Thus, the Z380 CPU

provides both a growth path for existing Z80-based de-

signs and a powerful processor for applications and the

products to be developed around this CPU core.

Zilog’s products are not authorized for use as critical compo-

nents in life support devices or systems unless a specific written

agreement pertaining to such intended use is executed between

the customer and Zilog prior to use. Life support devices or

systems are those which are intended for surgical implantation

into the body, or which sustains life whose failure to perform,

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result in

significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave.

Campbell, CA 95008-6600

Telephone (408) 370-8000

Telex 910-338-7621

FAX 408 370-8056

Internet: http://www.zilog.com

part of this document may be copied or reproduced in any form

or by any means without the prior written consent of Zilog, Inc.

The information in this document is subject to change without

notice. Devices sold by Zilog, Inc. are covered by warranty and

patent indemnification provisions appearing in Zilog, Inc. Terms

and Conditions of Sale only.

ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY,

IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMA-

TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF

THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY

INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MER-

CHANTABILITY OR FITNESS FOR ANY PURPOSE.

Zilog, Inc. shall not be responsible for any errors that may appear

in this document. Zilog, Inc. makes no commitment to update or

keep current the information contained in this document.

2-1

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2.1 INTRODUCTION

SER

’s M

ANUAL

CHAPTER 2

ADDRESS SPACES

The Z380 CPU supports five address spaces correspond-

ing to the different types of locations that can be ad-

dressed and the method by which the logical addresses

are formed. These five address spaces are:

■CPU Register Space. This consists of all the register

addresses in the CPU register file.

■CPU Control Register Space. This consists of the

Select Register (SR).

■Memory Address Space. This consists of the

addresses of all locations in the main memory.

2.2 CPU REGISTER SPACE

The Z380 register file is illustrated in Figure 2-1. Note that

this figure shows the configuration of the register on the

Z380 CPU, and the number of the register files may vary on

future Superintegration devices. The Z380 CPU contains

abundant register resources. At any given time, the pro-

gram has immediate access to both primary and alternate

registers in the selected register set. Changing register

sets is a simple matter of an LDCTL instruction to program

the Select Register (SR).

The CPU register file is divided into five groups of registers

(an apostrophe indicates a register in the auxiliary regis-

ters).

■Four sets of Flag and Accumulator registers (F, A, F’,

A’)

■Four sets of Primary and Working registers (B, C, D, E,

H, L, B’, C’, D’, E’, H’, L’)

■External I/O Address Space. This consists of all

external I/O ports addresses through which peripheral

devices are accessed.

■On-Chip I/O Address Space. This consists of all

internal I/O port addresses through which peripheral

devices are accessed. Also, this addressing space

contains registers to control the functionality of the

device, giving status information.

■Four sets of Index registers (IX, IY, IX’, IY’)

■Stack Pointer (SP)

■Program Counter, Interrupt register, Refresh register

(PC, I, R)

instruction or are implied by the semantics of the instruc-

tion.

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2.2 CPU REGISTER SPACE (Continued)

IXU IXL

IYU IYL

A' F'

B' C'

D' E'

H' L'

IXU' IXL'

IYU' IYL'

BCz'

DEz'

HLz'

IXz'

IYz'

BCz

DEz

HLz

IXz

IYz

SPz

PCz

4 Sets of Registers

Figure 2-1. Register File Organization (Z380 MPU)

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2.2.1 Primary and Working Registers

The working register set is divided into two register files:

the primary file and the alternate file (designated by prime

(‘)). Each file contains an 8-bit accumulator (A), a Flag

D, E, H, and L) with their Extended registers. Only one file

can be active at any given time, although data in the

inactive file can still be accessed by using EX R, R’

instructions for the byte-wide registers, EX RR, RR’ instruc-

tions for register pairs (either in 16-bit or 32-bit wide

depending on the LW status). Exchange instructions allow

the programmer to exchange the active file with the inac-

tive file. The EX AF, AF’, EXX, or EXALL instructions

changes the register files in use. Upon reset, the primary

sets is a simple matter of an LDCTL instruction to program

SR.

The accumulator is the destination register for 8-bit arith-

metic and logical operations. The six general-purpose

registers can be paired (BC, DE, and HL), and are ex-

tended to 32 bits by the extension to the register (with suffix

“z”; BCz/DEz/HLz), to form three 32-bit general-purpose

registers. The HL register serves as the 16-bit or 32-bit

accumulator for word operations. Access to the Extended

portion of the registers is possible using the SWAP instruc-

tion or word Load instructions in Long Word operation

mode.

The Flag register contains eight status flags. Four can be

individually used for control of program branching, two are

used to support decimal arithmetic, and two are reserved.

These flags are set or reset by various CPU operations. For

details on Flag operations, refer to Section 5.2, “Flag

2.2.2. Index Registers

The four index registers, IX, IX’, IY, and IY’, are extended

to 32 bits by the extension to the register (with suffix “z”;

IXz/IYz), to form 32-bit index registers. To access the

Extended portion of the registers use the SWAP instruction

or word Load instructions in Long Word operation mode.

These Index registers hold a 32-bit base address that is

used in the Index addressing mode.

Only one register of each can be active at any given time,

although data in the inactive file can still be accessed by

using EX IX, IX’ and EX IY, IY’ (either in 16-bit or 32-bit wide

depending on the LW bit status). Index registers can also

function as general-purpose registers with the upper and

lower bytes of the lower 16 bits being accessed individu-

ally. These byte registers are called IXU, IXU’, IXL, and IXL’

for the IX and IX’ registers, and IYU, IYU’, IYL, and IYL’ for

the IY and IY’ registers.

Selection of primary or auxiliary Index registers can be

made by EXXX, EXXY, or EXALL instructions, or program-

ming of SR. Upon reset, the primary registers in register set

0 is active. Changing register sets is a simple matter of an

LDCTL instruction to program SR.

2.2.3. Interrupt Register

The Interrupt register (I) is used in interrupt modes 2 and

3 for /INT0 to generate a 32-bit indirect address to an

interrupt service routine. The I register supplies the upper

24 or 16 bits of the indirect address and the interrupting

peripheral supplies the lower eight or 16 bits. In Assigned

Vectors mode for /INT3-/INT1, the upper 16 bits of the

vector are supplied by the I register; bits 15-9 are supplied

from the Assigned Vector Base register, and bits 8-0 are

the assigned vector unique to each of /INT3-/INT1.

2.2.4. Program Counter

The Program Counter (PC) is used to sequence through

instructions in the currently executing program and to

generate relative addresses. The PC contains the 32-bit

address of the current instruction being fetched from

memory. In Native mode, the PC is effectively only 16 bits

long, since the upper word [PC31-PC16] of the PC is

forced to zero, and when carried from bit 15 to bit 16 (Lower

word [PC15-PC0] to Upper word [PC31-PC16]) are inhib-

ited in this mode. In Extended mode, the PC is allowed to

increment across all 32 bits.

2.2.5. R Register

The R register can be used as a general-purpose 8-bit

read/write register. The R register is not associated with

the refresh controller and its contents are changed only by

the user.

2.2.6. Stack Pointer

The Stack Pointer (SP) is used for saving information when

an interrupt or trap occurs and for supporting subroutine

calls and returns. Stack Pointer relative addressing allows

parameter passing using the SP. The SP is 16 bits wide, but

is extended by the SPz register to 32 bits wide.

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2.2.6 Stack Pointer (Continued)

Increment/decrement of the Stack Pointer is affected by

modes of operation (Native or Extended). In Native mode,

the stack operates in modulo 216, and in Extended mode,

it operates in modulo 232. For example, SP holds 0001FFFEH,

and does the Word size Pop operation. After the operation,

SP holds 00010000H in Native mode, and 00020000H in

Extended mode. In either case, SPz can be programmed

to set Stack frame. This is done by the Load- to-Stack

pointer instructions in Long Word mode.

2.3. CPU CONTROL REGISTER SPACE

The CPU control register space consists of the 32-bit

Select Register (SR). The SR may be accessed as a whole

or the upper three bytes of the SR may be accessed

individually as YSR, XSR, and DSR. In addition, these

upper three bytes can be loaded with the same byte value.

The SR may also be PUSHed and POPed and is cleared to

zeros on Reset. For details on this register, refer to Chapter

5.3, “Select Register.”

2.4 MEMORY ADDRESS SPACE

The memory address space can be viewed as a string of

4 Gbytes numbered consecutively in ascending order.

The 8-bit byte is the basic addressable element in the Z380

MPU memory address space. However, there are other

addressable data elements: bits, 2-byte words, byte strings,

and 4-byte words.

The size of the data element being addressed depends on

the instruction being executed as well as the Word/Long

Word mode. A bit can be addressed by specifying a byte

and a bit within that byte. Bits are numbered from right to

left, with the least significant bit being 0, as illustrated in

Figure 2-2.

The address of a multiple-byte entity is the same as the

address of the byte with the lowest memory address in the

entity. Multiple-byte entities can be stored beginning with

either even or odd memory addresses. A word (either 2-

byte or 4-byte entity) is aligned if its address is even;

otherwise it is unaligned. Multiple bus transactions, which

may be required to access multiple-byte entities, can be

minimized if alignment is maintained.

The format of multiple-byte data types is also shown in

Figure 2-2. Note that when a word is stored in memory, the

least significant byte precedes the more significant byte of

the word, as in the Z80 CPU architecture. Also, the lower-

addressed byte is present on the upper byte of the external

data bus.

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Bits within a byte:

16-bit word at address n:

Least Significant Byte

Most Significant Byte

Address n

Address n+1

32-bit word at address n:

D7-0 (Least Significant Byte)

D15-8

Address n

Address n+1

Address n+2

Address n+3

D31-24 (Most Significant Byte)

D23-16

Memory addresses:

Least Significant Byte

Even address (A0=0)

Most Significant Byte

Odd address (A0=1)

1514131211109876543210

Figure 2-2. Bit/Byte Ordering Conventions

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2.5. EXTERNAL I/O ADDRESS SPACE

External I/O address space is 4 Gbytes in size and External

I/O addresses are generated by I/O instructions except

those reserved for on-chip I/O address space accesses. It

can take a variety of forms, as shown in Table 2.1. An

external I/O read or write is always one transaction, regard-

less of the bus size and the type of I/O instruction.

Table 2-1. I/O Addressing Options

Address Bus

I/O Instruction A31-A24 A23-A16 A15-A8 A7-A0

IN A, (n) 00000000 00000000 A7-A0 n

IN dst,(C) BC31-B24 BC23-B16 BC15-B8 BC7-B0

INA(W) dst,(mn) 00000000 00000000 m n

DDIR IB INA(W) dst,(lmn) 00000000 l m n

DDIR IW INA(W) dst,(klmn) k l m n

Block Input BC31-B24 BC23-B16 BC15-B8 BC7-B0

OUT (n),A 00000000 00000000 A7-A0 n

OUT (C),dst BC31-B24 BC23-B16 BC15-B8 BC7-B0

OUTA(W) (mn),dst 00000000 00000000 m n

DDIR IB OUTA(W) (lmn),dst 00000000 l m n

DDIR IW OUTA(W) (klmn),dst k l m n

Block Output BC31-B24 BC23-B16 BC15-B8 BC7-B0

2.6. ON-CHIP I/O ADDRESS SPACE

The Z380 CPU has the on-chip I/O address space to

control on-chip peripheral functions of the Superintegra-

tion™ version of the devices. A portion of its interrupt

functions are also controlled by several on-chip registers,

which occupy an on-chip I/O address space. This on-chip

I/O address space can be accessed only with the following

reserved on-chip I/O instructions which are identical to the

Z180 original I/O instructions to access Page 0 I/O ad-

dressing area.

IN0 R,(n) OTIM

IN0 (n) OTIMR

OUT0 (n),R OTDM

TSTIO n OTDMR

When one of these I/O instructions is executed, the Z380

MPU outputs the register address being accessed in a

pseudo-transaction of two BUSCLK cycles duration, with

the address signals A31-A8 at zero. In the pseudo-trans-

actions, all bus control signals are at their inactive state.

The following four registers are assigned to this address-

ing space as a part of the Z380 CPU core:

Interrupt Enable Register 17H

Assigned Vector Base Register 18H

Trap and Break Register 19H

Chip Version ID Register 0FFH

The Chip Version ID register returns one byte data, which

indicates the version of the CPU, or the specific implemen-

tation of the Z380 CPU based Superintegration device.

Currently, the value 00H is assigned to the Z380 MPU, and

other values are reserved.

For the other three registers, refer to Chapter 6, “Interrupts

and Traps.”

Also, the Z380 MPU has registers to control chip selects,

refresh, waits, and I/O clock divide to Internal I/O address

00H to 10H. For these registers, refer to the Z380 MPU

Product specification (DC-3003-01).

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DC-8297-03

Zilog’s products are not authorized for use as critical compo-

nents in life support devices or systems unless a specific written

agreement pertaining to such intended use is executed between

the customer and Zilog prior to use. Life support devices or

systems are those which are intended for surgical implantation

into the body, or which sustains life whose failure to perform,

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result in

significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave.

Campbell, CA 95008-6600

Telephone (408) 370-8000

Telex 910-338-7621

FAX 408 370-8056

Internet: http://www.zilog.com

part of this document may be copied or reproduced in any form

or by any means without the prior written consent of Zilog, Inc.

The information in this document is subject to change without

notice. Devices sold by Zilog, Inc. are covered by warranty and

patent indemnification provisions appearing in Zilog, Inc. Terms

and Conditions of Sale only.

ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY,

IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMA-

TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF

THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY

INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MER-

CHANTABILITY OR FITNESS FOR ANY PURPOSE.

Zilog, Inc. shall not be responsible for any errors that may appear

in this document. Zilog, Inc. makes no commitment to update or

keep current the information contained in this document.

2-1

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2.1 INTRODUCTION

SER

’s M

ANUAL

CHAPTER 2

ADDRESS SPACES

The Z380 CPU supports five address spaces correspond-

ing to the different types of locations that can be ad-

dressed and the method by which the logical addresses

are formed. These five address spaces are:

■CPU Register Space. This consists of all the register

addresses in the CPU register file.

■CPU Control Register Space. This consists of the

Select Register (SR).

■Memory Address Space. This consists of the

addresses of all locations in the main memory.

2.2 CPU REGISTER SPACE

The Z380 register file is illustrated in Figure 2-1. Note that

this figure shows the configuration of the register on the

Z380 CPU, and the number of the register files may vary on

future Superintegration devices. The Z380 CPU contains

abundant register resources. At any given time, the pro-

gram has immediate access to both primary and alternate

registers in the selected register set. Changing register

sets is a simple matter of an LDCTL instruction to program

the Select Register (SR).

The CPU register file is divided into five groups of registers

(an apostrophe indicates a register in the auxiliary regis-

ters).

■Four sets of Flag and Accumulator registers (F, A, F’,

A’)

■Four sets of Primary and Working registers (B, C, D, E,

H, L, B’, C’, D’, E’, H’, L’)

■External I/O Address Space. This consists of all

external I/O ports addresses through which peripheral

devices are accessed.

■On-Chip I/O Address Space. This consists of all

internal I/O port addresses through which peripheral

devices are accessed. Also, this addressing space

contains registers to control the functionality of the

device, giving status information.

■Four sets of Index registers (IX, IY, IX’, IY’)

■Stack Pointer (SP)

■Program Counter, Interrupt register, Refresh register

(PC, I, R)

instruction or are implied by the semantics of the instruc-

tion.

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2.2 CPU REGISTER SPACE (Continued)

IXU IXL

IYU IYL

A' F'

B' C'

D' E'

H' L'

IXU' IXL'

IYU' IYL'

BCz'

DEz'

HLz'

IXz'

IYz'

BCz

DEz

HLz

IXz

IYz

SPz

PCz

4 Sets of Registers

Figure 2-1. Register File Organization (Z380 MPU)

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2.2.1 Primary and Working Registers

The working register set is divided into two register files:

the primary file and the alternate file (designated by prime

(‘)). Each file contains an 8-bit accumulator (A), a Flag

D, E, H, and L) with their Extended registers. Only one file

can be active at any given time, although data in the

inactive file can still be accessed by using EX R, R’

instructions for the byte-wide registers, EX RR, RR’ instruc-

tions for register pairs (either in 16-bit or 32-bit wide

depending on the LW status). Exchange instructions allow

the programmer to exchange the active file with the inac-

tive file. The EX AF, AF’, EXX, or EXALL instructions

changes the register files in use. Upon reset, the primary

sets is a simple matter of an LDCTL instruction to program

SR.

The accumulator is the destination register for 8-bit arith-

metic and logical operations. The six general-purpose

registers can be paired (BC, DE, and HL), and are ex-

tended to 32 bits by the extension to the register (with suffix

“z”; BCz/DEz/HLz), to form three 32-bit general-purpose

registers. The HL register serves as the 16-bit or 32-bit

accumulator for word operations. Access to the Extended

portion of the registers is possible using the SWAP instruc-

tion or word Load instructions in Long Word operation

mode.

The Flag register contains eight status flags. Four can be

individually used for control of program branching, two are

used to support decimal arithmetic, and two are reserved.

These flags are set or reset by various CPU operations. For

details on Flag operations, refer to Section 5.2, “Flag

2.2.2. Index Registers

The four index registers, IX, IX’, IY, and IY’, are extended

to 32 bits by the extension to the register (with suffix “z”;

IXz/IYz), to form 32-bit index registers. To access the

Extended portion of the registers use the SWAP instruction

or word Load instructions in Long Word operation mode.

These Index registers hold a 32-bit base address that is

used in the Index addressing mode.

Only one register of each can be active at any given time,

although data in the inactive file can still be accessed by

using EX IX, IX’ and EX IY, IY’ (either in 16-bit or 32-bit wide

depending on the LW bit status). Index registers can also

function as general-purpose registers with the upper and

lower bytes of the lower 16 bits being accessed individu-

ally. These byte registers are called IXU, IXU’, IXL, and IXL’

for the IX and IX’ registers, and IYU, IYU’, IYL, and IYL’ for

the IY and IY’ registers.

Selection of primary or auxiliary Index registers can be

made by EXXX, EXXY, or EXALL instructions, or program-

ming of SR. Upon reset, the primary registers in register set

0 is active. Changing register sets is a simple matter of an

LDCTL instruction to program SR.

2.2.3. Interrupt Register

The Interrupt register (I) is used in interrupt modes 2 and

3 for /INT0 to generate a 32-bit indirect address to an

interrupt service routine. The I register supplies the upper

24 or 16 bits of the indirect address and the interrupting

peripheral supplies the lower eight or 16 bits. In Assigned

Vectors mode for /INT3-/INT1, the upper 16 bits of the

vector are supplied by the I register; bits 15-9 are supplied

from the Assigned Vector Base register, and bits 8-0 are

the assigned vector unique to each of /INT3-/INT1.

2.2.4. Program Counter

The Program Counter (PC) is used to sequence through

instructions in the currently executing program and to

generate relative addresses. The PC contains the 32-bit

address of the current instruction being fetched from

memory. In Native mode, the PC is effectively only 16 bits

long, since the upper word [PC31-PC16] of the PC is

forced to zero, and when carried from bit 15 to bit 16 (Lower

word [PC15-PC0] to Upper word [PC31-PC16]) are inhib-

ited in this mode. In Extended mode, the PC is allowed to

increment across all 32 bits.

2.2.5. R Register

The R register can be used as a general-purpose 8-bit

read/write register. The R register is not associated with

the refresh controller and its contents are changed only by

the user.

2.2.6. Stack Pointer

The Stack Pointer (SP) is used for saving information when

an interrupt or trap occurs and for supporting subroutine

calls and returns. Stack Pointer relative addressing allows

parameter passing using the SP. The SP is 16 bits wide, but

is extended by the SPz register to 32 bits wide.

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2.2.6 Stack Pointer (Continued)

Increment/decrement of the Stack Pointer is affected by

modes of operation (Native or Extended). In Native mode,

the stack operates in modulo 216, and in Extended mode,

it operates in modulo 232. For example, SP holds 0001FFFEH,

and does the Word size Pop operation. After the operation,

SP holds 00010000H in Native mode, and 00020000H in

Extended mode. In either case, SPz can be programmed

to set Stack frame. This is done by the Load- to-Stack

pointer instructions in Long Word mode.

2.3. CPU CONTROL REGISTER SPACE

The CPU control register space consists of the 32-bit

Select Register (SR). The SR may be accessed as a whole

or the upper three bytes of the SR may be accessed

individually as YSR, XSR, and DSR. In addition, these

upper three bytes can be loaded with the same byte value.

The SR may also be PUSHed and POPed and is cleared to

zeros on Reset. For details on this register, refer to Chapter

5.3, “Select Register.”

2.4 MEMORY ADDRESS SPACE

The memory address space can be viewed as a string of

4 Gbytes numbered consecutively in ascending order.

The 8-bit byte is the basic addressable element in the Z380

MPU memory address space. However, there are other

addressable data elements: bits, 2-byte words, byte strings,

and 4-byte words.

The size of the data element being addressed depends on

the instruction being executed as well as the Word/Long

Word mode. A bit can be addressed by specifying a byte

and a bit within that byte. Bits are numbered from right to

left, with the least significant bit being 0, as illustrated in

Figure 2-2.

The address of a multiple-byte entity is the same as the

address of the byte with the lowest memory address in the

entity. Multiple-byte entities can be stored beginning with

either even or odd memory addresses. A word (either 2-

byte or 4-byte entity) is aligned if its address is even;

otherwise it is unaligned. Multiple bus transactions, which

may be required to access multiple-byte entities, can be

minimized if alignment is maintained.

The format of multiple-byte data types is also shown in

Figure 2-2. Note that when a word is stored in memory, the

least significant byte precedes the more significant byte of

the word, as in the Z80 CPU architecture. Also, the lower-

addressed byte is present on the upper byte of the external

data bus.

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Bits within a byte:

16-bit word at address n:

Least Significant Byte

Most Significant Byte

Address n

Address n+1

32-bit word at address n:

D7-0 (Least Significant Byte)

D15-8

Address n

Address n+1

Address n+2

Address n+3

D31-24 (Most Significant Byte)

D23-16

Memory addresses:

Least Significant Byte

Even address (A0=0)

Most Significant Byte

Odd address (A0=1)

1514131211109876543210

Figure 2-2. Bit/Byte Ordering Conventions

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2.5. EXTERNAL I/O ADDRESS SPACE

External I/O address space is 4 Gbytes in size and External

I/O addresses are generated by I/O instructions except

those reserved for on-chip I/O address space accesses. It

can take a variety of forms, as shown in Table 2.1. An

external I/O read or write is always one transaction, regard-

less of the bus size and the type of I/O instruction.

Table 2-1. I/O Addressing Options

Address Bus

I/O Instruction A31-A24 A23-A16 A15-A8 A7-A0

IN A, (n) 00000000 00000000 A7-A0 n

IN dst,(C) BC31-B24 BC23-B16 BC15-B8 BC7-B0

INA(W) dst,(mn) 00000000 00000000 m n

DDIR IB INA(W) dst,(lmn) 00000000 l m n

DDIR IW INA(W) dst,(klmn) k l m n

Block Input BC31-B24 BC23-B16 BC15-B8 BC7-B0

OUT (n),A 00000000 00000000 A7-A0 n

OUT (C),dst BC31-B24 BC23-B16 BC15-B8 BC7-B0

OUTA(W) (mn),dst 00000000 00000000 m n

DDIR IB OUTA(W) (lmn),dst 00000000 l m n

DDIR IW OUTA(W) (klmn),dst k l m n

Block Output BC31-B24 BC23-B16 BC15-B8 BC7-B0

2.6. ON-CHIP I/O ADDRESS SPACE

The Z380 CPU has the on-chip I/O address space to

control on-chip peripheral functions of the Superintegra-

tion™ version of the devices. A portion of its interrupt

functions are also controlled by several on-chip registers,

which occupy an on-chip I/O address space. This on-chip

I/O address space can be accessed only with the following

reserved on-chip I/O instructions which are identical to the

Z180 original I/O instructions to access Page 0 I/O ad-

dressing area.

IN0 R,(n) OTIM

IN0 (n) OTIMR

OUT0 (n),R OTDM

TSTIO n OTDMR

When one of these I/O instructions is executed, the Z380

MPU outputs the register address being accessed in a

pseudo-transaction of two BUSCLK cycles duration, with

the address signals A31-A8 at zero. In the pseudo-trans-

actions, all bus control signals are at their inactive state.

The following four registers are assigned to this address-

ing space as a part of the Z380 CPU core:

Interrupt Enable Register 17H

Assigned Vector Base Register 18H

Trap and Break Register 19H

Chip Version ID Register 0FFH

The Chip Version ID register returns one byte data, which

indicates the version of the CPU, or the specific implemen-

tation of the Z380 CPU based Superintegration device.

Currently, the value 00H is assigned to the Z380 MPU, and

other values are reserved.

For the other three registers, refer to Chapter 6, “Interrupts

and Traps.”

Also, the Z380 MPU has registers to control chip selects,

refresh, waits, and I/O clock divide to Internal I/O address

00H to 10H. For these registers, refer to the Z380 MPU

Product specification (DC-3003-01).

2-7

Z380

™

USER'S MANUAL

ZILOG

DC-8297-03

Zilog’s products are not authorized for use as critical compo-

nents in life support devices or systems unless a specific written

agreement pertaining to such intended use is executed between

the customer and Zilog prior to use. Life support devices or

systems are those which are intended for surgical implantation

into the body, or which sustains life whose failure to perform,

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result in

significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave.

Campbell, CA 95008-6600

Telephone (408) 370-8000

Telex 910-338-7621

FAX 408 370-8056

Internet: http://www.zilog.com

part of this document may be copied or reproduced in any form

or by any means without the prior written consent of Zilog, Inc.

The information in this document is subject to change without

notice. Devices sold by Zilog, Inc. are covered by warranty and

patent indemnification provisions appearing in Zilog, Inc. Terms

and Conditions of Sale only.

ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY,

IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMA-

TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF

THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY

INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MER-

CHANTABILITY OR FITNESS FOR ANY PURPOSE.

Zilog, Inc. shall not be responsible for any errors that may appear

in this document. Zilog, Inc. makes no commitment to update or

keep current the information contained in this document.

3-1

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™

USER'S MANUAL

ZILOG

DC-8297-03

3.1 INTRODUCTION

SER

’s M

ANUAL

CHAPTER 3

NATIVE EXTENDED MODE, WORD/LONG

WORD MODE OF OPERATIONS

AND DECODER DIRECTIONS

The Z380™ CPU architecture allows access to 4 Gbytes

(232) of memory addressing space, and 4G locations of

I/O. It offers 16/32-bit manipulation capability while main-

taining object-code compatibility with the Z80 CPU. In

order to implement these capabilities and new instruction

sets, it has two modes of operation for address manipula-

tion (Native or Extended mode), two modes of operation for

data manipulation (Word or Long Word mode), and a

special set of new Decoder Directives.

On Reset, the Z380 CPU defaults in Native mode and Word

mode. In this condition, it behaves exactly the same as the

Z80 CPU, even though it has access to the entire 4 Gbytes

of memory for data access and 4G locations of I/O space,

access to the newly added registers which includes Ex-

tended registers and register banks, and the capability of

executing all the Z380 instructions.

As described below, the Z380 CPU can be switched

between Word mode and Long Word mode during opera-

tion through the SETC LW and RESC LW instructions, or

Decoder Directives. The Native and Extended modes are

a key exception— it defaults up in Native mode, and can

be set to Extended mode by the instruction. Only Reset can

return it to Native mode. Figure 3-1 illustrates the relation-

ship between these modes of operation.

For the instructions which work with the DDIR instructions, refer to Appendix D and E.

Word

Long Word

Native

Z380

Extended

Z80 Native Mode

Figure 3-1. Z380™ CPU Operation Modes

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3.2 DECODER DIRECTIVES

The Decoder Directive is not an instruction, but rather a

directive to the instruction decoder. The instruction de-

coder may be directed to fetch an additional byte or word

of immediate data or address with the instruction, as well

as tagging the instruction for execution in either Word or

Long Word mode. Since the Z80 CPU architecture’s ad-

dressing convention in the memory is “least significant

byte first, followed by more significant bytes,” it is possible

to have such instructions to direct the instruction decoder

to fetch additional byte(s) of address information or imme-

diate data to extend the instruction.

All eight combinations of the two options are supported, as

shown below. Instructions which do not support decoder

directives are assembled by the instruction decoder as if

the decoder directive were not present.

■DDIR W Word mode

■DDIR IB,W Immediate byte, Word mode

■DDIR IW,W Immediate Word, Word mode

■DDIR IB Immediate byte

■DDIR LW Long Word mode

■DDIR IB,LW Immediate byte, Long Word mode

■DDIR IW,LW Immediate Word, Long Word

mode

■DDIR IW Immediate Word

The IB decoder directive causes the decoder to fetch an

additional byte immediately after the existing immediate

data or direct address, and in front of any trailing opcode

bytes (with instructions starting with DD-CB or FD-CB, for

example).

Likewise, the IW decoder directive causes the decoder to

fetch an additional word immediately after the existing

immediate data or direct address, and in front of any

trailing opcode bytes.

Byte ordering within the instruction follows the usual con-

vention; least significant byte first, followed by more signifi-

cant bytes. More-significant immediate data or direct

address bytes not specified in the instruction are read as

all zeros by the processor.

The W decoder directive causes the instruction decoder to

tag the instruction for execution in Word mode. This is

useful while the Long Word (LW) bit in the Select Register

(SR) is set, but 16-bit data manipulation is required for this

instruction.

The LW decoder directive causes the instruction decoder

to tag the instruction for execution in Long Word mode.

This is useful while the LW bit in the SR is cleared, but 32-

bit data manipulation is required for this instruction.

3.3 NATIVE MODE AND EXTENDED MODE

The Z380 CPU can operate in either Native or Extended

mode, as a way to manipulate addresses.

In Native mode (the Reset configuration), the Program

Counter only increments across 16 bits, and all stack Push

and Pop operations manipulate 16-bit quantities (two

bytes). Thus, Native mode is fully compatible with the Z80

CPU’s 64 Kbyte address space and programming model.

The extended portion of the Program Counter (PC31-

PC15) is forced to 0 and program address location next to

0000FFFFH is 00000000H in this mode. This means in

Native mode, program have to reside within the first 64

Kbytes of the memory addressing space.

In Extended mode, however, the PC increments across all

32 bits and all stack Push and Pop operations manipulate

32-bit quantities. Thus, Extended mode allows access to

the entire 4 Gbyte address space. In both Native and

Extended modes, the Z380 CPU drives all 32 bits of the

address onto the external address bus; only the PC incre-

ments and stack operations distinguish Native from Ex-

tended mode.

Note that regardless of Native or Extended mode, a 32-bit

address is always used for the data access. Thus, for data

reference, the complete 4 Gbytes of memory area may be

accessed. For example:

LD BC, (HL)

uses the 32-bit address value stored in HL31-HL0 (HLz

and HL) as a source location address. However, on Reset,

the HL31-HL16 portion (HLz) initializes to 00H. Unless HLz

is modified to other than 00H, operation of this instruction

is identical to the one with the Z80 CPU. Modifying the

extended portion of the register is done either by using a

32-bit load instruction (in Long Word mode, or with DDIR

LW instructions), or using a 16-bit load instruction with

SWAP instructions.

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The Z380 CPU implements one instruction to switch to

Extended mode from Native mode; SETC XM (set Ex-

tended mode) places the Z380 CPU in Extended mode.

Once in Extended mode, only Reset can return it to Native

mode. On Reset, the Z380 is in Native mode. Refer to

Sections 4 and 5 for more examples.

3.4 WORD AND LONG WORD MODE OF OPERATION

The Z380 CPU can operate in either Word or Long Word

mode. In Word mode (the Reset configuration), all word

operations manipulate 16-bit quantities, and are compat-

ible with the Z80 CPU 16-bit operations. In the Long Word

mode, all word operations can manipulate 32-bit quanti-

ties. Note that the Native/Extended and Word/Long Word

selections are independent of one another, as Word/Long

Word pertains to data and operand address manipulation

only. The Z380 CPU implements two instructions and two

decoder directives to allow switching between these two

modes; SETC LW (Set Long Word) and RESC LW (Reset

Long Word) perform a global switch, while DDIR LW and

DDIR W are decoder directives that select a particular

mode only for the instruction that they precede.

Examples:

1. Effect of Word mode and Long Word mode

DDIR W

LD BC, (HL)

Loads BC15-BC0 from the location (HL) and

(HL+1), and BCz (BC31-BC16) remains un-

changed.

DDIR LW

LD BC, (HL)

Loads BC31-BC0 from the locations (HL) to (HL+3).

2. Immediate data load with DDIR instructions

DDIR IW,LW

LD HL,12345678H

Loads 12345678H into HL31-HL0.

DDIR IB,LW

LD HL,123456H

Loads 00123456H into HL31-HL0.

00H is appended as the Most significant byte as

HL31-HL24.

DDIR LW

LD HL,1234H

Loads 00001234H into HL31-HL0.

0000H is appended as the HL31-HL16 portion.

Zilog’s products are not authorized for use as critical compo-

nents in life support devices or systems unless a specific written

agreement pertaining to such intended use is executed between

the customer and Zilog prior to use. Life support devices or

systems are those which are intended for surgical implantation

into the body, or which sustains life whose failure to perform,

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result in

significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave.

Campbell, CA 95008-6600

Telephone (408) 370-8000

Telex 910-338-7621

FAX 408 370-8056

Internet: http://www.zilog.com

part of this document may be copied or reproduced in any form

or by any means without the prior written consent of Zilog, Inc.

The information in this document is subject to change without

notice. Devices sold by Zilog, Inc. are covered by warranty and

patent indemnification provisions appearing in Zilog, Inc. Terms

and Conditions of Sale only.

ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY,

IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMA-

TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF

THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY

INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MER-

CHANTABILITY OR FITNESS FOR ANY PURPOSE.

Zilog, Inc. shall not be responsible for any errors that may appear

in this document. Zilog, Inc. makes no commitment to update or

keep current the information contained in this document.

4-1

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4.1 INSTRUCTION

SER

’s M

ANUAL

CHAPTER 4

ADDRESSING MODES AND DATA TYPES

An instruction is a consecutive list of one or more bytes in

memory. Most instructions act upon some data; the term

operand refers to the data to be operated upon. For Z380™

CPU instructions, operands can reside in CPU registers,

memory locations, or I/O ports (internal or external). The

method used to designate the location of the operands for

an instruction are called addressing modes. The Z380

CPU supports seven addressing modes; Register, Imme-

diate, Indirect Register, Direct Address, Indexed, Program

Counter Relative Address, and Stack Pointer Relative. A

wide variety of data types can be accessed using these

addressing modes.

4.2 ADDRESSING MODE DESCRIPTIONS

The following pages contain descriptions of the address-

ing modes for the Z380 CPU. Each description explains

how the operand’s location is calculated, indicates which

address spaces can be accessed with that particular

addressing mode, and gives an example of an instruction

using that mode, illustrating the assembly language format

for the addressing modes.

4.2.1 Register (R, RX)

When this addressing mode is used, the instruction pro-

cesses data taken from one of the 8-bit registers A, B, C,

D, E, H, L, IXU, IXL, IYU, IYL, one of the 16-bit registers BC,

DE, HL, IX, IY, SP, or one of the special byte registers I or

Storing data in a register allows shorter instructions and

faster execution that occur with instructions that access

memory.

Instruction

OPERATION REGISTER →OPERAND

The operand value is the contents of the register.

The operand is always in the register address space. The

opcode. In the case of Long Word register operation, it is

specified either through the SETC LW instruction or the

DDIR LW decoder directive.

Example of R mode:

1. Load register in Word mode.

DDIR W ;Next instruction in Word mode

LD BC,HL ;Load the contents of HL into BC

BCz BC HLz HL

Before instruction

execution 1234 5678 9ABC DEF0

After instruction

execution 1234 DEF0 9ABC DEF0

2. Load register in Long Word mode.

DDIR LW ;Next instruction in Long Word mode

LD BC,HL ;Load the contents of HL into BC

BCz BC HLz HL

Before instruction

execution 1234 5678 9ABC DEF0

After instruction

execution 9ABC DEF0 9ABC DEF0

4.2.2 Immediate (IM)

When the Immediate addressing mode is used, the data

processed is in the instruction.

The Immediate addressing mode is the only mode that

does not indicate a register or memory address as the

source operand.

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4.2.2 Immediate (IM) (Continued)

Instruction

OPERATION

OPERAND

The operand value is in the instruction

Immediate mode is often used to initialize registers. Also,

this addressing mode is affected by the DDIR Immediate

Data Directives to expand the immediate value to 24 bits

or 32 bits.

Example of IM mode:

1. Load immediate value into accumulator

LD A,55H ;Load hex 55 into the accumulator.

Before instruction execution 12

After instruction execution 55

4.2.3 Indirect Register (IR)

In Indirect Register addressing mode, the register speci-

fied in the instruction holds the address of the operand.

The data to be processed is in the location specified by the

BC, DE, or HL register (depending on the instruction) for

memory accesses, or C register for I/O.

Memory or

Instruction Register I/O Port

OPERATION REGISTER →Address →OPERAND

The operand value is the contents of the location whose address is in the register.

Depending on the instruction, the operand specified by IR

mode is located in either the I/O address space (I/O

instruction) or memory address space (all other instruc-

tions).

Indirect Register mode can save space and reduce ex-

ecution time when consecutive locations are referenced or

one location is repeatedly accessed. This mode can also

be used to simulate more complex addressing modes,

since addresses can be computed before data is ac-

cessed.

The address in this mode is always treated as a 32-bit

mode. After reset, the contents of the extend registers

(registers with “z” suffix) are initialized as 0's; hence, these

instructions will be executed just as for the Z80/Z180.

Example of IR mode:

1. Load accumulator from the contents of memory

pointed by (HL)

LD A, (HL) ;Load the accumulator with the data

;addressed by the contents of HL

A HLz,HL

Before instruction

execution 0F 12345678

After instruction

execution 0B 12345678

Memory location 12345678 0B

2. Load 24-bit immediate value into HL

DDIR IB, LW ;next instruction is in Long Word

mode, with ;an additional

immediate data

LD HL, 123456H ;load HLz, and HL with constant

123456H

This case, the Z380 CPU appends 00H as a MSB byte.

HLz HL

Before instruction execution 0987 6543

After instruction execution 0012 3456

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4.2.4 Direct Address (DA)

When Direct Address mode is used, the data processed is

at the location whose memory or I/O port address is in the

instruction.

Instruction Memory or

OPERATION I/O Port

ADDRESS →OPERAND

The operand value is the contents of the location whose

address is in the instruction.

Depending on the instruction, the operand specified by

DA mode is either in the I/O address space (I/O instruction)

or memory address space (all other instructions).

This mode is also used by Jump and Call instructions to

specify the address of the next instruction to be executed.

(The address serves as an immediate value that is loaded

into the program counter.)

Also, DDIR Immediate Data Directives are used to expand

the direct address to 24 or 32 bits. Operand width is

affected by LW bit status for the load and exchange

instructions.

Example of DA mode:

1. Load BC register from memory location 00005E22H in Word mode

LD BC, (5E22H) ;Load BC with the data in address

;00005E22H

Before instruction execution 1234

After instruction execution 0301

Memory location 00005E22 01

00005E23 03

2. Load BC register from memory location 12345E22H in Word mode

DDIR IW ;extend direct address by one word

LD BC, (12345E22H) ;Load BC with the data in address

;12345E22H

Before instruction execution 1234

After instruction execution 0301

Memory location 12345E22 01

12345E23 03

3. Load BC register from memory location 12345E22H in Long Word mode

DDIR IW,LW ;extend direct address by one word,

;and operation in Long Word

LD BC, (12345E22H) ;Load BC with the data in address

;12345E22H

BCz BC

Before instruction execution 1234 5678

After instruction execution 0705 0301

Memory location 12345E22 01

12345E23 03

12345E24 05

12345E25 07

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4.2.5 Indexed (X)

When the Indexed addressing mode is used, the data

processed is at the location whose address is the contents

of IX or IY in use, offset by an 8-bit signed displacement in

the instruction.

The Indexed address is computed by adding the 8-bit

two’s complement signed displacement specified in the

instruction to the contents of the IX or IY register in use, also

specified by the instruction. Indexed addressing allows

random access to tables or other complex data structures

where the address of the base of the table is known, but the

particular element index must be computed by the pro-

gram.

The offset portion can be expanded to 16 or 24 bits,

instead of eight bits by using DDIR Immediate Data Direc-

tives (DDIR IB for 16-bit offset, DDIR IW for 24-bit offset).

Note that computation of the effective address is affected

by the operation mode (Native or Extended). In Native

mode, address computation is done in modulo 216, and in

Extended mode, address computation is done in modulo

232.

Address calculation: In Native mode, 0FFH encoding in

the instruction is sign extended to a 16-bit value before the

address calculation, but calculation is done in modulo 216

and does not take into account the index register’s

extended portion.

0000

+ FFFF

FFFF

Instruction REGISTER MEMORY

OPERATION REGISTER →ADDRESS →+ OPERAND

DISPLACEMENT _____________________________________ ↑

Example of X mode:

1. Load accumulator from location (IX-1) in Native mode

LD A, (IX-1) ;Load into the accumulator the

;contents of the memory location

;whose address is one less than

;the contents of IX

;Assume it is in Native mode

A IXz IX

Before instruction execution 01 0001 0000

After instruction execution 23 0001 0000

Memory location 0001FFFF 23

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2. Load accumulator from location (IX-1) in Extended mode

SETC XM ;Set Extended mode

LD A, (IX-1) ;Load into the accumulator the

;contents of the memory location

;whose address is one less than

;the contents of IX

A IXz IX

Before instruction execution 01 0001 0000

After instruction execution 23 0001 0000

Memory location 0000FFFF 23

Address calculation: In Extended mode, 0FFH encoding in

the instruction is sign extended to a 32-bit value before the

address calculation, but calculation is done in modulo 232

and takes into account the index register’s extended

portion.

00010000

+ FFFFFFFF

0000FFFF

4.2.6 Program Counter Relative Mode (RA)

The Program Counter Relative Addressing mode is used

by certain program control instructions to specify the

address of the next instruction to be executed (specifically,

the sum of the Program Counter value and the displace-

ment value is loaded into the Program Counter). Relative

addressing allows reference forward or backward from the

current Program Counter value; it is used for program

control instructions such as Jumps and Calls that access

constants in the memory.

As a displacement, an 8-bit, 16-bit, or 24-bit value can be

used. The address to be loaded into the Program Counter

is computed by adding the two’s complement signed

displacement specified in the instruction to the current

Program Counter.

Note that computation of the effective address is affected

by the mode of operation (Native or Extended). In Native

mode, address computation is done in modulo 216, and the

PC Extend (PC31-PC16) is forced to 0 and will not affect

this portion. In Extended mode, address computation is

done is modulo 232, and will affect the contents of PC

extend if there is a carry or borrow operation.

Also, in Native mode,

Instruction PC MEMORY

OPERATION ADDRESS →+ OPERAND

DISPLACEMENT —↑

Example of RA mode:

1. Jump relative in Native mode, 8-bit displacement

JR $-2 ;Jumps to the location

;(Current PC value) – 2

;’$’ represents for current PC value

;This instruction jumps to itself.

;since after the execution of this instruction,

;PC points to the next instruction.

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4.2.6 Program Counter Relative Mode (RA) (Continued)

PCz PC

Before instruction execution 0000 1000

After instruction execution 0000 0FFE

Address calculation: In Native mode, –2 is encoded as

0FEH in the instruction, and it is sign extended to a 16-bit

value before added to the Program Counter. Calculation is

done in modulo 216 and does not affect the Extended

portion of the Program Counter.

1000

+ FFFE

FFFE

Address calculation: Since this is a 4-byte instruction, the

PC value after fetch but before jump taking place is:

19590807

+ 00000004

1959080B

The displacement portion, –5000H, is sign extended to a

32-bit value before being added to the Program Counter.

Calculation is done in modulo 232 and affects the Extended

portion of the Program Counter.

1959080B

+ FFFFB000

1958B80B

2. Jump relative in Extended mode, 16-bit displacement

SETC XM ;Put it in Extended mode of operation

JR $-5000H ;Jumps to the location

;(Current PC value) – 5000H

;$ stands for current PC value

;This instruction jumps to itself.

PCz PC

Before instruction execution 1959 0807

After instruction execution 1958 B80B

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4.2.7 Stack Pointer Relative Mode (SR)

For Stack Pointer Relative addressing mode, the data

processed is at the location whose address is the contents

of the Stack Pointer, offset by an 8-bit displacement in the

instruction.

The Stack Pointer Relative address is computed by adding

the 8-bit two’s complement signed displacement speci-

fied in the instruction to the contents of the SP, also

specified by the instruction. Stack Pointer Relative ad-

dressing mode is used to specify data items to be found in

the stack, such as parameters passed to procedures.

Offset portion can be expanded to 16 or 24 bits by using

DDIR immediate instructions (DDIR IB for a 16-bit offset,

DDIR IW for a 24-bit offset).

Note that computation of the effective address is affected

by the operation mode (Native or Extended). In Native

mode, address computation is done in modulo 216, mean-

ing computation is done in 16-bit and does not affect upper

half of the SP portion for calculation (wrap around within the

16-bit). In Extended mode, address computation is done

in modulo 232.

Also, the size of the data transfer is affected by the LW

mode bit. In Word mode, transfer is done in 16 bits, and in

Long Word mode, transfer is done in 32 bits.

Instruction SP

OPERATION ADDRESS ——| MEMORY

DISPLACEMENT ——+ OPERAND

Example of SR mode:

1. Load HL from location (SP – 4) in Native mode, Word mode

LD HL, (SP–4) ;Load into the HL from the

;contents of the memory location

;whose address is four less than

;the contents of SP.

;Assume it is in Native/Word mode.

HLz HL SPz SP

Before instruction execution 1234 5678 07FF 7F00

After instruction execution EFCD AB89 07FF 7F00

Memory location 07FF7EFC 89

07FF7EFD AB

Address calculation: In Native mode, FCH (–4 in Decimal)

encoding in the instruction is sign extended to a 16-bit

value before the address calculation. Calculation is done

in modulo 216 and does not take into account the Stack

Pointer’s extended portion.

7F00

+ FFFC

7EFC

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4.2.7 Stack Pointer Relative Mode (SR) (Continued)

2. Load HL from location (SP – 4) in Extended mode, Long Word mode

SETC XM ;In Extended mode

DDIR LW ;operate next instruction in Long Word mode

LD HL, (SP–4) ;Load into the HL from the

;contents of the memory location

;whose address is four less than

;the contents of SP.

HLz HL SPz SP

Before instruction execution 1234 5678 07FF 7F00

After instruction execution EFCD AB89 07FF 7F00

Memory location 07FF7EFC 89

07FF7EFD AB

07FF7EFE CD

07FF7EFF EF

Address calculation: In Extended mode, FCH (–4 in Deci-

mal) encoding in the instruction is sign extended to a 32-

bit value before the address calculation, and calculation is

done in modulo 232.

07FF7F00

+ FFFFFFFC

07FF7EFC

3. Load HL from location (SP + 10000H) in Extended mode, Long Word mode

SETC XM ;In Extended mode,

DDIR IW,LW ;operate next instruction in Long Word mode

;with a word immediate data.

LD HL, (SP+10000) ;Load into the HL from the

;contents of the memory location

;whose address is 10000H more than

;the contents of SP.

HLz HL SPz SP

Before instruction execution 1234 5678 07FF 7F00

After instruction execution EFCD AB89 07FF 7F00

Memory location 08007F00 89

08007F01 AB

08007F02 CD

08007F03 EF

Address calculation: In Extended mode, 010000H encod-

ing in the instruction is sign extended to a 32-bit value

before the address calculation, and calculation is done in

modulo 232.

07FF7F00

+ 00010000

08007F00

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4.3 DATA TYPES

The Z380 CPU can operate on bits, binary-coded decimal

(BCD) digits (four bits), bytes (eight bits), words (16 bits or

32 bits), byte strings, and word strings. Bits in registers can

be set, cleared, and tested.

The basic data type is a byte, which is also the basic

accessible element in the register, memory, and I/O address

space. The 8-bit load, arithmetic, logical, shift, and rotate

instructions operate on bytes in registers or memory. Bytes

can be treated as logical, signed numeric, or unsigned

numeric value.

Words are operated on in a similar manner by the word

load, arithmetic, logical, and shift and rotate instructions.

Operation on 2-byte words is also supported. Sixteen-bit

load and arithmetic instructions operate on words in

registers or memory; words can be treated as signed or

unsigned numeric values. I/O reads and writes can be

8-bit or 16-bit operations. Also, the Z380 CPU architecture

supports operation in Long Word mode to handle a 32-bit

address manipulation. For that purpose, 16-bit wide

registers originally on the Z80 have been expanded to 32

bits wide, along with the support of the arithmetic instruction

needed for a 32-bit address manipulation.

Bits are fully supported and addressed by number within

a byte (see Figure 2-2). Bits within byte registers or

memory locations can be tested, set, or cleared.

Operation on binary-coded decimal (BCD) digits are sup-

ported by Decimal Adjust Accumulator (DAA) and Rotate

Digit (RLD and RRD) instructions. BCD digits are stored in

byte registers or memory locations, two per byte. The DAA

instruction is used after a binary addition or subtraction of

BCD numbers. Rotate Digit instructions are used to shift

BCD digit strings in memory.

Strings of up to 65536 (64K) bytes of Byte data or Word

data can be manipulated by the Z380 CPU’s block move,

block search, and block I/O instructions. The block move

instructions allow strings of bytes/words in memory to be

moved from one location to another. Block search instruc-

tions provide for scanning strings of bytes/words in memory

to locate a particular value. Block I/O instructions allow

strings of bytes or words to be transferred between memory

and a peripheral device.

Arrays are supported by Indexed mode (with 8-bit, 16-bit,

or 24-bit displacement). Stack is supported by the Indexed

and the Stack Pointer Relative addressing modes, and by

special instructions such as Call, Return, Push, and Pop.

Zilog’s products are not authorized for use as critical compo-

nents in life support devices or systems unless a specific written

agreement pertaining to such intended use is executed between

the customer and Zilog prior to use. Life support devices or

systems are those which are intended for surgical implantation

into the body, or which sustains life whose failure to perform,

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result in

significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave.

Campbell, CA 95008-6600

Telephone (408) 370-8000

Telex 910-338-7621

FAX 408 370-8056

Internet: http://www.zilog.com

part of this document may be copied or reproduced in any form

or by any means without the prior written consent of Zilog, Inc.

The information in this document is subject to change without

notice. Devices sold by Zilog, Inc. are covered by warranty and

patent indemnification provisions appearing in Zilog, Inc. Terms

and Conditions of Sale only.

ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY,

IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMA-

TION SET FORTH HEREIN OR REGARDING THE FREEDOM OF

THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY

INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MER-

CHANTABILITY OR FITNESS FOR ANY PURPOSE.

Zilog, Inc. shall not be responsible for any errors that may appear

in this document. Zilog, Inc. makes no commitment to update or

keep current the information contained in this document.

5-1

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5.1 INTRODUCTION

SER

’s M

ANUAL

CHAPTER 5

INSTRUCTION SET

The Z380™ CPU instruction set is a superset of the Z80 CPU

and the Z180 MPU; the Z380 CPU is opcode compatible

with the Z80 CPU/Z180 MPU. Thus, a Z80/Z180 program

can be executed on a Z380 CPU without modification. The

instruction set is divided into 12 groups by function:

■8-Bit Load/Exchange Group

■16/32-Bit Load, Exchange, SWAP and Push/Pop Group

■Block Transfers, and Search Group

■8-Bit Arithmetic and Logic Operations

■16/32-Bit Arithmetic Operations

■8-Bit Bit Manipulation, Rotate and Shift Group

■16-Bit Rotates and Shifts

5.2 PROCESSOR FLAGS

The Flag register contains six bits of status information that

are set or cleared by CPU operations (Figure 5-1). Four of

these bits are testable (C, P/V, Z, and S) for use with

conditional jump, call, or return instructions. Two flags are

not testable (H and N) and are used for binary-coded

decimal (BCD) arithmetic.

The Flag register provides a link between sequentially

executed instructions, in that the result of executing one

instruction may alter the flags, and the resulting value of the

flags can be used to determine the operation of a subse-

quent instruction. The program control instructions, whose

operation depends on the state of the flags, are the Jump,

Jump Relative, subroutine Call, Call Relative, and subrou-

tine Return instructions; these instructions are referred to

as conditional instructions.

Figure 5-1. Flag Register

■Program Control Group

■Input and Output Operations for External I/O Space

■Input and Output Operations for Internal I/O Space

■CPU Control Group

■Decoder Directives

This chapter describes the instruction set of the Z380 CPU.

Flags and condition codes are discussed in relation to the

instruction set. Then, the interpretability of instructions and

trap are discussed. The last part of this chapter is a

detailed description of each instruction, listed in alphabeti-

cal order by mnemonic. This section is intended as a

reference for Z380 CPU programmers. The entry for each

instruction contains a complete description of the instruc-

tion, including addressing modes, assembly language

mnemonics, and instruction opcode formats.

SZXHXP/VNC

76543210

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5.2.1 Carry Flag (C)

The Carry flag is set or cleared depending on the operation

being performed. For add instructions that generate a

carry and subtract instruction generating a borrow, the

Carry flag is set to 1. The Carry flag is cleared to 0 by an add

that does not generate a carry or a subtract that generates

no borrow. This saved carry facilitates software routines for

extended precision arithmetic. The multiply instructions

use the Carry flag to signal information about the precision

of the result. Also, the Decimal Adjust Accumulator (DAA)

instruction leaves the Carry flag set to 1 if a carry occurs

when adding BCD quantities.

For rotate instructions, the Carry flag is used as a link

between the least significant and most significant bits for

any register or memory location. During shift instructions,

the Carry flag contains the last value shifted out of any

Carry flag is cleared. The Carry flag can also be set and

complemented with explicit instructions.

5.2.2 Add/Subtract Flag (N)

The Add/Subtract flag is used for BCD arithmetic. Since

the algorithm for correcting BCD operations is different for

addition and subtraction, this flag is used to record when

an add or subtract was last executed, allowing a subse-

quent Decimal Adjust Accumulator instruction to perform

correctly. See the discussion of the DAA instruction for

further information.

5.2.3 Parity/Overflow Flag (P/V)

This flag is set to a particular state depending on the

operation being performed.

For signed arithmetic, this flag, when set to 1, indicates that

the result of an operation on two’s complement numbers

has exceeded the largest number, or less than the smallest

number, that can be represented using two’s complement

notation. This overflow condition can be determined by

examining the sign bits of the operands and the result.

The P/V flag is also used with logical operations and rotate

instructions to indicate the parity of the result. The of bits

set to 1 in a byte are counted. If the total is odd, this flag is

reset indicates odd parity (P = 0). If the total is even, this

flag is set indicates even parity (P = 1).

During block search and block transfer instructions, the P/

V flag monitors the state of the Byte Count register (BC).

When decrementing the byte counter results in a zero

value, the flag is cleared to 0; otherwise the flag is set to 1.

During Load Accumulator with I or R register instruction,

the P/V flag is loaded with the IEF2 flag. For details on this

topic,.refer to Chapter 6, “Interrupts and Traps.”

When a byte is inputted to a register from an I/O device

addressed by the C register, the flag is adjusted to indicate

the parity of the data.

5.2.4 Half-Carry Flag (H)

The Half-Carry flag (H) is set to 1 or cleared to 0 depending

on the carry and borrow status between bits 3 and 4 of an

8-bit arithmetic operation and between bits 11 and 12 of a

16-bit arithmetic operation. This flag is used by the Deci-

mal Adjust Accumulator instruction to correct the result of

an addition or subtraction operation on packed BCD data.

5.2.5 Zero Flag (Z)

The Zero flag (Z) is set to 1 if the result generated by the

execution of certain instruction is a zero.

For arithmetic and logical operations, the Zero flag is set to

1 if the result is zero. If the result is not zero, the Zero flag

is cleared to 0.

For block search instructions, the Zero flag is set to 1 if a

comparison is found between the value in the Accumulator

and the memory location pointed to by the contents of the

When testing a bit in a register or memory location, the Zero

flag contains the complemented state of the tested bit (i.e.,

the Zero flag is set to 1 if the tested bit is a 0, and vice-

versa).

For block I/O instructions, if the result of decrements B is

zero, the Zero flag is set to 1; otherwise, it is cleared to 0.

Also, for byte inputs to registers from I/O devices ad-

dressed by the C register, the Zero flag is set to 1 to

indicate a zero byte input.

5.2.6 Sign Flag (S)

The Sign flag (S) stores the state of the most significant bit

of the result. When the Z380 CPU performs arithmetic

operation on signed numbers, binary two’s complement

notation is used to represent and process numeric infor-

mation. A positive number is identified by a 0 in the most

significant bit. A negative number is identified by a 1 in the

most significant bit.

When inputting a byte from an I/O device addressed by the

C register to a CPU register, the Sign flag indicates either

positive (S = 0) or negative (S = 1) data.

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5.2.7 Condition Codes

The Carry, Zero, Sign, and Parity/Overflow flags are used

to control the operation of the conditional instructions. The

operation of these instructions is a function of the state of

one of the flags. Special mnemonics called condition

codes are used to specify the flag setting to be tested

during execution of a conditional instruction; the condition

codes are encoded into a 3-bit field in the instruction

opcode itself.

Table 5-1 lists the condition code mnemonic, the flag

setting it represents, and the binary encoding for each

condition code.

Table 5-1. Condition codes

Condition Codes for Jump, Call, and Return Instructions

Mnemonic Meaning Flag Setting Binary Code

NZ Not Zero* Z = 0 000

Z Zero* Z = 1 001

NC No Carry* C = 0 010

C Carry* C = 1 011

NV No Overflow V = 0 100

PO Parity Odd V = 0 100

V Overflow V = 1 101

PE Parity Even V = 1 101

NS No Sign S = 0 110

P Plus S = 0 110

S Sign S = 1 111

M Minus S = 1 111

*Abbreviated set

Condition Codes for Jump Relative and Call Relative Instructions

Mnemonic Meaning Flag Setting Binary Code

NZ Not Zero Z = 0 100

Z Zero Z = 1 101

NC No Carry C = 0 110

C Carry C = 1 111

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5.3 SELECT REGISTER

The Select Register (SR) controls the register set selection

and the operating modes of the Z380 CPU. The reserved

bits in the SR are for future expansion; they will always read

as zeros and should be written with zeros for future

compatibility. Access to this register is done by using the

newly added LDCTL instruction. Also, some of the instruc-

tions like EXX, IM p, and DI/EI change the bit(s). The SR

was shown in Figure 5-2.

Reserved (0)

23 2122 17

IYBANK IYP Reserved (0) IXBANK IXP

20 1819 1631 2930 2528 2627 24

XSRYSR

Reserved (0)

7561

MAINBANK ALT XM IM AFP

423015 1314 912 1011 8

DSR

LW IEF1 0 LCK

Figure 5-2. Select Register

5.3.1. IY Bank Select (IYBANK)

This 2-bit field selects the register set to be used for the IY

and IY’ registers. This field can be set independently of the

Reset selects Bank 0 for IY and IY’.

5.3.2. IY or IY’ Register Select (IY’)

This bit controls and reports whether IY or IY’ is the

currently active register. IY is selected when this bit is

cleared, and IY’ is selected when this bit is set. Reset

clears this bit, selecting IY.

5.3.3. IX Bank Select (IXBANK)

This 2-bit field selects the register set to be used for the IX

and IX’ registers. This field can be set independently of the

Reset selects Bank 0 for IX and IX’.

5.3.4. IX or IX’ Register Select (IX’)

This bit controls and reports whether IX or IX’ is the

currently active register. IX is selected when this bit is

cleared, and IX’ is selected when this bit is set. Reset

clears this bit, selecting IX.

5.3.5. Main Bank Select (MAINBANK)

This 2-bit field selects the register set to be used for the A,

F, BC, DE, HL, A’, F’, BC’, DE’, and HL’ registers. This field

can be set independently of the register set selection for

the other Z380 CPU registers. Reset selects Bank 0 for

these registers.

5.3.6. BC/DE/HL or BC’/DE’/HL’ Register

Select (ALT)

This bit controls and reports whether BC/DE/HL or BC’/DE’/

HL’ is the currently active bank of registers. BC/DE/HL is

selected when this bit is cleared, and BC’/DE’/HL’ is

selected when this bit is set. Reset clears this bit, selecting

BC/DE/HL.

5.3.7. Extended Mode (XM)

This bit controls the Extended/Native mode selection for

the Z380 CPU. This bit is set by the SETC XM instruction.

This bit can not be reset by software, only by Reset. When

this bit is set, the Z380 CPU is in Extended mode. Reset

clears this bit, and the Z380 CPU is in Native mode.

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5.3.8. Long Word Mode (LW)

This bit controls the Long Word/Word mode selection for

the Z380 CPU. This bit is set by the SETC LW instruction

and cleared by the RESC LW instruction. When this bit is

set, the Z380 CPU is in Long Word mode; when this bit is

cleared the Z380 CPU is in Word mode. Reset clears this

bit. Note that individual Word load and exchange instruc-

tions may be executed in either Word or Long Word mode

using the DDIR W and DDIR LW decoder directives.

5.3.9. Interrupt Enable Flag (IEF)

This bit is the master Interrupt Enable for the Z380 CPU.

This bit is set by the EI instruction and cleared by the DI

instruction, or on acknowledgment of an interrupt request.

When this bit is set, interrupts are enabled; when this bit is

cleared, interrupts are disabled. Reset clears this bit.

5.3.10. Interrupt Mode (IM)

This 2-bit field controls the interrupt mode for the /INT0

interrupt request. These bits are controlled by the IM

instructions (00 = IM 0, 01 = IM 1, 10 = IM 2, 11 = IM 3).

Reset clears both of these bits, selecting Interrupt Mode 0.

5.3.11. Lock (LCK)

This bit controls the Lock/Unlock status of the Z380 CPU.

This bit is set by the SETC LCK instruction and cleared by

the RESC LCK instruction. When this bit is set, no bus

requests will be accepted, providing exclusive access to

the bus by the Z380 CPU. When this bit is cleared, the Z380

CPU will grant bus requests in the normal fashion. Reset

clears this bit.

5.3.12. AF or AF’ Register Select (AF’)

This bit controls and reports whether AF or AF’ is the

currently active pair of registers. AF is selected when this

bit is cleared, and AF’ is selected when this bit is set. Reset

clears this bit, selecting AF.

5.4 INSTRUCTION EXECUTION AND EXCEPTIONS

Three types of exception conditions—interrupts, trap, and

Reset—can alter the normal flow of program execution.

Interrupts are asynchronous events generated by a device

external to the CPU; peripheral devices use interrupts to

request service from the CPU. Trap is a synchronous event

generated internally in the CPU by executing undefined

instructions. Reset is an asynchronous event generated by

outside circuits. It terminates all current activities and puts

the CPU into a known state. Interrupts and Traps are

discussed in detail in Chapter 6, and Reset is discussed in

detail in Chapter 7. This section examines the relationship

between instructions and the exception conditions.

5.4.1 Instruction Execution and Interrupts

When the CPU receives an interrupt request, and it is

enabled for interrupts of that class, the interrupt is normally

processed at the end of the current instruction. However,

the block transfer and search instructions are designed to

be interruptible so as to minimize the length of time it takes

the CPU to respond to an interrupt. If an interrupt request

is received during a block move, block search, or block

I/O instruction, the instruction is suspended after the

current iteration. The address of the instruction itself, rather

than the address of the following instruction, is saved on

the stack, so that the same instruction is executed again

when the interrupt handler executes an interrupt return

instruction. The contents of the repetition counter and the

registers that index into the block operands are such that,

after each iteration, when the instruction is reissued upon

returning from an interrupt, the effect is the same as if the

instruction were not interrupted. This assumes, of course,

that the interrupt handler preserves the registers.

5.4.2 Instruction Execution and Trap

The Z380 MPU generates a Trap when an undefined

opcode is encountered. The action of the CPU in response

to Trap is to jump to address 00000000H with the status

bit(s) set. This response is similar to the Z180 MPU’s action

on execution of an undefined instruction. The Trap is

enabled immediately after reset, and it is not maskable.

This feature can be used to increase software reliability or

to implement “extended” instructions. An undefined op-

code can be fetched from the instruction stream, or it can

be returned as a vector in an interrupt acknowledge

transaction in Interrupt mode 0.

Since it jumps to address 00000000H, it is necessary to

have a Trap handling routine at the beginning of the

program if processing is to proceed. Otherwise, it behaves

just like a reset for the CPU. For a detailed description, refer

to Chapter 6.

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5.5 INSTRUCTION SET FUNCTIONAL GROUPS

An Exchange instruction is available for swapping the

contents of the accumulator with another register or with

memory, as well as between registers. Also, exchange

instructions are available which swap the contents of the

bank.

The instruction in this group does not affect the flags.

This section presents an overview of the Z380 instruction

set, arranged by functional groups. (See Section 5.5 for an

explanation of the notation used in Tables 5-2 through 5-

11).

5.5.1 8-Bit Load/Exchange Group

This group of instructions (Table 5-2) includes load instruc-

tions for transferring data between byte registers, transfer-

ring data between a byte register and memory, and load-

ing immediate data into byte register or memory. For the

supported source/destination combinations, refer to Table

5-3.

Table 5-3. 8-Bit Load Group Allowed Source/Destination Combinations

Source

Dist. A B C D E H L IXH IXL IYH IYL n (nn) (BC) (DE) (HL) (IX+d) (IY+d)

A√√ √√√√ √ √ √ √ √ √√ √√ √ √ √

B√√√√√√√√ √√ √√ √√ √

C√√√√√√√√ √√ √√ √√ √

D√√√√√√√√ √√ √√ √√ √

E√√√√√√√√ √√ √√ √√ √

H√√ √√√√ √ √ √ √ √

L√√ √√√√ √ √ √ √ √

IXH √√ √√√ √ √ √

IXL √√ √√√ √ √ √

IYH √√ √√√ √ √ √

IYL √√ √√√ √ √ √

(BC) √

(DE) √

(HL) √√ √√√√ √ √

(nn) √

(IX+d) √√ √√√√ √ √

(IY+d) √√ √√√√ √ √

Table 5-2. 8-Bit Load Group Instructions

Instruction Name Format Note

Exchange with Accumulator EX A,r

EX A,(HL)

Exchange r and r’ EX r,r’ r=A, B, C, D, E, H or L

Load Accumulator LD A,src See Table 5-3

LD dst,A See Table 5-3

Load Immediate LD dst,n See Table 5-3

LD (HL),n See Table 5-3

Load Register (Byte) LD R,src See Table 5-3

LD R,(HL) See Table 5-3

LD dst,R See Table 5-3

LD (HL),R See Table 5-3

Note: √ are supported combinations.

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5.5.2 16-Bit and 32-Bit Load, Exchange,

SWAP, and PUSH/POP Group

This group of load, exchange, and PUSH/POP instructions

(Table 5-4) allows one or two words of data (two bytes

equal one word) to be transferred between registers and

memory.

The exchange instructions (Table 5-5) allow for switching

between the primary and alternate register files, exchang-

ing the contents of two register files, exchanging the

contents of an addressing register with the top word on the

stack. For possible combinations of the word exchange

instructions, refer to Table 5-5. The 16-bit and 32-bit loads

include transfer between registers and memory and imme-

diate loads of registers or memory. The Push and Pop

stack instructions are also included in this group. None of

these instructions affect the CPU flags, except for EX AF,

AF’.

Table 5-6 has the supported source/destination combina-

tion for the 16-bit and 32-bit load instructions. The transfer

size, 16-bit or 32-bit, is determined by the status of LW bit

in SR, or by DDIR Decoder Directives.

PUSH/POP instructions are used to save/restore the con-

tents of a register onto the stack. It can be used to

exchange data between procedures, save the current

stack, such as return addresses. Supported sources are

listed in Table 5-7.

Swap instructions allows swapping of the contents of the

Word wide register (BC, DE, HL, IX, or IY) with its Extended

portion. These instructions are useful to manipulate the

upper word of the register to be set in Word mode. For

example, when doing data accesses, other than

00000000H-0000FFFFH address range, use this instruc-

tion to set “data frame” addresses.

This group of instructions is affected by the status of the LW

bit in SR (Select Register), and Decoder Directives which

specifies the operation mode in Word or Long Word.

Table 5-4. 16-Bit and 32-Bit Load, Exchange, PUSH/POP Group Instructions

Instruction Name Format Note

Exchange Word/Long Word Registers EX dst,src See Table 5-5

Exchange Byte/Word Registers with Alternate Bank EXX

Exchange Register Pair with Alternate Bank EX RR,RR’ RR = AF, BC, DE, or HL

Exchange Index Register with Alternate Bank EXXX

EXXY

Exchange All Registers with Alternate Bank EXALL

Load Word/Long Word Registers LD dst,src See Table 5-6

LDW dst,src See Table 5-6

POP POP dst See Table 5-7

PUSH PUSH src See Table 5-7

Swap Contents of D31-D16 and D15-D0 SWAP dst dst = BC, DE, HL, IX, or IY

Table 5-5. Supported Source and Destination

Combination for 16-Bit and 32-Bit

Exchange Instructions

Source

Destination BC DE HL IX IY

BC √√√√

DE √√√

HL √√

IX √

(SP) √√√

Note: √ are supported combinations. The exchange in-

structions which designate IY register as destination are

covered by the other combinations. These Exchange

Word instructions are affected by Long Word mode.

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5.5.2 16-Bit and 32-Bit Load, Exchange,

SWAP and PUSH/POP Group (Continued)

Table 5-6. Supported Source and Destination Combination for 16-Bit and 32-Bit Load Instructions.

Source

Destination BC DE HL IX IY SP nn (nn) (BC) (DE) (HL) (IX+d) (IY+d) (SP+d)

BC LLLLL ILIL L L L IL IL IL

DE LLLLL ILIL L L L IL IL IL

HL LLLLL ILIL L L L IL IL IL

IX L L L L IL IL L L L IL IL

IY LLLL ILIL L L L IL IL

SP L L L IL IL

(BC) LLLLL ILW

(DE) LLLLL ILW

(HL) LLLLL ILW

(nn) IL IL IL IL IL IL

(IX+d) IL IL IL IL

(IY+d) IL IL IL IL

(SP+d) IL IL IL IL IL

Note: The column with the character(s) are the allowed

source/destination combinations. The combination with

“L” means that the instruction is affected by Long Word

mode, “I” means that the instruction is can be used with

DDIR Immediate instruction. Also, “W” means the instruc-

tion uses the mnemonic of “LDW” instead of “LD”.

Table 5-7. Supported Operand for PUSH/POP Instructions

AF BC DE HL IX IY SR nn

PUSH √ √ √ √√√√ √

POP √ √ √ √√√√

Note: These PUSH/POP instructions are affected by Long Word mode of operations.

Various Z380 CPU registers are dedicated to specific

functions for these instructions—the BC register for a

counter, the DEz/DE and HLz/HL registers for memory

pointers, and the accumulator for holding the byte value

being sought. The repetitive forms of these instructions are

interruptible; this is essential since the repetition count can

be as high as 65536. The instruction can be interrupted

after any interaction, in which case the address of the

instruction itself, rather than next one, is saved on the

stack. The contents of the operand pointer registers, as

well as the repetition counter, are such that the instruction

can simply be reissued after returning from the interrupt

without any visible difference in the instruction execution.

In case of Word or Long Word block transfer instructions,

the counter value held in the BC register is decremented

by two or four, depending on the LW bit status. Since

exiting from these instructions will be done when counter

value gets to 0, the count value stored in the BC registers

5.5.3 Block Transfer and Search Group

This group of instructions (Table 5-8) supports block

transfer and string search functions. Using these instruc-

tions, a block of up to 65536 bytes of byte, Word, or Long

Word data can be moved in memory, or a byte string can

be searched until a given value is found. All the operations

can proceed through the data in either direction. Further-

more, the operations can be repeated automatically while

decrementing a length counter until it reaches zero, or they

can operate on one storage unit per execution with the

length counter decremented by one and the source and

destination pointer register properly adjusted. The latter

form is useful for implementing more complex operations

in software by adding other instructions within a loop

containing the block instructions.

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has to be an even number (D0 = 0) in Word mode transfer,

and a multiple of four in Long Word mode (D1 and D0 are

both 0). Also, in Word or Long Word Block transfer,

memory pointer values are recommended to be even

numbers so the number of the transactions will be mini-

mized.

Note that regardless of the Z380’s operation mode, Native

or Extended, memory pointer increment/decrement will be

done in modulo 232. For example, if the operation is LDI and

HL31-HL0 (HLz and HL) hold 0000FFFF, after the opera-

tion the value in the HL31-HL0 will be 0010000.

Table 5-8. Block Transfer and Search Group

Instruction Name Format

Compare and Decrement CPD

Compare, Decrement and Repeat CPDR

Compare and Increment CPI

Compare, Increment and Repeat CPIR

Load and Decrement LDD

Load , Decrement and Repeat LDDI

Load and Increment LDI

Load, Increment and Repeat LDIR

Load and Decrement in Word/Long Word LDDW

Load, Decrement and Repeat in Word/Long Word

LDDRW

Load and Increment in Word/Long Word LDIW

Load, Increment and Repeat in Word/Long WordLDIRW

5.5.4 8-bit Arithmetic and Logical Group

This group of instructions (Table 5-9) perform 8-bit arith-

metic and logical operations. The Add, Add with Carry,

Subtract, Subtract with Carry, AND, OR, Exclusive OR, and

Compare takes one input operand from the accumulator

and the other from a register, from immediate data in the

instruction itself, or from memory. For memory addressing

modes, follows are supported—Indirect Register, Indexed,

and Direct Address—except multiplies, which returns the

16-bit result to the same register by multiplying the upper

and lower bytes of one of the register pair (BC, DE, HL, or

SP).

The Increment and Decrement instructions operate on

data in a register or in memory; all memory addressing

modes are supported. These instructions operate only on

the accumulator—Decimal Adjust, Complement, and Ne-

gate. The final instruction in this group, Extend Sign, sets

the CPU flags according to the computed result.

The EXTS instruction extends the sign bit and leaves the

result in the HL register. If it is in Long Word mode, HLz

(HL31-HL16) portion is also affected.

The TST instruction is a nondestructive AND instruction. It

ANDs "A" register and source, and changes flags accord-

ing to the result of operation. Both source and destination

values will be preserved.

Table 5-9. Supported Source/Destination for 8-Bit Arithmetic and Logic Group

src/

Instruction Name Format dst A B C D E H L IXH IXL IYH IYL n (HL) (IX+d) (IY+x)

Add With Carry (Byte) ADC A,src src √ √√√ √√√√ √ √ √ √√ √ √

Add (Byte) ADD A,src src √ √ √√ √√√√ √ √ √ √√ √ √

AND AND [A,]src src √ √ √√ √√√√ √ √ √ √√ √ √

Compare (Byte) CP [A,]src src √ √√√ √√√√ √ √ √ √√ √ √

Complement Accumulator CPL [A] dst √

Decimal Adjust Accumulator DAA dst √

Decrement (Byte) DEC dst dst √ √ √√ √√√√ √ √ √ √√ √ √

Extend Sign (Byte) EXTS [A] dst √

Increment (Byte) INC dst dst √ √√√ √√√√ √ √ √ √√ √ √

Multiply (Byte) MLT src Note 1

Negate Accumulator NEG [A] dst √

OR OR [A,]src src √ √ √√ √√√√ √ √ √ √√ √ √

Subtract with Carry (Byte) SBC A,src src √ √ √√ √√√√ √ √ √ √√ √ √

Subtract (Byte) SUB [A,]src src √ √ √√ √√√√ √ √ √ √√ √ √

Nondestructive Test TST dst src √ √√√ √√√ √√

Exclusive OR XOR [A,]src src √ √√√ √√√√ √ √ √ √√ √ √

Note 1: dst = BC, DE, HL, or SP.

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5.5.5 16-Bit Arithmetic Operation

This group of instructions (Table 5-10) provide 16-bit

arithmetic instructions. The Add, Add with Carry, Subtract,

Subtract with Carry, AND, OR, Exclusive OR, and Com-

pare takes one input operand from an addressing register

and the other from a 16-bit register, or from the instruction

itself; the result is returned to the addressing register. The

16-bit Increment and Decrement instructions operate on

data found in a register or in memory; the Indirect Register

or Direct Address addressing mode can be used to

specify the memory operand.

The remaining 16-bit instructions provide general arith-

metic capability using the HL register as one of the input

operands. The word Add, Subtract, Compare, and signed

and unsigned Multiply instructions take one input operand

from the HL register and the other from a 16-bit register,

from the instruction itself, or from memory using Indexed

Table 5-10. 16-Bit Arithmetic Operation

src/

Instruction Name Format dst BC DE HL SP IX IY nn (nn) (IX+d) (IY+d)

Add With Carry (Word) ADC HL,src src √√√√

ADCW [HL],src src √√√ √√√ √ √

Add (Word) ADD HL,src src √√√√ √ X

ADD IX,src src √√ √√ X

ADD IY,src src √√√√ X

ADDW [HL,]src src √√√ √√√ √ √

Add to Stack Pointer ADD SP,nn src √X

AND Word ANDW [HL,]src src √√√ √√√ √ √

Complement Accumulator CPLW [HL] dst √

Compare (Word) CPW [HL,]src src √√√ √√√ √ √

Decrement (Word) DEC[W] dst dst √√√√√√ X

Divide Unsigned DIVUW [HL,]src src √√√ √√√ √ √

Extend Sign (Word) EXTSW [HL] dst √

Increment (Word) INC[W] dst dst √√√√√√ X

Multiply Word Signed MULT [HL,]src src √√√ √√√ √ √

Multiply Word Unsigned MULTUW [HL,]src src √√√ √√√ √ √

Negate Accumulator NEGW [A] dst √

OR Word ORW [HL,]src src √√√ √√√ √ √

Subtract with Carry (Word) SBC HL,src src √√√√ √

SBCW [HL],src src √√√ √√√ √ √

Subtract (Word) SUB HL,(nn) src √X

SUBW [HL,]src src √√√ √√√ √ √

Subtract from Stack Pointer SUB SP,nn src √X

Exclusive OR XORW [HL,]src src √√√ √√√ √ √

Note: that the instructions with “X” at the rightmost column is affected by

Extended mode. These operate across all the 32 bits in Modulo 232 for

address calculation.

or Direct Address addressing mode. The 32-bit result of a

multiply is returned to the HLz and HL (HL31-HL0). The

unsigned divide instruction takes a 16-bit dividend from

the HL register and a 16-bit divisor from a register, from the

instruction, or memory using the Indexed mode. The 16-bit

quotient is returned in the HL register and the 16-bit

reminder is returned to the HLz (HL31-HL16). The Extend

Sign instruction takes the contents of the HL register and

delivers the 32-bit result to the HLz and HL registers. The

Negate HL instruction negates the contents of the HL

Except for Increment, Decrement, and Extend Sign, all the

instructions in this group set the CPU flags to reflect the

computed result.

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5.5.6 8-Bit Manipulation, Rotate and Shift

Group

Instructions in this group (Table 5-11) test, set, and reset

bits within bytes, and rotate and shift byte data one bit

position. Bits to be manipulated are specified by a field

within the instruction. Rotate can optionally concatenate

the Carry flag to the byte to be manipulated. Both left and

right shifting is supported. Right shifts can either shift 0 into

bit 7 (logical shifts), or can replicate the sign in bits 6 and

7 (arithmetic shifts). All these instructions, Set Bit and

Reset Bit, set the CPU flags according to the calculated

result; the operand can be a register or a memory location

specified by the Indirect Register or Indexed addressing

mode.

The RLD and RRD instructions are provided for manipulat-

ing strings of BCD digits; these rotate 4-bit quantities in

memory specified by the Indirect Register. The low-order

four bits of the accumulator are used as a link between

rotation of successive bytes.

Table 5-11. Bit Set/Reset/Test, Rotate and Shift Group

Instruction Name Format A B C D E H L (HL) (IX+d) (IY+d)

Bit Test BIT dst √√√√√√√√√√

Reset Bit RES dst √√√√√√√√√√

Rotate Left RL dst √√√√√√√√√√

Rotate Left Accumulator RLA √

Rotate Left Circular RLC dst √√√√√√√√√√

Rotate Left Circular (Accumulator) RLCA √

Rotate Left Digit RLD √

Rotate Right RR dst √√√√√√√√√√

Rotate Right Accumulator RRA √

Rotate Right Circular RRC dst √√√√√√√√√√

Rotate Right Circular (Accumulator) RRCA √

Rotate Right Digit RRD √

Set Bit SET dst √√√√√√√√√√

Shift Left Arithmetic SLA dst √√√√√√√√√√

Shift Right Arithmetic SRA dst √√√√√√√√√√

Shift Right Logical SRL √√√√√√√√√√

5.5.7 16-Bit Manipulation, Rotate and Shift

Group

Instructions in this group (Table 5-12) rotate and shift word

data one bit position. Rotate can optionally concatenate

the Carry flag to the word to be manipulated. Both left and

right shifting is supported. Right shifts can either shift 0 into

bit 15 (logical shifts), or can replicate the sign in bits 14 and

15 (arithmetic shifts). The operand can be a register pair or

memory location specified by the Indirect Register or

Indexed addressing mode, as shown below.

Table 5-12. 16-Bit Rotate and Shift Group.

Destination

Instruction Name Format BC DE HL IX IY (HL) (HL) (IX+d) (IY+d)

Rotate Left Word RLW dst √√√√√√√ √ √

Rotate Left Circular Word RLCW dst √√√√√√√ √ √

Rotate Right Word RRW dst √√√√√√√ √ √

Rotate Right Circular Word RRCW dst √√√√√√√ √ √

Shift Left Arithmetic Word SLAW dst √√√√√√√ √ √

Shift Right Arithmetic Word SRAW dst √√√√√√√ √ √

Shift Right Logical Word SRLW √√√√√√√ √ √

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5.5.8 Program Control Group

This group of instructions (Table 5-13) affect the Program

Counter (PC) and thereby control program flow. The CPU

registers and memory are not altered except for the Stack

Pointer and the Stack, which play a significant role in

procedures and interrupts. (An exception is Decrement

and Jump if Non-Zero [DJNZ], which uses a register as a

loop counter.) The flags are also preserved except for the

two instructions specifically designed to set and comple-

ment the Carry flag.

The Set/Reset Condition flag instructions can be used with

Conditional Jump, conditional Jump Relative, Conditional

Call, and Conditional Return instructions to control the

program flow.

The Jump and Jump Relative (JR) instructions provide a

conditional transfer of control to a new location if the

processor flags satisfy the condition specified in the in-

struction. Jump Relative, with an 8-bit offset (JR e), is a two

byte instruction that jumps any instructions within the

range –126 to +129 bytes from the location of this instruc-

tion. Most conditional jumps in programs are made to

locations only a few bytes away; the Jump Relative, with an

8-bit offset, exploits this fact to improve code compact-

ness and efficiency. Jump Relative, with a 16-bit offset (JR

[cc,]ee), is a four byte instruction that jumps any instruc-

tions within the range –32765 to +32770 bytes from the

location of this instruction, and Jump Relative, with a 24-bit

offset (JR [cc,] eee), is a five byte instruction that jumps any

instructions within the range –8388604 to +8388611 bytes

from the location of this instruction. By using these Jump

Relative instructions with 16-bit or 24-bit offsets allows to

write relocatable (or location independent) programs.

Call and Restart are used for calling subroutines; the

current contents of the PC are pushed onto the stack and

the effective address indicated by the instruction is loaded

Table 5-13. Program Control Group Instructions

Instruction Name Format nn (PC+d) (HL) (IX) (IY)

Call CALL cc,dst √

Complement Carry Flag CCF

Call Relative CALR cc,dst √

Decrement and Jump if Non-zero DJNZ dst √

Jump JP cc,dst √

JP dst √√ √

Jump Relative JR cc,dst √

Return RET cc

Restart RST p √

Set Carry Flag SCF

into the PC. The use of a procedure address stack in this

manner allows straightforward implementation of nested

and recursive procedures. Call, Jump, and Jump Relative

can be unconditional or based on the setting of a CPU flag.

Call Relative (CALR) instructions work just like ordinary

Call instructions, but with Relative address. An 8-bit, 16-

bit, or 24-bit offset value can be used, and that allows to call

procedure within the range of –126 to +129 bytes (8-bit

offset;CALR [cc,]e), –32765 to +32770 bytes (16-bit offset;

CALR [cc,]ee), or –8388604 to +8388611 bytes (JR [cc,]

eee) are supported. These instructions are really useful to

program relocatable programs.

Jump is available with Indirect Register mode in addition

to Direct Address mode. It can be useful for implementing

complex control structures such as dispatch tables. When

using Direct Address mode for a Jump or Call, the operand

is used as an immediate value that is loaded into the PC to

specify the address of the next instruction to be executed.

The conditional Return instruction is a companion to the

call instruction; if the condition specified in the instruction

is satisfied, it loads the PC from the stack and pops the

stack.

A special instruction, Decrement and Jump if Non-Zero

(DJNZ), implements the control part of the basic Pascal

FOR loop which can be implemented in an instruction. It

supports 8-bit, 16-bit, and 24-bit displacement.

Note that Jump Relative, Call Relative, and DJNZ instruc-

tions use modulo 216 in Native mode, and 232 in Extended

mode for address calculation. So it is possible that the

Z380 CPU can jump to an unexpected address.

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5.5.9 External Input/Output Instruction

Group

This group of instructions (Table 5-14) are used for trans-

ferring a byte, a word, or string of bytes or words between

peripheral devices and the CPU registers or memory. Byte

I/O port addresses transfer bytes on D7-D0 only. These 8-

bit peripherals in a 16-bit data bus environment must be

connected to data line D7-D0. In an 8-bit data bus environ-

ment, word I/O instructions to external I/O peripherals

should not be used; however, on-chip peripherals which is

external to the CPU core and assigned as word I/O device

can still be accessed by word I/O instructions.

The instructions for transferring a single byte (IN, OUT) can

transfer data between any 8-bit CPU register or memory

address specified in the instruction and the peripheral port

specified by the contents of the C register. The IN instruc-

tion sets the CPU flags according to the input data;

however, special instructions restricted to using the CPU

accumulator and Direct Address mode and do not affect

the CPU flags. Another variant tests an input port specified

by the contents of the C register and sets the CPU flags

without modifying CPU registers or memory.

The instructions for transferring a single word (INW, OUTW)

can transfer data between the register pair and the periph-

eral port specified by the contents of the C register. For

Word I/O, the contents of B, D, or H appear on D7-D0 and

the contents of C, E, or L appear D15-D7. These instruc-

tions do not affect the CPU flags.

Also, there are I/O instructions available which allow to

specify 16-bit absolute I/O address (with DDIR decoder

directives, a 24-bit or 32-bit address is specified) is avail-

able. These instructions do not affect the CPU flags.

The remaining instructions in this group form a powerful

and complete complement of instructions for transferring

blocks of data between I/O ports and memory. The opera-

tion of these instructions is very similar to that of the block

move instructions described earlier, with the exception

that one operand is always an I/O port whose address

remains unchanged while the address of the other oper-

and (a memory location) is incremented or decremented.In

Word mode of transfer, the counter (i.e., BC register) holds

the number of transfers, rather than number of bytes to

transfer in memory-to-memory word block transfer. Both

byte and word forms of these instructions are available.

The automatically repeating forms of these instructions are

interruptible, like memory-to-memory transfer.

The I/O addresses output on the address bus is de-

pendant on the I/O instruction, as listed in Table 2-1.

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5.5.9 External Input/Output Instruction Group (Continued)

Table 5-14. External I/O Group Instructions.

Instruction Name Format

Input IN dst,(C) dst=A, B, C, D, E, H or L

Input Accumulator IN A,(n)

Input to Word-Wide Register INW dst,(C) dst=BC, DE or HL

Input Byte from Absolute Address INAW A,(nn)

Input Word from Absolute Address INAW HL,(nn)

Input and Decrement (Byte) IND

Input and Decrement (Word) INDW

Input, Decrement, and Repeat (Byte) INDR

Input, Decrement, and Repeat (Word) INDRW

Input and Increment (Byte) INI

Input and Increment (Word) INIW

Input, Increment, and Repeat (Byte) INIR

Input, Increment, and Repeat (Word) INIRW

Output OUT (C),src src = A, B, C, D, E, H, L, or n

Output Accumulator OUT (n),A

Output from Word-Wide Register OUTW (C), src src = BC, DE, HL, or nn

Output Byte from Absolute Address OUTAW (nn),A

Output Word from Absolute Address OUTAW (nn),HL

Output and Decrement (Byte) OUTD

Output and Decrement (Word) OUTDW

Output, Decrement, and Repeat (Byte) OTDR

Output, Decrement, and Repeat (Word) OTDRW

Output and Increment (Byte) OUTI

Output and Increment (Word) OTIW

Output, Increment, and Repeat (Byte) OTIR

Output, Increment, and Repeat (Word) OTIRW

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5.5.10 Internal I/O Instruction Group

This group (Table 5-15) of instructions is used to access

on-chip I/O addressing space on the Z380 CPU. This

group consists of instructions for transferring a byte from/

to Internal I/O locations and the CPU registers or memory,

or a blocks of bytes from the memory to the same size of

Internal I/O locations for initialization purposes. These

instructions are originally assigned as newly added I/O

instructions on the Z180 MPU to access Page 0 I/O

addressing space. There is 256 Internal I/O locations, and

all of them are byte-wide. When one of these I/O instruc-

tions is executed, the Z380 MPU outputs the register

address being accessed in a pseudo transaction of two

BUSCLK durations cycle, with the address signals A31-A8

at 0. In the pseudo transactions, all bus control signals are

at their inactive state.

The instructions for transferring a single byte (IN0, OUT0)

can transfer data between any 8-bit CPU register and the

Internal I/O address specified in the instruction. The IN0

instruction sets the CPU flags according to the input data;

however, special instructions which do not have a destina-

tion in the instruction with Direct Address (IN0 (n)), do not

affect the CPU register, but alters flags accordingly. An-

other variant, the TSTIO instruction, does a logical AND to

the instruction operand with the internal I/O location speci-

fied by the C register and changes the CPU flags without

modifying CPU registers or memory.

The remaining instructions in this group form a powerful

and complete complement of instructions for transferring

blocks of data from memory to Internal I/O locations. The

operation of these instructions is very similar to that of the

block move instructions described earlier, with the excep-

tion that one operand is always an Internal I/O location

whose address also increments or decrements by one

automatically, Also, the address of the other operand (a

memory location) is incremented or decremented. Since

Internal I/O space is byte-wide, only byte forms of these

instructions are available. Automatically repeating forms

of these instructions are interruptible, like memory-to-

memory transfer.

Table 5-15. Internal I/O Instruction Group

Instruction Name Format

Input from Internal I/O Location IN0 dst,(n) dst=A, B, C, D, E, H or L

Input from Internal I/O Location(Nondestructive) IN0 (n)

Test I/O TSTIO n

Output to Internal I/O Location OUT0 (n),src src=A, B, C, D, E, H or L

Output to Internal I/O and Decrement OTDM

Output to Internal I/O and Increment OTIM

Output to Internal I/O, Decrement and Repeat OTDMR

Output to Internal I/O, Increment and Repeat OTIMR

Currently, the Z380 CPU core has the following registers as a part of the CPU core:

Interrupt Enable Register 16H

Assigned Vector Base Register 17H

Trap Register 18H

Chip Version ID Register 0FFH

Chip Version ID register returns one byte data, which

indicates the version of the CPU, or the specific implemen-

tation of the Z380 CPU based Superintegration device.

Currently, the value 00H is assigned to the Z380 MPU, and

other values are reserved.

For the other three registers, refer to Chapter 6, “Interrupt

and Trap.”

Also, the Z380 MPU has registers to control chip selects,

refresh, waits, and I/O clock divide to Internal I/O address

00H to 10H. For these register, refer to Z380 MPU Product

specification.

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5.5.11 CPU Control Group

The instructions in this group (Table 5-16) act upon the

CPU control and status registers or perform other functions

that do not fit into any of the other instruction groups. These

include two instructions used for returning from an inter-

rupt service routine. Return from Nonmaskable Interrupt

(RETN) and Return from Interrupt (RETI) are used to pop

the Program Counter from the stack and manipulate the

Interrupt Enable Flag (IEF1 and IEF2), or to signal a reset

to the Z80 peripherals family.

The Disable and Enable Interrupt instructions are used to

set/reset interrupt mask. Without a mask parameters, it

disables/enables maskable interrupt globally. With mask

data, it enables/disables interrupts selectively.

HALT and SLEEP instructions stop the CPU and waits for

an event to happen, or puts the system into the power save

mode.

Bank Test instructions reports which register file, primary

or alternate bank, is in use at the time, and reflect the status

into a flag register. For example, this instruction is useful to

implement the recursive program, which uses the alter-

nate bank to save a register for the first time, and saves

registers into memory thereafter.

Mode Test instructions reports the current mode of opera-

tion, Native/Extended, Word/Long Word, Locked or not.

This instruction can be used to switch procedures de-

pending on the mode of operation.

Load Accumulator from R or I Register instructions are

used to report current interrupt mask status. Load from/to

Load Control register instructions are used to read/write

the Status Register, set/reset control bit instructions and to

set/reset the control bits in the SR.

The No Operation instruction does nothing, and can be

used as a filler, for debugging purposes, or for timing

adjustment.

Table 5-16. CPU Control Group

Instruction Name Format

Bank Test BTEST

Disable Interrupt DI [mask]

Enable Interrupt EI [mask]

HALT HALT

Interrupt Mode Select IM p

Load Accumulator from I or R Register LD A,src

Load I or R Register from Accumulator LD dst,A

Load I Register from HL Register LD[W] HL,I

Load HL Register from I Register LD[W] HL,I

Load Control LDCTL dst,src

Mode Test MTEST

No Operation NOP

Return from Interrupt RETI

Return from Nonmaskable Interrupt RETN

Reset Control Bit RESC dst dst=LCK, LW

Set Control Bit SETC dst dst=LCK, LW, XM

Sleep SLP

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5.5.12 Decoder Directives

The Decoder Directives (Table 5-17) are a special instruc-

tions to expand the Z80 instruction set to handle the Z380’s

4 Gbytes of linear memory addressing space. For details

on this instruction, refer to Chapter 3.

Table 5-17. Decoder Directive Instructions

DDIR W Word Mode

DDIR IB,W Immediate Byte, Word Mode

DDIR IW,W Immediate Word, Word Mode

DDIR IB Immediate Byte

DDIR LW Long Word Mode

DDIR IB,LW Immediate Byte, Long Word Mode

DDIR IW,LW Immediate Word, Long Word Mode

DDIR IW Immediate Word

5.6 NOTATION AND BINARY ENCODING

The rest of this chapter consists of a detailed description

of the Z380 CPU instructions, arranged in alphabetical

order by mnemonic. This section describes the notational

conventions used in the instruction descriptions and the

binary encoding for register fields within the instruction’s

operation codes (opcodes).

The description of each instruction begins on a new page.

The instruction mnemonic and name are printed in bold

letters at the top of each page to enable the reader to easily

locate a desired description. The assembly language

syntax is then given in a single generic form that covers all

the variants of the instruction, along with a list of applicable

addressing modes. This is followed by a description of the

operation performed by the instruction in “pseudo Pascal”

fashion, a detailed description, a listing of all the flags that

are affected by the instruction, and illustrations of the

opcodes for all variants of the instruction.

Symbols. The following symbols are used to describe the

instruction set.

n An 8-bit constant

nn A 16-bit constant

d An 8-bit offset. (two’s complement)

src Source of the instruction

dst Destination of the instruction

SR Select Register

R Any register. In Word operation, any register pair.

Any 8-bit register (A, B, C, D, E, H, or L) for Byte

operation.

IR Indirect register

RX Indexed register (IX or IY) in Word operation, IXH,

IXL, IYH, or IYL for Byte operation.

SP Current Stack Pointer

cc Condition Code

[ ] Optional field

( ) Indirect Address Pointer or Direct Address

Assignment of a value is indicated by the symbol "←”. For

example,

dst ← dst + src

indicates that the source data is added to the destination

data and the result is stored in the destination location.

The symbol “↔” indicates that the source and destination

is swapping. For example,

dst ↔ src

indicates that the source data is swapped with the data in

the destination; after the operation, data at “src” is in the

“dst” location, and data in “dst “ is in the “src” location.

The notation “dst (b)” is used to refer to bit “b” of a given

location, “dst(m-n)” is used to refer to bit location m to n of

the destination. For example,

HL(7) specifies bit 7 of the destination.

and

HL(23-16) specifies bit location 23 to 16 of the HL

Flags. The F register contains the following flags followed

by symbols.

S Sign Flag

Z Zero Flag

H Half Carry Flag

P/V Parity/Overflow Flag

N Add/Subtract Flag

C Carry Flag

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5.6 NOTATION AND BINARY ENCODING (Continued)

Condition Codes. The following symbols describe the

condition codes.

Z Zero*

NZ Not Zero*

C Carry*

NC No Carry*

S Sign

NS No Sign

NV No Overflow

V Overflow

PE Parity Even

PO Parity Odd

P Positive

M Minus

*Abbreviated set

Field Encoding. For opcode binary format in the Tables,

use the following convention:

For example, to get the opcode format on the instruction

LD (IX+12h), C

First, find out the entry for “LD (XY+d),R”. That entry has

a opcode format of

11 y11 101 01 110 -r- ← d →

On the bottom of the each instruction, there are the field

encodings, if applicable. For the cases which call out “per

convention,” then use the following encoding:

r Reg

000 B

001 C

010 D

011 E

100 H

101 L

111 A

To form the opcode, first, look for the “y” field value for IX

Then find “r” field value for the C register, which is 001.

Replace “y” and “r” field with the value from the table,

replace “d” value with the real number. The results being:

76 543 210 HEX

11 011 101 DD

01 110 001 71

00 010 010 21

5.7 EXECUTION TIME

i in the execution time column indicates an I/O read

operation. The time required for a read operation is shown

in the Table 5-18 below.

o in the execution time column indicates an I/O write

operation. The time required for a write operation is shown

in the Table 5-18 below.

All entries in the table below assume no wait states. The

number of wait states per operation must be added to

these numbers.

Table 5-18 details the execution time for each instruction

encoding. All execution times are for instruction execution

only. Clock cycles required for fetch and decode are not

included because most of the time the clocks required for

these operations occur in parallel with execution of the

previous instruction(s).

r in the execution time column indicates a memory read

operation. The time required for a read operation is shown

in the Table 5-18 below.

w in the execution time column indicates a memory write

operation. The time required for a write operation is shown

in the Table 5-18 below.

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Table 5-18. Execution Time

Operation Byte Word Word Long Long Long Long Long

Sequence B W B/B W/W W/B/B B/W/B B/B/W B/B/B/B

Memory Read 3-4 3-4 5-6 5-6 7-8 7-8 7-8 9-10

Memory Write 0-1 0-1 2-3 2-3 4-5 4-5 4-5 6-7

Internal I/O Read 3-4 N/A N/A N/A N/A N/A N/A N/A

Internal I/O Write 0-1 N/A N/A N/A N/A N/A N/A N/A

1X External I/O Read 4-5 4-5 N/A N/A N/A N/A N/A N/A

1X External I/O Write 1-2 1-2 N/A N/A N/A N/A N/A N/A

2X External I/O Read 9-11 9-11 N/A N/A N/A N/A N/A N/A

2X External I/O Write 1-3 1-3 N/A N/A N/A N/A N/A N/A

4X External I/O Read 17-21 17-21 N/A N/A N/A N/A N/A N/A

4X External I/O Write 1-5 1-5 N/A N/A N/A N/A N/A N/A

6X External I/O Read 25-31 25-31 N/A N/A N/A N/A N/A N/A

6X External I/O Write 1-7 1-7 N/A N/A N/A N/A N/A N/A

8X External I/O Read 33-41 33-41 N/A N/A N/A N/A N/A N/A

8X External I/O Write 1-9 1-9 N/A N/A N/A N/A N/A N/A

Note: Units are in Clocks. “N/A” is not applicable for that particular transaction.

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ADC

ADD WITH CARRY (BYTE)

ADC A,src src = R, RX, IM, IR, X

Operation: A←A + src + C

The source operand together with the Carry flag is added to the accumulator and the sum

is stored in the accumulator. The contents of the source is unaffected. Two’s complement

addition is performed.

Flags: S: Set if the result is negative; cleared otherwise

Z: Set if the result is zero; cleared otherwise

H: Set if there is a carry from bit 3 of the result; cleared otherwise

V: Set if arithmetic overflow occurs, that is, if both operands cleared otherwise

N: Cleared

C: Set if there is a carry from the most significant bit of the result; cleared otherwise

Addressing Execute

Mode Syntax Instruction Format Time Note

R: ADC A,R 10001-r- 2

RX: ADC A,RX 11y11101 1000110w 2

IM: ADC A,n 11001110 —n— 2

IR: ADC A,(HL) 10001110 2+r

X: ADC A,(XY+d) 11y11101 10001110—d— 4+r I

Field Encodings: r: per convention

y: 0 for IX, 1 for IY

w: 0 for high byte, 1 for low byte

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ADC

ADD WITH CARRY (WORD)

ADC HL,src dst = HL

src = BC, DE, HL, SP

Operation: HL(15-0) ←HL(15-0) + src(15-0) + C

The source operand together with the Carry flag is added to the HL register and the sum is

stored in the HL register. The contents of the source are unaffected. Two’s complement

addition is performed.

Flags: S: Set if the result is negative; cleared otherwise

Z: Set if the result is zero; cleared otherwise

H: Set if there is a carry from bit 11 of the result; cleared otherwise

V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the

result is of the opposite sign; cleared otherwise

N: Cleared

C: Set if there is a carry from the most significant bit of the result; cleared otherwise

Addressing Execute

Mode Syntax Instruction Format Time Note

R: ADC HL,R 11101101 01rr1010 2

Field Encodings: rr: 00 for BC, 01 for DE, 10 for HL, 11 for SP

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ADCW

ADD WITH CARRY (WORD)

ADCW [HL,]src src = R, RX, IM, X

Operation: HL(15-0) ←HL(15-0) + src(15-0) + C

The source operand together with the Carry flag is added to the HL register and the sum is

stored in the HL register. The contents of the source are unaffected. Two’s complement

addition is performed.

Flags: S: Set if the result is negative; cleared otherwise

Z: Set if the result is zero; cleared otherwise

H: Set if there is a carry from bit 11 of the result; cleared otherwise

V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the

result is of the opposite sign; cleared otherwise

N: Cleared

C: Set if there is a carry from the most significant bit of the result; cleared otherwise

Addressing Execute

Mode Syntax Instruction Format Time Note

R: ADCW [HL,]R 11101101 100011rr 2

RX: ADCW [HL,]RX 11y11101 10001111 2

IM: ADCW [HL,]nn 11101101 10001110 -n(low)- n(high)- 2

X: ADCW [HL,](XY+d) 11y11101 11001110 ——d— 4+r I

Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL

y: 0 for IX, 1 for IY

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DC-8297-03

ADD

ADD (BYTE)

ADD A,src src = R, RX, IM, IR, X

Operation: A←A + src

The source operand is added to the accumulator and the sum is stored in the accumulator.

The contents of the source are unaffected. Two’s complement addition is performed.

Flags: S: Set if the result is negative; cleared otherwise

Z: Set if the result is zero; cleared otherwise

H: Set if there is a carry from bit 3 of the result; cleared otherwise

V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the

result is of the opposite sign; cleared otherwise

N: Cleared

C: Set if there is a carry from the most significant bit of the result; cleared otherwise

Addressing Execute

Mode Syntax Instruction Format Time Note

R: ADD A,R 10000-r- 2

RX: ADD A,RX 11y11101 1000010w 2

IM: ADD A,n 11000110 ——n— 2

IR: ADD A,(HL) 10000110 2+r

X: ADD A,(XY+d) 11y11101 10000110 ——d— 4+r I

Field Encodings: r: per convention

y: 0 for IX, 1 for IY

w: 0 for high byte, 1 for low byte

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ADD

ADD (WORD)

ADD dst,src dst = HL; src = BC, DE, HL, SP, DA

dst = IX; src = BC, DE, IX, SP

dst = IY; src = BC, DE, IY, SP

Operation: If (XM) then begin

dst(31-0) ←dst(31-0) + src(31-0)

end

else begin

dst(15-0) ←dst(15-0) + src(15-0)

end

The source operand is added to the destination and the sum is stored in the destination. The

contents of the source are unaffected. Two’s complement addition is performed. Note that

the length of the operand is controlled by the Extended/Native mode selection, which is

consistent with the manipulation of an address by the instruction.

Flags: S: Unaffected

Z: Unaffected

H: Set if there is a carry from bit 11 of the result; cleared otherwise

V: Unaffected

N: Cleared

C: Set if there is a carry from the most significant bit of the result; cleared otherwise

Addressing Execute

Mode Syntax Instruction Format Time Note

R: ADD HL,R 00rr1001 2 X

RX: ADD XY,R 11y11101 00rr1001 2 X

DA: ADD HL,(nn) 11101101 11000110 -n(low)- n(high)- 2+r I, X

Field Encodings: rr: 00 for BC, 01 for DE, 10 for register to itself, 11 for SP

y: 0 for IX, 1 for IY

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ADD

ADD TO STACK POINTER (WORD)

ADD SP,srcsrc = IM

Operation: if (XM) then begin

SP(31-0) ←SP(31-0) + src(31-0)

end

else begin

SP(15-0) ←SP(15-0) + src(15-0)

end

The source operand is added to the SP register and the sum is stored in the SP register. This

has the effect of allocating or allocating space on the stack. Two’s complement addition is

performed.

Flags: S: Unaffected

Z: Unaffected

H: Set if there is a carry from bit 11 of the result; cleared otherwise

V: Unaffected

N: Cleared

C: Set if there is a carry from the most significant bit of the result; cleared otherwise

Addressing Execute

Mode Syntax Instruction Format Time Note

IM: ADD SP,nn 11101101 10000010 -n(low)- -n(high) 2 I, X

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ADDW

ADD (WORD)

ADDW [HL,]src src = R, RX, IM, X

Operation: HL(15-0) ←HL(15-0) + src(15-0)

The source operand is added to the HL register and the sum is stored in the HL register. The

contents of the source are unaffected. Two’s complement addition is performed.

Flags: S: Set if the result is negative; cleared otherwise

Z: Set if the result is zero; cleared otherwise

H: Set if there is a carry from bit 11 of the result; cleared otherwise

V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the

result is of the opposite sign; cleared otherwise

N: Cleared

C: Set if there is a carry from the most significant bit of the result; cleared otherwise

Addressing Execute

Mode Syntax Instruction Format Time Note

R: ADDW [HL,]R 11101101 100001rr 2

RX: ADDW [HL,]RX 11y11101 10000111 2

IM: ADDW [HL,]nn 11101101 10000110 -n(low)- n(high)- 2

X: ADDW [HL,](XY+d) 11y11101 11000110 —d— 4+r I

Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL

y: 0 for IX, 1 for IY

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AND

AND (BYTE)

AND [A,]src src = R, RX, IM, IR, X

Operation:A←A AND src

A logical AND operation is performed between the corresponding bits of the source operand

and the accumulator and the result is stored in the accumulator. A 1 is stored wherever the

corresponding bits in the two operands are both 1s; otherwise a 0 is stored. The contents

of the source are unaffected.

Flags: S: Set if the most significant bit of the result is set; cleared otherwise

Z: Set if all bits of the result are zero; cleared otherwise

H: Set

P: Set if the parity is even; cleared otherwise

N: Cleared

C: Cleared

Addressing Execute

Mode Syntax Instruction Format Time Note

R: AND [A,]R 10100-r- 2

RX: AND [A,]RX 11y11101 1010010w 2

IM: AND [A,]n 11100110 ——n— 2

IR: AND [A,](HL) 10100110 2+r

X: AND [A,](XY+d) 11y11101 10100110——d— 4+r I

Field Encodings: r: per convention

y: 0 for IX, 1 for IY

w: 0 for high byte, 1 for low byte

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ANDW

AND (WORD)

ANDW [HL,]src src = R, RX, IM, X

Operation: HL(15-0) ←HL(15-0) AND src(15-0)

A logical AND operation is performed between the corresponding bits of the source operand

and the HL register and the result is stored in the HL register. A 1 is stored wherever the

corresponding bits in the two operands are both 1s; otherwise a 0 is stored. The contents

of the source are unaffected.

Flags: S: Set if the most significant bit of the result is set; cleared otherwise

Z: Set if all bits of the result are zero; cleared otherwise

H: Set

P: Set if the parity is even; cleared otherwise

N: Cleared

C: Cleared

Addressing Execute

Mode Syntax Instruction Format Time Note

R: ANDW [HL,]R 11101101 101001rr 2

RX: ANDW [HL,]RX 11y11101 10100111 2

IM: ANDW [HL,]nn 1110110110100110 n(low)- n(high)- 2

X: ANDW [HL,](XY+d) 11y11101 11100110 ——d— 4+r I

Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL

y: 0 for IX, 1 for IY

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BIT

BIT TEST

BIT b,dst dst = R, IR, X

Operation: Z←NOT dst(b)

The specified bit b within the destination operand is tested, and the Zero flag is set to 1 if

the specified bit is 0, otherwise the Zero flag is cleared to 0. The contents of the destination

are unaffected. The bit to be tested is specified by a 3-bit field in the instruction; this field

contains the binary encoding for the bit number to be tested. The bit number b must be

between 0 and 7.

Flags: S: Unaffected

Z: Set if the specified bit is zero; cleared otherwise

H: Set

V: Unaffected

N: Cleared

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: BIT b,R 11001011 01bbb-r- 2

IR: BIT b,(HL) 11001011 01bbb110 2+r

X: BIT b,(XY+d) 11y11101 11001011 ——d— 01bbb110 4+r I

Field Encodings: r: per convention

y: 0 for IX, 1 for IY

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BTEST

BANK TEST

BTEST

Operation: S←SR(16)

Z←SR(24)

V←SR(0)

C←SR(8)

The Alternate Register bits in the Select Register (SR) are transferred to the flags. This allows

the program to determine the state of the machine.

Flags: S: Set if the alternate bank IX is in use; cleared otherwise

Z: Set if the alternate bank IY is in use; cleared otherwise

H: Unaffected

V: Set if the alternate bank AF is in use; cleared otherwise

N: Unaffected

C: Set if the alternate bank of BC, DE and HL is in use; cleared otherwise

Addressing Execute

Mode Syntax Instruction Format Time Note

BTEST 11101101 11001111 2

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CALL

CALL [cc,]dst dst = DA

Operation: if (cc is TRUE) then begin

if (XM) then begin

SP ←SP - 4

(SP) ←PC(7-0)

(SP+1) ←PC(15-8)

(SP+2) ←PC(23-16)

(SP+3) ←PC(31-24)

PC(31-0) ←dst(31-0)

else begin

SP ←SP - 2

(SP) ←PC(7-0)

(SP+1) ←PC(15-8)

PC(15-0) ←dst(15-0)

end

A conditional Call transfers program control to the destination address if the setting of a

selected flag satisfies the condition code “cc” specified in the instruction; an Unconditional

Call always transfers control to the destination address. The current contents of the Program

Counter (PC) are pushed onto the top of the stack; the PC value used is the address of the

first instruction byte following the Call instruction. The destination address is then loaded

into the PC and points to the first instruction of the called procedure. At the end of a

procedure a Return instruction (RET) can be used to return to the original program.

Each of the Zero, Carry, Sign, and Overflow Flags can be individually tested and a call

performed conditionally on the setting of the flag.

The operand is not enclosed in parentheses with the CALL instruction.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

DA: CALL CC,addr 11-cc100 -a(low)- -a(high) note I, X

CALL addr 11001101 -a(low)- -a(high) 4+w I, X

Field Encodings: cc: 000 for NZ, 001 for Z, 010 for NC, 011 for C,

100 for PO or NV, 101 for PE or V, 110 for P or NS, 111 for M or S

Note: 2 if CC is false, 4+w if CC is true

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CALR

CALL RELATIVE

CALR [cc,]dst dst = RA

Operation: if (cc is true) then begin

dst ←SIGN EXTEND dst

if (XM) then begin

SP ←SP - 4

(SP) ←PC(7-0)

(SP+1) ←PC(15-8)

(SP+2) ←PC(23-16)

(SP+3) ←PC(31-24)

PC(31-0) ←PC(31-0) + dst(31-0)

end

else begin

SP ←SP - 2

(SP) ←PC(7-0)

(SP+1) ←PC(15-8)

PC(15-0) ←PC(15-0) + dst(15-0)

end

A conditional Call transfers program control to the destination address if the setting of a

selected flag satisfies the condition code “cc” specified in the instruction; an unconditional

call always transfers control to the destination address. The current contents of the Program

Counter (PC) are pushed onto the top of the stack; the PC value used is the address of the

first instruction byte following the Call instruction. The destination address is then loaded into

the PC and points to the first instruction of the called procedure. At the end of a procedure

a RETurn instruction is used to return to the original program. These instructions employ

either an 8-bit, 16-bit, or 24-bit signed, two’s complement displacement from the PC to

permit calls within the range of -126 to +129 bytes, –32,765 to +32,770 bytes or –8,388,604

to +8,388,611 bytes from the location of this instruction.

Each of the Zero, Carry, Sign, and Overflow flags can be individually tested and a call

performed conditionally on the setting of the flag.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

RA: CALR CC,addr 11101101 11-cc100 —disp— note X

CALR addr 11101101 11001101 —disp— 4+w X

CALR CC,addr 11011101 11-cc100 -d(low)- -d(high) note X

CALR addr 11011101 11001101 -d(low)- -d(high) 4+w X

CALR CC,addr 11111101 11-cc100 -d(low)- -d(mid)- -d(high) note X

CALR addr 11111101 11001101 -d(low)- -d(mid) -d(high) 4+w X

Field Encodings: cc: 000 for NZ, 001 for Z, 010 for NC, 011 for C, 100 for PO or NV, 101 for PE or V,

110 for P or NS, 111 for M or S

Note: 2 if CC is false, 4+w if CC is true

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CCF

COMPLEMENT CARRY FLAG

CCF

Operation: C←NOT C

The Carry flag is inverted.

Flags: S: Unaffected

Z: Unaffected

H: The previous state of the Carry flag

V: Unaffected

N: Cleared

C: Set if the Carry flag was clear before the operation; cleared otherwise

Addressing Execute

Mode Syntax Instruction Format Time Note

CCF 00111111 2

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ZILOG

COMPARE (BYTE)

CP [A,]src src = R, RX, IM, IR, X

Operation: A – src

The source operand is compared with the accumulator and the flags are set accordingly.

The contents of the accumulator and the source are unaffected. Two’s complement

subtraction is performed.

Flags: S: Set if the result is negative; cleared otherwise

Z: Set if the result is zero; cleared otherwise

H: Set if there is a borrow from bit 4 of the result; cleared otherwise

V: Set if arithmetic overflow occurs, that is, if the operands are of different signs and the

result is of the same sign as the source; cleared otherwise

N: Set

C: Set if there is a borrow from the most significant bit of the result; cleared otherwise

Addressing Execute

Mode Syntax Instruction Format Time Note

R: CP [A,]R 10111-r- 2

RX: CP [A,]RX 11y11101 1011110w 2

IM: CP [A,]n 11111110 ——n— 2

IR: CP [A,](HL) 10111110 2+r

X: CP [A,](XY+d) 11y11101 10111110 ——d— 4+r I

Field Encodings: r: per convention

y: 0 for IX, 1 for IY

w: 0 for high byte, 1 for low byte

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CPW

COMPARE (WORD)

CPW [HL,]src src = R, RX, IM, X

Operation: HL(15-0) – src(15-0)

The source operand is compared with the HL register and the flags are set accordingly. The

contents of the HL register and the source are unaffected. Two’s complement subtraction

is performed.

Flags: S: Set if the result is negative; cleared otherwise

Z: Set if the result is zero; cleared otherwise

H: Set if there is a borrow from bit 12 of the result; cleared otherwise

V: Set if arithmetic overflow occurs, that is, if the operands are of different signs and the

result is of the same sign as the source; cleared otherwise

N: Set

C: Set if there is a borrow from the most significant bit of the result; cleared otherwise

Addressing Execute

Mode Syntax Instruction Format Time Note

R: CPW [HL,]R 11101101 101111rr 2

RX: CPW [HL,]RX 11y11101 10111111 2

IM: CPW [HL,]nn 11101101 10111110 -n(low)- n(high)- 2

X: CPW [HL,](XY+d) 11y11101 11111110 ——d— 4+r I

Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL

y: 0 for IX, 1 for IY

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CPD

COMPARE AND DECREMENT (BYTE)

CPD

Operation: A - (HL)

if (XM) then begin

HL(31-0) ←HL(31-0) - 1

end

else begin

HL(15-0) ←HL(15-0) - 1

end

BC(15-0) ←BC(15-0) - 1

This instruction is used for searching strings of byte data. The byte of data at the location

addressed by the HL register is compared with the contents of the accumulator and the Sign

and Zero flags are set to reflect the result of the comparison. The contents of the accumulator

and the memory bytes are unaffected. Two’s complement subtraction is performed. Next

the HL register is decremented by one, thus moving the pointer to the previous element in

the string. The BC register, used as a counter, is then decremented by one.

Flags: S: Set if the result is negative; cleared otherwise

Z: Set if the result is zero, indicating that the contents of the accumulator and the memory

byte are equal; cleared otherwise

H: Set if there is a borrow from bit 4 of the result; cleared otherwise

V: Set if the result of decrementing BC is not equal to zero; cleared otherwise

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

CPD 11101101 10101001 3+r X

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CPDR

COMPARE, DECREMENT AND REPEAT (BYTE)

CPDR

Operation: Repeat until (BC=0 OR match) begin

A - (HL)

if (XM) then begin

HL(31-0) ←HL(31-0) - 1

end

else begin

HL(15-0) ←HL(15-0) - 1

end

BC(15-0) ←BC(15-0) - 1

end

This instruction is used for searching strings of byte data. The bytes of data starting at the

location addressed by the HL register are compared with the contents of the accumulator

until either an exact match is found or the string length is exhausted becuase the BC register

has decremented to zero. The Sign and Zero flags are set to reflect the result of the

comparison. The contents of the accumulator and the memory bytes are unaffected.Two’s

complement subtraction is performed.

After each comparison, the HL register is decremented by one, thus moving the pointer to

the previous element in the string.

The BC register, used as a counter, is then decremented by one. If the result of decrementing

the BC register is not zero and no match has been found, the process is repeated. If the

contents of the BC register are zero at the start of this instruction, a string length of 65,536

is indicated.

This instruction can be interrupted after each execution of the basic operation. The PC value

at the start of this instruction is pushed onto the stack so that the instruction can be resumed.

Flags: S: Set if the last result is negative; cleared otherwise

Z: Set if the last result is zero, indicating a match; cleared otherwise

H: Set if there is a borrow from bit 4 of the last result; cleared otherwise

V: Set if the result of decrementing BC is not equal to zero; cleared otherwise

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

CPDR 11101101 10111001 (3+r)n X

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CPI

COMPARE AND INCREMENT (BYTE)

CPI

Operation: A - (HL)

if (XM) then begin

HL(31-0) ←HL(31-0) + 1

end

else begin

HL(15-0) ←HL(15-0) + 1

end

BC(15-0) ←BC(15-0) - 1

This instruction is used for searching strings of byte data. The byte of data at the location

addressed by the HL register is compared with the contents of the accumulator and the Sign

and Zero flags are set to reflect the result of the comparison. The contents of the accumulator

and the memory bytes are unaffected. Two’s complement subtraction is performed. Next the

HL register is incremented by one, thus moving the pointer to the next element in the string.

The BC register, used as a counter, is then decremented by one.

Flags: S: Set if the result is negative; cleared otherwise

Z: Set if the result is zero, indicating that the contents of the accumulator and the memory

byte are equal; cleared otherwise

H: Set if there is a borrow from bit 4 of the result; cleared otherwise

V: Set if the result of decrementing BC is not equal to zero; cleared otherwise

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

CPI 11101101 10100001 3+r X

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CPIR

COMPARE, INCREMENT AND REPEAT (BYTE)

CPIR

Operation: Repeat until (BC=0 OR match) begin

A - (HL)

if (XM) then begin

HL(31-0) ←HL(31-0) + 1

end

else begin

HL(15-0) ←HL(15-0) + 1

end

BC(15-0) ←BC(15-0) - 1

end

This instruction is used for searching strings of byte data. The bytes of data starting at the

location addressed by the HL register are compared with the contents of the accumulator

until either an exact match is found or the string length is exhausted becuase the BC register

has decremented to zero. The Sign and Zero flags are set to reflect the result of the

comparison. The contents of the accumulator and the memory bytes are unaffected.

Two’s complement subtraction is performed.

After each comparison, the HL register is incremented by one, thus moving the pointer to

the next element in the string. The BC register, used as a counter, is then decremented by

one. If the result of decrementing the BC register is not zero and no match has been found,

the process is repeated. If the contents of the BC register are zero at the start of this

instruction, a string length of 65,536 is indicated.

This instruction can be interrupted after each execution of the basic operation. The PC value

at the start of this instruction is pushed onto the stack so that the instruction can be resumed.

Flags: S: Set if the last result is negative; cleared otherwise

Z: Set if the last result is zero, indicating a match; cleared otherwise

H: Set if there is a borrow from bit 4 of the last result; cleared otherwise

V: Set if the result of decrementing BC is not equal to zero; cleared otherwise

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

CPIR 11101101 10110001 (3+r)n X

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CPL

COMPLEMENT ACCUMULATOR

CPL [A]

Operation: A←NOT A

The contents of the accumulator are complemented (one's complement); all 1s are changed

to 0 and vice-versa.

Flags: S: Unaffected

Z: Unaffected

H: Set

V: Unaffected

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

CPL [A] 00101111 2

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CPLW

COMPLEMENT HL REGISTER (WORD)

CPLW [HL]

Operation: HL(15-0) ←NOT HL(15-0)

The contents of the HL register are complemented (ones complement); all 1s are changed

to 0 and vice-versa.

Flags: S: Unaffected

Z: Unaffected

H: Set

V: Unaffected

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

CPLW [HL] 11011101 00101111 2

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DAA

DECIMAL ADJUST ACCUMULATOR

DAA

Operation: A←Decimal Adjust A

The accumulator is adjusted to form two 4-bit BCD digits following a binary, two’s

complement addition or subtraction on two BCD-encoded bytes. The table below indicates

the operation performed for addition (ADD, ADC, INC) or subtraction (SUB, SBC, DEC,

NEG).

C Hex Value H Hex Value Number C H

Before Upper Digit Before Lower Digit Added After After

Operation DAA (Bits 7-4) DAA (Bits 3-0) to Byte DAA DAA

0 0-9 0 0-9 00 0 0

0 0-8 0 A-F 06 0 1

ADD 0 0-9 1 0-3 06 0 0

ADC 0 A-F 0 0-9 60 1 0

INC 0 9-F 0 A-F 66 1 1

(N=0) 0 A-F 1 0-3 66 1 0

1 0-2 0 0-9 60 1 0

1 0-2 0 A-F 66 1 1

1 0-3 1 0-3 66 1 0

SUB

SBC 0 0-9 0 0-9 00 0 0

DEC 0 0-8 1 6-F FA 0 1

NEG 1 7-F 0 0-9 A0 1 0

(N=1) 1 6-F 1 6-F 9A 1 1

Flags: S: Set if the most significant bit of the result is set; cleared otherwise

Z: Set if the result is zero; cleared otherwise

H: See table above

P: Set if the parity of the result is even; cleared otherwise

N: Not affected

C: See table above

Addressing Execute

Mode Syntax Instruction Format Time Note

DAA 00100111 3

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DDIR

DECODER DIRECTIVE

DDIR modemode = W or LW, IB or IW

Operation: None, decoder directive only

This is not an instruction, but rather a directive to the instruction decoder.

The instruction decoder may be directed to fetch an additional byte or word of immediate

data or address with the instruction, as well as tagging the instruction for execution in either

Word or Long Word mode. All eight combinations of the two options are supported, as shown

in the encoding below. Instructions which do not support decoder directives are assembled

by the instruction decoder as if the decoder directive were not present.

The IB decoder directive causes the decoder to fetch an additional byte immediately after

the existing immediate data or direct address, and in front of any trailing opcode bytes (with

instructions starting with DD-CB or FD-CB, for example).

Likewise, the IW decoder directive causes the decoder to fetch an additional word

immediately after the existing immediate data or direct address, and in front of any trailing

opcode bytes.

Byte ordering within the instruction follows the usual convention; least significant byte first,

followed by more significant bytes. More-significant immediate data or direct address bytes

not specified in the instruction are taken as all zeros by the processor.

The W decoder directive causes the instruction decoder to tag the instruction for execution

in Word mode. This is useful while the Long Word (LW) bit in the Select Register (SR) is set,

but 16-bit data manipulation is required for this instruction.

The LW decoder directive causes the instruction decoder to tag the instruction for execution

in Long Word mode. This is useful while the LW bit in the SR is cleared, but 32-bit data

manipulation is required for this instruction.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

DDIR mode 11w11101 110000im 0

Field Encodings: wim: 000 W Word mode

001 IB,W Immediate byte, Word mode

010 IW,W Immediate word, Word mode

011 IB Immediate byte

100 LW Long Word mode

101 IB,LW Immediate byte, Long Word mode

110 IW,LW Immediate word, Long Word mode

111 IW Immediate word

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DEC

DECREMENT (BYTE)

DEC dst dst = R, RX, IR, X

Operation: dst ←dst – 1

The destination operand is decremented by one and the result is stored in the destination.

Two’s complement subtraction is performed.

Flags: S: Set if the result is negative; cleared otherwise

Z: Set if the result is zero; cleared otherwise

H: Set if there is a borrow from bit 4 of the result; cleared otherwise

V: Set if arithmetic overflow occurs, that is, if the destination was 80H; cleared otherwise

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: DEC R 00-r-101 note

RX: DEC RX 11y11101 0010w101 2

IR: DEC (HL) 00110101 2+r+w

X: DEC (XY+d) 11y11101 00110101 ——d— 4+r+w I

Field Encodings: r: per convention

y: 0 for IX, 1 for IY

w: 0 for high byte, 1 for low byte

Note: 2 for accumulator, 3 for any other register

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DEC[W]

DECREMENT (WORD)

DEC[W] dstdst = R, RX

Operation: if (XM) then begin

dst(31-0) ←dst(31-0) - 1

end

else begin

dst(15-0) ←dst(15-0) - 1

end

The destination operand is decremented by one and the result is stored in the destination.

Two’s complement subtraction is performed. Note that the length of the operand is

controlled by the Extended/Native mode selection, which is consistent with the manipulation

of an address by the instruction.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: DEC[W] R 00rr1011 2 X

RX: DEC[W] RX 11y11101 00101011 2 X

Field Encodings: rr: 00 for BC, 01 for DE, 10 for HL, 11 for SP

y: 0 for IX, 1 for IY

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ZILOG

DISABLE INTERRUPTS

DI [n]

Operation: if (n is present) then begin

for i=1 to 4 begin

if (n(i) = 1) then begin

IER(i-1) ←0

end

if (n(0) = 1) then begin

SR(5) ←0

end

else begin

SR(5) ←0

end

If an argument is present, disable the selected interrupts by clearing the appropriate enable

bits in the Interrupt Enable Register, and then clear the Interrupt Enable Flag (IEF1) in the

Select Register (SR) if the least-significant bit of the argument is set, disabling maskable

interrupts. Bits 7-5 of the argument are ignored.

If no argument is present, IEF1 in the SR is set to 0, disabling maskable interrupts.

Note that during execution of this instruction the maskable interrupts are not sampled.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

DI 11110011 2

DI n 11011101 11110011 —n—— 2

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DC-8297-03

DIVUW

DIVIDE UNSIGNED (WORD)

DIVUW [HL,]src src = R, RX, IM, X

Operation: HL(15-0) ←HL / src

HL(31-16) ←remainder

The contents of the the HL register (dividend) are divided by the source operand (divisor)

and the quotient is stored in the lower word of the HL register; the remainder is stored in the

upper word of the HL register. The contents of the source are unaffected. Both operands are

treated as unsigned, binary integers. There are three possible outcomes of the DIVUW

instruction, depending on the division and the resulting quotient:

Case 1: If the quotient is less than 65536, then the quotient is left in the HL register, the

Overflow and Sign flags are cleared to 0, and the Zero flag is set according to the value of

the quotient.

Case 2: If the divisor is zero, the HL register is unchanged, the Zero and Overflow flags are

set to 1, and the Sign flag is cleared to 0.

Case 3: If the quotient is greater than or equal to 65536, the HL register is unchanged, the

Overflow flag is set to 1, and the Sign and Zero flags are cleared to 0.

Flags: S: Cleared

Z: Set if the quotient or divisor is zero; cleared otherwise

H: Unaffected

V: Set if the divisor is zero or if the computed quotient is greater than or equal to 65536;

cleared otherwise

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: DIVUW [HL,]R 11101101 11001011 101110rr 20

RX: DIVUW [HL,]RX 11101101 11001011 1011110y 20

IM: DIVUW [HL,]nn 11101101 11001011 10111111 -n(low)- -n(high) 20

X: DIVUW [HL,](XY+d) 11y11101 11001011 ——d— 10111010 22+r I

Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL

y: 0 for IX, 1 for IY

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ZILOG

DJNZ

DECREMENT AND JUMP IF NON-ZERO

DJNZ dst dst = RA

Operation: B←B-1

If (B <> 0) then begin

dst ←SIGN EXTEND dst

if (XM) then begin

PC(31-0) ←PC(31-0) + dst(31-0)

end

else begin

PC(15-0) ←PC(15-0) + dst(15-0)

end

The B register is decremented by one. If the result is non-zero, then the destination address

is calculated and then loaded into the Program Counter (PC). Control then passes to the

instruction whose address is pointed to by the PC. When the B register reaches zero, control

falls through to the instruction following DJNZ. This instruction provides a simple method of

loop control.

The destination address is calculated using Relative addressing. The displacement in the

instruction is added to the PC; the PC value used is the address of the instruction following

the DJNZ instruction.

These instructions employ either an 8-bit, 16-bit, or 24-bit signed, two’s complement

displacement from the PC to permit jumps within a range of -126 to +129 bytes, -32,765 to

+32,770 bytes, or -8,388,604 to +8,388,611 bytes from the location of this instruction.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

RA: DJNZ addr 00010000 —disp— note X

DJNZ addr 11011101 00010000 -d(low)- -d(high) note X

DJNZ addr 11111101 00010000 -d(low)- -d(mid)- -d(high) note X

Note: 3 if branch not taken, 4 if branch taken

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ENABLE INTERRUPTS

EI [n]

Operation: if (n is present) then begin

for i=1 to 4 begin

if (n(i) = 1) then begin

IER(i-1) ←1

end

if (n(0) = 1) then begin

SR(5) ←1

end

else begin

SR(5) ←1

end

If an argument is present, enable the selected interrupts by setting the appropriate enable

bits in the Interrupt Enable Register, and then set the Interrupt Enable Flag (IEF1) in the

Select Register (SR) if the least-significant bit of the argument is set, enabling maskable

interrupts. Bits 7-5 of the argument are ignored.

If no argument is present, IEF1 in the SR is set to 1, enabling maskable interrupts.

Note that during the execution of this instruction and the following instruction, maskable

interrupts are not sampled.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

EI 11111011 2

EI n 11011101 11111011 —n—— 2

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ZILOG

EXCHANGE ACCUMULATOR/FLAG WITH ALTERNATE BANK

EX AF,AF’

Operation: SR(0) ←NOT SR(0)

Bit 0 of the Select Register (SR), which controls the selection of primary or alternate bank

for the accumulator and flag register, is complemented, thus effectively exchanging the

accumulator and flag registers between the two banks.

Flags: S: Value in F’

Z: Value in F’

H: Value in F’

V: Value in F’

N: Value in F’

C: Value in F’

Addressing Execute

Mode Syntax Instruction Format Time Note

EX AF,AF’ 00001000 3

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EXCHANGE ADDRESSING REGISTER WITH TOP OF STACK

EX (SP),dst dst = HL, IX, IY

Operation: if (LW) then begin

(SP+3) ↔dst(31-24)

(SP+2) ↔dst(23-16)

end

(SP+1) ↔dst(15-8)

(SP) ↔dst(7-0)

The contents of the destination register are exchanged with the top of the stack. In Long

Word mode this exchange is two words; otherwise it is one word.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: EX (SP),HL 11100011 3+r+w L

EX (SP),XY 11y11101 11100011 3+r+w L

Field Encodings: y: 0 for IX, 1 for IY

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ZILOG

EXCHANGE REGISTER (WORD)

EX dst,src dst = R, RX

src = R, RX

Operation: if (LW) then begin

dst(31-0) ↔src(31-0)

end

else begin

dst(15-0) ↔src(15-0)

end

The contents of the destination are exchanged with the contents of the source.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: EX BC,DE 11101101 00000101 3 L

EX BC,HL 11101101 00001101 3 L

EX DE,HL 11101011 3 L

RX: EX R,RX 11101101 00rry011 3 L

EX IX,IY 11101101 00101011 3 L

Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL

y: 0 for IX, 1 for IY

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DC-8297-03

EXCHANGE REGISTER WITH ALTERNATE REGISTER (BYTE)

EX dst,src src = R

Operation: dst ↔src

The contents of the destination are exchanged with the contents of the source, where the

destination is a register in the primary bank and the source is the corresponding register in

the alternate bank

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: EX R,R’ 11001011 00110-r- 3

Field Encoding: r: per convention

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ZILOG

EXCHANGE REGISTER WITH ALTERNATE REGISTER (WORD)

EX dst,src src = R, RX

Operation: if (LW) then begin

dst(31-0) ↔src(31-0)

end

else begin

dst(15-0) ↔src(15-0)

end

The contents of the destination are exchanged with the contents of the source, where the

destination is a word register in the primary bank and the source is the corresponding word

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: EX R,R’ 11101101 11001011 001100rr 3 L

RX: EX RX,RX’ 11101101 11001011 0011010y 3 L

Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL

y: 0 for IX, 1 for IY

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DC-8297-03

EXCHANGE WITH ACCUMULATOR

EX A,src src = R, IR

Operation: dst ↔src

The contents of the accumulator are exchanged with the contents of the source.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: EX A,R 11101101 00-r-111 3

IR: EX A,(HL) 11101101 00110111 3+r+w

Field Encodings: r: per convention

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ZILOG

EXALL

EXCHANGE ALL REGISTERS WITH ALTERNATE BANK

EXALL

Operation: SR(24) ←NOT SR(24)

SR(16) ←NOT SR(16)

SR(8) ←NOT SR(8)

Bits 8, 16, and 24 of the Select Register (SR), which control the selection of primary or

alternate bank for the BC, DE, HL, IX, and IY registers, are complemented, thus effectively

exchanging the BC, DE, HL, IX, and IY registers between the two banks.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

EXALL 11101101 11011001 3

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EXTS

EXTEND SIGN (BYTE)

EXTS [A]

Operation: L←A

if (A(7)=0) then begin

H ¨ 00h

if (LW) then begin

HL(31-16) ←0000h

end

else begin

H ¨ FFh

if (LW) then begin

HL(31-16) ←FFFFh

end

The contents of the accumulator, considered as a signed, two’s complement integer, are

sign-extended to 16 bits and the result is stored in the HL register. The contents of the

accumulator are unaffected. This instruction is useful for conversion of short signed

operands into longer signed operands.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

EXTS [A] 11101101 01100101 3 L

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ZILOG

EXTSW

EXTEND SIGN (WORD)

EXTSW [HL]

Operation: If (HL(15)=0) then begin

HL(31-16) ←0000h

end

else begin

HL(31-16) ←FFFFh

end

The contents of the low word of the HL register, considered as a signed, two's complement

integer, are sign-extended to 32 bits in the HL register. This instruction is useful for

conversion of 16-bit signed operands into 32-bit signed operands.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

EXTSW [HL] 11101101 01110101 3

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EXX

EXCHANGE REGISTERS WITH ALTERNATE BANK

EXX

Operation: SR(8) ←NOT SR(8)

Bit 8 of the Select Register (SR), which controls the selection of primary or alternate bank

for the BC, DE, and HL registers, is complemented, thus effectively exchanging the BC, DE,

and HL registers between the two banks.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

EXX 11011001 3

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ZILOG

EXXX

EXCHANGE IX REGISTER WITH ALTERNATE BANK

EXXX

Operation: SR(16) ←NOT SR(16)

Bit 16 of the Select Register (SR), which controls the selection of primary or alternate bank

for the IX register, is complemented, thus effectively exchanging the IX register between the

two banks.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

EXXX 11011101 11011001 3

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EXXY

EXCHANGE IY REGISTER WITH ALTERNATE BANK

EXXY

Operation: SR(24) ←NOT SR(24)

Bit 24 of the Select Register (SR), which controls the selection of primary or alternate bank

for the IY register, is complemented, thus effectively exchanging the IY register between the

two banks.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

EXXY 11111101 11011001 3

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ZILOG

HALT

Operation: CPU Halts

The CPU operation is suspended until either an interrupt request or reset request is

received. This instruction is used to synchronize the CPU with external events, preserving

its state until an interrupt or reset request is accepted. After an interrupt is serviced, the

instruction following HALT is executed. While the CPU is halted, memory refresh cycles still

occur, and bus requests are honored. When this instruction is executed the signal /HALT

is asserted and remains asserted until an interrupt or reset request is accepted.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

HALT 01110110 2

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DC-8297-03

INTERRUPT MODE SELECT

IM p p = 0, 1, 2, 3

Operation: SR(4-3) ← p

The interrupt mode of operation is set to one of four modes. (See Chapter 6 for a description

of the various modes for responding to interrupts). The current interrupt mode can be read

from the Select Register (SR).

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

IM p 11101101 010pp110 4

Field Encodings: pp: 00 for Mode 0, 01 for Mode 3, 10 for Mode 1, 11 for Mode 2

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ZILOG

INPUT (BYTE)

IN dst,(C) dst = R

Operation: dst ←(C)

The byte of data from the selected peripheral is loaded into the destination register. During

the I/O transaction, the contents of the 32-bit BC register are placed on the address bus.

Flags: S: Set if the input data is negative; cleared otherwise

Z: Set if the input data is zero; cleared otherwise

H: Cleared

P: Set if the input data has even parity; cleared otherwise

N: Cleared

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: IN R,(C) 11101101 01-r-000 2+i

Field Encodings: r: per convention

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DC-8297-03

INW

INPUT (WORD)

INW dst,(C) dst = R

Operation: dst(15-0) ←(C)

The word of data from the selected peripheral is loaded into the destination register. During

the I/O transaction, the contents of the 32-bit BC register are placed on the address bus.

Flags: S: Set if the input data is negative; cleared otherwise

Z: Set if the input data is zero; cleared otherwise

H: Cleared

P: Set if the input data has even parity; cleared otherwise

N: Cleared

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: INW R,(C) 11011101 01rrr000 2+i

Field Encodings: rrr: 000 for BC, 010 for DE, 111 for HL

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ZILOG

INPUT ACCUMULATOR

IN A,(n)

Operation: A←(n)

The byte of data from the selected peripheral is loaded into the accumulator. During the

I/O transaction, the 8-bit peripheral address from the instruction is placed on the low byte

of the address bus, the contents of the accumulator are placed on address lines A15-A8,

and the high-order address lines are all zeros.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

IN A,(n) 11011011 ——n— 3+i

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DC-8297-03

IN0

INPUT (FROM PAGE 0)

IN0 dst,(n) dst = R

Operation: dst ←(n)

The byte of data from the selected on-chip peripheral is loaded into the destination register.

No external I/O transaction will be generated as a result of this instruction, although the

I/O address will appear on the address bus while this internal read is occurring. The

peripheral address is placed on the low byte of the address bus and zeros are placed on

all other address lines. When the second opcode byte is 30h no data is stored in a

destination; only the flags are updated.

Flags: S: Set if the input data is negative; cleared otherwise

Z: Set if the input data is zero; cleared otherwise

H: Cleared

P: Set if the input data has even parity; cleared otherwise

N: Cleared

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: IN0 R,(n) 11101101 00 -r- 000 ——n— 3+i

none: IN0 (n 11101101 00110000 ——n— 3+i

Field Encodings: r: per convention

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ZILOG

INA

INPUT DIRECT FROM PORT ADDRESS (BYTE)

INA A,(nn)

Operation: A←(nn)

The byte of data from the selected peripheral is loaded into the accumulator. During the

I/O transaction, the peripheral address from the instruction is placed on the address bus.

Any bytes of address not specified in the instruction are driven on the address lines as all

zeros.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

INA A,(nn) 11101101 11011011 -n(low)- -n(high) 3+i I

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DC-8297-03

INAW

INPUT DIRECT FROM PORT ADDRESS (WORD)

INAW HL,(nn)

Operation: HL(15-0) ←(nn)

The word of data from the selected peripheral is loaded into the HL register. During the

I/O transaction, the peripheral address from the instruction is placed on the address bus.

Any bytes of address not specified in the instruction are driven on the address lines as all

zeros.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

INAW HL,(nn) 11111101 11011011 -n(low)- -n(high) 3+i I

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ZILOG

INC

INCREMENT (BYTE)

INC dstdst = R, RX, IR, X

Operation: dst ←dst + 1

The destination operand is incremented by one and the sum is stored in the destination.

Two’s complement addition is performed.

Flags: S: Set if the result is negative; cleared otherwise

Z: Set if the result is zero; cleared otherwise

H: Set if there is a carry from bit 3 of the result; cleared otherwise

V: Set if arithmetic overflow occurs, that is, if the destination was 7FH; cleared otherwise

N: Cleared

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: INC R 00-r-100 note

RX: INC RX 11y11101 0010w100 2

IR: INC (HL) 00110100 2+r+w

X: INC (XY+d) 11y11101 00110100 ——d— 4+r+w I

Field Encodings: r: per convention

y: 0 for IX, 1 for IY

w: 0 for high byte, 1 for low byte

Note: 2 for accumulator, 3 for any other register

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DC-8297-03

INC[W]

INCREMENT (WORD)

INC[W] dst dst = R, RX

Operation: if (XM) then begin

dst(31-0) <dst(31-0) + 1

end

else begin

dst(15-0) ←dst(15-0) + 1

end

The destination operand is incremented by one and the sum is stored in the destination.

Two’s complement addition is performed. Note that the length of the operand is controlled

by the Extended/Native mode selection, which is consistent with the manipulation of an

address by the instruction.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: INC[W] R 00rr0011 2 X

RX: INC[W] RX 11y11101 00100011 2 X

Field Encodings: rr: 00 for BC, 01 for DE, 10 for HL, 11 for SP

y: 0 for IX, 1 for IY

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ZILOG

IND

INPUT AND DECREMENT (BYTE)

IND

Operation: (HL) ←(C)

B←B – 1

HL ←HL – 1

This instruction is used for block input of strings of data. During the I/O transaction the 32-

bit BC register is placed on the address bus. Note that the B register contains the loop count

for this instruction so that A15-A8 are not useable as part of a fixed port address.

First the byte of data from the selected peripheral is loaded into the memory location

addressed by the HL register. Then the B register, used as a counter, is decremented by

one. The HL register is then decremented by one, thus moving the pointer to the next

destination for the input.

Flags: S: Unaffected

Z: Set if the result of decrementing B is zero; cleared otherwise

H: Unaffected

V: Unaffected

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

IND 11101101 10101010 2+i+w

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INDW

INPUT AND DECREMENT (WORD)

INDW

Operation: (HL) ←(DE)

BC(15-0) ←BC(15-0) – 1

HL ←HL – 2

This instruction is used for block input of strings of data. During the I/O transaction the 32-

bit DE register is placed on the address bus.

First the word of data from the selected peripheral is loaded into the memory location

addressed by the HL register. Then the BC register, used as a counter, is decremented by

one. The HL register is then decremented by two, thus moving the pointer to the next

destination for the input.

Flags: S: Unaffected

Z: Set if the result of decrementing BC is zero; cleared otherwise

H: Unaffected

V: Unaffected

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

INDW 11101101 11101010 2+i+w

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ZILOG

INDR

INPUT, DECREMENT AND REPEAT (BYTE)

INDR

Operation: repeat until (B=0) begin

(HL) ←(C)

B←B – 1

HL ←HL – 1

end

This instruction is used for block input of strings of data. The string of input data from the

selected peripheral is loaded into memory at consecutive addresses, starting with the

location addressed by the HL register and decreasing. During the I/O transaction the

32-bit BC register is placed on the address bus. Note that the B register contains the loop

count for this instruction so that A15-A8 are not useable as part of a fixedport address.

First the byte of data from the selected peripheral is loaded into the memory location

addressed by the HL register. Then the B register, used as a counter, is decremented by

one. The HL register is then decremented by one, thus moving the pointer to the next

destination for the input. If the result of decrementing the B register is 0, the instruction is

terminated, otherwise the sequence is repeated. If the B register contains 0 at the start of

the execution of this instruction, 256 bytes are input.

This instruction can be interrupted after each execution of the basic operation. The Program

Counter value at the start of this instruction is saved before the interrupt request is accepted,

so that the instruction can be properly resumed.

Flags: S: Unaffected

Z: Set if the result of decrementing B is zero; cleared otherwise

H: Unaffected

V: Unaffected

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

INDR 11101101 10111010 n X (2+i+w)

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DC-8297-03

INDRW

INPUT, DECREMENT AND REPEAT (WORD)

INDRW

Operation: repeat until (BC=0) begin

(HL) ←(DE)

BC(15-0) ←BC(15-0) – 1

HL ←HL – 2

end

This instruction is used for block input of strings of data. The string of input data from the

selected peripheral is loaded into memory at consecutive addresses, starting with the

location addressed by the HL register and decreasing. During the I/O transaction the

32-bit DE register is placed on the address bus.

First the BC register, used as a counter, is decremented by one. First the word of data from

the selected peripheral is loaded into the memory location addressed by the HL register.

Then the BC register, used as a counter, is decremented by one. The HL register is then

decremented by two, thus moving the pointer to the next destination for the input. If the result

of decrementing the BC register is 0, the instruction is terminated, otherwise the sequence

is repeated. If the BC register contains 0 at the start of the execution of this instruction, 65536

bytes are input.

This instruction can be interrupted after each execution of the basic operation. The Program

Counter value at the start of this instruction is saved before the interrupt request is accepted,

so that the instruction can be properly resumed.

Flags: S: Unaffected

Z: Set if the result of decrementing BC is zero; cleared otherwise

H: Unaffected

V: Unaffected

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

INDRW 11101101 11111010 n X (2+i+w)

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ZILOG

INI

INPUT AND INCREMENT (BYTE)

INI

Operation: (HL) ←(C)

B←B – 1

HL ←HL + 1

This instruction is used for block input of strings of data. During the I/O transaction the 32-

bit BC register is placed on the address bus. Note that the B register contains the loop count

for this instruction so that A15-A8 are not useable as part of a fixed port address.

First the byte of data from the selected peripheral is loaded into the memory location

addressed by the HL register. Then the B register, used as a counter, is decremented by

one. The HL register is then incremented by one, thus moving the pointer to the next

destination for the input.

Flags: S: Unaffected

Z: Set if the result of decrementing B is zero; cleared otherwise

H: Unaffected

V: Unaffected

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

INI 11101101 10100010 2+i+w

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ZILOG

DC-8297-03

INIW

INPUT AND INCREMENT (WORD)

INIW

Operation: (HL) ←(DE)

BC(15-0) ←BC(15-0) – 1

HL ←HL + 2

This instruction is used for block input of strings of data.

During the I/O transaction the 32-bit DE register is placed on the address bus.

First the word of data from the selected peripheral is loaded into the memory location

addressed by the HL register. Then the BC register, used as a counter, is decremented by

one. The HL register is then incremented by two, thus moving the pointer to the next

destination for the input.

Flags: S: Unaffected

Z: Set if the result of decrementing BC is zero; cleared otherwise

H: Unaffected

V: Unaffected

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

INIW 11101101 11100010 2+i+w

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ZILOG

INIR

INPUT, INCREMENT AND REPEAT (BYTE)

INIR

Operation: repeat until (B=0) begin

(HL) ←(C)

B←B – 1

HL ←HL + 1

end

This instruction is used for block input of strings of data. The string of input data from the

selected peripheral is loaded into memory at consecutive addresses, starting with the

location addressed by the HL register and increasing. During the I/O transaction the 32-bit

BC register is placed on the address bus. Note that the B register contains the loop count

for this instruction so that A(15-8) are not useable as part of a fixedport address.

First the byte of data from the selected peripheral is loaded into the memory location

addressed by the HL register. Then the B register, used as a counter, is decremented by

one. The HL register is then incremented by one, thus moving the pointer to the next

destination for the input. If the result of decrementing the B register is 0, the instruction is

terminated, otherwise the sequence is repeated. If the B register contains 0 at the start of

the execution of this instruction, 256 bytes are input.

This instruction can be interrupted after each execution of the basic operation. The Program

Counter value at the start of this instruction is saved before the interrupt request is accepted,

so that the instruction can be properly resumed.

Flags: S: Unaffected

Z: Set if the result of decrementing B is zero; cleared otherwise

H: Unaffected

V: Unaffected

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

INIR 11101101 10110010 n X (2+i+w)

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DC-8297-03

INIRW

INPUT, INCREMENT AND REPEAT (WORD)

INIRW

Operation: repeat until (BC=0) begin

(HL) ←(DE)

BC(15-0) ←BC(15-0) – 1

HL ←HL + 2

end

This instruction is used for block input of strings of data. The string of input data from the

selected peripheral is loaded into memory at consecutive addresses, starting with the

location addressed by the HL register and increasing. During the I/O transaction the 32-bit

DE register is placed on the address bus.

First the word of data from the selected peripheral is loaded into the memory location

addressed by the HL register. Then the BC register, used as a counter, is decremented by

one. The HL register is then incremented by two, thus moving the pointer to the next

destination for the input. If the result of decrementing the BC register is 0, the instruction is

terminated, otherwise the sequence is repeated. If the BC register contains 0 at the start of

the execution of this instruction, 65536 bytes are input.

This instruction can be interrupted after each execution of the basic operation. The Program

Counter value at the start of this instruction is saved before the interrupt request is accepted,

so that the instruction can be properly resumed.

Flags: S: Unaffected

Z: Set if the result of decrementing BC is zero; cleared otherwise

H: Unaffected

V: Unaffected

N: Set

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

INIRW 11101101 11110010 n X (2+i+w)

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ZILOG

JUMP

JP [cc,]dst dst = IR, DA

Operation: if (cc is TRUE) then begin

if (XM) then begin

PC(31-0) ←dst(31-0)

end

else begin

PC(15-0) ←dst(15-0)

end

A conditional jump transfers program control to the destination address if the setting of a

selected flag satisfies the condition code “cc” specified in the instruction; an unconditional

jump always transfers control to the destination address. If the jump is taken, the Program

Counter (PC) is loaded with the destination address; otherwise the instruction following the

Jump instruction is executed.

Each of the Zero, Carry, Sign, and Overflow flags can be individually tested and a jump

performed conditionally on the setting of the flag.

When using DA mode with the JP instruction, the operand is not enclosed in parentheses.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

IR: JP (HL) 11101001 2 X

JP (XY) 11y11101 11101001 2 X

DA: JP CC,addr 11-cc010 -a(low)- -a(high) 2 I, X

JP addr 11000011 -a(low)- -a(high) 2 I, X

Field Encodings: y: 0 for IX, 1 for IY

cc: 000 for NZ, 001 for Z, 010 for NC, 011 for C, 100 for PO/NV, 101 for PE/V, 110 for

P/NS,111 for M/S

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ZILOG

DC-8297-03

JUMP RELATIVE

JR [cc,]dst dst = RA

Operation: if (cc is TRUE) then begin

dst ←SIGN EXTEND dst

if (XM) then begin

PC(31-0) ←PC(31-0) + dst(31-0)

end

else begin

PC(15-0) ←PC(15-0) + dst(15-0)

end

A conditional Jump transfers program control to the destination address if the setting of a

selected flag satisfies the condition code “cc” specified in the instruction; an unconditional

Jump always transfers control to the destination address. Either the Zero or Carry flag can

be tested for the conditional Jump. If the jump is taken, the Program Counter (PC) is loaded

with the destination address; otherwise the instruction following the Jump Relative instruc-

tion is executed.

The destination address is calculated using relative addressing. The displacement in the

instruction is added to the PC value for the instruction following the JR instruction, not the

value of the PC for the JR instruction.

These instructions employ either an 8-bit, 16-bit, or 24-bit signed, two’s complement

displacement from the PC to permit jumps within a range of –126 to +129 bytes, –32,765 to

+32,770 bytes, or –8,388,604 to +8,388,611 bytes from the location of this instruction.

Flags:S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

RA: JR CC,addr 001cc000 —disp— 2 X

JR addr 00011000 —disp— 2 X

JR CC,addr 11011101 001cc000 -d(low)- -d(high) 2 X

JR addr 11011101 00011000 -d(low)- -d(high) 2 X

JR CC,addr 11111101 001cc000 -d(low)- -d(mid)- -d(high) 2 X

JR addr 11111101 00011000 -d(low)- -d(mid)- -d(high) 2 X

Field Encodings: cc: 00 for NZ, 01 for Z, 10 for NC, 11 for C

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ZILOG

LOAD ACCUMULATOR

LD dst,src dst = A

src = R, RX, IM, IR, DA, X

dst = R, RX, IR, DA, X

src = A

Operation: dst ←src

The contents of the source are loaded into the destination.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Load into Accunulator

Addressing Execute

Mode Syntax Instruction Format Time Note

R: LD A,R 01111-r- 2

RX: LD A,RX 11y11101 0111110w 2

IM: LD A,n 00111110 ——n— 2

IR: LD A,(HL) 01111110 2+r

LD A,(IR) 000a1010 2+r

DA: LD A,(nn) 00111010 -n(low)- -n(high) 3+r I

X: LD A,(XY+d) 11y11101 01111110 ——d— 4+r I

Load from Accunulator

Addressing Execute

Mode Syntax Instruction Format Time Note

R: LD Rd,A 01-r-111 2

RX: LD RX,A 11y11101 0110w111 2

IR: LD (HL),A 01110111 3+w

LD (IR),A 000a0010 3+w

DA: LD (nn),A 00110010 -n(low)- -n(high) 4+w I

X:LD (XY+d),A 11y11101 01110111 ——d— 5+w I

Field Encodings: r: per convention

y: 0 for IX, 1 for IY

w: 0 for high byte, 1 for low byte

a: 0 for BC, 1 for DE

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ZILOG

DC-8297-03

LOAD IMMEDIATE (BYTE)

LD dst,n dst = R, RX, IR, X

Operation: dst ←n

The byte of immediate data is loaded into the destination.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: LD R,n 00-r-110 ——n— 2

RX: LD RX,n 11y11101 0010w110 ——n— 2

IR: LD (HL),n 00110110 ——n— 3+w

X: LD (XY+d),n 11y11101 00110110 ——d— ——n— 5+w I

Field Encodings: r: per convention

y: 0 for IX, 1 for IY

w: 0 for high byte, 1 for low byte

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ZILOG

LOAD IMMEDIATE (WORD)

LD dst,nn dst = R, RX

Operation: if (LW) then begin

dst(31-0) ←nn

end

else begin

dst(15-0) ←nn

end

The word of immediate data is loaded into the destination.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: LD R,nn 00rr0001 -n(low)- -n(high) 2 I, L

RX: LD RX,nn 11y11101 00100001 -n(low)- -n(high) 2 I, L

Field Encodings: rr: 00 for BC, 01 for DE, 10 for HL

y: 0 for IX, 1 for IY

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ZILOG

DC-8297-03

LDW

LOAD IMMEDIATE (WORD)

LDW dst,nn dst = IR

Operation: if (LW) then begin

dst(31-0) ←nn

end

else begin

dst(15-0) ←nn

end

The word of immediate data is loaded into the destination.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

IR: LDW (IR),nn 11101101 00pp0110 -n(low)- -n(high) 3+w I, L

Field Encodings: pp: 00 for BC, 01 for DE, 11 for HL

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DC-8297-03

ZILOG

LOAD REGISTER (BYTE)

LD dst,src dst = R

src = R, RX, IM, IR, X

or dst = R, RX, IR, X

src = R

Operation: dst ←src

The contents of the source are loaded into the destination.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Load into Register

Addressing Execute

Mode Syntax Instruction Format Time Note

R: LD Rd,Rs 01-rd-rs 2

RX: LD Rd,RX 11y11101 01-ra10w 2

LD RXa,RXb 11y11101 0110a10b 2

IM: LD R,n 00-r-110 ——n— 2

IR: LD R,(HL) 01-r-110 5+w

X: LD R,(XY+d) 11y11101 01-r-110 ——d— 7+w I

Load from Register

Addressing Execute

Mode Syntax Instruction Format Time Note

RX: LD RX,Rs 11y11101 0110w-ra 2

LD RXa,RXb 11y11101 0110a10b 2

IR: LD (HL),R 01110-r- 3+w

X: LD (XY+d),R 11y11101 01110-r- ——d— 5+w I

Field Encodings: r: per convention

rd: per convention

rs: per convention

y: 0 for IX, 1 for IY

w: 0 for high byte, 1 for low byte

ra: per convention, for A, B, C, D, E only

a: destination, 0 for high byte, 1 for low byte

b: source, 0 for high byte, 1 for low byte

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ZILOG

DC-8297-03

LD[W]

LOAD REGISTER (WORD)

LD[W] dst,src dst = R

src = R, RX, IR, DA, X, SR

dst = R, RX, IR, DA, X, SR

src = R

Operation: if (LW) then begin

dst(31-0) ←src(31-0)

end

else begin

dst(15-0) ←src(15-0)

end

The contents of the source are loaded into the destination.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Load into Register

Addressing Execute

Mode Syntax Instruction Format Time Note

R: LD Rd,Rs 11rs1101 00rd0010 2 L

RX: LD R,RX 11y11101 00rr1011 2 L

IR: LD R,(IR) 11011101 00rr11ri 2+r L

LD RX,(IR) 11y11101 00ri0011 2+r L

DA: LD HL,(nn) 00101010 -n(low)- -n(high) 3+r I, L

LD R,(nn) 11101101 01ra1011 -n(low)- -n(high) 3+r I, L

LD RX,(nn) 11y11101 00101010 -n(low)- -n(high) 3+r I, L

X: LD R,(XY+d) 11y11101 11001011 ——d— 00rr0011 4+r I, L

LD IX,(IY+d) 11111101 11001011 ——d— 00100011 4+r I, L

LD IY,(IX+d) 11011101 11001011 ——d— 00100011 4+r I, L

SR: LD R,(SP+d) 11011101 11001011 ——d— 00rr0001 4+r I, L

LD RX,(SP+d) 11y11101 11001011 ——d— 00100001 4+r I, L

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ZILOG

LD[W]

LOAD REGISTER (WORD)

Load from Register

Addressing Execute

Mode Syntax Instruction Format Time Note

RX: LD RX,R 11y11101 00rr0111 2 L

LD IX,IY 11011101 00100111 2 L

LD IY,IX 11111101 00100111 2 L

IR: LD (IR),RR 11111101 00rr11ri 3+w L

LD (IR),RX 11y11101 00ri0001 3+w L

DA: LD (nn),HL 00100010 -n(low)- -n(high) 4+w I, L

LD (nn),R 11101101 01ra0011 -n(low)- -n(high) 4+w I, L

LD (nn),RX 11y11101 00100010 -n(low)- -n(high) 4+w I, L

X: LD (XY+d),R 11y11101 11001011 ——d— 00rr1011 5+w I, L

LD (IY+d),IX 11111101 11001011 ——d— 00101011 5+w I, L

LD (IX+d),IY 11011101 11001011 ——d— 00101011 5+w I, L

SR: LD (SP+d),R 11011101 11001011 ——d— 00rr1001 5+w I, L

LD (SP+d),XY 11y11101 11001011 ——d— 00101001 5+w I, L

Field Encodings: rs: 01 for DE, 10 for BC, 11 for HL

rd: 00 for BC, 01 for DE, 11 for HL

y: 0 for IX, 1 for IY

rr: 00 for BC, 01 for DE, 11 for HL

ri: 00 for BC, 01 for DE, 11 for HL

ra: 00 for BC, 01 for DE, 10 for HL

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ZILOG

DC-8297-03

LOAD STACK POINTER

LD dst,src dst = SP

src = R, RX, IM, DA

dst = DA

src = SP

Operation: if (LW) then begin

dst(31-0) ←src(31-0)

end

else begin

dst(15-0) ←src(15-0)

end

The contents of the source are loaded into the destination.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Load into Stack Pointer

Addressing Execute

Mode Syntax Instruction Format Time Note

R: LD SP,HL 11111001 2 L

RX: LD SP,RX 11y11101 11111001 2 L

IM: LD SP,nn 00110001 -n(low)- -n(high) 2 I, L

DA: LD SP,(nn) 11101101 01111011 -n(low)- -n(high) 3+r I, L

Field Encodings: y: 0 for IX, 1 for IY

Load from Stack Pointer

Addressing Execute

Mode Syntax Instruction Format Time Note

DA: LD (nn),SP 11101101 01110011 -n(low)- -n(high) 4+w I, L

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ZILOG

LOAD FROM I OR R REGISTER (BYTE)

LD dst,src dst = A

src = I, R

Operation: dst ←src

The contents of the source are loaded into the accumulator. The contents of the source are

not affected. The Sign and Zero flags are set according to the value of the data transferred;

the Overflow flag is set according to the state of the interrupt enable. Note that if an interrupt

occurs during execution of either of these instructions the Overflow flag reflects the prior

state of the interrupt enable. Also note that the R register does not contain the refresh

address and is not modified by refresh transactions.

Flags: S: Set if the data loaded into the accumulator is negative; cleared otherwise

Z: Set if the data loaded into the accumulator is zero; cleared otherwise

H: Cleared

V: Set when loading the accumulator if interrupts are enabled; cleared otherwise

N: Cleared

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

LD A,I 11101101 01010111 2

LD A,R 11101101 01011111 2

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ZILOG

DC-8297-03

LOAD INTO I OR R REGISTER (BYTE)

LD dst,src dst = I, R

src = A

Operation: dst ←src

The contents of the accumulator are loaded into the destination. Note that the R register does

not contain the refresh address and is not modified by refresh transactions.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

R: LD I,A 11101101 01000111 2

LD R,A 11101101 01001111 2

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DC-8297-03

ZILOG

LD[W]

LOAD I REGISTER (WORD)

LD[W] dst,src dst = HL

src = I

dst = I

src = HL

Operation: if (LW) then begin

dst(31-0) ←src(31-0)

end

else begin

dst(15-0) ←src(15-0)

end

The contents of the source are loaded into the destination

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Load from I Register

Addressing Execute

Mode Syntax Instruction Format Time Note

R: LD[W] HL,I 11011101 01010111 2 L

Load into I Register

Addressing Execute

Mode Syntax Instruction Format Time Note

R: LD[W] I,HL 11011101 01000111 2 L

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ZILOG

DC-8297-03

LDCTL

LOAD CONTROL REGISTER (BYTE)

LDCTL dst,src dst = DSR, XSR, YSR

src = A, IM

dst = A

src = DSR, XSR, YSR

dst = SR

src = A, IM

Operation: if (dst = SR) then begin

SR(31-24) ←src

SR(23-16) ←src

SR(15-8) ←src

end

else begin

dst ←src

end

The contents of the source are loaded into the destination.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Load into Control Register

Addressing Execute

Mode Syntax Instruction Format Time Note

R: LDCTL SR,A 11011101 11001000 4

LDCTL Rd,A 11qq1101 11011000 4

IM: LDCTL SR,n 11011101 11001010 ——n— 4

LDCTL Rd,n 11qq1101 11011010 ——n— 4

Field Encodings: qq: 01 for XSR, 10 for DSR, 11 for YSR

Load from Control Register

Addressing Execute

Mode Syntax Instruction Format Time Note

R: LDCTL A,Rs 11qq1101 11010000 2

Field Encodings: qq: 01 for XSR, 10 for DSR, 11 for YSR

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DC-8297-03

ZILOG

LDCTL

LOAD FROM CONTROL REGISTER (WORD)

LDCTL dst,src dst = HL

src = SR

Operation: if (LW) then begin

dst(31-0) ←src(31-0)

end

else begin

dst(15-0) ←src(15-0)

end

The contents of the Select Register (SR) are loaded into the HL register.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Load from Control Register

Addressing Execute

Mode Syntax Instruction Format Time Note

R: LDCTL HL,SR 11101101 11000000 2 L

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ZILOG

DC-8297-03

LDCTL

LOAD INTO CONTROL REGISTER (WORD)

LDCTL dst,src dst = SR

src = HL

Operation: if (LW) then begin

dst(31-16) ←HL(31-16)

end

else begin

dst(31-24) ←HL(15-8)

dst(23-16) ←HL(15-8)

end

dst(15-8) ←HL(15-8)

dst(0) ←HL(0)

The contents of the HL register are loaded into the Select Register (SR). If Long Word mode

is not in effect the upper byte of the HL register is copied into the three most significant bytes

of the select register. This instruction does not modify the mode bits in the SR. There are

dedicated instructions to modify the mode bits.

Flags: S: Unaffected

Z: Unaffected

H: Unaffected

V: Unaffected

N: Unaffected

C: Unaffected

Load from Control Register

Addressing Execute

Mode Syntax Instruction Format Time Note

R: LDCTL SR,HL 11101101 11001000 4 L

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DC-8297-03

ZILOG

LDD

LOAD AND DECREMENT (BYTE)

LDD

Operation: (DE) ←(HL)

DE ←DE – 1

HL ←HL – 1

BC(15-0) ←BC(15-0) – 1

This instruction is used for block transfers of strings of data. The byte of data at the location

addressed by the HL register is loaded into the location addressed by the DE register. Both

the DE and HL registers are then decremented by one, thus moving the pointers to the

preceeding elements in the string. The BC register, used as a counter, is then decremented

by one.

Flags: S: Unaffected

Z: Unaffected

H: Cleared

V: Set if the result of decrementing BC is not equal to zero; cleared otherwise

N: Cleared

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

LDD 11101101 10101000 3+r+w

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ZILOG

DC-8297-03

LDDW

LOAD AND DECREMENT (WORD)

LDDW

Operation: if (LW) then begin

(DE) ←(HL)

(DE+1) ←(HL+1)

(DE+2) ←(HL+2)

(DE+3) ←(HL+3)

DE ←DE – 4

HL ←HL – 4

BC(15-0) ←BC(15-0) – 4

end

else begin

(DE) ←(HL)

(DE+1) ←(HL+1)

DE ←DE – 2

HL ←HL – 2

BC(15-0) ←BC(15-0) – 2

end

This instruction is used for block transfers of words of data. The word of data at the location

addressed by the HL register is loaded into the location addressed by the DE register. Both

the DE and HL registers are then decremented by two or four, thus moving the pointers to

the preceeding words in the array. The BC register, used as a byte counter, is then

decremented by two or four.

Both DE and HL should be even, to allow word transfers on the bus. BC must be even,

transferring an even number of bytes, or the operation is undefined.

Flags: S: Unaffected

Z: Unaffected

H: Cleared

V: Set if the result of decrementing BC is not equal to zero; cleared otherwise

N: Cleared

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

LDDW 11101101 11101000 3+r+w L

5-98

Z380

™

USER'S MANUAL

DC-8297-03

ZILOG

LDDR

LOAD, DECREMENT AND REPEAT (BYTE)

LDDR

Operation: repeat until BC=0 begin

(DE) ←(HL)

DE ←DE – 1

HL ←HL – 1

BC(15-0) ←BC(15-0) – 1

end

This instruction is used for block transfers of strings of data. The bytes of data at the location

addressed by the HL register are loaded into memory starting at the location addressed by

the DE register. The number of bytes moved is determined by the contents of the BC register.

If the BC register contains zero when this instruction is executed, 65,536 bytes are

transferred. The effect of decrementing the pointers during the transfer is important if the

source and destination strings overlap with the source string starting at a lower memory

address. Placing the pointers at the highest address of the strings and decrementing the

pointers ensures that the source string is copied without destroying the overlapping area.

This instruction can be interrupted after each execution of the basic operation. The Program

Counter value of the start of this instruction is saved before the interrupt request is

accepted,so that the instruction can be properly resumed.

Flags: S: Unaffected

Z: Unaffected

H: Cleared

V: Cleared

N: Cleared

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

LDDR 11101101 10111000 n X (3+r+w)

5-99

Z380

™

USER'S MANUAL

ZILOG

DC-8297-03

LDDRW

LOAD, DECREMENT AND REPEAT (WORD)

LDDRW

Operation: repeat until (BC=0) begin

if (LW) then begin

(DE) ←(HL)

(DE+1) ←(HL+1)

(DE+2) ←(HL+2)

(DE+3) ←(HL+3)

DE ←DE – 4

HL ←HL – 4

BC(15-0) ←BC(15-0) – 4

end

else begin

(DE) ←(HL)

(DE+1) ←(HL+1)

DE ←DE – 2

HL ←HL – 2

BC(15-0) ←BC(15-0) – 2

end

This instruction is used for block transfers of strings of data. The words of data at the location

addressed by the HL register are loaded into memory starting at the location addressed by

the DE register. The number of words moved is determined by the contents of the BC

transferred. The effect of decrementing the pointers during the transfer is important if the

source and destination strings overlap with the source string starting at a lower memory

address. Placing the pointers at the highest address of the strings and decrementing the

pointers ensures that the source string is copied without destroying the overlapping area.

This instruction can be interrupted after each execution of the basic operation. The Program

Counter value of the start of this instruction is saved before the interrupt request is

accepted,so that the instruction can be properly resumed.

Flags: S: Unaffected

Z: Unaffected

H: Cleared

V: Cleared

N: Cleared

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

LDDRW 11101101 11111000 nX(3+r+w) L

5-100

Z380

™

USER'S MANUAL

DC-8297-03

ZILOG

LDI

LOAD AND INCREMENT (BYTE)

LDI

Operation: (DE) ←(HL)

DE ←DE + 1

HL ←HL + 1

BC(15-0) ←BC(15-0) – 1

This instruction is used for block transfers of strings of data. The byte of data at the location

addressed by the HL register is loaded into the location addressed by the DE register. Both

the DE and HL registers are then incremented by one, thus moving the pointers to the next

elements in the string. The BC register, used as a counter, is then decremented by one.

Flags: S: Unaffected

Z: Unaffected

H: Cleared

V: Set if the result of decrementing BC is not equal to zero; cleared otherwise

N: Cleared

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

LDI 11101101 10100000 3+r+w

5-101

Z380

™

USER'S MANUAL

ZILOG

DC-8297-03

LDIW

LOAD AND INCREMENT (WORD)

LDIW

Operation: if (LW) then begin

(DE) ←(HL)

(DE+1) ←(HL+1)

(DE+2) ←(HL+2)

(DE+3) ←(HL+3)

DE ←DE + 4

HL ←HL + 4

BC(15-0) ←BC(15-0) – 4

end

else begin

(DE) ←(HL)

(DE+1) ←(HL+1)

DE ←DE + 2

HL ←HL + 2

BC(15-0) ←BC(15-0) – 2

end

This instruction is used for block transfers of words of data. The word of data at the location

addressed by the HL register is loaded into the location addressed by the DE register. Both

the DE and HL registers are then incremented by two or four, thus moving the pointers to

the succeeding words in the array. The BC register, used as a byte counter, is then

decremented by two or four.

Both DE and HL should be even, to allow word transfers on the bus. BC must be even,

transferring an even number of bytes, or the operation is undefined.

Flags: S: Unaffected

Z: Unaffected

H: Cleared

V: Set if the result of decrementing BC is not equal to zero; cleared otherwise

N: Cleared

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

LDIW 11101101 11100000 3+r+w L

5-102

Z380

™

USER'S MANUAL

DC-8297-03

ZILOG

LDIR

LOAD, INCREMENT AND REPEAT (BYTE)

LDIR

Operation: repeat until (BC=0) begin

(DE) ←(HL)

DE ←DE + 1

HL ←HL + 1

BC(15-0) ←BC(15-0) – 1

end

This instruction is used for block transfers of strings of data. The bytes of data at the location

addressed by the HL register are loaded into memory starting at the location addressed by

the DE register. The number of bytes moved is determined by the contents of the BC register.

If the BC register contains zero when this instruction is executed, 65,536 bytes are

transferred. The effect of incrementing the pointers during the transfer is important if the

source and destination strings overlap with the source string starting at a higher memory

address. Placing the pointers at the lowest address of the strings and incrementing the

pointers ensures that the source string is copied without destroying the overlapping area.

This instruction can be interrupted after each execution of the basic operation. The Program

Counter value of the start of this instruction is saved before the interrupt request is

accepted,so that the instruction can be properly resumed.

Flags: S: Unaffected

Z: Unaffected

H: Cleared

V: Cleared

N: Cleared

C: Unaffected

Addressing Execute

Mode Syntax Instruction Format Time Note

LDIR 11101101 10110000 3+r+w

5-103

Z380

™

USER'S MANUAL

ZILOG

DC-8297-03

LDIRW

LOAD, INCREMENT AND REPEAT (WORD)