CYF2018V
CYF2036V
CYF2072V
18/36/72-Mbit Programmable
Multi-Queue FIFOs
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-68336 Rev. *F Revised April 10, 2014
18/36/72-Mbit Programmable Multi-Queue FIFOs
Features
■Memory organization
❐Industry’s largest first in first out (FIFO) memory densities:
18-Mbit, 36-Mbit and 72-Mbit
❐Selectable memory organization: × 9, × 12, × 16, × 18, × 20,
× 24, × 32, × 36
■Up to 100-MHz clock operation
■Unidirectional operation
■Independent read and write ports
❐Supports simultaneous read and write operations
❐Reads and writes operate on independent clocks, upto a
maximum ratio of two, enabling data buffering across clock
domains.
❐Supports multiple I/O voltage standard: Low voltage
complementary metal oxide semiconductor (L VCMOS) 3.3 V
and 1.8 V voltage standards.
■Input and output enable control for write mask and read skip
operations
■User configured multi-queue operating mode upto 8-queues
■Mark and retransmit: resets read pointer to user marked
position
■Empty and full flags
■Flow-through mailbox register to send data from input to output
port, bypassing the FIFO seque nce
■Separate serial clock (SCLK) input for serial programming
■Master reset to clear entire FIFO
■Joint test action group (JT AG) port provided for boundary scan
function
■Industrial temperature range: –40 °C to +85 °C
Functional Description
The Cypress programmable FIFO family offers the industry’s
highest-density FIFO memory device. It has independent read
and write ports, which can be clocked up to 100 MHz. User can
configure input and output bus sizes. A maximum bus size of
36 bits enables a maximum data throughput of 3.6 Gbps. The
user-programmable registers enable user to configure the
device operation as desired. The device also offers a simple and
easy-to-use interface to reduce implementation and debugging
efforts, improve time-to-market, and reduce engineering costs.
This makes it an ideal memory choice for a wide range of
applications including multiprocessor interfaces, video and
image processing, networking and telecommunications,
high-speed data acquisition, or any system that needs buffering
at high speeds across different clock domains.
As implied by the name, the functionality of the FIFO is such that
the data is read out of the read port in the same sequence in
which it was written into the write port. If the writes and inputs are
enabled (WEN & IE), data on the write port gets written into the
device at the rising edge of write clock. Enabling reads and
outputs (REN & OE) fetches data on the read port at every rising
edge of the read clock. Both reads and writes can occur
simultaneously at different speeds provided the ratio between
read and write clock is in the range of 0.5 to 2. Appropriate flags
are set whenever the FIFO is empty or full.
The device supports multi-queue mode of operation where it can
be configured in 8, 4 or 2 queue modes with each queue
operating as an independent FIFO. It also supports single-queue
mode of operation. The FIFO includes features such as mark
and retransmit and a flow-through ma ilbox register.
All product features and specs are common to all densities
(CYF2072V, CYF2036V, and CYF2018V) unless otherwise
specified. All descriptions are given assuming the device is
CYF2072V operated in × 36 mode. They are valid for other
densities (CYF2036V, and CYF2018V) and all port sizes × 9,
× 12, × 16, × 18, × 20, × 24 and × 32 unless otherwise specified.
The only difference will be in the input and output bus width.
Table 1 on page 7 shows the part of bus with valid data from
D[35:0] and Q[35:0] in × 9, × 12, × 16, × 18, × 20, × 24, × 32 and
× 36 modes.
Errata: For information on silicon errata, see Errata on page 30. Details include trigger conditions, devices affected, and proposed workaround.
CYF2018V
CYF2036V
CYF2072V
Document Number: 001-68336 Rev. *F Page 2 of 32
Logic Block Diagram
WRITE POINTER
WRITE
CONTROL LOGIC
RESET POINTER
JTAG CONTROL
Memory Array
18-Mbit
36-Mbit
72-Mbit
OUTPUT
REGISTER
INPUT
REGISTER CONFIGURATION
REGISTERS/MAILBOX
FLAG LOGIC
READ POINTER
READ CONTROL
LOGIC
MEMORY LOGIC
ORGANIZATION
PORTSZ[2:0]
Q[35:0]
OE
RCLK
REN
MARK, RT
DVal
Qval[2:0]
EF
FF
MB
SPI_SI
LD SPI_SEN SPI_SCLK
D[35:0]
IE WEN WCLK
MRS
TCK
TRST
TMS
TDO
TDI
WQSEL[2:0]
RQSEL[2:0]
CYF2018V
CYF2036V
CYF2072V
Document Number: 001-68336 Rev. *F Page 3 of 32
Contents
Pin Diagram for CYF2XXXVXXL ......................................4
Pin Definitions ..................................................................5
Architecture ......................................................................6
Reset Logic .................................. ... .............. .. ... .........6
Multi-Queue Operation ................................................7
Selecting Word Sizes ..................................................7
Memory Organization for Different Port Sizes .............7
Data Valid Signal (DVal) ..............................................7
Queue Valid Signal (QVal[2:0]) ..................... .. ... ... ......7
Write Mask and Read Skip Operation .........................7
Flow-through mailbox Register ....................................8
Flag Operation ........................ ... .............. ... .............. ...8
Retransmit from Mark Operation .................................8
Programming Configuration Registers ........................8
Width Expansion Configuration .................................11
Power Up ........................ ... .............. .. .............. ... .......12
Read/Write Clock Requirements ...............................12
JTAG operation .................... .............. .............. ... ............13
Maximum Ratings ...........................................................14
Operating Range ..................... .. .............. ... .............. ... ....14
Recommended DC Operating Conditions ....................14
Electrical Characteristics ...............................................14
I/O Characteristics ..........................................................15
Latency Table ................ .. .............. ... ............................ ...15
AC Test Load Conditions ...............................................16
Switching Characteristics ..............................................17
Switching Waveforms ....................................................18
Ordering Information ......................................................27
Ordering Code Definitions .........................................27
Package Diagram ............................................................28
Acronyms ........................................................................ 29
Document Conventions .................. ... ... .............. ... ........29
Units of Measure ..... .. ... .............. ... ... .............. ... ........29
Errata ...............................................................................30
Part Numbers Affected ..............................................30
18-Mbit, 36-Mbit, and
72-Mbit Programmable FIFO Qualification Status ............30
18-Mbit, 36-Mbit, and
72-Mbit Programmable FIFO Errata Summary .................30
Document History Page ........................... ... .............. .. ...31
Sales, Solutions, and Legal Information ......................32
Worldwide Sales and Design Support .......................32
Products .................................................................... 32
PSoC® Solutions ......................................................32
Cypress Developer Community ...................... ... ........32
Technical Support .....................................................32
CYF2018V
CYF2036V
CYF2072V
Document Number: 001-68336 Rev. *F Page 4 of 32
Pin Diagram for CYF2XXXVXXL
Figure 1. 209-ball FBGA (Top View) [1]
1 2 3 4 5 6 7 8 9 10 11
AFF D0 D1 WQSEL0 PORTSZ0 PORTSZ1 DNU RQSEL0 RT Q0 Q1
BEF D2 D3 WQSEL1 DNU PORTSZ2 DNU RQSEL1 REN Q2 Q3
CD4 D5 WENWQSEL2 VCC1 DNU VCC1 RQSEL2 RCLK Q4 Q5
DD6 D7 V
SS VCC1 DNU LD DNU VCC1 VSS Q6 Q7
ED8 D9 V
CC2 VCC2 VCCIO VCCIO VCCIO VCC2 VCC2 Q8 Q9
FD10 D11 V
SS VSS VSS DNU VSS VSS VSS Q10 Q11
GD12 D13 V
CC2 VCC2 VCCIO VCC1 VCCIO VCC2 VCC2 Q12 Q13
HD14 D15 V
SS VSS VSS VCC1 VSS VSS VSS Q14 Q15
JD16 D17 V
CC2 VCC2 VCCIO VCC1 VCCIO VCC2 VCC2 Q16 Q17
K DNU DNU WCLK DNU VSS IE VSS DNU VCCIO VCCIO VCCIO
LD18 D19 V
CC2 VCC2 VCCIO VCC1 VCCIO VCC2 VCC2 Q18 Q19
MD20 D21 V
SS VSS VSS VCC1 VSS VSS VSS Q20 Q21
ND22 D23 V
CC2 VCC2 VCCIO VCC1 VCCIO VCC2 VCC2 Q22 Q23
PD24 D25 V
SS VSS VSS SPI_SEN VSS VSS VSS Q24 Q25
RD26 D27 V
CC2 VCC2 VCCIO VCCIO VCCIO VCC2 VCC2 Q26 Q27
TD28 D29 V
SS VCC1 VCC1 SPI_SI VCC1 VCC1 VSS Q28 Q29
UDVal DNU D30 D31 DNU DNU [2] SPI_SCLK VREF OE Q30 Q31
V QVal1 QVal0 D32 D33 DNU MRS MB DNU MARK Q32 Q33
W TDO QVal2 D34 D35 TDI TRST TMS TCK DNU Q34 Q35
Notes
1. Pin Diagram for 18-Mbit, 36-Mbit & 72-Mbit; 1.8V & 3.3V IO voltage options.
2. This pin should be tied to VSS preferably or can be left floating to ensure normal operation.
CYF2018V
CYF2036V
CYF2072V
Document Number: 001-68336 Rev. *F Page 5 of 32
Pin Definitions
Pin Name I/O Pin Descripti on
MRS Input Master reset: MRS initializes the read and write pointers to zero, resets to 8 queue operating mode and
sets the output register to all zeroes. During Master Reset, the configuration registers are all set to default
values and the flags are reset.
PORTSZ [2:0] Input Port word size select: Port word width select pins (common for read and write ports).
WCLK Input Write clock: Data is written into the FIFO queue indicated by W QSEL[2:0] on the risi ng edge of W CLK
provided writes are enabled (WEN low). Writes are performed either to the FIFO memory or configuration
registers based on the status of the load signal (LD).
LD Input Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configuration registers. Whe n
LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the FIFO.
WEN Input Write enable: WEN enables WCLK to write data into the FIFO memory and configurati on registers.
WQSEL[2:0] Input Write Queue selec t: Selects the FIFO queue to be written into based on the operating mode.
IE Input Input enable: IE is the data input enable signal that controls the enabling and disabling of the 36-bit data
input pins. If it is enabled, data on the D[35:0] pins is written into the FIF O. The internal write ad dress
pointer is always incremented at rising edge of WCLK if WEN is enabled, regardless of the IE level. This
is used for ‘write masking’ or incrementing the write pointer without writing into a location.
D[35:0] Input Data inputs: Data inputs for a 36-bit bus.
RCLK Input Read clock: Data is read from the FIFO queue indi cated by RQSEL[2:0] on e ach rising edge of RCLK
provided reads are enabled (REN low). LD determines whether the da ta is read from FIFO memory or
configuration registers.
REN Input Read enable: REN enables RCLK to read data from the FIFO memory and configuration registers.
RQSEL[2:0] Input Read Queue select: Selects the FIFO queue to be read from based on the operating mode.
OE Input Output enable: When OE is LOW , FIFO data outputs are enabled; when OE is HIGH, the FIFO’s outputs
are in High Z (high impedance) state.
Q[35:0] Output Data outputs: Data outputs for a 36-bit bus.
DVal Output Data valid: Active low data valid signal to indicate valid data on Q[35:0 ].
QVal[2:0] Output Queue valid: Validate with DVal to indicate the Queue for which data is being read out on Q[35:0]
DVal = 0 and QVal = 000 valid data read out from Queue-0 on Q[35 :0]
DVal = 0 and QVal = 001 valid data read out from Queue-1 on Q[35 :0]
DVal = 0 and QVal = 010 valid data read out from Queue-2 on Q[35 :0]
DVal = 0 and QVal = 011 valid data read out from Queue-3 on Q[35:0]
DVal = 0 and QVal = 100 valid data read out from Queue-4 on Q[35 :0]
DVal = 0 and QVal = 101 valid data read out from Queue-5 on Q[35 :0]
DVal = 0 and QVal = 110 valid data read out from Queue-6 on Q[35:0]
DVal = 0 and QVal = 111 valid data read out from Queue-7 on Q[35:0]
MARK Input Mark for retransmit: When this pin is asserted the memory location corresponding to valid data present
on the output bus is marked. Any subsequent retransmit operation resets the read pointer to this memory
location.
RT Input Retransmit: A HIGH pulse on RT resets the internal read pointer to a physical location in the FIFO which
is marked by the user (using MARK pin). With every valid read cycle after retransmit, previously accessed
data is read until the FIFO is empty.
MB Input Mailbox: When asserted the reads and writes happen to flow-through mailbox register.
EF Output Empty flag: When EF is LOW, the Queue is empty. EF is synchronized to RCLK.
FF Output Full flag: When FF is LOW, the Queue is full. FF is synchronized to WCLK.
SPI_SCLK Input Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the offset
registers if SPI_SEN is enabled.
CYF2018V
CYF2036V
CYF2072V
Document Number: 001-68336 Rev. *F Page 6 of 32
Architecture
The CYF2072V, CYF2036V, and CYF2018V are memory arrays
of 72-Mbit, 36-Mbit, and 18-Mbit respectively. The memory
organization is user configurable and word sizes can be selected
as × 9, × 12, × 16, × 18, × 20, × 24, × 32, or × 36. The logic blocks
to implement the FIFO functionality and the associated features
are built around these memory arrays.
The input and output data buses have a maximum width of
36 bits. The input data bus goes to an input register and the data
flow from the input register to the memory is controlled by the
write control logic. The inputs to the write logic block are WCLK,
WEN, IE and WQSEL[2:0]. When the writes are enabled through
WEN and inputs are enabled through IE, data on the input bus
is written into the FIFO queue indicated by WQSEL[2:0] at the
rising edge of WCLK. This also increments the write pointer for
the corresponding FIFO queue. Enabling writes but disabling the
data input through IE only increments the write pointer without
doing any writes or altering the contents of the location.
Similarly, the output register is connected to the data output bus.
Transfer of contents from the memory to the output register is
controlled by the read control logic. The inputs to the read control
logic include RCLK, REN, RQSEL[2:0], MARK and RT.
RQSEL[2:0] selects the Queue to be read. When reads are
enabled by REN and outputs are enabled through OE, data from
the FIFO queue is transferred to the output data bus at the rising
edge of RCLK along with active low DV al. Qval[2:0] indicates the
Queue number to which the read data belongs. If OE is disabled
and the reads are enabled, the outputs are in high impedance
state, but internally the read pointer for the corresponding
RQSEL[2:0] is incremented.
The MARK signal is used to ‘mark’ the location from which d ata
can be retransmitted when requested and RT is asserted to
retransmit the data from the marked location.
During write operation, the number of writes performed is always
an even number (i.e., minimum write burst length is two and
number of writes always a multiple of two). Whereas during read
operation, the number of reads performed can be even or odd
(i.e., minimum read burst length is one).
It is possible to divide the whole memory space into 2, 4 or 8
equal sized arrays. By default, the FIFO is accessed as a 8Q
device. For more explanation please refer to Multi-Queue
Operation on page 7.
Reset Logic
A Master Reset cycle is required after power up before accessing
the FIFO. MRS resets the configuration registers which
configures the device to Multi-Queue (8Q) mode and sets the
output register to zero. It also initializes the read and write
pointers to ze ro, and sets the flags to their defa ult condition (FF
deasserted and EF asserted) for all eight Queues. The mark
address is also set to the default physical location for each
queue.
After MRS, a minimum latency of 1024 clocks is necessary
before the first access. The word size is configured through
PORTSZ pins; values of the three PORTSZ pins are latched on
rising edge of MRS.
SPI_SI Input Serial input: Serial input when SPI_SEN is enabled.
SPI_SEN Input Serial enable: Enables serial loading of configuration registers.
TCK Input Test clock (TCK) pin for JTAG.
TRST Input Reset pin for JTAG.
TMS Input Test mode select (TMS) pin for JTAG.
TDI Input Test data in (TDI) pin for JTAG.
TDO Output Test data out (TDO) for JTAG.
VREF Input
Reference Reference voltage: Reference voltage of 0.75V (regardless of I/O standard used).
VCC1 Power
Supply Core voltage supply 1: 1.8 V supply voltage
VCC2 Power
Supply Core voltage supply 2: 1.5 V supply voltage
VCCIO Power
Supply Supply for I/Os
VSS Ground Ground
DNU – Do not use: These pins need to be left floating.
Pin Definitions (continued)
Pin Name I/O Pin Descripti on
CYF2018V
CYF2036V
CYF2072V
Document Number: 001-68336 Rev. *F Page 7 of 32
Multi-Queue Operation
In this mode, the entire memory space is divided into equal sized
memory arrays and each individual memory array can be
accessed as an independent FIFO. These equally sized memory
arrays are referred to as Queues and they are numbered
Queue-0 to Queue-7. For example, when the 72M device, is
configured in eight queue mode, the entire memory space of 72M
is divided into eight memory arrays of 9M capacity. These
queues can be accesse d independently usin g the queue select
signals WQSEL[2:0] and RQSEL[2:0].
It is also possible to configure the whole memory space of
CYF2072V into 4 or 2 equal sized arrays. This is equivalen t to
having four or two independent Queues inside the FIFO.
The device can be used as a single FIFO by configuring the FIFO
in single queue mode . In this case, the entire memo ry space is
accessed as a single Queue.
The number o f Qu eues is confi gure d based on the value of D2,
D1 & D0 bit of configuration register 0x3 (refer to Table 2 on page
9). Table 3 on page 9 shows the va lue to be set in D2, D1 & D0
of configuration register 0x3 to configure the device in 1/2/4/8
Queue modes.
Selecting Word Sizes
The word sizes are configured based on the logic levels on the
PORTSZ pins during the master reset (MRS) cycle only (latched
on low to high edge). The port size cannot be changed during
normal mode of operation and these pins are ignored. Table 1
explains the pins of D[35:0] and Q[35:0] that will have valid data
in modes where the word size is le ss than × 36. If word size is
less than × 36, the unused output pins are tri-stated by the
device.and unused input pins will be ignored by the internal logic.
The pins with valid data input D[N:0] a nd output Q[N:0] is given
in Table 1.
Memory Organization for Differen t Port Sizes
The 72-Mbit memory has different organizations for different port
sizes. Table 1 shows the depth of the FIFO for all port sizes.
Note that for all port sizes, four to eight locations are not available
for writing the data and are used to safeguard against false
synchronization of empty and full flags.
Data Valid Signal (DVal)
Data valid (DV al) is an active LOW signal, synchronized to RCLK
signal and is provided to check for the data on output bus. When
a read operation is performed, the DVal signal goes low along
with output data. This helps user to capture the data without
having to keep track of REN to data output latency. This signal
also helps when write and read operations are performed
continuously at different frequencies by indicating when valid
data is available at the output port Q[35:0]. In multi-queue mode,
this signal should be used along with Queue Valid Signal
(QVal[2:0]) to determine the queue from which data is being
read.
Queue Valid Signal (QVal[2:0])
Queue Valid (Qval[2:0]) is a three bit output that indicates the
Queue from which valid data is being read. When DVal signal is
high, the values on this bus should be ignored.
Write Mask and Read Skip Operation
As mentioned in Architecture on page 6, enabling writes but
disabling the inputs (IE HIGH) increments the write pointer
without doing any write operations or altering the contents of the
location.
This feature is called Write Mask and allows user to move the
write pointer withou t actually writing to th e locatio ns. Thi s “w rite
masking” ability is useful in some video applications such as
Picture In Picture (PIP).
Similarly , during a read operation, if the outputs are disabled (OE
high). The read data does not appear on the output bus;
however , the read pointer is incremented. This feature is referred
to as a Read Skip Operation.
Table 1. FIFO Depth - Word Size & Operating Mode
PORTSZ[2:0] Word Size FIFO Depth/qu eu e [3]
(No. of locations) Memory Size [3] Active Input
Data Pins D[N:0] Active Output
Data Pins Q[N:0]
1Q mode 2Q mode 4Q mode 8Q mode
000 × 9 8 M 4 M 2 M 1 M 72-Mbit D[8:0] Q[8:0]
001 × 12 4 M 2 M 1 M 512 K 48-Mbit D[11:0] Q[11:0]
010 × 16 4 M 2 M 1 M 512 K 64-Mbit D[15:0] Q[15:0]
011 × 18 4 M 2 M 1 M 512 K 72-Mbit D[17:0] Q[17:0]
100 × 20 2 M 1 M 512 K 256 K 40-Mbit D[19:0] Q[19:0]
101 × 24 2 M 1 M 512 K 256 K 48-Mbit D[23:0] Q[23:0]
110 × 32 2 M 1 M 512 K 256 K 64-Mbit D[31:0] Q[31:0]
111 × 36 2 M 1 M 512 K 256 K 72-Mbit D[35:0] Q[35:0]
Note
3. For all port sizes, four to eight locations are not available for writing the data.
CYF2018V
CYF2036V
CYF2072V
Document Number: 001-68336 Rev. *F Page 8 of 32
Flow-through mailbox Register
This register transfers data from input to output directly
bypassing the FIFO sequence. When MB signal is asserte d the
data present on D[35:0] will be available on Q[35:0] after two
WCLK cycles. Normal read and write operations are not allowed
during flow-through mailbox operation. Before starting
Flow-through mailbox operation FIFO read should be completed
to make data valid (DVal) high in order to avoid data loss from
FIFO. The width of flow-through mailbox register always
corresponds to port size.
Flag Operation
This device provides two flags to indicate the condition of the
FIFO Queues.
Full Flag
Full Flag (FF) LOW indicates whether the queue accessed by
WQSEL[2:0] is full and it operates on double wo rd (burst length
of two) boundaries. Write operations are inhibited whene ver FF
is LOW regardless of the state of WEN. FF is synchronized to
WCLK, that is, it is exclusively updated by each rising edge of
WCLK. The worst case assertion latency for Full Flag is four. As
the user cannot know that the FIFO is full for four clock cycles, it
is possible that user continues writing data during this time. In
this case, the four data words written will be stored to prevent
data loss and these words have to be read ba ck in order fo r full
flag to get de-asserted. In 2Q or 4Q or 8Q mode, FF indicates
the status of the queue sele cted by W QSEL[2:0]. Th e mini mum
number of reads required to de-assert full-flag are two and the
maximum number of reads required to de-assert full flag are six.
The assertion and de-assertion latencies of Full Fla g are given
in Latency Table on page 15.
Empty Flag
Empty Flag (EF) LOW indicates that the queue accessed by
RQSEL[2:0] is empty and its de-assertion depends on burst
writes. Read operations are inhibited whenever EF is LOW,
regardless of the state of REN. EF is synchronized to RCLK, i.e.,
it is exclusively updated by each rising edge of RCLK. In
2Q/4Q/8Q mode, EF indicates the status of the queue selected
by RQSEL[2:0]. The assertion and de-assertion latencies of
Empty Flag are given in Latency Table on page 15.
Retransmit from Mark Operation
The retransmit feature is useful fo r transferring packets of data
repeatedly. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Initiation of a
retransmit operation (using RT pin) resets the internal read
pointer to a physical l ocation of the FIFO that is marked by the
user (using the MARK pin).
The retransmit feature can be used when two or more data words
have been written to the queue. When the MARK pin is asserted,
the memory location corresponding to valid data (DVal signal
LOW) present on the output bus is marked. QV al[2:0] signals can
be used to validate the queue for which the mark operation is
being performed. A mark operation is mandated prior to initiating
a retransmit operation for a queue.
In this device the RT signal is validated with RQSEL[2:0], i.e.,
Retransmit function will be performed for the Queue that is
selected by RQSEL[2:0]. With every valid read cycle after
retransmit, previously accessed data is read until the queue
becomes empty. Data written to the queue (Queue on which
retransmit operation is being performed) after activation of RT
are also transmitted. The full depth of the queue can be
repeatedly retransmitted. Flags are governed by the relative
locations of the read and write pointers and are updated during
a retransmit cycle. Refer to the latency table for the associated
flag update latencies after initiation of a retransmit cycle [4].
A retransmit operation should not be initiated when reads or
writes are in progress. User should wait for four RCLK cycles
after disabling reads before RT is asserted to ensure that the
reads are completed.
On initiation of RT the ‘marked’ location becomes the new Full
Boundary. If user continues to write the data after initiati on of a
retransmit operation, FF will be asserted when this boundary is
reached i.e. FF is asserted once the write pointer reaches the
marked location.This prevents overwriting and data-loss. During
RT reads the full boundary remains frozen to the marked location
and is released when the FIFO becomes empty. i.e. FF remains
LOW until the entire FIFO is read. Full flag is deasserted
LFF_RELEASE cycles after the EF is asserted. Full boundary is
also released on a reset operation (MRS) [4].
Refer to Latency Table on page 15 for more details.
Programming Configuration Registers
The CYF2072V has ten 8-bit user configurable registers. These
registers are used to configure the number of queues & to set the
Fast CLK Bit.
These registers can be programmed in one of two ways: serial
loading or parallel loading method. The loading method is
selected using the SPI_SEN (Serial Enabl e) pin. A LOW on the
SPI_SEN selects the serial method for writing into the reg isters
whereas a HIGH on SPI_SEN selects parallel loading method.
For serial programming, there i s a separate SCLK and a Serial
Input (SI). In parallel mode, the load (LD) pin is used to perform
write and read operations on these registers. The write and read
operations are performed in a sequence from the first
location(0x1) to the last location (0xA) when the LD pin is held
LOW. If LD is HIGH, the FIFO queues are written or read.
Register values can be read through the parallel output port
regardless of the programming mode selected (serial or parallel).
Register values cannot be read serially. The configuration
registers should be programmed only once after master reset to
ensure accurate flag operation, regardless of whether serial or
parallel programming is selected.
See Table 4 on page 10 and Table 5 on page 11 for access to
configuration registers in serial and parallel modes.
In parallel mode, the read an d write operations loop back when
the maximum address location of the configuration registers is
reached. Simultaneous read and write operations must be
avoided on the configuration registers. Any change in
configuration registers will take effect after eight write clock
cycles (WCLK) cycles.
Notes
4. Errata: Refer to Errata on page 30 for details on flag operation and full boundary freezing during mark and retransmit operation.
CYF2018V
CYF2036V
CYF2072V
Document Number: 001-68336 Rev. *F Page 9 of 32
Table 2. Configuration Registers
ADDR Configuratio n Register Default Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0]
0x1Reserved 0x00 XXXXXXXX
0x2Reserved 0x00 XXXXXXXX
0x3 Number of Queues 0x07 X X X X X D2 D1 D0
0x4Reserved 0x7F XXXXXXXX
0x5Reserved 0x00 XXXXXXXX
0x6Reserved 0x00 XXXXXXXX
0x7Reserved 0x7F XXXXXXXX
0x8Reserved 0x00 XXXXXXXX
0x9Reserved 0x00 XXXXXXXX
0xA Fast CLK Bit Register 1XXXXXXXb Fast
CLK bit XXXXXXX
Table 3. Multi-Queue Configuratio n
Operating Mode
(given by configuration register 0x3 [7:0]) RQSEL[2:0]/WQSEL[2:0] Queue Number Selected
1Q mode
(register 0x3[2:0] = 8’b0000 0000) 000 0
001–111 Invalid
2Q mode
(register 0x3[2:0] = 8’b0000 0001) 000 0
001 1
010–111 invalid
4Q mode
(register 0x3[2:0] = 8’b0000 001X) 000 0
001 1
010 2
011 3
100–111 invalid
8Q mode
(register 0x3[2:0] = 8’b0000 01XX) 000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
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Table 4. W r iti ng a nd Rea ding Configuration Reg is te rs in Parallel Mode
SPI_SEN LD WEN REN WCLK RCLK SPI_SCLK Operation
1 001 First rising edge
because both LD and
WEN are low
X X Parallel write to first register
1 001 Second rising edge X X Parallel write to second register
1 001 Third rising edge X X Parallel write to third register
1 001 Fourth rising edge X X Parallel write to fourth register
1 001 XX
1 001 XX
1 001 XX
1 001 Tenth rising edge X X Parallel write to tenth register
1 001 Eleventh rising edge X X Parallel write to first register (roll
back)
1 010 X First rising edge
since both LD and REN
are low
X Parallel read from first register
1 010 X Second rising edge X Parallel read from second
register
1 010 X Third rising edge X Parallel read from third register
1 010 X Fourth rising edge X Parallel read from fourth register
1 010 X X
1 010 X X
1 010 X X
1 010 X Tenth rising edge X Parallel read from tenth register
1 010 X Eleventh rising edge X Paral lel read from first register
(roll back)
1 X 1 1 X X X No operation
X10X Rising edge X X Write to FIFO memory
X1X0 X Rising edge X Read from FIFO memory
0 0 X 1 X X X Illegal operation
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Width Expansion Configuration
The width of CYF2072V can be expanded to provide word widths
greater than 36 bits. During width expansion mode, all control
line inputs are common and all flags are availa ble. Empty (Full)
flags are created by ANDing the Empty (Full) flags of every FIFO.
This technique avoids reading data from or writing data to the
FIFO that is “staggered” by one clock cycle due to the variations
in skew between RCLK and WCLK. Figure 3 demonstrates an
example of a 72 bit-word width by using two 36-bit word
CYF2072Vs.
Table 5. Writing into Configuration Registers in Serial Mode
SPI_SEN LD WEN REN WCLK RCLK SCLK Operation
01XX X X Rising edge Each rising of the SCLK clocks
in one bit from the SI (Serial In).
Any of the 10 registers can be
addressed and written to,
followin g th e SPI protocol.
X10X
Rising edge X X Parallel write to FIFO memory.
X1X0 X Rising edge X Parallel read from FIFO
memory.
1 0 1 1 X X X This corresponds to parallel
mode (refer to Table 4 on page
10).
Figure 2. Serial WR ITE to Configuration Reg ister
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Power Up
The device becomes functional after VCC1, VCC2, VCCIO, and
Vref attain minimum stable voltage required as given in
Recommended DC Operating Conditions on page 14. The
device can be accessed in tPU time after these supplies attain the
minimum required level (see Switch ing Characteristics on page
17). There is no power sequencing required for the device.
Read/Write Clock Requirements
The read and write clocks must satisfy the following
requirements:
■Both read (RCLK) and write (WCLK) clocks should be
free-running.
■The clock frequency for both clocks should be between the
minimum and maximum range given in Switching
Characteristics on page 17.
■The RCLK to WCLK ratio should be in th e range of 0.5 to 2.
For proper FIFO operation, the device must determine which of
the input clocks – RCLK or WCLK – is faster. This is evaluated
by using counters after the MRS cycle. The device uses two 9-bit
counters inside (one running on RCLK and other on WCLK),
which count 256 cycles of read and write clock after MRS. The
clock of the counter which reaches its terminal count first is used
as master clock inside the FIFO.
When there is change in the relative frequency of RCLK and
WCLK during normal operation of FIFO, user can specify it by
using “Fast CLK bit” in the configuration register (0xA).
“1” - indicates freq (WCLK) > freq (RCLK)
“0” - indicates freq (WCLK) < freq (RCLK)
The result of counter evaluated frequency is available in this
register bit. User can override the counter evaluated frequency
for faster clock by changing this bit.
Whenever there is a change in this bit value, user must wait tPLL
time before issuing the next read or write to FIFO.
Figure 3. Using Two CYF2072Vs for Width Expansion
FF
FF EF EF
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
FF
CYF2072V CYF2072V
3672
DATAIN (D) 36 READCLOCK(RCLK)
READENABLE(REN)
OUTPUTENABLE(OE)
36
DATAOUT(Q)
36 72
EF
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JTAG operation
CYF2XXXVXXL has two devices connected internally in a JTAG chain as shown in Figure 4.
Figure 4. JTAG Operation
Table 6 shows the IR register length and device ID.
For boundary scan, device-1 should be in bypass mode.
Table 7 and Table 8 shows the JTAG instruction set for devices 1 and 2 respectively.
Table 6. JTAG IDCODES
IR Register length Device ID (HEX) Bypass register length
Device-1 3 “Ignore” 1
Device-2 8 1E3261CF 1
Table 7. JTAG Instru ctions
Device-1 Opcode (Binary)
BYPASS 111
Table 8. JTAG Instru ctions
Device-2 Opcode (HEX)
EXTEST 00
HIGHZ 07
SAMPLE/PRELOAD 01
BYPASS FF
IDCODE 0F
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperatur e (without bias) ........ –65 C to +150 C
Ambient temperature with
power applied .........................................–55 C to +125 C
Core supply voltage 1 (VCC1) to
ground potential .............................................–0.3 V to 2.5 V
Core supply voltage 2 (VCC2) to
ground potential .................. ... .............. ... .. ...–0.3 V to 1.65 V
Latch-up current .................................................> 100 mA
I/O port supply voltage (VCCIO) ....................–0.3 V to 3.7 V
Voltage applied to I/O pins ...........................–0.3 V to 3.75 V
Output current into outputs (LOW) .............................20 mA
Static discharge voltage
(per MIL–STD–883, Method 3015) .........................> 2001 V
Operating Range
Range Ambient Temperature
Industrial –40 C to +85 C
Recommended DC Operating Conditions
Parameter [5] Description Min Typ Max Unit
VCC1 Core supply voltage 1 1.70 1.80 1.90 V
VCC2 Core supply voltage 2 1.425 1.5 1.575 V
VREF Reference voltage (irrespective of I/O standard used) 0.7 0.75 0.8 V
VCCIO I/O supply voltage, read and write banks. LVCMOS33 3.00 3.30 3.60 V
LVCMOS18 1.70 1.8 1.90 V
Electrical Characteristics
Parameter Description Conditions Min Typ Max Unit
ICC Active current VCC1 = VCC1MAX – – 300 mA
VCC2 = VCC2MAX,
All I/O switching, 100 MHz – – 500 mA
VCCIO = VCCIOMAX
(All outputs disabled) – – 100 mA
IIInput pin leakage current VIN = VCCIOmax to 0 V –15 – 15 µA
IOZ I/O pin leakage current VO = VCCIOmax to 0 V –15 – 15 µA
CPCapacitance for TMS and TCK – – – 16 pF
CPIO Capacitance for pins ap art from TMS
and TCK –––8pF
Note
5. Device operation guaranteed for a supply rate > 1 V / µs.
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I/O Characteristics
I/O standard Nominal I/O
supply
voltage
Input Voltage (V) Output voltage (V) Output Current (mA)
VIL(max) VIH(min) VOL(max) VOH(min) IOL(max) IOH(max)
LVCMOS33 3.3 V 0.80 2.20 0.45 2.40 24 24
LVCMOS18 1.8 V 30% VCCIO 65% VCCIO 0.45 VCCIO – 0.45 16 16
Latency Table
Latency Parameter Number of cycles [6] Details
LFF_ASSERT Max = 4 Last data write to FF going low
LEF_ASSERT 0 Last data read to EF going low
LRQSEL_CHANGE 1 Minimum RCLK cycles before RQSEL[2:0] can change
LWQSEL_CHANGE 2 Minimum WCLK cycles before WQSEL[2:0] can change
LMAILBOX 2 Latency from write port to read port when MB = 1 (w.r.t. WCLK)
LREN_TO_DATA 4 Latency w hen REN is asserted low to first data output from FIFO
LREN_TO_CONFIG 4 Latency when REN is asserted along with LD to first data read from configuration
registers
LFF_DEASSERT 7 Read to FF going high
LRT_TO_REN 21 First RCLK posedge after RT goes low to initiation of reads by pulling REN low.
Flags update within this period after initiation of a retransmit operation .
LRT_TO_DATA Max = 25 First RCLK posedge after RT goes LOW to valid data on Q[35:0].
LIN Max = 35 Initial latency for data read after FIFO goes empty during simultaneous read/write
LEF_DEASSERT Max = 32 Write to EF going high
LFF_RELEASE[7] Max = 6 EF going low to FF de-assert during retransmit reads.
Note
6. Latency mentioned in th e latency t able are applicable for clock ratio of 1.
7. Errata: Refer to errata section for details on flag operation & full boundary freezing during mark & retran smit operation.
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AC Test Load Conditions
Figure 5. AC Test Load Condi ti ons
(a) VCCIO = 1.8 Volt
(b) VCCIO = 3.3 Volt
(c) All Input Pulses
30
0.9 V
30
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Switching Characteristics
Over the Operating Range
Parameter Description -100 Unit
Min Max
tPU Power-up time after all supplies reach minimum value – 2 ms
tSClock cycle frequency 3.3 V LVCMOS 24 100 MHz
tSClock cycle frequency 1.8 V LVCMOS 24 100 MHz
tA Data access time – 10 ns
tCLK Clock cycle time 10 41.67 ns
tCLKH Clock high time 4.5 – ns
tCLKL Clock low time 4.5 – ns
tDS Data setup time 3 – ns
tDH Data hold time 3 – ns
tQS RQSEL and WQSEL setup time 3 – ns
tQH RQSEL and WQSEL hold time 3 – ns
tENS Enable setup time 3 – ns
tENH Enable hold time 3 – ns
tENS_SI Setup time for SI and SEN in SPI mode 5 – ns
tENH_SI Hold time for SI and SEN in SPI mode 5 – ns
tRATE_SPI Frequency of SCLK – 25 MHz
tRS Reset pulse width 100 – ns
tPZS Port size select to MRS setup time 25 – ns
tPZH MRS to port size select hold time 25 – ns
tRSF Reset to flag output time – 50 ns
tPRT Retransmit pulse width 5 – RCLK
cycles
tOLZ Output enable to output in Low Z 4 15 ns
tOE Output enable to output valid – 15 ns
tOHZ Output enable to output in High Z – 15 ns
tWFF Write clock to FF –9.5ns
tREF Read clock to EF –9.5ns
tPLL Time required to synchronize PLL – 1024 cycles
tRATE_JTAG JTAG TCK cycle time 100 – ns
tS_JTAG Setup time for JTAG TMS,TDI 8 – ns
tH_JTAG Hold time for JTAG TMS,TDI 8 – ns
tCO_JTAG JTAG TCK low to TDO valid – 20 ns
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Switching Waveforms
Figure 6. Write Cycle Timing
Figure 7. Read Cycle Timing
Figure 8. Reset Timing
tCLKH tCLKL
NO OPERATION
tDS
tENS
WEN
, IE
tCLK
tDH
tENH
WCLK
D[35:0]
NO OPERATION
t
CLK
t
OHZ
RCLK
Q[35:0]
REN
OE
t
ENS
t
OLZ
t
A
t
ENH
VALID DATA
L
REN_TO_DATA
DVal
t
RS
Q[35:0]
MRS
t
RSF
t
RSF
t
RSF
OE=1
OE=0
EF
FF
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Figure 9. MRS to PORTSZ[2:0]
Figure 10. Flow-through mailbox Operation
Switching Waveforms (continued)
WCLK/RCLK
PORTSZ[2:0]
MRS
tPZS
tPZH
WCLK
D[35:0]
REN / WEN
MB
DO D1 D3
Q4Q1 Q2QO Q3
Q[35:0]
D2 D4
DVal
123
L MAILBOX
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Figure 11. Configuration Registe r Write
Figure 12. Conf iguration Register Read
Figure 13. WQSEL to FF
Switching Waveforms (continued)
LD
D[35:0] config-reg 0 config-reg 1 config-reg 2 config-reg 3 config-reg 4 config-reg 5
WCLK
WEN / IE
tENS
tDS tDH
WCLK
/RCLK
REN
LD
Q[35:0] Reg - 1
LREN_TO_CONFIG
543210
FF for QUE-5
FF for QUE-4
FF for QUE-3
FF for QUE-2
FF for QUE-1
FF for QUE-0
t
QS
t
WFF
WCLK
WQSEL[2:0]
FF
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Figure 14. RQSEL to EF
Figure 15. Write to Empty Flag De-assertion
Switching Waveforms (continued)
EF for QUE-6
EF for QUE-5
EF for QUE-4
EF for QUE-3
EF for QUE-2
4
276543
3210
10
RCLK
RQSEL[2:0]
EF EF for QUE-1
EF for QUE-0
tQS tREF
L REN_TO_DATA
D1D0
0
WCLK
RCLK
REN
EF
D[35:0]
WEN
0 1 2 3 4
EF for QUE-0
WQSEL[2:0]/
RQSEL[2:0]
LEF_DEASSERT
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Figure 16. Read to Empty Flag Assertion
Figure 17. Full Flag Assertion
Switching Waveforms (continued)
0
WQSEL[2:0]/
RQSEL[2:0]
RCLK
012
Q[35:0]
Q0
DVal
EF EF for QUE-0
REN
t
REF
L
REN_TO_DATA
0
QVal[2:0] 7
7
L
FF_RELEASE
FF
8
D
0
0
WQSEL[2:0]/
RQSEL[2:0]
WCLK
WEN
D[35:0] D
1
D
2
D
x
D
LAST-1
D
LAST
NOT
WRITTEN
NOT
WRITTEN
tWFF
FF
Note
8. Errata: Refer to Errata on page 30 for details on flag operation and full boundary freezing during Mark and Retransmit operation.
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Figure 18. Full Flag De-a ssertion
Figure 19. Switching between Queues - Write
Switching Waveforms (continued)
0
WQSEL[2:0]/
RQSEL[2:0] 0
WQSEL[2:0]/
RQSEL[2:0]
WCLK
WEN
D[35:0]
FF
D
LAST-4
D
LAST-3
D
LAST-2
D
LAST-1
D
LAST
RCLK
REN
LFF_DEASSERT
2-6 READS
D1
D0
D1
D0
D1
D0
D1
D0
D1
D0
D1
D0
WQSEL[2:0]
DATA for QUE-5DATA for QUE-4DATA for QUE-3DATA for QUE-2DATA for QUE-1DATA for QUE-0
WCLK
543210
D[35:0]
WEN
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Figure 20. Switching between Queues - Read
Switching Waveforms (continued)
Q0 Q0Q0 Q0Q0 Q0Q0 Q0
QVal[2:0]
DVal tQS
2654310
Q[35:0]
QUE-5 DATA QUE-3 DATA QUE-1 DATA
7
QUE-6 DATA QUE-4 DATA QUE-2 DATA QUE-0 DATA
5
26543
4321
10
RCLK
RQSEL[2:0]
REN L REN_TO_DATA
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Figure 21. Simultaneous Write & Read QUE - 0
Switching Waveforms (continued)
00
WQSEL[2:0]/
RQSEL[2:0]
WCLK
WEN
D[35:0] D
0
D
1
D
2
D
3
RCLK
REN
Q
0
Q
1
Q
2
Q
3
D
N
D
N+1
D
N+2
D
N+
3
Q[35:0]
DVal
L IN (initial latency)
0
QVal[2:0] 7
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Figure 22. Mark
Figure 23. Retransmit
Switching Waveforms (continued)
0
RQSEL[2:0] 0
DVal
RCLK
MARK
REN
Q[35:0] Q (N-1) Q (N) Q (N+1)
DATA MARKED IN QUE-0
Q (N+3)
Q (N+2) Q (N+5)
Q (N+4) Q (N+6)Q (N-2)
0
QVal[2:0] 7
RETRANSMIT FROM
DATA MARKED
Q (N+1)
Q (N)
DVal
RT
RCLK
REN
Q[35:0]
tPRT LRT_TO_REN
LRT_TO_DATA
RQSEL[2:0] 0
7
QVal[2:0] 1
FLAGS UPDATED AFTER RT
All Flags
0
9
9
Note
9. Errata: Refer to Errata on page 30 for details on flag operation and full boundary freezing during Mark and Retransmit operation.
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Ordering Information
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
100 CYF2072V33L-100BGXI 51-85167 209-ball FBGA (14 × 22 × 1.76 mm) Industrial
Ordering Code Definitions
I/O Voltage:
V18 = 1.8 V
Density:
018 = 18 M
Cypress
CY F X XXX VXX X - XXX BGXI
FIFO
I/O Standard:
L = LVCMOS
036 = 36 M
072 = 72 M
V33 = 3.3 V
Speed:
100 MHz
2 - Multi-Queue (8 queues)
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Package Diagram
Figure 24. 209-ball FBGA (14 × 22 × 1.76 mm) BB209A Packa ge Outline, 51-85167
51-85167 *C
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Acronyms Document Conventions
Units of Measure
Acronym Description
EF Empty Flag
FF Full Flag
FIFO First In First Out
IE Input Enable
I/O Input/Output
FBGA Fine-Pitch Ball Grid Array
JTAG Joint Test Action Group
LVCMOS Low Voltage Complementary Metal Oxide
Semiconductor
MB Mailbox
MRS Master Reset
OE Output Enable
REN Read Enable
RCLK Read Clock
RQSEL Read Queue Select
SCLK Serial Clock
TDI Test Data In
TDO Test Data Out
TCK Test Clock
TMS Test Mode Select
WCLK Write Clock
WEN Write Enable
WQSEL Write Queue Select
QUE-0 Queue Number 0
QUE-1 Queue Number 1
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
Amicroampere
mA milliampere
mm millimeter
ms millisecond
ns nanosecond
ohm
pF picofarad
Vvolt
Wwatt
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Errata
This section describes the errata for the 18-Mbit, 36-Mbit, and 72-Mbit programmable FIFOs. Details include errata trigger conditions,
scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative or raise a
technical support case at www.cypress.com/supp ort if you have questions.
Part Numbers Affected
18-Mbit, 36-Mbit, and 72-Mbit Programmable FIFO Qu alification Status
Product Status: In Production
18-Mbit, 36-Mbit, and 72-Mbit Programmable FIFO Errata Summary
This table defines the errata applicability to available 18-Mbit, 36-Mbit, and 72-Mbit Programmable FIFO family devices. An "X"
indicates that the erratum pertains to the selected device.
Note Errata items, in the following table, are hyperlinked. Click on any item entry to jump to its description.
1. Retransmit Issue
■Problem Definition
Flag Failure during Retransmit cycles: Flags (PAE, HF, PAF, and FF) are not updated during a retransmit cycle. These flags do not
recover on completion of retransmit cycles. The functionality of Empty Flag (EF) and Data Valid signal (DVal) remain intact
throughout device operation.
■Parameters Affected
Because flags (PAE, HF, P AF, and FF) are not updated during a retransmit cycle, their associated latencies and timing parameters
are not app l ica b le.
■Trigger Condition
Initiation of a retransmit cycle using RT signal.
■Scope of Impact
On initiation of a retransmit cycle, flags (PAE, HF, PAF, and FF) may not accurately reflect FIFO status. Customer applications
relying on these flags to keep track of number of words in the FIFO during retransmit may observe errors because these flags are
not updated. The failure mandates a reset cycle (Partial Reset for Single queue and Master Reset for Multi queue devices) to
ensure flag recovery after a retransmit cycle, that is, to restore flag functionality and resume normal FIFO operations after
completion of retransmit cycles.
■Workaround
During retransmit cycles, there is no workaround to restore PAE, HF, PAF, and FF functionalities.
After completion of retransmit cycles, a reset cycle (Partial Reset for Single queue and Master Reset for Multi queue devices) can
be performed to restore PAE, HF, PAF, and FF functionalities for normal FIFO operation.
■Fix Status
The fix for the retransmit issue is in progress. In devices wi th the de sign fix, the i ntended flag functiona lity will be restor ed d uring
retransmit cycles. Reset will not be mandatory after a retransmit cycle to resume normal FIFO operation. Fixed devices will be
available from February 04, 2013.
Part Number Device Characteristics
CYF0018V33L-133BGXI 18-Mbit Programmable Singl e-Queue FIFOs (3.3-V LVCMOS)
CYF0018V18L-133BGXI 18-Mbit Programmable Singl e-Queue FIFO (1.8-V LVCMOS)
CYF0036V33L-133BGXI 36-Mbit Programmable Singl e-Queue FIFO (3.3-V LVCMOS)
CYF0072V33L-133BGXI 72-Mbit Programmable Singl e-Queue FIFO (3.3-V LVCMOS)
CYF0072V18L-133BGXI 72-Mbit Programmable Singl e-Queue FIFO (1.8-V LVCMOS)
CYF2072V33L-100BGXI 72-Mbit Programmable Eight-Qu eue FIFO (3.3-V LVCMOS)
Items Part Numbers Silicon Revision Fix Status
1. Retransmit Issue CYF0018V, CYF0036V,
CYF0072V, CYF2072V XFix in progress.
Fixed devices to be available from February 04, 2013
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Document History Page
Document Title: CYF2018V/CYF2036V/CYF2072V, 18/36/72-Mbit Programmable Multi-Queu e FIFOs
Document Number: 001-68336
Rev. ECN No. Orig. of
Change Submission
Date Description of Change
** 3209860 SIVS 03/30/2011 New da ta sheet.
*A 3353401 AJU 08/26/2011 Updated Package Diagram.
*B 3387127 AJU 09/28/2011 Updated Pin Diagram for CYF2XXXVXXL (Added Note 2 and referred the
same note in DNU in ball U6).
Updated Multi-Queue Operation (Updated Table 4 (WCLK column in first row)).
Updated Recommended DC Operating Conditions (Added Note 5 and referred
the same note in Parameter column).
Updated Switching Waveforms (Removed the clock cycle numbers in
Figure 10, Figure 14, Figure 15, Figure 16, and Figure 20).
*C 3652368 ADMU 08/16/2012 Updated Pin Diagram for CYF2XXXVXXL (Updated Figure 1 (W9 ball marked
as DNU)).
Updated Figure 5.
*D 3997615 ADMU 05/11/2013 Updated Package Diagram:
spec 51-85167 – Changed revision from *B to *C.
Added Errata.
*E 4080484 ADMU 07/29/2013 Added Errata footnotes (Note 4, 7, 8, 9).
Updated Pin Diagram for CYF2XXXVXXL:
Added Note 1 and referred the same note in Figure 1.
Updated Functional Description.
Updated Logic Block Diagram.
Updated Architecture.
Updated Retransmit from Mark Operation:
Added Note 4 and referred the same note in 3rd paragraph and 5th paragraph.
Updated Programming Configuration Registers:
Updated Table 2 (Changed value of Register 0x3 from “0x00” to “0x07” in the
column “Default”).
Updated Latency Table:
Added Note 7 and referred the same note in the Latency parameter
“LFF_RELEASE”.
Updated Switching Waveforms:
Updated Figure 14, Figure 15, Figure 16, Figure 18, Figure 21, Figure 22,
Figure 23.
Added Note 8 and referred the same note in “LFF_RELEASE” in Figure 16.
Added Note 9 and referred the same note in “All Flags” and “FLAGS UPDATED
AFTER RT” in Figure 23.
Updated Ordering Information (Updated part numbers).
Updated in new template.
*F 4339515 ADMU 04/10/2014 No technical updates.
Completing Sunset Review.
Document Number: 001-68336 Rev. *F Revise d April 10, 2014 Page 32 of 32
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