935293259151 - NXP SEMICONDUCTORS

1. General description

The LPC122x ex ten d NXP's 32- bit ARM micr oc on tr olle r co nt inu um an d target a wide

range of industrial applications in the areas of factory and home automation. Benefitting

from the ARM Cortex-M0 Thumb instruction set, the LPC122x have up to 50 % higher

code density compared to common 8/16-bit microcontroller performing typical tasks. The

LPC122x also feature an optimized ROM-ba sed divide libra ry for Cortex- M0, which offers

several times the arithmetic performance of software-based libraries, as well as highly

deterministic cycle time combined with reduced flash code size. The ARM Cortex-M0

efficiency also helps the LPC122x achieve lower average power for similar applications.

The LPC122x operate at CPU frequencies of up to 45 MHz.They offer a wide range of

flash memory options, from 32 kB to 128 kB. The small 512-byte page erase of the flash

memory brings multiple design benefits, such as finer EEPROM emulation, boot-load

support from any serial interface and ease of in-field programming with reduced on-chip

RAM buffer requirements.

The peripheral complement of the LPC122x includes a 10-bit ADC, two comparators with

output feedback loop, two UARTs, one SSP/SPI interface, one I2C-bus interface with

Fast-mode Plus features, a Windo wed W a tchdog Timer, a DMA controller, a CRC engin e,

four general purpose timers, a 32-bit RTC, a 1 % internal oscillator for baud rate

generation, and up to 55 General Purpose I/O (GPIO) pins.

2. Features and benefits

Processor core

ARM Cortex-M0 processor, running at frequencies of up to 45 MHz (one wait state

from flash) or 30 MHz (zero wait states from flash). The LPC122x have a high

score of over 45 in CoreMark CPU performance benchmark testing, equivalent to

1.51/MHz.

ARM Cortex-M0 built-in Nested Vectored Interrupt Contro ller (NVIC).

Serial Wire Debug (SWD).

System tick timer.

Memory

Up to 8 kB SRAM.

Up to 128 kB on-chip flash programming memory.

In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

Includes ROM-based 32-bit integer division routines.

Clock generation unit

LPC122x

32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash and

8 kB SRAM

Rev. 2 — 26 August 2011 Product data sheet

Product data sheet Rev. 2 — 26 August 2011 2 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

Crystal oscillator with an operating range of 1 MHz to 25 MHz.

12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy that can optionally be

used as a system clock.

PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator or the internal RC

oscillator.

Clock output function with divider that can reflect the system oscillator clock, IRC

clock, main clock, and Watchdog clock.

Real-Time Clock (RTC).

Digital peripherals

Micro DMA controller with 21 channels.

CRC engine.

Two UARTs with fractional ba ud rate generation and internal FIFO. One UART with

RS-485 and modem support and one standard UART with IrDA.

SSP/SPI controller with FIFO and multi-protocol capabilities.

I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a

data rate of 1 Mbit/s with multiple address recognition and monitor mode. I2C-bus

pins have programmable glitch filter.

Up to 55 General Purpose I/O (GPIO) pins with programmable pull-up resistor,

open-drain mode, programmable digital input glitch filter, and programmable input

inverter.

Programmable outp ut drive on all GPIO pins. Four pins supp ort high-current output

drivers.

All GPIO pins can be used as edge and level sensitive interrupt sources.

Four general purpose counter/timers with four capture inputs and four match

outputs (32-bit timers) or two capture inputs and two match outputs (1 6-bit timers).

Windowed WatchDog Timer (WWDT); IEC-60335 Class B certified.

Analog peripherals

One 8-channel, 10-bit ADC.

Two highly flexible analog comparators. Comparator outputs can be programmed

to trigger a timer match signal or can be used to emulate 555 timer behavior.

Power

Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

Processor wake-up from Deep-sleep mode via start logic using 12 port pins.

Processor wake-up from Deep-power down and Deep-sleep modes via the RTC.

Brownout detect with three separate thresholds each for interrupt and forced reset.

Power-On Reset (POR).

Integrated PMU (Power Management Unit).

Unique device serial number for identification.

3.3 V power supply.

Available as 64-pin and 48-pin LQFP package.

Product data sheet Rev. 2 — 26 August 2011 3 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

3. Applications

eMetering

Lighting

Industrial networking

Alarm systems

White goods

4. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

LPC1227FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1226FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1225FBD64/321 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1225FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1224FBD64/121 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1224FBD64/101 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1227FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

LPC1226FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

LPC1225FBD48/321 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

LPC1225FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

LPC1224FBD48/121 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

LPC1224FBD48/101 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

Product data sheet Rev. 2 — 26 August 2011 4 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

4.1 Ordering options

Table 2. Ordering options for LPC122x

Type number Flash Total

SRAM UART I2C/

FM+ SSP/

SPI ADC

channels GPIO Package

LPC1227

LPC1227FBD64/301 128 kB 8 kB 2 1 1 8 55 LQFP64

LPC1227FBD48/301 128 kB 8 kB 2 1 1 8 39 LQFP48

LPC1226

LPC1226FBD64/301 96 kB 8 kB 2 1 1 8 55 LQFP64

LPC1226FBD48/301 96 kB 8 kB 2 1 1 8 39 LQFP48

LPC1225

LPC1225FBD64/321 80 kB 8 kB 2 1 1 8 55 LQFP64

LPC1225FBD64/301 64 kB 8 kB 2 1 1 8 55 LQFP64

LPC1225FBD48/321 80 kB 8 kB 2 1 1 8 39 LQFP48

LPC1225FBD48/301 64 kB 8 kB 2 1 1 8 39 LQFP48

LPC1224

LPC1224FBD64/121 48 kB 4 kB 2 1 1 8 55 LQFP64

LPC1224FBD64/101 32 kB 4 kB 2 1 1 8 55 LQFP64

LPC1224FBD48/121 48 kB 4 kB 2 1 1 8 39 LQFP48

LPC1224FBD48/101 32 kB 4 kB 2 1 1 8 39 LQFP48

Product data sheet Rev. 2 — 26 August 2011 5 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

5. Block diagram

Fig 1. LPC122x block diagram

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

MICRO DMA

CONTROLLER

system

bus

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

XTALIN

XTALOUT

RESET

SWD

CRC

ENGINE

LPC122x

master

32/48/64/80/

96/128 kB

FLASH

slave

4/8 kB

SRAM

slave

ROM

slave

slaveslaveslave

002aaf269

GPIO ports

WINDOWED WDT

IOCONFIG

RTC 32 kHz OSCILLATOR

SYSTEM CONTROL

CLKOUT

SSP/SPI

UART0 RS-485

I2C

32-bit COUNTER/TIMER 0

SCK

SSEL

MISO

MOSI

4 × MAT

4 × CAP

SDA

SCL

UART1

TXD1

TXD0

RXD1

RXD0

32-bit COUNTER/TIMER 1

4 × MAT

4 × CAP

16-bit COUNTER/TIMER 0

2 × MAT

2 × CAP

16-bit COUNTER/TIMER 1

2 × MAT

2 × CAP

DTR0, DSR0, CTS0,

DCD0, RI0, RTS0

10-bit ADC

MICRO DMA REGISTERS

COMPARATOR0/1

AD[7:0]

ACMP0_I[3:0]

ACMP1_O

ACMP1_I[3:0]

VREF_CMP

ACMP0_O

AHB-LITE BUS

AHB-APB

BRIDGE

HIGH-SPEED

GPIO

RTCXOUT

RTCXIN

IRC, OSCILLATORS

POR

BOD

clocks and controls

Grey-shaded blocks represent peripherals

with connection to the micro DMA controller

Product data sheet Rev. 2 — 26 August 2011 6 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

6. Pinning information

6.1 Pinning

(1) High-current out put driver.

Remark: For a full listing of all functions for each pin see Table 3.

Fig 2. Pin configuration LQFP64 package

LPC122x

XTALIN R/PIO1_0

XTALOUT R/PIO0_31

VREF_CMP R/PIO0_30

PIO0_19 PIO0_18

PIO0_20 PIO0_17

PIO0_21 PIO0_16

PIO0_22 PIO0_15

PIO0_23 PIO0_14

PIO0_24 RESET/PIO0_13

SWDIO/PIO0_25 PIO0_12

(1)

SWCLK/PIO0_26 PIO0_11

PIO0_27

(1)

PIO0_10

PIO2_12 PIO2_7

PIO2_13 PIO2_6

PIO2_14 PIO2_5

PIO2_15 PIO2_4

PIO0_28

(1)

SSIO

PIO0_29

(1)

DD(IO)

PIO0_0 PIO2_11

PIO0_1 PIO2_10

PIO0_2 PIO2_9

PIO0_3 PIO2_8

PIO0_4 RTCXIN

PIO0_5 RTCXOOUT

PIO0_6 V

DD(3V3)

PIO0_7 V

PIO0_8 PIO1_6

PIO0_9 PIO1_5

PIO2_0 PIO1_4

PIO2_1 PIO1_3/WAKEUP

PIO2_2 PIO1_2

PIO2_3 R/PIO1_1

002aaf554

Product data sheet Rev. 2 — 26 August 2011 7 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

(1) High-current out put driver.

Remark: For a full listing of all functions for each pin see Table 3.

Fig 3. Pin configuration LQFP48 package

LPC122x

XTALIN R/PIO1_0

XTALOUT R/PIO0_31

VREF_CMP R/PIO0_30

PIO0_19 PIO0_18

PIO0_20 PIO0_17

PIO0_21 PIO0_16

PIO0_22 PIO0_15

PIO0_23 PIO0_14

PIO0_24 RESET/PIO0_13

SWDIO/PIO0_25 PIO0_12(1)

SWCLK/PIO0_26 PIO0_11

PIO0_27(1) PIO0_10

PIO0_28(1) VSSIO

PIO0_29(1) VDD(IO)

PIO0_0 RTCXIN

PIO0_1 RTCXOUT

PIO0_2 VDD(3V3)

PIO0_3 VSS

PIO0_4 PIO1_6

PIO0_5 PIO1_5

PIO0_6 PIO1_4

PIO0_7 PIO1_3/WAKEUP

PIO0_8

PIO0_9

PIO1_2

R/PIO1_1

002aaf724

Product data sheet Rev. 2 — 26 August 2011 8 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

6.2 Pin description

All pins except the supply pins can have more than one function as shown in Table 3. The

pin function is selected through the pin’s IOCON register in the IOCONFIG block. The

multiplexed functions (see Table 4) include the counter/timer inputs and outputs, the

UART receive, transmit, and control functions, and the serial wire debug functions.

For each pin, the default function is listed first together with the pin’s reset state.

Tabl e 3. LPC122x pin description

Symbol

Pin LQFP48

Pin LQFP64

Start

logic

input

Type Reset

state

[1]

Description

PIO0_0 to PIO0_31 I/O Port 0 — Port 0 is a 32-bit I/O port with individual direction and

function controls for each bit. The operation of port 0 pins

depends on the function selecte d through the IOCONFIG

PIO0_0/RTS0 15 19 [2]

[3] yes I/O I; PU PIO0_0 — General purpose digital input/output pin.

O- RTS0 — Request To Send output for UART0.

PIO0_1/RXD0/

CT32B0_CAP0/

CT32B0_MAT0

16 20 [2]

[3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin.

I- RXD0 — Receiver input for UART0.

I- CT32B0_CAP0 — Capture input, channel 0 for 32-bit timer 0.

O- CT32B0_MAT0 — Match output, channel 0 for 32-bit timer 0.

PIO0_2/TXD0/

CT32B0_CAP1/

CT32B0_MAT1

17 21 [2]

[3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.

O- TXD0 — Transmitter outpu t for UART0.

I- CT32B0_CAP1 — Capture input, channel 1 for 32-bit timer 0.

O- CT32B0_MAT1 — Match output, channel 1 for 32-bit timer 0.

PIO0_3/DTR0/

CT32B0_CAP2/

CT32B0_MAT2

18 22 [2]

[3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin.

O- DTR0 — Data Terminal Ready output for UART0.

I- CT32B0_CAP2 — Capture input, channel 2 for 32-bit timer 0.

O- CT32B0_MAT2 — Match output, channel 2 for 32-bit timer 0.

PIO0_4/DSR0/

CT32B0_CAP3/

CT32B0_MAT3

19 23 [2]

[3] yes I/O I; PU PIO0_4 — General purpose digital input/output pin.

I- DSR0 — Data Set Ready input for UART0.

I- CT32B0_CAP3 — Capture input, channel 3 for 32-bit timer 0.

O- CT32B0_MAT3 — Match output, channel 3 for 32-bit timer 0.

PIO0_5/DCD0 20 24 [2]

[3] yes I/O I; PU PIO0_5 — General purpose digital input/output pin.

I- DCD0 — Data Carrier Detect input for UART0.

PIO0_6/RI0/

CT32B1_CAP0/

CT32B1_MAT0

21 25 [2]

[3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.

I- RI0 — Ring Indicator input for UART0.

I- CT32B1_CAP0 — Capture input, channel 0 for 32-bit timer 1.

O- CT32B1_MAT0 — Match output, channel 0 for 32-bit timer 1.

Product data sheet Rev. 2 — 26 August 2011 9 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

PIO0_7/CTS0/

CT32B1_CAP1/

CT32B1_MAT1

22 26 [2]

[3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin.

I- CTS0 — Clear To Send input for UART0.

I- CT32B1_CAP1 — Capture input, channel 1 for 32-bit timer 1.

O- CT32B1_MAT1 — Match output, channel 1 for 32-bit timer 1.

PIO0_8/RXD1/

CT32B1_CAP2/

CT32B1_MAT2

23 27 [2]

[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.

I- RXD1 — Receiver input for UART1.

I- CT32B1_CAP2 — Capture input, channel 2 for 32-bit timer 1.

O- CT32B1_MAT2 — Match output, channel 2 for 32-bit timer 1.

PIO0_9/TXD1/

CT32B1_CAP3/

CT32B1_MAT3

24 28 [2]

[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin.

O- TXD1 — Transmitter outpu t for UART1.

I- CT32B1_CAP3 — Capture input, channel 3 for 32-bit timer 1.

O- CT32B1_MAT3 — Match output, channel 3 for 32-bit timer 1.

PIO0_10/SCL 25 37 [4] yes I/O I; IA PIO0_10 — General purpose digital input/output pin.

I/O - SCL — I2C-bus clock input/output.

PIO0_11/SDA/

CT16B0_CAP0/

CT16B0_MAT0

26 38 [4] yes I/O I; IA PIO0_11 — General purpose digital input/output pin.

I/O - SDA — I2C-bus data input/output.

I- CT16B0_CAP0 — Capture input, channel 0 for 16-bit timer 0.

O- CT16B0_MAT0 — Match output, channel 0 for 16-bit timer 0.

PIO0_12/CLKOUT/

CT16B0_CAP1/

CT16B0_MAT1

27 39 [9] no I/O I; PU PIO0_12 — General purpose digital input/output pin. A LOW

level on this pin during reset starts the ISP command handler.

High-current output driver.

O- CLKOUT — Clock out pin.

I- CT16B0_CAP1 — Capture input, channel 1 for 16-bit timer 0.

O- CT16B0_MAT1 — Match output, channel 1 for 16-bit timer 0.

RESET/PIO0_13 28 40 [5]

[3] no I I; PU RESET — External reset input: A LOW on this pin resets the

device, causing I/O ports and peripherals to take on their

default states, and processor execution to begin at address 0.

I/O - PIO0_13 — General purpose digital input/o utput pin.

PIO0_14/SCK 29 41 [2]

[3] no I/O I; PU PIO0_14 — General purpose digital input/output pin.

I/O - SCK — Serial clock for SSP/SPI.

PIO0_15/SSEL/

CT16B1_CAP0/

CT16B1_MAT0

30 42 [2]

[3] no I/O I; PU PIO0_15 — General purpose digital input/output pin.

I/O - SSEL — Slave select for SSP/SPI.

I- CT16B1_CAP0 — Capture input, channel 0 for 16-bit timer 1.

O- CT16B1_MAT0 — Match output, channel 0 for 16-bit timer 1.

PIO0_16/MISO/

CT16B1_CAP1/

CT16B1_MAT1

31 43 [2]

[3] no I/O I; PU PIO0_16 — General purpose digital input/output pin.

I/O - MISO — Master In Slave Out for SSP/SPI.

I- CT16B1_CAP1 — Capture input, channel 1 for 16-bit timer 1.

O- CT16B1_MAT1 — Match output, channel 1 for 16-bit timer 1.

Tabl e 3. LPC122x pin description …continued

Symbol

Pin LQFP48

Pin LQFP64

Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 2 — 26 August 2011 10 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

PIO0_17/MOSI 32 44 [2]

[3] no I/O I; PU PIO0_17 — General purpose digital input/output pin.

I/O - MOSI — Master Out Slave In for SSP/SPI.

PIO0_18/SWCLK/

CT32B0_CAP0/

CT32B0_MAT0

33 45 [2]

[3] no I/O I; PU PIO0_18 — General purpose digital input/output pin.

I- SWCLK — Serial wire clock, alternate location.

I- CT32B0_CAP0 — Capture input, channel 0 for 32-bit timer 0.

O- CT32B0_MAT0 — Match output, channel 0 for 32-bit timer 0.

PIO0_19/ACMP0_I0/

CT32B0_CAP1/

CT32B0_MAT1

44 [6]

[7] no I/O I; PU PIO0_19 — General purpose digital input/output pin.

I- ACMP0_I0 — Input 0 for comparator 0.

I- CT32B0_CAP1 — Capture input, channel 1 for 32-bit timer 0.

O- CT32B0_MAT1 — Match output, channel 1 for 32-bit timer 0

PIO0_20/ACMP0_I1/

CT32B0_CAP2/

CT32B0_MAT2

55 [6]

[7] no I/O I; PU PIO0_20 — General purpose digital input/output pin.

I- ACMP0_I1 — Input 1 for comparator 0.

I- CT32B0_CAP2 — Capture input, channel 2 for 32-bit timer 0.

O- CT32B0_MAT2 — Match output, channel 2 for 32-bit timer 0.

PIO0_21/ACMP0_I2/

CT32B0_CAP3/

CT32B0_MAT3

66 [6]

[7] no I/O I; PU PIO0_21 — General purpose digital input/output pin.

I- ACMP0_I2 — Input 2 for comparator 0.

I- CT32B0_CAP3 — Capture input, channel 3 for 32-bit timer 0.

O- CT32B0_MAT3 — Match output, channel 3 for 32-bit timer 0.

PIO0_22/ACMP0_I3 7 7 [6]

[7] no I/O I; PU PIO0_22 — General purpose digital input/output pin.

I- ACMP0_I3 — Input 3 for comparator 0.

PIO0_23/

ACMP1_I0/

CT32B1_CAP0/

CT32B1_MAT0

88 [6]

[7] no I/O I; PU PIO0_23 — General purpose digital input/output pin.

I- ACMP1_I0 — Input 0 for comparator 1.

I- CT32B1_CAP0 — Capture input, channel 0 for 32-bit timer 1.

O- CT32B1_MAT0 — Match output, channel 0 for 32-bit timer 1.

PIO0_24/ACMP1_I1/

CT32B1_CAP1/

CT32B1_MAT1

99 [6]

[7] no I/O I; PU PIO0_24 — General purpose digital input/output pin.

I- ACMP1_I1 — Input 1 for comparator 1.

I- CT32B1_CAP1 — Capture input, channel 1 for 32-bit timer 1.

O- CT32B1_MAT1 — Match output, channel 1 for 32-bit timer 1.

SWDIO/ACMP1_I2/

CT32B1_CAP2/

CT32B1_MAT2/

PIO0_25

10 10 [6]

[7] no I/O I; PU SWDIO — Serial wire debug input/output, default location.

I- ACMP1_I2 — Input 2 for comparator 1.

I- CT32B1_CAP2 — Capture input, channel 2 for 32-bit timer 1.

O- CT32B1_MAT2 — Match output, channel 2 for 32-bit timer 1.

I/O - PIO0_25 — General purpose digital input/o utput pin.

SWCLK/ACMP1_I3/

CT32B1_CAP3/

CT32B1_MAT3/

PIO0_26

11 11 [6]

[7] no I I; PU SWCLK — Serial wire clock, default location.

I- ACMP1_I3 — Input 3 for comparator 1.

I- CT32B1_CAP3 — Capture input, channel 3 or 32-bit timer 1.

O- CT32B1_MAT3 — Match output, channel 3 for 32-bit timer 1.

I/O PIO0_26 — General purpose digital input/output pin.

Tabl e 3. LPC122x pin description …continued

Symbol

Pin LQFP48

Pin LQFP64

Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 2 — 26 August 2011 11 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

PIO0_27/ACMP0_O 12 12 [9] no I/O I; PU PIO0_27 — General purpose digital input/output pin

(high-current output driver).

O- ACMP0_O — Output for comparator 0.

PIO0_28/ACMP1_O/

CT16B0_CAP0/

CT16B0_MAT0

13 17 [9] no I/O I; PU PIO0_28 — General purpose digital input/output pin

(high-current output driver).

O- ACMP1_O — Output for comparator 1.

I- CT16B0_CAP0 — Capture input, channel 0 for 16-bit timer 0.

O- CT16B0_MAT0 — Match output, channel 0 for 16-bit timer 0.

PIO0_29/ROSC/

CT16B0_CAP1/

CT16B0_MAT1

14 18 [9] no I/O I; PU PIO0_29 — General purpose digital input/output pin

(high-current output driver).

I/O - ROSC — Relaxation oscillator for 555 timer applications.

I- CT16B0_CAP1 — Capture input, channel 1 for 16-bit timer 0.

O- CT16B0_MAT1 — Match output, channel 1 for 16-bit timer 0.

R/PIO0_30/AD0 34 46 [6]

[3] no I I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.

I/O - PIO0_30 — General purpose digital input/o utput pin.

I- AD0 — A/D converter, input 0.

R/PIO0_31/AD1 35 47 [6]

[3] no I I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.

I/O - PIO0_31 — General purpose digital input/o utput pin.

I- AD1 — A/D converter, input 1.

PIO1_0 to PIO1_6 I/O Port 1 — Port 1 is a 32-bit I/O port with individual direction and

function controls for each bit. The operation of port 1 pins

depends on the function selecte d through the IOCONFIG

R/PIO1_0/AD2 36 48 [6]

[3] no O I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.

I/O - PIO1_0 — General purpose digital input/output pin.

I- AD2 — A/D converter, input 2.

R/PIO1_1/AD3 37 49 [6]

[3] no I I; PU R — Reserved. Configure for an alternate function in the

IOCONFIG block.Do not pull th is pin LOW at reset.

I/O - PIO1_1 — General purpose digital input/output pin.

I- AD3 — A/D converter, input 3.

PIO1_2/SWDIO/AD4 38 50 [6]

[3] no I/O I; PU PIO1_2 — General purpose digital input/ou tput pin.

I/O - SWDIO — Serial wire debug input/output, alternate location.

I- AD4 — A/D converter, input 4.

PIO1_3/AD5/WAKEUP 39 51 [8]

[3] no I/O I; PU PIO1_3 — General purpose digital input/ou tput pin.

I- AD5 — A/D converter, input 5.

I- WAKEUP — Deep power-down mode wake-up pin.

PIO1_4/AD6 40 52 [6]

[3] no I/O I; PU PIO1_4 — General purpose digital input/ou tput pin.

I- AD6 — A/D converter, input 6.

Tabl e 3. LPC122x pin description …continued

Symbol

Pin LQFP48

Pin LQFP64

Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 2 — 26 August 2011 12 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

PIO1_5/AD7/

CT16B1_CAP0/

CT16B1_MAT0

41 53 [6]

[3] no I/O I; PU PIO1_5 — General purpose digital input/ou tput pin.

I- AD7 — A/D converter, input 7.

I- CT16B1_CAP0 — Capture input, channel 0 for 16-bit timer 1.

O- CT16B1_MAT0 — Match output, channel 0 for 16-bit timer 1.

PIO1_6/

CT16B1_CAP1/

CT16B1_MAT1

42 54 [2]

[3] no I/O I; PU PIO1_6 — General purpose digital input/ou tput pin.

I- CT16B1_CAP1 — Capture input, channel 1 for 16-bit timer 1.

O- CT16B1_MAT1 — Match output, channel 1 for 16-bit timer 1.

PIO2_0 to PIO2_15 I/O Port 2 — Port 2 is a 32-bit I/O port with individual direction and

function controls for each bit. The operation of port 2 pins

depends on the function selecte d through the IOCONFIG

available.

PIO2_0/

CT16B0_CAP0/

CT16B0_MAT0/

RTS0

-29

[2]

[3] no I/O I; PU PIO2_0 — General purpose digital input/ou tput pin.

I- CT16B0_CAP0 — Capture input, channel 0 for 16-bit timer 0.

O- CT16B0_MAT0 — Match output, channel 0 for 16-bit timer 0.

O- RTS0 — Request To Send output for UART0.

PIO2_1/

CT16B0_CAP1/

CT16B0_MAT1/RXD0

-30

[2]

[3] no I/O I; PU PIO2_1 — General purpose digital input/ou tput pin.

I- CT16B0_CAP1 — Capture input, channel 1 for 16-bit timer 0.

O- CT16B0_MAT1 — Match output, channel 1 for 16-bit timer 0.

I- RXD0 — Receiver input for UART0.

PIO2_2/

CT16B1_CAP0/

CT16B1_MAT0/TXD0

-31

[2]

[3] no I/O I; PU PIO2_2 — General purpose digital input/ou tput pin.

I- CT16B1_CAP0 — Capture input, channel 0 for 16-bit timer 1.

O- CT16B1_MAT0 — Match output, channel 0 for 16-bit timer 1.

O- TXD0 — Transmitter outpu t for UART0.

PIO2_3/

CT16B1_CAP1/

CT16B1_MAT1/DTR0

-32

[2]

[3] no I/O I; PU PIO2_3 — General purpose digital input/ou tput pin.

I- CT16B1_CAP1 — Capture input, channel 1 for 16-bit timer 1.

O- CT16B1_MAT1 — Match output, channel 1 for 16-bit timer 1.

O- DTR0 — Data Terminal Ready output for UART0.

PIO2_4/

CT32B0_CAP0/

CT32B0_MAT0/CTS0

-33

[2]

[3] no I/O I; PU PIO2_4 — General purpose digital input/ou tput pin.

I- CT32B0_CAP0 — Capture input, channel 0 for 32-bit timer 0.

O- CT32B0_MAT0 — Match output, channel 0 for 32-bit timer 0.

I- CTS0 — Clear To Send input for UART0.

PIO2_5/

CT32B0_CAP1/

CT32B0_MAT1/RI0

-34

[2]

[3] no I/O I; PU PIO2_5 — General purpose digital input/ou tput pin.

I- CT32B0_CAP1 — Capture input, channel 1 for 32-bit timer 0.

O- CT32B0_MAT1 — Match output, channel 1 for 32-bit timer 0.

I- RI0 — Ring Indicator input for UART0.

Tabl e 3. LPC122x pin description …continued

Symbol

Pin LQFP48

Pin LQFP64

Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 2 — 26 August 2011 13 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

PIO2_6/

CT32B0_CAP2/

CT32B0_MAT2/DCD0

-35

[2]

[3] no I/O I; PU PIO2_6 — General purpose digital input/ou tput pin.

I- CT32B0_CAP2 — Capture input, channel 2 for 32-bit timer 0.

O- CT32B0_MAT2 — Match output, channel 2 for 32-bit timer 0.

I- DCD0 — Data Carrier Detect input for UART0.

PIO2_7/

CT32B0_CAP3/

CT32B0_MAT3/DSR0

-36

[2]

[3] no I/O I; PU PIO2_7 — General purpose digital input/ou tput pin.

I- CT32B0_CAP3 — Capture input, channel 3 for 32-bit timer 0.

O- CT32B0_MAT3 — Match output, channel 3 for 32-bit timer 0.

I- DSR0 — Data Set Ready input for UART0.

PIO2_8/

CT32B1_CAP0/

CT32B1_MAT0

-59

[2]

[3] no I/O I; PU PIO2_8 — General purpose digital input/ou tput pin.

I- CT32B1_CAP0 — Capture input, channel 0 for 32-bit timer 1.

O- CT32B1_MAT0 — Match output, channel 0 for 32-bit timer 1.

PIO2_9/

CT32B1_CAP1/

CT32B1_MAT1

-60

[2]

[3] no I/O I; PU PIO2_9 — General purpose digital input/ou tput pin.

I- CT32B1_CAP1 — Capture input, channel 1 for 32-bit timer 1.

O- CT32B1_MAT1 — Match output, channel 1 for 32-bit timer 1.

PIO2_10/

CT32B1_CAP2/

CT32B1_MAT2/TXD1

-61

[2]

[3] no I/O I; PU PIO2_10 — General purpose digital input/output pin.

I- CT32B1_CAP2 — Capture input, channel 2 for 32-bit timer 1.

O- CT32B1_MAT2 — Match output, channel 2 for 32-bit timer 1.

O- TXD1 — Transmitter outpu t for UART1.

PIO2_11/

CT32B1_CAP3/

CT32B1_MAT3/RXD1

-62

[2]

[3] no I/O I; PU PIO2_11 — General purpose dig ital input/ou tput pin.

I- CT32B1_CAP3 — Capture input, channel 3 for 32-bit timer 1.

O- CT32B1_MAT3 — Match output, channel 3 for 32-bit timer 1.

I- RXD1 — Receiver input for UART1.

PIO2_12/RXD1 - 13 [2]

[3] no I/O I; PU PIO2_12 — General purpose digital input/output pin.

I- RXD1 — Receiver input for UART1.

PIO2_13/TXD1 - 14 [2]

[3] no I/O I; PU PIO2_13 — General purpose digital input/output pin.

O- TXD1 — Transmitter outpu t for UART1.

PIO2_14 - 15 [2]

[3] no I/O I; PU PIO2_14 — General purpose digital input/output pin.

PIO2_15 - 16 [2]

[3] no I/O I; PU PIO2_15 — General purpose digital input/output pin.

RTCXIN 46 58 [10] - I - Input to the 32 kHz oscillator circui t.

RTCXOUT 45 57 [10] - O - Output from the 32 kHz oscillator amplifier.

XTALIN 1 1 - I - Input to the system oscillator circuit and internal clock

generator circuits.

XTALOUT 2 2 - O - Output from the system oscillator amplifier.

VREF_CMP 3 3 - I - Reference voltage for comparator.

Tabl e 3. LPC122x pin description …continued

Symbol

Pin LQFP48

Pin LQFP64

Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 2 — 26 August 2011 14 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled.

[2] 3.3 V tolerant, digital I/O pin; default: pull-up enabled, no hysteresis.

[3] If set to output, this normal-drive pin is in low mode by default.

[4] I2C-bus pins; 5 V tolerant; open-drain; default: no pull-up/pull-down; no hysteresis.

[5] 3.3 V tolerant, digital I/O pin with RESET function; default: pull-up enabled, no hysteresis. An external pull-up resistor is required on this

pin for the Deep power-down mode.

[6] 3.3 V tolerant, digital I/O pin with analog function; default: pull-up enabled, no hysteresis.

[7] If set to output, this normal-drive pin is in high mode by default.

[8] 3.3 V tolerant, digital I/O pin with analog function and WAKEUP function; default: pull-up enabled, no hysteresis.

[9] 3.3 V tolerant, high-drive digital I/O pin; default: pull-up enabled, no hysteresis.

[10] If the RTC is not used, RTCXIN and RTCXOUT can be left floating.

To enable a peripheral function, find the corresponding port pin, or select a port pin if the

function is multiplexed, and program the port pin’s IOCONFIG register to enable that

function. The primary SWD functions and RESET are the default functions on their pins

after reset.

VDD(IO) 47 63 - I - Input/output supply voltage.

VDD(3V3) 44 56 - I - 3.3 V supply voltage to the internal regulator and the ADC. Also

used as the ADC reference voltage.

VSSIO 48 64 - I - Ground.

VSS 43 55 - I - Ground.

Tabl e 3. LPC122x pin description …continued

Symbol

Pin LQFP48

Pin LQFP64

Start

logic

input

Type Reset

state

[1]

Description

Table 4. Pin multiplexing

Peripheral Function Type Available on ports:

Analog comparators ROSC I/O PIO0_29 - -

ACMP0_I0 I PIO0_19 - -

ACMP0_I1 I PIO0_20 - -

ACMP0_I2 I PIO0_21 - -

ACMP0_I3 I PIO0_22 - -

ACMP0_O O PIO0_27 - -

ACMP1_I0 I PIO0_23 - -

ACMP1_I1 I PIO0_24 - -

ACMP1_I2 I PIO0_25 - -

ACMP1_I3 I PIO0_26 - -

ACMP1_O O PIO0_28 - -

Product data sheet Rev. 2 — 26 August 2011 15 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

ADC AD0 I PIO0_30 - -

AD1 I PIO0_31 - -

AD2 I PIO1_0 - -

AD3 I PIO1_1 - -

AD4 I PIO1_2 - -

AD5 I PIO1_3 - -

AD6 I PIO1_4 - -

AD7 I PIO1_5 - -

CT16B0 CT16B0_CAP0 I PIO0_11 PIO0_28 PIO2_0

CT16B0_CAP1 I PIO0_12 PIO0_29 PIO2_1

CT16B0_MAT0 O PIO0_11 PIO0_28 PIO2_0

CT16B0_MAT1 O PIO0_12 PIO0_29 PIO2_1

CT16B1 CT16B1_CAP0 I PIO0_15 PIO1_5 PIO2_2

CT16B1_CAP1 I PIO0_16 PIO1_6 PIO2_3

CT16B1_MAT0 O PIO0_15 PIO1_5 PIO2_2

CT16B1_MAT1 O PIO0_16 PIO1_6 PIO2_3

CT32B0 CT32B0_CAP0 I PIO0_1 PIO0_18 PIO2_4

CT32B0_CAP1 I PIO0_2 PIO0_19 PIO2_5

CT32B0_CAP2 I PIO0_3 PIO0_20 PIO2_6

CT32B0_CAP3 I PIO0_4 PIO0_21 PIO2_7

CT32B0_MAT0 O PIO0_1 PIO0_18 PIO2_4

CT32B0_MAT1 O PIO0_2 PIO0_19 PIO2_5

CT32B0_MAT2 O PIO0_3 PIO0_20 PIO2_6

CT32B0_MAT3 O PIO0_4 PIO0_21 PIO2_7

CT32B1 CT32B1_CAP0 I PIO0_6 PIO0_23 PIO2_8

CT32B1_CAP1 I PIO0_7 PIO0_24 PIO2_9

CT32B1_CAP2 I PIO0_8 PIO0_25 PIO2_10

CT32B1_CAP3 I PIO0_9 PIO0_26 PIO2_11

CT32B1_MAT0 O PIO0_6 PIO0_23 PIO2_8

CT32B1_MAT1 O PIO0_7 PIO0_24 PIO2_9

CT32B1_MAT2 O PIO0_8 PIO0_25 PIO2_10

CT32B1_MAT3 O PIO0_9 PIO0_26 PIO2_11

UART0 RXD0 I PIO0_1 PIO2_1 -

TXD0 O PIO0_2 PIO2_2 -

CTS0 I PIO0_7 PIO2_4 -

DCD0 I PIO0_5 PIO2_6 -

DSR0 I PIO0_4 PIO2_7 -

DTR0 O PIO0_3 PIO2_3 -

RI0 I PIO0_6 PIO2_5 -

RTS0 O PIO0_0 PIO2_0 -

Table 4. Pin multiplexing

Peripheral Function Type Available on ports:

Product data sheet Rev. 2 — 26 August 2011 16 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

[1] After reset, the SWD functions are selected by default on pins PIO0_26 and PIO0_25.

7. Functional description

7.1 ARM Cortex-M0 processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption.

7.1.1 System tick timer

The ARM Cortex-M0 includes a System T ick time r (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval.

7.2 On-chip flash program memory

The LPC122x contain up to 128 kB of on-chip flash memory.

7.3 On-chip SRAM

The LPC122x contain a total of up to 8 kB on-chip static RAM memory.

7.4 Memory map

The LPC122x incorporates several distinct memory regions, shown in the following

figures. Figure 4 shows the overall map of the entire address space from the user

program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128

peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32

peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows

simplifying the address decoding for each peripheral.

UART1 RXD1 I PIO0_8 PIO2_11 PIO2_12

TXD1 O PIO0_9 PIO2_10 PIO2_13

SSP/SPI SCK I/O PIO0_14 - -

MISO I/O PIO0_16 - -

MOSI I/O PIO0_17 - -

SSEL I/O PIO0_15 - -

I2C SCL I/O PIO0_10 - -

SDA I/O PIO0_11 - -

SWD SWCLK[1] I PIO0_18 PIO0_26 -

SWDIO[1] I/O PIO0_25 PIO1_2 -

Reset RESET I PIO0_13 - -

Clockout pin CLKOUT O PIO0_12 - -

Table 4. Pin multiplexing

Peripheral Function Type Available on ports:

Product data sheet Rev. 2 — 26 August 2011 17 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

7.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

7.5.1 Features

•Controls system exceptions and peripheral interrupts.

Fig 4. LPC122x memory map

0x5000 0000

0x5001 0000

0x5002 0000

AHB peripherals

3 - 6 reserved

GPIO PIO1

0x5003 0000

GPIO PIO2

0x5007 0000

0x5008 0000

CRC

GPIO PIO0

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

WDT

32-bit counter/timer 0

32-bit counter/timer 1

ADC

UART0

UART1

PMU

I2C-bus

9 - 13 reserved

22 - 31 reserved

reserved

0x0000 0000

0 GB

4 GB

1 GB

0x0000 C000

0x0000 8000

0x1000 1000

0x1FFF 0000

0x1FFF 2000

0x4000 0000

0x4008 0000

0x5000 0000

0x5008 0000

0xFFFF FFFF

reserved

APB peripherals

AHB peripherals

4 kB SRAM (LPC1224)

0x1000 2000

8 kB SRAM (LPC1225/6/7)

0x1FFC 0000

reserved

0x1FFC 4000

16 kB NXP library ROM

0x1FFE 0000

reserved

0x1FFE 2000

8 kB custom ROM

reserved

0x1000 0000

LPC122x

48 kB on-chip flash (LPC1224/121)

32 kB on-chip flash (LPC1224/101)

0x0001 0000

64 kB on-chip flash (LPC1225/301)

0x0001 4000

80 kB on-chip flash (LPC1225/321)

0x0001 8000

96 kB on-chip flash (LPC1226/301)

0x0002 0000

128 kB on-chip flash (LPC1227/301)

8 kB boot ROM

0x0000 0000

0x0000 00C0

active interrupt vectors

reserved

SSP

16-bit counter/timer 1

16-bit counter/timer 0

IOCONFIG

system control

0x4005 0000

19 micro DMA registers

0x4005 4000

20 RTC

0x4005 8000

21 comparator 0/1

reserved

002aaf270

0xE000 0000

0xE010 0000

private peripheral bus

Product data sheet Rev. 2 — 26 August 2011 18 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

•In the LPC122x, the NVIC support s 32 vectored interrupts. In addition, up to 12 of the

individual GPIO inputs are NVIC-vector capable.

•Four programmable interrupt priority levels with hardware priority level masking.

•Software interrupt generation.

•Non-maskable Interrupt (NMI) can be programmed to use any of the peripheral

interrupts. The NMI is not available on an external pin.

7.5.2 Interrupt sources

Each peripheral devi ce has one interrupt line con nected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any GPIO pin (total of up to 55 pins) regardless of the selected function, ca n be

programmed to generate an interrupt on a level, a rising edge or falling edge, or both.

7.6 IOCONFIG block

The IOCONFIG block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be conn ected to the appro priate pins prior to being activated and pr ior

to any related interrup t(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.6.1 Features

•Programmable pull-up resistor.

•Programmable digital glitch filter.

•Programmable input inverter.

•Programmable drive current.

•Programmable open-drain mode.

7.7 Micro DMA controller

The micro DMA controller enables memory-to-memory, memory-to-peripheral, and

peripheral-to-memory data transfers. The supported peripherals are: UART0 (transmit

and receive), UART1 (transmit and receive), SSP/SPI (transmit and receive), ADC, RTC,

32-bit counter/timer 0 (match output channels 0 and 1), 32-bit counter/timer 1 (match

output channels 0 and 1), 16-bit counter/timer 0 (match output channel 0), 16-bit

counter/timer 1 (match output channel 0), comparator 0, comparator 1, GPIO0 to GPIO2.

7.7.1 Features

•Single AHB-Lite master for transferring data using a 32-bit address bus and 32-bit

data bus.

•21 DMA channels.

•Handshake signals and priority level programmable for each channel.

•Each priority level arbitrates using a fixed priority that is determined by the DMA

channel number.

Product data sheet Rev. 2 — 26 August 2011 19 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

•Supports memory-to-memory, memory-to-peripheral, and peripheral-to-memory

transfers.

•Supports multiple DMA cycle types and multiple DMA transfer widths.

•Performs all DMA transfers using the single AHB-Lite burst type.

7.8 CRC engine

The Cyclic Redundancy Check (CRC) engine with programmable polynomial settings

supports several CRC standards commonly used. To save syste m po we r an d bu s

bandwidth, the CRC engine supports DMA transfers.

7.8.1 Features

•Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.

–CRC-CCITT: x16 + x12 + x5 + 1

–CRC-16: x16 + x15 + x2 + 1

–CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

•Bit order reverse and 1’s complement programmable setting for input data and CRC

sum.

•Programmable seed number setting.

•Supports CPU programmed I/O or DMA back-to-back transfer.

•Accept any size of data width per write: 8, 16 or 32-bit.

–8-bit write: 1-cycle operation

–16-bit write: 2-cycle opera tion (8-b it  2-cycle)

–32-bit write: 4-cycle opera tion (8-b it  4-cycle)

7.9 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any nu mber of outp uts simultan eously. The value of the

output register may be read back as well as the current state of the port pins.

7.9.1 Features

•Bit level set and clear registers allow a single instr uction to set or clear any nu mber of

bits in one port.

•Direction control of individual bits.

•All I/O default to inputs after reset.

7.10 UARTs

The LPC122x cont ains two UAR Ts. UAR T0 sup port s full modem con trol and RS-4 85/9-b it

mode and allows both software address detection and automatic hardware address

detection using 9-bit mode.

The UARTs include a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

Product data sheet Rev. 2 — 26 August 2011 20 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

7.10.1 Features

•16-byte Receive an d Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

•Auto-baud capabilities and FIFO control mechanism that enables software flow

control implementation.

•Support for RS-4 85 /9 -b it mo d e (UART0).

•Support for modem control (UART0).

7.11 SSP/SPI serial I/O controller

The LPC122x contain one SSP/SPI controller. The SSP/SPI controller is capable of

operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and

slaves on the bus. Only a single master and a single slave can communicate on the bus

during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits

to 16 bits of data flo wing fro m the ma ster to the slave and from the slave to the master. In

practice, often only one of these data flows carries meaningful data.

7.11.1 Features

•Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

•Synchronous serial communication

•Master or slave operation

•8-frame FIFOs for both transmit and receive

•4-bit to 16-bit frame

7.12 I2C-bus serial I/O controller

The LPC122x contain one I2C-bus controller.

The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a r eceiver-o nly device ( e.g., an LCD driver) or a tra nsmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can oper ate in eithe r master or sl ave mo de, dependin g on wheth er the chip has

to initiate a data transfer or is only addressed. The I2C is a multi-master bus an d ca n be

controlled by more than one bus master connected to it.

7.12.1 Features

•The I2C-interface is a standard I2C-compliant bus interface with open-drain pins and

supports I2C Fast-mode Plus with bit rates of up to 1 Mbit/s.

•Programmable digital glitch filter providing a 60 ns to 1 s input filter.

•Easy to configure as master, slave, or master/slave.

•Programmable clocks allow versatile rate control.

Product data sheet Rev. 2 — 26 August 2011 21 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake mech anism to suspend and

resume serial transfer.

•The I2C-bus can be used for test and diagnostic purposes.

•The I2C-bus controller support s multiple ad dress recognition and a bus monitor mode.

7.13 10-bit ADC

The LPC122x contains one ADC. It is a single 10-bit successive approximation ADC with

eight channels.

7.13.1 Features

•10-bit successive approximation ADC.

•Input multiplexing among 8 pins.

•Power-down mode.

•Measurement range 0 V to VDD(3V3).

•10-bit conver sio n time of 25 7 kHz.

•Burst conversion mode for single or multiple inputs.

•Optional conversion on transition of input pin or counter/timer match signal.

•Individual result registers for each ADC channel to reduce interrupt overhead.

7.14 Comparator block

The comparator block consists of two analog comparators.

7.14.1 Features

•Up to six selectable external sources per comparator; fully configurable on either

positive or negative comparator input channels.

•BOD 0.9 V internal reference volta ge selectable on both comparators; configurable on

either positive or negative comparator input channels.

•32-stage voltage ladder internal reference voltage selectable on both comparators;

configurable on either positive or negative comparator input channels.

•Voltage ladder source voltage is selectable from an external pin or an internal 3.3 V

voltage rail if external power source is not available.

•Voltage ladder can be separately powered down for applications only requirin g the

comparator function.

•Relaxation oscillator circuitry output for a fe edback 555-style timer application.

•Common interrupt connected to NVIC.

•Comparator outputs selectable as synchronous or asynchronous.

Product data sheet Rev. 2 — 26 August 2011 22 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

•Comparator outputs connect to two timers, allowing for the recording of comparison

event time stamps.

7.15 General purpose external event counter/timers

The LPC122x includes two 32-bit counter/timers and two 16-bit counter/timers. The

counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. Each counter/timer also includes up to four capture inputs to trap the

timer value when an input signal transitions, optionally generating an interrupt.

7.15.1 Features

•A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

•Counter or timer op er a tion .

•Up to four capture channels per timer, that can take a snapshot of the timer value

when an input signal transitions. A capture event may also generate an interrupt.

•Four match registers per timer tha t allow :

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Up to four external outputs corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

•The timer and prescaler may be configured to be cleared on a designated capture

event. This feature permits easy pulse width measurement by clearing the timer on

the leading edge of an input pulse and capturing the timer value on the trailing edge.

•Supports timed DMA requests.

7.16 Windowed WatchDog timer (WWDT)

The purpose of the watchdog is to reset the microcontroller within a windowed amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

7.16.1 Features

•Internally resets chip if not periodically reloaded.

•Debug mode.

•Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

•Safe operation: can be locked by software to be always on.

•Flag to indicate watchdog reset.

•Programmable 24-bit timer with internal prescaler.

Product data sheet Rev. 2 — 26 August 2011 23 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

•Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in

multiples of Tcy(WDCLK) 4.

•The W atchdog Clock (WDCLK) source can be selected from the Internal RC oscillator

(IRC) or the W atchdog oscillator . This gives a wide range of potential timing choices of

Watchdog operation under dif ferent power reduction conditions. It also provides the

ability to run the WDT from an entirely internal source that is not dependent on an

external crystal and its associated components and wiring for increased reliability.

7.17 Real-time clock (RTC)

The RTC provides a basic alarm function or can be used as a long time base counter. The

RTC g enerates an interrupt a fte r coun ting for a p rogrammed n umber of cycles o f the R TC

clock input.

7.17.1 Features

•Uses dedicated 32 kHz ultra low-power oscillator.

•Selectable clock inputs: RTC oscillator (1 Hz, delayed 1 Hz, or 1 kHz clock) or main

clock with programmable clock divider.

•32-bit counter.

•Programmable 32-bit match/compare register.

•Software maskable interrupt when counter and compare registers are identical.

•Generates wake-up from Deep-sleep and Deep power-down modes.

7.18 Clocking and power control

7.18.1 Crystal oscillators

The LPC122x include four independent oscillators. These are the system oscillator, the

Internal RC oscillator (IRC), the RTC 32 kHz oscillator (for the RTC only), and the

Watchdog oscillator. Except for the RTC oscillator, each oscillator can be used for more

than one purpose as required in a particular application.

Following reset, the LPC122x will operate from the Internal RC oscillator until switched by

software. This allows systems to operate without any external crystal and the bootloader

code to operate at a known frequency.

See Figure 5 for an overview of the LPC1 22x clock generation.

Product data sheet Rev. 2 — 26 August 2011 24 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

7.18.1.1 Internal RC oscillator

The IRC may be used as the clock so urce for th e WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the LPC1 22x use the IRC as the clock source. Software

may later switch to one of the other available clock sources.

7.18.1.2 System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using

the PLL.

Fig 5. LPC122x clocking genera tio n block diagram

SYSTEM PLL

watchdog oscillator

IRC oscillator

watchdog oscillator

system oscillator

MAINCLKSEL

(main clock select)

SYSPLLCLKSEL

CLOCK

DIVIDER

AHB clock 0

(system)

CLOCK

DIVIDER peripheral clocks

(SSP, UART0, UART1)

RTC

WWDT

watchdog oscillator

IRC oscillator

system oscillator CLOCK

DIVIDER CLKOUT pin

CLKOUTUEN

(CLKOUT clock update enable)

RTC oscillator 1 kHz clock

RTC oscillator 1 Hz clock

RTC oscillator 1 Hz delayed clock

RTCOSCCTRL

WDCLKSEL

(WWDT clock select)

main clock system clock

CLOCK

DIVIDER

SYSAHBCLKCTRL[1:31]

(AHB clock enable)

AHB clocks

1 to 31

(memories

and peripherals)

002aaf271

CLOCK

DIVIDER peripheral clocks

(IOCONFIG glitch filter)

Product data sheet Rev. 2 — 26 August 2011 25 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL. The ARM processor clock frequency is referred to as CCLK elsewhere in this

document.

7.18.1.3 Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the

watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is

programmable betwee n 7.8 kHz and 1.7 MHz. The frequency spread over p rocessing and

temperature is 40 %.

7.18.2 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The output

divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output

frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is

insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed

following a chip reset and may be enabled by software. The program must configure and

activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.

The PLL settling time is 100 s.

7.18.3 Clock output

The LPC122x features a clock output function that routes the IRC oscillator, the system

oscillator, the watchdog oscillator, or the main clock to an output pin.

7.18.4 Wake-up process

The LPC122x begin operation at power-up and when awakened from Deep power-down

mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation

to resume quickly. If the main oscillator or the PLL is needed by the application, software

will need to enable these features and wait for them to stabilize before they are used as a

clock source.

7.18.5 Power control

The LPC122x su pp or t a vari et y of po we r con tr ol feat ur es. There are thre e spe cia l mo de s

of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down

mode. The CPU clock rate may also be controlled as needed by changing clock sources,

reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a

trade-off of power versus processing speed based on application requirements. In

addition, a register is provided for shutting down the clocks to individual on-chip

peripherals, allowing fine tuning of power consumption by eliminating all dynamic power

use in any periph era ls th at ar e no t req uired for the a pplica tion. Selected per ipher als have

their own clock divide r wh ich pr ovides even better power control.

7.18.5.1 Sleep mode

When Sleep mode is entered, the clock to the core is stoppe d. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

Product data sheet Rev. 2 — 26 August 2011 26 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.18.5.2 Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition all a nalog blo cks are shut

down. As an exception, the user has the option to keep the watchdog oscillator and the

BOD circuit running for se lf-timed wake-up and BOD pr otection. Deep- sleep mod e allows

for additiona l powe r sa vin gs.

The GPIO pins PIO0_0 to PIO0_11 (up to 12 pins total) and the RTC match interrupt can

serve as a wake-up input to the start logic to wake up the chip from Deep-sleep mode.

Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source

should be switched to IRC before entering Deep-sleep mode, because the IRC can be

switched on and off glitch-free.

7.18.5.3 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

Real T ime Clock, the four general-pur pose registers, an d the W AKEUP pin. The LPC122 x

can wake up from Deep power-down mode via the WAKEUP pin or the RTC match

interrupt.

When entering Deep power-down mode, an external pull-up resistor is required on the

WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from

floating while in Deep power-down mode.

7.19 System control

7.19.1 Start logic

The start logic connects external pins to corresponding interrupts in the NVIC. Each pin

shown in Table 3 as input to the start logic has an individual interrupt in the NVIC interrupt

vector table. The start logic pins can serve as external interrupt pins when the chip is

running. In addition, an input signal on the start logic pins can wake up the chip from

Deep-sleep mode when all clocks are shut down.

The start logic must be configured in the system configuration block and in the NVIC

before being used.

7.19.2 Reset

Reset has four sources on the LPC122x: the RESET pin, the Watchdog reset, power-on

reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip re set by a ny source, on ce the ope ratin g voltage attains

a usable level, starts the IRC and initializes the flash controller.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

Product data sheet Rev. 2 — 26 August 2011 27 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

An external pull-up resistor is required on the RESET pin if Deep power-down mode is

used.

7.19.3 Brownout detection

The LPC122x includes four levels for monitoring the voltage on the VDD(3V3) pin. If this

voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to

the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the

NVIC in order to cause a CPU interrupt; if not, so ftware can monitor the signal by reading

a dedicated status register. An additional threshold level can be selected to cause a

forced reset of the chip.

7.19.4 Code security (Code Read Protection - CRP)

This feature of the LPC122x allows user to enable dif ferent levels of security in the system

so that access to the on-chip flash and use of the SWD and ISP can be restricted. When

needed, CRP is invoked by pr ogramming a specific pattern into a dedicated flash location.

IAP commands are not affected by the CRP.

There are three levels of Code Read Protection:

1. CRP1 disables access to chip via the SWD and allows partial fla sh update (exclu ding

flash sector 0) using a limited set of the ISP commands. This mode is useful when

CRP is required and flash field updates are needed but all sectors can not be erased.

2. CRP2 disabl es ac ce ss to chip via th e SWD an d on ly allo ws fu ll flash era se and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to chip via

the SWD pins and the ISP. Th is mode effect ively disables ISP override using PIO0_12

pin, too. It is up to the user’s application to provide (if needed) flash update

mechanism using IAP calls or call reinvoke ISP command to enable flash update via

UART0.

In addition to the three CRP levels, sampling of pin PIO0_12 for valid user code can be

disabled.

7.19.5 APB interface

The APB peripherals are located on one APB bus.

7.19.6 AHB-Lite

The AHB-Lite connect s the CPU bus of the ARM Cortex-M0 to the flash memory, the main

static RAM, and the Boot ROM.

7.19.7 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Product data sheet Rev. 2 — 26 August 2011 28 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

7.20 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug is supported.

7.21 Integer division routines

The LPC122x conta in perfor mance- optimized intege r division ro utines with suppor t for up

to 32-bit width in the numerator and denominator. Routines for signed and unsigned

division and division with remainder are available . The integer division routines are

ROM-based to reduce code-size.

Product data sheet Rev. 2 — 26 August 2011 29 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

8. Limiting values

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] Dependent on package type.

[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD(3V3) supply voltage (3.3 V) 3.0 3.6 V

VDD(IO) input/output supply voltage 3.0 3.6 V

VIinput voltage on all digital pins [2] 0.5 +3.6 V

on pins PIO0_10

and PIO0_11

(I2C-bus pins)

05.5V

IDD supply current per supply pin [3] - 100 mA

ISS ground current per ground pin [3] - 100 mA

Ilatch I/O latch-up current (0.5VDD) < VI <

(1.5VDD);

Tj < 125 C

- 100 mA

Tstg storage temperature [4] 65 +150 C

Ptot(pack) total power dissipation (per package) based on package

heat transfer, not

device power

consumption

-1.5W

VESD electrostatic discharge voltage human body

model; all pins [5] 8000 +8000 V

Product data sheet Rev. 2 — 26 August 2011 30 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

9. Thermal characteristics

9.1 Thermal characteristics

The average chip junction temperature, Tj (C), can be calculated using the following

equation:

(1)

•Tamb = ambient temperature (C),

•Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)

•PD = sum of internal and I/O power dissipation

The internal power dissipation is the product of IDD and VDD. The I/O power dissip ation of

the I/O pins is of ten small and ma ny times can be n egligible. However it can be significant

in some applications.

TjTamb PDRth j a–

+=

Table 6. Thermal characteristics

VDD = 3.0 V to 3.6 V; Tamb =





C to +85



C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-a) thermal resistance from

junction to ambient JEDEC test board; no

air flow

LQFP64 package

61 - C/W

LQFP48 package 86 - C/W

Rth(j-c) thermal resistance from

junction to case JEDEC test board

LQFP64 package -19 - C/W

LQFP48 package 36 - C/W

Tj(max) maximum junction

temperature --150 C

Product data sheet Rev. 2 — 26 August 2011 31 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

10. Static characteristics

Table 7. Static characteristics

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD(IO) input/output supply

voltage on pin VDD(IO) 3.0 3.3 3.6 V

VDD(3V3) supply voltage (3.3 V) 3.0 3.3 3.6 V

IDD supply current Active mode;

VDD(3V3) =3.3V;

Tamb =25C; code

while(1){}

executed from flash

all peripherals disabled:

CCLK = 12 MHz - 4.6 - mA

CCLK = 24 MHz - 9 - mA

CCLK = 33 MHz - 12.2 - mA

all peripherals enabled:

CCLK = 12 MHz - 6.6 - mA

CCLK = 24 MHz - 10.9 - mA

CCLK = 33 MHz - 14.1 - mA

Sleep mode;

VDD(3V3) = 3.3 V;

Tamb =25C;

all peripherals disabled

CCLK = 12 MHz - 1.8 - mA

CCLK = 24 MHz - 3.3 - mA

CCLK = 33 MHz - 4.4 - mA

Deep-sleep mode;

VDD(3V3) = 3.3 V;

Tamb =25C

-30-A

Deep power-down mode;

VDD(3V3) = 3.3 V;

Tamb =25C

- 720 - nA

Normal-drive output pins (S tandard port pins, RESET)

IIL LOW-level input

current VI=0V; - - 100 nA

IIH HIGH-level input

current VI=V

DD(IO); - - 100 nA

IOZ OFF-st ate output

current VO=0V; V

O=V

DD(IO); - - 100 nA

VIinput voltage pin configured to provide a

digital function [2][3][4] 0- V

DD(IO) V

VOoutput voltage output active 0 - VDD(IO) V

VIH HIGH-level input

voltage 0.7VDD(IO) --V

Product data sheet Rev. 2 — 26 August 2011 32 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

VIL LOW-level input

voltage --0.3V

DD(I

Vhys hysteresis voltage - 0.4 - V

VOH HIGH-level output

voltage low mode; IOH =2 mA VDD(IO) 

0.4 --V

high mode; IOH =4 mA VDD(IO) 

0.4 --V

VOL LOW-level output

voltage low mode; IOL =2 mA - - 0.4 V

high mode; IOL = 4 mA 0.4

IOH HIGH-level output

current low mode; VOH = VDD(IO) 

0.4 V 2- -mA

high mode; VOH = VDD(IO) 

0.4 V 4- -mA

IOL LOW-level output

current low mode; VOL =0.4V 2 - - mA

high mode; VOL =0.4V 4 - - mA

IOHS HIGH-level

short-circuit output

current

VOH =0V [5] --45 mA

IOLS LOW-level

short-circuit output

current

VOL =V

DDA [5] --50mA

Ipu pull-up current VI=0V 50 80 100 A

High-drive output pins (PIO0_27, PIO0_28, PIO0_29, PIO0_12)

IIL LOW-level input

current VI=0V; - - 100 nA

IIH HIGH-level input

current VI=V

DD(IO); - - 100 nA

IOZ OFF-st ate output

current VO=0V; V

O=V

DD(IO); - - 100 nA

VIinput voltage pin configured to provide a

digital function [2][3]

[4] 0- V

DD(IO) V

VOoutput voltage output active 0 - VDD(IO) V

VIH HIGH-level input

voltage 0.7VDD(IO) --V

VIL LOW-level input

voltage - - 0.3VDD(IO) --

Vhys hysteresis voltage - - V

VOH HIGH-level output

voltage low mode; IOH =20 mA VDD(IO) 

0.7 --V

high mode; IOH =28 mA VDD(IO) 

0.7 --V

VOL LOW-level output

voltage low mode; IOL = 12 mA - - 0.4 V

high mode; IOL = 18 mA - - 0.4 V

Table 7. Static characteristics …continued

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 2 — 26 August 2011 33 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[2] Including voltage on outputs in 3-state mode.

[3] VDD(3V3) and VDD(IO) supply voltages must be present.

[4] 3-state outputs go into 3-state mode when VDD(IO) is grounded.

[5] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[6] To VSS.

IOH HIGH-level output

current low mode; VOH = VDD(IO) 

0.7 20 - - mA

high mode; VOH = VDD(IO) 

0.7 28 - - mA

IOL LOW-level output

current VOL =0.4V

low mode 12 - - mA

high mode 18 - - mA

IOLS LOW-level

short-circuit output

current

VOL =V

DD [5] -- mA

Ipu pull-up current VI=0V 50 80 100 A

I2C-bus pins (PIO0_10 and PIO0_11)

VIH HIGH-level input

voltage 0.7VDD(IO) --V

VIL LOW-level input

voltage --0.3V

DD(I

Vhys hysteresis voltage - 0.05VDD(IO) -V

VOL LOW-level output

voltage IOLS =20 mA - - 0.4 V

ILI input leakage current VI=V

DD(IO) [6] -24A

VI=5V - 10 22 A

Cicapacitance for each

I/O pin on pins PIO0_10 and

PIO0_11 --8pF

Oscillator pins

Vi(xtal) crystal input voltage see Section 12.1 01.81.95V

Vo(xtal) crystal output voltage 0 1.8 1.95 V

Table 7. Static characteristics …continued

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 2 — 26 August 2011 34 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

10.1 Peripheral power consumption

The supply current p er peripheral is measured as the differ ence in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG

and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both

registers and no code is executed. Measured on a typical sample at Tamb =25 C and

VDD(3V3) = 3.3 V.

10.2 Power consumption

Power measurement s in Active, Sleep , and Deep-sleep mod es were performed under the

following conditions (see LPC122x user manual):

•Active mode: all GPIO pins set to input with external pull-up resistors.

•Sleep and Deep-sleep modes: all GPIO pins set to output driving LOW.

•Deep power-down mode: all GPIO pins set to input with external pull-up resistors.

Table 8. Peripher al power consumption

Peripheral Typical current consumption IDD in mA

Frequency

independent 24 MHz 12 MHz

system

oscillator + PLL IRC + PLL system

oscillator IRC

IRC 0.29 - - - -

PLL (PLL output

frequency = 24 MHz) 1.87 - - - -

WDosc (WDosc output

frequency = 500 kHz) 0.25 - - - -

BOD 0.06 - - - -

Analog comparator 0/1 - 0.05 0.05 0.03 0.02

ADC - 1.86 1.85 1.61 1.61

CRC engine - 0.04 0.04 0.02 0.02

16-bit timer 0 (CT16B0) - 0.09 0.09 0.04 0.04

16-bit timer 1 (CT16B1) - 0.09 0.09 0.04 0.04

32-bit timer 0 (CT32B0) - 0.08 0.08 0.04 0.04

32-bit timer 1 (CT32B1) - 0.08 0.08 0.04 0.04

GPIO0 - 0.34 0.34 0.17 0.17

GPIO1 - 0.34 0.34 0.17 0.17

GPIO2 - 0.36 0.37 0.18 0.18

I2C - 0.09 0.09 0.05 0.05

IOCON - 0.09 0.10 0.05 0.05

RTC - 0.10 0.10 0.05 0.05

SSP - 0.30 0.29 0.15 0.15

UART0 - 0.52 0.51 0.26 0.26

UART1 - 0.52 0.51 0.26 0.26

DMA - 0.18 0.18 0.09 0.09

WWDT - 0.06 0.06 0.03 0.03

Product data sheet Rev. 2 — 26 August 2011 35 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

Conditions: Tamb = 25 C; active mode entered executing code

while(1){}

from flash; all

peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

(3) System oscillator enabled; IRC and system PLL disabled.

Fig 6. Active mo de: Typical supply curr ent IDD versus supply voltage VDD(3V3) for

different system clock frequencies (all peripherals disabled)

Conditions: VDD(3V3) = 3.3 V; active mode entered executing code

while(1){}

from flash; all

peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

(3) System oscillator enabled; IRC and system PLL disabled.

Fig 7. Active mo de: Typical supply curr ent IDD versus temperatur e for different system

clock frequencies (pe ripherals disabled)

VDD(3V3) (V)

3 3.63.43.2

002aag186

IDD

(mA)

33 MHz(2)

24 MHz(2)

12 MHz(1)

4 MHz(3)

1 MHz(3)

12 MHz(1)

4 MHz(3)

1 MHz(3)

33 MHz(2)

24 MHz(2)

002aag023

temperature (°C)

-40 853510 60-15

IDD

(mA)

Product data sheet Rev. 2 — 26 August 2011 36 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

Conditions: Tamb = 25 C; active mode entered executing code

while(1){}

from flash; all

peripherals enabled in the SYSAHBCLKCTRL register.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

(3) System oscillator enabled with external clock input; IRC and system PLL disabled.

Fig 8. Active mo de: Typical supply curr ent IDD versus supply voltage VDD(3V3) for

different system clock frequencies (all peripherals enabled)

Conditions: VDD(3V3) = 3.3 V; active mode entered executing code

while(1){}

from flash; all

peripherals enabled in the SYSAHBCLKCTRL register.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

(3) System oscillator enabled with external clock input; IRC and system PLL disabled.

Fig 9. Active mo de: Typical supply curr ent IDD versus temperatur e for different system

clock frequencies (pe ripherals enabled)

VDD(3V3) (V)

3 3.63.43.2

002aag187

IDD

(mA)

33 MHz(2)

24 MHz(2)

12 MHz(1)

4 MHz(3)

1 MHz(3)

12 MHz(1)

4 MHz(3)

1 MHz(3)

33 MHz(2)

24 MHz(2)

002aag024

temperature (°C)

-40 853510 60-15

IDD

(mA)

Product data sheet Rev. 2 — 26 August 2011 37 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

Conditions: VDD(3V3) = 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled.

(1) System oscillator and system PLL disabled; IRC enabled.

(2) System oscillator and system PLL enabled; IRC disabled.

(3) System oscillator enabled with external clock input; IRC and system PLL disabled.

Fig 10. Sleep mode: Typical supply current IDD versus supply voltage VDD(3V3) for

different system clock frequencies

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

Fig 11. Deep-sleep mode: Typical supply current IDD versus temperature for different

supply vo ltages VDD(3V3)

VDD(3V3) (V)

3.0 3.63.43.2

002aag188

IDD

(mA)

33 MHz(2)

24 MHz(2)

12 MHz(1)

1 MHz(3)

4 MHz(3)

002aag190

IDD

(μA)

temperature (°C)

-40 853510 60-15

VDD(3V3) = 3.6 V

3.3 V

3.0 V

Product data sheet Rev. 2 — 26 August 2011 38 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

10.3 Electrical pin characteristics

Fig 12. Deep power-down mode: Typical supply current IDD versus temperature for

different supply voltages VDD(3V3)

002aag189

0.7

0.9

0.8

1.0

IDD

(μA)

0.6

temperature (°C)

-40 853510 60-15

VDD(3V3) = 3.6 V

3.3 V

3.0 V

Conditions: VDD(IO) = 3.3 V

Fig 13. High-drive pins: Typical HIGH-level output voltage VOH versus HIGH-level output

current IOH

IOH (mA)

0483216

002aag175

2.8

2.4

3.2

3.6

VOH

(V)

low mode

-40 °C

+25 °C

+70 °C

+85 °C

low mode

-40 °C

+25 °C

+70 °C

+85 °C

Product data sheet Rev. 2 — 26 August 2011 39 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

Conditions: VDD(IO) = 3.3 V

Fig 14. High-drive pins: Typical LOW-level output voltage VOL versus LOW-level output

current IOL

Conditions: VDD(IO) = 3.3 V.

Fig 15. I2C-bus pins (high current sink): Typical LOW-level output voltage VOL versus

LOW-level output current IOL

IOL (mA)

0483216

002aag310

0.4

0.8

1.2

VOL

(V)

low mode

-40 °C

+25 °C

+70 °C

+85 °C

high mode

-40 °C

+25 °C

+70 °C

+85 °C

IOL (mA)

048362412

002aag180

0.4

0.2

0.6

0.8

VOL

(V)

-40 °C

+25 °C

+70 °C

+85 °C

Product data sheet Rev. 2 — 26 August 2011 40 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

Conditions: VDD(IO) = 3.3 V.

Fig 16. Normal-drive pins: Typical LOW-level output voltage VOL versus LOW-level output

current IOL

Conditions: VDD(IO) = 3.3 V.

Fig 17. Normal-drive pins: Typical HIGH-level output vol tage VOH versus HIGH-level

output source curre n t IOH

002aag181

IOL (mA)

0161284

0.4

0.8

1.2

VOL

(V)

40 °C

+25 °C

+70 °C

+85 °C

40 °C

+25 °C

+70 °C

+85 °C

low mode

high mode

IOH (mA)

0161284

002aag182

2.6

2.2

3.0

3.4

VOH

(V)

1.8

-40 °C

+25 °C

+70 °C

+85 °C

-40 °C

+25 °C

+70 °C

+85 °C

low mode

high mode

Product data sheet Rev. 2 — 26 August 2011 41 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

Conditions: VDD(IO) = 3.3 V.

Fig 18. Typical pull-up current Ipu versus input voltage VI

VI (mA)

0 321

002aag185

-60

-40

-80

-20

Ipu

(mA)

-100

+85 °C

+70 °C

+25 °C

-40 °C

Product data sheet Rev. 2 — 26 August 2011 42 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

10.4 ADC characteristics

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[2] Conditions: VSS =0V, V

DD(3V3) =3.3V.

[3] The ADC is monotonic, there are no missing codes.

[4] The differential linearity error (ED) is the difference between the actual step width and the ideal step width.

See Figure 19.

[5] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and

the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 19.

[6] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the

straight line which fits the ideal curve. See Figure 19.

[7] The gain error (EG) is the relative difference in percent betw een the straight line fitting the actual transfer

curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 19.

[8] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer

curve of the non-calibrated ADC and the ideal transfer curve. See Figure 19.

[9] Tamb = 25 C; maximum sampling frequency fs = 257 kHz and analog input capacitance Cia = 1 pF.

[10] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs  Cia).

Table 9. ADC static characteristics

Tamb =





C to +85



C unless otherwise specified; ADC frequency 9 MHz, VDD(3V3) = 3.0 V to

3.6 V.

Symbol Parameter Conditions Min Typ[1] Max Unit

VIA analog input voltage 0 - VDD(3V3) V

Cia analog input capacitance - - 1 pF

EDdifferential linearity error [2][3][4] --  1LSB

EL(adj) integral non-linearity [2][5] --  2.5 LSB

EOoffset error [2][6] --  1LSB

EGgain error [2][7] --  3LSB

ETabsolute er ror [2][8] --  3LSB

fc(ADC) ADC conversion frequency - - 257 kHz

Riinput resistance [9][10] -- 3.9 M

Product data sheet Rev. 2 — 26 August 2011 43 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

(1) Example of an actual transfer cur ve.

(2) The ide al transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 19. ADC characteristics

002aae787

1023

1022

1021

1020

1019

(2)

(1)

10241018 1019 1020 1021 1022 1023

7123456

1018

(5)

(4)

(3)

1 LSB

(ideal)

code

out

VDD(3V3) − VSS

1024

offset

error

gain

error

offset error

VIA (LSBideal)

1 LSB =

Product data sheet Rev. 2 — 26 August 2011 44 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

10.5 BOD static characteristics

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC122x

user manual.

Table 10. BOD static characteristics[1]

Tamb =25



Symbol Parameter Conditions Min Typ Max Unit

Vth threshold voltage interrupt level 1

assertion - 2.25 - V

de-assertion - 2.39 - V

interrupt level 2

assertion - 2.54 - V

de-assertion - 2.67 - V

interrupt level 3

assertion - 2.83 - V

de-assertion - 2.93 - V

reset level 1

assertion - 2.04 - V

de-assertion - 2.18 - V

reset level 2

assertion - 2.34 - V

de-assertion - 2.47 - V

reset level 3

assertion - 2.62 - V

de-assertion - 2.76 - V

Product data sheet Rev. 2 — 26 August 2011 45 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

11. Dynamic characteristics

11.1 Power-up ramp conditions

[1] See Figure 20.

[2] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up.

Table 11. Power-up characteristics

Tamb =40 C to +85 C.

Symbol Parameter Conditions Min Typ Max Unit

trrise time at t = t1: 0 < VI 400 mV [1] 0- 500 ms

twait wait time [1][2] 12 - - s

VIinput voltage at t = t1 on pin VDD 0 - 400 mV

Condition: 0 < VI 400 mV at start of power-up (t = t1)

Fig 20. Power-up ramp

400 mV

wait

t = t

1002aag001

Product data sheet Rev. 2 — 26 August 2011 46 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

11.2 Flash memory

[1] Erase and programming times are valid over the lifetime of the device (minimum 20000 cycles).

[2] Number of program/erase cycles.

11.3 External clock

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

Table 12. Dynamic characteristic: flash memory

Tamb =





C to +85



C; VDD(3V3) over specified rang e s.

Symbol Parameter Conditions Min Max Unit

ter erase time for one page (512 byte) [1] -20ms

for one sector (4 kB) [1] 162 ms

for all sectors; mass

erase [1] -20ms

tprog programming

time one word (4 bytes) [1] -49s

four sequential words [1] -194s

128 bytes (one row of 32

words) [1] -765s

Nendu endurance [2] 20000 - cycles

tret retention time 10 - years

Table 13. Dynamic characteristic: external clock

Tamb =





C to +85



C; VDD(3V3) over specified rang e s.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc oscillator frequency 1 - 25 MHz

Tcy(clk) clock cycle time 40 - 1000 ns

tCHCX clock HIGH time Tcy(clk) 0.4--ns

tCLCX clock LOW time Tcy(clk) 0.4--ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Fig 21. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)

tCHCL tCLCX tCHCX

Tcy(clk)

tCLCH

002aaa907

Product data sheet Rev. 2 — 26 August 2011 47 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

11.4 Internal oscillators

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %.

[3] See the LPC122x user manual.

Table 14. Dynamic characteristic: internal oscillators

Tamb =





C to +85



C; VDD(3V3) over specified rang e s.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc(RC) internal RC oscillator frequency - 11.88 12 12.12 MHz

Fig 22. Internal RC oscillator frequency versus temperature

Table 15. Dynamic characteristics: Watchdog oscillator

Symbol Parameter Conditions Min Typ[1] Max Unit

fosc(int) internal oscillator

frequency DIVSEL = 0x1F, FREQSEL = 0x1

in the WDTOSCCTR L register; [2][3] -7.8 - kHz

DIVSEL = 0x00, FREQSEL = 0xF

in the WDTOSCCTR L register [2][3] - 1700 - kHz

002aag020

11.95

12.05

12.15

fosc(RC)

(MHz)

11.85

temperature (°C)

−40 853510 60−15

VDD = 3.6 V

3.3 V

3.0 V

12 MHz + 1%

12 MHz − 1%

Product data sheet Rev. 2 — 26 August 2011 48 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

11.5 I2C-bus

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[4] Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.

[5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified tf.

[6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

[7] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or

tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If

the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[8] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the

acknowledge.

[9] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

Table 16 . Dynamic characteristic: I 2C-bus pins

Tamb =





C to +85



C.[1]

Symbol Parameter Conditions Min Max Unit

fSCL SCL clock frequency Standard-mode 0 100 kHz

Fast-mode 0 400 kHz

Fast-mode Plus 0 1 MHz

tffall time [3][4][5][6] of both SDA and

SCL signals

Standard-mode

-300ns

Fast-mode 20 + 0.1  Cb300 ns

Fast-mode Plus - 120 ns

tLOW LOW period of the SCL clock Standard-mode 4.7 - s

Fast-mode 1.3 - s

Fast-mode Plus 0.5 - s

tHIGH HIGH period of the SCL clock Standard-mode 4.0 - s

Fast-mode 0.6 - s

Fast-mode Plus 0.26 - s

tHD;DAT data hold time [2][3][7] Standard-mode 0 - s

Fast-mode 0 - s

Fast-mode Plus 0 - s

tSU;DAT data set-up time

[8][9] Standard-mode 250 - ns

Fast-mode 100 - ns

Fast-mode Plus 50 - ns

Product data sheet Rev. 2 — 26 August 2011 49 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

Fig 23. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

HD;DAT

SCL

1 / f

SCL

70 %

30 % 70 %

30 %

VD;DAT

HIGH

LOW

SU;DAT

Product data sheet Rev. 2 — 26 August 2011 50 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

12. Application information

12.1 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommende d that the inpu t be coupled throug h a cap acitor with

Ci = 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground Cg which attenuate s the input volt age by a facto r Ci/(Ci + Cg). In slave

mode, a minimum of 200 mV(RMS) is needed.

12.2 XTAL Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors C x1,Cx2, and Cx3 in case of

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be made as small as possible in

order to keep the no ise couple d in via th e PCB as sm all as po ss ible . A lso parasitic s

should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

Fig 24. Slave mode operation of the on-chip oscillator

LPC1xxx

XTALIN

100 pF Cg

002aae788

Product data sheet Rev. 2 — 26 August 2011 51 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

12.3 ElectroMagnetic Compatibility (EMC)

Radiated emission measurements according to the IEC61967-2 standard using the

TEM-cell method are shown for the LPC1227FBD64/301 in Table 17.

[1] IEC levels refer to Appendix D in the IEC61967-2 Specification.

Table 17. ElectroMagnetic Compatibility (EMC) for part LPC1227FBD64/301 (TEM-cell

method)

VDD = 3.3 V; Tamb = 25



Parameter Frequency band System clock = Unit

12 MHz 24 MHz 33 MHz

Input clock: IRC (12 MHz)

maximum

peak level 150 kHz - 30 MHz 4.2 3.8 6.4 dBV

30 MHz - 150 MHz 7.3 5.4 9 dBV

150 MHz - 1 GHz 16.4 20.1 23.4 dBV

IEC level[1] - MLL-

Input clock: crystal oscillator (12 MHz)

maximum

peak level 150 kHz - 30 MHz 4.8 46.6 dBV

30 MHz - 150 MHz 6.9 5.6 10 dBV

150 MHz - 1 GHz 16.3 20.3 22.3 dBV

IEC level[1] - MLL-

Product data sheet Rev. 2 — 26 August 2011 52 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

13. Package outline

Fig 25. Package outline SOT314-2 (LQFP64)

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05 1.45

1.35 0.25 0.27

0.17 0.18

0.12 10.1

9.9 0.5 12.15

11.85 1.45

1.05 7

0.12 0.11 0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT314-2 MS-026136E10 00-01-19

03-02-25

D(1) (1)(1)

10.1

9.9

12.15

11.85

1.45

1.05

EA1

detail X

(A )

HA2

vMB

vMA

48 33

pin 1 index

0 2.5 5 mm

scale

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2

Product data sheet Rev. 2 — 26 August 2011 53 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

Fig 26. Package outline SOT313-2 (LQFP48)

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05 1.45

1.35 0.25 0.27

0.17 0.18

0.12 7.1

6.9 0.5 9.15

8.85 0.95

0.55 7

0.12 0.10.21

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT313-2 MS-026136E05 00-01-19

03-02-25

D(1) (1)(1)

7.1

6.9

9.15

8.85

0.95

0.55

vMB

vMA

36 25

detail X

(A )

0 2.5 5 mm

scale

pin 1 index

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2

Product data sheet Rev. 2 — 26 August 2011 54 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

14. Soldering

Fig 27. Re flow soldering of the LQFP48 package

SOT313-2

DIMENSIONS in mm

occupied area

Footprint information for reflow soldering of LQFP48 package

AyBy

D2 (8×)D1

(0.125)

Ax Ay Bx By D1 D2 Gx Gy Hx Hy

10.350

0.560 10.350 7.350 7.350

0.500 0.280

1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr

solder land

Generic footprint pattern

Refer to the package outline drawing for actual layout

Product data sheet Rev. 2 — 26 August 2011 55 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

Fig 28. Re flow soldering of the LQFP64 package

SOT314-2

DIMENSIONS in mm

occupied area

Footprint information for reflow soldering of LQFP64 package

AyBy

P1P2

D2 (8×) D1

(0.125)

Ax Ay Bx By D1 D2 Gx Gy Hx Hy

13.300 13.300 10.300 10.300

0.500

0.560 0.280

1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr

solder land

Generic footprint pattern

Refer to the package outline drawing for actual layout

Product data sheet Rev. 2 — 26 August 2011 56 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

15. Abbreviations

Table 18. Abbreviations

Acronym Description

ADC Analog-to-Digital-Converter

AHB Advanced Hig h-performance Bus

APB Advanced Peripheral Bus

BOD BrownOut Detection

CCITT Comité Consultatif International Téléphonique et Télégraphique

CRC Cyclic Redundancy Check

DMA Direct Memory Access

FIFO First-In-First-Out

GPIO General Purpose Input/Output

I/O Input/Output

IrDA Infrared Data Association

IRC Internal Resistor-Capacitor

JEDEC Joint Electron Devices Engineering Council

PLL Phase-Locked Loop

SPI Serial Peripheral Interface

SSI Serial Synchronous Interface

SSP Synchronous Serial Port

UART Universal Asynchronous Receiver/Tra nsmitter

Product data sheet Rev. 2 — 26 August 2011 57 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

16. Revision history

Table 19. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC122X v.2 20110826 Product data sheet - LPC122X v.1.2

Modifications: •Power consumption data updated in Table 7.

•Power consumption graphs added in Section 10.2.

•Electrical pin characteristics updated for all pins in Table 7 and Section 10.3.

•Parameter Ri added to Table 9.

•EMC data added (Section 12.3).

•Parameter VI updated for I2C-bus pins in Table 5.

•Section 11.1 “ Power-up ramp conditions” added.

•Data sheet status updated to Product Data Sheet.

•SSP dynamic characteristics removed.

LPC122X v. 1.2 20110329 Objective data sheet - LPC122X v.1.1

Modifications: •Figure 2 “Pin configuration LQFP64 package”: Pin RTCXIN changed to 58 and pin

RTCXOUT changed to 57.

•Table 3 “LPC122x pin description”: In column Pin LQFP64, pin RTCXIN changed to 58

and pin RTCXOUT changed to 57.

LPC122X v. 1.1 20110221 Objective data sheet - LPC122X v.1

Modifications: •Section 1 “General description”: Upda ted text.

•Section 2 “Features and benefits”: Updated text.

LPC122X v. 1 20110214 Objective data sheet - -

Product data sheet Rev. 2 — 26 August 2011 58 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) d escribed in th is docume nt may have changed since this docume nt was pub lished and may dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conf lict with the short data sheet, the

full data sheet shall pre vail.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

17.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semicondu ctors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descripti ons, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-crit ical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associate d with t heir

applications and products.

NXP Semiconductors does not accept any liabil ity related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the appl ication or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] dat a sheet Production This document contains the product specificatio n.

Product data sheet Rev. 2 — 26 August 2011 59 of 61

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors prod uct is automotive qualified,

the product is not suitable for automotive use. It i s neit her qua lif ied nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

17.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 2 — 26 August 2011 60 of 61

continued >>

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

7 Functional description . . . . . . . . . . . . . . . . . . 16

7.1 ARM Cortex-M0 processor. . . . . . . . . . . . . . . 16

7.1.1 System tick timer . . . . . . . . . . . . . . . . . . . . . . 16

7.2 On-chip flash program memory . . . . . . . . . . . 16

7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 16

7.4 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.5 Nested Vectored Interrupt Controller (NVIC) . 17

7.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.5.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 18

7.6 IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 18

7.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.7 Micro DMA controller . . . . . . . . . . . . . . . . . . . 18

7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.8 CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.9 Fast general purpose parallel I/O . . . . . . . . . . 19

7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.10 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.11 SSP/SPI serial I/O controller . . . . . . . . . . . . . 20

7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.12 I2C-bus serial I/O controller . . . . . . . . . . . . . . 20

7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.13 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.14 Comparator block . . . . . . . . . . . . . . . . . . . . . . 21

7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.15 General purpose external event

counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 22

7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.16 Windowed WatchDog timer (WWDT). . . . . . . 22

7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.17 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . 23

7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.18 Clocking and power control . . . . . . . . . . . . . . 23

7.18.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 23

7.18.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 24

7.18.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 24

7.18.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 25

7.18.2 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.18.3 Clock output. . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.18.4 Wake-up process. . . . . . . . . . . . . . . . . . . . . . 25

7.18.5 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 25

7.18.5.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.18.5.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 26

7.18.5.3 Deep power-down mode . . . . . . . . . . . . . . . . 26

7.19 System control. . . . . . . . . . . . . . . . . . . . . . . . 26

7.19.1 Start logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.19.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.19.3 Brownout detection . . . . . . . . . . . . . . . . . . . . 27

7.19.4 Code security (Code Read Protection - CRP) 27

7.19.5 APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 27

7.19.6 AHB-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.19.7 External interrupt inputs. . . . . . . . . . . . . . . . . 27

7.20 Emulation and debugging . . . . . . . . . . . . . . . 28

7.21 Integer division routines. . . . . . . . . . . . . . . . . 28

8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29

9 Thermal characteristics . . . . . . . . . . . . . . . . . 30

9.1 Thermal characteristics . . . . . . . . . . . . . . . . . 30

10 Static characteristics . . . . . . . . . . . . . . . . . . . 31

10.1 Peripheral power consumption . . . . . . . . . . . 34

10.2 Power consumption . . . . . . . . . . . . . . . . . . . 34

10.3 Electrical pin characteristics. . . . . . . . . . . . . . 38

10.4 ADC characteristics . . . . . . . . . . . . . . . . . . . . 42

10.5 BOD static characteristics . . . . . . . . . . . . . . . 44

11 Dynamic characteristics. . . . . . . . . . . . . . . . . 45

11.1 Power-up ramp conditions. . . . . . . . . . . . . . . 45

11.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 45

11.3 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 46

11.4 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 47

11.5 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

12 Application information . . . . . . . . . . . . . . . . . 50

12.1 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

12.2 XTAL Printed Circuit Board (PCB) layout

guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

12.3 ElectroMagnetic Compatibility (EMC) . . . . . . 51

13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 52

14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 56

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 57

17 Legal information . . . . . . . . . . . . . . . . . . . . . . 58

17.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 58

17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 58

NXP Semiconductors LPC122x

32-bit ARM Cortex-M0 microcontroller

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 26 August 2011

Document identifier: LPC122X

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 59

18 Contact information. . . . . . . . . . . . . . . . . . . . . 59

19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60