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Digital Step Attenuator ZX76-15R5-SP
ZX76-15R5-SP+
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Simplified Schematic
The ZX76-15R5-SP(+) Serial interface consists of 5 control bits that select the desired attenuation state, as
shown in Table 1: Truth Table
Figure 1: Serial Interface Timing Diagram
Table 2. Serial Interface AC Characteristics
Symbol Parameter Min. Max. Units
fclk
Serial data clock
frequency (Note 1) 10 MHz
tclkH Serial clock HIGH time 30 ns
tclkL Serial clock LOW time 30 ns
tLESUP
LE set-up time after last
clock falling edge 10 ns
tLEPW
LE minimum pulse
width 30 ns
tSDSUP
Serial data set-up time
before clock rising edge 10 ns
tSDHLD
Serial data hold time
after clock falling edge 10 ns
Note 1. fclk verified during the functional pattern test. Serial programming
sections of the functional pattern are clocked at 10MHz to verify fclk speci-
fication.
The serial interface is a 5-bit serial in, parallel-out shift register buffered by a transparent latch.
It is controlled by three CMOS-compatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock
inputs allow data to be serially entered into the shift register, a process that is independent of the state of
the LE input.
The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift
register control the attenuator. When LE is brought LOW, data in the shift register is latched.
The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as
data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data.
The timing for this operation is defined by Figure 1 (Serial Interface Timing Diagram) and Table 2 (Serial
Interface AC Characteristics).
Control cables for programming and CD with software can be ordered separately. For details see page 10.
Digital Serial Control
RF Input
8dB 4dB 2dB 1dB 0.5dB
RF Out
.
Table 1. Truth Table
Attenuation
State C8 C4 C2 C1 C0.5
Reference 00000
0.5 (dB) 00001
1 (dB) 00010
2 (dB) 00100
4 (dB) 01000
8 (dB) 10000
15.5 (dB) 11111
Note: Not all 32 possible combinations of C0.5 - C8 are shown
in table
LE
Clock
Data MSB LSB
tLESUP
t
SDSUP
t
SDHLD
t
LEPW