UC2842A/3A/4A/5A UC3842A/3A/4A/5A (R) HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER . .. . . .. .. TRIMMED OSCILLATOR DISCHARGE CURRENT CURRENT MODE OPERATION TO 500kHz AUTOMATIC FEED FORWARD COMPENSATION LATCHING PWM FOR CYCLE-BY-CYCLE CURRENT LIMITING INTERNALLY TRIMMED REFERENCE WITH UNDERVOLTAGE LOCKOUT HIGH CURRENT TOTEM POLE OUTPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS LOW START-UP CURRENT (< 0.5mA) DOUBLE PULSE SUPPRESSION Minidip SO8 comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the offstate. Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC3842A and UC3844A have UVLO thresholds of 16V (on) and 10V (off), ideally suited off-line applications The corresponding thresholds for the UC3843A and UC3845A are 8.5 V and 7.9V. The UC3842A and UC3843A can operate to duty cycles approaching 100%. A range of the zero to < 50 % is obtained by the UC3844A and UC3845A by the addition of an internal toggle flip flop which blanks the output off every other clock cycle. DESCRIPTION The UC384xA family of control ICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include a trimmed oscillator for precise DUTY CYCLE CONTROL under voltage lockout featuring start-up current less than 0.5mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM BLOCK DIAGRAM (toggle flip flop used only in UC3844A and UC3845A) Vi 7 UVLO 34V GROUND S/R 5 8 5V REF INTERNAL BIAS 2.50V VREF GOOD LOGIC RT/CT VFB COMP CURRENT SENSE 4 2 1 3 6 OSC + - ERROR AMP. VREF 5V 50mA OUTPUT T 2R R S 1V R CURRENT SENSE COMPARATOR PWM LATCH UC3842A D95IN331 March 1999 1/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vi Supply Voltage (low impedance source) Vi IO Supply Voltage (Ii < 30mA) EO Output Energy (capacitive load) Value Unit 30 V Self Limiting 1 5 Output Current Analog Inputs (pins 2, 3) A - 0.3 to 5.5 J V 10 1.25 mA W Error Amplifier Output Sink Current Ptot Power Dissipation at Tamb 25 C (Minidip) Ptot Power Dissipation at Tamb 25 C (SO8) 800 mW Tstg Storage Temperature Range - 65 to 150 TJ TL Junction Operating Temperature Lead Temperature (soldering 10s) - 40 to 150 300 C C C * All voltages are with respect to pin 5, all currents are positive into the specified terminal. PIN CONNECTION (top view) Minidip/SO8 COMP 1 8 VREF VFB 2 7 Vi ISENSE 3 6 OUTPUT RT/CT 4 5 GROUND D95IN332 PIN FUNCTIONS No Function 1 COMP Description 2 VFB This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. 3 ISENSE A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. 4 RT/CT The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and cpacitor CT to ground. Operation to 500kHz is possible. 5 GROUND This pin is the combined control circuitry and power ground. 6 OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sunk by this pin. 7 VCC This pin is the positive supply of the control IC. 8 Vref This is the reference output. It provides charging current for capacitor C T through resistor RT. This pin is the Error Amplifier output and is made available for loop compensation. ORDERING NUMBERS SO8 UC2842AD1; UC2843AD1; UC2844AD1; UC2845AD1; 2/15 UC3842AD1 UC3843AD1 UC3844AD1 UC3845AD1 Minidip UC2842AN; UC2843AN; UC2844AN; UC2845AN; UC3842AN UC3843AN UC3844AN UC3845AN UC2842A/3A/4A/5A - UC3842A/3A/4A/5A THERMAL DATA Symbol Rth j-amb Description Thermal Resistance Junction-ambient. Minidip SO8 Unit 100 150 C/W max. ELECTRICAL CHARACTERISTICS ( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85C for UC284XA; 0 < Tamb < 70C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF) Symbol Parameter REFERENCE SECTION VREF Output Voltage Test Conditions Line Regulation 12V Vi 25V VREF Load Regulation 1 Io 20mA VREF/T Temperature Stability eN ISC (Note 2) 10Hz f 10KHz Tj = 25C (note 2) 50 Long Term Stability Tamb = (note 2) 5 125C, -30 Tj = 25C TA = Tlow to Thigh VOSC Oscillator Voltage Swing (peak to peak) Idischg Discharge Current (VOSC =2V) TJ = 25C ERROR AMP SECTION Input Voltage V2 VFB = 5V AVOL Unity Gain Bandwidth Ib 2 20 mV 3 25 mV 0.2 5.1 4.82 mV/C 5.18 -100 -180 5 -30 V V 50 25 V 25 -100 -180 mV mA 47 52 57 47 52 57 KHz - 0.2 1 - 0.2 1 % - 5 - - 5 - % - 1.6 - - 1.6 - V 7.8 8.3 8.8 7.8 8.3 8.8 mA 2.45 2.50 2.55 2.42 2.50 2.58 -0.1 -1 -0.1 -2 V A 2V Vo 4V 65 90 65 90 dB TJ = 25C 0.7 1 0.7 1 MHz Power Supply Rejec. Ratio 12V Vi 25V 60 70 60 70 dB Output Sink Current VPIN2 = 2.7V VPIN1 = 1.1V 2 12 2 12 mA -0.5 -1 -0.5 -1 mA 5 6.2 5 6.2 V Output Source Current VPIN2 = 2.3V VPIN1 = 5V VOUT High VPIN2 = 2.3V; RL = 15K to Ground VPIN2 = 2.7V; RL = 15K to Pin 8 CURRENT SENSE SECTION GV Gain SVR VPIN1 = 2.5V Input Bias Current VOUT Low V3 4.9 1000Hrs Output Short Circuit Frequency Change with Temp. Io 25 Output Noise Voltage fOSC/T Io 3 Line, Load, Temperature Frequency Change with Volt. VCC = 12V to 25V PSRR 20 0.2 fOSC/V BW 2 Total Output Variation OSCILLATOR SECTION fOSC Frequency Ib 4.95 5.00 5.05 4.90 5.00 5.10 Tj = 25C Io = 1mA VREF UC284XA UC384XA Unit Min. Typ. Max. Min. Typ. Max. 0.8 1.1 0.8 1.1 V (note 3 & 4) 2.85 3 3.15 2.85 3 3.15 V/V Maximum Input Signal VPIN1 = 5V (note 3) 0.9 1 1.1 1 1.1 V Supply Voltage Rejection 12 Vi 25V (note 3) Input Bias Current Delay to Output 70 0.9 70 dB -2 -10 -2 -10 A 150 300 150 300 ns 3/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions UC284XA UC384XA Unit Min. Typ. Max. Min. Typ. Max. OUTPUT SECTION VOL VOH VOLS Output Low Level Output High Level ISINK = 20mA 0.1 0.4 0.1 0.4 V ISINK = 200mA 1.6 2.2 1.6 2.2 V ISOURCE = 20mA 13 13.5 13 13.5 V ISOURCE = 200mA 12 13.5 12 13.5 V UVLO Saturation VCC = 6V; ISINK = 1mA 0.7 1.2 0.7 1.2 V tr Rise Time Tj = 25C CL = 1nF (2) 50 150 50 150 ns tf Fall Time Tj = 25C CL = 1nF (2) 50 150 50 150 ns UNDER-VOLTAGE LOCKOUT SECTION Start Threshold Min Operating Voltage After Turn-on X842A/4A 15 16 17 14.5 16 17.5 V X843A/5A 7.8 8.4 9.0 7.8 8.4 9.0 V X842A/4A 9 10 11 8.5 10 11.5 V X843A/5A 7.0 7.6 8.2 7.0 7.6 8.2 V X842A/3A 94 96 100 94 96 100 % X844A/5A 47 48 50 47 48 50 % 0 % PWM SECTION Maximum Duty Cycle Minimum Duty Cycle 0 TOTAL STANDBY CURRENT Ist Ii Viz Start-up Current Vi = 6.5V for UCX843A/45A 0.3 0.5 0.3 0.5 mA Vi = 14V for UCX842A/44A 0.3 0.5 0.3 0.5 mA 12 17 12 17 mA Operating Supply Current VPIN2 = VPIN3 = 0V Zener Voltage Ii = 25mA 30 36 30 36 V Notes : 1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close to Tamb as possible. 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at trip point of latch with VPIN2 = 0. 4. Gain defined as : VPIN1 A= ; 0 VPIN3 0.8 V VPIN3 5. Adjust Vi above the start threshold before setting at 15 V. 4/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A Figure 1: Open Loop Test Circuit. VREF RT 4.7K 2N2222 100K ERROR AMP. ADJUST 4.7K COMP VFB 1K ISENSE ADJUST A VREF ISENSE 5K RT/CT 0.1F 8 1 Vi 7 Vi 2 3 OUTPUT 6 4 1W 1K 0.1F UC3842A OUTPUT GROUND 5 CT GROUND D95IN343 High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5 K potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. Figure 2: Oscillator Frequency vs Timing Resistance Figure 3: Maximum Duty Cycle vs Timing Resistor fo (Hz) D96IN362 fo (Hz) D96IN363 80 1M CT =4 1nF 70 pF 60 2.2 100K nF 4.7 nF 40 10K 20 0 1K 300 1K 3K 10K 30K RT() 300 1K 3K 10K 30K RT() 5/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A Figure 4: Oscillator Discharge Current vs. Temperature. Idischg (mA) D95IN335 Vi=15V VOSC=2V Figure 5: Error Amp Open-Loop Gain and Phase vs. Frequency. D95IN337 (dB) Vi=15V VO=2V to 4V RL=100K TA=25C 80 Gain 8.5 60 40 8.0 30 60 Phase 90 20 120 0 150 7.5 7.0 -55 -25 0 25 50 75 100 TA(C) Figure 6: Current Sense Input Threshold vs. Error Amp Output Voltage. Vth (V) D95IN338 -20 10 100 1K 10K 100K 1M 180 f(Hz) Figure 7: Reference Voltage Change vs. Source Current. D95IN339 60 Vi=15V Vi=15V 50 1.0 TA=25C 30 0.4 20 TA=-40C 10 0.2 0 0 2 4 6 VO(V) Figure 8: Reference Short Circuit Current vs. Temperature. D95IN340 ISC (mA) Vi=15V RL0.1 100 90 80 70 60 50 -55 6/15 TA=25C TA=125C TA=125C 0.6 0.0 TA=-40C 40 0.8 -25 0 25 50 75 100 TA(C) 0 20 40 60 80 100 Iref(mA) UC2842A/3A/4A/5A - UC3842A/3A/4A/5A Figure 9: Output Saturation Voltage vs. Load Current. Ii (mA) D95IN341 Vi -1 -2 Source Saturation (Load to Ground) TA=25C TA=-40C D95IN342 20 Vi=15V 80s Pulsed Load 120Hz Rate 15 UCX843/45 3 10 TA=-40C 2 TA=25C 5 1 Sink Saturation (Load to Vi) 0 0 200 400 RT=10K CT=3.3nF VFB=0V ISense=0V TA=25C UCX842/44 Vsat (V) Figure 10: Supply Current vs. Supply Voltage. GND 0 600 IO(mA) Figure 11: Output Waveform. 0 10 20 30 Vi(V) Figure 12: Output Cross Conduction Vi =30V CL = 15pF TA = 25C Vi =15V CL = 1.0nF TA = 25C 90% VO 20V/DIV ICC 10% 100mA/DIV 50ns/DIV 100ns/DIV Figure 13: Oscillator and Output Waveforms. Vi CT 7 8 5V REG OUTPUT PWM 6 RT LARGE RT/SMALL CT OUTPUT CLOCK 4 OSCILLATOR CT ID OUTPUT CT 5 SMALL RT/LARGE CT GND D95IN344 7/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A Figure 14 : Error Amp Configuration. 2.5V 1mA + VFB 2 COMP 1 Zi - Zf D95IN345 Figure 15 : Under Voltage Lockout. 7 Vi ON/OFF COMMAND TO REST OF IC ICC UC3842A UC3843A UC3844A UC3845A VON 16V 8.4V VOFF 10V 7.6V <17mA <0.5mA VOFF VON VCC Fig.15-UC3842A Figure 16 : Current Sense Circuit . ERROR AMPL. IS COMP R RS C 1 3 CURRENT SENSE 5 GND D95IN347 Peak current (is) is determined by the formula 1.0 V IS max RS A small RC filter may be required to suppress switch transients. 8/15 2R R 1V CURRENT SENSE COMPARATOR UC2842A/3A/4A/5A - UC3842A/3A/4A/5A Figure 17 : Slope Compensation Techniques. VREG VREG 8 RT RT RT/CT IS RSLOPE 4 UC3842A RT/CT IS CT R1 8 RSLOPE ISENSE R1 3 5 RS 4 UC3842A CT ISENSE 3 5 RS GND GND D95IN348 Figure 18 : Isolated MOSFET Drive and Current Transformer Sensing. VCC Vin 7 ISOLATION BOUNDARY + 5.0Vref - VGS Waveforms + 0 - Q1 6 + S R Q 50% DC Ipk = - + 0 - V(pin 1) -1.4 3RS 25% DC NS ( ) NP + COMP/LATCH R 3 C RS NS NP D95IN349 9/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A Figure 19 : Latched Shutdown. 4 OSC 8 R BIAS R + 1mA 2R + - 2 EA R 1 5 2N 3905 2N 3903 D95IN350 SCR must be selected for a holding current of less than 0.5mA at TA(min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K. Figure 20: Error Amplifier Compensation From VO + 2.5V 1mA Ri - 2 Rd 2R + Cf EA R Rf 1 5 Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current. From VO + 2.5V 1mA RP Ri 2 CP Rd 2R + Cf Rf - EA R 1 5 D95IN351 Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current. 10/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A Figure 21: External Clock Synchronization. VREF 8 R BIAS RT R 4 EXTERNAL SYNC INPUT OSC + CT 0.01F 2R + 47 - 2 EA R 1 5 D95IN352 The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300mV below ground Figure 22: External Duty Cycle Clamp and Multi Unit Synchronization. VREF 8 RA R RB 5K 8 6 + 5 5K C S - 4 + Q + R 3 R - 2 BIAS 4 7 2 5K NE555 1 OSC 2R + - EA R 1 5 f= 1.44 (RA + 2RB)C Dmax = RB TO ADDITIONAL UCX84XAs UCX84XAs D95IN353 RA + 2RB 11/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A Figure 23: Soft-Start Circuit 8 5Vref R + BIAS - R 4 OSC + S 1mA 2R + 2 - 1M Q + EA R - 1V R 1 C 5 D95IN354 Figure 24: Soft-Start and Error Amplifier Output Duty Cycle Clamp. VCC Vin 7 8 + 5Vref R - + BIAS 7 - R 4 VClamp 1mA 2 R2 R 5 Q + EA Q1 S 2R + - 6 OSC + R 1V 1 Comp/Latch 5 C R1 RS BC109 VCLAMP = * 12/15 R1 R1 + R 2 where 0 <VCLAMP <1V Ipk(max) = VCLAMP RS D95IN355 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.25 a2 MAX. 0.069 0.004 0.010 1.65 0.065 a3 0.65 0.85 0.026 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.020 c1 45 (typ.) D (1) 4.8 5.0 0.189 0.197 E 5.8 6.2 0.228 0.244 e 1.27 e3 0.050 3.81 0.150 F (1) 3.8 4.0 0.15 0.157 L 0.4 1.27 0.016 0.050 M S OUTLINE AND MECHANICAL DATA 0.6 0.024 SO8 8 (max.) (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 13/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A mm DIM. MIN. A TYP. inch MAX. MIN. 3.32 TYP. MAX. 0.131 a1 0.51 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 0.020 D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L Z 14/15 3.18 OUTLINE AND MECHANICAL DATA 3.81 1.52 0.125 0.150 0.060 Minidip UC2842A/3A/4A/5A - UC3842A/3A/4A/5A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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