7 MACH210A-7/10/12 MACH210-12/15/20 MACH210AQ-12/15/20 COML: -7/10/12/15/20, Q-12/15/20 IND: -12/14/18/24 cl Advanced Micro Devices High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS @ 44 Pins @ 64 Macrocells @ 7.5 ns tep Commercial 12 ns tep Industrial @ 133 MHz fentr @ 38 inputs; 210A Inputs have built-in pull-up resistors @ Peripheral Component Interconnect (PCI) compliant 32 Outputs 64 Flip-flops; 2 clock choices 4PAL22V16 blocks with buried macrocells Pin-compatible with MACH110, MACH111, MACH211, and MACH215 GENERAL DESCRIPTION The MACH210is amember of AMD's high-performance EE CMOS MACH 2 device family. This device has approximately six times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH210 consists of four PAL blocks intercon- nected by a programmable switch matrix. The four PAL blocks are essentially PAL22V 16 structures complete with product-term arrays and programmable macro- cells, including additional buried macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH210 has two kinds of macrocell: output and buried. The MACH210 output macrocell provides regis- tered, latched, or combinatorial outputs with program- mable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. Ali output macrocells can be connected to an (/O cell. if a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACH210 has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers or latches for use in synchronizing signals and reducing setup time require- ments. Publication# 14128 Rev.{ Amendment/0 issue Date: May 1995 1-87iN amo BLOCK DIAGRAM lo-l1, /Oo-/07 VOs-/015 Ial4 8, 8, 0 7 7 [ V/O Cells s | VO Cells kk & & 7 8 7 8 Macrocells Macrocells Macrocells Be \ OE OE 44x68 44x 68 4 AND Logic Array AND Logic Array A and and Logic Allocator Logic Altocator 22) 22 Switch Matrix 22y 22y 44 x 68 44x68 AND Logic Array AND Logic Array and and 2 Logic Allocator Logic Allocator 4 OE : OE Macrocelis: Macrocells Macrocells 2, / ~ Te 5 7 Hy Le 7 [ /O Cells JH CLKolle, VO24-1/031 VOre-I/O23 CLKi/Is 141281-1 1-88 MACH210-7/10/12/15/20, Q-12/15/20CONNECTION DIAGRAM Top View lo |] 04 en} 1/03 > []v02 11 1/04 ho 110g ef] GND = [Vcc 3 |] VvO34 1 | VOg9 21] VO29 3 [1 VOog Os []7 Og (48 vO7 [9 io LJ 10 4 Oa anp [12 CLKo/lo [13 Og L14 Og [] 15 VOi9 Lf 16 O44 L] 17 Note: AMD cl | O27 7] VO26 al V/Oe5 |] VO24 [] CLK 4/5 [| @np a l4 a ig r] VO23 | VOoo ] vO24 141281-2 Pin-compatible with MACH110, MACH111, MACH211, and MACH215. MACH210-7/10/12/15/20, Q-12/15/20 1-89"Lt AMD CONNECTION DIAGRAM Top View TQFP eae ,8 Saag 88888389998 OPSIrsSESS5aaas VO5 C7 1 33 |[=Tr 1/027 vo6 Cr7}2 32 | 026 VO7 71/3 31 | F-17025 fo co 4 30 jE 1/024 crc 5 29 |=" CLK1/15 GND (=r 6 28 |r GND CLKO/l2 [17 27 |= 14 O08 (1/8 26 |= 13 VO9 [1-9 25 | 1 1/023 VO10 Co 10 24 | 1/022 VO11 I 11 23 | 1/021 NETHMeheeagad Sean seer eeR SSSS>FQQQG 141281-3 Note: Pin-compatible with MACH111 and MACH211. PIN DESIGNATIONS CLK/L = Clock or 'nput GND Ground I = Input VO = Input/Output Vec = Supply Voltage 1-90 MACH210-7/10/12/15/20, Q-12/15/20AMD cl ORDERING INFORMATION Commercial Products AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 210A --7) J C L OPTIONAL PROCESSING FAMILY TYPE MACH = Macro Array CMOS High-Speed Blank = Standard Processing DEVICE NUMBER 210 = 64 Macrocells, 44 Pins 210A = 64 Macrocells, 44 Pins, Input Pull-Up Resistors OPERATING CONDITIONS 210AQ = 64 Macrocells, 44 Pins, Input Pull-Up Resistors, = Commercial (0C to +70C) Quarter Power SPEED J PACKAGE TYPE -7 = 7.5nstep Jo= 44-Pin Plastic Leaded Chip -10 = 10nstpp Carrier (PL 044) : V = 44-Pin Thin Quad Flat Pack 12 = 12nstpep * (PQTO44) -15 = 15nstep -20 = 20ns tpp Valid Combinations Valid Combinations The Valid Combinations table lists configurations MACH210A-7 JC, planned to be supported in volume for this device. Con- MACH210A-10 VC sult the local AMD sales office to confirm availability of MACH?210A-12 specific valid combinations or to check on newly re- MAGH210-12 leased combinations. MAGH210-15 MAGH210-20 JC MACH210AQ-12 MACH210AQ-15 MACH210AQ-20 MACH210-7/10/12/15/20, Q-12/15/20 (Coml) 1-91al AMO ORDERING INFORMATION industrial Products AMD programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: FAMILY TYPE MACH = Macro Array CMOS High-Speed DEVICE NUMBER 210 on 64 Macrocells, 44 Pins _MACH 210A -12 J 1 L OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS 210A 64 Macrocells, 44 Pins, Input Pull-Up Resistors | = Industrial (-40C to +85C) SPEED PACKAGE TYPE -12 = 12nstep = 44-Pin Plastic Leaded Chip -14 = 14.5nstpp Carrier (PL 044) -18 = 18nstpp -24 = 24ns trp Valid Combinations Valid Combinations The Valid Combinations table lists configurations MACH210A-12 planned to be supported in volume for this device. Con- MACH210A-14 sult the local AMD sales office to confirm availability of MACH210-14 Jl specific valid combinations or to check on newly re- MACH210-18 {eased combinations. MACH210-24 1-92 MACH210-12/14/18/24 (Ind)FUNCTIONAL DESCRIPTION The MACH210 consists of four PAL blocks connected by a switch matrix. There are 32 I/O pins and 4 dedicated input pins feeding the switch matrix. These signals are distributed to the four PAL blocks for efficient design implementation. There are two clock pins that can also be used as dedicated inputs. The MACH210A inputs and I/O pins have built-in pull-up resistors. While itis always a good design practice to tie unused pins high, the 210A pull-up resistors provide design security and stability in the event that unused pins are left disconnected. The PAL Blocks Each PAL block in the MACH210 (Figure 1) contains a 64-product-term logic array, a logic allocator, 8 output macrocells, 8 buried macrocells, and 8 I/O cells. The switch matrix feeds each PAL block with 22 inputs. This makes the PAL block look effectively like an independ- ent PAL22V 16 with 8 buried macrocells. In addition to the logic product terms, two output enable product terms, an asynchronous reset product term, and an asynchronous preset product term are provided. One of the two output enable product terms can be chosen within each I/O cell in the PAL block. Allflip-flops within the PAL block are initialized together. The Switch Matrix The MACH210 switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 16 internal feedback signals and 8 1/O feedback signals. The switch matrix distributes these signals back to the PAL blocks in an efficient manner that also provides for high performance. The design software automatically configures the switch matrix when fitting a design into the device. The Product-term Array The MACH210 product-term array consists of 64 product terms for logic use, and 4 special-purpose product terms. Two of the special-purpose product terms provide programmable output enable; one pro- vides asynchronous reset, and one provides asynchro- nous preset. The Logic Allocator The logic allocator in the MACH210 takes the 64 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven by up to 16 product terms. The design software automatically configures the logic allocator when fitting the design into the device. AMD cl Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers. Table 1. Logic Allocation Macrocell Available Output Buried Clusters Mo Co, Ci, Ce Mi Co, C1, Ca, Ca Me C1, C2, Ca, C4 Ms Ca, Cs, Ca, C5 M4 Ca, Ca, Cs, Ce Ms C4, Cs, Ce, C7 Me Cs, Ce, C7, Ca M7 Ce, C7, Cs, Co Ms C7, Ca, Ca, Cio Mg Ca, Co, Cio, Cit Mio Cg, Cro, C11, Cr2 Mi1 Cio, C11, C12, Cia Mi2 Cit, Cra, C13, Cra Mi3 Ci2, Cis, Cra, Cis Mia Cis, C14, Cis Mis Cra, Cis The Macrocell The MACH210 has two types of macrocell: output and buried. The output macrocells can be configured as either registered, latched, or combinatorial, with pro- grammable polarity. The macrocell provides internal feedback whether configured with or without the flip- flop. The registers can be configured as D-type or T-type, allowing for product-term optimization. The flip-flops can individually select one of two clock/ gate pins, which are also available as data inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The latch holds its data when the gate input is HIGH, and is transparent when the gate input is LOW. The flip-flops can also be asynchronously initial- ized with the common asynchronous reset and preset product terms. The buried macrocells are the same as the output macrocells if they are used for generating logic. In that case, the only thing that distinguishes them from the output macrocells is the fact that there is no I/O cell connection, and the signal is only used internally. The buried macrocell can also be configured as an input register or latch. MACH210-7/10/12/15/20, Q-12/15/20 1-93ol AMD The I/O Cell The {/O cell in the MACH210 consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to ail {/O cells in a PAL block. These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus. PCI Compliance The MACH210A-7/10 is fully compliant with the PCf Local Bus Specification published by the PCI Special Interest Group. The MACH210A-7/10s predictable timing ensures compliance with the PCI AC specifica- tions independent of the design. On the other hand, in CPLD and FPGA architectures without predictable timing, PCI compliance is dependent upon routing and product term distribution. 1-94 MACH210-7/10/1 2/15/20, Q-12/15/20AMD cl Switch Matrix Logic Altocator 141281-4 Figure 11. MACH210 PAL Block MACH210-7/10/12/15/20, Q-12/15/20 1-95ol AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature ........... ~65C to +150C Ambient Temperature with Power Applied ............. -55C to +125C Supply Voltage with Respect io Ground ............. -0.5 V to +7.0 V DC Input Voltage ........... 0.5 V to Vcc + 0.5 V DC Output or VO Pin Voltage ............ 0.5 V to Veco + 0.5 V Static Discharge Voltage ..............06. 2001 V Latchup Current (TA = 0C 10 +-70C) 2. eee ee eee 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Pro- gramming conditions may differ. OPERATING RANGES Commercial (C) Devices Temperature (Ta) Operating in Free Air... cee ce ee eee eee 0C to +70C Supply Voltage (Vcc) with Respect to Ground ............ +4.75 V to +5.25 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter _ Symbol Parameter Description Test Conditions Min | Typ | Max] Unit Vou Output HIGH Voltage loH =-3.2 mA, Vcc = Min 2.4 Vv ViN = VIH or VIL VoL Output LOW Voltage lo. = 16 mA, Vcc = Min 0.5 v Vin = Vin or Vit Vin Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voltage for all Inputs (Note 1) Vit Input LOW Voltage Guaranteed Input Logical LOW 0.8 v Voltage for all Inputs (Note 1) {te Input HIGH Leakage Current VIN = 5.25 V, Voc = Max (Note 2) 10 pA lit input LOW Leakage Current Vin = 0 V, Voc = Max (Note 2) -100} pA loz Off-State Output Leakage Vout = 5.25 V, Voc = Max 10 pA Current HIGH Vin = Vin or Vit (Note 2) loz Off-State Output Leakage Vout = 0 V, Vcc = Max ~100] pA Current LOW Vin = Vin or Vit (Note 2) Isc Output Short-Circuit Current VouT = 0.5 V, Voc = Max (Note 3) -30 -160} mA Ioc Supply Current Vin= 0 V, Outputs Open (lout = 0 mA) 130 mA Voc = 5.0 V, f = 25 MHz, Ta = 25C (Note 4) Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. VO pin leakage is the worst case of Ii, and lozz (or liq and lozx). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is measured with a 16-bit up/down counter pattem. This pattem is programmed in each PAL blockand capable of being loaded, enabled, and reset. 1-96 MACH210A-7 (Coml)AMD cl CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance VIN = 2.0 V Veo = 5.0 V, Ta = 25C, 6 pF Cout Output Capacitance VouT= 2.0 V f=1MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Parameter 7 Symbol Parameter Description Min Max Unit tpp Input, I/O, or Feedback to Combinatorial Output 75 | ns ts Setup Time from Input, 1/O or Feedback to Clock D-Type 5.5 ns T-Type 6.5 ns tH Register Data Hoid Time 0 ns tco Clock to Output 5 ns twe Clock Width LOW 3 ns tWH HIGH 3 ns External Feedback D-type 100 MHz Maximum T-Type 91 MHz Max | Frequency! smal Feedback (fonr) pType = m T-Type 125 MHz No Feedback 166.7 MHz tsL Setup Time from Input, /O, or Feedback to Gate 5.5 ns tHE Latch Data Hold Time 0 ns tao Gate to Output 6 ns few. Gate Width LOW 3 ns tpoL Input, /O, or Feedback to Output Through 9.5 ns Transparent Input or Output Latch tsIR Input Register Setup Tima ns tHIR Input Register Hold Time ns tico Input Register Clock to Combinatorial Output 1 ns tics Input Register Clock to Output Register Setup D-Type 9 ns T-Type 10 ns twice Input Register Clock Width LOW 3 ns twicH HIGH ns IMAXIR Maximum Input Register Frequency 166.7 MHz tsiL Input Latch Setup Time 2 ns tHIL Input Latch Hold Time ns tigo Input Latch Gate to Combinatorial Output 12 ns tiGoL Input Latch Gate to Output Through Transparent Output Latch 14 ns tSLL Setup Time from Input, /O, or Feedback Through 7.56 ns Transparent Input Latch to Output Latch Gate MACH210A-7 (Coml) 1-97a AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (continued) Parameter 77 Symbol Parameter Description Min Max Unit ties Input Latch Gate to Output Latch Setup 10 ns tWIGL Input Latch Gate Width LOW 3 ns {PDLL Input, [/O, or Feedback to Output Through Transparent 11.5 ns Input and Output Latches . tar Asynchronous Reset to Registered or Latched Output 12 ns taRw Asynchronous Reset Width 8 ns taRR Asynchronous Reset Recovery Time 8 ns tap Asynchronous Preset to Registered or Latched Output 12 ns tapw Asynchronous Preset Width 8 ns taPR Asynchronous Preset Recovery Time 8 ns tea Input, I/O, or Feedback to Output Enable 7.5 ns teR Input, I/O, or Feedback to Output Disable 75 ns Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 1-98 MACH210A-7 (Coml)ABSOLUTE MAXIMUM RATINGS Storage Temperature ........... -65C to +150C Ambient Temperature with Power Applied ............. ~65C to +125C Supply Voltage with Respect to Ground ............. 0.5 V to +7.0 V DC Input Voltage........... -0.5 Vto Veco + 0.5 V DC Output or VO Pin Voltage ............ 0.5 V to Vcc + 0.5 V Static Discharge Voltage ................. 2001 V Latchup Current (Ta = 0C to +70C) ...... 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. AMD ol OPERATING RANGES Commercial (C) Devices Temperature (Ta) Operating in Free Air... ... ee cece eee wees 0C to +70C Supply Voltage (Vcc) with Respect to Ground ............ +4.75 V to +5.25 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit Vou Output HIGH Voltage lon = -3.2 mA, Voc = Min 2.4 Vv Vin = Vie or Vit Vou Output LOW Voltage lo. = 16 MA, Veo = Min 0.5 Vv Vin = Vin or Viv Vin Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 v Voltage for all inputs (Note 1) Vir Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 1) hy Input HIGH Leakage Current Vw = 5.25 V, Voc = Max (Note 2) 10 pA he Input LOW Leakage Current Vin = 0 V, Voc = Max (Note 2) -100 uA loz Off-State Output Leakage Vour = 5.25 V, Voc = Max 10 pA Current HIGH Vin = Vinor Vu, (Note 2) loz. Off-State Output Leakage Vour = 0 V, Veco = Max -100 pA Current LOW Vin = Vinor Vit (Note 2) Isc Output Short-Circuit Current Vour = 0.5 V, Voc = Max (Note 3) ~30 -160 mA loc Supply Current (Typical) Vec= 5V, Ta= 25C, f = 25 MHz 135 mA (Note 4) - Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. VO pin leakage is the worst case of In. and loz. (or ht and loz). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Vour = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4, Measured with a 16-bit up/down counter pattem. This loaded, enabled, and reset. pattem is programmed in each PAL block and is capable of being MACH210A-10/12 (Coml) 1-99a AMD CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit Cin Input Capacitance Vin= 2.0 V Vcc = 5.0 V, Ta = 25C, 6 pF Cour Output Capacitance Vour=2.0V |} f=1MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter -10 12 Symbol! | Parameter Description Min | Max| Min| Max| Unit tep Input, I/O, or Feedback to Combinatorial Output (Note 3) 10 12 ns ts Setup Time from Input, /O, D-Type 6.5 ns or Feedback to Clock T-Type 75 ns tH Register Data Hold Time 0 ns tco Clock to Output (Note 3) 6 8 ns tw. Clock LOW 5 6 ns twu Width HIGH 5 6 ns D-Type 80 66.7 MHz Maxirnum External Feedback | 1/(ts + tco) T-Type 74 625 MHz fMax Frequency D-Type 100 83.3 MHz (Note 1) Internal Feedback (fcnT) T-Type 1 769 MHz No Feedback i/(ts + ty) 100 83.3 MHz tsi Setup Time from Input, /O, or Feedback to Gate 6.5 7 ns tu Latch Data Hold Time 0 0 ns tao Gate to Output (Note 3) 7 10 ns tewt Gate Width LOW 5 6 ns tept Input, /O, or Feedback to Output Through Transparent Input or Output Latch 12 14 ns tsin Input Register Setup Time 2 2 ns tur Input Register Hold Time 2 2 ns tico Input Register Clock to Combinatorial Output 13 15 ns tics Input Register Clock to Output Register Setup D-Type 10 12 ns T-Type 11 13 ns twice Input Register LOW 5 6 ns twickt Clock Width HIGH 5 6 ns faxin Maximum Input Register Frequency | 1/(twict. + twicy) 100 83.3 MHz tsit Input Latch Setup Time 2 2 ns tHe Input Latch Hold Time 2 2 ns tico Input Latch Gate to Combinatorial Output 14 17 | ns tigot Input Latch Gate to Output Through Transparent Output Latch 16 19 ns tsi Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 8.5 9 ns ties Input Latch Gate to Output Latch Setup 11 13 ns 1-100 MACH210A-10/12 (Coml)SWITCHING CHARACTERISTI AMD cl CS over COMMERCIAL operating ranges (Note 2) (continued) Parameter; -12 Symbol | Parameter Description Min | Max| Min] Max] Unit twie. Input Latch Gate Width LOW 5 6 ns teow Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 14 16 ns tar Asynchronous Reset to Registered or Latched Output 25 16 ns tanw Asynchronous Reset Width (Note 1) 10 12 ns taRR Asynchronous Reset Recovery Time (Note 1) 10 8 ns tap Asynchronous Preset to Registered or Latched Output 15 16 ns tapw Asynchronous Preset Width (Note 1) 10 12 ns taPr Asynchronous Preset Recovery Time (Note 1) 10]. 8 ns tea Input, I/O, or Feedback to Output Enable (Note 3) 10 12 ns ter input, i/O, or Feedback to Output Disable (Note 3) 10 12 ns Notes: 1, These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. MACH210A-10/12 (Coml) 1-101zt AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature ........... -65C to +150C Ambient Temperature with Power Applied ............. 56C to +125C Supply Voltage with Respect to Ground ............. -0.5 V to +7.0 V DC Input Voltage ........... ~0.5 V to Veo + 0.5 V DC Output or VO Pin Voltage ............ 0.5 V to Veo + 0.5 V Static Discharge Voltage ...........22 000. 2001 V Latchup Current (Ta = 0C to +70C) ...... 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. INDUSTRIAL OPERATING RANGES Temperature (Ta) Operating in Free Air... 2... cee eee 40C to +85C Supply Voltage (Vcc) with Respect to Ground ...........-65 +4.5 V to +6.5 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit Vou Output HIGH Voltage lox =-3.2 MA, Veo = Min 2.4 Vv Vin = Vin or Vit Vo. Output LOW Voltage lo. = 16 MA, Voc = Min 0.5 v Vin = Vin or Vit Vin Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voltage for all Inputs (Note 1) Vie Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all inputs (Note 1) tin Input HIGH Leakage Current Vin = 5.25 V, Voc = Max (Note 2) 10 pA fie Input LOW Leakage Current Vin = 0 V, Voc = Max (Note 2) -100 pA loz Off-State Output Leakage Vour = 5.25 V, Veco = Max 10 pA Current HIGH Vin = Vinor Vi. (Note 2) loz. Off-State Output Leakage Vour = 0 V, Vec = Max -100 pA Current LOW : Vin = Viwor Vi. (Note 2) Isc Output Short-Circuit Current Vour = 0.5 V, Vec = Max (Note 3) -30 -160 mA lec Supply Current (Typical) Vec= 5V, Ta= 28C, f = 25 MHz 135 mA (Note 4) Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. VO pin leakage is the worst case of Ii, and lozz (or lit and lozx). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4, Measured with a 16-bit up/down counter pattem. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. 1-102 MACH210A-12/14 (Ind)pot AM CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit Cin Input Capacitance Vin= 2.0 V Voc = 5.0 V, Ta = 25C, 6 pF Cour Output Capacitance Vout=2.0V | f=1MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter 12 14 Symbol | Parameter Description Min| Max} Min] Max| Unit tep Input, /O, or Feedback to Combinatorial Output (Note 3) 12 14.5] ns ts Setup Time from Input, I/O, D-Type 8 8.5 ns or Feedback to Clack T-Type 9 10 ns ty Register Data Hold Time 0 0 ns tco Clock to Output (Note 3) 7.5 10 ns two Clock LOW 6 7.5 ns twH Width HIGH 6 7.5 ns D-Type 64 53 MHz Maximum External Feedback | 1/(ts + tco) T-Type 59 50 Maz faux Frequency D-Type 80 61.5 MHz (Note 1) Internal Feedback (font) T-Type 72.5 57 MHz No Feedback | t/(ts + tu) 80 66.5 _ MHz ts. Setup Time from Input, I/O, or Feedback to Gate 8 8.5 ns tut, Latch Data Hold Time 0 0 ns tao Gate to Output (Note 3) 8.5 12 ns tawt Gate Width LOW 6 7.5 ns tro. Input, /O, or Feedback to Output Through Transparent Input or Output Latch 14.5 17 ns tsir input Register Setup Time 2.5 2.5 ns thin Input Register Hold Time 3 3 ns tico Input Register Clock to Combinatorial Output 16 18 ns tics Input Register Clock to Output Register Setup D-Type 12 14.5 ns T-Type 13 16 ns twiet Input Register LOW. 6 7.5 ns twich Clock Width HIGH 6 7.5 ns fuaxin Maximum Input Register Frequency | 1/(twict + twicy) 80 66.5 MHz tsit Input Latch Setup Time 2.5 2.5 ns tu Input Latch Hold Time 3 3 ns tigo Input Latch Gate to Combinatorial Output 17 20.5} ns tigot Input Latch Gate to Output Through Transparent Output Latch 19.5 23 | ns ts. Setup Time from input, 1/O, or Feedback Through - Transparent Input Latch to Output Latch Gate 10.5 11 ns ties Input Latch Gate to Output Latch Setup 13.5 16 ns MACH210A-12/14 (Ind) 1-103un AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter -12 -14 Symbol Parameter Description Min | Max|{ Min| Max] Unit twict Input Latch Gate Width LOW 6 75 ns tPoLe Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 17 19.5| ns tar Asynchronous Reset to Registered or Latched Output 19.5 19.5] ns tanw Asynchronous Reset Width (Note 1) 12 14.5 ns taRR Asynchronous Reset Recovery Time (Note 1) 12 10 ns tap Asynchronous Preset to Registered or Latched Output 18 19.5} ns tapw Asynchronous Preset Width (Note 1) 12 14.5 ns tapr Asynchronous Preset Recovery Time (Note 1) 12 10 ns tea Input, 1/0, or Feedback to Output Enable (Note 3) 12 14.5} ns ter Input, I/O, or Feedback to Output Disable (Note 3) 12 14.5] ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 1-104 MACH210A-12/14 (Ind)ABSOLUTE MAXIMUM RATINGS Storage Temperature ........... 65C to +150C Ambient Temperature with Power Applied ............. 55C to +125C Supply Voltage with Respect to Ground ............. -0.5Vt0+7.0V DC input Voltage ........... 0.5 V to Vec + 0.5 V DC Output or /O Pin Voltage ............ 0.5 V to Vec + 0.5 V Static Discharge Voltage ................. 2001 V Latchup Current (Ta = 0C to +70C) ...... 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. AMD cl OPERATING RANGES Commercial (C) Devices Temperature (Ta) Operating in Free Air... 2... ee eee eee 0C to +70C Supply Voltage (Vcc) with Respect to Ground ............ +4.75 V to +5.25 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit Vou Output HIGH Voltage lon = 3.2 MA, Voc = Min 2.4 Vv Vin = Vie or Vic Vor Output LOW Voltage lo. = 16 MA, Voc = Min 0.5 Vv Vin = Via or Vin Vi Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voltage for ail Inputs (Note 1) Vi Input LOW Voltage Guaranieed Input Logical LOW 0.8 Vv Voitage for all Inputs (Note 1) le Input HIGH Leakage Current | Vin = 5.25 V, Voc = Max (Note 2) 10 pA te Input LOW Leakage Current Vin = 0 V, Voc = Max (Note 2) ~10 pA lozn Off-State Output Leakage Vour = 5.25 V, Voc = Max 10 pA Current HIGH Vin = Vor Vii (Note 2) loz. Off-State Output Leakage Vour = 0 V, Vec = Max -10 pA Current LOW Vin = Viwor Vii (Note 2) Isc Output Short-Circuit Current Vour = 0.5 V, Vec = Max (Note 3) -30 j; -160 mA icc Supply Current (Typical) Voc= 5V, Ta= 25C, f = 25 MHz 120 mA (Note 4) Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. VO pin leakage is the worst case of lit, and lozt. (or lin and lozn). 3, Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Vour = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4, Measured with a 16-bit up/down counter loaded, enabled, and reset. pattem. This pattern is programmed in each PAL block and is capable of being MACH210-12/15/20 (Coml) 1-105zl AMD CAPACITANCE (Note 1) Parameter : Symbol Parameter Description Test Conditions Typ Unit Cin Input Capacitance Vin= 2.0 V Voc = 5.0 V, Ta = 25C, 6 pF Court Output Capacitance Vour=2.0V | f= 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter 12 715 -20 Symbol | Parameter Description Min | Max] Min | Max} Min} Max| Unit tep Input, 1/0, or Feedback to Combinatorial Output {Note 3) 12 15 20 ns Setup Time from Input, {/O, D-type 7 10 13 ns ts or Feedback to Clock T-type 8 14 14 ns tH Register Data Hold Time 0 0 ns tco Clock to Output (Note 3) 8 10 12 ns fw Clock LOW. 6 6 8 ns twx Width HIGH 6 6 8 ns D-type | 66.7 50 40 MHz Maximum External Feedback } 1/(ts + tco) Taype | 62.5 476 305 Miz fax Frequency D-type | 83.3 66.6 50 MHz (Note 1) Internal Feedback (fen) Type | 76.9 625 476 MHz No Feedback | 1/(twe + tu) 83.3 83.3 62.5 MHz ts. Setup Time from Input, {/O, or Feedback to Gate 7 10 13 ns tH Latch Data Hold Time 0 0 0 ns teo Gate to Output (Note 3) 10 1 12 ns few. Gate Width LOW 6 6 8 ns treo. Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 14 17 22 ns tsir Input Register Setup Time 2 2 2 ns thin Input Register Hold Time 2 2.5 3 ns tico . Input Register Clock to Combinatorial Output 15 18 23 ns tics Input Register Clock to Output Register Setup D-type 12 15 20 ns T-type | 13 16 21 ns twiel input Register LOW 6 6 8 ns twicu Clock Width HIGH 6 6 8 ns fMaxin Maximum Input Register Frequency | 1/(twict + twich) 83.3 83.3 62.5 MHz tsi. Input Latch Setup Time 2 2 2 ns tit Input Latch Hold Time 2 2.5 3 ns tico Input Latch Gate to Combinatorial Output 17 20 25 ns tigo. Input Latch Gate to Output Through Transparent Output Latch 19 22 27 ns tsu Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 9 12 15 ns tes Input Latch Gate to Output Latch Setup 13 16 21 ns 1-106 MACH210-12/15/20 (Coml)AMD cl SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter, -12 15 -20 Symbol | Parameter Description Min | Max| Min| Max] Min] Max] Unit twia. | Input Latch Gate Width LOW 6 6 8 ns ted Input, I/O, or Feedback to Output Through Transparent input and Output Latches 16 19 24 ns tar Asynchronous Reset to Registered or Latched Output 16 20 25 ns tanw Asynchronous Reset Width (Note 1) 12 15 20 ns tanR Asynchronous Reset Recovery Time (Note 1) 8 10 15 ns tap Asynchronous Preset to Registered or Latched Output 16 20 25 ns tapw Asynchronous Preset Width (Note 1) 12 15 20 ns tapR Asynchronous Preset Recovery Time (Note 1) 8 10 15 ns tea Input, I/O, or Feedback to Output Enable (Note 3) 12 15 20 ns ter Input, 1/0, or Feedback to Output Disable (Note 3) 12 15 20 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. MACH210-12/15/20 (Coml) 1-107at AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature ........... 65C to +150C Ambient Temperature . With Power Applied ............. 55C to +125C Supply Voltage with Respect to Ground ............. 0.5 V to +7.0 V DC Input Voltage ............ 0.5 V to Vec + 0.5 V DC Output or I/O Pin Voltage ........0.. enue ~0.5 V to Vec+ 0.5 V Static Discharge Voliage ...........00 eee 2001 V Latchup Current (Ta 40C 10 485C) 0... eee eee eee 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. INDUSTRIAL OPERATING RANGES Ambient Temperature (Ta) Operating in Free Air ............ 40C to +85C Supply Voltage (Vcc) with Respect to Ground .......... +4.5 V to +5.5 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified Parameter Symbo! Parameter Description Test Conditions Min | Typ | Max | Unit Vou Output HIGH Voltage lon =-3.2 mA, Vcc = Min 2.4 Vv Vin = Vin or Vit Vor Output LOW Voltage lo. = 16 MA, Voc = Min 05); V Vin = Vin or Vic Vin Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voltage for all Inputs (Note 1) Vi Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 1) fa Input HIGH Leakage Current Vin = 5.25 V, Voc = Max (Note 2) 10 pA fie Input LOW Leakage Current Vin =0 V, Vcc = Max (Note 2) -10 | pA lozH Off-State Output Leakage Vour = 5.25 V, Vec = Max 70 ] pA Current HIGH Vin = Vin or Viz (Note 2) loz. Off-State Output Leakage Vout = 0 V, Voc = Max -10 |] WA Current LOW Vin = Vin or Vit (Note 2) Isc Output Short-Circuit Current Vout = 0.5 V, Vec = Max (Note 3) ~30 -160| mA Ice Supply Current (Typical) Voc = 5 V, Ta = 25C, f = 25 MHz (Note 4) 120 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. V/O pin leakage is the worst case of In and lozt (or la and loz). Vour = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2. 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. 4 |. Measured with a 16-bit up/down counter pattern. This pattem is programmed in each PAL block and is capable of being loaded, enabled, and reset. 1-108 MACH210-14/18/24 (Ind)AMD cl CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit Cin Input Capacitance Vin = 2.0 V Vec = 5.0 V, Ta = 25C, 6 pF Cour Output Capacitance Vout =2.0V | f= 1 MHz 8 pF SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Parameter 214 718 24 Symbol | Parameter Description Min | Max} Min| Max|{ Min] Max! Unit tep Input, I/O, or Feedback to Combinatorial Output 14.5 18 241 ns (Note 3) ts Setup Time from Input, [/O, D-type 8.5 12 16 ns or Feedback to Clock T-type 10 135 17 ns ty Register Data Hold Time 0 0 0 ns {co Clock to Output (Note 3) 10 12 14.5] ns tw Clock LOW 25 75 10 os_| twx Width HIGH 75 7.5 10 ns External Feedback | 1/(ts + tco) D-type = 82 Miz Maximum T-type 50 38 30.5 MHz fax Frequency D-type | 61.5 53 38 MHz (Note 1) Internal Feedback (font) T-type 57 44 345 MHz No Feedback [tt + twu) 66.5 66.5 50 MHz ts Setup Time from Input, 1/O, or Feedback to Gate 8.5 12 16 ns tH. Latch Data Hold Time 0 0 0 ns tao Gate to Output (Note 3) 12 13.5 14.5] ns tow. Gate Width LOW 75 75 10 ns feo. input, I/O, or Feedback to Output Through 17 20.5 26.5| ns Transparent Input or Output Latch tsirn Input Register Setup Time 2.5 2.5 2.5 ns tur Input Register Hold Time 3 3.5 4 ns tico Input Register Clock to Combinatorial Output 18 22 28 ns ties Input Register Clock to Output Register Setup D-type | 14.5 18 24 ns T-type 16 19.5 25.5 ns twict Input Register LOW 7.5 7.5 10 ns twich Clock Width HIGH 7.5 7.5 10 ns fuaxin Maximum Input Register Frequency | 1/(twice + twicu) 66.5 66.5 50 MHz tsi. input Latch Setup Time 2.5 2.5 2.5 ns tot Input Latch Hold Time 3 3.5 4 ns tico Input Latch Gate to Combinatorial Output 20.5 24 30 ns ticot Input Latch Gate to Output Through Transparent 23 26.5 32.5| ns Output Latch tsu Setup Time from input, I/O, or Feedback Through 11 14.5 18 ns Transparent Input Latch to Output Latch Gate ties Input Latch Gate to Output Latch Setup 16 19.5 25.5 ns twiat Input Latch Gate Width LOW 7.5 7.5 10 ns tepu, Input, /O, or Feedback to Output Through Transparent 19.5 23 29 ns Input and Output Latches MACH210-14/18/24 (Ind) 1-109cl AMD SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued) Parameter -14 -18 -24 Symbol | Parameter Description Min | Max| Min} Max] Min] Max} Unit tar Asynchronous Reset to Registered or Latched Output 19.5 24 30 ns tarw Asynchronous Reset Width (Note 1) 14.5 18 24 ns tarr Asynchronous Reset Recovery Time (Note 1) 10 12 18 ns tap Asynchronous Preset to Registered or Latched Output 19.5 24 30 ns tapw Asynchronous Preset Width (Note 1) 14.5 18 24 ns tapr Asynchronous Preset Recovery Time (Note 1) 10 12 18 ns tea Input, /O, or Feedback to Output Enable (Note 3) 14.5 18 24 ns fer Input, 1/O, or Feedback to Output Disable (Note 3) 14.5 18 24 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2 See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 1-110 MACH210-14/18/24 (ind)ABSOLUTE MAXIMUM RATINGS Storage Temperature ........... ~65C to +150C Ambient Temperature with Power Applied ............. ~55C to +125C Supply Voltage with Respect to Ground ............. ~0.5 V to +7.0V DC Input Voltage ........... -0.5 V to Veco + 0.5 V DC Output or VO Pin Voltage ............ -0.5 Vto Veco + 0.5 V Static Discharge Voltage ................. 2001 V Latchup Current (Ta = 0C to +70C) ...... 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. AMD &A OPERATING RANGES Commercial (C) Devices Temperature (Ta) Operating in Free Air... kk ee cc aes 0C to +70C Supply Voltage (Vcc) with Respect to Ground ............ +4.75 V to +5.25 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit Vou Output HIGH Voltage lon = -3.2 mA, Voc = Min 2.4 Vv Vin = Vin or Vit Vo. Output LOW Voltage lo. = 16 mA, Veco = Min 0.5 v Vin = Vin or Vic View Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 v Voltage for all Inputs (Note 1) Vit Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for ail Inputs (Note 1) hw Input HIGH Leakage Current Vin = 5.25 V, Voc = Max (Note 2) 10 pA Ie Input LOW Leakage Current Vin = 0 V, Voc = Max (Note 2) -100 pA loz Off-State Output Leakage Vour = 5.25 V, Veco = Max 10 pA Current HIGH Vin = Vin or Vi (Note 2) loz. Off-State Qutput Leakage Vour = 0 V, Voc = Max ~100 pA Current LOW Vin = Vinor Vir (Note 2) Isc Output Short-Circuit Current Vour = 0.5 V, Vcc = Max (Note 3) -30 160 mA lec Supply Current (Typical) Vec= 5 V, Ta= 25C, f = 25 MHz 45 mA (Note 4) Notes: 1, These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. /O pin leakage is the worst case of lit, and loz. (or litt and lozt). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Vour = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. MACH210AQ-12 (Coml) 1-111z\ AMD CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit Cin Input Capacitance Vin= 2.0 V Veo = 5.0 V, Ta = 25C, 6 pF Cour Output Capacitance Vout=2.0V | f=1MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter 12 Symbol Parameter Description Min Max Unit teo Input, 1/0, or Feedback to Combinatorial Output 12 ns Setup Time from Input, 1/0, D-type 12 ns ts or Feedback to Clock T-type 13 ns ty Register Data Hold Time 0 ns tco Clock to Output 6 ns two Clock LOW. 6 ns twH Width HIGH 6 ns D-type 55.6 MHz Maximum External Feedback T-type 52.6 MHz fuax Frequency D-type 83.3 MHz (Note 1) intemal Feedback (font) Type 76.9 MHz No Feedback 83.3 MHz tet. Setup Time from Input, /O, or Feedback to Gate 12 ns tHE Latch Data Hold Time 0 ns tao Gate to Output 7 ns tewt Gate Width LOW 6 ns teoL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 14 ns tsin Input Register Setup Time 2 ns fHIR Input Register Hold Time 2.5 ns tico Input Register Clock to Combinatorial Output 17 ns tics Input Register Clock to Output Register Setup D-type 15 ns T-type 16 ns twice. Input Register . LOW 6 ns wich Clock Width HIGH 6 ns fuaxin Maximum Input Register Frequency 83.3 MHz tsiL {Input Latch Setup Time 2 ns tHIL Input Latch Hold Time 25 ns tico Input Latch Gate to Combinatorial Output 19 ns ticot Input Latch Gate to Output Through Transparent Output Latch 20 ns tsut Setup Time from Input, I/O, or Feedback Through Transparent input Latch to Output Latch Gate 13 ns tas Input Latch Gate to Output Latch Setup 16 ns 1-112 MACH210AQ-12 (Com'l)SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) AMD cl Parameter -12 Symbol Parameter Description Min Max Unit twiet Input Latch Gate Width LOW 6 ns teow Input, [/O, or Feedback to Output Through Transparent Input and Output Latches 18 ns tan Asynchronous Reset to Registered or Latched Output 24 ns tanw Asynchronous Reset Width (Note 1) 19 ns tan Asynchronous Reset Recovery Time (Note 1) 19 ns tap Asynchronous Preset to Registered or Latched Output 24 ns tapw Asynchronous Preset Width (Note 1) 19 ns tarr Asynchronous Preset Recovery Time (Note 1) 19 ns tea Input, 1/O, or Feedback to Output Enable 12 ns ter Input, 1/0, or Feedback to Output Disable 12 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. MACH210AQ-12 (Coml) 1-413cl AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature ........... ~65C to +150C Ambient Temperature with Power Applied ............. -55C to +125C Supply Voltage with Respect to Ground ............. -0.5 V to +7.0 V DC Input Voltage ........... 0.5 V to Veo + 0.5 V DC Output or VO Pin Voltage ..........--- -0.5 V to Veco + 0.5 V Static Discharge Voltage .........--.++-65 2001 V Latchup Current (Ta = 0C to +70C) ...... 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Temperature (Ta) Operating in Free Air... . 0... eee eee eee eee 0C to +70C Supply Voltage (Vcc) with Respect to Ground ............ +4.75 V to +5.25 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol! Parameter Description Test Conditions Min Typ Max Unit Vou Output HIGH Voltage lox =~3.2 mA, Voc = Min 2.4 Vv Vin = Vie or Vit Vo. Output LOW Voltage lo. = 16 MA, Vec = Min 0.5 v Vin = Vin or Vit Vie Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voltage for all Inputs (Note 1) Ve Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 1) lia Input HIGH Leakage Current Vin = 5.25 V, Veo = Max (Note 2) 10 pA he Input LOW Leakage Current Vin = 0 V, Voc = Max (Note 2) 100 pA loz Off-State Output Leakage Vout = 5.25 V, Voc = Max 10 pA Current HIGH Vin = Vinor Vir (Note 2) loz Off-State Output Leakage Vour = 0 V, Vec = Max ~100 pA Current LOW Vin = Vinor Vi. (Note 2) Isc Output Short-Circuit Current Vour = 0.5 V, Vcc = Max (Note 3) -30 -160 mA lec Supply Current (Typical) Vec= 5V, Ta= 25C, f = 25 MHz 45 mA (Note 4) Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. W/O pin leakage is the worst case of In, and loz (or liq and lozn). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second, Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4, Measured with a 16-bit up/down counter pattem. This pattem is programmed in each PAL block and is capable of being loaded, enabled, and reset. 1-114 MACH210AQ-15/20 (Com'l)pat AM CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit Cin Input Capacitance Vin= 2.0 V Voc = 5.0 V, Ta = 25C, 6 pF Cour Output Capacitance Vout=2.0V | f=1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter ' 15 -20 Symbol | Parameter Description Min] Max| Min] Max] Unit tep Input, I/O, or Feedback to Combinatorial Output (Note 3) 16 20 ns Setup Time from input, 1/O, D-type 13 17 ns ts or Feedback to Clock T-type 14 18 ns ty Register Data Hold Time 0 0 ns tco Clock to Output (Note 3) 7 8 ns twi Clock LOW 6 8 ns twr Width HIGH 6 8 ns D-type 50 40 MHz Maximum External Feedback | 1/(ts + tco) T-type 47.6 38.4 Miz fax Frequency D-type 58.8 45.4 MHz (Note 1) | Intemal Feedback (font) Type 555 434 Miz D-type 76.9 58.8 MHz No Feedback Its + th) T-type 714 555 Miz tet Setup Time from input, I/O, or Feedback to Gate 13 17 ns tH Latch Data Hold Time 0 0 ns fao Gate to Output (Note 3) 8 8 ns tew. Gate Width LOW 6 8 ns tept Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 17 22 ns tsin Input Register Setup Time 2 2 ns trim Input Register Hold Time 2.5 3 ns tico Input Register Clock to Combinatorial Output 18 23 ns tics Input Register Clock to Output Register Setup D-type 17 22 ns T-type 18 23 ns twier Input Register LOW 6 8 ns twick Clock Width HIGH 6 8 ns faxin Maximum Input Register Frequency | 1/(twic. + twicy) 83.3 62.5 MHz tsu, tnput Latch Setup Time 2 2 ns tH Input Latch Hold Time 2.5 3 ns tico Input Latch Gate to Combinatorial Output 20 25 ns tigot Input Latch Gate to Output Through Transparent Output Latch 22 27 ns tsut Setup Time from input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 15 19 ns tas Input Latch Gate to Output Latch Setup 18 23 ns MACH210AQ-15/20 (Coml) 1-115at AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter] -15 -20 Symbol | Parameter Description Min | Max| Min| Max| Unit fwiat Input Latch Gate Width LOW 6 8 ns tebe Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 19 24 ns tar Asynchronous Reset to Registered or Latched Output 25 30 ns tarw Asynchronous Reset Width (Note 1) : 20 25 ns tarr Asynchronous Reset Recovery Time (Note 1) 20 25 ns tap Asynchronous Preset to Registered or Latched Output 25 30 ns tapw Asynchronous Preset Width (Note 1) 20 25 ns tar Asynchronous Preset Recovery Time (Note 1) 20 25 ns tea Input, I/O, or Feedback to Output Enable (Note 3) 15 20 ns ter Input, I/O, or Feedback to Output Disable (Note 3) 15 20 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3, Parameters measured with 16 outputs switching. 1-116 MACH210AQ-15/20 (Coml)ABSOLUTE MAXIMUM RATINGS Storage Temperature ........... 65C to +150C Ambient Temperature (Ta) Ambient Temperature Operating in Free Air ............ With Power Applied ............. 55C to +125C Supply Voltage (Vcc) Supply Voltage with with Respect to Ground .......... Respect to Ground ............. 0.5 V to +7.0 V DC Input Voltage eee een eres ~0.5 V to Veo + 0.5 V tionality of the device is guaranteed. DC Output or /O Pin Voltage ..............0. 0.5 V to Voc + 0.5 V Static Discharge Voltage ................ 2001 V Latchup Current (Ta = 40C to +85C) 00. eee eee 200 mA AM INDUSTRIAL OPERATING RANGES Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. pel ~40C to +85C +4.5 V to +5.5 V Operating ranges define those limits between which the func- DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol! Parameter Description Test Conditions Min | Typ | Max j Unit Vou Output HIGH Voltage lon = ~3.2 mA, Voc = Min 2.4 Vv Vin = Vie or Vit Voi Output LOW Voltage lo. = 16 MA, Vec = Min 0.5 v Vin = Vin or Vit Vie Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 v Voltage for all Inputs (Note 1) Vir Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 1) lis Input HIGH Leakage Current Vin = 5.25 V, Voc = Max (Note 2) 10 | pA te Input LOW Leakage Current Vin = 0 V, Veco = Max (Note 2) -100/ pA fozH Off-State Output Leakage Vout = 5.25 V, Vcc = Max 10 7 WA Current HIGH Vin = Vin or Vit (Note 2) loz. Off-State Output Leakage Vout = 0 V, Veco = Max -100] pA Current LOW Vin = Vin or Vit (Note 2) Isc Output Short-Circuit Current Vour = 0.5 V, Vcc = Max (Note 3) ~30 ~160| mA lec Supply Current (Typical) Vcc = 5 V, Ta = 25C, f = 25 MHz (Note 4) 45 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. VO pin leakage is the worst case of ln and loz. (or hy and loz). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. Vour = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4 , Measured with a 16-bit up/down counter being loaded, enabled, and reset. pattem. This pattern is programmed in each PAL block and is capable of MACH210AQ-18/24 (Ind) 1-117zt AMD CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit Cin Input Capacitance Vin = 2.0V Voc = 5.0 V, Ta = 25C, 6 pF Cour Output Capacitance Vout =2.0V | f=1MHz 8 pF SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Parameter -18 24 Symbol | Parameter Description Min | Max] Min| Max} Unit tep Input, /O, or Feedback to Combinatorial Output 18 24 ns (Note 3) Setup Time from Input, I/O, D-type 16 20.5 ns ts or Feedback to Clock T-type 17 22 ns ty Register Data Hold Time 0 0 ns tco Clock to Output (Note 3) 8.5 10 ns two Clock LOW 7.5 10 ns_| twu Width HIGH 7.5 10 ns D-type 40 32 MHz Manirnum Extemal Feedback | 1/(ts + tco) T-type 38 305 MHz fuax Frequency D-type 47 36 MHz (Note 1) Intemal Feedback (fen) T-type mi 345 MHz No Feedback (ts + th) D-type sts 7 Mrz T-type 57 47 MHz tsi Setup Time from Input, I/O, or Feedback to Gate 16 20.5 ns te Latch Data Hold Time 0 0 ns teo Gate to Output (Note 3) 10 10 ns tawe Gate Width LOW 75 10 ns teo. Input, 1/O, or Feedback to Output Through 20.5 26.5| ns Transparent Input or Output Latch tsir input Register Setup Time 2.5 2.5 ns tun Input Register Hold Time 3.5 4 ns tico Input Register Clock to Combinatorial Output 22 28 ns tics Input Register Clock to Output Register Setup D-type 20.5 26.5 ns T-type 22 28 ns twict Input Register LOW, 7.5 10 ns twick Clock Width HIGH 7.5 10 ns fmaxin Maximum Input Register Frequency | 1A(twien + twich) 66.5 50 MHz tsi. Input Latch Setup Time 2.5 2.5 ns tui. Input Latch Hold Time 3.5 4 ns tico Input Latch Gate to Combinatorial Output 24 30 ns tico. Input Latch Gate to Output Through Transparent 26.5 32.5} ns Output Latch tsi. Setup Time from Input, I/O, or Feedback Through 18 23 ns Transparent Input Latch to Output Latch Gate tas Input Latch Gate to Output Latch Setup 22 28 ns twiet Input Latch Gate Width LOW 75 10 ns tebe Input, /O, or Feedback to Output Through Transparent 23 29 ns Input and Output Latches 1-118 MACH210AQ-18/24 (Ind)SWITCHING CHARACTERISTICS over IND (continued) USTRIAL operating ranges (Note 2) Parameter -18 -24 Symbol | Parameter Description Min | Max| Min] Max| Unit tar Asynchronous Reset to Registered or Latched Output 30 36 ns tanw Asynchronous Reset Width (Note 1) 24 30 ns tana Asynchronous Reset Recovery Time (Note 1) 24 30 ns tap Asynchronous Preset to Registered or Latched Output 30 36 ns tapw Asynchronous Preset Width (Note 1) 24 30 ns tapr Asynchronous Preset Recovery Time (Note 1) 24 30 ns tea Input, 1/O, or Feedback to Output Enable (Note 3) 18 24 ns ter Input, /O, or Feedback to Output Disable (Note 3) 18 24 ns Notes: 1. 2. 3. These parameters are not 100% tested, but are evaluated at initial ch where capacitance may be affected. See Switching Test Circuit, for test conditions. Parameters measured with 16 outputs switching. : aracterization and at any time the design is modified MACH210AQ-18/24 (Ind) 1-119ot AMD TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS Vec = 5.0 V, Ta = 25C lor (mA) 80 -T 60 -r 40 T 20 T L 1 { | | l 1 I t T t v T T T t 1.0 0.8 0.6 -0.4 -0.2 2 4 6 #0 + 40 7 -60 F -80 -~ Output, LOW 14128I-5 lo (mA) 25 T 3 -2 +t -25 4 -50 - 75 4 -100 150 + Output, HIGH 141281-6 It (mA) Input ; Vi(V) 141281-7 1-120 MACH210-7/10/12/15/20, Q-12/15/20AMD cl TYPICAL Icc CHARACTERISTICS Veo = 5 V, Ta = 25C MACH210A 150 - MACH210 125 - 100 + lec (mA) MACH210AQ 50 - 0 LJ t v I qT T v 1 T 7 T q T 1 T J T 1 v 1 0 10 20 30 40 50 60 70 80 90 100 Frequency (MHz) 141281-8 The selected typical pattern is a 16-bit up/down counter. This patter is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. MACH210-7/10/12/15/20, Q-12/15/20 1-121ct AMD TYPICAL THERMAL CHARACTERISTICS Measured at 25C ambient. These parameters are not tested. Parameter Typ Symboi Parameter Description TQFP PLCC Unit Qjc Thermal impedance, junction to case 11.3 15 CW ja Thermal impedance, junction to ambient 41 40 CiW Ojma Thermal impedance, junction to 200 Ifpm air 35 36 C/W ambient with air flow 400 ifpm air 33.7 33 oC 600 ffpm air 32.6 31 CAV 800 Ifpm air 32 29 CW Plastic 0j Considerations The data listed for plastic Ojc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the @jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, 9jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 1-122 MACH210-7/10/12/15/20, Q-12/15/20