DATASHEET
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE IDT1337
IDT™
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IDT1337 REV H 120208
General Description
The IDT1337 device is a low power serial real-t ime clock
(RTC) device with two prog rammable time-of-day alarms
and a programmable square-wave output. Address and
data are tr ansfer red serially through an I2C bus . The de vice
provides seconds, minutes, hours, day, date, month, and
year inform ation. The date at the end of the month is
automatically adjusted for months with fewer than 31 days,
including corrections for leap year. The clock operates in
either the 24-hour or 12-hour format with AM/PM indicator.
Applications
•Telecommunication (Routers, Switches, Servers)
•Handhelds (GPS, POS terminals, MP3 players)
•Set-Top Box, Digital Recording,
•Office (Fax/Printers, Copiers)
•Medical (Glucometer, Medicine Dispensers)
•Other (Thermostats, Vending Machines, Modems, Utility
Meters, Digital Photo Frame devices)
Features
•Real-Time Clock (R TC) counts seconds, minutes, hours,
day, date, month, and year with leap-year compensation
valid up to 2100
•Packaged in 8-pin MSOP, 8-pin SOIC, or 16-pin SOIC
(surface-mount package with an int egrated crystal)
•I2C Serial interface (Normal and Fast modes)
•Two time-of-day alarms
•Oscillator Stop Flag
•Progr ammable squar e-wa ve ou tput def aults to 32 kHz on
power-up
•Operating voltage of 1.8 to 5.5 V
•Industrial temperatu re range (-40 to +85°C)
Block Diagram
SCL
SDA
Crystal in sid e pa cka ge
for 16-pin SOIC ONLY
X1
X2
1 Hz/4.096 kHz/
8.192 kHz/32.768 kHz SQW/INTB
I2C
Interface
32.768 kHz
Oscillator and
Divider
Control
Logic
MUX/
Buffer
Clock,
Calendar
Counter
1 Byte
Control 7 Bytes
Buffer Alarm
Registers
INTA
VCC
GND
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Pin Assignment (8-pin MSOP/SOIC) Pin Assignment (16-pin SOIC)
Pin Descriptions
X1
INTA SCL
SQW/INTB
GND
VCC1
2
3
4
8
7
6
5SDA
X2 IDT1337
16
1
15
2
14
3
13
4
5
6
7
89
10
12
11
SCL
VCC
NC
NC
NC
NC
NC NC
NC
NC
NC
NC
SDA
GND
INTA
SQW/INTB
IDT1337C
Pin
Number Pin
Name Pin Description/Function
MSOP SOIC
1 — X1 Connections for standard 32.768 kHz quartz crystal. The internal oscillator circuitry is
designed for operati on with a crystal having a specified load capacitance (CL) of 7 pF. An
external 32.768 kHz oscillator can also drive the IDT1337. In this configuration, the X1 pin
is connected to the external oscillator signal and the X2 pin is left floating.
2— X2
314INTA
Interrupt output. When enable d, INTA is asserted low when the time/day/date matches the
values set in the alarm registers. This pin is an open-drain output and requires an external
pull-up resistor (10 k Ω typical).
4 15 GND Connect to ground. DC power is provided to the device on these pins.
5 16 SD A Serial data input/output . SD A is the input/output pin f or the I2C serial interface. The SD A pin
is an open-drain output and requires an external pull-up resistor ( 2 kΩ typical).
6 1 SCL Serial clock input. SCL is used to synchronize data movement on the serial interface. The
SCL pin is an open-drain output and requires an ex ternal pull-up resistor (2 k Ω typical).
7 2 SQW/INTB
Square-Wave/Interrupt output. Programmable square-wave or interrupt output signal. The
SQW/INT pin is an open-dr ain output and requires an external pull-up resistor (10 kΩ
typical). This pin can also function as an additional interrupt pin under certain conditions
(see page 6 for details).
8 3 VCC Primary power supply. DC power is applied to this pin.
— 4 - 13 NC No connect. These pins are unused and must be connected to ground.
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Typical Operating Circuit
Detailed Description
Communications to and from the IDT1337 occur serially
over an I2C bus. The IDT1337 operates as a slave device on
the serial bus. Access is obtained by implementing a START
condition and providing a device identification code,
followed by data. Subsequent registers can be accessed
sequentially until a ST O P condition is ex ecuted. Th e de vice
is fully accessible through the I2C interface whenever VCC
is between 5.5 V and 1.8 V. I2C operatio n is not guaranteed
when VCC is below 1.8 V. The IDT1337 maintains the time
and date when VCC is as low as 1.3 V.
The f ollowing sections discuss in detail the Oscillator bloc k,
Clock/Calendar Register Block and Serial I2C block.
Oscillator Block
Selection of the right crystal, correct load capacitance and
careful PCB layout ar e important for a stable crystal
oscillator. Due to the optimization for the lowest possible
current in the design f or these oscillators, losses caused by
parasitic currents can have a significant impact on the
ov erall oscillator perf ormance. Extra care needs to be taken
to maintain a certain quality and cleanliness of the PCB.
Crystal Selection
The key parameters when selecting a 32 kHz crystal to work
with IDT1337 RTC are:
•Recommended Load Capacitance
•Crystal Effective Series Resistance (ESR)
•Frequency Tolerance
Effective Load Capacitance
Please see diagram below for effective load capacitance
calculation. The effective load capacitance (CL) should
match the recommende d load capacita nce of the crystal in
order for the crystal to oscillate at its specified parallel
resonant frequency with 0ppm frequency error.
In the above figure, X1 and X2 are the crystal pins of our
device . Cin1 and Cin2 are the internal capacitors which
include the X1 and X2 pin capacitan ce. Ce x1 an d Ce x2 are
the external capacitors that are needed to tune the crystal
frequency. Ct1 and Ct2 are the PCB trace capacitances
between the crystal and the device pins. CS is the shunt
capacitance of the crystal (as specified in the crystal
manufacturer's datasheet or measured using a network
analyzer).
CPU
X1 X2 VCC
SQW/INTB
INTA
GND
SDA
SCL
CRYSTAL
IDT1337
VCC
2k
2k
VCC
VCC
10k 10k
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Note: IDT1337C SRI int egrates a stan da r d 32 .7 68 kHz
crystal in the package and contributes an additional
frequency er ro r of 10 p pm at no m i na l VCC (+ 3.3 V) and
TA=+25°C.
ESR (Effective Series Resistance)
Choose the crystal with lower ESR. A low ESR helps the
crystal to start up and stabilize to the correct output
frequency faster compared to high ESR cry sta ls.
Frequency Tolerance
The frequency tolerance for 32 KHz crystals should be
specified at nominal temperature (+25°C) on the crystal
manufacturer datasheet. The crystals used with IDT1337
typically have a frequency tolerance of +/-20ppm at +25°C.
Specifications for a typical 32 kHz crystal used with our
device are shown in the table below.
PCB Design Consideration
•Signal traces between IDT device pins and the crystal
must be kept as short as possible. This minimizes
parasitic capacitance and sensitivity to crosstalk and
EMI. Note that the trace capacitances play a role in the
effective crystal load capacitance calculation.
•Data lines and freque ntly switching signal lines should be
routed as far away from the crystal connections as
possible. Crosstalk from these signals may disturb the
oscillator signal.
•Reduce the parasitic capacitance between X1 and X2
signals by routing them as far apart as possible.
•The oscillation loop current flows between the crystal and
the load capacitors. This signal path (crystal to CL1 to
CL2 to crystal) should be kept as short as possibl e and
ideally be symmetric. The ground connections for both
capacitors should be as close together as possible.
Never route the ground connection between the
capacitors all around th e crystal, because this long
ground trace is sensitive to crosstalk and EMI.
•To reduce the radiation / coupling from oscillator circuit,
an isolated ground island on the GND layer could be
made. This g r ou nd isla nd can be co nne ct e d at one point
to the GND layer. This helps to keep noise generated by
the oscillator circuit locally on this separated island. The
ground connections for the load capacitors and the
oscillator should be connected to this island.
PCB Layout
PCB Assembly, Soldering and Cleaning
Board-assembly production process and assembly quality
can affect the performance of the 32 KHz oscillator.
Depending on the flux material used, the soldering process
can leave critical residues on the PCB surface. High
humidity and fast tempe rature cycles that cause humidity
condensation on the printed circuit board can create
process residuals. These process residuals cause the
insulation of the sensitive oscillator signal lines towards
each other and neighboring signals on the PCB to decrease.
High humidity can lead to moisture condensation on the
surface of the PCB and, together with process residuals ,
reduce the surf ace resistivity o f the board. Flux residuals on
the board can cause leakage current paths, especially in
humid environments. Thorough PCB cleaning is therefore
highly recommended in order to achieve maximum
performance by removing flux residuals from the board after
assembly. In general, reduction of losses in the oscillator
circuit leads to better safety margin and reliability.
Parameter Symbol Min Typ Max Units
Nominal Freq. fO32.768 kHz
Series Resistance ESR 50 kΩ
Load Capacitance CL7pF
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Address Map
Table 2 (Timekeeper Registers) shows the address map for the IDT1337 registers. During a multibyte access, when the
address pointer reaches the end of the register space (0Fh), it wraps around to location 00h. On an I2C START, STOP, or
address pointer incrementing to location 00h, the current time is transferred to a second set of regi sters. The time
inf ormation is read from these secondary registers , while the cloc k ma y continue to run. This eliminates the need to re-re ad
the registers in case of an update of the main registers during a read.
Table 1. Timekeeper Registers
Note: Unless otherwise specified, the state of the registers are not defined when power is first applied or when VCC falls below th e VCCT
min
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function Ra nge
00h 0 10 seconds Seconds Seconds 00 - 59
01h 0 10 minutes Minutes Minutes 00 - 59
02h 0 12/24 AM/PM 10 hour Hour Hours 1 - 12 +
AM/PM
00 - 23
10 hour
03h00000 Day Day 1 - 7
04h 0 0 10 date Date Date 01 - 31
05h Century 0 0 10 month Month Month/Century 01 - 12 +
Century
06h 10 year Year Year 00 - 99
07h A1M1 10 seconds Seconds Alar m 1
Seconds 00 - 59
08h A1M2 10 minutes Minutes Alarm 1
Minutes 00 - 59
09h A1M3 12/24 AM/PM 10 hour Hour Alarm 1 Hours 1 - 12 +
AM/PM
00 - 23
10 hour
0Ah A1M4 DY/DT 10 date Day, Alarm 1 Day 1 - 7
Date Alar m 1 Date 1 - 31
0Bh A2M2 10 minutes Minutes Alarm 2
Minutes 00 - 59
0Ch A2M3 12/24 AM/PM 10 hour Hour Alarm 2 Hours 1 - 12 +
AM/PM
00 - 23
10 hour
0Dh A2M4 DY/DT 10 date Day, Alarm 2 Day 1 - 7
Date Alar m 2 Date 1 - 31
0Eh EOSC 0 0 RS2 RS1 INTCN A2IE A1IE Control
0FhOSF00000A2FA1FStatus
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Clock and Calendar
The time and calendar information is obtained by reading
the appropriate register bytes. The RTC registers are
illustrated in Table 1. The time and calendar are set or
initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the
binary-coded decimal (BCD) f ormat.
The day-of-week register increments at midnight. Values
that correspond to the day of week are user-def ined but
must be sequential (i.e., if 1 equals Sunday, then 2 equals
Monda y, and so on). I llogical time and dat e entries result in
undefined operation.
When reading or writing the time and date registers,
secondary (user) buffers are used to prevent errors when
the internal registers update. When reading the time and
date registers, the user buffers are synchronized to the
internal registers on any start or stop and when the register
pointer rolls over to zero.
The countdown chain is reset whenever the seconds
register is written. Write transfers occur on the acknowledge
pulse from the device. To avoid rollover issues, once the
countdown chain is reset, the remaining time and date
register s must be written within 1 second. The 1Hz
square-wave output, if en able, transitions hig h 500ms after
the seconds data transf er, provided the oscillator is already
running.
The IDT1337 can be run in either 12-hour or 24-hour mode .
Bit 6 of the hours register is defined as the 12- or 24-hour
mode-select bit. When high, the 12-hour mode is selected.
In the 12-hour mode, bit 5 is the AM/PM bit with logic high
being PM. In the 24-hour mode, bit 5 is the second 10-hour
bit (20–23 hours). All hours values, including t he alarms,
must be reinitialized whenever the 12/24 -hour mode bit is
changed. The century bit (bit 7 of the month register) is
toggled when the years register overflows from 99–00.
Alarms
The IDT1337 conta ins two time of da y/date alarms. Alarm 1
can be set by writing to registers 07h to 0Ah. Alarm 2 can be
set by writing to registers 0Bh to 0Dh. The alarms can be
programmed (by t he INTCN bits of the Control Register) to
operate in two different modes—each alarm can drive its
own separate interrupt output or both alarms can drive a
common interrupt output. Bit 7 of each of the
time-of-day/date alarm regis te rs ar e m ask bits (Table 1).
When all of the mask bits for each alarm are logic 0, an
alarm only occurs when the values in the timekeeping
registers 00h– 06h match the values stored in the
time-of-day/date alarm registers. The alarms can also be
programmed to repeat every second, minute, hour, day, or
date. Table 2 (Alarm Mask Bits table) shows the possible
settings. Configurations not listed in the table result in
illogical operation
The D Y/DT bits (bit 6 of the alarm day/date registers) control
whether the alarm value stored in bits 0 to 5 of that register
reflects the day of the week or the date of the month. If
DY/DT is written to a logic 0, the alarm is the result of a
match with date of the month. If DY/DT is written to a logic
1, the alarm is the result of a match with day of the wee k.
When the RTC register values match alarm register
settings, the corresponding Alarm Flag (‘A1F’ or ‘A2F’) bit is
set to logic 1. If the corre sp o nd ing Alarm In te rrupt Enable
(‘A1IE’ or ‘A2IE’) is also set to logic 1, the alarm condition
activates one of the interrupt output (INTA or SQW/INTB)
signals. The match is tested on the once-per-second update
of the time and date registers.
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Table 2. Alarm Mask Bits
Special-Purpose Registers
The IDT1337 has two additional registers (control and status) that control the RTC, alarms, and square-wave output.
Control Register (0Eh)
Bit 7: Enable Oscillator (EOSC). This active-lo w bit when set to logic 0 starts the oscillator. When this bit is set to
a logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied.
Bits 4 and 3: Rate Sele ct (RS2 an d RS 1) . These bits control the frequency of the square-w ave output wh en the
square wave has been enabled. Table 3 sho ws the squar e-w av e f requencies t hat ca n be sele cted wit h the RS bits .
These bits are both set to logic 1 (32 kHz) when power is first applied.
Table 3. SQW/INT Output
DY/DT Alarm 1 Register Mask Bits (Bit 7) Alarm Rate
A1M4 A1M3 A1M2 A1M1
X1111Alarm once per second.
X1110Alarm when seconds match.
X1100Alarm when minutes and seconds match.
X1000Alarm when hours, minutes, and seconds match.
00000Alarm when date, hours, minutes, and seconds match.
10000Alarm when day, hours, minutes, and seconds match.
DY/DT Alarm 2 Register Mask Bits (Bit 7) Alarm Rate
A2M4 A2M3 A2M2
X 1 1 1 Alarm once per minute (00 seconds of every minute).
X 1 1 0 Alarm when minutes match.
X 1 0 0 Alarm when hours and minutes match.
0 0 0 0 Alarm when date, hours, and minutes match.
1 0 0 0 Alarm when day, hours, and minutes match.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EOSC 0 0 RS2 RS1 INTCN A2IE A1IE
INTCN RS2 RS1 SQW/INTB Output A2IE
000 1 Hz X
0 0 1 4.096 kHz X
0 1 0 8.192 kHz X
0 1 1 32.768 kHz X
1XX A2F 1
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Bit 2: Interrupt Contro l (INTCN). This bit controls the re lationship bet ween the t wo alarms and the inte rrupt output
pins. When the INTCN bit is set to logic 1, a ma tch be twee n th e tim ekeeping regis ter s an d th e ala rm 1 re gist er s
activate the INTA pin (provided that the alarm is enabled) and a match between the timekeeping registers and the
alarm 2 registers ac tivates the SQW/INTB pin (provided that the alarm is enabled). When the INTCN bit is set to
logic 0, a square wave is output on the SQW/INTB pin. This bit is set to logic 0 when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the
status register to assert INTA (when INTCN = 0) or to assert SQW/INTB (when INTCN = 1). When the A2IE bit is
set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (l ogic 0) when power is first
applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). Whe n set to logic 1, this bit p ermits the Alarm 1 Flag (A1F) bit in the status
register to assert INTA. When the A1IE bit is set to logic 0, the A1F bit does not initiate the INTA signal. The A1IE
bit is disabled (logic 0) when power is first applied.
Status Register (0Fh)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped
f or some period of time and may be used to judge the validit y of the clock and calendar dat a. This bit is is set to logic
1 anytime the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on VCC is insufficient to support oscillation.
3) The EOSC bit is turned off.
4) External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to a logic 0.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers.
This flag can be used to generate an interrupt on either INTA or SQW/INTB depending on the status of the INTCN
bit in the control registe r . If the INTCN bit is set to logic 0 and A2F is at l ogic 1 (and A2IE bit is also logic 1), the INTA
pin goes low. If the INTCN bit is set to logic 1 and A2F is logic 1 (and A2IE bit is also logic 1), the SQW/INTB pin
goes low. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1
leaves the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the Alarm 1 Flag bit indicates that the time matched the alarm 1 registers. If
the A1IE bit is also a logic 1, the INTA pin goes low. A1F is cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves the value unchanged .
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OSF00000A2FA1F
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I2C Serial Data Bus
The IDT1337 supports the I2C bus protocol. A device that
sends data onto the bus is defined as a transmitter and a
device receiving data as a receiv er . The device that controls
the message is calle d a ma st er. The devices that are
controlled by the master are referred to as slaves . A master
device that generates the serial clock (SCL), controls the
bus access, and generates the START and STOP conditions
must control the bus. The IDT 1337 operates as a slave on
the I2C bus . Within the b us specifications , a standar d mode
(100 kHz maximum clock rate) and a fast mode (400 kH z
maximum clock rate) are defined. The IDT1337 works in
both modes. Connections to the bus are ma de via the
open-dr ain I/O lines SDA and SCL.
The follo wing bus protocol has been defined (see the “Data
Transfer on I2C Serial Bus” figure):
•Data transfer may be initiated only when the bus is not
busy.
•During data transfer, the data line must remain stable
whene ver the cloc k line is HIGH. Changes in the data line
while the clock line is HIGH are interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line,
from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop data transfer: A change in the state of the data line,
from LOW to HIGH, while the clock line is HIGH, defines the
STOP condition.
Data valid: The state of the data line represents valid data
when, after a START condition, the data line is stab le for the
duration of the HIGH period of the clock signal. The data on
the line must be changed during the LOW period of the clock
signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of data
bytes transf erred between START and STOP conditions are
not limited, and ar e de te rmin ed by the master device. The
information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Acknowledge: Each receiving de vice, when addressed , is
obliged to generate an acknowledge after the reception of
each b yte . The master device must generate a n e xtr a clock
pulse that is associated with this ackno wle dge bit.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the
ackn owledge related cloc k pulse. Of course, setup and ho ld
times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge
bit on the last byte that has been clock ed out of the slav e. In
this case, the sla ve m ust leav e the data line HIGH to enable
the master to generate the ST OP condition.
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Data Transfer on I2C Serial Bus
Depending upon the state of the R/W bit, two types of data
transfer are possible:
1) Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received byte.
Data is transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a master
receiver. The fir st byte (the slav e address) is tran smitted by
the master. The slave then returns an acknowledge bit,
followed by the slave transmitti ng a number of data bytes.
The master returns an acknowledge bit after all received
bytes other than the last byte . At the end of the last receiv ed
byte, a “not acknowledge” is returned. The master device
generates all of the serial clock pulses and the START and
STOP conditions. A transf er is ended with a STOP condition
or with a repeated START condition. Since a repeated
START condition is also th e beginning of the next serial
transf er , the b us is not released. Data is transf erred with the
most significant bit (MSB) first.
The IDT1337 can operate in the following two mo des:
1) Slave Receiver Mode (Write Mode): Serial data and
clock a re received throug h SDA an d SCL. After each b yte is
received an acknowledge bit is transmitted. START and
STOP conditions are recog nized as the beginning and end
of a serial transfer. Address recognition is performed by
hardwa re after re ception of the sla ve address and direction
bit (see the “Dat a Write–Slave Receiv er Mode” figure ). The
slav e address byte is the first byte received after the STAR T
condition is generated by the master. The slave address
byte contains the 7-bit IDT13 37 address, which is 11 01000,
followed by the direction bit (R/W), which is 0 for a write.
After receiving and decoding the slave address byte th e
device outputs an acknowledge on the SDA line. After the
IDT1337 acknowledges the slave address + write bit, the
master transmits a register address to the IDT1337. This
sets the regist er pointer on the IDT1337. The master may
then transmit zero or more bytes of data, with the IDT1337
acknowledging each byte received. The address pointer
increments after each data byte is transferred. The master
generates a STOP condition to terminate the data write.
2) Slave Transmitter Mode (Read Mode): The firs t by te is
received and handled as in the slave rece iver mode.
How ever, in this mode, the direction bit indicates that the
transfer direction is reversed. Serial data is transmitted on
SDA by the IDT13 37 while the serial clock is input on SCL.
START and STOP conditions are re cognized as the
beginning and end of a serial transfer (see the “Data
Read–Slave Transmitter Mode” figure). The slave address
byt e is the first byte received after the START condition is
generated by the master. The slave address byte contains
the 7-bit IDT1337 address, which is 1101000, followed by
the direction bit (R/W), which is 1 f or a read. After receiving
and decoding the slave address byte the slave outputs an
ackn o wle dge on th e SDA line. The IDT133 7 t hen b egin s to
transmit data starting with the register address pointed to by
the register pointer. If the register pointer is not written to
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bef ore the initiation of a read mode the first address that is
read is the last one stored in the register pointer. The IDT1337 must rece ive a “not acknowledge” to end a read.
Data Write – Slave Receiver Mode
Data Read (from current Pointer location) – Slave Transmitter Mode
Data Read (Write Pointer, then Read) – Slave Receive and Transmit
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT1337. These ratings, which are
standard v alues for IDT commercially rated parts, are stress ratings only. Functional operation of the de vice at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range .
Recommended DC Operating C onditions
DC Electrical Characteristics
Unless stated otherwise, VCC = 1.8 V to 5.5 V, Ambient Temperature -40 to +85°C, Note 1
Item Rating
Voltage Range (on any pin relative to ground) -0.3 V to +6.0 V
Storage Tempera ture -55 to +125°C
Soldering Temperature 260°C
Ambient Operating Temperature -40 to +85°C
Parameter Symbol Conditions Min. Typ. Max. Units
VCC Supply Voltage VCC Full operation 1.8 3.3 5.5 V
VCCT Timekeeping 1.3 1.8 V
Ambient Operating Temperature TA-40 +85 °C
Logic 1 VIH SCL, SDA 0 .7VCC VCC + 0.3 V
INTA, SQW/INTB 5.5
Logic 0 VIL -0.3 +0.3VCC V
Parameter Symbol Conditions Min. Typ. Max. Units
Input Leakage ILI Note 2 -1 +1 µA
I/O Leakage ILO Note 3 -1 +1 µA
Logic 0 Output
VOL = 0.4 V IOL Note 3 3 mA
Active Supply Current ICCA Note 4 150 µA
Standby Current ICCS Notes 5, 6 1.5 µ A
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE RTC
IDT™
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 13
IDT1337 REV H 120208
DC Electrical Characteristics
Unless stated otherwise, VCC = 1.3 V to 1.8 V, Ambient Temperature -40 to +85°C, Note 1
AC Electrical Characteristics
Unless stated otherwise, VCC = 1.8 V to 5.5 V, Ambient Temperature -40 to +85°C, Note 1
Parameter Symbol Conditions Min. Typ. Max. Units
Timekeeper Current (Oscillator
Enabled) ICCTOSC Notes 5, 7, 8, 9 425 600 nA
Data-Retention Current (Oscillator
Disabled) ICCTDDR Notes 5, 9 100 nA
Parameter Symbol Conditions Min. Typ. Max. Units
SCL Clock Frequency fSCL Fast Mode 100 400 kHz
Standard Mode 0 100
Bus Free Time Between a STOP and
START Condition tBUF Fast Mode 1.3 µs
Standard Mode 4.7
Hold Time (Repeated) STAR T
Condition, No te 10 tHD:STA Fast Mode 0.6 µs
Standard Mode 4.0
Low Period of SCL Clock tLOW Fast Mode 1.3 µs
Standard Mode 4.7
High Period of SCL Clock tHIGH Fast Mode 0.6 µs
Standard Mode 4.0
Setup Time for a Repeated START
Condition tSU:STA Fast Mode 0.6 µ s
Standard Mode 4.7
Data Hold Time, Notes 11, 12 tHD:DAT Fast Mode 0 0.9 µs
Standard Mode 0
Data Setup Time, Note 13 tSU:DAT Fast Mode 100 ns
Standard Mode 250
Rise Time of Both SDA and SCL
Signals, Note 14 tRFast Mode 20 + 0.1CB300 ns
Standard Mode 20 + 0.1CB1000
F all Time of Both SDA and SCL Signals,
Note 14 tFFast Mode 20 + 0.1CB300 ns
Standard Mode 20 + 0.1CB300
Setup Time for STOP Condition tSU:STO Fast Mode 0.6 µ s
Standard Mode 4.0
Capacitive Load for Each Bus Line,
Note 14 CB400 pF
I/O Capacitance (SDA, SCL) CI/O Note 15 10 pF
32.768 kHz Clock Accuracy with
External Crystal TA=25°C
VCC=3.3 V ±10 ppm
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE RTC
IDT™
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 14
IDT1337 REV H 120208
Note 1: Limits at -40°C are guarantee d by design and are not production tested.
Note 2: SCL only.
Note 3: SDA, INTA, and SQW/INTB.
Note 4: ICCA—SCL clocking at maxim um frequency = 400 kHz, VIL = 0.0V, VIH = VCC.
Note 5: Specified with the I2C bus inactive, VIL = 0.0V, VIH = VCC.
Note 6: SQW enabled.
Note 7: Specified with the SQW function disabled by setting INTCN = 1.
Note 8: Using recommended crystal on X1 and X2.
Note 9: The device is fully accessib le when 1.8 < VCC < 5.5 V. Time and date are maintained when 1.3 V < VCC <
1.8 V.
Note 10: After this period, the firs t clock pulse is generated.
Note 11: A de vice m ust internally provide a hold tim e of at least 300 n s f or the SDA signal (ref erre d to the VIHMIN of
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 12: The maximum t HD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL
signal.
Note 13: A f ast-mode de vice can be used in a standard-mo de system, b ut the requirement tSU:DAT > to 250 ns m ust
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) +
tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is released.
Note 14: CB—total capacita nce of one bus line in pF.
Note 15: Guaranteed by design. Not production tested.
32.768 kHz Clock Accuracy with
Internal Crystal TA=25°C
VCC=3.3 V
(crystal accuracy
±20ppm)
±30 ppm
Parameter Symbol Conditions Min. Typ. Max. Units
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE RTC
IDT™
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 15
IDT1337 REV H 120208
Timing Diagram
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE RTC
IDT™
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 16
IDT1337 REV H 120208
Typical Operating Characteristics
Icc vs Vcc
200
300
400
500
600
700
800
900
1.3 2.3 3.3 4.3 5.3
Vcc (V)
Icc (nA)
INTCN=1
INTCN=0
IccA vs Vcc
0
2
4
6
8
10
1.3 2.3 3.3 4.3 5.3
Vcc (V)
Icc (uA)
ICCA
Icc vs Temper atur e
200
300
400
500
600
700
800
-40-20 0 20406080
Temperature (C)
Icc (nA)
INTCN=1
INTCN=0
Oscillator Frequency vs Vcc
(as measured on one IDT1337C sample)
32768.3
32768.32
32768.34
32768.36
32768.38
32768.4
1.3 2.3 3.3 4.3 5.3
Vcc(V)
Frequency (Hz)
Freq
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE RTC
IDT™
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 17
IDT1337 REV H 120208
Thermal Characteristics for 8SOIC
Thermal Characteristics for 8MSOP
Thermal Characteristics for 16SOIC
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient θJA Still air 150 °C/W
θJA 1 m/s air flow 140 °C/W
θJA 3 m/s air flow 120 °C/W
Thermal Resistance Junct ion to Case θJC 40 °C/W
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient θJA Still air 95 °C/W
Thermal Resistance Junction to Case θJC 48 °C/W
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient θJA Still air 120 °C/W
θJA 1 m/s air flow 115 °C/W
θJA 3 m/s air flow 105 °C/W
Thermal Resistance J unction to Case θJC 58 °C/W
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE RTC
IDT™
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 18
IDT1337 REV H 120208
Marking Diagram (8 MSOP)
Marking Diagram (16 SOIC)
Marking Diagram (8 SOIC)
Notes:
1. # = product stepping.
2. $ = assembler code.
3. ** = sequential code number for traceability.
4. YYWW is the last two digits of the year and week that the part was assembled.
5. “G” denotes RoHS compliant package.
6. “I” denotes ind us trial grade.
7. Bottom marking: country of origin if not USA.
37GI
YWW$
18
916
IDT
1337CSRI
#YYWW**$
IDT1337
DCGI
#YYWW$
14
58
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE RTC
IDT™
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 19
IDT1337 REV H 120208
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
INDEX
AREA
1 2
8
D
E
SEATING
PLANE
A1
A
e
- C -
B
.10 (.004) C
C
L
H
h x 45
Millimeters Inches
Symbol Min Max Min Max
A 1.35 1.75 .0532 .0688
A1 0.10 0.25 .0040 .0098
B 0.330.51.013.020
C 0.19 0.25 .0075 .0098
D 4.80 5.00 .1890 .1968
E 3.80 4.00 .1497 .1574
e 1.27 BASIC 0.050 BASIC
H 5.80 6.20 .2284 .2440
h 0.250.50.010.020
L 0.401.27.016.050
α0°8°0°8°
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE RTC
IDT™
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 20
IDT1337 REV H 120208
Package Outline and Package Dimensions (8-pin MSOP, 3.00 mm Body)
Package dimensions are kept current with JEDEC Publication No. 95
INDEX
AREA
1 2
8
D
E1 E
SEATING
PLANE
A
1
A
A
2
e
- C -
b
aaa C
c
L
*For reference only. Controlling dimensions in mm.
Millimeters Inches*
Symbol Min Max Min Max
A--1.10--0.043
A1 0 0.15 0 0.006
A2 0.79 0.97 0.031 0.038
b 0.22 0.38 0.008 0.015
C 0.08 0.23 0.003 0.009
D 3.00 BASIC 0.118 BASIC
E 4.90 BASIC 0.193 BASIC
E1 3.00 BASIC 0.118 BASIC
e 0.65 Basic 0.0256 Basic
L 0.40 0.80 0.016 0.032
α0°8°0°8°
aaa - 0.10 - 0.004
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE RTC
IDT™
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 21
IDT1337 REV H 120208
Package Outline and Package Dimensions (16-pin SOIC, 300 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
The 1337C packages are RoHS compliant. Packages without the integrated crystal are Pb-free; packages that include the
integrated crystal (as designated with a “C” before the two-letter package code) may include lead that is exempt under RoHS
requirements. The lead finish is JESD9 1 category e3.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or f or the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additi onal processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
Part / Order Number Marking Shipping Packaging Package Temperature
1337DVGI see page 18 Tubes 8-pin MSOP -40 to +85° C
1337DVGI8 Tape and Reel 8-pin MSOP -40 to +85° C
1337CSRI Tubes 16-pin SOIC -40 to +85° C
1337CSRI8 Tape and Reel 16-pin SOIC -40 to +85° C
1337DCGI Tubes 8-pin SOIC -40 to +85° C
1337DCGI8 Tape and Reel 8-pin SOIC -40 to +85° C
INDEX
AREA
1 2
16
D
E1 E
SEATING
PLANE
A
1
A
A
2
e
- C -
b
aaa C
c
L
*For reference only. Controlling dimensions in mm.
Millimeters Inches*
Symbol Min Max Min Max
A -- 2.65 -- 0.104
A1 0.10 -- 0.0040 --
A2 2.05 2.55 0.081 0.100
b 0.33 0.51 0.013 0.020
c 0.18 0.32 0.007 0.013
D 10.10 10.50 0.397 0.413
E 10.00 10.65 0.394 0.419
E1 7.40 7.60 0.291 0.299
e 1.27 Basic 0.050 Basic
L 0.40 1.27 0.016 0.050
α0°8°0°8°
aaa - 0.10 - 0.004
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE RTC
IDT™
REAL-TIME CLOCK WITH I
2
C SERIAL INTERFACE 22
IDT1337 REV H 120208
Revision History
Rev. Originator Date Description of Change
A S. Sharma 06/26/07 New device. Preliminary release.
B J. Sarma 10/31/07 Added 8-pin SOIC package and ordering info.
C J. Sarma 01/16/08 Updates to Pin Descriptions, load capacitance, Timekeeper Registers table, and
Recommended DC Operating Conditions table.
D J. Sarma 03/03/08 Added top-side device markings.
E J. Sarma 03/18/08 Revised top-side markings.
F J . Sarma 03/28/08 Added new note to P art Ordering information pertaining to RoHS compliance and Pb-free
devices.
G J. Sarma 05/19/08 Changed the part number for the RoHS compliant 16pin SOIC package with Xtals for
IDT1337CSOGI to IDT133 7CSRI
H J. Sarma 12/02/08 Updated Block diagram, Pin descriptions, Typical Operating Circuit diagram, Detailed
Description section, Typical Operating Characteristics graphs.
© 2006 Integrated Dev ice Tech nology, Inc. All righ ts reserved. Product spec ifications subject to c hange without notice. IDT an d the IDT logo are tra demarks of Integrated Devi ce
Tec hnology, Inc. Accelerated Thinking is a service mark of In tegrated Device Technology, Inc. All other brands, product names a nd marks a re or ma y be tr ademarks or regist ered
trademarks used to identify products or services of their respective owners.
Printed in USA
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
www.idt.com/go/clockhelp
Innovate with IDT and accelerate your future networks. Contact:
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IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE RTC
