Rev. 4202B–SCR–07/03
1
Features
•80C51 Core :
– 6 Clocks per Instruction
– Speed up to 16 MHz
•768 Bytes RAM
•AT83C5122: 32 Kbytes ROM
•AT83C5123: 30 Kbytes ROM
•AT85C5122: 32 Kbytes Code RAM and 32 Kbytes ROM
•AT89C5122 : 32 Kbytes Flash
•AT85EC5122, AT83EC5123, AT83EC5122: Additional 512 Bytes EEPROM (AT24C04)
•Multi-protocol Smart Card Interface
–Certified According to ISO7816, EMV2000, GIE-CB and WHQM Standards
–Asynchronous Protocols T = 0 and T = 1, with Direct and Inverse Modes
–Step-up/Down Converter with Programmable Voltage Output: 5V and 3V (60 mA),
1.8V (20 mA)
–4 kV ESD Protection (MIL/STD 833 Class 3)
•Alternate Card Support with CLK, IO and RST
•USB Module with 7 Endpoints Programmable with In or Out Directions and with ISO,
Bulk or Interrupt Transfers
•UART with Integrated Baud Rate Generator (BRG)
•8 MHz On-chip Oscillator Analog PLL for 96 MHz Synthesis, Possible 48 MHz Clock
Input
•Two 16-bit Timer/Counters: T0 and T1
•Hardware Watchdog and Power-fail Detector (PFD)
•Idle and Power-down Modes
•Self Powered USB
•Low Power
–30 mA Maxi mum Operating Current (at 32 MHz X1)
–100 µA Ma ximu m Power-down Current at 5.4V (without Smart Card and USB)
•Voltage Range: 3.6 to 5.5V
•For AT8xC5122 version:
–Keyboard Interrupt Interface on Port 5 (8 Bits)
–Five 8-bit I/O Ports, One 6-bit
–SPI Interface (Master Slave)
–Packages: VQFP64, PLCC28
–Seven LED Outputs with Programmable Current Sources: 2-4-10 mA
•For AT8xC5123 version:
–Four LED Outputs with Programmable Current Sources: 2-4-10 mA
–Two 8-bit I/O Ports, One 6-bit I/O port, One I/O bit (on LQP32 package)
–Packages: LQFP32, PLCC28
C51
Microcontroller
with USB and
Smart Card
Reader
Interfaces
AT83C5122
AT83EC5122
AT85C5122
AT85EC5122
AT89C5122
AT83C5123
AT83EC5123
Preliminary
2
AT8xC5122/23 4202B–SCR–07/03
Description AT8xC5122 is a hi gh-performan ce CMOS der ivati ve of th e 80 C51 8-bit micr oc ontrol le rs
optimized for USB keyboard with smart card reader applications.
AT8xC5122 reta ins the fea t ures of th e A tme l 80C5 1 with 32 K bytes RO M c apa city, 768
bytes of internal RAM, a 4-level interrupt system, two 16-bit timer/counters (T0/T1), a full
duplex enhanced UART (EUART) with baud rate generator (BRG) and an on-chip
oscillator.
In addi tion, AT 8xC5122 h as a US B 2.0 f ull-speed functi on contro ller with seven E nd-
points, a multi-protocol smart card interface, a dual data pointer, seven programmable
LED current sources (2-4-10 mA) and a hardware watchdog.
AT8xC5122 Flash RAM version and AT8xC5122 Code RAM version with 32 Kbytes
memory can b e loaded by In-S ystem Programm ing (ISP) softwa re resi ding in th e on-
chip ROM from USB or UART.
AT8xC5122 have 2 software-selectable modes of reduced activity for further reduction
in power consumption.
AT8xC 5123 is a low pi n count of the A T8xC5122. This v ersion d oesn’t have the k ey-
board and the SPI interfaces. The PLCC28 packages for AT8xC5122 and AT8xC5123
have the same pinout. The AT8xC5123 is also proposed in a VQFP32 package.
AT8xC5 122 and AT8 xC5123 are pr oposed wit h a 512 bytes EEPROM (AT24C04) and
respectively named AT8xEC5122 and AT8xEC5123.
3
AT8xC5122/23
4202B–SCR–07/03
AT8xC5122 Block Diagram
AT8xC5123 Block Diagram
Time r 0 INT
RAM
256 x 8
T0
T1
RxD
TxD
XTAL2
XTAL1
EUART
CPU
Time r 1
INT1
Ctrl
INT0
C51
CORE
P1
IB-bus
ROM*
Xtal
Osc XRAM
512
x 8
SCIB
CC8
CRST
CPRES
CIO
CC4
CCLK
CVCC
8
LI
External
Memory
32K x8
SCK
LED
LED0-6
Out
PLL
(1)
Watchdog
CVSS
P2
P0
EA
PSEN
ALE
DC/DC
Converter
Level
Shifters
POR
PFD
USB
D+
D-
I/Os
P3
8
I/Os
P4
6
I/Os
P5
8
I/Os
and Ports
KB
CIO1
CCLK1
CRST1
P5
Alternate
card
SPI
VREF
MISO
MOSI
SS
PLLF
AVCC
AVSS
VSS
VCC
BRG
RST
Parallel I/O Por ts DVCC
CRAM*
32K x8 Flash*
32K x8
* see versions
Time r 0 INT
RAM
256 x 8
T0
T1
RxD
TxD
XTAL2
XTAL1
EUART
CPU
Time r 1
INT1
Ctrl
INT0
C51
CORE
P1
IB-bus
ROM
Xtal
Osc XRAM
512
x 8
SCIB
CC8
CRST
CPRES
CIO
CC4
CCLK
CVCC
8
LI
30K x8
LED
LED0-3
Out
PLL
Watchdog
CVSS
DC/DC
Converter
Level
Shifters
POR
PFD
USB
D+
D-
I/Os
P3
8
I/Os
P4
2
I/Os
P5
CIO1
CCLK1
CRST1
Alternate
card
VREF
PLLF
AVCC
AVSS
VSS
VCC
BRG
RST
Parallel I/O Por ts DVCC
1
I/Os
4
AT8xC5122/23 4202B–SCR–07/03
Pin Description
Figure 1. VQFP64 Pinout (only for AT8xC5122)
Figure 2. PLCC28 Pinout
62 61 60 59 58 63
57
56 55 54 53
P0.1/AD1
P0.3/AD3
P0.5/AD5
P0.7/AD7 D+
P4.1/MOSI
P4.0/MISO
P4.2/SCK
P4.5/LED6
P3.1/TxD
P4.3/LED4
P4.4/LED5
P3.6/WR/LED2
D-
RST
XTAL1
XTAT2 P2.5/A13
P2.4/A12
P2.2/A10
P2.1/A9
P2.0/A8
P1.5/CRST
P1.4/CCLK
LI
P2.3/A11
2
3
4
5
6
7
8
9
10
11
48
47
46
45
44
43
42
41
40
39
38
VQFP64
64 52
12
13 36
37
VCC
VSS
P5.0/KB0
EA
P3.7/RD/LED3
51 50
AVSS
49
AVCC
P3.3/INT1
35
33
34
P3.4/T0/LED1
P3.5/T1/CRST1
CVCC
14
15
16
CVSS
31 3 2
P0.0/AD0
P1.2/CPRES
P0.2/AD2
P0.4/AD4
P0.6/AD6
P1.6/SS
P2.7/A15
P2.6/A14
P1.7/CCLK1
P5.1/KB1
P5.2/KB2
P5.3/KB3
P5.4/KB4
P5.5/KB5
P5.6/KB6
P5.7/KB7
P3.2/INT0/LED0/CIO1
VREF
P1.3/CC4
PLLF
ALE
PSEN
DVCC
P1.1/CC8
P1.0/CIO
P3.0/RxD
1
30 29 28 27 26 25 24 23 22 21 20 19 18 17
P1.0/CIO
PLCC28
P3.1/TxD
P1.4/CCLK
VSS
P1.3/CC4
DVCC
P1.1/CC8
XTAL1
XTAT2
LI
VCC
P3.7/LED3
CVCC
CVSS
P3.6/LED2
RST
P1.5/CRST P3.3/INT1
P1.2/CPRES
D-
D+
AVCC
AVSS
VREF
PLLF
P3.2/INT0/LED0
P3.4/T0/LED1
P3.0/RxD
1234282726
5
6
7
8
9
10
11
25
24
23
22
21
20
19
15141312 1617 18
5
AT8xC5122/23
4202B–SCR–07/03
Figure 3. LQFP32 Pinout (only for AT83C5123)
Figure 4. PLCC68 Pinout (Engineering package only for AT85C5122, check availability
with ATMEL sales office)
P1.0/CIO
LQFP32
P3.1/TxD
P1.4/CCLK
P5.0
P1.3/CC4
DVCC
P1.1/CC8
XTAL1
XTAT2
LI
VCC
P3.7/LED3
CVCC
CVSS
P3.6/LED2
P1.5/CRST
P3.3/INT1
P1.2/CPRES
D-
D+
AVCC
AVSS
PLLF
P3.2/INT0/LED0/CIO1
P3.4/LED1/T0
P3.0/RxD
28 27 26
1
2
3
4
5
6
7
24
23
22
21
20
19
18
1211109131415
VSS 816
RST
17
P1.6
P3.5/T1/CRST1
P1.7/CCLK1
VREF
25
29
30
31
32
62 61 60 59 58 63 57 56 55 54 53
P0.1/AD1
P0.3/AD3
P0.5/AD5
P0.7/AD7
D+
P4.1/MOSI
P4.0/MISO
P4.2/SCK
P4.5
P1.1/CC8
P4.3
P4.4
P3.6/WR
D-
RST
XTAL2
XTAT1
P2.5/A13
P2.4/A12
P2.2/A10
P2.1/A9
P2.0/A8
P3.1/TxD
P1.4/CCLK
LI
P2.3/A11
1
2
3
4
5
6
7
8
9
10
11
48
47
46
45
44
43
42
41
40
39
38
PLCC68
64 52
12
13 36
37
VCC
VSS
P5.0
EA
P3.7/RD
51 50
AVSS
49
AVCC
P3.3/INT1
35
33
34
P3.4/T0
P3.5/T1/CRST1
CVCC
14
CVSS
P1.0/CIO
32
P0.0/AD0
P3.0/RxD
P0.2/AD2
P0.4/AD4
P0.6/AD6
P1.6/SS
P2.7/A15
P2.6/A14
P1.7/CCLK1
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P3.2/INT0/CIO1
VREF
P1.3/CC4
PLLF
ALE
PSEN
DVCC
P1.2/CPRES
P1.5/CRST
N/A
N/A
168 67 66 65 64 63 62 6123456789
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
10
11
12
13
14
15
16
17
18
19
20
21
22
24
25
26 62 61 60 59 58 63 57 56 55 54 53
64 52 51 50 49
35 36 37 38 39 40 41 42 433433323130292827
23
NC
NC
6
AT8xC5122/23 4202B–SCR–07/03
Signals All the signals are detailed in Table 1:
Table 1. Pinout Description
Port
VQFP64
LQFP32
PLCC68
PLCC28
Internal
Power
Supply ESD I/O Reset
Level Alt Reset
Config Conf 1 Conf 2 Conf 3 Led
P0.0 30 - 41 - VCC 2KV I/O Float AD0 P0 KB_OUT Push-pull
P0.1 29 - 40 - VCC 2KV I/O Float AD1 P0 KB_OUT Push-pull
P0.2 28 - 39 - VCC 2KV I/O Float AD2 P0 KB_OUT Push-pull
P0.3 27 - 38 - VCC 2KV I/O Float AD3 P0 KB_OUT Push-pull
P0.4 25 - 36 - VCC 2KV I/O Float AD4 P0 KB_OUT Push-pull
P0.5 24 - 35 - VCC 2KV I/O Float AD5 P0 KB_OUT Push-pull
P0.6 23 - 34 - VCC 2KV I/O Float AD6 P0 KB_OUT Push-pull
P0.7 22 - 33 - VCC 2KV I/O Float AD7 P0 KB_OUT Push-pull
P1.0 64 32 9 4 CVCC 4KV I/O 0 CIO Port51 CVCC inactive at reset
P1.1 3 3 12 7 CVCC 4KV I/O 0 CC8 Port51 CVCC inactive at reset
P1.2 2 2 11 6 VCC 2KV I/O 1 CPRES Port51 Weak & medium pull-up can be
disconnected
P1.3 9 5 18 9 CVCC 4KV I/O 0 CC4 Port51 CVCC inactive at reset
P1.4 12 6 21 10 CVCC 4KV O 0 CCLK Push-pull CVCC inactive at reset
P1.5 6 4 15 8 CVC C 4KV O 0 CRST Push-pull CVCC inactive at reset
P1.6 47 23 58 - VCC 2KV I/O 1 SS Port51
P1.7 62 31 7 - VCC 2KV I/O 1 CCLK1 Port51
P2.0 58 - 3 - VCC 2KV I/O 1 A8 Port51 Push-pull KB_OUT Input
WPU
P2.1 57 - 2 - VCC 2KV I/O 1 A9 Port51 Push-pull KB_OUT Input
WPU
P2.2 56 - 1 - VCC 2KV I/O 1 A10 Port51 Push-pull KB_OUT Input
WPU
P2.3 52 - 65 - VCC 2KV I/O 1 A11 Port51 Push-pull KB_OUT Input
WPU
P2.4 51 - 64 - VCC 2KV I/O 1 A12 Port51 Push-pull KB_OUT Input
WPU
P2.5 50 - 63 - VCC 2KV I/O 1 A13 Port51 Push-pull KB_OUT Input
WPU
P2.6 49 - 62 - VCC 2KV I/O 1 A14 Port51 Push-pull KB_OUT Input
WPU
P2.7 46 - 57 - VCC 2KV I/O 1 A15 Port51 Push-pull KB_OUT Input
WPU
7
AT8xC5122/23
4202B–SCR–07/03
P3.0 45 22 56 24 VCC 2KV I/O 1 RxD Port51 Push-pull KB_OUT Input
WPU
P3.1 48 24 59 25 VCC 2KV I/O 1 TxD Port51 Push-pull KB_OUT Input
WPU
P3.2 43 20 54 23 VCC 2KV I/O 1 INT0 Port51 LED0
P3.3 41 19 52 22 VCC 2KV I/O 1 INT1 Port51 Push-pull KB_OUT Input
WPU
P3.4 39 18 50 21 VCC 2KV I/O 1 T0 Port51 Push-pull KB_OUT Input
WPU LED1
P3.5 44 21 55 - VCC 2KV I/O 1 T1 Port51
P3.6 36 17 47 20 VCC 2KV I/O 1 WR Port51 LED2
P3.7 26 13 37 16 VCC 2KV I/O 1 RD Port51 LED3
P4.0 42 - 53 - VCC 2KV I/O 1 MISO Port51
P4.1 40 - 51 - VCC 2KV I/O 1 MOSI Port51
P4.2 38 - 49 - VCC 2KV I/O 1 SCK Port51
P4.3 37 - 48 - VCC 2KV I/O 1 Port51 Push-pull KB_OUT Input
MPU LED4
P4.4 35 - 46 - VCC 2KV I/O 1 Port51 Push-pull KB_OUT Input
MPU LED5
P4.5 33 - 44 - VCC 2KV I/O 1 Port51 Push-pull KB_OUT Input
MPU LED6
P4.6 - - 61 - VCC 2KV I/O 1 Reserved
P4.7 - - 60 - VCC 2KV I/O 1 Reserved
P5.0 14 7 23 - VCC 2KV I/O 1 KB0 Port51 Push-pull Input
MPU Input
WPU
P5.1 13 - 22 - VCC 2KV I/O 1 KB1 Port51 Push-pull Input
MPU Input
WPU
P5.2 11 - 20 - VCC 2KV I/O 1 KB2 Port51 Push-pull Input
MPU Input
WPU
P5.3 10 - 19 - VCC 2KV I/O 1 KB3 Port51 Push-pull Input
WPD Input
WPU
P5.4 8 - 17 - VCC 2KV I/O 1 KB4 Port51 Push-pull Input
WPD Input
WPU
P5.5 7 - 16 - VCC 2KV I/O 1 KB5 Port51 Push-pull Input
WPD Input
WPU
Table 1. Pinout Description (Continued)
Port
VQFP64
LQFP32
PLCC68
PLCC28
Internal
Power
Supply ESD I/O Reset
Level Alt Reset
Config Conf 1 Conf 2 Conf 3 Led
8
AT8xC5122/23 4202B–SCR–07/03
P5.6 5 - 14 - VCC 2KV I/O 1 KB6 Port51 Push-pull Input
WPD Input
WPU
P5.7 4 - 13 - VCC 2KV I/O 1 KB7 Port51 Push-pull Input
WPD Input
WPU
RST 34 16 45 19 VCC I/0
Reset Input
Holding this pin low for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage lower than VIL is applied, whether or not the oscillator is running.
This pin has an internal pull-up resistor which allows the device to be reset
by connecting a capacitor between this pin and VSS.
Asserting RST when the chip is in Idle mode or Power-Down mode returns
the chip to normal operation.
The output is active for at least 12 oscillator periods when an internal reset
occurs.
D+ 60 29 5 2 DVCC I/O USB Positive Data Upstream Port
This pin requires an external 1.5 k
Ω
pull-up to VREF for full speed
D- 59 28 4 1 DVCC I/O USB Negative Data Upstream Port
VREF 61 30 6 3 AVCC O USB Voltage Reference: 3.0 < VREF < 3.6 V
VREF can be connected to D+ with a 1.5 k
Ω
resistor. The VREF voltage is
controlled by software.
XTAL
131 14 42 17 VCC I Input t o the on-chip inverti ng os c illator amplifier
To use the inte rna l oscillator, a crystal/resonator circuit is connected to this
pin. If an external oscillator is used, its output is connected to this pin.
XTAL
232 15 43 18 VCC O Output of the on-chip inverting oscillator amplifier
To use the inte rna l oscillator, a crystal/resonator circuit is connected to this
pin. If an external oscillator is used, leave XTAL2 unconnected.
EA 63 - 8 - VCC I
External Access Enable
EA must be strapped to ground in order to enable the device to f etch code
from external memory locations 0000h to FFFFh.
If security level 1 is programmed, EA will be latched on reset.
ALE 21 - 32 - VCC O
Address Latch Enable/Program Pulse: Output pulse for latching the low
byte of the address during an access to external memory. In normal
operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the
oscillator frequency, and can be used for external timing or clocking. Note
that one ALE pulse is skipped during each access to external dat a memory.
This pin is also the progr am pulse input (PROG) during Flash
programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this
bit set, ALE will be inactiv e during internal fetches
PSEN 15 - 24 - VCC O
Program Strobe Enable: The read strobe to external program memory.
When executing code from the external program memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external data memory. PSEN is not
activated during fetches from internal program memory.
PLLF 54 26 67 27 AVCC O PLL Low Pass Filter input
Receives the RC network of the PLL low pass filter.
AVCC 55 27 68 28 PWR Analog Supply Voltage
AVCC is used to supply the on-chip PLL and the USB drivers
Table 1. Pinout Description (Continued)
Port
VQFP64
LQFP32
PLCC68
PLCC28
Internal
Power
Supply ESD I/O Reset
Level Alt Reset
Config Conf 1 Conf 2 Conf 3 Led
9
AT8xC5122/23
4202B–SCR–07/03
VCC 20 12 31 15 PWR Supply Voltage
VCC is used to power the internal voltage re gulators and internal I/O’s
LI 18 10 29 13 PWR DC/DC Input
LI must be tied to VCC through an external c oil and provide the current for
the pump charge of the DC/DC converter
CVCC 17 9 28 12 PWR Card Supply Volt age
CVCC is the programmable voltage output for the Card interface. It must be
connected to an external decoupling capacitor
DVCC 1 1 10 5 PWR
Digital Supply Voltage
DVCC is used to supply the digital core and internal I/O’s. It is internally
connected to the output of a 3.3V voltage regulat or and must be connected
to an external decoupling capac itor
CVSS 19 11 30 14 GND DC/DC Ground
CVSS is used to sink high shunt currents from the external coil
VSS 16 8 25 11 GND Digital Ground
VSS is used to supply the buff er ring and the digital c ore
AVSS 53 25 66 26 GND Analog Gr ound
AVSS is used to supply the on-chip PLL and the USB drivers
Table 1. Pinout Description (Continued)
Port
VQFP64
LQFP32
PLCC68
PLCC28
Internal
Power
Supply ESD I/O Reset
Level Alt Reset
Config Conf 1 Conf 2 Conf 3 Led
10
AT8xC5122/23 4202B–SCR–07/03
I/O Port Definition
Ports vs packages Table 2. IO number vs packages
Port 0 Port 0 has the following functions:
–Default function: Port 0 is an 8-bit I/O port.
–Alternate function: Port 0 is also the multiplexed low-order address and data
bus during accesses to external Program and Data Memory. In this
application, it uses strong internal pull-ups when emitting 1’s and it can drive
CMOS inputs without external pull-ups.
Port 0 has the following configurations:
–Default configuration: open drain bi-directional I/O port. Port 0 pins that have
1’s written to them float, and in this state they can be used as high-
impedance inputs.
–Configu ra tio n 2: Low speed outp ut, “KB_OUT”
–Configuration 3: Push-pull output
Port 1 Port 1 has the following functions:
–Default function: Only Port 1.2, P1.6 and P1.7 are standard I/O’s; the other
ports can only be activated with the SCIB function.
–Alternate function and configuration: see Table 3.
Table 3. Port 1 description.
P0 P1 P2 P3 P4 P5 Total
VQFP6488888646
LQFP32 8 8 1 17
PLCC28 6 6 1 13
PLCC6888888848
Port
Alternate Function Configuration
Signal Description Mode Description
P1.0 CIO Smart card interface function
Car d I/O Port51 CVCC supply: inactive at reset
P1.1 CC8 Smart card interface function
Card contact 8 Push-pull CVCC supply: zero level at reset
P1.2 CPRES Smart card interface function
Card presence Port51 Weak & medium pull-up can be
deconnected by software
P1.3 CC4 Smart card interface function
Card contact 4 Push-pull CVCC supply: zero level at reset
P1.4 CCLK Smart card interface function
Car d cloc k Push-pull CVCC supply: zero level at reset
P1.5 CRST Smart card interface function
Card reset Push-pull CVCC supply: zero level at reset
P1.6 SS SS pin of the SPI function Port51
11
AT8xC5122/23
4202B–SCR–07/03
Note: P1.7 is switched automatically to Push-pull when the alternate clock is selected (see
Table 42 on page 48 )
Port 2 Port 2 has the following functions:
–Default function: Port 2 is an 8-bit I/O port.
–Alternate function 1: Port 2 is also the multiplexed high-order address during
accesses to external Program and Data Memory. In this application, it uses
strong internal pull-ups when emitting 1’s and it can drive CMOS inputs
without external pull -u ps.
Port 2 has the following configurations:
–Default configuration: Pseudo bi-directional “Port51” digital input/output with
internal pull-ups.
–Configuration 1: Push-pull output
–Configu ra tio n 2: Low speed outp ut, “KB_OUT
–Configuration 3: Input with weak pull-up, “WPU input”
Port 3 Port 3 has the following functions:
–Default function: Port 3 is an 8-bit I/O port.
–Alternate functions: see table below
Port 3 has the following configurations:
–Default configuration: Pseudo bi-directional “Port51” digital input/output with
internal pull-ups.
–Alternate configurations: See Table 4.
Table 4. Port 3 description
P1.7 CCLK1 Altern ate smart card clock output Port51/P
ush-pull
Port
Altern a te Functions Configurations
Signal Description Mode 1 Mode 2 Mode 3 Mode 4
P3.0 RxD Receiver data input (asynchronous) or data input/output
(synchronous) of the serial interface Push-pull KB_O UT Input WPU
P3.1 TxD Transm itter data output (asynchronous ) or clock output
(synchronous) of the serial interface Push-pull KB_O UT Input WPU
P3.2 INT0 External interrupt 0 input/timer 0 gate control input LED0
P3.3 INT1 Ext ernal interrupt 1input/timer 1 gate control input Push-pull KB_O UT Input WPU
P3.4 T0 Timer 0 counter input Push-pull KB_OUT Input WPU LED1
P3.5 T1 Timer 1 counter input
P3.6 WR External Data Memory write strobe; latches the data byte
from port 0 into the external data memory LED2
P3.7 RD Ext ernal Data Memory read strobe; Enables the external
data memory. Port 3 can drive CMOS inputs without external
pull-ups LED3
12
AT8xC5122/23 4202B–SCR–07/03
Port 4 Port 4 has the following functions:
–Default function: Port 4 is an 6-bit I/O port.
–Alternate functions: see table below
Port 4 has the following configurations:
–Default configuration: Pseudo bi-directional “Port51” digital input/output with
internal pull-ups.
–Alternate configurations: See Table 5..
Table 5. Port 4 description
Port 5 Port 5 has the following functions:
–Default function: Port 5 is an 8-bit I/O port.
–Alternate function 1: Port 5 is an 8-bit keyboard port KB0 to KB7.
Port 5 has the following configurations:
–Default configuration: Pseudo bi-directional “Port51” digital input/output with
internal pull-ups.
–Alternate configuration: see Table 6..
Table 6. Port 5 description
Port
Alternate Functions Configurations
Signal Description Mode 1 Mode 2 Mode 3
P4.0 MISO SPI Master In Sl av e Out I/O
P4.1 M O SI SPI Master Out Sl ave In I/ O
P4.2 SCK SPI clock
P4.3 Push-pull KB_OUT Input MPU
P4.4 Push-pull KB_OUT Input MPU
P4.5 Push-pull KB_OUT Input MPU
Port
Configurations
Mode 1 Mode 2 Mod e 3
P5.0 Push-pull Input MPU Input WPU
First clus terP5.1 Push-pull Input MPU Input WPU
P5.2 Push-pull Input MPU Input WPU
P5.3 Push-pull Inp ut WPD Input WPU Second cluster
P5.4 Push-pull Inp ut WPD Input WPU
P5.5 Push-pull Inp ut WPD Input WPU
P5.6 Push-pull Inp ut WPD Input WPU Third cluster
P5.7 Push-pull Inp ut WPD Input WPU
13
AT8xC5122/23
4202B–SCR–07/03
Port Configuration
Standard I/O P0 The P0 port is described in Figure 5.
Figure 5. Standard Input/Output P0
Quasi-Bi-directional Output
Configuration The default port output configuration for standard I/O ports is the quasi-bi-directional
output th at is common on the 80 C51 and mos t of its derivati ves. The “Port51” ou tput
type can be used as both an input and output without the need to reconfigure the port.
This is possible because when the port outputs a logic high, it is weakly driven, allowing
an external device to pull the pin low.
When the port outputs a logic low state, it is driven strongly and is able to sink a fairly
large current.
These features are somewhat similar to an open-drain output except that there are three
pull-up transistors in the quasi-bi-directional output that serve different purposes.
One of these pull-ups, called the weak pull-up, is turned on whenever the port latch for
the pin contains a logic 1. The weak pull-up sources a very small current that will pull the
pin hi gh if it is lef t floating . The we ak pull-u p can be turned off by the DPU bi t in AUXR
register.
A second pull -up, c all ed the med ium pull -up, i s turne d on whe n the port latch for t he pin
contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the pri-
mar y so u rce c urrent fo r a qu a si- bi-direc t io na l pi n th a t is output ti n g a 1. I f a pi n th a t ha s a
logic 1 on it is pulled low by an external device, the medium pull-up turns off, and only
the weak pull-up remains on. In order to pull the pin low under these conditions, the
external device has to sink enough current to overpower the medium pull-up and take
the voltage on the port pin below its input threshold.
The “Port51” is described in Figure 6.
MUX
Pin
ADDR/DATA CONTROL Vcc
1
0
Input
Data
Port latch
Data
PMOS
NMOS
14
AT8xC5122/23 4202B–SCR–07/03
Figure 6. Quasi-Bi-directional Output
Push-pull Output
Configuration The push-pull output configuration has the same pull-down structur e as both the open
drain and the quasi-bi-directional output modes, but provides a continuous strong pull-
up when the port la tch con tains a lo gic 1. The pus h-pull mo de may be us ed when mor e
source current is needed from a port output.
The Push-pu ll port con fig ur ation is shown in Figu re 7.
Figure 7. Push-pull Output
Input with Medium or Weak
Pull-up Configuration The input with pull-up (Input MPU and Input WPU) configuration is shown in Figure 8.
2 CPU
Input
Pin
Strong Weak Medium
N
PP
P
CLOCK DELAY
Port Latch
Data
Data
DPU (AUXR Reg.)
PMOS
NMOS
Input
Pin
Strong
N
P
Port latch
Data
Data
PMOS
NMOS
15
AT8xC5122/23
4202B–SCR–07/03
Figure 8. Input with Pull-up
Input with Weak Pull-down
Configuration The input with pull-down (input WPD) configuration is shown in Figure 9
Figure 9. Input with Pull-down
Low Speed Output
Configuration The low speed output with low speed tFALL and tRISE can drive keyboard.
The curren t limitation of the LED2CTRL bloc k requires a p olarisation current of about
250 µA. This block is automatically disabled in power-down mode.
The low speed output configuration (KB_OUT) is shown in Figure 10.
Figure 10. Low-speed Output
Input
Pin
Data
Weak
P Medium
P
Stuck to 0 if Medium
Stuck to 0 if Weak
Input
Pin
Data
Weak
N
1
Pin
P
PWEAKCTRL
Port latch
Data N
N
NMOS
PCON.1
Weak
LED2CTRL
Input
Data
16
AT8xC5122/23 4202B–SCR–07/03
LED Source Cur rent The LED configuration is shown in Figure 11.
Figure 11. LED Source Current
Notes: 1. When switching a low level, LEDCTRL device has a permanent current of about
N mA/15 (N is 2, 4 or 8).
2. The port must be configured to be used as output by means of PMOD0 and PMOD1
registers and the level of current must be programmed by means of LEDCON0 and
LEDCON1 registers before switching the led on.
3. The value of th e pull -up dep ends o n the mo de that is sel ected to conf igur e the po rt as
output.
Table 7. Low Speed Output Configuration
Input S ignals Outputs Signa ls
PIN CommentsPCON.1 Port Latch Data NMOS LED2CTRL PWEAKCTRL
0001 10
Operating mode
0100 01
1010 10
Power down mode
1100 01
Pin
Port Latch
Data
LEDx.0
LEDx.1
NMOS N
N
(See Note 3)
LEDCTRL
Input
Data
17
AT8xC5122/23
4202B–SCR–07/03
Registers
Reset Value = 0000 0x00 b
Table 8. LED Source Current
LEDx.1 LEDx.0 Port Latch Da ta NMOS PIN Comments
00 0 10
LED control disabled
00 1 01
01 0 00LED mode 2 mA
01 1 01
10 0 00LED mode 4 mA
10 1 01
11 0 00
LED mode 10 mA
11 1 01
Table 9. Port Mode Register 0 - PMOD0 (91h) for AT8xC5122
7654 3 210
P3C1 P3C0 P2C1 P2C0 CPRESRES - P0C1 P0C0
Bit Number Bit Mnemonic Description
7 - 6 P3C1-P3C0
Port 3 Configuration bits (Applicable to P3.0, P3.1, P3.3, P3.4 only)
00 Quasi bi-directional
01 Push-pull
10 Output Low Speed
11 Input with weak pull-up
5-4 P2C1-P2C0
Port 2 Co nfigura tion b its
00 Quasi bi-directional
01 Push-pull
10 Output Low Speed
11 Input with weak pull-down
3CPRESRES
Card Presence Pull-up resistor
Cleared to connect the internal pull-up
Set to disconnect the internal pull-up
2-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1-0 P0C1-P0C0
Port 0 Co nfigura tion b its
00 C51 Standard P0
01 Reserved
10 Output Low Speed
11 Push-pull
18
AT8xC5122/23 4202B–SCR–07/03
Reset Value = 00xx 0x xx b
Reset Value = 0000 0000b
Table 10. Port Mode Register 0 - PMOD0 (91h) for AT8xC5123
7654 3 210
P3C1 P3C0 - - CPRESRES - - -
Bit Number Bit Mnemonic Description
7 - 6 P3C1-P3C0
Port 3 Configuration bits (Applicable to P3.0, P3.1, P3.3, P3.4 only)
00 Quasi bi-directional
01 Push-pull
10 Output Low Speed
11 Input with weak pull-up
5-4 Reserved
The value read from this bit is indeterminate. Do not set this bit.
3CPRESRES
Card Presence Pull-up resistor
Cleared to connect the internal pull-up
Set to disconnect the internal pull-up
2-0 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
Table 11. Port Mode Register 1 - PMOD1 (84h) for AT8xC5122
76543210
P5HC1 P5HC0 P5MC1 P5MC0 P5LC1 P5LC0 P4C1 P4C0
Bit Number Bit Mnemonic Description
7 - 6 P5HC1-P5HC0
Port 5 High Configuration bits (Applicable from P5.6 to P5.7 only )
00 Quasi bi-directional
01 Push-pull
10 Input with weak pull- down
11 Input with weak pull-up
5 - 4 P5MC1-P5MC0
Port 5 Me dium Config ura tion bi t s ( Appl icab le f rom P 5.3 t o P5 .5 on ly)
00 Quasi bi-directional
01 Push-pull
10 Input with weak pull- down
11 Input with weak pull-up
3 - 2 P5LC1-P5LC0
Port 5 Low Configuration bits (Applicable from P5.0 to P5.2 only)
00 Quasi bi-directional
01 Push-pull
10 Input with medium pull-up
11 Input with weak pull-up
1 - 0 P4C1-P4C0
Port 4 Configuration bits (Applicable from P4.3 to P4.5 only)
00 Quasi bi-directional
01 Push-pull
10 Output Low Speed
11 Input with medium pull-up
19
AT8xC5122/23
4202B–SCR–07/03
Reset Val ue = xxxx 00x xb
Reset Value = 0000 0000b
Table 12. Port Mode Register 1 - PMOD1 (84h) for AT8xC5123
76543210
----P5LC1P5LC0--
Bit Number Bit Mnemonic Description
7 - 4 Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 - 2 P5LC1-P5LC0
Port 5 Low Configuration bits (Applicable from P5.0 to P5.2 only)
00 Quasi bi-directional
01 Push-pull
10 Input with medium pull-up
11 Input with weak pull-up
1 - 0 Reserved
The value read from this bit is indeterminate. Do not set this bit.
Table 13. LED Port Control Register 0 - LEDCON0 (F1h)
76543210
LED3.1 LED3.0 LED2.1 LED2.0 LED1.1 LED1.0 LED0.1 LED0.0
Bit Number Bit Mnemonic Description
7 - 6 LED3
Port LED3 C on f i gu r a tion bi ts
00 LED control disabled
01 2 mA current source when P3.7 is configured as Quasi-bi-directional mode
10 4 mA current source when P3.7 is configured as Quasi-bi-directional mode
11 10 mA curr ent source when P3.7 is configured as Quasi-bidirect. mode
5 - 4 LED2
Port LED2 C on f i gu r a tion bi ts
00 LED control disabled
01 2 mA current source when P3.6 is configured as Quasi-bi-directional mode
10 4 mA current source when P3.6 is configured as Quasi-bi-directional mode
11 10 mA curr ent source when P3.6 is configured as Quasi-bidirect. mode
3 - 2 LED1
Port LED1 C on f i gu r a tion bi ts
00 LED control disabled
01 2 mA current source when P3.4 is configured as Quasi-bi-directional mode
10 4 mA current source when P3.4 is configured as Quasi-bi-directional mode
11 10 mA curr ent source when P3.4 is configured as Quasi-bidirect. mode
1 - 0 LED0
Port LED0 C on f i gu r a tion bi ts
00 LED control disabled
01 2 mA current source when P3.2 is configured as Quasi-bi-directional mode
10 4 mA current source when P3.2 is configured as Quasi-bi-directional mode
11 10 mA curr ent source when P3.2 is configured as Quasi-bidirect. mode
20
AT8xC5122/23 4202B–SCR–07/03
Reset Value = 0000 0000b
Table 14. LED Port Control Register 1- LEDCON1 (F1h) only for AT8xC5122
76543210
- - LED6.1 LED6.0 LED5.1 LED5.0 LED4.1 LED4.0
Bit Number Bit Mnemonic Description
7 - 6 Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 - 4 LED6
Port LED6 C on f i gu r a tion bi ts
00 LED control disabled
01 2 mA current source when P4.5 is configured as Quasi-bi-directional mode
10 4 mA current source when P4.5 is configured as Quasi-bi-directional mode
11 10 mA curr ent source when P4.5 is configured as Quasi-bidirect. mode
3 - 2 LED5
Port LED5 C on f i gu r a tion bi ts
00 LED control disabled
01 2 mA current source when P4.4 is configured as Quasi-bi-directional mode
10 4 mA current source when P4.4 is configured as Quasi-bi-directional mode
11 10 mA curr ent source when P4.4 is configured as Quasi-bidirect. mode
1 - 0 LED4
Port LED0 C on f i gu r a tion bi ts
00 LED control disabled
01 2 mA current source when P4.3 is configured as Quasi-bi-directional mode
10 4 mA current source when P4.3 is configured as Quasi-bi-directional mode
11 10 mA curr ent source when P4.3 is configured as Quasi-bidirect. mode
21
AT8xC5122/23
4202B–SCR–07/03
SFR Description The S pecial Func tion Regis ters (SFRs ) of the A T8xC5122/2 3 fall into the foll owing
categories:
•C51 Core Registers: ACC, B, DPH, DPL, PSW, SP
•System Configuration Registers: PCON, CKRL, CKCON0, CKCON1, CKSEL,
PLLCON , PLLDIV, AUXR, AUXR1
•I/O Port Registers: P0, P1, P2, P3, P4, P5,PMOD1, PMOD2
•Timer Registers: TCON, TH0, TH1, TMOD, TL0, TL1
•Watchdog (WD) Registers: WDTRST, WDTPRG
•Serial I/O Port Registers: SADDR, SADEN, SBUF, SCON
•Baud Rate Generator (BRG) Registers: BRL, BDRCON
•System Interrupt Registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1
•Smart Card Interface (SCI) Registers: SCSR, SCCON/SCETU0, SCISR/SCETU1,
SCIER/SCIIR, SCTBUF/SCRBUF, SCGT0/SCWT0, SCGT1/SCWT1,
SCICR /SCW T 2, SCICLK
•DC/DC Converter Registers: DCCKPS
•Keyboard Interfac e Registers: KBE, KBF, KBLS
•Serial Port Interface (SPI) Registers: SPCON , SPSTA, SPDAT
•Universal Serial Bus (USB) Registers:USBCON, USBADDR, USBINT, USBIEN,
UEPNUM, UEPCONX, UEPSTAX, UEPRST, UEPINT, UEPIEN, UEPDATX,
UBYCTX, UFNUML, UFNUMH
•LED Controller Registers: LEDCON0, LEDCON1
22
AT8xC5122/23 4202B–SCR–07/03
Notes: 1. Mapping is done using SCRS bit in SCSR register: if SCRS = 0, upper cell, if SCRS = 1, lower cell.
2. Mapping is done using P/D# bit in PMOD0 register : if P/D# = 0, upper cell, if P/D# = 1, lower cell.
Note: Blank: Reserved, no write or read is allowed.
Table 15. AT8xC5122 SFR Mapping
Bit
addressable Not bit addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h UEPINT
0000 0000 FFh
F0h B
0000 0000 LEDCON0
0000 0000 F7h
E8h P5
1111 1111 EFh
E0h ACC
0000 0000 LEDCON1
XX00 0000 UBYCTX
0000 0000 E7h
D8h DFh
D0h PSW
0000 0000 RCON
XXXX 0XXX UEPCONX
1000 0000 UEPRST
0000 0000 D7h
C8h UEPSTAX
0000 0000 UEPDATX
0000 0000 CFh
C0h P4
1111 1111
SCWT3(1)
0000 0000 UEPIEN
0000 0000 SPCON
0001 0100 SPSTA
0000 0000 SPDAT
1111 1111 USBADDR
1000 0000 UEPNUM
0000 0000 C7h
SCICLK(1)
0X10 1111
B8h IPL0
X000 000 SADEN
0000 0000 UFNUML
0000 0000 UFNUMH
0000 0000 USBCON
0000 0000 USBINT
0000 0000 USBIEN
0000 0000 DCCKPS
0000 0000 BFh
B0h P3
1111 1111 IEN1
XXXX X000 IPL1
00XX 00X0 IPH1
00XX 00X0
SCWT0(1)
1000 0000 SCWT1 (1)
0010 0101 SCWT2 (1)
0000 0000 IPH0
X000 0000 B7h
SCGT0 (1)
0000 1100 SCGT1(1)
XXXX XXX0 SCICR (1)
0000 0000
A8h IEN0
0000 0000 SADDR
0000 0000
SCTBUF (1)
0000 0000 SCSR
X000 1000
SCCON (1)
000 0000 SCISR (1)
10X0 0000 SCIIR (1)
0X00 0000 CKCON1
XXXX XXX0 AFh
SCRBUF (1)
0000 0000 SCETU0 (1)
0111 0100 SCETU1 (1)
XXXX X001 SCIER (1)
0X00 0000
A0h P2
1111 1111 ISEL
0000 0100 AUXR1
XX1X 0XX0 PLLCON
XXXX X000 PLLDIV
0000 0000 WDTRST
XXXX XXXX WDTPRG
XXXX X000 A7h
98h SCON
0000 0000 SBUF
XXXX XXXX BRL
0000 0000 BDRCON
XXX0 0000 KBLS
0000 0000 KBE
0000 0000 KBF
0000 0000 9Fh
90h P1
1111 1111 PMOD0(2)
0000 0000 CKRL
XXXX 11 11 97h
88h TCON
0000 0000 TMOD
0000 0000 TL0
0000 0000 TL1
0000 0000 TH0
0000 0000 TH1
0000 0000 AUXR
0XXX X000 CKCON0
X0X0 X000 8Fh
80h P0
1111 1111 SP
0000 0111 DPL
0000 0000 DPH
0000 0000 PMOD1
0000 0000 CKSEL
XXXX XXX0 PCON
00X1 0000 87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
23
AT8xC5122/23
4202B–SCR–07/03
Notes: 1. Mapping is done using SCRS bit in SCSR register: if SCRS = 0, upper cell, if SCRS = 1, lower cell.
2. Mapping is done using P/D# bit in PMOD0 register : if P/D# = 0, upper cell, if P/D# = 1, lower cell.
Note: Blank: Reserved, no write or read is allowed.
Table 16. AT8xC5123 SFR Mapping
Bit
addressable Not bit addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h UEPINT
0000 0000 FFh
F0h B
0000 0000 LEDCON0
0000 0000 F7h
E8h P5
XXXX XXX1 EFh
E0h ACC
0000 0000 UBYCTX
0000 0000 E7h
D8h DFh
D0h PSW
0000 0000 UEPCONX
1000 0000 UEPRST
0000 0000 D7h
C8h UEPSTAX
0000 0000 UEPDATX
0000 0000 CFh
C0h
0P4
11XX XXXX
SCWT3
0000 0000 UEPIEN
0000 0000 USBADDR
1000 0000 UEPNUM
0000 0000
0
C7h
1SCICLK
0X10 1111 1
B8h IPL0
X000 000 SADEN
0000 0000 UFNUML
0000 0000 UFNUMH
0000 0000 USBCON
0000 0000 USBINT
0000 0000 USBIEN
0000 0000 DCCKPS
0000 0000 BFh
B0h
0P3
1111 1111 IEN1
X0XX 0XXX IPL1
X0XX 0XXX IPH1
X0XX 0XXX
SCWT0(1)
1000 0000 SCWT1 (1)
0010 0101 SCWT2 (1)
0000 0000 IPH0
X000 0000
0
B7h
1SCGT0 (1)
0000 1100 SCGT1(1)
XXXX XXX0 SCICR (1)
0000 0000 1
A8h
0IEN0
0000 0000 SADDR
0000 0000
SCTBUF (1)
0000 0000 SCSR
X000 1000
SCCON (1)
000 0000 SCISR (1)
10X0 0000 SCIIR (1)
0X00 0000 CKCON1
XXXX XXX0
0
AFh
1SCRBUF (1)
0000 0000 SCETU0 (1)
0111 0100 SCETU1 (1)
XXXX X001 SCIER (1)
0X00 0000 1
A0h ISEL
0000 0100 AUXR1
XXXX 0XX0 PLLCON
XXXX X000 PLLDIV
0000 0000 WDTRST
XXXX XXXX WDTPRG
XXXX X000 A7h
98h SCON
0000 0000 SBUF
XXXX XXXX BRL
0000 0000 BDRCON
XXX0 0000 9Fh
90h P1
1111 1111 PMOD0(2)
00XX 0XXX CKRL
XXXX 11 11 97h
88h TCON
0000 0000 TMOD
0000 0000 TL0
0000 0000 TL1
0000 0000 TH0
0000 0000 TH1
0000 0000 AUXR
0XXX X000 CKCON0
X0X0 X000 8Fh
80h SP
0000 0111 DPL
0000 0000 DPH
0000 0000 PMOD1
XXXX 00XX CKSEL
XXXX XXX0 PCON
00X1 0000 87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
24
AT8xC5122/23 4202B–SCR–07/03
Note: 1. Only for AT8xC5122
Note: 1. Only for AT8xC5122
Table 17. C51 Core Registers
MnemonicAddName 76543210
ACC E0h Accumulator ACC
B F0h B Register B
PSW D0h Pro gram Status Word CY AC F0 RS1 RS0 O V F1 P
SP 81h Stack Pointer SP
DPL 82h Data Pointer Low byte (LSB
of DPTR) DPL
DPH 83h Data Pointer High byte
(MSB of DPTR) DPH
Table 18. System Configuration Registers
MnemonicAddName 76 5 43210
PCON 87h Power Controller SMOD1 SMOD0 POF GF1 GF0 PD IDL
CKCON0 8Fh Clock Controller 0 WDX2 SIX2 T1X2 T0X2 X2
CKCON1 A Fh Clock Controller 1 SPIX2
CKSEL 85h Clock Selection CKS
CKRL 97h Clock Reload Register CKREL 3-0
PLLCON A3h PLL Controller Register EXT48 PLLEN PLOCK
PLLDIV A4h PLL Divider register R3-0 N3-0
RCON (1) D1h Data Memory
Configuration RPS
AUXR 8Eh Auxiliary Register 0 DPU XRS0 EXTRAM A0
AUXR1 A2h Auxiliary Register 1 ENBOOT(1) GF3 DPS
Table 19. I/O Ports Register
Mnemonic Add Name 7 6 5 4 3 2 1 0
P0(1) 80h Port 0 P0
P1 90h Port 1 P1
P2(1) A0h Port 2 P2
P3 B0h Port 3 P3
P4(1) C0h Port 4 P4
P5 E8 h Port 5 P5(only P5.0 for AT8xC5122)
PMOD0 91h Port Mode Register 0 P3C1 P3C0 P2C1 (1) P2C0(1) CPRESRES - P0C1(1) P0C0(1)
PMOD1 84h Port Mode Register 1 P5HC1(1) P5HC0(1) P5MC1(1) P5MC0(1) P5LC1 P5LC0 P4C1(1) P4C0(1)
25
AT8xC5122/23
4202B–SCR–07/03
Note: 1. Only for AT8xC5122
Table 20. Timer Registers
MnemonicAddName 76543210
TH0 8Ch Timer/Counter 0 High byt e TH0
TL0 8Ah Timer/Counter 0 Low byte TL0
TH1 8Dh Timer/Counter 1 High byt e TH1
TL1 8Bh Timer/Counter 1 Low byte TL1
TCON 88h Timer/Counter 0 and 1
control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TMOD 89h Timer /Counter 0 and 1
Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00
Table 21. Wat ch dog Regi st ers
MnemonicAddName 76543210
WDTRST A6h Wat chdog Timer Reset WDT RST
WDTPRG A7h Watchdog Timer Program S2-0
Table 22. Serial I/O Port Registers
MnemonicAddName 76543210
SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 R B8 TI RI
SBUF 99h Serial Data Buffer SBUF
SADEN B9h Slave Address Mask SADEN
SADDR A9h Slave Address SADDR
Table 23. Baud Rate Generator (BRG) Registers
MnemonicAddName 76543210
BRL 9Ah Baud Rate Reload BRL
BDRCON 9Bh Baud Rate Control BRR TBCK RBCK SPD SRC
Table 24. System Interrupt Registers
MnemonicAddName 76543210
IEN0 A 8h Interrupt Enable Control 0 EA ES ET1 EX1 ET0 EX0
IEN1 B 1h Interrupt Enable Control 1 EUSB ESCI ESPI(1) EKB(1)
IPL0 B8h Interrupt Priority Control
Low 0 PSL PT1L PX1L PT0L PX0L
IPH0 B7h Interrupt Priority Control
High 0 PSH PT1H PX1H PT0H PX0H
IPL1 B2h Interrupt Priority Control
Low 1 PUSBL PSCIL PSPIL(1) PKBL(1)
IPH1 B3h Interrupt Priority Control
High 1 PUSBH PSCIH PSPIH(1) PKBH(1)
ISEL A1h Interrupt Enable Register CPLEV PRESIT RXIT OELEV OEEN PRESEN RXEN
26
AT8xC5122/23 4202B–SCR–07/03
Note: 1. Only for AT8xC5122
Table 25. Smart Card Interface (SCI) Registers
MnemonicAddName 76543210
SCGT0 B4h Smart Card Transmit Guard
Time Register 0 GT7 - 0
SCGT1 B5h Smart Card Transmit Guard
Time Register 1 GT8
SCWT0 B4h Smart Card Character/ Block
Wait Time Register 0 WT7 - 0
SCWT1 B5h Smart Card Character/ Block
Wait Time Register 1 WT15-8
SCWT2 B6h Smart Card Character/ Block
Wait Time Register 2 WT23-16
SCWT3 C1h Smart Card Character/ Block
Wait Time Register 3 WT31-24
SCICR B6h Smart Card Interface Control
Register RESET CARDDET VCARD1-0 UART WTEN CREP CONV
SCCON ACh Smart Card Interface
Contacts Register CLK CARDC8 CARDC4 CARDIO CARDCLK CARDRST CARDVCC
SCETU0 ACh Smart Card ETU Register 0 ETU7 - 0
SCETU1 ADh Smart Card ETU Register 1 COMP ETU10-8
SCISR ADh Smart Card UART Interface
Status Register (Read only) SCTBE CARDIN ICARDOVF VCARDOK SCWTO SCTC SCRC SCPE
SCIIR AEh Smart Card UART Interrupt
Identification Register (Read
only) SCTBI ICARDERR VCARDERR SCWTI SCTI SCRI SCPI
SCIER AEh Smart Card UART Interrupt
Enable Register ESCTBI ICARDER EVCARDER ESCWTI ESCTI ESCRI ESCPI
SCSR ABh Smart Card Selection
Register BGTEN CREPSEL ALTKPS1-0 SCCLK1 SCRS
SCTBUF AAh Smart Card Transmit Buffer
Register (Write only) Can store a new byte to be transmitted on the I/O pin when SCTBE is set. Bit ordering on the I/ O pin
depends on the convention
SCRBUF AAh Smart Card Receive Buffer
Register (Read Only) Provides the byte received from the I/O pin when SCRI is set. Bit ordering on the I/O pin depends on
the convention.
SCICLK C1h Smart Card Frequency
Prescaler Register XTSCS(1) SCICLK5-0
Table 26. DC/DC Converter Register
MnemonicAddName 76543210
DCCKPS BFh DC/DC Converter Reload
Register MODE OVFADJ BOOST[1-0] DCCKPS3-0
Table 27. Keyboard Interface Registers
MnemonicAddName 76543210
KBF(1) 9E h Keyboard Flag Register KBE7 - 0
KBE(1) 9Dh Keyboard Input Enable
Register KBF7 - 0
27
AT8xC5122/23
4202B–SCR–07/03
Note: 1. Only for AT8xC5122
Notes: 1. Only for AT8xC5122
Note: 1. Only for AT8xC5122
KBLS(1) 9Ch Keyboard Level Selector
Register KBLS7 - 0
Table 27. Keyboard Interface Registers
MnemonicAddName 76543210
Table 28. Serial Port Interface (SPI) Registers
MnemonicAddName 76543210
SPCON(1) C3h Ser ial Peripheral Control S PR2 SPEN S SDIS MSTR CPOL CPH A SPR1 S PR0
SPSTA(1) C4h Ser ial Peripheral Status-
Control SPIF WCOL MODF
SPDAT(1) C5h Serial Peripheral Data R7 - 0
Table 29. Universal Serial Bus (USB) Registers
MnemonicAddName 76543210
USBCON BCh USB Global Control USBE SUSPCLK SDRMWUP DETACH UPRSM RMWUPE CONFG FADDEN
USBADDR C6h USB Address FEN UADD6-0
USBINT BDh USB Global Interrupt WUPCPU EORINT SOFINT SPINT
USBIEN BEh US B G lobal Interrupt
Enable EWUPCPU EEORINT ESOFINT ESPINT
UEPNUM C7h USB Endpoint Number EPNUM3-0
UEPCONX D4h USB Endpoint X Control EPEN NAKIEN NAKOUT NAKIN DTGL EPDIR EPTYPE1 EPTYPE0
UEPSTAX CEh USB Endpoint X Status DIR RXOUTB1 STALLRQ TXRDY STL/CRC RXSETUP RXOUTB0 TXCMP
UEPRST D5h USB Endpoint Reset EP6RST EP5RST EP4RST EP3RST EP2RST EP1RST EP0RST
UEPINT F8h USB Endpoint Interrupt EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
UEPIEN C2h USB Endpoint Interrupt
Enable EP6INTE EP5INTE EP4INTE EP3INTE EP2INTE EP1INTE EP0INTE
UEPDATX CFh USB Endpoint X Fifo Data FDAT7 - 0
UBYCTX E2h US B Byt e Counter Low
(EPX) BYCT6-0
UFNUML BAh USB Frame Number Low FNUM7 - 0
UFNUMH BBh USB Frame Number High CRCOK CRCERR FNUM10-8
Table 30. LED Cont roll er Registers
MnemonicAddName 76543210
LEDCON0 F1h LED Control 0 LED3 LED2 LED1 LED0
LEDCON1(1) E1h LED Control 1 LED6 LED5 LED4
28
AT8xC5122/23 4202B–SCR–07/03
Clock Controller The clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock
Loop (PLL). All the internal clocks to the peripherals and CPU core are generated by this
controller.
The AT8xC5122/23 XTAL1 and XTAL2 pins are the input and the output of a single-
stage o n-chip inve rter (see Fi gure 12), whic h can be confi gured with of f-chip comp o-
nents as a Pierce oscillator (see Figure 14). Value of capacitors and crystal
characteristics are detailed in the Section “DC Charac teristics” of th e AT8xC51 22/23
datasheet.
The XTAL1 pin can also be used as input for an external 48 MHz clock.
The clock controller outputs several different clocks as shown in Figure 12:
•a clock for the CPU core
•a clock for the peripherals which is used to generate the timers, watchdog, SPI,
UART, and ports sampling clocks. This divided clock will be used to generate the
alternate card clock.
•a clock for the USB
•a clock for the SCIB controller
•a clock for the DC/DC converter
These cl ock s ar e en abl ed or not d epending o n the pow er reduc ti on m ode as deta il ed in
Section “Power Management”, page 142.
These clocks are generated using four presacalers defined in the table below:
Prescaler Register Reload Factor Function
PR1 CKRL CKRL0-3 CPU & Peripheral clocks
PR2 SCICLK SCICLK0-5 Smart card
PR3 SCSR ALTKPS0-1 Alternate card
PR4 DCCKPS DCCKPS3:0 DC/DC
29
AT8xC5122/23
4202B–SCR–07/03
Figure 12. Oscillator Block Diagram
CPU and Peripheral Clock Two clocks sources are available for CPU and peripherals:
–Crystal oscillator on XTAL1 and XTAL2 pins and a 96 MHz PLL (Set by SFR
to this value).
–External 48 MHz clock on XTAL1 pin
These clock sources are adapted by the PR1 prescaler to generate the CPU core
CK_CPU and the peripheral clocks:
–CK_IDLE for alternate card and peripherals registers access
–CK_T0 for Timer 0
–CK_T1 for Timer 1
–CK_SI for the UART
–CK_WD for the Watchdog
–CK_SPI for SPI
XTAL1
XTAL2
PD
PCON.1
PLL 96
MHz
EXT48
PLLCON.2
0
1
0
1
CKS
CKSEL.0
0
1
X2
CKCON.0
PR1
CKRL.3:0
IDL
PCON.0
CPU
DC/DC
PR4
SCIB
PR2
CK_IDLE
Alt Card
PR3
Converter
1/2
CK_USB
0
1
USB
CK_ISO
CK_CPU
CK_XTAL1
CK_PLL
DCCKPS.3:0
SCICLK5:0
SCSR3:2
0
1
PeriphX2
CKCON0.X or
1
0
X2
CKCON0.0
CK_T0
Peripherals
CK_T1
CK_SI
CK_WD
CK_SPI
CK_Periph
CK_IDLE
CK_IDLE
PLLEN
PLLCON.1
CK_XTAL1
CK_PLL
CK_PLL
CK_XTAL1
CK_XTAL1
Periph = T0, T1, SI, WD or SPI
CKCON1.0
XTSCS
SCICLK.7
30
AT8xC5122/23 4202B–SCR–07/03
The CPU and peripherals clocks frequencies are defined in the table below.
CK_ISO and CK_CPU selection
Two conditions must be present for an optimal work of the SCIB:
•CK_ CPU > 4/3 * CK_ISO and
•CK_CPU < 6 * CK_ISO.
If the CK_CPU <= 4/3 * CK_ISO, the SCIB doesn’t work.
If the CK_CPU >= 6* CK_ISO, the programmer must take care in three cases:
•Read (or write) operation on a SCIB register followed immediatly with an other Read
(or write) operation on the same register.
•Read (or write) operation on a SCIB register followed immediatly with an other Read
(or write) operation on a linked register. The list of linked registers is in the t able
below.
•Write operation on a register of the list below followed immediatly with a read
operation on a SCIB register.
To avoid any trouble, a dela y must be added between the two access es on the SCIB
register. The SCIB must complete the first read (or write) operation before to receive the
second. A solution is to add NOP (no operation) instructions. The number of NOP to add
depends of the rate between CK_CPU and CK_ISO (see table below).
CKS X2 FCK_CPU and FCK_IDLE
00F
CK_XTAL1/(2*(16-CKRL))
01F
CK_XTAL1
10F
CK_PLL/(2*(16-CKRL))
11Not allowed
Linked registers
Write in SCICR and after read of SCETU0-1
Write in SCTBUF and after read of SCISR
Wait after Write operation on this registers
SCICR, SCIER, SCETU0-1,SCGT0-1,
SCWT0-3,SCCON
min CLK_CPU max CLK_CPU Number of
CPU cycles to add
CLK_CPU >= 6 * CLK_ISO CLK_CPU <= 12 * CLK_ISO 6 ( example1 NOP)
CLK_CPU >= 12* CLK_ISO CLK_CPU <= 16 * CLK_ISO 12 ( example 2 NOP)
31
AT8xC5122/23
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Smart Card Interface Block The Smart Card Interface Block (SCIB) uses two clock trees:
–The first one, CK_IDLE, is the peripheral clock used for the interface with the
microcontroller.
–The second one, CK_ISO, is independant from the CPU clock and is
generated from the PLL output. PR2, a 6-bit pre scaler, will be used to
generate: 12/9.6/8/6.85/6/5.33/4.8/4.36/ ..../1MHz frequencies. SCIB clock
must be lower than CPU clock.
During SC I Reset, the CK_ISO input must be in the range 1 - 5 MHz according to ISO
7816. The SCIB clocks frequency is defined in Figure 27: Prescaler 2 Description and
Table 37 on page 43.
Alternate Card Clock The alternat e Card uses th e per ipheral clock d ivided b y the PR3 p rescal er. (1; 1/2; 1/ 4;
1/8 division ratio). See Section " Alternate Card", page 43 for the definition of the alter-
nate clock.
DC/DC Clock The DC/DC block needs a clock with a 50% duty cycle. The frequency must also respect
a value be tween 3.68 MHz and 6MHz . The PR4 presca ler is used to compl y with the
DC/DC frequency requirement.
Figure 13. Functional Block Diagram
Before supplying the DC/DC block, the oscillator clock is adapted to the clock needed by
the DC/DC converter. This factor is controlled with the DCCKPS3:0 register.
Examples of factors are shown in the following table:
XTA L1 (MHz) DCCKPS3:0 value Prescaler
Factor DC/DC converter CLK (MHz)
802 4
PR4 FCLK_DC/DC
FCK_XTAL1
DCCKPS3:0
32
AT8xC5122/23 4202B–SCR–07/03
USB Clock The USB Interface Block use two clock trees:
–The first one is the CPU clock used for the interface with the microcontroller ,
CK_IDLE.
–The second one is the USB clock, CK_USB. Since the USB frequency must
be
48 MHz, a 96 MHz PLL with a by 2 divider has to be used. An external
frequency can also be used.
Oscillator Two clock sources are available for CPU:
•Crystal oscillator on XTAL1 and XTAL2 pins: Up to 8 MHz
•External 48 MHz clock on XTAL1 pin
Figure 14. Crystal Connection
PLL
PLL Description The AT 8xC5122 PLL is used to generate internal high frequency clock synchronized
with an external low-frequency. Figure 15 shows the internal structure of the PLL.
The PFLD block is the Phase Frequency Compar ator and Lock Detector. This block
makes the comparison between the reference clock coming from the N divider and the
reverse clock coming from the R divider and generates some pulses on the Up or Down
signa l depend ing on the edge posi tion of th e reverse c lock. T he PLLEN bit in PLLC ON
regist er is used to enab le the cloc k gene ration. W hen the P LL is loc ked, th e bit PL OCK
in PLLCON register is set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by
injecting or extracting charges from the external filter connected on PLLF pin (see
Figure 16). Value of the filter components are detailed in the Section “DC
Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage VREF pro-
duced by the charge pump. It generates a square wave signal: the PLL clock.The
CK_PLL frequency is defined by the follwing formula:
FCK_PLL = FCK_XTAL1 * (R+1) / (N+1)
XTAL1
XTAL2
8 MHz
33
AT8xC5122/23
4202B–SCR–07/03
Figure 15. PLL Block Diagram and Symbol
Figure 16. PLL Filter Connection
PLL Programming The PLL is programmed VREF using the flow showed in Figure 17. As soon as clock gen-
eration is enabled, user must wait until the lock indicator is set to ensure the clock output
is stable.
Figure 17. PLL Programming Flow
PLLEN
PLLCON.1
N3:0
N Divider
R divider
VCO CK_PLL
CK_XTAL1 PFLD
PLOCK
PLLCON.0
PLLF
CHP VREF
Up
Down
R3:0
VSS
PLLF
VSS
PLL
Programming
Configure Dividers
N3:0= xxxxb
R3:0= xxxxb
Enable PLL
PLLEN= 1
PLL Locked?
PLOCK= 1?
34
AT8xC5122/23 4202B–SCR–07/03
Registers
Reset Val ue = XXXX XXX 0b
Reset Valu e = XXXX 1111b
Reset Val ue = XXXX XXX 0b
Table 31. Clock Selection Register - CKSEL (S:85h)
76543210
-------CKS
Bit Number Bit Mnemonic Description
7:1 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
0CKS
CPU Oscillator Select Bit
Set this bit to connect CPU and Peripherals to PLL output.
Clear this to to connect CPU and Peripherals to XTA L1 clock input.
Table 32. Clock Reload Register - CKRL (S:97h)
76543210
----CKRL3CKRL2CKRL1CKRL0
Bit Number Bit Mnemonic Description
7 - 4 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
3:0 CKRL3:0 Clock Reload register
Prescaler1 value
Fck_cpu =[ 1 / 2*(16-CKRL)] * Fck_XTAL1
Table 33. Clock Configuration Register 1 - CKCON1 (S:AFh) only for AT8xC5122
76543210
-------SPIX2
Bit Number Bit Mnemonic Description
7 - 4 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0SPIX2
SPI cloc k
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Cleared to bypass the PR1 prescaler .
Set to select the PR1 output for this peripheral.
35
AT8xC5122/23
4202B–SCR–07/03
Reset Valu e = X0X0 X00 0b
Table 34. Clock Configuration Register 0 - CKCON0 (S:8Fh)
76543210
- WDX2 - SIX2 - T1X2 T0X2 X2
Bit Number Bit Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6WDX2
Watchdog clock
This control bit is validated when t he CPU clock X2 is set; when X2 is low,
this bit has no effect.
Cleared to bypass the PR1 prescaler .
Set to select the PR1 output for this peripheral.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4SIX2
Enhanced UART clock (Mode 0 and 2)
This control bit is validated when t he CPU clock X2 is set; when X2 is low,
this bit has no effect.
Cleared to bypass the PR1 prescaler .
Set to select the PR1 output for this peripheral.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2T1X2
Timer 1 clock
This control bit is validated when t he CPU clock X2 is set; when X2 is low,
this bit has no effect.
Cleared to bypass the PR1 prescaler .
Set to select the PR1 output for this peripheral.
1T0X2
Timer 0 clock
This control bit is validated when t he CPU clock X2 is set; when X2 is low,
this bit has no effect.
Cleared to bypass the PR1 prescaler .
Set to select the PR1 output for this peripheral.
0X2
System clock Control bit
Cleared to select the PR1 output for CPU and all the peripherals .
Set to bypass the PR1 prescaler and to enable the i ndividual peripherals ‘X2’
bits.
36
AT8xC5122/23 4202B–SCR–07/03
Reset Value = 0000 0000b
Reset Value = 0000 0000b
Table 35. PLL Control Register - PLLCON (S:A3h)
76543210
-----EXT48PLLEN PLOCK
Bit Number Bit Mnemonic Description
7 - 3 - Reserved
The value read from these bits is always 0. Do not set this bits.
2EXT48
External 48 MHz Enable Bit
Set this b it to sele c t XTAL1 as USB clock.
Clear this bit to select PLL as USB clock.
SCIB clock is controlled by EXT48 bit and XTSCS bit.
1PLLEN
PLL Enab le bit
Set to enable the PLL.
Clear to disable the PLL.
0PLOCK
PLL Lock Indicator
Set by hardware when PLL is locked
Clear by hardware when PLL is unlocked
Table 36. PLL Divider Register - PLLDIV (S:A4h)
76543210
R3 R2 R1 R0 N3 N2 N1 N0
Bit Number Bit Mnemonic Description
7 - 4 R3:0 PLL R Divider Bits
3 - 0 N3:0 PLL N Divider Bits
37
AT8xC5122/23
4202B–SCR–07/03
Smart Card Interface
Block (SCIB) The SCI B provides al l signals to i nterface dir ectly wit h a smart card. T he complia nce
with the ISO7816, EMV’2000, GSM and WHQL sta nda rd s has been certi fie d.
Both synchronous (e.g. memory card) and asynchronous smart cards (e.g. micropro-
cessor card) are supported. The component supplies the different voltages requested by
the smart card. The power off sequence is directly managed by the SCIB.
The card presence switch of the smart card connector is used to detect card insertion or
card removal. I n case of card remo val, the SCIB de-activates the smart card using the
de-activation sequence. An interrupt can be generated when a card is inserted or
removed.
Any malfunction is reported to the microcontroller (interrupt + control register).
The different operating modes are configured by internal registers.
•Support of ISO/IEC 7816
•character mode
•one transmit buffer + one receive buffer
•11 bits ETU counter
•9 bits guard time counter
•32 bi ts waiting time counter
•Auto character repetition on error signal detection in transmit mode
•Auto error signal generation on parity error detection in receive mode
•Power on and power off sequence generation
•Manual mode to drive directly the card I/O
38
AT8xC5122/23 4202B–SCR–07/03
Block Diagram
The Smart Card Interface Block diagram is shown Figure 18:
Figure 18. SCIB Block Diagram
Functional Description The architecture of the Smart Card Interface Block can be detailed as follows:
Barrel Shifter The Barrel Shifter allows the translation between 1 bit serial data and 8 bits parallel data
The barrel function is useful for character repetition since the character is still present in
the shifter at the end of the character transmission.
This sh ifter is able to shift the data in both di rectio ns and to invert the inp ut or outp ut
value in order to manage both direct and inverse ISO7816-3 convention.
Coupled with the barrel shifter there is a parity checker and generator.
There are 2 registers connected to this barrel shifter, one for the transmission and one
for the reception. They act as buffers to relieve the CPU of timing constraints.
B arre l sh ifter
SCI Registers
Scart
fsm
Interrupt generator Power on
Power off
fsm
I/O
mux
IO ( in)
IO ( o u t)
CLK
RST
C4 (out)
Clk_iso
C8 (out)
CLK1
C4 (in)
C8 (in)
W aiting time counter
Guard time counter
VCARD
INT
Clk_cpu Etu counter
39
AT8xC5122/23
4202B–SCR–07/03
SCART FSM (Smart Card Asynchronous Receiver Transmitter Finite State Machine)
This is the co re of the design. Its purpose is to control the barrel shifter. To sequenc e
corr ec t ly t he ba r r el shi f ter fo r a re ce ption or a tran sm is si on , it us es th e si gn a ls issu e d by
the different counters. One of the most important counters is the guard time counter that
gives time slots corresponding to the character frame.
The SCART FSM is enabled only in UART mode.
The transition from the receipt mode to the transmit mode is done automatically. Priority
is given to the transmission.
ETU Counter The ETU (E lemen tary Tim ing Un it) cou nter contr ols the working freq uency of the ba rre l
shifter, in fact it generates the enable signal of the barrel shifter.
The ETU is 11 bits wide and there is a speci al compensation mode activated wi th the
most s ignifican t bit that al lows non i nteger ETU value wi th a workin g clock equ al to the
card cl ock ( CK_ ISO ) . But the dec im al value is li mi ted to a ha lf cl oc k cyc le. In fac t the bi t
duration is not fixed. It takes turns in n clock cycles and n-1 clock cycles.T he character
duration (10 bits) is also equal to 10*(n + 1/2) clock cycles.
This allows to reach the required precision of the character duration specified by the
ISO7816 standard.
example : F=372 D=3 2 => ETU= 11. 625 cl oc k cy cl es.
ETU = (ETU[10-0] -0.5 * COMP) / f iso with ETU[10-0] = 12, COMP = 1 (bit 7 of
SCETU1)
To achieve this clock rate, we activated the compensation mode and we programmed
the ETU duration to 12 clock cycles.
The result will be a full character duration (10 bits) equal to 11.5 clock cycles.
Guard Time and Block Guard
Time Counters The minimum time between the leading edge of the start bit of a character and the lead-
ing edg e o f the start bit o f th e follo win g char acter t rans mitted (Gua rd time ) is co ntrolle d
by one counter, as described in Figure 19.
The min imu m time b etween the le adi ng edge of th e s tar t bit of the last re ce iv ed cha ra c-
ter and the first character transmitted (Block guard time) is controlled by another
counter. The bit BGTEN in SCS R register must b e set to use this functionality. The
transfe r of GT[8 -0] value to the BG T counte r is done on th e rising ed ge of the B GTEN.
They are 9 bits wide and are incremented at the ETU rate.
Figure 19. Guard Time and Block Guard Time.
CHAR 1 CHAR 2 CHAR n CHAR n+1 CH A R n+2 CHAR n+3
< Block Guard Time < Guard
RECEPTION TRANSMISSION
Time
Write “Block Guard Time” in GT
Write “Guard Time” in GT
40
AT8xC5122/23 4202B–SCR–07/03
Figure 20. Guard Time and Block Guard Time counters
Waiting Time (WT) Counter The WT counter is a 32 bits down counter which can be loaded with the value contained
in the SCWT3, SCWT2, SCW T1, SCWT0 regis ters. Its main purpose is timeout signal
generation. It is 32 bits wide and is decremented at the ETU rate. The ETU counter acts
as a prescaler: see Figure 21.
When the WT counter times out, an interrupt is g enerated and the SCIB funct ion is
locked: reception and emission are disabled. It can be enabled by resetting the macro or
reloadi ng the cou nte r.
Figure 21. Waiting Time Counter
The counter is loaded, if WTEN = 0, during the write of SCWT2 register.
This counter is available in both UART and manual modes. But the behavior depends
on the selected mode.
In manual mode, the WTEN signal controls the start of the counter (rising edge) and the
stop of the counter (falling edge). After a timeout of the counter, a falling edge on
WTEN, a rel oa d of S CW T2 and a r ising edg e of W T EN are neces s ary to sta rt again th e
counter and to release the SCIB macro. The reload of SCWT2 transfers all SCWT0,
SCWT1, SCWT2 and SCWT3 registers to the WT counter.
In UART mode ther e is an automatic load on the star t bit detection. This automati c load
is very useful for changing on-the-fly the timeout value since there is a register to hold
the load v alu e. Th at is th e cas e, for e xa mpl e when i n T = 1 we have to la unc h the BW T
timeout on the star t bit of t he last t ransmitted c haracter. But on the receipt of the first
character an other timeout value (CWT) must be used. For this, the new load value of
the waitin g time c ounter must be load ed with C WT val ue before t he tran smis sion of th e
last character. The reload of SCWT[3-0] with the new value occurs with WTEN = 1.
After a timeout of the counter in UART mode, the restart is done as in manual mode.
The max imum i nter v al bet ween the s tart leadin g e dge of a charact er an d t he s ta rt le ad-
ing edge of the next character is loaded in the SCWT3, SCWT2, SCWT1, SCWT0
registers (see Figure 21).
ETU Counter Block Guard Time Counter Timeout
SCGT1 SCGT0
GT[8:0]
Guard Time Counter Timeout
ETU Counter WT Counter Timeout
SCWT2 SCWT1 SCWT0
WT[31:0]
Load
WTEN
Start Bit
UART
Write_SCWT2
SCWT3
41
AT8xC5122/23
4202B–SCR–07/03
In T=1 mode, the CWT (character waiting time) or the BWT (block waiting time) are
loaded in the same registers.
The maximum time between two consecutive start bit is WT[31:0] * ETU.
When used to check BWT according to ISO 7816 , WT can be set between 971 and
15728651.
The WT coun ter is 32 bits wide in order to handl e the BWT extensi on. In this case, WT
must be loaded with the value BWT * WTX.
Figure 22. T=0 mode
Figure 23. T=1 Mode
Power-on and Power-off FSM In this state, th e machin e applie s the sig nals on the smar t card in accord ance with
ISO7816 standard.
To be able to power on the SCIB, the card presence is mandatory. Removal of the smart
card will automatically start the power off sequence as described in Figure 24.
The SCI deactivation sequence after a reset of the CPU or after a lost of power supply is
ISO7816 compliant. The switching order of the signals is the same as in Figure 24 but
the delay between signals is analog and not clock dependant.
CHAR 1 CHAR 2
< WT
> GT
BLOC 1
CHAR 1 CHAR 2 CHAR n
BLOC 2
CHAR n+1 CHA R n+2 CHAR n+3
< CWT < BWT < CWT
TRANSMISSION RECEPTION
42
AT8xC5122/23 4202B–SCR–07/03
Figure 24. SCI Deactivation Sequence after a Card Extraction
Interrupt Generator There are s ev er al so ur ce s o f in ter rupti on but the S CIB ma cr o- cel l i ssu e s o nly o ne i nte r-
rupt signa l: SCIB IT.
Figure 25. SCIB Interrupt Sources
This signal is high level active. One of the sources is able to set up the INT signal and
this is the read of the Smart Card Interrupt register by the CPU that clears this signal.
If during the read of the Smart Card Int errupt regis ter an interrupt oc curs, the set of the
corresponding bit into the Smart Card Interrupt register and the set of the INT signal will
be delayed after the read access.
Registers There are fifteen registers to control the SCIB macro-cell. They are described in Table
54 to Table 45.
Some of the reg ister widths are greater than a byte. Des pite the 8 bits acce ss provide d
by the BIU, the address mapping of this kind of register respects the following rule:
The Low significant byte register is implemented at the higher address.
This imple mentation mak es access to these regi sters easie r when using high level pro-
gramming language (C,C++).
CVCC
CRST
CCLK
CIO
8 Clock C ycles
ESCTBI
ICARDER
ESCWTI
ESCRI
ESCPI
EVCARDER
Transmit buffer
copied to shift register
Output current
out of range
Output voltage
out of range
Timeout on WT
counter
Complete
transmission
Complete
reception
Parity error
detected
SCIB IT
ESCTI
43
AT8xC5122/23
4202B–SCR–07/03
Additional Features
Clock The CK_ISO input must be in the range 1 - 5 MHz according to ISO 7816.
The CK_ ISO can be programme d u p to 12 MHz . In th is cas e, t he timing spec if ic ati on of
the output buffer will not comply to ISO 7816.
Figure 26. Clock Diagram of the SCIB Block
Figure 27. Prescaler 2 Description
The division factor SCICLK must be smaller than 49. If it is greater or equal to 49, the
PR2 prescaler is locked.
Table 37. Examples of Settings Ffor Clocks
Alternate Card A second card named ‘Alternate Card’ can be controlled.
XTAL1 (MHz) EXT48 S CICLK CK_ ISO
48 1 42 4
80 36 4
8 0 44 12
80 42 8
80 40 6
80 24 2
80 0 1
PR2
Ck_cpu
Ck_ISO
SCIB
FCK_PLL or
FCK_IDLE
FCK_XTAL1
PR2
/ (2 * (48 - SCICLK[5-0])) CK_ISO
EXT48
PLLCON.2
0
1
CK_PLL
CK_XTAL1
XTSCS
SCCLK.7
SCICLK.[5:0]
=48
0
1
44
AT8xC5122/23 4202B–SCR–07/03
The Clock signal CCLK 1 can be adapted to the XTAL frequency . Thank s to the clock
prescaler which can divide the frequency by 1, 2, 4 or 8. The bits ALTKPS0 and
ALTKPS1 in SCSR Register are used to set this factor.
Figure 28. Alternate Card
Card Presence Input The internal pull-up (weak pull-up) on Card Presence input can be disconnected in order
to reduce the consumption (CPRESRES, bit 3 in PMOD0).
In this case, an external resistor (typically 1 M
Ω
) must be externally tied to Vcc.
CPRES input can generate an interrupt (see Interrupt system section).
The detection level can be selected.
SCIB Reset The SCICR r egist er conta ins a r eset bit. If set, this bit gener ates a r eset of the SCI an d
its registers. Table 38 defines the SCIB registers that are reset and their reset values.
Table 38. Reset Values for SCI Registers
SIM, SAM
CARD
Alternate
card
CVCC
CRST
CIO
CCLK
FCK_IDLE 1
0CCLK1
SCSR Reg.
PR3
SCCLK1
1, 1/2, 1/4 or 1/8
P1.7
Main
card
CPRES
SMART
CARD
SCSR Reg.
ALTKPS0,1
Register Name SCIB Reset Value (Binary)
SCICR 0000 0000
SCCON 0X00 0000
SCISR 1000 0000
SCIIR 0X00 0000
SCIER 0X00 0000
SCSR X000 1000
SCTBUF 0000 0000
SCRBUF 0000 0000
SCETU1, SCETU0 XXXX X001, 0111 0100 (372)
SCGT1, SCGT0 0000 0000, 0000 1100 (12)
SCWT3, SCWT2, SCWT1, SCWT0 0000 0000, 0000 0000, 0010 0101, 1000 0000 (9600)
SCICLK 0X10 1111
45
AT8xC5122/23
4202B–SCR–07/03
Registers
Reset Value = 0000 0000b
Table 39. Smart Card Interface Control Register - SCICR (S:B6h, SCRS = 1)
76543210
RESET CARDDET VCARD1 VCARD0 UART WTEN CREP CONV
Bit
Number Bit
Mnemonic Description
7 RESET
Reset
Set this bit to reset and deactivate the Smart Card Interface.
Clear this bit to activate the Smart Card Interface.
This bit acts as an ac tive high software reset.
6 CARDDET
Card Presence Detector Sense
Clear this bit to indicate the card presence detector is open when no card is
inserted (CPRES is high).
Set this bit to indicate the card presence detector is closed when no card is
inserted (CPRES is low).
5-4 VCARD[1:0]
Card Volt age Selection:
VCARD[1] VCARD[0] CVCC
0 0 0.0V
0 1 1.8V
1 03.0V
1 1 5.0V
3UART
Card UART Selection
Clear this bit to use the Card I/O bit to drive the Card I/O pin.
Set this bit to use the Smart Card UART to drive the Card I/O pin.
Controls also the Wait Ti me Counter as described in Section “Waiting Time
(WT) Counter”, page 40
2WTEN
Wait Time counter Enable
Clear this bit to stop the counter and enable the load of the W ait Time counter
hold registers.
The hold registers are loaded with SCWT0, SCWT1, SCWT2 and SCWT3
values when SCWT2 is written.
Set this bit to start the Wait Time counter. The counters stop when it reaches
the timeout value.
If the UART bit i s set, the Wait Ti me counter automatically reloads with the hold
registers whenever a start bit is sent or received.
1 CREP
Character Repetition
Clear this bit to disable parity error detection and indication on the Card I/O pin
in receive mode and to disable character repetition in transmit mode.
Set this bit to enable parity error indication on the Card I/O pin in receive mode
and to set automatic character repetition when a parity error is ind icated in
transmit mode. In receive mode, three times error indication is performed and
the parity error flag is set after four times parity error detection. In transmit
mode, up to three times character repetition is allowed and the parity error flag
is set aft er five times (reset configuration, can be set at 4 using CREPSET bit
in SCSR Register) consecutive parity error indication.
0CONV
ISO Conventio n
Clear this bit to use the direct convention: b0 bit (LSB) is sent first, the parity bit
is added after b7 bit and a low level on the Card I/O pin represents a’0’.
Set this bit to use the inverse convention: b7 bit (LSB) is sent first, the p arity bit
is added after b0 bit and a low level on the Card I/O pin represents a’1’.
46
AT8xC5122/23 4202B–SCR–07/03
Reset Value = 0X00 0000b
Table 40. Smart Card Contacts Register - SCCON (S:ACh, SCRS=0)
76543210
CLK - CARDC8 CARDC4 CARDIO CARDCLK CARDRST CARDVCC
Bit
Number Bit
Mnemonic Description
7CLK
Card Clock Selection
Clear this bit to use the Card CLK bit (CARDCLK) to drive Card CLK pin.
Set this bit to use XTAL or PLL signal to drive the Card CLK pin.
Note: internal synchronization avoids glitches on the CLK pin when switching
this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
5 CARDC8
Card C8
Clear this bit to drive a low level on the Card C8 pin.
Set this bit to set a high level on the Card C8 pin.
The CC8 pin can be used as a pseudo bi-directional I/O when this bit is set.
4 CARDC4
Card C4
Clear this bit to drive a low level on the Card C4 pin.
Set this bit to set a high level on the Card C4 pin.
The CC4 pin can be used as a pseudo bi-directional I/O when this bit is set.
3 CARDIO
Card I/O
When the UART bit is cleared in Registers, the value of this bit is driven to the
Card I/O pin.
Then this pin can be used as a pseudo bi-directional I/O when this bit is set.
To be used as an input, this bit must contain a 1.
2 CARDCLK Ca rd CLK
When the CLK bit is cleared in SCCON Register, the value of this bit is dr iven
to the Card CLK pin.
1 CARDRST Card RST
Clear this bit to drive a low level on the Card RST pin.
Set this bit to set a high level on the Card RST pin.
0 CARDVCC
Card VCC Control
Clear this bit to desactivate the Card interface and set its power-off. The other
bits of SCCON register have no effect while t his bit is cleared.
Set this bit to power-on the Card interface. The activation sequence should be
handled by software.
47
AT8xC5122/23
4202B–SCR–07/03
Reset Value = 1000 0000b
Table 41. Smart Card UART Interface Status Register -
SCISR (S:ADh, SCRS=0)
765 43210
SCTBE CARDIN ICARDOVF VCARDOK SCWTO SCTC SCRC SCPE
Bit
Number Bit
Mnemonic Description
7SCTBE
SCIB Transmi t Buffer Empt y
This bit is set by hardware when the Transmit Buffer is copied to the transmit shift
register of the Smart Card UART.
It is cleared by hardware when SCTBUF register is written.
6 CARDIN
Card Presence Statu s
This bit is set by hardware if there is a card presence (debouncing filter has to be
done by software).
This bit is cleared by hardware if there is no card presence.
5 ICARDOVF
ICC Overflow on card
This bit is set when the current on card is above the limit specified by bit OVF ADJ
in DCCKPS register (Table 56 on page 56)
It is cleared by hardware.
4 VCARDOK
Card Vo ltage Status
This bit is set when the output voltage is within the voltage range specified by
VCARD field.
It is cleared otherwise.
3SCWTO
Smart Card Wait Timeout
This bit is set by hardware when the Smart Card Waiting Time Counter expires.
It is cleared by the reload of the counter or by the reset of the SCIB.
2SCTC
Smart Card Transmitted Character
This bit is set by hardware when the Smart Card UART has transmitted a
character.
It shall be cleared by software after this register is read.
1 SCRC Smart Card Received Character
This bit is set by hardware when the Smart Card UART has r e ceived a character
It is cleared by hardware when SCBUF register is read.
0SCPE
Smart Card Parity Error
This bit is set at the same time as SCTI or SCRI if a parity error is detected.
It shall be cleared by software after this register is read.
48
AT8xC5122/23 4202B–SCR–07/03
Reset Value = 0X00 0000b
Table 42. Smart Card UART Interrupt Identification Register (Read Only)
SCIIR (S:AEh, SCRS=0)
765 4 3210
SCTBI - ICARDERR VCARDERR SCWTI SCTI SCRI SCPI
Bit
Number Bit Mnemon ic Description
7SCTBI
SCIB T ransmit Buffer Interrupt
This bit is set by hardware when the Transmit Buffer is copied to the transmit
shift register of the Smart Card UART.
It is cleared by hardware when this register is read.
6-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
5 ICARDERR Card Current Statu s
This bit is set when the output current goes out of the current range.
It is cleared by hardware when this register is read.
4 VCARDERR
Card Voltage Status
This bit is set when t he output volt age goes out of the volt age range specified
by VCARD field.
It is cleared by hardware when this register is read.
3SCWTI
Smart Card Wa it Timeout Interrupt
This bit is set by hardware when the Smart Card Timer times out.
It is cleared by hardware when this register is read.
2SCTI
Smart Card Transmit Interrupt
This bit is set by hardware when the Smart Card UART completes a
character transmiss ion.
It is cleared by hardware when this register is read.
1 SCRI
Smart Card Receive Interrupt
This bit is set by hardware when the Smart Card UART completes a
character reception.
It is cleared by hardware when this register is read.
0SCPI
Smart Card Parity Error Interrupt
This bit is set at the same time as SCTI or SCRI if a parity er ror is detected.
It is cleared by hardware when this register is read.
49
AT8xC5122/23
4202B–SCR–07/03
Reset Value = 0X00 0000b
Table 43. Smart Card UART Interrupt Enable Register - SCIER (S:AEh, SCRS=1)
765 4 3210
ESCTBI - ICARDER EVCARDER ESCWTI ESCTI ESCRI ESCPI
Bit Number Bit
Mnemonic Description
7ESCTBI
Smart Card UART Transmit Buffer Empty Interrupt Enable
Clear this bit to disable the Smart Card UART Transmit Buffer Empty interrupt.
Set this bit to enable the Smart Card UART Transmit Buffer Empty interrupt.
6-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
5 ICARDER Card Current Error Interrupt Enable
Clear this bit to disable the Card Current Error interrupt.
Set this bit to enable the Card Current Error interrupt.
4 EVCARDER Card Voltage Error Interrupt Enable
Clear this bit to disable the Card Voltage Error interrupt.
Set this bit to enable the Card Voltage Error interrupt.
3ESCWTI
Smart Card Wait Timeout Interrupt Enable
Clear this bit to disable the Smart Card Wait timeout interrupt.
Set this bit to enable the Smart Card Wait timeout interrupt.
2ESCTI
Smart Card Transmit Interrupt Enable
Clear this bit to disable the Smart Card UART Transmit interrupt.
Set this bit to enable the Smart Card UART Transmit interrupt.
1 ESCRI Smart Card Receive Interrupt Enable
Clear this bit to disable the Smart Card UART Receive interrupt.
Set this bit to enable the Smart Card UART Receive interr upt.
0ESCPI
Smart Card Parity Error Interrupt Enable
Clear this bit to disable the Smart Card UART Parity Error interrupt.
Set this bit to enable the Smart Card UART Parit y Error interrupt.
50
AT8xC5122/23 4202B–SCR–07/03
Reset Value = X000 1000b
Reset Value = 0000 0000b
Table 44. Smart Card Selection Register - SCSR (S:ABh)
76543210
- BGTEN - CREPSEL ALTKPS1 ALTKPS0 SCCLK1 SCRS
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
6BGTEN
Block Gua r d Tim e En a b le
Set this bit to select the minimum interval between the leading edge of the start
bits of the last received character and the first character sent in the opposite
direction. The transfer of GT[8-0] value to the BGT counter is done on the rising
edge of the BGTEN.
Clear this bit to suppress the minimum time between reception and
transmission.
5-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
4 CREPSEL Character repetition selection
Clear this bit to select 5 times repetition before parity error indication
Set this bit to select 4 times repetition before parity error indication
3-2 ALTKPS1:0
Alternate Card Clock prescaler factor
00 ALTKPS = 0: prescaler factor equals 1
01 ALTKPS = 1: prescaler factor equals 2
10 ALTKPS = 2: prescaler factor equals 4 (reset value)
11 A LTKPS = 3: prescaler factor equals 8
1 SCCLK1 Alternate card clock selection
Set to select the prescaled clock (CCLK1)
Clear to select the standard port configuration
0 SCRS Smart Card Register Selection
The SCRS bit selects which set of the SCIB registers is accessed.
Table 45. Smart Card Transmit Buffer Register - SCTBUF (S:AA, write-only, SCRS=0)
76543210
--------
Bit
Number Bit
Mnemonic Description
--
Can store a new byte to be transmitted on the I/O pin when SCTBE is set.
Bit ordering on the I/O pin depends on the Convention.
51
AT8xC5122/23
4202B–SCR–07/03
Reset Value = 0000 0000b
Reset Value = 0XXX X0 01b
Reset Value = 0111 0100b
Table 46. Smart Card Receive Buffer Register - SCRBUF (S:AA read-only, SCRS=1)
76543210
--------
Bit
Number Bit
Mnemonic Description
--
Provides the byte received from the I/O pin when SCRI is set.
Bit ordering on the I/O pin depends on the Convention.
Table 47. Smart Card ETU Register 1 - SCETU1 (S:ADh, SCRS=1)
76543210
COMP - - - - ETU10 ETU9 ETU8
Bit
Number Bit
Mnemonic Description
7COMP
Compensation
Clear this bit when no t ime com pensatio n is needed (i.e. when the ETU to Card
CLK period ratio is close to an int eger with an error less than 1/4 of Card CLK
period).
Set this bit otherwise and reduce the ETU period by 1 Card CLK cycle for even
bits.
6-3 - Reserved
The value read from these bits is indeterminate. Do not change these bits.
2-0 ETU[10:8] ETU MSB
Used together with the ETU LSB in SCETU0 (Table 48)
Table 48. Smart Card ETU Register 0 - SCETU0 (S:ACh, SCRS=1)
76543210
ETU7 ETU6 ETU5 ETU4 ETU3 ETU2 ETU1 ETU0
Bit
Number Bit
Mnemonic Description
7 - 0 ET U[7:0]
ETU LSB
The Elementary T ime Unit i s (ETU[10:0] - 0.5*COMP)/f, where f is the Card CLK
frequency.
According to ISO 7816, ETU[10:0] can be set between 11 and 2047.
The default reset value of ETU[10:0] is 372 ( F=372, D=1).
52
AT8xC5122/23 4202B–SCR–07/03
Reset Value = 0000 1100b
Reset Val ue = XXXX XXX 0b
Reset Value = 0000 0000b
Table 49. Smart Card Transmit Guard Time Register 0 - SCGT0 (S:B4h, SCRS=1)
76543210
GT7 GT6 GT5 GT4 GT3 GT2 GT1 GT0
Bit
Number Bit
Mnemonic Description
7 - 0 GT[7:0]
Transmit Guard Time LSB
The minimum time between two consecutive start bits in transmit mode is
GT[8:0] * E T U .
According to ISO 7816, GT can be set between 11 and 266 (11 to 254+12 ETU).
Table 50. Smart Card Transmit Guard Time Register 1 - SCGT1 (S:B5h, SCRS=1)
76543210
-------GT8
Bit
Number Bit
Mnemonic Description
7 - 1 - Reserved
The value read from these bits is indeterminate. Do not change these bits.
0GT8
Transmit Guard Time MSB
Used together with the Transmit Guard Time LSB in SCGT0 register (Table 49).
Table 51. Smart Card Character/Block Wait Time Register 3
SCWT3 (S:C1h , SCRS= 0)
76543210
WT31 WT30 WT29 WT28 WT27 WT26 WT25 WT24
Bit
Number Bit
Mnemonic Description
7 - 0 WT[31:24] Wait Ti me Byte3
Used together with WT[23:0] in registers SCWT2,SCWT1, SCWT0 (see Table
52).
53
AT8xC5122/23
4202B–SCR–07/03
Reset Value = 0000 0000b
Reset Value = 0010 0101b
Reset Value = 1000 0000b
Table 52. Smart Card Character/Block Wait Time Register 2
SCWT2 (S:B 6h, SCRS =0)
76543210
WT23 WT22 WT21 WT20 WT19 WT18 WT17 WT16
Bit
Number Bit
Mnemonic Description
7 - 0 WT[23:16] Wait Ti me Byte2
Used together with WT[31:24] and WT[15:0] in registers SCWT3,SCWT1,
SCWT0 (see Table 54).
Table 53. Smart Card Character/Block Wait Time Register 1
SCWT1 (S:B 5h, SCRS =0)
76543210
WT15 WT14 WT13 WT12 WT11 WT10 WT9 WT8
Bit
Number Bit
Mnemonic Description
7 - 0 WT[15:8] Wait Time Byte 1
Used together with WT[31:16] and WT[7:0] in registers SCWT3,SCWT2, SCWT0
(see Table 51).
Table 54. Smart Card Character/Block Wait Time Register 0
SCWT0 (S:B 4h, SCRS =0)
76543210
WT7 WT6 WT5 WT4 WT3 WT2 WT1 WT0
Bit
Number Bit
Mnemonic Description
7 - 0 WT[7:0]
Wait Time Byte 0
WT[31:0] is the reload value of t he Wait Time counter WTC.
The WTC is a general-purpose timer. It is using the ETU clock and is controlled
by the WTEN bit (see Table 39 on page 45 and Section “Waiting T ime (WT)
Counter”, page 40).
When UART bit of Registers is set, the WTC is automatically reloaded at each
start bit of t he UART. It is used to check the maximum time between to
consecutive start bits.
54
AT8xC5122/23 4202B–SCR–07/03
Reset Value = 0X10 1111b (default value for a divider by two)
DC/DC Converter The Smart Card voltage (CVCC) is supplied by the integrated DC/DC converter which is
controlled by several registers:
•The SCIIR register (Table 42 on page 48) controls the CVCC level by means of bits
VCARD[1:0].
•The SCCON register (Table 40 on page 46) enables to switch the DC/DC converter
on or of f by means of bit CARDVCC.
•The DCCKPS register (Table 56 on page 56) controls the DC/DC clock and current.
The DC/DC converter cannot be switched on wh ile the CPRES pin remains inactive. If
CPRES pin becomes inactive while the DC/DC converter is operating an automatic shut
down sequence of the DC/DC converter is initiated by the electronics.
It is mandatory to switch off the DC/DC Converter before entering in Power-down mode.
Configuration The DC/DC Converter can work in two different modes which are selected by bit Mode
in DCCKPS register:
•Pump Mode: an external inductance of 10 µH must be connected between pins LI
and VCC. VCC can be higher or lower than CVCC.
•Regulator mode: no external inductance is required but VCC must be always higher
than CVCC.
The DC/DC clock prescaler which is controlled by bits DCCKPS[3:0], in DCCKPS regis-
ter must be configured to set the DC/DC clock to a working frequency of 4 MHz which
depends on the value of the quartz. There is no need to change the default configuration
set by the reset sequence if an 8 MHz quartz is used by the application.
The DC/DC Converter implements a current overflow controller which avoids permanent
damage of the DC/DC conv erter in cas e of sh or t cir cuit be tween C VCC and CV SS . The
maximum limit i s around 100 mA. It is pos sible to in crea se this limit in norma l operatin g
Table 55. Smart Card Clock Reload Register - SCICLK (S:C1h, SCRS=1)
76543210
XTSCS - SCICLK5 SCICLK4 SCICLK3 SCICLK2 SCICLK1 SCICLK0
Bit Number Bit
Mnemonic Description
7XTSCS
Smart Card Clock Selection Bit
If XTSC S bit is set, XTAL1 is SCIB clock.
If XTSCS bit is cleared and EXT48 bit is set , XTA L1 is SCIB clock.
If XTSCS bit is cleared and EXT48 bit is reset, PLL is SCIB clock.
6-
Reserved
The value read from this bit is indeterminate. Do not change these bits.
5 - 0 SCICLK5:0
SCIB clock reload register
Prescaler 2 reload value is used to defines the card clock frequency.
If SCICLK5:0 is smaller than 48
Fck_iso = Fck_pll or Fck_XTAL1/ (2 * (48 - SCICLK5:0))
If SCICLK5:0 is equal to 48
Fck_iso = Fck_XTAL1 or Fck_XTAL1
SCICLK5:0 must be smaller than 49.
55
AT8xC5122/23
4202B–SCR–07/03
mode by 20% by means of bit OVFADJ in DCCKPS register. When the current overflow
controller is operating, the ICARDOVF is set by the hardware in SCISR register.
The current drawn from power supply by the DC/DC converter is controlled during the
startup phase i n o rd er to a vo id h igh trans ie nt c urr ent mai nly i n P ump Mod e whi ch c oul d
cause the power supply voltage to drop dramatically. This control is done by means of
bits BOOST[1:0] , which increases progressively the startup current level.
Initialization Procedure The initialization procedure is described in flow chart of Figure 29.
•Select the CVCC level by means of bits VCARD[1:0] in SCIIR register,
•Set bits BOOST[1:0] in DCCKPS register following the current level control wanted.
•Switch the DC/DC on by means of bit CARDVCC in SCCON register,
•Monitor bit VCARDOK in SCISR register in order to know when the DC/DC
Converter is ready (CVCC voltage has reached the expected level)
Figure 29. DC/DC Conver ter Initi al izati on Proc edu re
While VCC r emains hi gher than 3.6V and sta rtup cur rent lower than 30 mA (dependin g
on the l oad type ), the DC/D C conver ter shoul d be ready w ithout ha ving to i ncremen t
BOOST[1:0]=[0:0]
VCARDOK=1
Set Timeout to 3 ms
Timeout
Expired
Increment
BOOST [1:0]
BOOST[1:0] is
at Maximum?
DC/DC Converter
Initializ ation Failure
END
END
Decrement
BOOST[1:0]
to adjust the
current overflow
56
AT8xC5122/23 4202B–SCR–07/03
BOOST[1:0] bits beyond [0:0] level. If at least one of the two conditions are not met
(VCC < 3.6V or startup current > 30 mA), it will be necessary to increment the
BOOST[1:0] bits until the DC/DC converter is ready.
Incrementation of BOOST[1:0] bits increases at the same time the current overflow level
in the same proportion as the startup current. So once the DC/D C converter is ready it
advised to decrement the BOOST[1:0] bits to restore the overflow current to its normal
or desired value.
Reset Value = 0000 0000b
Table 56. DC/DC Converter Control Register - DCCKPS (S:BFh)
76543210
MODE OVFADJ BOOST1 BOOST0 DCCKPS3 DCCKPS2 DCCKPS1 DCCKPS0
Bit
Number Bit Mnemonic Description
7MODE
Regulation mode
0 DC/DC converter (External Inductance required)
1 Voltage Regulator (No External inductance required but VCC >
CVCC+0.3V)
6OVFADJ
Current Overflow Adjustment on Smart Card terminal
0 normal: 100 mA average
1 normal + 20%
5 - 4 BOO ST[1:0]
Maximum Start up Cur r e nt dr a wn
from power supply
00 Normal: 30 mA average
01 Normal + 10%
10 Normal + 30%
11 Normal + 60%
Current Overflow Level on Smart
Card terminal
00 Normal = OVF ADJ
01 Normal + 10%
10 Normal + 30%
11 Normal + 60%
3 - 0 D CCKP S[3:0]
DC/DC Clock Prescaler Value
0000 Division factor: 2 (reset value)
0001 Division factor: 3
0010 Division factor: 4
0011 Division factor: 5
0100 Division factor: 6
0101 Division factor: 8
0110 Division factor: 10
0111 Division factor: 12
1000 Division factor: 24
Other values reserved
57
AT8xC5122/23
4202B–SCR–07/03
USB Controller The AT8x C5122 i mplem ents a USB de vic e contro ller suppo rting Full S peed da ta tran s-
fer. In addition to the default control endpoint 0, it provides 6 other endpoints, which can
be configured in Control, Bulk, Interrupt or Isochronous modes:
• Endpoint 0: 32-byte FIFO, default control endpoint
• Endpoint 1,2,3: 8-byte FIFO
• Endpoint 4,5: 64-byte FIFO
• Endpoint 6: 2 x 64-byte Ping-pong FIFO
This allows the firmware to be developed conforming to most USB device classes , for
example:
•USB Mass Storage Class Control/Bulk/Interrupt (CBI) Transport, Revision 1.0 -
December 14, 1998.
•USB Mass Storage Class Bulk-Only Transport, Revision 1.0 - September 31, 1999.
•USB Human Interface Device Class, Version 1.1 - April 7, 1999.
•USB Device Firmware Upgrade Class, Revision 1.0 - May 13, 1999.
USB Mass Storage Classes
USB Mass Storage Class CBI
Transport Within the CBI framework, the Control endpoint is used to transport command blocks as
well as to tran sp or t s tan dard USB r e ques ts. On e B ul k-O ut end point is u sed t o tra nsp or t
data from the host to the device. One Bulk-In endpoint is used to transport data from the
device to the host. And one interrupt endpoint may also be used to signal command
completion (protocol 0); it is optional and may not be used (protocol 1).
The following configuration adheres to these requirements:
•Endpoint 0: 8 bytes, Control In-Out
•Endpoint 4: 64 bytes, Bulk-Out
•Endpoint 5: 64 bytes, Bulk-In
•Endpoint 1: 8 bytes, Interrupt In
USB Mass Storage Class Bulk-
Only Transport Within the B ulk-Only fram ework, the Control endp oint is only used to tr ansport class-
spec ific an d stan dard USB requ ests for de vice s et-up an d conf igur ation . One Bul k-Ou t
endpoint is used to transport commands and data from the host to the device. One Bulk-
In endpoint is used to transport sta tus and data from the device to the host. No interrupt
endpoint is needed .
The following configuration adheres to these requirements:
•Endpoint 0: 8 bytes, Control In-Out
•Endpoint 4: 64 bytes, Bulk-Out
•Endpoint 5: 64 bytes, Bulk-In
USB Device Firmware
Upgrade (DFU) The US B Device Firmware Update (D FU) proto col ca n be used to upgrad e the on-c hip
program memory of the AT8xC5122. This allows the implementation of product
enhancements and patches to devices that are already in the field. Two different config-
urations and description sets are used to support DFU functions. The Run-Time
config uratio n co-exi sts with the usual func tions of the devi ce, which ma y be USB Ma ss
Storage for the AT8xC5122. It is used to initiate DFU from the normal operating mode.
The DFU configuration is used to perform the firmware update after device re-configura-
tion and USB reset. It excludes any other function. Only the default control pipe
(endpoint 0) is used to support DFU services in both configurations.
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The only possible value for the wMaxP acketSize in the DFU configuration is 32 bytes,
which is the size of the FIFO implemented for endpoint 0.
Description The USB device controller provides the hardware that the AT8xC5122 and the
AT8xC5 123 ne ed to i nterfac e a US B li nk to a data flow s tored in a do uble p ort m emory
(DPRAM).
The USB controller requires a 48 MHz reference clock, which is the output of the
AT8xC5122/23 PLL (see Section "PLL", page 32) divided by a clock prescaler . T his
clock is used to generat e a 12 MH z f ull speed bit c lock fr om the rec eive d USB d ifferen-
tial data and to transmit data according to full speed USB device tolerance. Clock
recover y is don e by a Digital Phase Locked Loo p (DPLL ) block, which is compl iant wi th
the jitter specification of the USB bus.
The Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuffing,
CRC generat ion and chec king, and the serial-parall el data conv ersion. The Univ ersal
Function In ter face ( UFI) perfor ms the inter fa ce betwe en the data fl ow an d the Dual Port
Ram
Figure 30. USB Device Controller Block Diagram
Serial Interface Engine (SIE) The SIE performs the following functions:
•NRZI data encoding and decoding.
•Bit stuffing and unstuffing.
•CRC generation and checking.
•Handshakes.
•TOKEN type identifying.
•Addr ess checking.
•Clock generation (via DPLL).
SIE
DPLL
USB
D+/D-
Buffer UFI
12MHz
48 MHz +/- 0.25%
D+
Up to 48 MHz
UC_SYSCLK
C51
Microcontroller
Interface
D-
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Figure 31. SIE Block Diagram
Function Interface Unit (UFI) The Function Interface Unit provides the interface between the AT8xC5122 (or
AT8xC5123) and the SIE. It manages transactions at the packet level with minimal inter-
vention from the device firmware, which reads and writes the endpoint FIFOs.
Figure 32. UFI Block Diagram
End of Packet
Detection
Start of Packet
Detection
D+
D-
Clock
Recovery
SYNC detection
PID decoder
Address Decoder
Serial to Parallel
Conversion
CRC5 & CRC16
Generation/Check
USB Pattern Generator
Parallel to Serial Converter
Bit Stuffing
NRZI Converter
CRC16 Generator
NRZI ‘ NRZ
Bit U n s tuffing
Packet bit counter
Clk48
(48 MHz)
SysClk
(12 MHz)
DataIn [7:0]
DataOut
8
8
Transfer
Control
FSM
DPR Control
USB side
CSREG 0 to 7
Registers
Bank
DPR Control
mP side
UFI
User DPRAM
Up to 48 MHz
UC_SYSCLK
C51
Microcontroller
Interface
Asynchronous Information
Transfer
Endpoint 0
Endpoint 1
Endpoint 2
Endpoint 3
SIE
DPLL
Endpoint 4
Endpoint 5
Endpoint 6
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Figure 33. Min im um Inter vent ion from the USB Device F irmwa re
OUT Transactions:
HOST
UFI
C51
OUT DATA0 (n Bytes)
ACK Endpoint FIFO read (n bytes)
OUT DATA1
NACK
OUT DATA1
ACK
IN Transactions:
HOST
UFI
C51
IN ACK
Endpoint FIFO write
IN
DATA1
NACK
interrupt C51
IN
DATA1 interrupt C51
Endpoint FIFO write
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Configuration
General Configuration •USB controller enable
Before any USB transa ction, the 48 MH z required by the USB con troller must be co r-
rectly generated (Section "Clock Controller", page 28).
The USB controller should be then enabled by setting the USBE bit in the USBCON
register.
•Set address
After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in
the USBADDR register. This action will allow the U SB controller to answer to the
requests sent at the address 0.
When a SET_ADDRESS request has been received, the USB controller must only
answer to th e addres s defi ned by the reques t. T he ne w addres s should be sto r ed in the
USBADDR register. The FEN bit and the FADD EN bit in the USBCON register should
be set to allow the USB controller to answer only to requests sent at the new address.
•Set configuration
The CONF G bit in the US BCON register sh ould be set after a SET_ CONFIG URATIO N
request with a non-zero value. Otherwise, this bit should be cleared.
Endpoint Configuration •Selection of an Endpoint
The endpoint register access is p erformed using the UEPNUM register . The following
registers
corresp ond to the e ndpoin t whos e num ber is stored in the UE PNUM reg ister. To sel ect
an Endpoint, the firmware has to write the endpoint number in the UEPNUM register.
–UEPSTAX,
–UEPCONX,
–UEPDATX,
–UBYCTX,
Figure 34. End poi nt Sel ec tio n
•Endpoint enable
UEPNUM
Endpoint 0
Endpoint 6
UEPSTA0 UEPCON0 UEPDAT0
UEPSTA6 UEPCON6 UEPDAT6
0
1
2
3
4
5
6
SFR Registers
UEPSTAX UEPCONX UEPDATX
X
UBYCT0
UBYCT6
UBYCTX
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Before using an endpoint, this one should be enabled by setting the EPEN bit in the
UEPCONX register.
An endpoint which is not enabled won’t answer to any USB request. The Default Control
Endp oint (Endpoint 0) should always b e e nabled in or der to answer to USB standard
requests.
•Endpoint type configuration
All Standar d Endpoints can be config ured in Control, Bul k, Interrupt or Isochronous
mode. The Ping-pong Endpoints can be configured in Bulk, Interrupt or Isochronous
mode. The configuration of an endpoint is performed by setting the field EPTYPE with
the following values:
–Control: EPTYPE = 00b
–Isochronous: EPTYPE = 01b
–Bulk: EPTYPE = 10b
–Interrupt: EPTYPE = 11b
The Endpoint 0 is the Default Control Endpoint and should always be configured in Con-
trol type.
•Endpoint direction configuration
For Bulk, Inter rupt and Isochronous endpoints, the direction is defined with the EPDIR
bit of the UEPCONX re gis te r with the followi ng valu es:
–IN:EPDIR = 1b
–OUT:EPDIR = 0b
For Control endpoints, the EPDIR bit has no effect.
•Summary of Endpoint Configuration:
Make sure to select the correct endpoint number in the UEPNUM register before
accessing to endpoint specific registers.
Table 57. Summar y of Endpoi nt Confi gu ra tio n
Endpoint confi gur ation EPEN EPDIR EPTYPE UEPCONX
Dis abled 0b Xb XXb 0XXX XXXb
Control 1b Xb 00b 80h
Bulk-In 1b 1b 10b 86h
Bulk-Out 1b 0b 10b 82h
Interrupt-In 1b 1b 11b 87h
Interrupt-Out 1b 0b 11b 83h
Isochronous-In 1b 1b 01b 85h
Isochronous-Out 1b 0b 01b 81h
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•Endpoint FIFO reset
Before us ing an endpo int, its FIFO sh ould be reset. Thi s action res ets the FIFO poin ter
to its original value, resets the byte counter of the endpoint (UBYCTX r egister), and
resets the data toggle bit (DTGL bit in UEPCONX).
The rese t of an endp oint FIF O is perform ed by settin g to 1 a nd re settin g to 0 the cor re-
sponding bit in the UEPRST register.
For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then 0000
0000b in the UEPR ST reg ister .
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Read/Write Data FIFO
Read Data FIFO The read access for each OUT endpoint is performed using the UEPDATX register.
After a ne w va lid pac k et ha s be en r ece ive d on an E ndpo in t, the data are sto red i nto th e
FIFO and th e byte coun ter of the endpoi nt is upd ated (UBY CTX regi ster) . The fir mwar e
has to store the endpoint byte counter before any access to the endpoint FIFO. The byte
counter is not updated when reading the FIFO.
To read data from an endpoint, select the correct endpoint number in UEPNUM and
read the UEPDATX register. This action automatically decreases the corresponding
address vector, and the next data is then available in the UEPDATX register.
Write Data FIFO The write access for each IN endpoint is performed using the UEPDATX register.
To write a by te into an IN en dpoint FIFO, sele ct the correct endp oint numbe r in UEP-
NUM and write into the UEPDATX register. The corresponding address vector is
automatically increased, and another write can be carried out.
Warning 1: The byte counter is not updated.
Warning 2: Do not write more bytes than supported by the corresponding endpoint.
Figure 35. En dpoi nt FIFO C onfigur a tion
Endpoint 0 - bank 0
Endpoint 1 - bank 0
Endpoint 2 - bank 0
Endpoint 3 - bank 0
Endpoint 4 - bank 0
Endpoint 5 - bank 0
Endpoint 6 - bank 0
Endpoint 6 - bank 1
8 Bytes
32 Bytes
8 Bytes
8 Bytes
64 Bytes
2 x 64 Bytes
Base Addresses
00H
20H
28H
30H
38H
78H
B8H
F8H
138H
64 Bytes
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Bulk / Interrupt
Transactions Bulk and Interrupt transactions are managed in the same way.
Bulk/Interrupt OUT
Transactions in Standard
Mode
Figure 36. Bulk/Interrupt OUT transactions in Standard Mode
An end point s ho uld be fi r st e nab le d and co nfi gur ed befo re bei ng abl e to r e cei ve B ulk or
Interrupt packets.
When a vali d OUT pa cket i s rece ived o n an en dpoint, the R XOUTB0 bit is set b y the
USB cont roller . This tri ggers an inter rupt if en abled. T he firm ware h as to sel ect the cor-
responding endpoint, store the number of data bytes by reading the UBYCTX register. If
the rece iv ed p ac ke t is a ZL P ( Z ero L ength Pac ket ), the UBYCT X reg is ter value is e qua l
to 0 and no data has to be read.
When all the endpoint FIFO bytes have been read, the firmware sho uld clear th e
RXOUTB0 bi t to allow the USB c ontroller to accept the next OUT p acket on this end-
point. Until the RX OUTB0 bi t has been cle ared by th e firmwa re, the USB co ntroller will
answer a NAK handshake for each OUT requests.
If the Host sends more bytes than supported by the endpoint FIFO, the o verflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct and the endpoint byte counter contains the number of bytes sent by the Host.
OUT DATA0 (n bytes)
ACK
HOST UFI C51
Endpoint FIFO read byte 1
OUT DATA1
NAK
RXOUTB0
Endpoint FIFO read byte 2
Endpoint FIFO read byte n
Clear RXOUTB0
OUT DATA1
NAK
OUT DATA1
ACK RXOUTB0 Endpoint FIFO read byte 1
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Bulk/Interrupt OUT
Transactions in Ping-Pong
Mode (Endpoints 6)
Figure 37. Bulk / Interrupt OUT transactions in Ping-Pong mode
An end point s ho uld be fi r st e nab le d and co nfi gur ed befo re bei ng abl e to r e cei ve B ulk or
Interrupt packets.
When a valid OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by
the USB controller. This triggers an interrupt if enabled. The firmware has to select the
corres ponding endpoint , store the num ber of data byte s by readin g the UBYC TX regis-
ter. If the r eceived packet is a ZLP ( Zero Len gth Pack et), the UBYCTX reg ister v alue is
equal to 0 and no data has to be read.
When all the endpoint FIFO bytes have been read, the firmware sho uld clear th e
RXOUB0 bi t to allow the USB contro ller to accept the next OUT pa cket on the endpoi nt
bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has
been cleared by the firmware, the USB controller will answer a NAK handshake for each
OUT requests on the bank 0 endpoint FIFO.
When a new vali d OUT packet is re ceived on the en dpoint bank 1, the RXOU TB1 bit is
set by the USB controller. This triggers an interrupt if enabled. The firmware empties the
bank 1 endpoint FIFO before clea ring the RXOUTB1 bit. Until the RXOUTB1 bit has
been cleared by the firmware, the USB controller will answer a NAK handshake for each
OUT requests on the bank 1 endpoint FIFO.
The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each
new valid packet receipt.
The firmware has to clear one of these two bits after having read al l the data FIF O to
allow a new valid packet to be stored in the corresponding bank.
A NAK handsh ake is sent by the USB controller only if the banks 0 an d 1 has not been
released by the firmware.
OUT DATA0 (n bytes)
ACK
HOST UFI C51
Endpoint FIFO bank 0 - read byte 1
RXOUTB0
Endpoint FIFO bank 0 - read byte 2
Endpoint FIFO bank 0 - read byte n
Clear RXOUTB0
OUT DATA1 (m bytes)
ACK
RXOUTB1 Endpoint FIFO bank 1 - read byte 1
Endpoint FIFO bank 1 - read byte 2
Endpoint FIFO bank 1 - read byte m
Clear RXOUTB1
OUT DATA0 (p bytes)
ACK
RXOUTB0 Endpoint FIFO bank 0 - read byte 1
Endpoint FIFO bank 0 - read byte 2
Endpoint FIFO bank 0 - read byte p
Clear RXOUTB0
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If the Host sends more bytes than supported by the endpoint FIFO, the o verflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct.
Bulk/Interrupt IN T ransactions
In Standard Mode Figure 38. Bu lk /Inte rru pt IN Transa ctions in Standard Mod e
An endpoint sh ould be first enabled and config ured before being able to send Bulk or
Interrupt packets.
The firm ware shou ld fill the F IFO with the data to be sen t and set th e TXRDY bit in the
UEPSTAX register to allow the USB controller to send the data stored in FIFO at the
next IN request concerning this endpoint. To send a Zero Length Packet, the firmware
should set the TXRDY bit without writing any data into the endpoint FIFO.
Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK
handshake for each IN requests.
To cancel the sending of th is packet, the firmware has to reset the TXRDY bit. The
packet stored in the endpoint FIFO is then cleared and a new packet can be written and
sent.
When the IN packet has been sent and acknowledged by the Host, the TXCMPL bit in
the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if
enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO with
new data.
The firmware should never write more bytes than supported by the endpoint FIFO.
All USB retry mechanisms are automatically managed by the USB controller.
IN DATA0 (n bytes)
ACK
HOST UFI C51
Endpoint FIFO write byte 1
IN
NAK
TXCMPL
Endpoint FIFO write byte 2
Endpoint FIFO write byte n
Set TXRDY
Clear TXCMPL
Endpoint FIFO write byte 1
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Bulk/Interrupt IN T ransactions
in Ping-Pong Mode Figure 39. Bulk / Interrupt IN transactions in Ping-Pong mode
An end point wi ll be fi rst enab led and co nfi gured before being able to s end Bu lk or Inte r-
rupt packe ts.
The fir mware w ill fill th e F IFO b ank 0 with t he data to be sent a nd s et the TXRDY bit in
the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the
next IN request concerning the endpoint. The FIFO banks are automatically switched,
and the firmware can immediately write into the endpoint FIFO bank 1.
When the IN packet concerning the bank 0 has been sent and acknowledged by the
Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if
enabled. T he firmware will clear the TXCMP L bit befor e filli ng the end poi nt FIF O bank 0
with new data. The FIFO banks are then automatically switched.
When the IN packet concerning the bank 1 has been sent and acknowledged by the
Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if
enabled. T he firmware will clear the TXCMP L bit befor e filli ng the end poi nt FIF O bank 1
with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by
the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank,
the USB controller will answer a NAK handshake for each IN requests concerning this
bank.
Note that in the example ab ove, the firmwar e clears the Tr ansmit Complete b it (TXC-
MPL) b efo re s etti ng th e Tra nsm it Ready b it ( TXRDY ) . Th is i s d one i n o rder t o av oid th e
firmware to clear at the same time the TXCMPL bit for bank 0 and the bank 1.
The firmware will never write more bytes than supported by the endpoint FIFO.
IN DATA0 (n Bytes)
ACK
HOST UFI C51
Endpoint FIFO Bank 0 - Write Byte 1
IN
NACK
TXCMPL
Endpoint FIFO Bank 0 - Write Byte 2
Endpoint FIFO Bank 0 - Write Byte n
Set TXRDY
Endpoint FIFO Bank 1 - Write Byte 1
Endpoint FIFO Bank 1 - Write Byte 2
Endpoint FIFO Bank 1 - Write Byte m
Set TXRDY
IN DATA1 (m Bytes)
ACK
Endpoint FIFO Bank 0 - Write Byte 1
Endpoint FIFO Bank 0 - Write Byte 2
Endpoint FIFO Bank 0 - Write Byte p
Set TXRDY
Clear TXCMPL
IN
DATA0 (p Bytes)
ACK
TXCMPL Clear TXCMPL
Endpoint FIFO Bank 1 - Write Byte 1
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Control Transactions
Setup Stage The DIR bit in the UEPSTAX register should be at 0.
Receiving Setup packets is the same as receiving Bulk Ou t packets, except that the
Rxsetup bit in the UEPSTAX register is set by the USB controller instead of the
RXOUTB0 bi t to indic ate t hat an O ut pa cket wi th a S etu p P ID has be en r ecei ved on th e
Control endpoint. When the RXSET UP bit has been set, a ll the other bits of the UEP-
STAX register are cleared and an interrupt is triggered if enabled.
The firm ware h as to read the Setup requ est stor ed in the Co ntrol en dpoint FIFO before
clearing the RXSETUP bit to free the endpoint FIFO for the next transaction.
Dat a Stage: Control Endpoint
Direction The data stage management is similar to Bulk management.
A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and
OUT. All othe r end point ty pes ar e manag ed as half- duplex e ndpoint : IN o r OUT. The
firmware has to specify the control endpoint direction for the data stage using the DIR bit
in the UEPSTAX register.
•If the data stage consists of INs,
the firmware has to set the DIR bit in the UEPSTAX register before writing into the
FIFO and sending t he data by setting to 1 the TXRDY bit in the UEPSTAX register.
The IN transaction is complete when the TXCMPL has been set by the hardware.
The firmware should clear the TXCMPL bit before any other transaction.
•If the data stage consists of OUTs,
the firmware has to leave the DIR bit at 0. The RXOUTB0 bit is set by hardware
when a new valid packet has been received on the endpoint. The firmware must
read the data stored into the FIFO and then clear the RXOUTB0 bit to reset the
FIFO and to allow the next transaction.
The bit DIR is used to send the correct data toggle in the data stage.
To send a STALL handshake, see “STALL Handshake” on page 72.
Status Stage The DIR bit in the UEPSTAX register should be reset at 0 for IN and OUT status stage.
The status stage management is similar to Bulk management.
•For a Control Write transaction or a No-Data Control transaction, the status stage
consists of a IN Zero Length Packet (see “Bulk/Interrupt IN Transactions In
Standar d Mod e” on page 67). To send a STALL handshake, see “STALL
Handshake” on page 72.
•For a Control Read transaction, the status stage consists of a OUT Zero Length
Packet (see “Bulk/In ter rupt OU T Tra nsa ct ion s in Sta ndard Mod e” on page 65).
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Isochronous
Transactions
Isochronous OUT
Transactions in Standard
Mode
An endpoint should be first enabled and configured before being able to receive Isochro-
nous pack ets .
When an OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB
controller. This triggers an interrupt if enabled. The firmwa re has to select the corre-
sponding endpoint, store the number of data bytes by reading the UBYCTX register. If
the rece iv ed p ac ke t is a ZL P ( Z ero L ength Pac ket ), the UBYCT X reg is ter value is e qua l
to 0 and no data has to be read.
The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet
stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt.
When all the endpoint FIFO bytes have been read, the firmware sho uld clear th e
RXOUTB0 bit to allow the USB controller to store the next OUT packet data into the
endpoint FIFO. Until the RXO UTB0 bi t has been c leared by th e firmwar e, the data sent
by the Host at each OUT transaction will be lost.
If the RXOUTB0 bit is cleared while the Host is sending data, the USB controller will
store only the remaining bytes into the FIFO.
If the Host sends more bytes than supported by the endpoint FIFO, the o verflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct.
Isochronous OUT
Transactions in Ping-pong
Mode
An endpoint should be first enabled and configured before being able to receive Isochro-
nous pack ets .
When a OUT pack et is receive d on the endpoi nt bank 0, the RXOU TB0 bit is set by the
USB cont roller . This tri ggers an inter rupt if en abled. T he firm ware h as to sel ect the cor-
responding endpoint, store the number of data bytes by reading the UBYCTX register. If
the rece iv ed p ac ke t is a ZL P ( Z ero L ength Pac ket ), the UBYCT X reg is ter value is e qua l
to 0 and no data has to be read.
The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet
stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt.
When all the endpoint FIFO bytes have been read, the firmware sho uld clear th e
RXOUB0 bi t to allow the USB contr oll er to sto re the nex t OUT pac ket data i nto the end-
point FIFO ba nk 0. T hi s act ion swi tches the end poi nt ba nk 0 an d 1. Un til the RXOU TB 0
bit has been clea red by the fi rmware, the d ata s ent by th e Hos t on t he ban k 0 e ndp oint
FIFO will be lost.
If the RXOUTB0 bit is cleared while the Host is sending data on the endpoint bank 0, the
USB controller will store only the remaining bytes into the FIFO.
When a new OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by
the USB controller. This triggers an interrupt if enabled. The firmware empties the
bank 1 endpoint FIFO before clea ring the RXOUTB1 bit. Until the RXOUTB1 bit has
been cleared by the firmware, the data sent by the Host on the bank 1 endpoint FIFO
will be lost .
The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each
new packet receipt.
The firmware has to clear one of these two bits after having read al l the data FIF O to
allow a new packet to be stored in the corresponding bank.
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If the Host sends more bytes than supported by the endpoint FIFO, the o verflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct.
Isochronous IN Transactions
in Standard Mode An endpoint should be first enabled and configur ed before being able to send Isochro-
nous pack ets .
The firm ware shou ld fill the F IFO with the data to be sen t and set th e TXRDY bit in the
UEPSTAX register to allow the USB controller to send the data stored in FIFO at the
next IN request concerning this endpoint.
If the TXRDY bi t is not set wh en the IN r eques t occurs, no thing wi ll be sent b y the USB
controller.
When the IN pa cket has bee n sent, the TXCMPL bit in the UEPSTAX register is set by
the USB cont roller. This triggers a USB interrupt if enabled. The firmware should clear
the TXCMPL bit before filling the endpoint FIFO with new data. The firmw are should
never write more bytes than supported by the endpoint FIFO.
Isochronous IN Transactions
in Ping-Pong Mode An endpoint should be first enabled and configur ed before being able to send Isochro-
nous pack ets .
The firmwar e sh oul d fill the FIFO ban k 0 with the data to be sent and set the TXRDY bi t
in the UE PST AX reg ister t o allow t he USB cont roll er to s end the data s tored i n FIFO at
the next IN request concerning the endpoint. The FIFO banks are automatically
switched, and the firmware can immediately write into the endpoint FIFO bank 1.
If the TXRDY bi t is not set wh en the IN r eques t occurs, no thing wi ll be sent b y the USB
controller.
When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the
USB controller . This triggers a USB interrupt if enabled. The firmware should clear the
TXCMPL bit befo re fil li ng t he e ndpo in t FI FO b ank 0 wi th n ew da ta. T he FIF O bank s are
then automatically switched.
When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the
USB controller . This triggers a USB interrupt if enabled. The firmware should clear the
TXCMPL bit before filling the endpoint FIFO bank 1 with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by
the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank,
the USB controller won’t send anything at each IN requests concerning this bank.
The firmware should never write more bytes than supported by the endpoint FIFO.
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Miscellaneous
USB Reset The E ORINT bit in the US BINT register is set by hardwa re when a End of Rese t has
been de tecte d on the USB b us. T his trig gers a USB inte rrupt if en able d. The US B c on-
troller is still enabled, but all the USB registers are reset by hardware. The firmwar e
should clear the EORINT bit to allow the next USB reset detection.
STALL Handshake This function is only available for Control, Bulk, and Interrupt endpoints.
The firmwa re has to set the STA LLRQ bit in the UEPS TAX register to send a STALL
handshake at the next request of the Host on the endpoint selected with the UEPNUM
register. The RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first
reset to 0. The bit STLCRC is set at 1 by the USB controller when a STALL has been
sent. This triggers an interrupt if enabled.
The firmware should clear the STALLRQ and STLCRC bits after each STALL sent.
The STALLRQ bit i s cleared automatically by hardware when a valid SETUP PID is
received on a CONTROL type endpoint.
Start of Frame Detection The SOFINT bit in the USBINT register is set when the USB controller detects a Start Of
Frame P ID. T h is tri gge rs a n inter rupt if ena bled. The fir mw ar e s ho ul d cle ar th e SO FINT
bit to allow the next Start of Frame detection.
Frame Number When receiving a Start of Frame, the frame number is automatically stored in the
UFNUML and UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of
the last St art Of Frame is valid ( CRCOK set at 1) or co rrupt (CRCERR s et at 1). The
UFNUML and UFNUMH registers are automatically updated when receiving a new Start
of Frame.
Data Toggle Bit The Data Toggle bit is set by hardware when a DATA 0 packet is received and accepted
by the USB cont roller and clear ed b y ha rdware when a DA TA 1 pack et i s rec eived and
accepte d by th e USB con trolle r. This bit is res et wh en the firmwa re res ets the endp oint
FIFO using the UEPRST register.
For Contro l endpoi nts, ea ch SETU P transac tion star ts with a DATA 0 and data toggl ing
is then used as for Bulk endpoints until the end of the Data stage (for a control write
transfer). The Status stage completes the data transfer with a DATA 1 (for a control read
transfer).
For Isochronous endpoints, the device firmware should ignore the data-toggle.
NAK handshakes When a NAK handshak e is sent by the US B contro ller to a IN or OUT requ est from the
Host, th e NAKIN or NA KOUT bit is s et by hardwar e. This infor mation can be used to
determine the direction of the communication during a Control transfer.
These bits are cleared by software.
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Suspend/Resume Management
Suspend The Suspend state can be detected by the USB c ontroller if all the clocks are enabled
and if the USB contr oller is enabled. The bit SPINT is set by hardware when an idle
state is detected for more than 3 ms. This triggers a USB interrupt if enabled.
In order to reduce current consumption, the firmware can put the USB PAD in idle mode,
stop the c locks and p ut the C5 1 in Id le or Power- down mo de. The R esu me dete ction is
still active.
The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to
avoid a new suspe nd detectio n 3ms later, th e firmware has to disa ble the USB clock
input using the SUSPCLK bit in the USBCON Register. T he USB PAD automatically
exits of idle mode when a wake-up event is detected.
The stop of the 48 MHz clock from the PLL should be done in the following order:
1. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUS-
PCLK bit in the USBCON register.
2. Disable the PLL by clearing the PLLEN bit in the PLLCON register.
Resume W hen the US B cont roller is in Sus pend s tate, the Re sume d etecti on is acti ve ev en if all
the clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit
is set by hardwa re when a non-idle state oc cur s on the USB bu s. Thi s trigge rs an inte r-
rupt if enabled. This interrupt wakes up the CPU from its Idle or Power-down state and
the interrup t functi on is then ex ecuted . The firmw are will fi rst enable the 48 MHz gene r-
ation and then reset to 0 the SUSPCLK bit in the USBCON register if needed.
The firmware has to clear the SPINT bit in the USBINT register before any other USB
operation in order to wake up the USB controller from its Suspend mode.
The USB controller is then re-activated.
Figure 40. Example of a Suspend/Resume Management
USB Contro ll er Init
Detection of a SUSPEND State SPINT
Set SUSPCLK
Disable PLL
microcontroller in Power-down
Detection of a RESUME State WUPCPU
Enable PLL
Clear SUSPCLK
Clear WUPCPU Bit
Clear SPINT
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AT8xC5122/23 4202B–SCR–07/03
Upstream Resume A USB dev ice can be allowed by the Hos t to send an upstream resume for Remote
Wake-up purpose.
When the USB controller receives the SET_FEATURE request:
DEVICE_REMOTE _WAKEUP, the fir mware should set to 1 the RMWUPE bit in the
USBCON register to enable this function. RMWUPE value should be 0 in the other
cases.
If the device is in SUSPEND mode, the USB controller can send an upstream resume by
clearing first the SPINT bit in the USBINT register and by setting then to 1 the SDRM-
WUP bit in the USBC ON registe r. The US B controller se ts to 1 the UPRSM bi t in the
USBCON register. All clocks must be enabled first. The Remote Wake is sent only if the
USB bus was in Suspend st ate for at least 5 ms . When the upstream r esume is com-
pleted, the UPRSM bit is reset to 0 by hardware. The firmware should then clear the
SDRMW U P bit .
Figure 41. Example of REMOTE WAKEUP Management
USB Controller Init
Detection of a SUSPEND state SPINT
Set RMWUPE
Suspend management
Enable Clocks
upstream RESUME sent UPRSM
Clear SPINT
Set SDMWUP
Clear SDRMWUP
SET_FEATURE: DEVICE_REMOTE_WAKEUP
Need USB Resume
UPRSM = 1
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AT8xC5122/23
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Detach Simulation In orde r to be re-e numerate d by the Hos t, the AT 8xC5122/23 has the po ssib ility to sim-
ulate a DETACH-ATTACH of the USB bus.
The VREF output voltage is between 3.0V and 3.6V. This output can be connected to the
D+ pull-up as shown in Figure 42. This output can be put in high-impedance when the
DETACH bit is set to 1 in the USBC ON register. Maintaining this output in high imped-
ance for more than 3 µs wil l simulate the disco nnection of the device. W hen resetting
the DETA CH bit, an ATTACH is then simula ted. The US B controll er should be enabled
to use this feature.
Figure 42. Example of VREF Connectio n
Figure 43. Disconnect Timing
D-
D+ D-
D+
GND
VCC
VREF
1.5 kΩ
USB-B Connecto r
1
2
3
4
D+
D-
VSS
VIL
VIHZ(min)
Device
Disconnected Disconnect
Detected
>= 2,5 µs
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AT8xC5122/23 4202B–SCR–07/03
USB Interrupt System
Interrupt System Priorities
Figure 44. USB Interrupt Control System
Interrupt Control System As shown in Figure 45, many events can produce a USB interrupt:
•TXCMPL: Transmitted In Data (Table 65 on page 83). This bit is set by hardware
when the Host accept a In packet.
•RXOUTB0: Received Out Data Bank 0 (Table 65 on page 83). This bit is set by
hardware when an Out packet is accepted by the endpoint and stored in bank 0.
•RXOUTB1: Received Out Data Bank 1 (only for Ping-Pong endpoints) (Table 65 on
page 83). This bit is set by hardware when an Out packet is accepted by the
endpoint and stored in bank 1.
•RXSETUP: Received Setup (Table 65 on page 83). This bit is set by hardware when
an SETUP packet is accepted by the endpoint.
•NAKIN and NAKOUT: These bits are set by hardware when a Nak Handshake has
been received on the corresponding endpoint. These bits are cleared by software.
•STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table on page
84). This bit is set by hardware when a STALL handshake has been sent as
requested by STALLRQ, and is reset by hardware when a SETUP packet is
received.
•SOFINT: St art Of Frame Interrupt (Table 60 on page 79). This bit is set by hardware
when a USB start of frame packet has been received.
•WUPCPU: Wake-Up CPU Interrupt (Table 60 on page 79). This bit is set by
hard war e when a USB resum e is de te cted on the USB b us, aft er a SU SPEN D st ate .
•SPINT: Suspend Interrupt (Table 60 on page 79). This bit is set by hardware when a
USB suspend is detected on the USB bus.
EUSB
IEN1.6 EA
IEN0.7
USB
Controller
IPH/L
Interrupt Enable Lowest Priority Interrupts
Priority Enable
00
01
10
11
D+
D-
Table 58. Priority Levels
IPHUSB IPLUSB USB Priority Level
0 0 0 Lowest
01 1
10 2
1 1 3 Highest
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Figure 45. USB Interrupt Control Block Diagram
TXCMP
UEPSTAX.0
RXOUTB0
UEPSTAX.1
RXSETUP
UEPSTAX.2
STLCRC
UEPSTAX.3
EPXIE
UEPIEN.X
EPXINT
UEPINT.X
SOFINT
USBINT.3
ESOFINT
USBIEN.3
SPINT
USBINT.0 ESPINT
USBIEN.0
EUSB
IE1.6
Endpoint X (X = 0..6)
EORINT
USBINT.4
WUPCPU
USBINT.5
EWUPCPU
USBIEN.5
RXOUTB1
UEPSTAX.6
EEORINT
USBIEN.4
NAKOUT
UEPCONX.5
NAKIN
UEPCONX.4 NAKIEN
UEPCONX.6
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AT8xC5122/23 4202B–SCR–07/03
Registers
Reset Value = 0000 0000b
Table 59. USB Global Control Register - USBCON (S:BCh)
76 543210
USBE SUSPCLK SDRMWUP DETACH UPRSM RMWUPE CONFG FADDEN
Bit
Number Bit
Mnemonic Description
7USBE
USB Enable
Set this bit to enable the USB controller.
Clear this bit to disable and re set the USB controller, to disable the USB
transceiver an to disable the USB controller clock inputs.
6SUSPCLK
Suspend USB Clock
Set this bit to disable t he 48MHz clock input (Resume Detection is still active).
Clear this bit to enable the 48MHz clock input.
5SDRMWUP
Send Remote Wake-up
Set this bit to force an external interrupt on the USB controller for Remote Wake
UP purpose.
An upstream resume is send only if the bit RMWUPE is set, all USB clocks are
enabled AND the USB bus was in SUSPEND state for at least 5 ms. See UPRSM
below. This bit is cleared by soft ware.
4DETACH
Detach Command
Set this bit to simulate a Detach on the USB line. The VREF pin is then in a
floating state.
Cle a r this b i t to mainta in VREF at 3.3V.
3UPRSM
Upstream Resume (read only)
This bit is set by hardware when SDRMWUP has been set and if RMWUPE is
enabled.
This bit is cleared by hardware after the upstream resume has been sent.
2RMWUPE
Remote Wake-Up Enable
Set this bit to enabled r equest an upstream resume signaling to the host.
Clear this bit otherwise.
Note: Do not set this bit if the host has not set the DEVICE_REMOTE_WAKEUP
feature for the device.
1CONFG
Configured
This bit should be set by the device firmware after a SET_CONFIGURATION
request with a non-zero value has been correctly processed.
It should be cleared by the device firmware when a SET_CONFIGURATION
request with a zero value is received. It is cleared by hardware on hardware reset
or when an USB reset is detected on the bus (SE0 state for at least 32 Full Speed
bit times: typically 2.7 µs).
0 FADDEN
Function Address Enable
This bit should be set by the device firmware after a successful status phase of a
SET_ADDRESS transaction.
It should not be cleared afterw ards by the device firmware. It is cleared by
hardware on hardware reset or when an USB reset is received (see above).
When this bit is cleared, the default function address is used (0).
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Reset Value = 0000 0000b
Table 60. USB Global Interrupt Register - USBINT (S:BDh)
76543210
- - WUPCPU EORINT SOFINT - - SPINT
Bit Number Bit
Mnemonic Description
7 - 6 - Reserved
The value read from these bits is always 0. Do not change these bits.
5 WUPCPU
Wa ke-up CPU Interrupt
This bit is set by hardware when the USB controller is in SUSPEND state and is
re-activated by a non-idle signal FROM USB line (not by an upstream resume).
This triggers a USB interrupt when EWUPCPU is set in the Table on page 80.
When receiving this interrupt, user has to enable all USB clock inputs.
This bit should be cleared by software (USB clocks must be enabled before).
4EORINT
End of Reset Interrupt
This bit is set by hardware when a End of Reset has been detected by the USB
controller. This triggers a USB interrupt when EEORINT is set in the Table on
page 80.
This bit should be cleared by software.
3SOFINT
Start Of Frame Interrupt
This bit is set by hardware when an USB St art Of Frame PID (SOF) has been
detected. This triggers a USB interrupt when ESOFINT is set in the Table on
page 80.
This bit should be cleared by software.
2-1 - Reserved
The value read from these bits is always 0. Do not change these bits.
0SPINT
Suspend Interrupt
This bit is set by hardware when a USB Suspend (Idle bus for three frame
periods: a J state for 3 ms) is detected. This triggers a USB interrupt when
ESPINT is set in the Table on page 80.
This bit should be cleared by softwar e BEFO RE any other USB operation to re-
activate the macro.
80
AT8xC5122/23 4202B–SCR–07/03
Reset Value = 0001 0000b
Reset Value = 1000 0000b
Table 61. USB Global Interrupt Enable Register - USBIEN (S:BEh)
76543210
- - EWUPCPU EEORINT ESOFINT - - ESPINT
Bit Number Bit
Mnemonic Description
7 - 6 - Reserved
The value read from these bits is always 0. Do not change these bits.
5EWUPCPU
Enable Wake-up CPU Interrupt
Set this bit to enable W ake-up CPU Interrupt.
Clear this bit to disable Wake-up CPU Interrupt.
4EEOFINT
Enable End of Reset Interrupt
Set this bit to enable End of Reset Interrupt. This bit is set after reset.
Clear this bit to disable End of Reset Interrupt.
3ESOFINT
Enable SOF Inte rrup t
Set this b i t to enable SOF Interrupt.
Clear this bit to disable SOF Interrupt.
2-1 - Reserved
The value read from these bits is always 0. Do not change these bits.
0ESPINT
Enable Suspend Interrupt
Set this bit to enable Suspend Interrupts (See Table 60 on page 79).
Clear this bit to disable Suspend Interrupts.
Table 62. USB Address Register - USBADDR (S:C6h)
76543210
FEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0
Bit
Number Bit
Mnemonic Description
7FEN
Function Enable
Set this bit to enable the function. FADD is reset to 1.
Cleared this bit to disable the function.
6-0 UADD[6:0]
USB Address
This field contains the default address (0) after power-up or USB bus reset.
It should be written wit h the value set by a SET_ADDRESS request received by
the device firmware.
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Reset Value = 0000 0000b
Table 63. USB Endpoint Number - UEPNUM (S:C7h)
76543210
----EPNUM3EPNUM2EPNUM1EPNUM0
Bit
Number Bit
Mnemonic Description
7 - 4 - Reserved
The value read from these bits is always 0. Do not change these bits.
3 - 0 EPNUM[3:0]
Endpoint Number
Set this field with the number of the endpoint which should be accessed when
reading or writing to, USB Byte Count Register X (X=EPNUM set in UEPNUM
Register) - UBYCTX (S:E2h) or USB Endpoint X Control Register - UEPCONX
(S:D4h). This value can be 0, 1, 2, 3, 4, 5 or 6.
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Reset Value = 1000 0000b when UEPNUM = 0
Reset Value = 0000 0000b othe rw is e
Table 64. USB Endpoint X Control Register - UEPCONX (S:D4h)
76543210
EPEN NAKIEN NAKOUT NAKIN DTGL EPDIR EPTYPE1 EPTYPE0
Bit Number Bit
Mnemonic Description
7 EPEN
Endpoint Enable
Set this bit to enable t he endpoint according to the device configuration.
Endpoint 0 will always be enabled after a hardware or USB bus reset and
participate in the device configuration.
Clear this bit to disable the endpoint according to the device configuration.
6NAKIEN
NAK Interrupt Enable
Set this bit to enable NAKIN and NAKOUT Interrupt.
Clear this bit to disable NAKIN and NAKOUT Interrupt.
5NAKOUT
NAK OUT Sent
This bit is set by hardware when the a NAK handshake is sent by the USB
controller to an OUT request from the Host. This generates an interrupt if the
NAKIEN bi t is se t.
This bit shall be cleared by software.
4NAKIN
NAK IN Sent
This bit is set by hardware when the a NAK handshake is sent by the USB
controller to an IN request from the Host. This generates an interrupt if the
NAKIEN bi t is se t.
This bit shall be cleared by software.
3DTGL
Data Toggle (Read-only)
This bit is set by hardware when a valid DATA0 packet is received and
accepted.
This bit is cleared by hardware when a v alid DATA1 packet is received and
accepted.
2EPDIR
Endpoint Direction
Set this bit to configure IN direction for Bulk, Interrupt and Isochronous
endpoints.
Clear this bit to configure O UT direction for Bulk, Interrupt and Isochronous
endpoints.
This bit has no effect for Control endpoints.
1-0 EPTYPE[1:0]
Endpoint Type
Set this field according to the end point configurati on (Endpoint 0 will alway s be
configured as control):
00Control endpoint
01Isochronous endpoint
10Bulk endpoint
11Interrupt endpoint
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AT8xC5122/23
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Reset Value = 0000 0000b
Table 65. USB Endpoint Status and Control Register X - UEPSTAX (S:CEh) X=EPNUM set in UEPNUM Register)
76543210
DIR RXOUTB1 STALLRQ TXRDY STL/CRC RXSETUP RXOUTB0 TXCMP
Bit
Number Bit
Mnemonic Description
7DIR
Control Endpoint Dir e c t ion
This bit is used only i f the endpoint is configured in t he control type (see“USB Endpoint X Control Register - UEPCONX (S:D4h)”
on page 82).
This bit determines the Control data and status direction.
The device firmware should set this bit ONLY for the IN data s tage, before any other USB operation. Otherwise, the device
firmware should clear this bit.
6 RXOUTB1
Received OUT Data Bank 1 for Endpoint 6 (Ping-pong Mode)
This bit is set by hardware after a new packet has been stored in the endpoint FIFO Data bank 1 (only in Ping-pong mode).
Then, the endpoint interrupt is triggered if enabled (see “USB Global Interrupt Register - USBINT (S:BDh)” on page 79) and all
the following OUT packets to the endpoint bank 1 are rejected (NAK’ed) until this bit has been cleared, excepted for Isochronous
Endpoints.
This bit should be cleared by the device firmware after reading the O UT data from the endpoint FIFO.
5 STALLRQ
Stall Handshake Request
Set this bit to request a STALL answer to the host for the next handshake.
Clear this bit otherwise.
For CONTROL endpoints: cleared by hardware when a valid SETUP PID is received.
4 TXRDY
TX Packet Ready
Set this bit after a packet has been written into the endpoint FIFO for IN data transfers. Data should be written into the endpoint
FIFO only after this bit has been cleared. Set this bit without writing data to the endpoint FIFO to send a Z ero Length Packet.
This bit is cleared by hardware, as soon as the packet has been sent for Isochronous endpoints, or after the host has
acknowledged the packet for Control, Bulk and Interrupt endpoints. When this bit is cleared, the endpoint interrupt is triggered if
enabled (see Table 60 on page 79).
3STLCRC
Stall Sent / CRC error flag
- For Control, Bulk and Interrupt Endpoints :
This bit is set by hardware after a STALL handshake has been sent as requested by STALLRQ. Then, the endpoint interrupt is
triggered if enabled (see“” on page 79)
It should be cleared by the device firm ware.
- For Isochronous Endpoints (Read-Only):
This bit is set by hardware if the last received data is corrupted (CRC error on data).
This bit is updated by hardware when a new data is received.
2 RXSETUP
Received SETUP
This bit is set by hardware when a valid SETUP packet has been received from the host. Then, all the other bits of the register
are cleared by hardware and the endpoint interrupt is triggered if enabled (see Table 60 on page 79).
It should be cleared by the device firm ware after reading the SETUP data from the endpoint FIFO.
1 RXOUTB0
Received OUT Data Bank 0 (see also RXOUTB1 bit for Ping-pong Endpoints)
This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 0. Then, the endpoint interrupt is
triggered if enabled (see“” on page 79) and all the following OUT p ackets to the endpoint bank 0 are rejected (NAK’ed) until this
bit has been cleared, excepted for Isochronous Endpoints. However, for control endpoints, an early SETUP transaction may
overwrite the content of the endpoint FIFO, even if its Data packet is received while this bit is set.
This bit should be cleared by the device firmware after reading the O UT data from the endpoint FIFO.
0TXCMPL
Transmitted IN Data Complete
This bit is set by hardware after an IN packet has been transmitted for Isochronous endpoints and after it has been accepted
(ACK’ed) by the host for Control, Bulk and Interrupt endpoints. Then, the endpoint interrupt is triggered if enabled ( see Table
60).
This bit should be cleared by the device firmware before setting TXRDY.
84
AT8xC5122/23 4202B–SCR–07/03
Reset Val ue = XXXX XXX Xb
Reset Value = 0000 0000b
Table 66. USB FIFO Data Endpoint X (X=EPNUM set in UEPNUM Register) -
UEPDATX (S:CFh)
76543210
FDAT7 FDAT6 FDAT5 FDAT4 FDAT3 FDAT2 FDAT1 FDAT0
Bit
Number Bit
Mnemonic Description
7 - 0 FDAT[7:0] E ndpoint X FIFO data
Data byte to be written to FIFO or data byte to be read from the FIFO, for the
Endpoint X (see EPNUM).
Table 67. USB Byte Count Register X (X=EPNUM set in UEPNUM Register) - UBYCTX
(S:E2h)
76543210
- BYCT6 BYCT5 BYCT4 BYCT3 BYCT2 BYCT1 BYCT0
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from these bits is alwa ys 0. Do not change this bit.
6 - 0 BYCT[6:0] Byte Count LSB
Least Significant Byte of the byte count of a received data packet. This byte count
is equal to the number of data bytes received after the Data PID.
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Reset Value = 0000 0000b
Table 68. USB Endpoint FIFO Reset Register - UEPRST (S:D5h)
76543210
- EP6RST EP5RST EP4RST EP3RST EP2RST EP1RST EP0RST
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from these bits is always 0. Do not change this bit.
6EP6RST
Endpoint 6 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
5EP5RST
Endpoint 5 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
4EP4RST
Endpoint 4 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
3EP3RST
Endpoint 3 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
2EP2RST
Endpoint 2 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
1EP1RST
Endpoint 1 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
0EP0RST
Endpoint 0 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.
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AT8xC5122/23 4202B–SCR–07/03
Reset Value = 0000 0000b
Table 69. USB Endpoint Interrupt Register - UEPINT (S:F8h read-only)
76543210
- EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from these bits is always 0. Do not change this bit.
6EP6INT
Endpoint 6 Interr upt
This bit is set by hardware when an interrupt is triggered by the (see Table 65 on
page 83) and this endpoint interrupt is enabled by t he UEPIEN Register (see Table
70 on page 87).
This bit is cleared by hardware.
5EP5INT
Endpoint 5 Interr upt
This bit is set by hardware when an interrupt is triggered by the UEPST AX Register
(see Table 65 on page 83) and this endpoint interrupt is enabled by the UEPIEN
Register (see Table 70 on page 87).
This bit is cleared by hardware.
4EP4INT
Endpoint 4 Interr upt
This bit is set by hardware when an interrupt is triggered by the UEPST AX Register
(see Table 65 on page 83) and this endpoint interrupt is enabled by the UEPIEN
Register (see Table 70 on page 87).
This bit is cleared by hardware.
3EP3INT
Endpoint 3 Interr upt
This bit is set by hardware when an interrupt is triggered by the UEPST AX Register
(see Table 65 on page 83) and this endpoint interrupt is enabled by the UEPIEN
Register (see Table 70 on page 87).
This bit is cleared by hardware.
2EP2INT
Endpoint 2 Interr upt
This bit is set by hardware when an interrupt is triggered by the UEPST AX Register
(see Table 65 on page 83) and this endpoint interrupt is enabled by the UEPIEN
Register (see Table 70 on page 87).
This bit is cleared by hardware.
1EP1INT
Endpoint 1 Interr upt
This bit is set by hardware when an interrupt is triggered by the UEPST AX Register
(see Table 65 on page 83) and this endpoint interrupt is enabled by the UEPIEN
Register (see Table 70 on page 87).
This bit is cleared by hardware.
0EP0INT
Endpoint 0 Interr upt
This bit is set by hardware when an interrupt is triggered by the UEPST AX Register
(see Table on page 83) and this endpoint interrupt is enabled by the UEPIEN
Register (see Table 70 on page 87).
This bit is cleared by hardware.
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Reset Value = 0000 0000b
Table 70. USB Endpoint Interrupt Enable Register - UEPIEN (S:C2h)
76543210
- EP6INTE EP5INTE EP4INTE EP3INTE EP2INTE EP1INTE EP0INTE
Bit Number Bit Mnemonic Description
7-
Reserved
The value read from these bits is always 0. Do not change this bit.
6EP6INTE
Endpoint 6 Inte r r upt Enable
Set this bit to enable t he interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
5EP5INTE
Endpoint 5 Inte r r upt Enable
Set this bit to enable t he interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
4EP4INTE
Endpoint 4 Inte r r upt Enable
Set this bit to enable t he interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
3EP3INTE
Endpoint 3 Inte r r upt Enable
Set this bit to enable t he interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
2EP2INTE
Endpoint 2 Inte r r upt Enable
Set this bit to enable t he interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
1EP1INTE
Endpoint 1 Inte r r upt Enable
Set this bit to enable t he interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
0EP0INTE
Endpoint 0 Inte r r upt Enable
Set this bit to enable t he interrupts for this endpoint.
Clear this bit to disable the interrupts for this endpoint.
88
AT8xC5122/23 4202B–SCR–07/03
Seria l I/ O P o rt The serial I/O port in the AT 8xC5122/23 is compatible with the se rial I/O port in the
80C52.
The I /O port provide s both synchron ous an d async hronous communi cation m odes. It
operate s as an Univer sal A syn chr onous R ecei ver an d Transmi tter (UAR T) in thre e ful l-
duple x mo des ( Mod es 1, 2 and 3). As yn ch ro nou s trans mi s sion and recepti on c an occ ur
simultaneously and at different baud rates
Serial I/O port includes the following enhancements:
•Framing error detection
•Automatic address recognition
Framing Error Detection Fr aming bit error detection is provided for the thr ee asynchronous modes (Modes 1, 2
and 3). To enable the framin g bi t erro r de tection featur e, se t SMOD 0 bit in PCON regi s-
ter (See Figure 46).
Figure 46. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See Figure 51 on page 92) bit is set.
Software may examine F E bit after each reception to c heck for data errors. Once s et,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits c annot clear FE bit. When FE feature is enable d, RI r ise s on stop bit i nstead of th e
last data bit (See Figure 47 and Figure 48).
Figure 47. UART Timings in Mode 1
RITIRB8TB8RENSM2SM1SM0/FE
IDLPDGF0GF1POF-SMOD0SMOD1
To UART Framing Error Control
SM0 to UART Mode Control (SMOD0 = 0)
Set FE Bit if Stop Bit is 0 (Framing Error) (SMOD0 = 1)
SCON (98h)
PCON (87h)
Data Byte
RI
SMOD0=X
Stop
Bit
Start
Bit
RXD D7D6D5D4D3D2D1D0
FE
SMOD0=1
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Figure 48. UART Timings in Modes 2 and 3
Automatic Addres s
Recognition The aut oma tic a ddr ess r ec ogn iti on feat ure i s en abl ed when th e m ul tiproce ssor c om mu-
nication feature is enabled (SM2 bit in SCON register is set).
Imple mente d in hard ware, automati c addre ss rec ogniti on enha nces th e multip roces sor
communication feature by allowing the serial port to examine the address of each
inco ming command fr ame. Only when t he serial port re cognizes it s own address, th e
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired , you may enabl e the automat ic address recogniti on feature in mode 1. In this
configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the
received command frame address matches the device’s addre ss and is ter min ated by a
valid stop bit.
To supp ort automatic a ddr ess re co gni tio n, a dev ic e i s identifie d by a giv en add re ss an d
a broadcast address.
Note: The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
Given Address E ach device has an i ndivi dual addr ess th at is sp ecif ied i n S ADDR r egiste r; t he SA DEN
register is a mask byte that contains don’t care bits (defined by zeros) to form the
device’s given address. The don’t care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0010b
SADEN1111 1101b
Given1111 00X1b
RI
SMOD0=0
Data byte Ninth
bit Stop
bit
Start
bit
RXD D8D7D6D5D4D3D2D1D0
RI
SMOD0=1
FE
SMOD0=1
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AT8xC5122/23 4202B–SCR–07/03
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t car e bit; fo r slav es B and C, bi t 0 i s a 1. To commu -
nicate with slave A only, the master must send an address where bit 0 is clear (e.g.
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with
slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both
set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set,
bit 1 clear, and bit 2 clear (e.g. 1111 0001b).
Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t care bits, e.g.:
SADDR0101 0110b
SADEN1111 1100b
Broadcast =SADD R OR SA DEN1111 111X b
The use of don’t care bits provides flexibility in defining the broadcast address, however
in most applications, a broadcast address is FFh. The following is an example of using
broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR=1111 0010b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the s lave s, the ma ster mus t send a n add ress F Fh. To com mun icate with slav es A
and B, but not slave C, the master can send and address FBh.
Reset Addresses On reset, the SADDR and SADEN registers are initializ ed to 00h, i.e. the given and
broadc ast addr esses are XXXX XXXXb (all don ’t care bits). Thi s ensures tha t the seria l
port will reply to any ad dress, and so, that it is backwar ds compatible with the 80C5 1
microcontrollers that does not support automatic address recognition.
Timer 1 When using the Timer 1, the Baud Rate is derived from the overflow of the timer. As
shown in Figure 49 the Timer 1 is used in its 8-bit auto-re load mode). SMOD1 bit in
PCON register allows doubling of the generated baud rate.
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Figure 49. Timer 1 Baud Rate Generator Block Diagram
Internal Baud Rate Generator When using th e Inter nal Bau d Rate Generato r, th e Baud Rate i s derive d from the o ver-
flow of the ti mer. As shown in Figu re 5 0 the I nternal B aud Rat e Gener ator is an 8-bi t
auto- reload time r feed by th e peripheral clock or by the periphe ral clock di vided by 6
depending on the SPD bit in BDRCON register (see Figure 76 on page 98). The Internal
Baud Rate Gene rator i s enabl ed by setting BBR b it in BDRCO N regis ter. SMO D1 bi t in
PCON register allows doubling of the generated baud rate.
Figure 50. Internal Baud Rate Generator Block Diagram
Synchronous Mode (Mode 0) Mode 0 is a half-dup lex, syn chronous mode, whi ch is com monly used to expa nd the I/0
capabil ities of a d evice with shift r egis ters. The trans mit d ata (TXD ) pin o utputs a set of
eight clo ck pul se s whi le the r ec eive data (RXD) pi n tra ns mi ts or rece iv es a byt e of dat a.
The 8-b it data are tr ansmitt ed an d recei ved le ast-si gnifi cant bit (LSB ) first. Shifts occur
at a fixed Baud Rate (see Secti on “Baud Rate Selec tion (Mode 0)”). Figure 51 shows
the serial port block diagram in Mode 0.
TR1
TCON.6
0
1
GATE1
TMOD.7
Overflow
C/T1#
TMOD.6
TL1
(8 bits)
TH1
(8 bits)
INT1#
T1
CK_
T1 / 6 0
1
SMOD1
PCON.7
/ 2
T1
CLOCK
To serial Port
0
1
Overflow
SPD
BDRCON.1
BRG
(8 bits)
BRL
(8 bits)
CK_
SI / 6
IBRG
CLOCK
BRR
BDRCON.4
0
1
SMOD1
PCON.7
/ 2 To serial Port
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Figure 51. Serial I/O Port Block Diagram (Mode 0)
Transmission (Mode 0) To start a transmission mode 0, write to SCON register clearing bits SM0, SM1.
As show n in F igur e 52, writi ng t he byte to tra nsm it to S BUF reg is ter s tar ts the tra ns mi s-
sion. Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle
composed of a high level then low level signal on TXD. During the eighth clock cycle the
MSB (D7 ) is on the RXD pin . T he n, h ar dware drives the RXD pi n hi gh and as se rt s TI to
indicate the end of the transmission.
Figure 52. Transmission Waveforms (Mode 0)
Reception (Mode 0) To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bits
and setting the REN bit.
As shown in Figure 53, Clock is puls ed and the LSB (D0) is sampled on the RXD pin.
The D0 bit is then shifted into the shi ft register. A fter eight sampl ing, the MSB ( D7) is
shifted into the shift register, and hardware asserts RI bit to indicate a completed recep-
tion. Software can then read the received byte from SBUF register.
Figure 53. Reception Waveforms (Mode 0)
IBRG
CLOCK
TXD
RXDSBUF Tx SR
SBUF Rx SR
SM1
SCON.6 SM0
SCON.7
Mode Decoder
M3 M2 M1 M0
Mode
Controller
RI
SCON.0
TI
SCON.1
CK_
T1 Baud Rate
Controller
Write to SBUF
TXD
RXD
TI
D0 D1 D2 D3 D4 D5 D6 D7
Write to SCON
TXD
RXD
RI
D0 D1 D2 D3 D4 D5 D6 D7
Set REN, Clear RI
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Baud Rate Selection (Mode 0) In mode 0, baud rate can be either fixed or variable.
As shown in Figure 54, the selection is done using M0SRC bit in BDRCON register.
Figure 55 gives the baud rate calculation formulas for each baud rate source.
Figure 54. Baud Rate Source Selection (Mode 0)
Figure 55. Baud Rate Formulas (Mode 0)
Asynchronous Modes
(Modes 1, 2 and 3) The Serial Port has one 8-bit and two 9-bit asynchronous modes of operation. Figure 56
shows the Serial Port block diagram in such asynchronous modes.
Figure 56. Serial I/O Port Block Diagram (Modes 1, 2 and 3)
Mode 1 Mode 1 is a full-duplex, asynchronous mode. The data frame (see Figure 57) consists of
10 bits : on e s ta rt, ei ght da ta b its a nd one st op bit. S er ial data i s tr ans mitted o n the TXD
pin and re ceived on the R XD pin. When a dat a is received , the stop bit is rea d in the
RB8 bit in SCON register.
0
1
M0SRC
BDRCON.0
CK_
SI / 6
To Serial Port
IBRG
CLOCK
Baud_Rate = 6(1-SPD) ⋅ 32 ⋅ (256 -BRL)
2SMOD1 ⋅ FCK_SI
BRL = 256 -6(1-SPD) ⋅ 32 ⋅ Baud_Rate
2SMOD1 ⋅ FCK_SI
a. Fixed For mula b. Variable Formula
Baud_Rate = 6
FCK_SI
TB8
SCON.3
IBRG
CLOCK
RXD
TXDSBUF Tx SR
Rx SR
SM1
SCON.6 SM0
SCON.7
Mode D ecode r
M3 M2 M1 M0
RI
SCON.0
TI
SCON.1
Mode & Clock
Controller
SBUF Rx RB8
SCON.2
SM2
SCON.4
T1
CLOCK
CK_
SI
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Figure 57. Data Frame Format (Mode 1)
Modes 2 and 3 Modes 2 and 3 are full -duplex, asyn chronous modes. The data frame (see Figure 58)
consists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one
programma ble ninth dat a bit a nd one s top bi t. Seri al data is tran sm itted o n the TX D pin
and receiv ed on the RXD pin. On receive, the ni nth bit is read from RB8 bit in S CON
register. On transmit, the ninth data bit is written to TB8 bit in SCON register. Alterna-
tively, you can use the ninth bit as a command/data flag.
Figure 58. Data Frame Format (Modes 2 and 3)
Transmission
(Modes 1, 2 and 3) T o initiat e a trans missi on, write to SCON re gister, setting SM0 and SM1 bits ac cordin g
to Fi gure 51 o n pa ge 9 2, and s etti ng the n inth bi t by wri tin g to T B 8 b it. Th en, writi ng th e
byte to be transmitted to SBUF register starts the transmission.
Reception
(Modes 1, 2 and 3) To prepare for a reception, write to SCON register, setting SM0 and SM1 bits according
to Fi gure 51 o n pa ge 92, and set tin g RE N bi t. The actua l rec ep tio n is th en i nit ia ted by a
detected high-to-low transition on the RXD pin.
Framing Er ror D etect ion
(Modes 1, 2 and 3) F raming error detection is pr ovided for the three asy nchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register as shown in
Figure 59.
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two devices. If a valid stop bit is not found, the software sets FE bit in
SCON register.
Software may examine F E bit after each reception to c heck for data errors. Once s et,
only so ftware o r a chip rese t clear FE bit. S ubseq uently receiv ed fra mes with v alid stop
bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on
stop bit instead of the last data bit as detailed in Figure 57 and Figure 58.
Figure 59. Framing Error Block Diagram
Mode 1 D0 D1 D2 D3 D4 D5 D6 D7
Start bit 8-bit data Stop bit
Modes 2 and 3 D0 D1 D2 D3 D4 D5 D6 D8
Start bit 9-bit data Stop bit
D7
SM0
1
0
SMOD0
PCON.6
SM0/FE
SCON.7
Framing Error
Controller FE
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Baud Rate Selection
(Modes 1 and 3) In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud
Rate Generator and allows different baud rate in reception and transmission.
As shown in Figure 60 th e s election is done using RBCK and TBCK bits in BDRCON
register.
Figure 61 gives the baud rate calculation formulas for each baud rate source while
Table 71 det ails Internal Baud Rate Generato r config uration for different periphe ral
clock frequencies and giving baud rates closer to the standard baud rates.
Figure 60. Baud Rate Source Selection (Modes 1 and 3)
Figure 61. Baud Rate Formulas (Modes 1 and 3)
0
1
RBCK
BDRCON.2
T1
CLOCK To serial
IBRG
CLOCK rece pti on Port 0
1
TBCK
BDRCON.3
T1
CLOCK To serial
IBRG
CLOCK transmission Port
/ 16/ 16
Baud_Rate =6(1-SPD) ⋅ 32 ⋅ (256 -BRL)
2SMOD1 ⋅ FCK_SI
BRL = 256 - 6(1-SPD) ⋅ 32 ⋅ Baud_Rate
2SMOD1 ⋅ FCK_SI
Baud_Rate =6 ⋅ 32 ⋅ (256 -TH1)
2SMOD1 ⋅ FCK_T1
TH1 = 256 -192 ⋅ Baud_Rate
2SMOD1 ⋅ FCK_T1
a. IBRG Formula b. T1 Formula
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Notes: 1. These frequencies are achieved in X1 mode, FCK_IDLE = FOSC ÷ 2.
2. These frequencies are achieved in X2 mode, FCK_IDLE = FOSC.
Baud Rate Selection (Mode 2) In mode 2, the baud rate can only be programmed to two fixed values: 1/16 or 1/32 of
the peripheral clock frequency.
As shown in Figure 62 the selection is done using SMOD1 bit in PCON register.
Figure 63 gives the baud rate calculation formula depending on the selection.
Figure 62. Baud Rate Generator Selection (Mode 2)
Figure 63. Baud Rate Formula (Mode 2)
For mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 76)
Table 71. Internal Baud Rate Generator Value
Baud Rate
FCK_IDLE= 6 MHz(1) FCK_IDLE= 8 MHz(1) FCK_IDLE= 10 MHz(1)
SPD SMOD1 BRL Error% SPD SMOD1 BRL Error% SPD SMOD1 BRL Error%
115200 - -----------
57600 - - - - 1 1 247 3.55 1 1 245 1.36
38400 1 1 246 2.34 1 1 243 0.16 1 1 240 1.73
19200 1 1 236 2.34 1 1 230 0.16 1 1 223 1.36
9600 1 1 217 0.16 1 1 204 0.16 1 1 191 0.16
4800 1 1 178 0.16 1 1 152 0.16 1 1 126 0.16
Baud Rate
FCK_IDLE= 12 MHz(2) FCK_IDLE= 16 MHz(2) FCK_IDLE= 20 MHz(2)
SPD SMOD1 BRL Error% SPD SMOD1 BRL Error% SPD SMOD1 BRL Error%
115200 - - - - 1 1 247 3.55 1 1 245 1.36
57600 1 1 243 0.16 1 1 239 2.12 1 1 234 1.36
38400 1 1 236 2.34 1 1 230 0.16 1 1 223 1.36
19200 1 1 217 0.16 1 1 204 0.16 1 1 191 0.16
9600 1 1 178 0.16 1 1 152 0.16 1 1 126 0.16
4800 1 1 100 0.16 1 1 48 0.16 1 0 126 0.16
0
1
SMOD1
PCON.7
CK_
SI / 2 ³ 16 To Serial Port
Baud_Rate = 32
2SMOD1 ⋅ FCK_SI
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Registers
Reset Value = 0000 0000b (B it addre ssable)
76543210
FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
Bit
Number Bit
Mnemonic Description
7
FE
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0 Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
6SM1
Serial port Mode bit 1
SM0 SM1 Mode Description Baud Rate
0 0 0 Shif t Register FCk_IDLE/6
0 1 1 8-bit UART Va riable
1 0 2 9-bit UART FCK_IDLE /32 or /16
1 1 3 9-bit UART Variable
5SM2
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.
This bit should be cleared in mode 0.
4REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3TB8
Trans mitter Bit 8/Ninth bit to transmit in modes 2 and 3.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2RB8
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit tim e in mode 0 or at the beginning of the
stop bit in the other modes.
0RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 47 and Figure
48 in the other modes.
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Reset Value = 0000 0000b
Reset Value = 0000 0000b
Reset Val ue = XXXX XXX Xb
Reset Value = 0000 0000b
Table 76. Baud Rate Control Register - BDRCON - (9Bh)
Reset Value = XXX0 0000b (Not bit addressable)
Table 72. Slave Address Mask Register for UART - SADEN (B9h)
76543210
Table 73. Slave Address Register for UART - SADDR (A9h)
76543210
Table 74. Serial Buf fer Register for UART - SBU F (99h)
76543210
Table 75. Baud Rate Reload Register for the internal baud rate generator,
UART - BRL (9Ah)
76543210
76543210
---BRR TBCK RBCK SPD SRC
Bit
Number Bit
Mnemonic Description
7 - 5 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
4BRR
Baud Rate Run Control bit
Cleared to stop the internal B aud Rate Generat or.
Set to start the inter nal Baud Rate Generator.
3TBCK
Transmission Baud rate Generator Selecti on bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
2RBCK
Reception Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
1SPD
Baud Rate Spee d Cont rol bit for UART
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
0SRC
Baud Rate Source select bit in Mode 0 for UART
Cleared to select FOSC/12 as the Baud Rate Generator (FCL_IDLE/6 in X2 mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
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Serial Port Interface
(SPI) Only for AT8xC5122.
The Serial Peripheral Interface modul e (SPI) which allows full-duplex, synchronous,
serial communication between the MCU and peripheral devices, including other MCUs.
Features Features of the SPI module include the following:
•Full-duplex, three-wire synchronous transfers
•Master or Slave operation
•Eight programmable Master clock rates
•Serial clock with programmable polarity and phase
•Master Mode fault error flag with MCU interrupt capability
•Write collision flag protection
Signal Description Figure 64 show s a typical SPI bus configuration using one Master controller and many
Slave peripherals. The bus is made of three wires connecting all the devices:
Figure 64. Typical SPI Bus
The Master device selects the individual Slave devices by using four pins of a parallel
port to control the four SS pins of the Slave devices.
Master Output Slave Input
(MOSI) This 1-bit signal is directly connected between the Master Device and a Slave Device.
The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,
it is an outp ut s ig nal fr om the M as ter, a nd an input si gna l to a S la ve . A b yt e ( 8-bi t wor d)
is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
Master Input Slave Output
(MISO) This 1-bit signal is directly connected between the Slave Device and a Master Device.
The MISO line is used to transfer data in series from the Slave to the Master. Therefore,
it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit
word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
SPI Serial Clock (SCK) This signal is used to synchronize the data movement both in and out the devices
through their MOS I and MISO lines. It i s driven by the Master for eight clock cycles
which allows to exchange one byte on the serial lines.
Slave 1
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
0
1
2
3
Slave 3Slave 4
MISO
MOSI
SCK
SS
Slave 2
VDD
Master
PORT
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
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Slave Sel ect (SS )Each Slave peripheral is s elected by one Slave Select pin (SS). This signal must stay
low for any message for a Slave. Only one Master (SS high level) can drive the network.
The Mas ter m ay select e ac h S lave d ev ice by softwar e th ro ugh port pins (Figure 64). T o
prevent bus conflicts on the MISO line, only one slave should be selected at a time by
the Master for a transmission.
In a Master config urati on, the SS line c an be used i n conju nctio n with the M ODF flag i n
the SPI Status register (SPSTA) to prevent multiple masters from driving MO SI and
SCK (see Section “Error Conditions”, page 6).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
•The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the network
and there is no way that the SS pin will be pulled low. Therefore, the MODF flag in
the SPSTA will never be set (1).
•The Device is configured as a Slave with CPHA and SSDIS control bits set (2). This
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the SS pin to select the communicating Slave device.
Baud Rate In Master mode, the baud rate can be selected from a baud rate generator which is con-
troled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is
chosen from one of six clock rates resulting from the division of the internal clock by 4, 8,
16, 32, 64 or 128.
Table 77 gives the different clock rates selected by SPR2:SPR1:SPR0
Table 77. SPI Master Baud Rate Selection
1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because in
this mode, the SS is us ed to start the transmission.
SPR2:SPR1:SPR0 Clock Rate Baud Rate Divisor (BD)
000 Reserved N/A
001 FCK_SPI /4 4
010 FCK_SPI / 8 8
011 FC K_SPI /16 16
100 FCK_SPI /32 32
101 FCK_SPI /64 64
110 FCK_SPI /128 128
111 Reserved N/A
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Functional Description Figure 65 shows a detailed structure of the SPI module.
Figure 65. SPI Module Block Diagram
Operating Modes The Serial Peripheral Interface can be configured as one of the two modes: Ma ster
mode or Salve mode. The configuration and initialization of the SPI module is made
through one register:
•The Serial Peripheral Control register (SPCON)
Once the SPI is configured, the data exchange is made using:
•SPCON
•The Serial Peripheral Status register (SPSTA)
•The Serial Peripheral Data register (SPDAT)
During an SP I trans mi ssi on, da ta i s s imultaneous ly tr ans mi tted (shi fted out ser i all y) an d
receiv ed (shifted in serial ly). A s erial cloc k line ( SCK) synchr onizes sh ifting and sam-
pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows
indivi dual selecti on of a Slave SPI devic e; Slave devices that are not sel ected do not
interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave
device responds by sendi ng data to the Master device via the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the same clock
(Figure 66).
Shift Registe r01
234567
Internal Bus
Pin
Control
Logic MISO
MOSI
SCK
M
S
Clock
Logic
Clock
Divider
Clock
Select
/4
/64
/128
SPI Interrupt Request
8-bit bus
1-bit signal
SS
IntClk
/32
/8
/16 Receive Data Register
SPDAT
SPI
Control
SPSTA
CPHA SPR0
SPR1
CPOLMSTRSSDISSPENSPR2 SPCON
WCOL MODFSPIF - ----
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Figure 66. Full-duplex Master-Slave Interconnection
Maste r Mode The SPI operates in Master mode when the Master bit, MSTR (1), in the SPCON register
is set. Only one Master SPI device can initiate transmissions. Software begins the trans-
mission from a Ma ster SPI module by wr iting to the Serial Periphera l Data Register
(SPDA T). If the shift regist er is empty , the byte is immedia tely transfer red to the shi ft
register. The byte begins shifting out on MOSI pin under the control of the serial clock,
SCK. Simultaneously, another byte shifts in from the Slave on the Master’s MISO pin.
The transmi ssion ends whe n the Serial Peripheral tr ansfer data fl ag, SPIF, in SPS TA
becomes set. At the same time that SPIF becomes set, the received byte from the Slave
is transferr ed to the receive data register in SPDAT. S oftware clears SPIF by reading
the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the
SPDAT.
When the pin SS is pulled down during a transmission, the data is interrupted and when
the transmission is established again, the data present in the SPDAT is resent.
Slave Mode The SPI operates in Slave mode when the Master bit, MSTR (2), in the SPCON register is
cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave
device must be set to ’0’. SS must remain low until the transmission is complete.
In a Slave SPI module, data enters the shift register under the control of the SCK from
the Master SPI module. After a byte enters the shift register, it is immediately transferred
to the receive data register in SP DAT, and the SPIF bit is set. To prevent an overflow
condition, Slave software must then read the SPDAT befor e another byte enters the
shift register (3 ). A Sl ave SPI must compl ete the write to the SPD AT (shift reg ister) at
least one bus cycle before the Master SPI starts a transmission. I f the write to the data
register is la te, the SPI transmi ts th e data alread y in the shi ft re gister from the p revious
transmission.
Transmission Formats Software can select any of four combinations of serial cloc k (SCK) phase and polarity
using two bits in the SPCON: the Clock Polarity (CPOL (4)) and the Clock Phase
(CPHA(4)). CPOL defines the default SCK line level in idle state. It has no significant
effect on the tr ansmiss ion format. CPHA defines the edges on which the input da ta are
sampled and the edges on whi ch the outp ut data a re s hifted (Figure 67 a nd Figur e 6 8).
The clock phase and polarity should be identical for the Master SPI device and the com-
municating Slave device.
8-bit Shift Register
SPI
Clock Generator
Master MCU
8-bit Shift Register
MISOMISO
MOSI MOSI
SCK SCK
VSS
VDD SSSS Slave MCU
1. The SPI module s hould be configured as a Master before it is enabled (SPEN set). Also
the Master SPI should be configured before the Slave SPI.
2. The SPI module should be configured as a Slave before it is enabled (SPEN set).
3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock
speed.
4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).
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Figure 67. Data Transmission Format (CPHA = 0)
Figure 68. Data Transmission Format (CPHA = 1)
As shown in Figu re 67, the first SCK edge is the MSB capture strobe. Th erefore the
Slave must begin driving its data before the first SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each byte transmitted (Figure 69).
Figure 69. CPHA/SS Timing
Figure 68 shows an SPI transmission in which CPHA is “1”. In this case, the Master
begins dr iving its MOSI pi n o n the first SCK edge. T herefore, the Sl ave uses the first
SCK edge as a start trans mi ssio n signal . The S S pin can remain low between transmis-
sions (Figure 69). This format may be preferable in systems having only one Master and
only one Slave driving the MISO data line.
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
bit6 bit5 bit4 bit3 bit2 bit1MSB LSB
13245678
Capture Point
SS (to Slave)
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (internal)
SCK Cycle Number
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
bit6 bit5 bit4 bit3 bit2 bit1
MSB LSB
132 45678
Capture point
SS (to Slave)
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (internal)
SCK C y c l e Numb er
Byte 1 Byte 2 Byte 3
MISO/MOSI
Master SS
Slave SS
(CPHA = 1)
Slave SS
(CPHA = 0)
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Error Conditions The following flags in the SPSTA signal SPI error conditions.
Mode Fault (MODF) MODF error bit in Master mode SPI indicates that the level on the Slave Select (SS) pin
is inconsistent with the actual mode of the device. MODF is set to warn that there may
have a multi-master conflict for system control. In this case, the SPI system is affected in
the following ways:
•An SPI receiver/error CPU interrupt request is generated.
•The SPEN bit in SPCON is cleared. This disable the SPI.
•The MSTR bit in SPCON is cleared.
When SS Disable (SSDIS) bi t in the SPCON regi ster is cleared, the MODF flag is set
when the SS signal becomes ’0’.
However, as stated before, for a system with one Master, if the SS pi n of t he Ma ster
devi ce is pull ed low, there i s no way th at anot her Ma ster is att empti ng to dr ive the n et-
work. In this case, to prevent the MODF flag from being set, software can set the SSDIS
bit in the SPCON register and therefore making the SS pin as a general-purpose I/O pin.
Clearin g the MO DF bi t is acc omp li sh ed b y a re ad of SP STA r egi ste r with MO DF bit se t,
followed by a write to the SPCON register. SPEN Control bit may be restored to its orig-
inal set state after the MODF bit has been cleared.
Write Collision (WCOL) A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is
done during a transmit sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clear ing the WCOL bi t is done throug h a softwar e sequence of an acc ess to SPSTA
and an access to SPDAT.
Overrun Condition An ove rrun con dition o ccurs when the M aster dev ice trie s to s end sever al data bytes
and the Slave device has not cleared the SPIF bit issuing from the previous data byte
transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was
last cleared. A read of the SPDAT returns this byte. All others bytes are lost.
This condition is not detected by the SPI peripheral.
SS Erro r Flag ( SSERR ) A Synchronous Serial Slave Error occurs when SS goes high before the end of a
received data in slave mode. SSERR does not cause in interruption, this bit is cleared
by writing 0 to SPEN bit ( reset of the SPI state machine ).
Interrupts Two SPI status flags can generate a CPU interrupt requests:
Table 78. SPI Interrupts
Serial Per ipheral data transfe r flag, SPIF: This bit is set by hardware when a trans fer
has been completed. SPIF bit generates transmitter CPU interrupt requests.
Mode Fault flag, MODF: This bi t becomes set to indicate that the level on the SS is
inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error
CPU interrupt requests.
Flag Request
SPIF (SP data transfer) SPI Trans mitter Interrupt request
MODF (Mode Fault) SPI Receiver/E rror Interrupt Request (if SSDIS = ’0’)
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Figure 70 gives a logical view of the above statements.
Figure 70. SPI Interrupt Requests Generation
Registers There are thr ee registers in the module that provide control, st atus and data storage
functions. These registers are describes in the following paragraphs.
Serial Peripheral Control
Register (SPCON) The Serial Peripheral Control Register does the following:
•Selects one of the Master clock rates
•Configures the SPI module as Master or Slave
•Selects serial clock polarity and phase
•Enab le s the SP I modul e
•Free s the SS pin for a general-purpose
SSDIS
MODF
CPU Interrupt Request
SPI Receiver/error
CPU Interrupt Request
SPI Transmitter SPI
CPU Interrupt Request
SPIF
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Reset Value = 0001010 0b
Table 79. Serial Peripheral Control Register - SPCON (C3h)
76543210
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
Bit
Number Bit
Mnemonic R/W
Mode Description
7SPR2RW
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate
6 SPEN RW Serial Peripheral Enable
Clear to disable the SPI interface (internal reset of the SPI)
Set to enable the SPI interface
5SSDISRW
SS Disable
Clear to enable SS in both Master and Slave modes
Set to disable SS in both Master and Slave modes. In Slave mode, this
bit has no effect if CPHA = ’0’
4MSTRRW
Serial Peripheral Master
Clear to configure the SPI as a Slave
Set to configure the SPI as a Master
3CPOLRW
Clock Polarity
Clear to have the SCK set to ’0’ in idle state
Set to h a ve th e SCK se t to ’1’ in idle low
2CPHARW
Clock Phase
Clear to have the data sampled when the SPSCK leaves the idle state
(see CPOL)
Set to have the data sampled when the SPSCK returns to idle state
(see CPOL)
1SPR1RW
Serial Peripheral Rate (SPR2:SPR1:SPR0)
000: Reserved
001: FCK_SPI /4
010: FCK_SPI/8
011 : FCK_SPI/16
0SPR0RW
100: FCK_SPI/32
101: FCK_SPI/64
110: FCK_SPI/128
111: Reserved
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Serial Peripheral Status Register
(SPSTA) The Serial Peripheral Status Register contains flags to signal the following
conditions:
•Data transfer complete
•Write collision
•Inconsistent logic level on SS pin (mode fault error)
Reset Val ue = 00X0X XX Xb
Table 80. Serial Peripheral Status and Control Register - SPSTA (C4h)
76543210
SPIFWCOLSSERRMODF----
Bit
Number Bit
Mnemonic R/W
Mode Description
7SPIFR
Serial Peripheral data transfer flag
Clear by hardware to indicate data t ransfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
6WCOLR
Write C o llisi o n f l a g
Cleared by hardware to indicate that no c o llision has occurred or has
been approved by a clearing sequence.
Set by hardware to indicate that a collision has been det ected.
5 SSERR R Synchronous Serial Slave Error flag
Set by hardware when SS is modified before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
4MODFR
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic
level, or has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level
3 - 0 - RW Reserved
The value read from this bit is indeterm in ate. Do not change these bits.
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Serial Peripheral DATa Register
(SPDAT) The Serial Peripheral Data Register (Table 81) is a read/write buffer for the receive data
register . A write to SPD AT places data di rectly into the shift register. No tran smit buffer
is available in this model.
A read of the S PD AT returns th e v al ue lo ca ted in the r e cei ve b uffer an d n ot the co nte nt
of the shift register.
Reset Val ue = XXXX XXX Xb
Table 81. Serial Peripheral Data Register - SPDAT (C5h)
76543210
R7 R6 R5 R4 R3 R2 R1 R0
Bit Number Bit
Mnemonic Description
7-0 R7:0
Receive data bits
SPCON, SPSTA and SPDAT registers may be read and written at any time while
there is no on-going exchange. However, special care should be taken when
writing to them while a transm ission is on-going:
Do not change SPR2, SPR1 and SPR0
Do not change CPHA and CPOL
Do not change MSTR
Clearing SPEN would immediately disable the peripheral
Writing to the SPDAT will cause an overflow
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Timers/Counters The AT8xC5122 implements two general-purpose, 16-bit Timers/Counters. Although
they are identified as Timer 0, Timer 1, you can independently configure each to operate
in a v ar ie ty of m ode s as a Ti mer or as an e ven t Coun ter. When ope ra tin g as a Tim er , a
Timer/Counter runs for a programmed length of time, then issues an interrupt request.
When ope ra tin g as a Coun ter, a T im er/Coun ter c oun ts negative tr ans it ion s on an exte r-
nal pin. After a preset number of counts, the Counter issues an interrupt request.
The Timer registers and associated control registers are implemented as addressable
Special Function Registers (SFRs). Two of the SFRs provide programmable control of
the Timers as follows:
•Timer/Counter mode control register (TMOD) and Timer/Counter control register
(TCON) control respectively Timer 0 and Timer 1.
The various operating modes of each Timer/Counter are described below.
Timer/Counter
Operations For example, a basic operation is Timer registers THx and TLx (x= 0, 1) connected in
cascade to form a 16-bit Timer. Setting the run c ontrol bit (TRx) in the TCON register
(see Table 82 on page 114) turns the Timer on by allowing the selected input to incre-
ment TLx. When TLx overflows, it increments THx and when THx overflows it sets the
Timer ov erflow fl ag ( TFx) in the TC ON reg ister. S etting the TR x does not cl ear th e THx
and TLx T im er re gis te rs. T im er regis ter s can be ac ce ss ed to ob ta in th e cu rren t cou n t or
to enter pre set value s. They ca n be read at an y time but the T Rx bit mus t be clea red to
preset their values, otherwise the behavior of the Timer/Counter is unpredictable.
The C/Tx# control bit selects Timer oper ation or Counter operation by selecting the
divided-down system clock or the exte rnal pin T x as the source for the counte d signal.
The TRx bit must be cleared when changing the operating mode, otherwise the behavior
of the Timer/Counter is unpredictable.
For Timer operatio n (C/Tx#= 0), the Timer register c ounts the divided-down system
clock. The Timer register is incremented once every peripheral cycle.
Exceptions are the Timer 2 Baud Rate and Clock-Out modes in which the Timer register
is incremented by the system clock divided by two.
For Count er op eration (C/T x#= 1) , the Timer r egister co unts the neg ative tr ansi tions o n
the Tx external input pin. The external input is sampled during every S5P2 sta te. The
Programmer’s Guide des cribes the notation for the states in a peripher al cycle. When
the sample is high in one cycle and low in the next one, the Counter is incremented. The
new count value appear s in the register during the next S3P1 state after the transition
has bee n detected. Sin ce i t takes 12 s tates (24 os cilla tor periods ) to r ecogni ze a nega-
tive transit ion, the max imum count rate is 1/24 of the oscill ator frequenc y. There are no
restrictions on the duty cycle of the external input signal, but to ensure that a given level
is samp led at l east on ce befo re it chan ges, i t shoul d be hel d for at lea st one f ull per iph-
eral cycle.
Timer 0 Timer 0 functions as either a Timer or an event Counter in four operating modes.
Figure 71 through Figure 77 show the logic configuration of each mode.
Timer 0 is controll ed by the four lower bits of the TMOD r egist er (see Tab le 83 on pag e
115) and bits 0, 1, 4 and 5 of the TCON register (see Table 82 on page 114). The TMOD
register selects the meth od of Timer gating (GATE0), Timer or Counter operation
(T/C0#) and the operating mode (M10 and M00). The TCON register provides Timer 0
control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and inter-
rupt type control bit (IT0).
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AT8xC5122/23 4202B–SCR–07/03
For normal Timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by
the selected input. Setting GATE0 and TR 0 allows ex ternal pin INT0# to control Timer
operation.
Timer 0 ov erflow (count roll s over fro m all 1s to all 0s) sets the TF0 flag and ge nerates
an interru pt reques t.
It is important to stop the Timer/Counter before changing modes.
Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 reg-
ister) with a modulo-32 prescaler implemented with the lower five bits of the TL0 register
(see Figure 71). The upper three bits of the TL0 register are indeterminate and should
be ignored. Prescaler overflow increments the TH0 register.
Figure 72 gives the overflow period calculation formula.
Figure 71. Timer/Counter x (x= 0 or 1) in Mode 0
Figure 72. Mode 0 Overflow Period Formula
Mode 1 (16-bit Timer) Mo de 1 c onf igu re s Time r 0 a s a 1 6-bit Timer wi th th e TH 0 an d TL 0 regi s ter s co nne cte d
in a cascade (see Figure 73). The selected input increments the TL0 register.
Figure 74 gives the overflow period calculation formula when in timer mode.
TRx
TCON reg
TFx
TCON reg
0
1
GATEx
TMOD reg
Overflow Timer x
Interrupt
Request
C/Tx#
TMOD reg
TLx
(5 bits)
THx
(8 bits)
INTx#
Tx
FCK_Tx /6
6 ⋅ (163 84 – (THx, TLx))
TFxPER =FCK_Tx
111
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Figure 73. Timer/Counter x (x = 0 or 1) in Mode 1
Figure 74. Mode 1 Overflow Period Formula
Mode 2 (8-bit Timer with Auto-
Reload) Mode 2 con figures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads
from the TH 0 regist er (see F igure 75). TL 0 overfl ow sets the TF 0 flag in the TCO N reg-
ister and reloads TL0 with the contents of TH0, which is preset by the software. When
the interrupt request is serviced, the hardware clears TF0. The reload leaves TH0
unchan ged. The ne xt relo ad value may be changed at any time by writing it to th e TH0
register.
Figure 76 gives the autoreload period calculation formula when in timer mode.
Figure 75. Timer/Counter x (x = 0 or 1) in Mode 2
Figure 76. Mode 2 Autoreload Period Formula
TRx
TCON reg
TFx
TCON reg
0
1
GATEx
TMOD reg
Overflow Timer x
Interrupt
Request
C/Tx#
TMOD reg
TLx
(8 bits)
THx
(8 bits)
INTx#
Tx
FCK_Tx /6
6 ⋅ (65536 – (THx, TLx))
TFxPER = FCK_Tx
TRx
TCON reg
TFx
TCON reg
0
1
GATEx
TMOD reg
Overflow Timer x
Interrupt
Request
C/Tx#
TMOD reg
TLx
(8 bits)
THx
(8 bits)
INTx#
Tx
FCK_Tx /6
TFxPER=FCK_Tx
6 ⋅ (256 – THx)
112
AT8xC5122/23 4202B–SCR–07/03
Mode 3 (Two 8-bit Timers) Mode 3 co nfigu res Time r 0 s o th at r egi sters TL0 an d TH0 oper ate as 8-bit Timer s (see
Figure 77). This mode is provided for applications requiring an additio nal 8-bit Timer or
Coun t e r. TL 0 us es the Ti me r 0 c on t ro l bi t s C / T0 # an d GATE0 in th e T MO D r e gi st e r, a nd
TR0 and T F0 in the TCON regi ster in the norm al manner. TH0 is locked into a T imer
function (counting FUART) and takes over use of the Timer 1 interrupt (TF1) and run con-
trol (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode 3.
Figure 78 gives the autoreload period calculation formulas for both TF0 and TF1 flags.
Figure 77. Timer/Counter 0 in Mode 3: Two 8-bit Counters
Figure 78. Mode 3 Overflow Period Formula
Timer 1 Timer 1 is identical to Timer 0 except for Mode 3 which is a hold-count mode. The fol-
lowing comments help to understand the differences:
•Timer 1 functions as either a Timer or an event Counter in three operating modes.
Figure 71 through Figure 75 show the logical configuration for modes 0, 1, and 2.
Mode 3 of Timer 1 is a hold-count mode.
•Timer 1 is controlled by the four high-order bits of the TMOD register (see Table 83
on page 115) and bits 2, 3, 6 and 7 of the TCON register (see Table 82 on page
114). The TMOD register selects the method of Timer gating (GATE1), Timer or
Counter operation (C/T1#) and the operating mode (M11 and M01). The TCON
register provides T imer 1 control functions: overflow flag (TF1), run control bit (TR1),
interrupt flag (IE1) and the interrupt type control bit (IT1).
•Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best
suited for this purpose.
•For normal T imer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented
by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control
Timer operation.
•Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag and
generates an interrupt request.
TR0
TCON.4
TF0
TCON.5
INT0#
0
1
GATE0
TMOD.3
Overflow Timer 0
Interrupt
Request
C/T0#
TMOD.2
TL0
(8 bits)
TR1
TCON.6
TH0
(8 bits) TF1
TCON.7
Overflow Timer 1
Interrupt
Request
T0
FCK_T0 /6
FCK_T0 /6
TF0PER = FCK_T0
6 ⋅ (256 – TL0) TF1PER =FCK_T0
6 ⋅ (256 – TH0)
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•When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit
(TR1). For this situation, use Timer 1 only for applications that do not require an
interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in
and out of mode 3 to turn it off and on.
•It is important to stop the Timer/Counter before changing modes.
Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-
ister) with a modulo-32 prescaler implemented with the lower 5 bits of the T L1 register
(see Figure 71). The uppe r 3 bits of TL1 regi ster ar e ignor ed. Pre scaler overflo w incr e-
ments the TH1 register.
Mode 1 (16-bit Timer) Mode 1 configures T imer 1 as a 16-bit Timer with TH1 and TL1 registers connected in
cascade (see Figure 73). The selected input increments the TL1 register.
Mode 2 (8-bit Timer with Auto-
Reload) Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from
the TH1 register on overflow (see Figure 75 ). TL1 overfl ow sets the T F1 flag in the
TCON r egister and re loads TL1 with the co ntents of TH 1, which is preset by th e soft-
ware. The reload leaves TH1 unchanged.
Mode 3 (Halt) Placi ng Timer 1 in mo de 3 causes it to halt and hold i ts count. T his can be use d to halt
Timer 1 when the TR1 run control bit is not available i.e. when Timer 0 is in mode 3.
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Registers Ti mer/Counter Control Register
Reset Value = 0000 0000b
Table 82. TC ON (S:88h)
76543210
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Bit
Number Bit
Mnemonic Description
7TF1
Timer 1 Overflow flag
Cleared by the hardware when processor vectors interrupt routine.
Set by the hardware on Timer/Counter overflow when T imer 1 register overflows.
6TR1
Timer 1 Run Con trol bit
Clear to turn off Timer/Counter 1.
Set to turn on Timer/Counter 1.
5TF0
Timer 0 Overflow flag
Cleared by the hardware when processor vectors interrupt routine.
Set by the hardware on Timer/Counter overflow when T imer 0 register overflows.
4TR0
Timer 0 Run Con trol bit
Clear to turn off Timer/Counter 0.
Set to turn on Timer/Counter 0.
3IE1
Interrupt 1 Edge flag
Cleared by the hardware when interrupt is processed if edge- triggere d (see IT1).
Set by the hardware when external interrupt is detected on the INT1# pin.
2IT1
Interrupt 1 Type Control bit
Clear to select low level active (level triggered) for external interrupt 1 (INT1#).
Set to select falling edge active (edge triggered) fo r external interrupt 1.
1IE0
Interrupt 0 Edge flag
Cleared by the hardware when interrupt is processed if edge- triggere d (see IT0).
Set by the hardware when external interrupt is detected on IN T0# pin.
0IT0
Interrupt 0 Type Control bit
Clear to select low level active (level triggered) for external interrupt 0 (INT0#).
Set to select falling edge active (edge triggered) fo r external interrupt 0.
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Reset Value = 0000 0000b
Table 83. Timer/Counter Mode Control Register - TMOD (S:89h)
76543210
GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00
Bit Number Bit Mnemonic Description
7GATE1
Timer 1 Gating Control bit
Clear to enable Timer 1 whenever TR1 bit is set.
Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set.
6C/T1#
Timer 1 Counter/Timer Select bit
Clear for Timer operation: Timer 1 counts the divided-down system clock.
Set for Counter operation: Timer 1 counts negative transitions on external pin T1.
5M11Timer 1 Mode Select bits
M11 M01 Operating mode
0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1).
0 1 Mode 1:16-bit Timer/Counter.
1 0 Mode 2:8-bit auto-reload Ti mer/Counter (TL1). Reloaded from TH1 at overflow.
1 1 Mode 3:Timer 1 halted. Retains count.
4M01
3GATE0
Timer 0 Gating Control bit
Clear to enable Timer 0 whenever TR0 bit is set.
Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set.
2C/T0#
Timer 0 Counter/Timer Select bit
Clear for Timer operation: Timer 0 counts the divided-down system clock.
Set for Counter operation: Timer 0 counts negative transitions on external pin T0.
1M10Timer 0 Mode Select bit
M10 M00 Operating mode
0 0 Mode 0:8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0).
0 1 Mode 1:16-bit Timer/Counter.
1 0 Mode 2:8-bit auto-reload Timer /Counter (TL0). Reloaded from TH0 at overflow.
1 1 Mode 3:TL0 is an 8-bit Ti mer /Counter.
TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.
0M00
116
AT8xC5122/23 4202B–SCR–07/03
Reset Value = 0000 0000b
Reset Value = 0000 0000b
Reset Value = 0000 0000b
Reset Value = 0000 0000b
Table 84. Timer 0 High Byte Register - TH0 (S:8Ch)
76543210
Bit Number Bit
Mnemonic Description
7:0 High Byte of Timer 0
Table 85. Timer 0 Low Byte Register - TL0 (S:8Ah)
76543210
Bit
Number Bit
Mnemonic Description
7:0 Low Byte of Timer 0
Table 86. Timer 1 High Byte Register - TH1 (S:8Dh)
76543210
Bit Number Bit
Mnemonic Description
7:0 High Byte of Timer 1
Table 87. Timer 1 Low Byte Register - TL1 (S:8Bh)
76543210
Bit Number Bit
Mnemonic Description
7:0 Low Byte of Timer 1
117
AT8xC5122/23
4202B–SCR–07/03
Keyboard Interface Only for AT8xC5122.
Introduction The AT8x C5122/23 imple ments a k eyboar d inter face allow ing the c onnec tion of a 8 x n
matri x keyboa rd. It is based on 8 inputs with pro grammab le in terrupt capabi lity on bot h
high or low level. These inputs are available as alternate function of P5 and allow to exit
from idle and power-down modes.
Description The keyboard inter faces with the C51 core through 3 special function registers: KBLS,
the Keyboard Lev el Selection register (Table 90 o n page 120), KBE, The Keybo ard
inter rupt Ena ble regi ster ( Table 89 on pag e 119), an d KBF, th e Keybo ard Fl ag regist er
(Table ).
Interrupt The keyboard inputs are considered as 8 independent interrupt sources sharing the
same in terrup t vector . An inte rrupt en able bit ( KBD in IE1 ) allows gl obal ena ble or di s-
able of the keyboard interrupt (see Figure 79). As detailed in Figure 80 each keyboard
input has the capability to detect a programmable level according to KBLS.x bit value.
Level detection is then reported in interrupt flags KBF.x that can be masked by software
using KBE.x bits.
This structure allows keyboard arrangement from 1 by n to 8 by n matrix and allows
usage of P5 inputs for other purpose.
The KB F.x flags a re set by har dware when a n active lev el is on in put P5.x. The y are
automatically reset after an y read access on KB F. If the content of KBF must be ana-
lyzed, th e first r ead instr uctio n must tran sfer KBF contend to anot her locat ion. The K BF
register cannot be written by software.
Figure 79. Keyboard Interface Block Diagram
Figure 80. Keyboard Input Circuitry
P5.0
Keyb oard Interface
Interr upt Requ est
EKB
IEN1.0
Input Circuitry
P5.1 Input Circuitry
P5.2 Input Circuitry
P5.3 Input Circuitry
P5.4 Input Circuitry
P5.5 Input Circuitry
P5.6 Input Circuitry
P5.7 Input Circuitry
KBDIT
P5.x
KBE.x
KBF.x
KBLS.x
0
1
118
AT8xC5122/23 4202B–SCR–07/03
Power Reduction Mode P5 inputs allow exit from idle and power-down modes as detailed in Section "Power-
Down Mode".
Registers
Reset Value = 0000 0000b
Table 88. Keyboard Flag Register - KBF (9Eh)
76543210
KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
Bit
Number Bit
Mnemonic Description
7KBF7
Keyboard line 7 flag
Set by hardware when the Port line 7 detects a programmed level. It generates a
Keyboard interrupt request if the KBKBIE.7 bit in KBIE register is set.
Cleared by hardware after the read of the KBF register .
6KBF6
Keyboard line 6 flag
Set by hardware when the Port line 6 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.6 bit in KBIE register is set.
Cleared by hardware after the read of the KBF register .
5KBF5
Keyboard line 5 flag
Set by hardware when the Port line 5 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.5 bit in KBIE register is set.
Cleared by hardware after the read of the KBF register .
4KBF4
Keyboard line 4 flag
Set by hardware when the Port line 4 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.4 bit in KBIE register is set.
Cleared by hardware after the read of the KBF register .
3KBF3
Keyboard line 3 flag
Set by hardware when the Port line 3 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.3 bit in KBIE register is set.
Cleared by hardware after the read of the KBF register .
2KBF2
Keyboard line 2 flag
Set by hardware when the Port line 2 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.2 bit in KBIE register is set.
Cleared by hardware after the read of the KBF register .
1KBF1
Keyboard line 1 flag
Set by hardware when the Port line 1 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.1 bit in KBIE register is set.
Cleared by hardware after the read of the KBF register .
0KBF0
Keyboard line 0 flag
Set by hardware when the Port line 0 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.0 bit in KBIE register is set.
Cleared by hardware after the read of the KBF register .
119
AT8xC5122/23
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Reset Value = 0000 0000b
Table 89. Keyboard Input Enable Register - KBE (9Dh)
76543210
KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
Bit
Number Bit
Mnemonic Description
7 KBE7 Keyboard line 7 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.7 bit in KBF register to generate an interrupt request.
6 KBE6 Keyboard line 6 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.6 bit in KBF register to generate an interrupt request.
5 KBE5 Keyboard line 5 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.5 bit in KBF register to generate an interrupt request.
4 KBE4 Keyboard line 4 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.4 bit in KBF register to generate an interrupt request.
3 KBE3 Keyboard line 3 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.3 bit in KBF register to generate an interrupt request.
2 KBE2 Keyboard line 2 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.2 bit in KBF register to generate an interrupt request.
1 KBE1 Keyboard line 1 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.1 bit in KBF register to generate an interrupt request.
0 KBE0 Keyboard line 0 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.0 bit in KBF register to generate an interrupt request.
120
AT8xC5122/23 4202B–SCR–07/03
Reset Value = 0000 0000b
Table 90. Keyboard Level Selector Register - KBLS (9Ch)
76543210
KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
Bit
Number Bit
Mnemonic Description
7KBLS7
Keyboard line 7 Level Selection bit
Cleared to enable a low lev el detection on Port line 7.
Set to enable a high level detection on Port line 7.
6KBLS6
Keyboard line 6 Level Selection bit
Cleared to enable a low lev el detection on Port line 6.
Set to enable a high level detection on Port line 6.
5KBLS5
Keyboard line 5 Level Selection bit
Cleared to enable a low lev el detection on Port line 5.
Set to enable a high level detection on Port line 5.
4KBLS4
Keyboard line 4 Level Selection bit
Cleared to enable a low lev el detection on Port line 4.
Set to enable a high level detection on Port line 4.
3KBLS3
Keyboard line 3 Level Selection bit
Cleared to enable a low lev el detection on Port line 3.
Set to enable a high level detection on Port line 3.
2KBLS2
Keyboard line 2 Level Selection bit
Cleared to enable a low lev el detection on Port line 2.
Set to enable a high level detection on Port line 2.
1KBLS1
Keyboard line 1 Level Selection bit
Cleared to enable a low lev el detection on Port line 1.
Set to enable a high level detection on Port line 1.
0KBLS0
Keyboard line 0 Level Selection bit
Cleared to enable a low lev el detection on Port line 0.
Set to enable a high level detection on Port line 0.
121
AT8xC5122/23
4202B–SCR–07/03
Interrupt System The AT 8xC5122/23 imple ments an interru pt controller wit h 15 inputs but onl y 9 are
used: two external interrupts (INT0 and INT1), two timer interrupts (timers 0, 1), the
serial port interrupt, SPI interrupt, Keyboard interrupt, USB interrupt and the SCIB global
interrupt.
122
AT8xC5122/23 4202B–SCR–07/03
Figure 81. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Inte rrupt Ena ble regi sters ( Table 92 on page 12 5 and Tabl e 93 on page
126). These registers also contain a global disable bit, which must be cleared to disable
all interrupts at once.
IE0
SPI
SMA RT C ARD
INT1/OE
CPRES
RXD
RXEN
0
1IE1
1
0
0
1PRESIT
ISEL.0
ISEL.4
RXIT
OEEN
ISEL.2
OELEV
ISEL.3 IT1
TCON.2
TCON.3
PRESEN
ISEL.1
CPLEV
ISEL.7
ISEL.5
0
1
IT0
TCON.0
TF0
TF1
RI
TI
ET1
IEN0.3
EUSB
IEN1.6
ES
IEN0.4
EX0
IEN0.0
00
01
10
11
EA
IEN0.7
ET0
IEN0.1
EX1
IEN0.2
EKB (1)
IEN1.0
ESPI (1)
IEN1.2
IPH/L
Interrupt Enable Lowest Priority
Priority Enable
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
ESCI
IEN1.3
00
01
10
11
Highest Priority
Interrupts
Interrupts
TCON.1
INT0#
RXD
TXD
D+
D-
CIO
CCLK
MOSI
SCK
MISO
TCON.5
TCON.7
SCON.0
SCON.1
P5.x 0
1KBFx
KBExKBLSx
SERIAL
INTERFACE
CONTROLLER
CONTROLLER
USB
CONTROLLER
CONTROLLER
INTERFACE
note (1): only for AT8xC5122
(1)
123
AT8xC5122/23
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Each interrupt source can also be individually programmed to one out of four priority lev-
els by setting or clearing a bit in the Interrupt Priority Low regis ters (Table 95 on page
127 and Table 97 on page 129) and in the Interrupt Priority High register (Table 96 on
page 128 and Table 99 on page 131) shows the bit values and priority levels associated
with each combination.
INT1 Interrupt Vector The INT1 interrupt is multiplexed with the following three inputs:
•INT1/OE: Standard 8051 interrupt input
•RXD: Received data on UART
•CPRES: Insertion or remove of the main card
The setting configurations for each input is detailed below.
INT1/OE Input This interrupt input is active under the following conditions :
•It must be enabled by OEEN Bit (ISEL Register)
•It can be active on a level or falling edge following IT1 Bit (TCON Register) status
•If le vel t rig geri ng select ion is s et, t he act ive l evel 0 or 1 ca n be sel ect ed wi th OELEV
Bit (ISEL Register)
The Bit IE1 (TCON Register) is set by hardware when external interrupt detected. It is
cleared when interrupt is processed.
RXD Input A se cond ve ct or interru pt input i s the rec eption of a charac ter. U ART Rx inp ut can g en-
erate an interrupt if enabled with Bit RXEN (ISEL.0). The global enable bits EX1 and EA
must also be set.
Then, the Bit RXIT (ISEL Register) is set by hardware when a low level is detected on
P3.0/RXD input.
CPRES Input The thir d input is the dete cti on o f a le ve l c han ge o n CPRES inp ut ( P1 .2). T hi s input can
generate an interrupt if enabled with PRES EN (ISEL.1) , EX1 (IE0.2) and EA (IE0.7)
Bits.
This detection is done according to the level selected with Bit CPLEV (ISEL.7).
Then the Bit PRESIT ( ISEL.5) is set by hardware when the triggering conditions are
met. This Bit must be cleared by software.
Registers A low-priori ty inte rrupt can be int errupt ed by a high prior ity i nterru pt, b ut no t by an other
low-priority in terrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
reques t of high er prio rity lev el is s ervic ed. If in terrupt r eques ts of th e same priori ty leve l
are received simultaneously, an internal polling sequence determines which request is
serviced first. T hus within each p riority level the re is a second prior ity structure deter-
mined by the polling sequence.
124
AT8xC5122/23 4202B–SCR–07/03
Table 91. Priority Level Bit Values
IPH.x IPL.x I nterrupt Level Priority
0 0 0 (Lowest)
011
102
1 1 3 (Highest)
125
AT8xC5122/23
4202B–SCR–07/03
Reset Value = 0000 0000b (B it addre ssable)
Table 92. Interrupt Enable Register 0 - IEN0 (A8h)
76543210
EA - - ES ET1 EX1 ET0 EX0
Bit
Number Bit
Mnemonic Description
7EA
Enab le A ll interr u pt b it
Cleared to disable all int errupts.
Set to enable all interrupts.
6 - 5 - Reserved
The value read from this bit is indeterm inate. Do not change these bits.
4ES
Serial port Enable bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
3ET1
Timer 1 overflow interrupt Enable bit
Cleared to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2EX1
Exter na l int e rrupt 1 Enable bit
Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
1ET0
Timer 0 overflow interrupt Enable bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0EX0
Exter na l int e rrupt 0 Enable bit
Cleared to disable external interrupt 0.
Set to enable external interrupt 0.
126
AT8xC5122/23 4202B–SCR–07/03
Reset Value = X0XX 00X 0b (Bit addressable)
Table 93. Interrupt Enable Register 1 - IEN1 (B1h) for AT8xC5122
76543210
- EUSB - - ESCI ESPI - EKB
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterm i nate. Do not change this bit.
6EUSB
USB Interrupt Enable bit
Cleared to disable USB interrupt .
Set to enable USB interrupt.
5 - 4 - Reserved
The value read from this bit is indeterm i nate. Do not change these bits.
3ESCI
SCI interrupt Enable bit
Cleared to disable SCIinterrupt .
Set to enable SCI interrupt.
2 ESPI SPI interrupt Enable bit
Cleared to disable SPI interrupt .
Set to enable SPI interrupt.
1-
Reserved
The value read from this bit is indeterm i nate. Do not change this bit.
0EKB
Keyboard inter r upt Enable bit
Cleared to disable keyboard interrupt .
Set to enable keyboard interrupt.
127
AT8xC5122/23
4202B–SCR–07/03
Reset Value = X0XX 0X XX b (Bit addr essable)
Reset Value = X000 0000b (Bit addressable)
Table 94. Interrupt Enable Register 1 - IEN1 (B1h) for AT8xC5123
76543210
-EUSB- -ESCI -
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterm i nate. Do not change this bit.
6EUSB
USB Interrupt Enable bit
Cleared to disable USB interrupt .
Set to enable USB interrupt.
5 - 4 - Reserved
The value read from this bit is indeterm i nate. Do not change these bits.
3ESCI
SCI interrupt Enable bit
Cleared to disable SCIinterrupt .
Set to enable SCI interrupt.
2Reserved
The value read from this bit is indeterm i nate. Do not change this bit.
1-
Reserved
The value read from this bit is indeterm i nate. Do not change this bit.
0Reserved
The value read from this bit is indeterm i nate. Do not change this bit.
Table 95. Interrupt Priority Low Register 0 - IPL0 (B8h)
76543210
- - - PSL PT1LPX1LPT0LPX0L
Bit
Number Bit
Mnemonic Description
7 - 5 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
4PSL
Serial port Priority bit
Refer to PSH for priority level.
3PT1L
Timer 1 o verflow interrupt Priority bit
Refer to PT1H for priority l evel.
2 PX1L External interrupt 1 Priority bit
Refer to PX1H for priority level.
1PT0L
Timer 0 o verflow interrupt Priority bit
Refer to PT0H for priority l evel.
0 PX0L External interrupt 0 Priority bit
Refer to PX0H for priority level.
128
AT8xC5122/23 4202B–SCR–07/03
Reset Value = X000 0000b (Not bit addressable)
Table 96. Interrupt Priority High Register 0 - IPH0 (B7h)
76543210
- - - PSH PT1H PX1H PT0H PX0H
Bit
Number Bit
Mnemonic Description
7 - 5 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
4PSH
Seria l por t Priority High bit
PSH PSL Priority Level
0 0 Lowest
01
10
1 1 Highest
3PT1H
Timer 1 ov e r flow interrupt Priority High bit
PT1H PT1L Priority Level
0 0 Lowest
01
10
1 1 Highest
2PX1H
External interrupt 1 Priority High bit
PX1H PX1L Priority Level
0 0 Lowest
01
10
1 1 Highest
1PT0H
Timer 0 ov e r flow interrupt Priority High bit
PT0H PT0L Priority Level
0 0 Lowest
01
10
1 1 Highest
0PX0H
External interrupt 0 Priority High bit
PX0H PX0L Priority Level
0 0 Lowest
01
10
1 1 Highest
129
AT8xC5122/23
4202B–SCR–07/03
Reset Value = X00X 00X0b (Bit addressable)
Table 97. Interrupt Priority Low Register 1 - IPL1 (B2h) for AT8xC5122
76543210
- PUSBL - - PSCIL PSPIL - PKBDL
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
6PUSBL
USB Interrupt Priority bit
Refer to PUSBH for priority level.
5 - 4 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
3PSCIL
SCI Interrupt Priority bit
Refer to PSPIH for priority level.
2 PSPIL SPI Int e rr upt Priority b it
Refer to PSPIH for priority level.
1-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
0PKBL
Keyboard Interrupt Priority bit
Refer to PKBDH for priority level.
130
AT8xC5122/23 4202B–SCR–07/03
Reset Value = X0XX 0X XX b (Bit addr essable)
Table 98. Interrupt Priority Low Register 1 - IPL1 (B2h) for AT8xC5123
76543210
- PUSBL - - PSCIL
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
6PUSBL
USB Interrupt Priority bit
Refer to PUSBH for priority level.
5 - 4 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
3PSCIL
SCI Interrupt Priority bit
Refer to PSPIH for priority level.
2Reserved
The value read from this bit is indeterminate. Do not change this bit.
1Reserved
The value read from this bit is indeterminate. Do not change this bit.
0Reserved
The value read from this bit is indeterminate. Do not change this bit.
131
AT8xC5122/23
4202B–SCR–07/03
Reset Value = XXXX X000b (Not bit addressable)
Table 99. Interrupt Priority High Register 1 - IPH1 (B3h) for AT8xC5122
76543210
- PUSBH - - PSCIH -
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
6PUSBH
USB Interrupt Priotity High bit
PUSBH PUSBL Priority Level
0 0 Lowest
01
10
1 1 Highest
5-4 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
3PSCIH
SCI Inter rupt Priority High bit
PSCIH PSCIL Priority Level
0 0 Lowest
01
10
1 1 Highest
2PSPIH
SPI Interrupt Priority High bit
PSPIH PSPIL Priority Level
0 0 Lowest
01
10
1 1 Highest
1-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
0PKBH
Keyboard Interrupt Priority High bit
PKBDH PKBDL Priority Level
0 0 Lowest
01
10
1 1 Highest
132
AT8xC5122/23 4202B–SCR–07/03
Reset Value = X0XX 0X XX b (Not bit addre ssable)
Table 100. Interrupt Priority High Register 1 - IPH1 (B3h) for AT8xC5123
76543210
-PUSBH--PSCIH---
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
6PUSBH
USB Interrupt Priotity High bit
PUSBH PUSBL Priority Level
0 0 Lowest
01
10
1 1 Highest
5-4 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
3PSCIH
SCI Inter rupt Priority High bit
PSCIH PSCIL Priority Level
0 0 Lowest
01
10
1 1 Highest
2Reserved
The value read from this bit is indeterminate. Do not change these bits.
1-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
0Reserved
The value read from this bit is indeterminate. Do not change these bits.
133
AT8xC5122/23
4202B–SCR–07/03
Reset Value = 0000 0000b
Table 101. Interrupt Enable Register - ISEL (S:A1h)
76543210
CPLEV - PRESIT RXIT OELEV OEEN PRESEN RXEN
Bit
Number Bit
Mnemonic Description
7CPLEV
Card presence detection level
This bit indicates which CPRES level will bring about an interrupt
Set this bit to indicate that Card Presence IT will appear if CPRES is at high
level.
Clear this bit to indicate that Card Presence IT will appear if CPRES is at low
level.
6-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
5PRESIT Card presence detection interrupt flag
Set by hardware
Must be cleared by software
4RXIT Received data interrupt flag
Set by hardware
Must be cleared by software
3OELEV OE/INT1 signal active level
Set this bit to indicate that high level is active.
Clear this bit to indicate that low level is active.
2OEEN OE/INT1 Interrupt Disable bit
Clear to disable INT1 interrupt
Set to enable INT1 interrupt
1PRESEN Card presence detection Interrupt Enable bit
Clear to disable the card presence detection interrupt coming fr om SCI B.
Set to enable the c ard presenc e detection interrupt coming from SCIB.
0RXEN
Received data In terrupt Enable bit
Clear to disable the RxD interrupt.
Set to enable the RxD interrupt (a minimal bit width of 100 µs is required to
wake up from power-down) .
134
AT8xC5122/23 4202B–SCR–07/03
Interrupt Sources and
Vector Addresses
Note: 1. Only fot AT8xC5122
Table 102. Interrupt Vectors
Interrupt Source Polling Priority
at Same Level Vector
Address
Reset 0
(Highest Pr iority) C:0000h
INT0 1 C:0003h
Timer 0 2 C:000Bh
INT1 3 C:0013h
Timer 1 4 C:001Bh
UART 6 C:0023h
Reserved 7 C:002Bh
Reserved 5 C:0033h
Keyboard Controller (1) 8 C:003Bh
Reserved 9 C:0043h
SPI Controller (1) 10 C:004Bh
Smart Card Controller 11 C:0053h
Reserved 12 C:005Bh
Reserved 13 C:0063h
USB Controller 14 C:006Bh
Reserved 15
(Lowest Priority) C:0073h
135
AT8xC5122/23
4202B–SCR–07/03
Reset and Power
Monitor
Reset From the system point of view, the reset controller must provide the following four
functions:
•an active reset each time the reset pin is set to a low state.
•an active reset during power on sequence without the need of external components
•a device protection for preventing code execution if the power supply goes out of the
functional range of the microcontroller’s core.
•a watchdog function
Therefore the RESET controller is fed by three sources:
- Signal coming from Reset pin
- Signal coming from Power Monitor circuit assuring the Power On Reset and the Power
Fail detect functions
- Watchdog circuit
136
AT8xC5122/23 4202B–SCR–07/03
Figure 82. Reset Controller
Regulator
3.3V
Vss
DVcc
RST
C51 core
Vcc
VPFDM VPFDP
DVcc
VPFD
0
1
VPFD
Vcc
Xtal2
Xtal1
OSC.
Watchdog Ou tput
Internal Reset
0
1
1024 COUNTER
Time
Q
Time
1024*TCLKOUT
VPFD
Clkin
Q
Vcc/2-0.5 Vcc/2+0.5
Clkin
CLKOUT
0
1
POWER MONITOR
ANALOG BUF F ER
CLKOUT
137
AT8xC5122/23
4202B–SCR–07/03
Power Monitor
Overview The Power Monitor function supervises the evolutions of the voltages feeding the micro-
controller, and if needed, suspends its activity when the detected value is out of
specification.
It guarantees to start up properly when AT8xC5122 is powered up and prevents code
execution e rrors when the r egulated power su pply become s lower than the functional
threshold.
This section describes the functions of the Power Monitor.
Description In order to startup and to maintain properly the microcontroller operation, VCC has to be
stabilized in the VCC operating range and the oscillator has to be stabilised with a nom-
inal amplitude compatible with logic threshold.
This control is carried out during three phases which are the power-up, normal operation
and stop. So it is in accordance with the following requirements:
•it guarantees an operationnal Reset when the microcontroller is powered
•and a protection if the power supply goes out from the functional range of the
microcontroller.
Figure 83. Power Monitor Block Diagram
Power Monitor Diagram The target of the Power monitor is to survey the power-supply in order to detect any volt-
age dro ps whi ch ar e not i n th e t ar get sp ec ifi cat io n. Th is P owe r Mon ito r ch ecks two kin d
of situations which occur:
•during the power-up condition, when VCC is reaching the product specification,
•during a steady-state condition, when VCC is stable but disturbed by any
undesirable voltage drops.
Figure 84 shows some configurations which can be met by the Power monitor.
External
Power-Supply
DC to DC
3.3V Regulator
VCC
DVCC
CVCC
Internal RESET
Power Fail
Detector
Power up
Detector
138
AT8xC5122/23 4202B–SCR–07/03
Figure 84. Power-up and Steady-state Conditions Monitored
Such device when it is integrated in a microcontroller, forces the CPU in reset mode
when VCC reaches a voltage condition which is out of the specification.
The thresholds and their functions are:
•VPFDP: the output voltage of the regulator has reached a minimum functional value
at the power-up. The circuit leaves the RESET mode.
•VPFDM: the output voltage of the regulator has reached a low threshold functional
value for the microcontroller. An internal RESET is set.
A glitch fil tering pr events the s ystem to RESE T when shor t duration gl itche s are carrie d
on DVCC power-sup ply .
Power-up Steady State Cond it ion
DVCC
t
Reset
VPFDP
VPFDM
tG
Vcc
139
AT8xC5122/23
4202B–SCR–07/03
Watchdog Timer AT 8xC5122 co ntain s a p ower full p rog rammab le h ardwar e W atchdo g T ime r (WDT ) tha t
automatical ly resets the chip if its software fails to reset the WDT before the selecte d
time interval has elapsed. It permits large Timeout ranking from 16 ms to 2s @Fosc = 12
MHz.
This WD T cons ist of a 14- bit cou nter plus a 7 - bit pro gramm able co unter , a Watch dog
Timer reset register (WDTRST) and a Watchdog Timer programmation (WDTPRG) reg-
ister. When e xitin g reset, the WD T is -by de fault- disa ble. To enable the W DT, the user
has to write the sequence 1EH and E1H into WDRST regis ter. When the Watchdog
Time r is enabled, i t will incre ment ever y machine cy cle while th e oscillato r is runnin g
and there is no way to disable the WDT except through reset (either hardware reset or
WDT overflow reset). When WDT overflows, it will generate an output RESET pulse at
the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the
best use of the WDT, it should be serviced in those sections of code that will periodically
be executed within the time required to prevent a WDT reset.
The WDT is controlled by two registers (WDTRST and WDTPRG).
Figure 85. Watchdog Timer
RESET Decoder
Control
WDTRST
WR
Enable
14-bit COUNTER 7 - bit COUNTER
Outputs
FCK_WD
RESET
- - -
- - 2 1 0
WDTPRG
140
AT8xC5122/23 4202B–SCR–07/03
Reset Val ue = XXXX X000b
The three lower bits (S0, S1, S2) located into WDTPRG register enables to program the
WDT duration.
To compute WD Timeout, the following formula is applied:
Time Out = 6 * (214 * 2 Svalue - 1 ) / FCK_WD
Note: Svalue represents the decimal va lue of (S2 S1 S0) / CKRL repres ents the Prescaler
Table 103. Watchdog Timer Out Register - WDTPRG (0A7h)
76543210
-----S2S1S0
Bit
Number Bit
Mnemonic Description
7 - 3 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
2 S2 WDT Time-out select bit 2
1 S1 WDT Time-out select bit 1
0 S0 WDT Time-out select bit 0
Table 104. Machine Cycle Count
S2 S1 S0 Machine Cycle Count
000 2
14 - 1
001 2
15 - 1
010 2
16 - 1
011 2
17 - 1
100 2
18 - 1
101 2
19 - 1
110 2
20 - 1
111 2
21 - 1
141
AT8xC5122/23
4202B–SCR–07/03
Table 105. Timeout value for Fosc = 12 MHz
Reset Val ue = XXXX XXX Xb
The WDTRST regis ter is used to reset/enable the W DT by writing 1EH then E1H in
sequence.
Watchdog Timer During
Power-down Mode and
Idle
In Power-down m ode the osc illator stops, whi ch means th e WDT also s tops. While i n
Power-down mode the us er doe s not need to se rvi ce t he W DT . The re are 2 methods of
exiting Power-down mode: by a hardware reset or via a level activated external interrupt
which is enabl ed p rior to e nterin g Po wer-do wn mo de. W hen Powe r-down is e xited wit h
hardware reset, servicing the WDT should occur as it normally does whenever
AT8xC5122 is reset. Exiting Power-down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabiliz e. When the interrupt is
brough t high, the inter rupt is service d. To prevent th e WDT from reset ting the devi ce
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is su ggested tha t the WDT be rese t during th e interr upt servi ce for the interrup t used
to exit Power-down.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it
is best to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from re setting
while in Idle mode, the user should always set up a timer that will periodically exit Idle,
service the WDT, and re-enter Idle mode.
S2 S1 S0 Timeout for FCK_WD= 6 MHz
0 0 0 16.38 ms
0 0 1 32.77 ms
0 1 0 65.54 ms
0 1 1 131.07 ms
1 0 0 262.14 ms
1 0 1 524.29 ms
1 1 0 1.05 s
1 1 1 2.10 s
Table 106. Watchdog Timer Enable register (Write Only) - WDTRST (A6h)
76543210
--------
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AT8xC5122/23 4202B–SCR–07/03
Power Management
Idle Mode An in structi on that sets PCON.0 indica tes that it is the las t inst ructio n to b e execute d
before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to
the CPU, b ut not to the inter rupt, Tim er, and Se rial Por t functions. The CP U status is
preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word,
Accumulat or and all other register s maintain thei r data during I dle. The por t pins hold
the logical states they had at the time Idle was activated. ALE and PSEN hold at logic
high level.
There are two ways to terminate the Idle mode. Activation of any enabled interrupt will
cause PCON.0 to be cleared by ha rdware, ter minat ing the Idl e mode. Th e interru pt will
be serviced, and following RETI the next instruction to be executed will be the one fol-
lowing the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured dur-
ing norma l operation or durin g an Idle. For examp le, an instructio n that activates Idle
can al so set one or b oth fla g bits. When Id le is te rminat ed by an inte rrupt, the in terrup t
service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
Power-down Mode To save maximum power, a power-down mode can be invoked by software (see Table
13, PCON register).
WARNING: To minimize power consumption, all peripherals and I/Os with static current
consumption must be set in the proper state. I/Os programmed with low s peed output
config ura tion (KB_O UT) must be swi tch to push-pul l or Standar d C51 configuratio n
before entering power-down. The CVCC generator must also be switch off.
In power-down mode, the oscillator is stopped and the instruction that invoked power-
down mode is the last instruction executed. The internal RAM and SFRs retain their
value until the power-down mode is terminated. VCC can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from power-
down. To properly terminate power-down, the reset or external interrupt should not be
executed befor e V CC is restored to i ts normal operating level an d must be h eld active
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 , INT1, Keyboard, Card insertion/removal and USB I nter-
rupts are useful to exit from power-down. For that, interrupt must be en abled and
configured as level or edge sens itive interrupt input. When Keyboard Interrupt occurs
after a po wer-down mode, 1024 cl ocks are neces sary to exi t to power-d own mode and
enter in operating mode.
Holding th e pi n low r es tarts the o scil la tor bu t br in gin g the pi n hi gh completes the e xit as
detailed in Figure 86. When both interrupts are enabled, the oscillator restarts as soon
as one of the two inputs is held low and power-down exit will be completed when the first
input is released. In this case, the higher priority interrupt service routine is executed.
Once th e interr upt is s ervic ed, the next i nstruc tion to be ex ecuted after RET I wil l be th e
one following the instruction that put AT8xC5122/23 into power-down mode.
143
AT8xC5122/23
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Figure 86. Power-d own Ex it Wavefor m
Exit from power-down by reset redefines all the SFRs, exit from power-down by external
interrupt does no affect the SFRs.
Exit fro m power-down by eit her reset or extern al interrupt does not aff ect the interna l
RAM content.
Note: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence
is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and
idle mode is not entered.
Table 107 shows the state of ports during idle and power-down modes.
Note: 1. Port 0 can force a 0 level. A "one" will leave port floating.
Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with
external progr am o r data memory. Nevertheless, during interna l code execu tion, ALE
signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting
AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no
longer output but remains active during MOVX and MOV C instructions and external
fetches. During ALE disabling, ALE pin is weakly pulled high.
INT1
INT0
XTAL1
Power-down phase Oscillator restart phase Active phaseActive phase
Table 107. Stat e of Ports
Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 PORTI2
Idle Internal 1 1 Port Data(1) Port Data Port Data Port Data Port Data
Idle External 1 1 Floating Port Data Address Port Data Port Data
Power-down Internal 0 0 Port Dat* Port Data Port Data Port Data Port Data
Power-down External 0 0 Floating Port Data Por t Data Port Data Port Data
144
AT8xC5122/23 4202B–SCR–07/03
USB Interface
Suspend The Suspend state can be detected by the USB c ontroller if all the clocks are enabled
and if the USB contr oller is enabled. The bit SPINT is set by hardware when an idle
state is detected for more than 3 ms. This triggers a USB interrupt if enabled.
In order to reduce current consumption, the firmware can put the USB PAD in idle mode,
stop the c locks and p ut the C5 1 in Id le or Power- down mo de. The R esu me dete ction is
still active.
The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to
avoid a new suspe nd detectio n 3ms later, th e firmware has to disa ble the USB clock
input using the SUSPCLK bit in the USBCON Register. T he USB PAD automatically
exits of idle mode when a wake-up event is detected.
The stop of the 48 MHz clock from the PLL should be done in the following order:
1. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUS-
PCLK bit in the USBCON register.
2. Disable the PLL by clearing the PLLEN bit in the PLLCON register.
Resume W hen the US B cont roller is in Sus pend s tate, the Re sume d etecti on is acti ve ev en if all
the clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit
is set by hardwa re when a non-idle state oc cur s on the USB bu s. Thi s trigge rs an inte r-
rupt if enabled. This interrupt wakes up the CPU from its Idle or Power-down state and
the interrup t functi on is then ex ecuted . The firmw are will fi rst enable the 48 MHz gene r-
ation and then reset to 0 the SUSPCLK bit in the USBCON register if needed.
The firmware has to clear the SPINT bit in the USBINT register before any other USB
operation in order to wake up the USB controller from its Suspend mode.
The USB controller is then re-activated.
Figure 87. Example of a Suspend/Resume Management
USB Contro ll er Init
Detection of a SUSPEND State SPINT
Set SUSPCLK
Disable PLL
microcontroller in Power-down
Detection of a RESUME State WUPCPU
Enable PLL
Clear SUSPCLK
Clear WUPCPU Bit
Clear SPINT
145
AT8xC5122/23
4202B–SCR–07/03
Smart Card Interfa ce
Entering in Power -down Mode In order to re duce the powe r consu mption , a power- down or idle mo de can b e invoke d
by softwar e (see Table 13, PCON regis ter). Befor e activatin g these m odes the appl ica-
tion will need to:
Power-off the Smart Card Interface by applying the following sequence:
•Set CRST pin at low level by clearing the bit CARDRST in SCCON register.
•Set CCLK pin at low level by clearing the bit CLK then the CARDCLK in SCCON
register.
•Set CIO pin at low level by clearing the bit UART in SCICR register then the bit
CARDIO in SCCON register.
•Power the Smart Interface off by clearing the CARDVCC bit in SCCON register . This
instruction enables to switch DC/DC converter off.
CPRES input:
•Set the bit PRSEN in ISEL register
•Set the bit EX1 in IE0 register
•Set the bit EA in the IE0 register
•Invert the bit CPLEV in ISEL register (INT1 interrupt vector)
•Clear the bit PRESI T in the ISEL reg ister
Exiting from Power-down
Mode The micr ocon tr oll er wi ll e xit fr om P owe r-do wn or Idl e mod es up on a reset or I NT 1 inte r-
rupt whi ch is a mu ltiplexing of the interrup tions gene rated by t he CPRES pin (Card
detection), RxD flag (UART reception) and INT1 pin.
Keyboard Interface Only for AT8xC5122.
Entering in Power -down Mode In order to reduce the power consumption, the microcontroller can be set in power-down
or idle mode by software (see Table 13, PCON register). Before activating these modes
the application will need to configure the keyboard interface as follows:
•Set all keyboard’s ouputs pins KB Rx at low level by writing a 0 on the ports. This
operation has a double effect:
–any key that is pressed generates an interrupt capable of waking-up the
microcontroller,
–Set all bits KBE.x in KBE registers to enable interrupts.
Exiting from Power-down
Mode The microcontroller will exit from Power-down Mode upon a reset or any interrupt gener-
ated by a key pr es s. Not e th at 1 024 cl ocks are nece ssar y to exit fro m pow er- dow n mode
when a ke yboard interru pt occurs. Thi s means that there will be a delay betw een the
time at whi ch the k ey is pr essed an d the tim e at whic h the ap plic ation is a ble to i dentify
the key.
146
AT8xC5122/23 4202B–SCR–07/03
Registers
Reset Value = 0XXX X0 00b
Table 108. Auxiliary Register - AUXR (8Eh)
76543210
DPU - - - XRS0 EXTRAM AO
Bit
Number Bit
Mnemonic Description
7DPU
Disable weak Pull-up
Reset weak pull-up is enable
Set weak pull-up is disable
6-3 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
2XRS0
XRAM Size
0 256 bytes (default)
1 512 bytes
1EXTRAM
EXTRAM bit
Cleared to access internal XRAM using MOVX @ Ri/ @ DPTR.
Set to access external memory.
Programmed by hardware after Power-up regarding Hardware Sec urity Byte
(HSB), default setting , XRAM selected.
0AO
ALE Output bit
Cleared , ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used)(default).
Set , ALE is active only during a M O VX or MOVC instructione is used.
147
AT8xC5122/23
4202B–SCR–07/03
Reset Value = 00X1 0000b
Power-off flag reset value will be 1 only after a power on (cold r eset). A warm reset
doesn’t affect the value of this bit.
Table 109. Power Control Register - PCON (S:87h)
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number Bit
Mnemonic Description
7SMOD1
Serial port Mode bit 1 for UART
Set to select double baud rate in mode 1,2 or 3
6SMOD0
Serial port Mode bit 0 for UART
Cleared to select SM0 bit in S C ON register
Set to select FE bit in SCON register
5-
Reserved
The value read from this bit is indeterm inate. Do not change this bit.
4POF
Power-Off Flag
Cleared to recognize next reset type
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set
by software
3GF1
General purpose Flag
Cleared by user for general-purpose usage
Set by user for general-purpose usage
2GF0
General purpose Flag
Cleared by user for general-purpose usage
Set by user for general-purpose usage
1PD
Power-Down mode bit
Cleared by hardware when reset occurs
Set to enter power-down mode
0IDL
Idle mode bit
Cleared by hardware when interrupt or reset occurs
Set to enter idle mode
148
AT8xC5122/23 4202B–SCR–07/03
Data Memo ry
Management
Expanded RAM (XRAM) The AT 8 xC5 122 /23 and A T8xC5123 p ro vides a ddi tio nal B yt es of random acce ss mem-
ory (RAM) space for increased data parameter handling and high level language usage.
AT8xC5122/23 and AT8xC5123 devices have expanded RAM in external data space;
maximum size and location are described in Table 110.
The AT8xC5122/23 and AT8xC5123 have internal data memory that is mapped into four
separate segments.
The four segments are:
•The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
•The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable
only.
•The Special Function Registers, SFRs, (addresses 80h to FFh) are directly
addressable only.
•The expanded RAM bytes are indirectly accessed by MOVX instructions, and with
the EXTRAM bit cleared in the AUXR register (see Table 108 on page 146)
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper
128 bytes ca n be access ed by indirect ad dressing only. T he Upper 128 bytes occupy
the same add r ess space as th e S F R. Tha t means t hey ha ve the s ame ad dres s, but ar e
physically separate from SFR space.
Table 110. Description of Expanded RAM
XRAM size
Address
Start End
AT8x C5122 and
AT8xC5123 512 00h 1FFh
149
AT8xC5122/23
4202B–SCR–07/03
Figure 88. Internal and External Data Memory Address
When an instru ction a ccesse s an inte rnal lo cation a bove ad dress 7Fh , the CPU knows
whether the access is in the upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction.
•Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data, accesses the SFR at location 0A0h (which is P2).
•Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte
at address 0A0h, rather than P2 (whose address is 0A0h).
•The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared
and MOVX instructions. This part of memory which is physically located on-chip,
logically occupies the first bytes of external data memory. The bit XRS0 is used to
hide a part of the available XRAM as explained in Table 108 on page 146. This can
be useful if external peripherals are mapped at addresses already used by the
internal XRAM.
•With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An
access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For
example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H,
accesses the XRAM at address 0A0H rather than external memory. An access to
external data memory locations higher than the accessible size of the XRAM will be
performed with the MOVX DPTR instructions in the same way as in the standard
80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and
read timing signals. Accesses to XRAM above 0FFH can only be done by the use of
DPTR.
XRAM
Upper
128 bytes
Internal
RAM
Lower
128 bytes
Internal
Ram
Special
Function
Register
80h 80h
00
1FFh
0FFh
00
0FFh
External
Data
Memory
0000
00FFh up to 03FFh
0FFFFh
indirect accesses direct accesses
direct or indirect
accesses
7Fh
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AT8xC5122/23 4202B–SCR–07/03
•With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard
80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port 0
and any output port pins can be used to output higher order address bits. This is to
provide the external paging capability. MOVX @DPTR will generate a sixteen-bit
address. Port 2 outputs the high-order eight address bits (the contents of DPH)
while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @
Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and
P3.7 (RD).
The s tack point er (SP) ma y be loc ated any where in the 256 byt es RAM (l ower and
upper RAM) internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
Dual Data Pointer
Register (DDPTR) The additional data pointer can be used to speed up code execution and reduce code
size.
The dual DPTR structure is a way by which the chip will specify the address of an exter-
nal data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1.0 (see Table 112) that allow the program
code to switch between them (Figure 89).
Figure 89. Use of Dual Pointer
a. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
Exte rn a l D a ta Me m o r y
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
07
DPTR0
DPTR1
151
AT8xC5122/23
4202B–SCR–07/03
ASSEMBLY LANGUAGE ; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 QU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ;increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a par-
ticul ar state, bu t simply to ggles it. In simple routin es, such as the block move examp le,
only the fact th at DPS is toggled in the proper sequenc e matters, not its ac tual value.
For examp le, the bl ock mov e routine works the same whethe r DPS is ’0’ or ’1’ on entry.
Observe that without the last instruction (INC AUXR 1), the routine will exit with DPS in
the opposite state.
Registers See Table 108 on page 146 for the definition of AUXR register.
Table 111. Auxiliary Register 1 AUXR1- (0A2h) for AT8xC5122
Reset Value = XX1X XX0X0b (Not bit addressable)
76543210
--ENBOOT-GF30-DPS
Bit
Number Bit
Mnemonic Description
7 - 6 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
5ENBOOT
Enable Boot ROM (ROM/CRAM version only)
Set this bit to map the Boot ROM from 8000h to FFFFh. If the PC increments
beyond 7FFFh address, the code is fetch from internal ROM
Clear this bit to disable Boot ROM. If the PC increments beyond 7FFFh address,
the code is fetch from external code memory (C51 standard roll over function)
This bit is forced to 1 at res et
4-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
3 GF3 This bit is a general-purpose user flag.
2 0 Always cleared.
1-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
0DPS
Data Pointer Selection
Cleared to select DP TR0. Set to select DPTR1.
152
AT8xC5122/23 4202B–SCR–07/03
Table 112. Auxiliary Register 1 AUXR1- (0A2h) for AT8xC5123
Reset Value = XXXX XX0X0b (Not bit addressable)
76543210
----GF30-DPS
Bit
Number Bit
Mnemonic Description
7 - 6 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
5Reserved
The value read from this bit is indeterminate. Do not change these bits.
4-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
3 GF3 This bit is a general-purpose user flag.
2 0 Always cleared.
1-
Reserved
The value read from this bit is indeterminate. Do not change this bit.
0DPS
Data Pointer Selection
Cleared to select DPTR0.
Set to sel ect DPTR1.
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4202B–SCR–07/03
Program Memory
Management The AT8xC5122/23 will be available in two configurations:
•CRAM / ROM
•ROM
•Both configurations provide:
–32K Bytes of Internal ROM (only 30K Bytes for AT8xC5123)
–256 bytes of RAM
–512 bytes of internal XRAM
The CR AM/RO M c onfig uration con tain an IS P sof tware (Boot loade r) and a RO M mon i-
tor (Emulator) mainly dedicated for pre-production, code development and debug, or
specific applications while the ROM configuration contains the final customer
application.
154
AT8xC5122/23 4202B–SCR–07/03
ROM Configuration
Register The ROM Configuration Register is masked and is not accessible by the MCU. It con-
tains fuse bits which enable the product configuration.
Table 113. ROM Configuration Register for AT8xC5122
Table 114. ROM Configuration Register for AT8xC5123
76543210
BLJRB LB2 LB1 LB0
Bit
Number Bit
Mnemonic Description
7-
Reserved
6BLJRB
Bootloader Jump Rom Bit
Set to configure User Code in ROM with a reset@0000h
Clear to configure in CRAM/ROM (Bootloader mode with a reset@F800h)
5 - 3 - Reserved
2 - 0 LB2: 0
Progr a m Lock Bits
The program lock bits protects the on-chip program against software piracy.
The AT8xC5122 products are delivered with the lowest protection level as
detailed in the following table:
LB2 LB1 LB0 Security
Level Protection Description
111 1
No program lock features enabled.
101 2
Read test mode function is disabled.
High pin count package
MOVC instruction executed from external
program memory are disabled from
fetching code bytes from internal memory.
EA is sampled and latched on reset.
External execution is enabled.
Checksum control is enabled.
Low pin count package
Checksum control is enabled.
76543210
-----LB2LB1LB0
Bit
Number Bit
Mnemonic Description
7 - 3 - Reserved
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2 - 0 LB2: 0
Progr a m Lock Bits
The program lock bits protects the on-chip program against software piracy.
The AT8xC5122 products are delivered with the lowest protection level as
detailed in the following table:
LB2 LB1 LB0 Security
Level Protection Description
111 1
No program lock features enabled.
101 2
Read test mode function is disabled.
High pin count package
MOVC instruction executed from external
program memory are disabled from
fetching code bytes from internal memory.
EA is sampled and latched on reset.
External execution is enabled.
Checksum control is enabled.
Low pin count package
Checksum control is enabled.
Bit
Number Bit
Mnemonic Description
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CRAM/ROM
Configuration The split of internal memory spaces depends on the product and is detailed below.
The ins tructio n code s ar e fetch ed fro m extern al or inter nal prog ram m emory de pendin g
on the logic state of microcontroller’s EA pin. Only valid for high pin count packages
(VQFP64).
Case EA = 0 After th e r es et, the pr og ram counter is i nitialised to 0000h and the c ode i ns tructions are
fetched from external program memory.
Case EA = 1 The ROM contains the bootloade r code. After reset sequen ce the pr ogram counter is
initialized to F800h and the bootloader is run. The bootloader downloads the application
into the CRAM. The sources to download the application from are in priority:
•an external 32K EEPROM attached to a synchronous serial interface
•a host attached to a USB interface
•a host attached to a RS232C interface
Note: Since the ROM is mapped in the upper 32K of program memory, the bootloader is not
able to provide direct interrup services.
Rollover Function Once th e appl ication is r unning in the inter nal l ower 32 K me mory sp ace, i t can roll ov er
in the external upper 32K memory space. A bit called ENBOOT and contained in
AUXR1 regis te r enables to sele ct this function. ENBOO T bit is set to 1 by the reset
function.
Mapping The program memory space is described in Figure 90.
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Figure 90. ROM contents (CRAM / ROM Configuration)
8000
FFFF
C000
BFFF
7FFF
0000
CRAM
Reserved
ROM
Bootloader
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ROM Configuration The product provides the following program and data memory spaces.
The ins tructio n code s ar e fetch ed fro m extern al or inter nal prog ram m emory de pendin g
on the logic state of microcontroller’s EA pin. Only valid for high pin count packages
(VQFP64).
Case EA = 0 After the reset the program counter is initialised to 0000h and the code instructions are
fetched from external program memory.
Case EA = 1 After a reset the pr ogram counter is initi alized to 0000h and the cus tomer applicatio n
contained in internal ROM is executed from address 0000h to 7FFFh.
The program memory space is described in figure below:
Figure 91. ROM Contents (ROM Configuration)
Memory Mapping In the products ROM versions, the following internal spaces are defined:
•RAM
•XRAM
•CRAM: 32K Bytes Program RAM Memory
•ROM
The specific accesses from/to these memories are:
• XRAM: if the bit RPS in RCON (described below) is reset, MOVX instructions
address the XRAM space.
• CRAM: if the bit RPS in RCON is set, MOVX instructions address the CRAM
space.
Reset@<0000>
ROM Configuration
7FFF
ROM
USER
CODE
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Reset Val ue = XXXX 0XXX b
CRAM Version without
Customer Mask Two memory blocks are implemented:
•The ROM mem ory con tains the Bootlo ader program .
•The CRAM is the Application program memory.
After a Reset, the program is downloaded, as described above, from:
•either an external EEPROM, or
•from an host conected on RS232 serial link.
into the program CRAM memory of 32K bytes. Then the Program Count er is set at
address 0000h of the CRAM space and the program is executed.
Figure 92. CRAM+ROM Mapping
Table 115. RAM Configuration Register - RCON (D1h)
76543210
----RPS---
Bit
Number Bit
Mnemonic Description
7 - 4 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
3RPS
CRAM Space Map Bi t
Set to map the CRAM space during MOVX instructions
Clear to map the Data space during MOVX. This bit has priority over the
EXTRAM bit.
2-0 - Reserved
The value read from this bit is indeterminate. Do not change these bits.
32K
512b
0000h
7FFFh
CRAM XRAM RAMROM
FFFFh
256b
8000h Bootloader
F800h Entry Point
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CRAM Version with Customer
Mask and ROM Version In this version, the customer program is masked in 32K bytes ROM.
Two memory areas are implemented:
•The customer program is masked in ROM during the final production phase. The
ROM Size will be determinated at mask generation process depending of the
program size.
•In the CRAM+ROM product, the CRAM is not used.
The Bo otload er Jum p ROM B it (BLJRB ) is s et to enable the us er ROM pro gram wh ich
is executed after reset.
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Electrical Characteristics
Absolute Maximum Ratings
DC Parameters
TA = -40 to +85°C; VSS = 0 V, F= 0 to 16MHz
X2 Core
VCC = 3.6V to 5.5V on -M Version
Ambiant Temperature Under Bias ......... ...... ...... .-25°C to 85°C
Storage Temperature................................... . -65°C to + 150°C
Voltage on VCC to VSS......................................-0.5 V to + 6.0V
Voltage on Any Pin to VSS........................-0.5 V to VCC + 0.5 V
Power Dissipation TBD W
Note: Stresses at or above those listed under “Absolute
Maximu m Rating s” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions may affect
device reliability.
Power Dissipation value is based on the maximum
allowable die temperature and the thermal resistance
of the packa ge.
Table 116. Core DC Parameters (XTAL, RST, P0, P2, P3, P4, P5, ALE, PSEN, EA)
Symbol Parameter Min Typ Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.2 VCC - 0.1 V
VIH Input High Voltage except XTAL1, RST 0.2 VCC + 0.9 VCC + 0.5 V
VIH1 Input High Voltage, XTAL1, RST 0.7 VCC VCC + 0.5 V
VOL Output Low Voltage: P0, ALE, PSEN 0.45 V IOL = 1.6 mA
VOH Output High Voltage: P0, ALE, PSEN 0.9 VCC VI
OH = -40 µA
VOL1 Outpu t Low Voltage: P2, P3 , P4, P5, P1.2, P1.6 ,
P1.7, 0.45 V IOL = 0.8 mA
VOH1 Output High V oltage: P2, P3, P4, P5, P1.2, P1.6,
P1.7 0.9 VCC VI
OH = -10 µA
IIL Logical 0 Input Current ports 2 to 5 and P1.2,
P1.6, P1.7, if Weak pull-up enabled -50 µA V in = 0.45 V
ILI Input Leakage Current ±10 µA 0.45 V < VIN < VCC
ITL Logical 1 to O transistion Current, Port 51
configuration −650 µAV
IN = 2 V
RMEDIUM Medium Pullup Resistor 10 kΩ
RWEAK Weak Pullup Resistor 100 kΩ
CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz
TA = 25°C
CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz
TA = 25°C
DICC Digital Supply Output Current 10 mA CL = 100 nF
F= 16 MHz X1
DVCC Digital Supply Voltage 3 3.3 3.6 V CL = 100 nF
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Operating ICC Test Condition Figure 93. ICC Test Condition, Idle Mode
Figure 94. ICC Test Condition, Power-down Mode
Figure 95. Clock Signal Waveform for ICC Tests in Idle Mode
VPFDP Power fail high level threshold 2.8 V
VPFDM Power fail low level threshold 2.6 V
trise, tfall VDD rise and fall time 1µs 600 second
RRST Internal reset pull-up resistor 15 k
Ω
C External reset capacitor 150 nF 1 µF
T rst Reset duration 10 70 ms Trst=0.7*R*C
Table 116. Core DC Parameters (XTAL, RST, P0, P2, P3, P4, P5, ALE, PSEN, EA) (Continued)
Symbol Parameter Min Typ Max Unit Test Conditions
All other pins are disconnected.
Reset = VCC after a high pulse
during at least 24 clock cycles EA
(NC)
CLOCK SIGNAL Vss
XTAL1
XTAL2
VCC
VCC RST
VCC
Icc
VCC
P0
All other pins are disconnected.
Reset = VCC after a high pulse
during at least 24 clock cycles VCC RST EA
VCC
Icc
VCC VCC
(NC)
P0
XTAL2
XTAL1
Vss
VCC-0.5V
0.45V 0.7VCC
0.2VCC-0.1
TCLCH
TCHCL
TCLCH = TCHCL = 5 ns.
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Figure 96. ICC Test Condition, Active Mode
LED’s
Note: 1. (TA = -20°C to +50°C, VCC - VOL = 2 V ± 20%)
Smart Card Interface
All other pins are disconnected.
Reset = VCC after a high pulse
during at least 24 clock cycles VCC RST EA
VCC
Icc
VCC VCC
(NC)
P0
XTAL2
XTAL1
Vss
VCC
CLOCK SIGNAL
Table 117. LED Outputs DC Parameters
Symbol Parameter Min Typ Max Unit Test Conditions
IOL Output Low Current, P3.6 and P3.7 LED modes 1
2
5
2
4
10
4
8
20
mA
mA
mA
2 mA configuration
4 mA configuration
10 mA configuration
Table 118. Smart Card 5V Interface DC Parameters
Symbol Parameter Min Typ Max Unit Test Conditions
CICC Card Supply Current 60 121
105
102 mA VCC = 5.5V
VCC = 4V
VCC = 2.85V
CVCC Card Supply Voltage 4.6 5.4 V CIcc = 60 mA
Ripple on Vcard 200 mV 0 < CIcc < 60 mA
CVCC Spikes on Vcard 4.6 5.4 V
Maxi. charge 20 nA
Max. duration 400 ns
Max. variation CIcc 100
mA
TVHLl Vcard to 0 750 µsCIcc = 0
Vcard = 5V to 0.4V
Table 119. Smart Card 3V Interface DC Parameters
Symbol Parameter Min Typ Max Unit Test Conditions
CICC Card Supply Current 60 110
89
110 mA VCC = 5.5V
VCC = 4V
VCC = 2.85V
CVCC Card Supply Voltage 2.76 3.24 V CIcc = 60 mA
Ripple on Vcard 200 mV 0 < CIcc < 60 mA
CVCC Spikes on Vcard 2.76 3.24 V Maxi. charge 10nA.s
Max. duration 400 ns
Max. variation CIcc 50mA
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Notes: 1. Test conditions, Capacitor 10 µF, Inductance 10 µH.
2. Ceramic X7R, SMD type capaci tor with minimum ESR or 250 m
Ω
is mandatory
Note: 1. The voltage on CLK should remain between -0.3V and VCC+0.3V during dynamic operation
TVHLl CVcc to 0 750 µsIcard=0
Vcard = 5V to 0.4V
Table 119. Smart Card 3V Interface DC Parameters
Symbol Parameter Min Typ Max Unit Test Conditions
Table 120. Smart Card 1.8V Interface DC parameters
Symbol Parameter Min Typ Max Unit Test Condition s
CICC Card Supply Current 20 109
100
82 mA VCC = 5.5V
VCC = 4V
VCC = 2.85V
CVCC Card Supply Voltage 1.68 1.92 V CIcc = 20 mA
CVCC Spikes on Vcard 1.68 1.92 V
TVHLl CVcc to 0 750 µsCIcc = 0
CVCC = 5V to 0.4V
Table 121. Smart Card Clock DC parameters (Port P1.4)
Symbol Parameter Min Typ Max Unit Test Conditions
VOL Output Low Voltage 0(1)
0(1) 0.2xVCC
0.4 VI
OL = 20 µΑ (1.8V, 3V)
IOL= 50 µA (5V)
IOL Output Low Current 15 mA
VOH Output High Voltage
0.7 CVCC
0.7 CVCC
0.7 CVCC
CVCC - 0.5
CVCC
CVCC
CVCC
CVCC
V
V
V
V
IOH = 20 µA (1.8V)
IOH = 20 µA (3V)
IOH = 20 µA (5V)
IOH = 50 µA (5V)
IOH Output High Current 15 mA
tR tFRise and Fall delays 16
22.5
50 ns
CIN=30pF (5V)
CIN=30pF (3V)
CIN=30pF (1.8V)
Voltage Stability -0.25
CVCC-0.5 0.4 CVCC
CVCC + 0.25 V Low level
High level
Frequency variation 1 %
Cycle ratio 45% 55%
Table 122. Smart Card I/O DC Parameters (P1.0)
Symbol Parameter Min Ty p Max Unit Test Conditions
VIL Input Low Voltage 0(1)
0(1) 0.5
0.15 CVCC
VI
IL= 500 µA
IIL = 20 µA
IIL Input Low Current 500 µA
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Note: 1. The voltage on RST should remain between -0.3V and VCC+0.3V during dynamic operation.
Note: 1. The voltage on RST should remain between -0.3V and VCC+0.3V during dynamic operation.
VIH Input High Voltage 0.7 CVCC CVCC VI
IH = -20 µA
IIH Input High Current -20 / +20 µA
VOL Output Low Voltage 0(1) 0.4
0.4
0.3 VIOL = 1mA (5V)
IOL = 1mA (3V)
IOL = 1mA (1.8V)
IOL Output Low Current 15 mA
VOH Output High Voltage 0.8 CVCC
0.7 CVCC
CVCC (1) VIOH = 20 µA (5V)
IOH = 20 µA (3V, 1.8V)
IOH Output High Current 15 mA
Voltage Stability -0.25
0.8 CVCC
0.4
CVCC + 0.25 V Low level
High level
tR tFRise and Fall delays 0.8 µsC
IN=30pF
Table 122. Smart Card I/O DC Parameters (P1.0) (Continued)
Symbol Parameter Min Ty p Max Unit Test Conditions
Table 123. Smart Card RST, CC4, CC8, DC Parameters (Port P1.5, P1.3, P1.1)
Symbol Parameter Min Typ Max Unit Test Conditions
VOL Output Low Voltage 0(1)
0(1) 0.12 x VCC
0.4 VIOL = 20 µΑ
IOL= 50 µΑ
IOL Output Low Current 15 mA
VOH Output High Voltage CVCC - 0.5
0.8 x VCC
CVCC
CVCC (1) VI
OH = 50 µΑ
IOH = 20 µΑ
IOH Output High Current 15 mA
tR tFRise and Fall delays 0.8 µsC
IN=30 pF
Voltage Stability -0.25
CVCC-0.5 0. 4 x CVCC
CVCC + 0.25 Low level
High level
Table 124. Card Presence DC Parameters (P1.2)
Symbol Parameter Min Typ Max Unit Test Conditions
IOL1 CPRES weak pull-up output current 3 10 25 µAP1.2=1, short to VSS
Pull-up enabled
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USB Interface Figure 97. USB Interface
AC Parameters
Explanation of the AC
Symbols Each timing symbol has 5 char acters. The first character is always a “T” (stands for
time). The other characters, depending on their positions, stand for the name of a signal
or the logical status of that signal. The following is a list of all the characters and what
they stand for.
Example:TAVLL = Time for Addres s Val id to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
TA = -40°C to +85°C; VSS = 0V; VCC = 5V ±10%; F = 0 to 40 MHz.
(Load Capacitance for port 0, ALE and PSEN = 60 pF; Load Capaci tance for all other
outputs = 60 pF.)
Table 125, Table 128 and Table 131 give the description of each AC symbols.
Table 126, Table 130 and Table 132 give for each range the AC parameter.
Table 127, Table 130 a nd Table 133 gi ve the frequency d erating formula of th e AC
parame ter for each spee d range des cription. T o calculate each AC symbo ls. take the x
value and use this value in the formula.
Example: TLLIV and 20 MHz, Standard clock.
x = 30 ns
T = 50 ns
TCCIV = 4T - x = 170 ns
Symbol Parameter Min Typ(5) Max Unit
VREF USB Reference Vo ltage 3.0 3.6 V
VIH Input High Voltage for D+ and D- (driven) 2.0 V
VIHZ Input High Voltage for D+ and D- (floating) 2.7 3.6 V
VIL Input Low Voltage for D+ an d D- 0.8 V
VOH Output High V oltage for D+ and D- 2.8 3.6 V
VOL Output Low Voltage for D+ and D- 0.0 0.3 V
1
4
23
1- VBUS
2 - D -
3 - D +
4 - GND
USB “B”
Receptacle
VREF
D +
D -
R
Rpad
Rpad
R = 1.5 kΩ
Rpad = 27Ω
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External Program Memory
Characteristics Table 125. Symbol Description
Symbol Parameter
T Oscillator clock period
TLHLL ALE pulse width
TAVLL Ad dress Va lid to ALE
TLLAX Address Hold After ALE
TLLIV ALE to Valid Instruction In
TLLPL ALE to PSEN
TPLPH PSEN Pulse Width
TPLIV PSEN t o Valid Instruction In
TPXIX Input Instruction Hold Aft er P SE N
TPXIZ Input Instruction Float After PSEN
TAVIV Ad dress to Valid Instruction In
TPLAZ PSEN Low to Address Float
Table 126. AC Parameters for a Fix Clock (F = 40 MHz)
Symbol Min Max Units
TTBD ns
TLHLL TBD ns
TAVLL TBD ns
TLLAX TBD ns
TLLIV TBD ns
TLLPL TBD ns
TPLPH TBD ns
TPLIV TBD ns
TPXIX TBD ns
TPXIZ TBD ns
TAVIV TBD ns
TPLAZ TBD ns
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Table 127. AC Parameters for a Variable Clock
External Program Memory Read Cycle
Symbol Type Standard
Clock X2 Clock X parameter Units
TLHLL Min 2 T - x T - x 10 ns
TAVLL Min T - x 0.5 T - x 15 ns
TLLAX Min T - x 0.5 T - x 15 ns
TLLIV Max 4 T - x 2 T - x 30 ns
TLLPL Min T - x 0.5 T - x 10 ns
TPLPH Min 3 T - x 1.5 T - x 20 ns
TPLIV Max 3 T - x 1.5 T - x 40 ns
TPXIX Min x x 0 ns
TPXIZ Max T - x 0.5 T - x 7 ns
TAVIV Max 5 T - x 2.5 T - x 4 0 ns
TPLAZ Max x x 10 ns
12 TCLCL
TLLIV
TLHLL TLLPL
ALE TPLPH
PSEN
PORT 0 INS TR IN A0-A7 INSTR IN A0-A7 INSTR IN
TLLAX TPLAZ
TPXAV
TAVLL TPXIX TPXIZ
TPLIV
TAVIV
PORT 2 ADDRESS
OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15
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Exte rnal Data Memory
Characteristics Table 128. Symbol Description
Table 129. AC Parameters for a Variable Clock (F = 40 MHz)
Symbol Parameter
TRLRH RD Pulse Width
TWLWH WR Pulse Width
TRLDV RD to Valid Data In
TRHDX Data Hold After RD
TRHDZ Data Float After RD
TLLDV ALE to Valid Data In
TAVDV Add re s s to Valid D a ta In
TLLWL ALE to WR or RD
TAVWL Address to WR or RD
TQVWX Dat a Valid to WR Trans ition
TQVWH Data set-up to WR High
TWHQX Data Hold After WR
TRLAZ RD Low to Address Float
TWHLH RD or WR High to ALE high
Symbol Min Max Units
TRLRH TBD ns
TWLWH TBD ns
TRLDV TBD ns
TRHDX TBD ns
TRHDZ TBD ns
TLLDV TBD ns
TAVDV TBD ns
TLLWL TBD TBD ns
TAVWL TBD ns
TQVWX TBD ns
TQVWH TBD ns
TWHQX TBD ns
TRLAZ TBD ns
TWHLH TBD TBD ns
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Table 130. AC Parameters for a Variable Clock
External Data Memory Write Cycle
Symbol Type Standard
Clock X2 Clock X parameter Units
TRLRH Min 6 T - x 3 T - x 20 ns
TWLWH Min 6 T - x 3 T - x 20 ns
TRLDV Max 5 T - x 2.5 T - x 25 ns
TRHDX Min x x 0 ns
TRHDZ Max 2 T - x T - x 20 ns
TLLDV Max 8 T - x 4T -x 40 ns
TAVDV Max 9 T - x 4.5 T - x 6 0 ns
TLLWL Min 3 T - x 1.5 T - x 25 ns
TLLWL Max 3 T + x 1.5 T + x 25 ns
TAVWL Min 4 T - x 2 T - x 25 ns
TQVWX Min T - x 0.5 T - x 15 ns
TQVWH M in 7 T - x 3. 5 T - x 25 ns
TWHQX Min T - x 0.5 T - x 10 ns
TRLAZ Max x x 0 ns
TWHLH Min T - x 0.5 T - x 15 ns
TWHLH Max T + x 0.5 T + x 15 ns
TQVWH
TLLAX
ALE
PSEN
WR
PORT 0
PORT 2
A0-A7 DATA OUT
ADDRESS
OR SFR-P2
TAVWL
TLLWL
TQVWX
ADDRESS A8-A15 OR SFR P2
TWHQX
TWHLH
TWLWH
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External Data Memory Read Cycle
Serial Port Timing - Shift
Register Mode Table 131. Symbol Description (F = 40 MHz)
Table 132. AC Parameters for a Fix Clock (F = 40 MHz)
Table 133. AC Parameters for a Variable Clock
Shif t Register Timing Waveform
ALE
PSEN
RD
PORT 0
PORT 2
A0-A7 DATA IN
ADDRESS
OR SFR-P2
TAVWL
TLLWL
TRLAZ
ADDRESS A8-A15 OR SFR P2
TRHDZ
TWHLH
TRLRH
TLLDV
TRHDX
TLLAX
TAVDV
Symbol Parameter
TXLXL Serial port clock cycl e time
TQVHX Output data set-up to clock rising edge
TXHQX Output data hold aft er clock rising edge
TXHDX Input data hold after clock rising edge
TXHDV Clock rising edge to input data valid
Symbol Min Max Units
TXLXL TBD ns
TQVHX TBD ns
TXHQX TBD ns
TXHDX TBD ns
TXHDV TBD ns
Symbol Type Standard
Clock X2 Clock X parameter
for -M range Units
TXLXL Min 12 T 6 T ns
TQVHX Min 10 T - x 5 T - x 50 ns
TXHQX Min 2 T - x T - x 20 ns
TXHDX Min x x 0 ns
TXHDV Max 10 T - x 5 T- x 133 ns
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External Clo ck Driv e
Characteristics (XTAL1) Table 134. AC Parameters
External Clo ck Driv e
Waveforms
AC Testing Input/Output
Waveforms
AC in pu ts dur ing tes ting are dri ven a t VCC - 0.5 for a logic “1” and 0.45V for a l ogic “0”.
Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.
Float W aveforms
For timing purposes as port pin is no longer floating when a 100 mV change from load
voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level
occurs. IOL/IOH ≥ ± 20 mA.
VALID VALID VALID VALID VALID
VALID
INPUT DATA VALID
0123456 87
ALE
CLOCK
OUTPUT DATA
WRIT E to SBUF
CLEAR RI
TXLXL
TQVXH TXHQX
TXHDV TXHDX SET TI
SET RI
INSTRUCTION
01234567
VALID
Symbol Parameter Min Max Units
TCLCL Osc illator Period 25 ns
TCHCX High Time 5 ns
TCLCX Low Time 5 ns
TCLCH Rise Time 5 ns
TCHCL Fall Time 5 ns
TCHCX/TCLCX Cyclic ratio in X2 mode 40 60 %
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCL TCLCX TCLCL
TCLCH
TCHCX
INPUT/OUTPUT 0.2 VCC + 0.9
0.2 VCC - 0.1
VCC -0.5V
0.45V
FLOAT
VOH - 0.1 V
VOL + 0.1 V
VLOAD VLOAD + 0.1 V
VLOAD - 0.1 V
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Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
This diagram indicates when signals are clocked internally. The time it takes the signals
to propa gate to the pi ns, howeve r, ranges from 25 to 125 ns. This pro pagatio n delay is
dependent on variables such as temperature and pin loading. Propagation also varies
from output to output and component. Typically though (TA=25°C fully loaded) RD and
WR propag atio n delays are ap proxim ately 50 ns. Th e other signals are typi cally 85 ns.
Propagation delays are incorporated in the AC specifications.
DATA PCL OUT DATA PCL OUT DATA PCL OUT
SAMPLED SAMPLED SAMPLED
STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
FLOAT FLOAT FLOAT
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
INDICATES ADDRESS TRANSITIONS
EXTERNAL PROGRAM MEMORY FETCH
FLOAT
DATA
SAMPLED
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (IF PROGRAM
MEMORY IS EXTERN AL)
PCL OUT (EVEN IF PROGRAM
MEMO RY IS INT ERNAL)
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL
OLD DATANEW DATA P0 PINS SAMP LED
P1, P2, P3 PINS SAMPLED P1, P2 , P3 PI NS SAMPLED
P0 PINS SAMPLED
RXD SAMPLED
INTERNAL
CLOCK
XTAL2
ALE
PSEN
P0
P2 (EXT)
READ CYCLE
WRITE CYC LE
RD
P0
P2
WR
PORT OPERATION
MOV PO RT SR C
MOV DES T P0
MOV DEST PORT (P1. P2. P3)
(INC L U D ES INTO . INT1. TO T1)
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
DATA OUT
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P0
P2
RXD SAMPLED
174
AT8xC5122/23 4202B–SCR–07/03
USB Interface
Rise Time Fall Time
VCRS
Differential
Data Lines
90%
10%
90%
10%
tRtF
VHmin
VLmax
Table 135. USB AC Para meters
Symbol Parameter Min Typ(5) Max Unit
tRRise Time 4 20 ns
tFFall Time 4 20 ns
tFDRATE Full-speed Data Rate 11.9700 12.0300 Mb/s
VCRS Crossover Voltage 1.3 2.0 V
tDJ1 Source Jitter Total to next transaction -3.5 3. 5 ns
tDJ2 Source Jitter Total for paired
transactions -4 4 ns
tJR1 Receiver Jitter to next transaction -18.5 18.5 ns
tJR2 Receiver Jitter for paired transactions -9 9 ns
175
AT8xC5122/23
4202B–SCR–07/03
Typical Application
Figure 98. Typical Smart Card Reader and Keyboard Application Schematic
GND
100 nF
VCC
VREF
XTAL1 XTAL2
LI
CVCC
CPRES
CRST
CCLK
CC4
CC8
CIO
+10 uF
CVSS CVSS
I/O
C8
C4
CLK
RST
GND
GND
GND
D-
LEDX
MASTER
CARD
I/O
RST
CLK
CIO1
CRST1
CCLK1
VCC
1 M
Ω
(Optional Resistor)
PLLF
D+
P0
P2
P4
P5
SCAN OUTP UT
GND
1.5 k
Ω
CVSS
10 µH
470 nF
DVCC
GND
VCC
100 nF
GND GND
22 pF22 pF
8 MHz
ALTERNATE
CARD
EA
VCC
RST
10 K
Ω
+
GND
(optional capacitor)
DIGITAL
MA STER CARD
MA STER CARD
CARD PRESENCE
SWITCH
POWER SUPPLY
RESET
AVSS VSS
POWER SUPPLY
100 nF
AVSS
ANALOG
POWER SUPPLY
AVCC
GND
Note 1: As close as possible from MCU
LINE D+
LINE D-
27
Ω
27
Ω
VCC
SCAN OUTP UT
SCAN OUTP UT
SCAN INPUT
KEYBOARD
GROUND
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 1)
USB HOST
176
AT8xC5122/23 4202B–SCR–07/03
Figure 99. Typical Smart Card Reader Application Schematic
GND
100 nF
VCC
VREF
XTAL1 XTAL2
LI
CVCC
CPRES
CRST
CCLK
CC4
CC8
CIO
+10 uF
CVSS CVSS
I/O
C8
C4
CLK
RST
GND
GND
GND
D-
LEDX
MASTER
CARD
I/O
RST
CLK
CIO1
CRST1
CCLK1
VCC
1 M
Ω
(Optional Resistor)
PLLF
D+
GND
1.5 k
Ω
CVSS
10 µH
470 nF
DVCC
GND
VCC
100 nF
GND GND
22 pF22 pF
8 MHz
ALTERNATE
CARD
RST
+
GND
(optional capacitor)
DIGITAL
MA STER CARD
MA STER CARD
CARD PRESENCE
SWITCH
POWER SUPPLY
RESET
AVSS VSS
POWER SUPPLY
100 nF
AVSS
ANALOG
POWER SUPPLY
AVCC
GND
Note 1: As close as possible from MCU
LINE D+
LINE D-
27
Ω
27
Ω
VCC
GROUND
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 1)
USB HOST
177
AT8xC5122/23
4202B–SCR–07/03
Ordering Information
Part Number Memory Size
(bytes) Supply Voltage (V) Temperature
Range Max Frequency
(MHz) Package Packing
AT83C5122xxx-RDTIM 32K ROM 3.6 - 5.5 Industrial 32 VQFP64 Tray
AT83C5122xxx-RDRIM 32K ROM 3.6 - 5.5 Industrial 32 VQFP64 Tape & Reel
AT83C5122x xx- SI SI M 32K ROM 3.6 - 5.5 Industrial 32 PLCC28 Stick
AT83C5122xxx-SIRIM 32K ROM 3.6 - 5.5 Industrial 32 PLCC28 Tape & Reel
AT85EC5122-RDVIM 32K ROM + 512
Bytes EEPR O M 3.6 - 5.5 Industrial 32 VQFP64 Tray & Dry pack
AT85EC5122-RDFIM 32K ROM + 512
Bytes EEPR O M 3.6 - 5.5 Industrial 3 2 VQF P64 Tray & Reel
& Dry pack
AT85EC5122-SIUIM(1) 32K ROM + 512
Bytes EEPR O M 3.6 - 5.5 Industrial 32 PLCC28 Stick & Dry pack
AT85EC5122-SIXIM(1) 32K ROM + 512
Bytes EEPR O M 3.6 - 5.5 Industrial 3 2 PLCC28 Tray & Reel
& Dry pack
AT85C5122xxx-RDTIM RAM 3.6 - 5.5 I ndustrial 3 2 VQFP64 Tray
AT85C5122xxx-RDRIM RAM 3.6 - 5.5 Industrial 32 VQFP64 Tape & Reel
AT85C5122x xx- SI SI M RAM 3.6 - 5.5 Industrial 32 PLCC28 Stick
AT85C5122xxx-SIRIM RAM 3.6 - 5.5 Industrial 32 PLCC28 Tape & Reel
AT89C5122-RDTIM(1) 32K Flash RAM 3.6 - 5.5 Indust rial 32 VQFP64 Tray
AT89C5122-RDRIM(1) 32K Flash RAM 3.6 - 5.5 Industrial 32 VQFP64 Tape & Reel
AT89C5122-SISIM(1) 32K Flash RAM 3.6 - 5.5 Indust rial 32 PLCC28 Stick
AT89C5122-SIRIM(1) 32K Flash RAM 3.6 - 5.5 Industrial 32 PLCC28 Tape & Reel
AT83C5123xxx-RATIM 30K ROM 3.6 - 5.5 Industrial 32 LQFP32 Tray
AT83C5123xxx-RARIM 30K ROM 3.6 - 5.5 Industrial 32 LQFP32 Tape & Reel
AT83C5123x xx- SI SI M 30K ROM 3.6 - 5.5 Industrial 32 PLCC28 Stick
AT83C5123xxx-SIRIM 30K ROM 3.6 - 5.5 Industrial 32 PLCC28 Tape & Reel
AT83EC5123xxx-RAVIM 30K ROM + 512
Bytes EEPR O M 3.6 - 5.5 Industrial 32 LQFP32 Tray & Dry pack
AT83EC5123xxx-RAFIM 30K ROM + 512
Bytes EEPR O M 3.6 - 5.5 Industrial 3 2 LQFP32 Tray & Reel
& Dry pack
AT83EC5123xxx-SIUIM(1) 30K ROM + 512
Bytes EEPR O M 3.6 - 5.5 Industrial 32 PLCC28 Stick & Dry pack
178
AT8xC5122/23 4202B–SCR–07/03
Note: 1. Check avaibility with sales office
AT83EC5123xxx-SIXIM(1) 30K ROM + 512
Bytes EEPR O M 3.6 - 5.5 Industrial 3 2 PLCC28 Tray & Reel
& Dry pack
Part Number Memory Size
(bytes) Supply Voltage (V) Temperature
Range Max Frequency
(MHz) Package Packing
179
AT8xC5122/23
4202B–SCR–07/03
Packaging
Information
PLCC28
180
AT8xC5122/23 4202B–SCR–07/03
VQFP64
181
AT8xC5122/23
4202B–SCR–07/03
PLCC68
182
AT8xC5122/23 4202B–SCR–07/03
LQFP32
183
AT8xC5122/23
4202B–SCR–07/03
Datasheet Change Log
Changes from 4202A to 4122B
1. Product AT8xEC5122 added.
2. Products AT83C5123 and AT83EC5123 added.
iAT8xC5122/23 4202B–SCR–07/03
Table of Content s
Features ................................................................................................. 1
Description ............................................................................................ 2
AT8xC5122 Bloc k Diagra m. .................. ....................... ..... ................... 3
AT8xC5123 Bloc k Diagra m. .................. ....................... ..... ................... 3
Pin Description ..................................................................................... 4
.............................................................................................................................. 4
Signals.................................................................................................................. 6
I/O Port Definition ............................................................................................... 10
Port Configuration............................................................................................... 13
Registers............................................................................................................. 17
SFR Description ..................................................................................21
Clock Controller .................................................................................. 28
Oscillator............................................................................................................. 32
PLL ..................................................................................................................... 32
Registers............................................................................................................. 34
Smart Card Interface Block (SCIB) .................................................... 37
Block Diagram .................................................................................................... 38
Functional Description ........................................................................................ 38
Additional Features............................................................................................. 43
Registers............................................................................................................. 45
DC/DC Converter................................................................................................ 54
USB Controller ....................................................................................57
Description.......................................................................................................... 58
Configuration ...................................................................................................... 61
Read/Write Data FIFO. ....... ...... ...... ....... ................... ....... ...... ....... ...... ....... ...... ... 64
Bulk / Interrupt Transactions............................................................................... 65
Control Transactions........................................................................................... 69
Isochronous Transactions................................................................................... 70
Miscellaneous..................................................................................................... 72
Suspend/Resume Management .........................................................................73
Detach Simulation............................................................................................... 75
USB Interrupt System......................................................................................... 76
Registers............................................................................................................. 78
Serial I/O Port ...................................................................................... 88
Framing Error Detection ..................................................................................... 88
ii
AT8xC5122/23
4202B–SCR–07/03
Automatic Address Recognition.......................................................................... 89
Asynchronous Modes (Modes 1, 2 and 3).......................................................... 93
Modes 2 and 3.................................................................................................... 94
Registers............................................................................................................. 97
Serial Port Interface (SPI) ................................................................... 99
Features.............................................................................................................. 99
Signal Des criptio n............... ................... ...... ....... ...... ....... ................... ....... ...... ... 99
Functional Description ...................................................................................... 101
Timers/Counters ............................................................................... 109
Timer/Counter Operations................................................................................ 109
Timer 0.............................................................................................................. 109
Timer 1.............................................................................................................. 112
Registers........................................................................................................... 114
Keyboard Interface ........................................................................... 1 17
Introduction....................................................................................................... 117
Description........................................................................................................ 117
Registers........................................................................................................... 118
Interrupt Syst em ............................................................................... 121
INT1 Interrupt Vector........................................................................................ 123
Registers........................................................................................................... 123
Interrupt Sources and Vector Addresses.......................................................... 134
Reset and Power Monitor ................................................................. 135
Reset ................................................................................................................ 135
Power Monitor................................................................................................... 137
Watchdog Timer ................................................................................139
Watchdog Timer During Power-down Mode and Idle....................................... 141
Power Management .......................................................................... 142
Idle Mode.......................................................................................................... 142
Power-down Mode............................................................................................ 142
Reduced EMI Mode.......................................................................................... 143
USB Interface ................................................................................................... 144
Smart Card Interface ........................................................................................ 145
Keyboard Inter fa ce ............. ...... ...... ....... ...... ....... ...... ....... ...... ....... ...... .............. 145
Registers........................................................................................................... 146
Data Memory Management .............................................................. 148
Expanded RAM (XRAM)................................................................................... 148
Dual Data Pointer Register (DDPTR)............................................................... 150
ASSEMBLY LANGUAGE ................................................................................. 151
iii AT8xC5122/23 4202B–SCR–07/03
Registers........................................................................................................... 151
Program Memory Management ....................................................... 153
ROM Configuration Register............................................................................. 154
CRAM/ROM Configuration ............................................................................... 156
ROM Configuration........................................................................................... 158
Memory Mapping.............................................................................................. 158
Electrical Characteristics .................................................................161
Absolute Maximum Ratings ..............................................................................161
DC Parameters .................................................................................................161
AC Parameters................................................................................................. 166
Float Waveforms............................................................................................... 172
Clock Waveforms.............................................................................................. 173
Typical Application ........................................................................... 175
Ordering Information ........................................................................ 177
Packaging Information ..................................................................... 179
PLCC28............................................................................................................ 179
VQFP64............................................................................................................ 180
PLCC68............................................................................................................ 181
LQFP32 ............................................................................................................ 182
Datasheet Change Log ..................... ........................ .... ..... ............... 183
Changes from 4202A to 4122B ........................................................................183
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4202B–SCR–07/03 /0M
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