109
AT8xC5122/23
4202B–SCR–07/03
Timers/Counters The AT8xC5122 implements two general-purpose, 16-bit Timers/Counters. Although
they are identified as Timer 0, Timer 1, you can independently configure each to operate
in a v ar ie ty of m ode s as a Ti mer or as an e ven t Coun ter. When ope ra tin g as a Tim er , a
Timer/Counter runs for a programmed length of time, then issues an interrupt request.
When ope ra tin g as a Coun ter, a T im er/Coun ter c oun ts negative tr ans it ion s on an exte r-
nal pin. After a preset number of counts, the Counter issues an interrupt request.
The Timer registers and associated control registers are implemented as addressable
Special Function Registers (SFRs). Two of the SFRs provide programmable control of
the Timers as follows:
•Timer/Counter mode control register (TMOD) and Timer/Counter control register
(TCON) control respectively Timer 0 and Timer 1.
The various operating modes of each Timer/Counter are described below.
Timer/Counter
Operations For example, a basic operation is Timer registers THx and TLx (x= 0, 1) connected in
cascade to form a 16-bit Timer. Setting the run c ontrol bit (TRx) in the TCON register
(see Table 82 on page 114) turns the Timer on by allowing the selected input to incre-
ment TLx. When TLx overflows, it increments THx and when THx overflows it sets the
Timer ov erflow fl ag ( TFx) in the TC ON reg ister. S etting the TR x does not cl ear th e THx
and TLx T im er re gis te rs. T im er regis ter s can be ac ce ss ed to ob ta in th e cu rren t cou n t or
to enter pre set value s. They ca n be read at an y time but the T Rx bit mus t be clea red to
preset their values, otherwise the behavior of the Timer/Counter is unpredictable.
The C/Tx# control bit selects Timer oper ation or Counter operation by selecting the
divided-down system clock or the exte rnal pin T x as the source for the counte d signal.
The TRx bit must be cleared when changing the operating mode, otherwise the behavior
of the Timer/Counter is unpredictable.
For Timer operatio n (C/Tx#= 0), the Timer register c ounts the divided-down system
clock. The Timer register is incremented once every peripheral cycle.
Exceptions are the Timer 2 Baud Rate and Clock-Out modes in which the Timer register
is incremented by the system clock divided by two.
For Count er op eration (C/T x#= 1) , the Timer r egister co unts the neg ative tr ansi tions o n
the Tx external input pin. The external input is sampled during every S5P2 sta te. The
Programmer’s Guide des cribes the notation for the states in a peripher al cycle. When
the sample is high in one cycle and low in the next one, the Counter is incremented. The
new count value appear s in the register during the next S3P1 state after the transition
has bee n detected. Sin ce i t takes 12 s tates (24 os cilla tor periods ) to r ecogni ze a nega-
tive transit ion, the max imum count rate is 1/24 of the oscill ator frequenc y. There are no
restrictions on the duty cycle of the external input signal, but to ensure that a given level
is samp led at l east on ce befo re it chan ges, i t shoul d be hel d for at lea st one f ull per iph-
eral cycle.
Timer 0 Timer 0 functions as either a Timer or an event Counter in four operating modes.
Figure 71 through Figure 77 show the logic configuration of each mode.
Timer 0 is controll ed by the four lower bits of the TMOD r egist er (see Tab le 83 on pag e
115) and bits 0, 1, 4 and 5 of the TCON register (see Table 82 on page 114). The TMOD
register selects the meth od of Timer gating (GATE0), Timer or Counter operation
(T/C0#) and the operating mode (M10 and M00). The TCON register provides Timer 0
control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and inter-
rupt type control bit (IT0).