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Motorola Master Selection GuideLogic: Standard, Special and Programmable 3.1–2
A retargetting rules file is read and the input netlist is
transformed into a series of MPA cells and associated
interconnections. Rules files provide a mechanism to
perform attribute mapping, cell mapping and macro
expansion. By creating custom rule files, the user can
extend the importation process from arbitrary sources. The
MPA design system comes with rules for it’s native
library/EDIF. The resulting netlist is optimized to clip unused
logic and remove redundant logic. For example: each MPA
cell has programmable input inversion capability. All
Inverters or non–inverting buffers can be removed from the
netlist and replaced with signal sense information attached
to each input.
A series of design rule checks are performed to insure
design integrity before the layout process begins.
Constraint Generation
Timing constraints, the optimized MPA netlist and static
timing analysis is used to generate path slack constraints
for all paths in the design. Each unique signal pathway
between a register output and a register input throughout
the design are enumerated. The total logic and estimated or
real wire delays along the path are summed. The time
between the active upstream register clock edge and the
next active downstream clock edge minus the downstream
register setup time is subtracted from the total path delay.
This difference is called path slack. If any path in the design
has a negative slack value, the implementation will not
function at the required clock rate(s).
Path constraints are utilized throughout the layout
process to insure that a design implementation which meets
timing constraints is automatically generated. If no clock or
timing specifications are provided, the MPA design system
uses the fastest possible clock based on very small net
delay estimates to generate the path constraints. This
usually results in the best possible implementation, but may
take longer than the time required to generate a satisfactory
rather than best possible result.
Contrast this to other programmable logic design tools
which only provide manual net constraint annotation or net
criticality assignment. In these cases significant effort is
necessary to generate constraints and many costly
iterations are required to tune these constraints for a given
design. If any changes are made to the design, another
costly round of iterations is required.
Autolayout
The autolayout process makes use of the hierarchical
organization of the MPA device to minimize run time and
deliver implementations that meet timing requirements.
Designs which have diverse timing requirements are ideally
implemented because path slack estimates are refined
throughout the autolayout process insuring only the
resources required to meet timing requirements are
consumed.
The process begins by flattening the design and
partitioning it into small component groups of approximately
the same size called clusters. A cluster boundary delay
estimation is applied to pull the most tightly constrained
paths into a minimum number of clusters. The clusters are
then assigned to zones talking into account zonal boundary
delay cost and relative zone placement delay costs. Other
costs like total number of port connections per zone and are
also considered. As assignment proceeds, cluster and zone
boundary delay costs are added to each path and slack is
recomputed.
Next global placement and routing is done. Global routes
begin and end on either I/O cells or port cells. Intrazone
placement and routing is deferred to a later phase. During
global routing all the port cell and I/O cell locations are fixed
and the connections between them established. High fanout
nets are constructed in a highly regular manner to insure
efficient resource utilization. As in partitioning, slack
estimates are refined throughout global routing.
Finally the intrazonal placement and routing is done.
Cells assigned to a particular zone are placed and routed to
other zone cells or zone port cells. Port cells and core cells
are constructed to allow port swapping. Core cells can be
routed through if necessary. Allowing core cells to act as
routing cells allows dynamic adjustment of routing
resources within the zone. Dynamic resource adjustment is
a powerful design specific adaptation mechanism.
This process produces a layout from which device
configurations, delay back annotations, and chipviews can
be generated.
Incremental Design Support
When specification changes necessitate design
iterations, simply push the button again. Constraints are
automatically recalculated and autolayout only reworks
those portions of the design which have changed. Full
incremental design support means simple design changes
to facilitate design verification can be made quickly and
easily.
Delay Back Annotation
Designs can be verified through numerous methods. One
particularly useful method is the annotation of device and
implementation specific delays back into the original
simulation environment to improve system or device level
simulation accuracy. A MPA device layout can be
transformed into an appropriately formatted delay
annotation file or annotated netlist quickly and easily. The
annotated delay information represents the worst case
delays for a given device speed grade.
Chipview
While the MPA design system provides a rich set of
reports describing the implementation of a design, a
graphical view of the implementation can be indispensable
for reviewing overall layout quality. Chipview provides a
graphical view of a completed layout. Chipview can be
useful during initial design iterations to visually verify I/O pin
placements before commencing PCB layout, for example.