Hitachi Single-Chip Microcomputer H8/520 HD6475208 HD6435208 User's Manual (Hardware) Preface The H8/520 is a high-performance single-chip microcomputer featuring a high-speed CPU with 16-bit internal data paths and a full complement of on-chip supporting modules. The H8/520 is an ideal microcontroller for a wide variety of medium-scale devices, including both office and industrial equipment and consumer products. Its instruction set is designed for fast execution of programs coded in the high-level C language. On-chip facilities include large RAM and ROM memories, numerous timers, serial I/O, an A/D converter, I/O ports, and other functions for compact implementation of high-performance application systems. The H8/520 is available in both a ZTATTM version* with on-chip PROM, ideal for the early stages of production or for products with frequently-changing specifications, and a masked-ROM version suitable for volume production. This manual gives a hardware description of the H8/520. For details of the instruction set, refer to the H8/500 Series Programming Manual, which applies to all chips in the H8/500 family. Note: * ZTAT (Zero Turn-Around Time) is a registered trademark of Hitachi, Ltd. Contents Section 1 Overview ................................................................................................................. 1.1 1.2 1.3 Features ................................................................................................................................ Block Diagram ..................................................................................................................... Pin Arrangements and Functions ......................................................................................... 1.3.1 Pin Arrangement ...................................................................................................... 1.3.2 Pin Functions............................................................................................................ 1 1 4 5 5 8 Section 2 MCU Operating Modes and Address Space ................................................... 23 2.1 2.2 2.3 2.4 Overview.............................................................................................................................. Mode Descriptions ............................................................................................................... Address Space Map.............................................................................................................. 2.3.1 Page Segmentation ................................................................................................... 2.3.2 Page 0 Address Allocations...................................................................................... Mode Control Register (MDCR) ......................................................................................... 23 24 25 25 27 29 Section 3 CPU........................................................................................................................... 31 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Overview.............................................................................................................................. 3.1.1 Features .................................................................................................................... 3.1.2 Address Space .......................................................................................................... 3.1.3 Register Configuration ............................................................................................. CPU Register Descriptions .................................................................................................. 3.2.1 General Registers ..................................................................................................... 3.2.2 Control Registers...................................................................................................... 3.2.3 Initial Register Values .............................................................................................. Data Formats........................................................................................................................ 3.3.1 Data Formats in General Registers........................................................................... 3.3.2 Data Formats in Memory ......................................................................................... Instructions........................................................................................................................... 3.4.1 Basic Instruction Formats......................................................................................... 3.4.2 Addressing Modes.................................................................................................... 3.4.3 Effective Address Calculation.................................................................................. Instruction Set ...................................................................................................................... 3.5.1 Overview .................................................................................................................. 3.5.2 Data Transfer Instructions ........................................................................................ 3.5.3 Arithmetic Instructions............................................................................................. 3.5.4 Logic Operations ...................................................................................................... 3.5.5 Shift Operations........................................................................................................ 3.5.6 Bit Manipulations..................................................................................................... 3.5.7 Branching Instructions ............................................................................................. 3.5.8 System Control Instructions ..................................................................................... 3.5.9 Short-Format Instructions ........................................................................................ Operating Modes.................................................................................................................. 3.6.1 Minimum Mode........................................................................................................ 3.6.2 Maximum Mode....................................................................................................... Basic Operational Timing .................................................................................................... 3.7.1 Overview .................................................................................................................. 3.7.2 On-Chip Memory Access Cycle .............................................................................. 3.7.3 Pin States during On-Chip Memory Access ............................................................ 31 31 32 33 34 34 35 40 41 42 43 44 44 45 47 49 49 51 53 54 55 56 57 59 62 62 62 63 63 63 64 65 3.8 3.7.4 Register Field Access Cycle (Addresses H'FF80 to H'FFFF).................................. 3.7.5 Pin States during Register Field Access (Addresses H'FF80 to H'FFFF)................ 3.7.6 External Access Cycle.............................................................................................. CPU States ........................................................................................................................... 3.8.1 Overview .................................................................................................................. 3.8.2 Program Execution State.......................................................................................... 3.8.3 Exception-Handling State ........................................................................................ 3.8.4 Reset State ................................................................................................................ 3.8.5 Power-Down State.................................................................................................... 65 66 66 67 67 69 70 70 70 Section 4 Exception Handling .............................................................................................. 71 4.1 Overview.............................................................................................................................. 4.1.1 Types of Exception Handling and Their Priority ..................................................... 4.1.2 Hardware Exception-Handling Sequence ................................................................ 4.1.3 Exception Sources and Vector Table ........................................................................ 4.2 Reset..................................................................................................................................... 4.2.1 Overview .................................................................................................................. 4.2.2 Reset Sequence......................................................................................................... 4.2.3 Stack Pointer Initialization ....................................................................................... 4.3 Address Error ....................................................................................................................... 4.3.1 Instruction Prefetch from Illegal Address ................................................................ 4.3.2 Word Data Access at Odd Address .......................................................................... 4.3.3 Off-Chip Address Access in Single-Chip Mode ...................................................... 4.4 Trace..................................................................................................................................... 4.5 Interrupts .............................................................................................................................. 4.6 Invalid Instruction................................................................................................................ 4.7 Trap Instructions and Zero Divide ....................................................................................... 4.8 Cases in Which Exception Handling is Deferred ................................................................ 4.8.1 Instructions that Disable Interrupts .......................................................................... 4.8.2 Disabling of Exceptions Immediately after a Reset ................................................. 4.8.3 Disabling of Interrupts after a Data Transfer Cycle ................................................. 4.9 Stack Status after Completion of Exception Handling ........................................................ 4.9.1 PC Value Pushed on Stack for Trace, Interrupts, Trap Instructions, and Zero Divide Exceptions........................................................ 4.9.2 PC Value Pushed on Stack for Address Error and Invalid Instruction Exceptions.............................................................................................. 4.10 Notes on Use of the Stack.................................................................................................... 71 71 72 72 75 75 75 76 79 79 79 79 80 80 82 83 83 84 84 85 86 88 88 88 Section 5 Interrupt Controller .............................................................................................. 89 5.1 5.2 5.3 5.4 Overview.............................................................................................................................. 5.1.1 Features .................................................................................................................... 5.1.2 Block Diagram ......................................................................................................... 5.1.3 Register Configuration ............................................................................................. Interrupt Types ..................................................................................................................... 5.2.1 External Interrupts.................................................................................................... 5.2.2 Internal Interrupts..................................................................................................... 5.2.3 Interrupt Vector Table............................................................................................... Register Descriptions ........................................................................................................... 5.3.1 Interrupt Priority Registers A to D (IPRA to IPRD)................................................ 5.3.2 NMI Control Register (NMICR)--H'FFFC............................................................. 5.3.3 IRQ Control Register (IRQCR)--H'FFFD .............................................................. Interrupt-Handling Sequence ............................................................................................... 89 89 90 91 91 91 93 94 96 96 97 97 100 5.5 5.6 5.4.1 Interrupt-Handling Flow .......................................................................................... 5.4.2 Stack Status after Interrupt Exception-Handling Sequence ..................................... 5.4.3 Timing of Interrupt Exception-Handling Sequence ................................................. Interrupts During Operation of the Data Transfer Controller .............................................. Interrupt Response Time...................................................................................................... 100 103 104 104 107 Section 6 Data Transfer Controller ...................................................................................... 109 6.1 6.2 6.3 6.4 6.5 Overview.............................................................................................................................. 6.1.1 Features .................................................................................................................... 6.1.2 Block Diagram ......................................................................................................... 6.1.3 Register Configuration ............................................................................................. Register Descriptions ........................................................................................................... 6.2.1 Data Transfer Mode Register (DTMR) .................................................................... 6.2.2 Data Transfer Source Address Register (DTSR) ..................................................... 6.2.3 Data Transfer Destination Register (DTDR)........................................................... 6.2.4 Data Transfer Count Register (DTCR) .................................................................... 6.2.5 Data Transfer Enable Registers A to D (DTEA to DTED) ...................................... Data Transfer Operation....................................................................................................... 6.3.1 Data Transfer Cycle.................................................................................................. 6.3.2 DTC Vector Table..................................................................................................... 6.3.3 Location of Register Information in Memory .......................................................... 6.3.4 Length of Data Transfer Cycle................................................................................. Procedure for Using the DTC .............................................................................................. Example ............................................................................................................................... 109 109 109 110 111 111 112 112 112 113 114 114 116 118 118 120 121 Section 7 Wait-State Controller ............................................................................................ 125 7.1 7.2 7.3 Overview.............................................................................................................................. 7.1.1 Features .................................................................................................................... 7.1.2 Block Diagram ......................................................................................................... 7.1.3 Register Configuration ............................................................................................. Wait-State Control Register ................................................................................................. Operation in Each Wait Mode.............................................................................................. 7.3.1 Programmable Wait Mode........................................................................................ 7.3.2 Pin Wait Mode.......................................................................................................... 7.3.3 Pin Auto-Wait Mode ................................................................................................ 125 125 126 126 127 128 128 129 131 Section 8 Clock Pulse Generator ......................................................................................... 133 8.1 8.2 8.3 Overview.............................................................................................................................. 8.1.1 Block Diagram ......................................................................................................... Oscillator Circuit.................................................................................................................. System Clock Divider .......................................................................................................... 133 133 133 136 Section 9 I/O Ports ................................................................................................................... 137 9.1 9.2 9.3 Overview.............................................................................................................................. Port 1.................................................................................................................................... 9.2.1 Overview .................................................................................................................. 9.2.2 Port 1 Registers ........................................................................................................ 9.2.3 Pin Functions in Each Mode .................................................................................... Port 2.................................................................................................................................... 9.3.1 Overview .................................................................................................................. 9.3.2 Port 2 Registers ........................................................................................................ 9.3.3 Pin Functions in Each Mode .................................................................................... 137 141 141 143 144 152 152 152 154 9.4 9.5 9.6 9.7 9.8 Port 3.................................................................................................................................... 9.4.1 Overview .................................................................................................................. 9.4.2 Port 3 Registers ........................................................................................................ 9.4.3 Pin Functions in Each Mode .................................................................................... 9.4.4 Built-In MOS Pull-Up.............................................................................................. Port 4.................................................................................................................................... 9.5.1 Overview .................................................................................................................. 9.5.2 Port 4 Registers ........................................................................................................ 9.5.3 Pin Functions in Each Mode .................................................................................... 9.5.4 Built-in MOS Pull-Up .............................................................................................. Port 5.................................................................................................................................... 9.6.1 Overview .................................................................................................................. 9.6.2 Port 5 Registers ........................................................................................................ 9.6.3 Pin Functions............................................................................................................ Port 6.................................................................................................................................... 9.7.1 Overview .................................................................................................................. 9.7.2 Port 6 Registers ........................................................................................................ Port 7.................................................................................................................................... 9.8.1 Overview .................................................................................................................. 9.8.2 Port 7 Registers ........................................................................................................ 9.8.3 Pin Functions............................................................................................................ 155 155 155 157 158 162 162 163 165 170 171 171 171 173 176 176 177 178 178 180 181 Section 10 16-Bit Free-Running Timers ............................................................................ 189 10.1 Overview.............................................................................................................................. 10.1.1 Features .................................................................................................................... 10.1.2 Block Diagram ......................................................................................................... 10.1.3 Input and Output Pins............................................................................................... 10.1.4 Register Configuration ............................................................................................. 10.2 Register Descriptions ........................................................................................................... 10.2.1 Free-Running Counter (FRC)--H'FF92, H'FFA2.................................................... 10.2.2 Output Compare Registers A and B (OCRA and OCRB)--H'FF94 and H'FF96, H'FFA4 and H'FFA6 .......................... 10.2.3 Input Capture Register (ICR)--H'FF98, H'FFA8 .................................................... 10.2.4 Timer Control Register (TCR)--H'FF90, H'FFA0................................................... 10.2.5 Timer Control/Status Register (TCSR)--H'FF91, H'FFA1 ..................................... 10.3 CPU Interface....................................................................................................................... 10.4 Operation.............................................................................................................................. 10.4.1 FRC Incrementation Timing .................................................................................... 10.4.2 Output Compare Timing .......................................................................................... 10.4.3 Input Capture Timing ............................................................................................... 10.4.4 Setting of FRC Overflow Flag (OVF)...................................................................... 10.5 CPU Interrupts and DTC Interrupts..................................................................................... 10.6 Synchronization of Free-Running Timers 1 and 2............................................................... 10.6.1 Synchronization after a Reset................................................................................... 10.6.2 Synchronization by Writing to FRCs ....................................................................... 10.7 Sample Application.............................................................................................................. 10.8 Application Notes ................................................................................................................ 189 189 190 191 192 193 193 193 194 195 197 199 201 201 202 204 206 206 207 207 207 211 211 Section 11 8-Bit Timer............................................................................................................ 217 11.1 Overview.............................................................................................................................. 11.1.1 Features .................................................................................................................... 11.1.2 Block Diagram ......................................................................................................... 11.1.3 Input and Output Pins............................................................................................... 11.1.4 Register Configuration ............................................................................................. 11.2 Register Descriptions ........................................................................................................... 11.2.1 Timer Counter (TCNT)--H'FFD4 ........................................................................... 11.2.2 Time Constant Registers A and B (TCORA and TCORB)--H'FFD2 and H'FFD3....................................................... 11.2.3 Timer Control Register (TCR)--H'FFD0 ................................................................ 11.2.4 Timer Control/Status Register (TCSR) .................................................................... 11.3 Operation.............................................................................................................................. 11.3.1 TCNT Incrementation Timing.................................................................................. 11.3.2 Compare Match Timing ........................................................................................... 11.3.3 External Reset of TCNT........................................................................................... 11.3.4 Setting of TCNT Overflow Flag .............................................................................. 11.4 CPU Interrupts and DTC Interrupts..................................................................................... 11.5 Sample Application.............................................................................................................. 11.6 Application Notes ................................................................................................................ 217 217 218 219 219 219 219 220 220 222 224 224 226 227 228 229 230 231 Section 12 Watchdog Timer .................................................................................................. 237 12.1 Overview.............................................................................................................................. 12.1.1 Features .................................................................................................................... 12.1.2 Block Diagram ......................................................................................................... 12.1.3 Register Configuration ............................................................................................. 12.2 Register Descriptions ........................................................................................................... 12.2.1 Timer Counter (TCNT)--H'FFED........................................................................... 12.2.2 Timer Control/Status Register (TCSR)--H'FFEC (Read), H'FFED (Write) ........... 12.2.3 Reset Control/Status Register (RSTCSR)--H'FFFF (Read), H'FFFE (Write) ........ 12.2.4 Notes on Register Access......................................................................................... 12.3 Operation.............................................................................................................................. 12.3.1 Watchdog Timer Mode............................................................................................. 12.3.2 Interval Timer Mode ................................................................................................ 12.3.3 Operation in Software Standby Mode...................................................................... 12.3.4 Setting of Overflow Flag.......................................................................................... 12.3.5 Setting of Watchdog Timer Reset (WRST) Bit........................................................ 12.4 Application Notes ................................................................................................................ 237 237 238 239 239 239 240 241 242 244 244 246 246 247 248 248 Section 13 Serial Communication Interface ..................................................................... 251 13.1 Overview.............................................................................................................................. 13.1.1 Features .................................................................................................................... 13.1.2 Block Diagram ......................................................................................................... 13.1.3 Input and Output Pins............................................................................................... 13.1.4 Register Configuration ............................................................................................. 13.2 Register Descriptions ........................................................................................................... 13.2.1 Receive Shift Register (RSR)................................................................................... 13.2.2 Receive Data Register (RDR)--H'FFDD (Channel 1), H'FFC5 (Channel 2).......... 13.2.3 Transmit Shift Register (TSR) ................................................................................. 13.2.4 Transmit Data Register (TDR)--H'FFDB (Channel 1), H'FFC3 (Channel 2)......... 13.2.5 Serial Mode Register (SMR)--H'FFD8 (Channel 1), H'FFC0 (Channel 2) ............ 13.2.6 Serial Control Register (SCR)--H'FFDA (Channel 1), H'FFC2 (Channel 2) ......... 251 251 252 253 253 254 254 254 254 255 255 257 13.2.7 Serial Status Register (SSR)--H'FFDC (Channel 1), H'FFC4 (Channel 2) ............ 13.2.8 Bit Rate Register (BRR)--H'FFD9 (Channel 1), H'FFC1 (Channel 2) ................... 13.3 Operation.............................................................................................................................. 13.3.1 Overview .................................................................................................................. 13.3.2 Asynchronous Mode ................................................................................................ 13.3.3 Synchronous Mode................................................................................................... 13.4 CPU Interrupts and DTC Interrupts..................................................................................... 13.5 Application Notes ................................................................................................................ 259 261 267 267 268 272 276 277 Section 14 A/D Converter ..................................................................................................... 14.1 Overview.............................................................................................................................. 14.1.1 Features .................................................................................................................... 14.1.2 Block Diagram ......................................................................................................... 14.1.3 Input Pins.................................................................................................................. 14.1.4 Register Configuration ............................................................................................. 14.2 Register Descriptions ........................................................................................................... 14.2.1 A/D Data Registers (ADDR)--H'FFE0 to H'FFE7 ................................................. 14.2.2 A/D Control/Status Register (ADCSR)--H'FFE8 ................................................... 14.2.3 A/D Control Register (ADCR)--H'FFE9 ................................................................ 14.3 CPU Interface....................................................................................................................... 14.4 Operation.............................................................................................................................. 14.4.1 Single Mode ............................................................................................................. 14.4.2 Scan Mode................................................................................................................ 14.4.3 Input Sampling Time and A/D Conversion Time .................................................... 14.4.4 External Triggering of A/D Conversion................................................................... 14.5 Interrupts and the Data Transfer Controller......................................................................... 281 281 281 282 283 284 284 284 285 287 288 289 290 293 295 297 297 Section 15 RAM ....................................................................................................................... 299 15.1 Overview.............................................................................................................................. 15.1.1 Block Diagram ......................................................................................................... 15.1.2 Register Configuration ............................................................................................. 15.2 RAM Control Register (RAMCR)....................................................................................... 15.3 Operation.............................................................................................................................. 15.3.1 Expanded Modes (Modes 1, 2, 3 and 4)................................................................... 15.3.2 Single-Chip Mode (Mode 7) .................................................................................... 299 299 300 300 300 300 301 Section 16 ROM ....................................................................................................................... 303 16.1 Overview.............................................................................................................................. 16.1.1 Block Diagram ......................................................................................................... 16.2 PROM Mode........................................................................................................................ 16.2.1 PROM Mode Setup .................................................................................................. 16.2.2 Socket Adapter Pin Arrangements and Memory Map ............................................. 16.3 Programming........................................................................................................................ 16.3.1 Writing and Verifying............................................................................................... 16.3.2 Notes on Writing ...................................................................................................... 16.3.3 Reliability of Written Data ....................................................................................... 16.3.4 Erasing of Data......................................................................................................... 16.4 Handling of Windowed Packages ........................................................................................ 303 303 304 304 305 307 307 310 311 312 312 Section 17 Power-Down State .............................................................................................. 313 17.1 Overview.............................................................................................................................. 313 17.2 Sleep Mode .......................................................................................................................... 314 17.2.1 Transition to Sleep Mode ......................................................................................... 17.2.2 Exit from Sleep Mode .............................................................................................. 17.3 Software Standby Mode....................................................................................................... 17.3.1 Transition to Software Standby Mode...................................................................... 17.3.2 Software Standby Control Register (SBYCR) ......................................................... 17.3.3 Exit from Software Standby Mode........................................................................... 17.3.4 Sample Application of Software Standby Mode...................................................... 17.3.5 Application Notes..................................................................................................... 17.4 Hardware Standby Mode ..................................................................................................... 17.4.1 Transition to Hardware Standby Mode .................................................................... 17.4.2 Recovery from Hardware Standby Mode................................................................. 17.4.3 Timing Sequence of Hardware Standby Mode ........................................................ 314 314 314 314 315 316 316 317 317 317 318 318 Section 18 Electrical Specifications .................................................................................... 321 18.1 Absolute Maximum Ratings ................................................................................................ 18.2 Electrical Characteristics ..................................................................................................... 18.2.1 DC Characteristics.................................................................................................... 18.2.2 AC Characteristics.................................................................................................... 18.2.3 A/D Converter Characteristics ................................................................................. 18.3 MCU Operational Timing.................................................................................................... 18.3.1 Bus Timing ............................................................................................................... 18.3.2 Control Signal Timing.............................................................................................. 18.3.3 Clock Oscillator Stabilization Timing...................................................................... 18.3.4 I/O Port Timing ........................................................................................................ 18.3.5 16-Bit Free-Running Timer Timing ......................................................................... 18.3.6 8-Bit Timer Timing .................................................................................................. 18.3.7 Serial Communication Interface Timing.................................................................. 18.3.8 A/D External Trigger Input Timing ......................................................................... 321 321 321 324 327 328 328 330 331 332 333 334 335 335 Appendix A Instructions ........................................................................................................ 337 A.1 A.2 A.3 A.4 Instruction Set ...................................................................................................................... Instruction Codes ................................................................................................................. Operation Code Map............................................................................................................ Instruction Execution Cycles ............................................................................................... A.4.1 Calculation of Instruction Execution States ............................................................. A.4.2 Tables of Instruction Execution Cycles.................................................................... 337 342 353 358 358 359 Appendix B Register Field .................................................................................................... 367 B.1 B.2 Register Addresses and Bit Names ...................................................................................... 367 Register Descriptions ........................................................................................................... 372 Appendix C I/O Port Schematic Diagrams ....................................................................... 405 C.1 C.2 C.3 C.4 C.5 C.6 C.7 Schematic Diagram of Port 1............................................................................................... Schematic Diagram of Port 2............................................................................................... Schematic Diagram of Port 3............................................................................................... Schematic Diagram of Port 4............................................................................................... Schematic Diagram of Port 5............................................................................................... Schematic Diagram of Port 6............................................................................................... Schematic Diagram of Port 7............................................................................................... 405 410 411 412 414 421 422 Appendix D Memory Map .................................................................................................... 426 Appendix E Pin States ............................................................................................................ 427 E.1 E.2 Port State of Each Pin State ................................................................................................. 427 Pin Status in the Reset State................................................................................................. 431 Appendix F Package Dimensions ........................................................................................ 438 viii Section 1 Overview 1.1 Features The H8/520 is an original Hitachi CMOS microcomputer unit (MCU) comprising a high-performance CPU core plus a full range of supporting functions--an entire system integrated onto a single chip. The CPU features a highly orthogonal instruction set that permits addressing modes and data sizes to be specified independently in each instruction. An internal 16-bit architecture and 16-bit access to onchip memory enhance the CPU's data-processing capability and provide the speed needed for realtime control applications. The address space can be expanded to perform high-volume data processing. The on-chip supporting functions include RAM, ROM, timers, a serial communication interface (SCI), A/D converter, and I/O ports. An on-chip data transfer controller (DTC) provides an efficient way to transfer data in either direction between memory and I/O. For the on-chip ROM, a choice is offered between masked ROM and programmable ROM (PROM). The PROM version can be programmed by the user with a general-purpose PROM writer. Table 1-1 lists the main features of the H8/520 chip. 1 Table 1-1 Features Feature Description CPU General-register machine * Eight 16-bit general registers * Five 8-bit and two 16-bit control registers High speed * Maximum clock rate: 10 MHz (oscillator frequency: 20 MHz) Expanded operating modes supporting external memory * Minimum mode: up to 64-kbyte address space * Maximum mode: up to 1-Mbyte address space Highly orthogonal instruction set * Addressing modes and data size can be specified independently for each instruction Instructions can address registers or memory * Register-register operations * Register-memory operations Instruction set optimized for C language Memory * Special short formats for frequently-used instructions and addressing modes * 512-Byte high-speed RAM on-chip * 16-kbyte programmable or masked ROM on-chip 16-Bit free- Each channel provides: running * 1 free-running counter (which can count external events) timer * 2 output-compare registers (2 channels) * 1 input capture register 8-Bit timer * One 8-bit up-counter (which can count external events) (1 channel) * 2 time constant registers Watchdog * An overflow generates a reset timer * Can output an external reset signal (1 channel) * Can also be used as an interval timer 2 Table 1-1 Features (cont) Feature Description Serial com- * Asynchronous or synchronous mode (selectable) munication * Full duplex: can send and receive simultaneously interface (SCI) * Built-in baud rate generator * 10-Bit resolution * 4 (or 8*) channels, controllable in single mode or scan mode (selectable) * Sample-and-hold function * Can be externally triggered * 46 input/output pins (five 8-bit ports, one 6-bit port) * 4 (or 8*) input-only pins (one 4- or 8*-bit port) Interrupt * 9 external interrupt pins (NMI, IRQ0 to IRQ7) controller * 18 internal interrupts (INTC) * 8 priority levels Data transfer Performs efficient, rapid, bidirectional data transfer between memory and I/O with controller (DTC) minimal CPU programming. Wait-state Can insert wait states in access to external memory or I/O (2 channels) A/D converter I/O ports controller (WSC) Operating 5 MCU operating modes modes * Expanded minimum modes, supporting up to 64 kbytes external memory with or without using on-chip ROM (Modes 1 and 2) * Expanded maximum modes, supporting up to 1 Mbyte external memory with or without using on-chip ROM (Modes 3 and 4) * Single-chip mode (Mode 7) 3 power-down modes * Sleep mode * Software standby mode * Hardware standby mode Other features * Clock generator on-chip Product line-up Model Name Package Options ROM HD6475208C 64-Pin windowed shrink DIP (DC-64S) PROM HD6475208P 64-Pin shrink DIP (DP-64S) HD6475208CP 68-Pin PLCC (CP-68) HD6475208F 64-Pin QFP (FP-64A) HD6435208P 64-Pin shrink DIP (DP-64S) Masked HD6435208CP 68-Pin PLCC (CP-68) ROM HD6435208F 64-Pin QFP (FP-64A) Note: * CP- 68 package only. 3 1.2 Block Diagram P20 /D 0 P21 /D 1 P22 /D 2 P23 /D3 P24 /D 4 P25 /D5 P26 /D6 P27 /D 7 P10 /WAIT P11 /IRQ0 P12 /A 18 /IRQ1 /ADTRG P13 /A 17/IRQ 2 P14 /A 16 /IRQ 3 P15 /AS P16 /RD P17 /WR Figure 1-1 shows a block diagram of the H8/520 chip. Port 1 Port 3 PROM/masked ROM 16 kbytes RAM 512 bytes Port 4 MD 0 MD 1 MD 2 Waitstate controller P3 0 /A0 P3 1 /A1 P3 2 /A2 P3 3 /A3 P3 4 /A4 P3 5 /A5 P3 6 /A6 P3 7 /A7 P4 0 /A8 P4 1 /A9 P4 2 /A10 P4 3 /A11 P4 4 /A12 /IRQ4 P4 5 /A13 /IRQ5 P4 6 /A14 /IRQ6 P4 7 /A15 /IRQ7 Address bus RES (High) Data bus (High) (Low) XTAL Clock Generator Data bus (Low) EXTAL Port 2 Interrupt controller CPU Data transfer controller NMI Serial communication interface (x 2 channels) Vcc Vss 8 bit timer 16 bit freerunning timer (x 2 channels) 10-bit A/D converter (4 or 8* channels) Port 5 Port 6 P57/FTOA2/o P56/FTOA1 P55/FTOB2/FTCI2 P54/FTOB1/FTCI1 P53/TMO P52/FTI2/TMRI P51/FTI1 P50/TMCI P75/SCK 1 P74/RXD1 P73/TXD1 P72/SCK 2/A19 P71/RXD2 P70/TXD2 Port 7 Watchdog timer P67/AN7 * P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 AVcc AVss Note: * CP-68 package only Figure 1-1 Block Diagram 4 1.3 Pin Arrangements and Functions 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the DC-64S and DP-64S packages. Figure 1-3 shows the pin arrangement of the FP-64A package. Figure 1-4 shows the pin arrangement of the CP-68 package. EXTAL 1 64 VSS XTAL 2 63 P75 /SCK 1 P10/WAIT 3 62 P11/IRQ 0 4 61 P74 /RXD1 P73 /TXD1 P12/A 18 /ADTRG/IRQ1 5 60 P72 /SCK2/A 19 P13/A 17 /IRQ 2 6 59 P71 /RXD 2 P14/A 16 /IRQ 3 7 58 P15/AS 8 57 P70 /TXD2 AVcc P16/RD 9 56 P17/WR 10 55 P6 3 /AN 3 P6 2 /AN 2 VCC 11 54 P6 1 /AN 1 MD0 12 53 P6 0 /AN 0 MD1 13 52 AVss MD2 14 51 Vss RES 15 50 NMI 16 49 DC - 64S DP - 64S 48 18 47 P5 4 /FTOB1 /FTCI1 P21/D1 19 46 P53 /TMO P22/D2 20 45 P52 /FTI2 /TMRI P23/D3 21 44 P5 1 /FTI1 P24/D4 22 43 P5 0 /TMCI P25/D5 23 42 Vcc P26/D6 24 41 P27/D7 25 40 P47 /A15 /IRQ7 P46 /A14 /IRQ6 P30/A 0 26 39 P31/A 1 27 38 P45 /A13 /IRQ5 P4 4 /A12 /IRQ4 P32/A 2 28 37 P43 /A11 P33/A 3 29 36 P42 /A10 P34/A 4 30 35 P41 /A9 P35/A 5 31 34 P36/A 6 32 33 P40 /A8 P37 /A7 JAPAN 17 P20/D0 H8/520 HD6475208C VSS P57 /FTOA2 /o P5 6 /FTOA1 P55 /FTOB2 /FTCI2 H8/520 HD6475208P JAPAN Pin No. 1 Pin No. 1 DC - 64S DP - 64S Figure 1-2 Pin Arrangement (DC-64S, DP-64S, Top View) 5 AVCC P70/TXD2 P71/RXD2 P72/SCK2/A19 P73/TXD1 P74/RXD1 VSS P75/SCK1 EXTAL XTAL P10/WAIT P11/IRQ0 P16/RD 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 P63/AN3 P17/WR 2 47 P62/AN2 VCC 3 46 P61/AN1 MD0 4 45 P60/AN0 MD1 5 44 AVSS MD2 6 43 VSS RES 7 42 P57/FTOA2/o NMI 8 41 P56/FTOA1 VSS 9 40 P55/FTOB2/FTCI2 P20/D0 10 39 P54/FTOB1/FTCI1 P21/D1 11 38 P53/TMO P22/D2 12 37 P52/FTI2/TMRI P23/D3 13 36 P51/FTI1 P24/D4 14 35 P50/TMCI P25/D5 15 34 VCC P26/D6 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P47/A15 /IRQ7 P46/A14 /IRQ6 P45/A13 /IRQ5 P43/A11 P44/A12 /IRQ4 P41/A9 P42/A10 P40/A8 P37/A7 P36/A6 P35/A5 P34/A4 P33/A3 P32/A2 P31/A1 P30/A0 P27/D7 FP - 64A Pin No. 1 H8/520 HD6475208F JAPAN Figure 1-3 Pin Arrangement (FP-64A, Top View) Figure 1-3 6 P66/AN6 P67/AN7 AVCC P70/TXD2 P71/RXD2 P72/SCK2/A 19 P73/TXD1 P74/RXD1 P75/SCK1 VSS EXTAL XTAL P17/WR 12 58 P63/AN3 VCC 13 57 P62/AN2 MD0 14 56 P61/AN1 MD1 15 55 P60/AN0 MD2 16 54 AVSS RES 17 53 VSS NMI 18 52 P57/FTOA2/o VSS 19 51 P56/FTOA1 P20/D0 20 50 P55/FTOB2/FTCI2 P21/D1 21 49 P54/FTOB1/FTCI1 P22/D2 22 48 P53/TMO P23/D3 23 47 P52/FTI2/TMRI P24/D4 24 46 P51/FTI1 P25/D5 25 45 P50/TMCI P26/D6 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 P64/AN4 VCC P47/A 15 /IRQ 7 P46/A 14 /IRQ 6 P45/A 13 /IRQ 5 P44/A 12 /IRQ 4 P43/A 11 P42/A 10 P41/A 9 P40/A 8 P37/A 7 P36/A 6 P35/A 5 P34/A 4 P33/A 3 P32/A 2 P31/A 1 CP - 68 P30/A 0 P27/D7 P65/AN5 P16/RD 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 10 59 11 P15/AS Pin No. 1 H8/520 HD6475208CP JAPAN Figure 1-4 Pin Arrangement (CP-68, Top View) 7 Figure 1-4 1.3.2 Pin Functions Pin Arrangements in Each Operating Mode: Table 1-2 lists the arrangements of the pins of the DC-64S and DP-64S packages in each operating mode. Table 1-3 lists the arrangements for the FP-64A package. Table 1-4 lists the arrangements for the CP-68 package. Table 1-2 Pin Arrangements in Each Operating Mode (DC-64S , DP-64S ) Pin Name Expanded Minimum Pin Modes Expanded Maximum Single-Chip Modes Mode PROM No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Mode 1 EXTAL EXTAL EXTAL EXTAL EXTAL NC 2 XTAL XTAL XTAL XTAL XTAL NC 3 P10 / WAIT P10 / WAIT P10 / WAIT P10 / WAIT P10 NC 4 P11 / IRQ0 P11 / IRQ0 P11 / IRQ0 P11 / IRQ0 P11 / IRQ0 NC 5 P12 / IRQ1 / P12 / IRQ1 / A18 P12 / A18 / IRQ1 / P12 / IRQ1 / NC ADTRG ADTRG ADTRG ADTRG 6 P13 / IRQ2 P13 / IRQ2 A17 P13 / A17 / IRQ2 P13 / IRQ2 NC 7 P14 / IRQ3 P14 / IRQ3 A16 P14 / A16 / IRQ3 P14 / IRQ3 NC 8 AS AS AS AS P15 NC 9 RD RD RD RD P16 NC 10 WR WR WR WR P17 NC 11 VCC VCC VCC VCC VCC VCC 12 MD0 MD0 MD0 MD0 MD0 VCC 13 MD1 MD1 MD1 MD1 MD1 VSS 14 MD2 MD2 MD2 MD2 MD2 VCC 15 RES RES RES RES RES VPP 16 NMI NMI NMI NMI NMI A9 17 VSS VSS VSS VSS VSS VSS 18 D0 D0 D0 D0 P20 00 19 D1 D1 D1 D1 P21 01 20 D2 D2 D2 D2 P22 02 21 D3 D3 D3 D3 P23 03 22 D4 D4 D4 D4 P24 04 Notes: 1. For the PROM mode, see section 16, "ROM." 2. Pins marked NC should be left unconnected. 8 Table 1-2 Pin Arrangements in Each Operating Mode (DC-64S, DP-64S) (cont) Pin Name Expanded Minimum Pin Modes Expanded Maximum Single-Chip Modes Mode PROM No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Mode 23 D5 D5 D5 D5 P25 05 24 D6 D6 D6 D6 P26 06 25 D7 D7 D7 D7 P27 07 26 A0 A0 A0 A0 P30 A0 27 A1 A1 A1 A1 P31 A1 28 A2 A2 A2 A2 P32 A2 29 A3 A3 A3 A3 P33 A3 30 A4 A4 A4 A4 P34 A4 31 A5 A5 A5 A5 P35 A5 32 A6 A6 A6 A6 P36 A6 33 A7 A7 A7 A7 P37 A7 34 A8 P40 / A8 A8 P40 / A8 P40 A8 35 A9 P41 / A9 A9 P41 / A9 P41 OE 36 A10 P42 / A10 A10 P42 / A10 P42 A10 37 A11 P43 / A11 A11 P43 / A11 P43 A11 38 A12 P44 / A12 / IRQ4 A12 P44 / A12 / IRQ4 P44 / IRQ4 A12 39 A13 P45 / A13 / IRQ5 A13 P45 / A13 / IRQ5 P45 / IRQ5 A13 40 A14 P46 / A14 / IRQ6 A14 P46 / A14 / IRQ6 P46 / IRQ6 A14 41 A15 P47 / A15 / IRQ7 A15 P47 / A15 / IRQ7 P47 / IRQ7 CE 42 VCC VCC VCC VCC VCC VCC 43 P50 / TMCI P50 / TMCI P50 / TMCI P50 / TMCI P50 / TMCI VCC 44 P51 / FTI1 P51 / FTI1 P51 / FTI1 P51 / FTI1 P51 / FTI1 VCC 45 P52 / FTI2 / P52 / FTI2 / P52 / FTI2 / P52 / FTI2 / P52 / FTI2 / NC TMRI TMRI TMRI TMRI TMRI 46 P53 / TMO P53 / TMO P53 / TMO P53 / TMO P53 / TMO NC 47 P54 / FTOB1 / P54 / FTOB1 / P54 / FTOB1 / P54 / FTOB1 / P54 / FTOB1 / NC FTCI1 FTCI1 FTCI1 FTCI1 FTCI1 Notes: 1. For the PROM mode, see section 16, "ROM." 2. Pins marked NC should be left unconnected. 9 Table 1-2 Pin Arrangements in Each Operating Mode (DC-64S, DP-64S) (cont) Pin Name Expanded Minimum Pin Modes Expanded Maximum Single-Chip Modes Mode PROM Mode 7 Mode NC No. Mode 1 Mode 2 Mode 3 Mode 4 48 P55 / FTOB2 / P55 / FTOB2 / P55 / FTOB2 / P55 / FTOB2 / P55 / FTOB2 / FTCI2 FTCI2 FTCI2 FTCI2 FTCI2 49 P56 / FTOA1 P56 / FTOA1 P56 / FTOA1 P56 / FTOA1 P56 / FTOA1 NC 50 P57 / FTOA2 / o P57 / FTOA2 / o P57 / FTOA2 / o P57 / FTOA2 / o P57 / FTOA2 / o NC 51 VSS VSS VSS VSS VSS VSS 52 AVSS AVSS AVSS AVSS AVSS VSS 53 P60 / AN0 P60 / AN0 P60 / AN0 P60 / AN0 P60 / AN0 NC 54 P61 / AN1 P61 / AN1 P61 / AN1 P61 / AN1 P61 / AN1 NC 55 P62 / AN2 P62 / AN2 P62 / AN2 P62 / AN2 P62 / AN2 NC 56 P63 / AN3 P63 / AN3 P63 / AN3 P63 / AN3 P63 / AN3 NC 57 AVCC AVCC AVCC AVCC AVCC VCC 58 P70 / TXD2 P70 / TXD2 P70 / TXD2 P70 / TXD2 P70 / TXD2 NC 59 P71 / RXD2 P71 / RXD2 P71 / RXD2 P71 / RXD2 P71 / RXD2 NC 60 P72 / SCK2 P72 / SCK2 A19 P72 / SCK2 / A19 P72 / SCK2 NC 61 P73 / TXD1 P73 / TXD1 P73 / TXD1 P73 / TXD1 P73 / TXD1 NC 62 P74 / RXD1 P74 / RXD1 P74 / RXD1 P74 / RXD1 P74 / RXD1 NC 63 P75 / SCK1 P75 / SCK1 P75 / SCK1 P75 / SCK1 P75 / SCK1 NC 64 VSS VSS VSS VSS VSS VSS Notes: 1. For the PROM mode, see section 16, "ROM." 2. Pins marked NC should be left unconnected. 10 Table 1-3 Pin Arrangements in Each Operating Mode (FP-64A) Pin Name Expanded Minimum Pin Modes Expanded Maximum Single-Chip Modes Mode PROM No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Mode 1 RD RD RD RD P16 NC 2 WR WR WR WR P17 NC 3 VCC VCC VCC VCC VCC VCC 4 MD0 MD0 MD0 MD0 MD0 VCC 5 MD1 MD1 MD1 MD1 MD1 VSS 6 MD2 MD2 MD2 MD2 MD2 VCC 7 RES RES RES RES RES VPP 8 NMI NMI NMI NMI NMI A9 9 VSS VSS VSS VSS VSS VSS 10 D0 D0 D0 D0 P20 O0 11 D1 D1 D1 D1 P21 O1 12 D2 D2 D2 D2 P22 O2 13 D3 D3 D3 D3 P23 O3 14 D4 D4 D4 D4 P24 O4 15 D5 D5 D5 D5 P25 O5 16 D6 D6 D6 D6 P26 O6 17 D7 D7 D7 D7 P27 O7 18 A0 P30/A0 A0 P30/A0 P30 A0 19 A1 P31/A1 A1 P31/A1 P31 A1 20 A2 P32/A2 A2 P32/A2 P32 A2 21 A3 P33/A3 A3 P33/A3 P33 A3 22 A4 P34/A4 A4 P34/A4 P34 A4 23 A5 P35/A5 A5 P35/A5 P35 A5 24 A6 P36/A6 A6 P36/A6 P36 A6 25 A7 P37/A7 A7 P37/A7 P37 A7 26 A8 P40 / A8 A8 P40 / A8 P40 A8 27 A9 P41 / A9 A9 P41 / A9 P41 OE 28 A10 P42 / A10 A10 P42 / A10 P42 A10 29 A11 P43 / A11 A11 P43 / A11 P43 A11 Notes: 1. For the PROM mode, see section 16, "ROM." 2. Pins marked NC should be left unconnected. 11 Table 1-3 Pin Arrangements in Each Operating Mode (FP-64A) (cont) Pin Name Expanded Minimum Pin Modes Expanded Maximum Single-Chip Modes Mode PROM Mode 7 Mode No. Mode 1 Mode 2 Mode 3 30 A12 P44 / A12 / IRQ4 A12 P44 / A12 / IRQ4 P44 / IRQ4 A12 31 A13 P45 / A13 / IRQ5 A13 P45 / A13 / IRQ5 P45 / IRQ5 A13 32 A14 P46 / A14 / IRQ6 A14 P46 / A14 / IRQ6 P46 / IRQ6 A14 33 A15 P47 / A15 / IRQ7 A15 P47 / A15 / IRQ7 P47 / IRQ7 CE 34 VCC VCC VCC VCC VCC VCC 35 P50 /TMCI P50 /TMCI P50 /TMCI P50 /TMCI P50 /TMCI VCC 36 P51 /FTI1 P51 /FTI1 P51 /FTI1 P51 FTI1 P51 /FTI1 VCC 37 P52 /FTI2 / P52 /FTI2 / P52 /FTI2 / P52 /FTI2 / P52 /FTI2 / NC TMRI TMRI TMRI TMRI TMRI 38 P53/TMO P53/TMO P53/TMO P53/TMO P53/TMO NC 39 P54 /FTOB1 / P54 /FTOB1 / P54 /FTOB1 / P54 /FTOB1 / P54 /FTOB1 / NC FTCI1 FTCI1 FTCI1 FTCI1 FTCI1 P55 /FTOB2 / P55 /FTOB2 / P55 /FTOB2 / P55 /FTOB2 / P55 /FTOB2 / FTCI2 FTCI2 FTCI2 FTCI2 FTCI2 41 P56 /FTOA1 P56 /FTOA1 P56 /FTOA1 P56 /FTOA1 P56 /FTOA1 NC 42 P57 /FTOA2 / o P57 /FTOA2 / o P57 /FTOA2 / o P57 /FTOA2 / o P57 /FTOA2 / o NC 43 VSS VSS VSS VSS VSS VSS 44 AVSS AVSS AVSS AVSS AVSS VSS 45 P60 / AN0 P60 / AN0 P60 / AN0 P60 / AN0 P60 / AN0 NC 46 P61 / AN1 P61 / AN1 P61 / AN1 P61 / AN1 P61 / AN1 NC 47 P62 / AN2 P62 / AN2 P62 / AN2 P62 / AN2 P62 / AN2 NC 48 P63 / AN3 P63 / AN3 P63 / AN3 P63 / AN3 P63 / AN3 NC 49 AVCC AVCC AVCC AVCC AVCC VCC 50 P70 / TXD2 P70 / TXD2 P70 / TXD2 P70 / TXD2 P70 / TXD2 NC 40 Mode 4 Notes: 1. For the PROM mode, see section 16, "ROM." 2. Pins marked NC should be left unconnected. 12 NC Table 1-3 Pin Arrangements in Each Operating Mode (FP-64A) (cont) Pin Name Expanded Minimum Pin Modes Expanded Maximum Single-Chip Modes Mode PROM No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Mode 51 P71 / RXD2 P71 / RXD2 P71 / RXD2 P71 / RXD2 P71 / RXD2 NC 52 P72 / SCK2 P72 / SCK2 A19 P72 / SCK2 / A19 P72 / SCK2 NC 53 P73 / TXD1 P73 / TXD1 P73 / TXD1 P73 / TXD1 P73 / TXD1 NC 54 P74 / RXD1 P74 / RXD1 P74 / RXD1 P74 / RXD1 P74 / RXD1 NC 55 P75 / SCK1 P75 / SCK1 P75 / SCK1 P75 / SCK1 P75 / SCK1 NC 56 VSS VSS VSS VSS VSS VSS 57 EXTAL EXTAL EXTAL EXTAL EXTAL NC 58 XTAL XTAL XTAL XTAL XTAL NC 59 P10 / WAIT P10 / WAIT P10 / WAIT P10 / WAIT P10 NC 60 P11 / IRQ0 P11 / IRQ0 P11 / IRQ0 P11 / IRQ0 P11 / IRQ0 NC 61 P12 / IRQ1 / P12 / IRQ1 / A18 P12 / A18 / P12 / IRQ1 / NC ADTRG ADTRG IRQ1/ ADTRG ADTRG 62 P13 / IRQ2 P13 / IRQ2 A17 P13 / A17 / IRQ2 P13 / IRQ2 NC 63 P14 / IRQ3 P14 / IRQ3 A16 P14 / A16 / IRQ3 P14 / IRQ3 NC 64 AS AS AS AS P15 NC Notes: 1. For the PROM mode, see section 16, "ROM." 2. Pins marked NC should be left unconnected. 13 Table 1-4 Pin Arrangements in Each Operating Mode (CP-68) Pin Name Expanded Minimum Pin Modes Expanded Maximum Single-Chip Modes Mode PROM No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Mode 1 P75 / SCK1 P75 / SCK1 P75 / SCK1 P75 / SCK1 P75 / SCK1 NC 2 VSS VSS VSS VSS VSS VSS 3 EXTAL EXTAL EXTAL EXTAL EXTAL NC 4 XTAL XTAL XTAL XTAL XTAL NC 5 P10 / WAIT P10 / WAIT P10 / WAIT P10 / WAIT P10 NC 6 P11 / IRQ0 P11 / IRQ0 P11 / IRQ0 P11 / IRQ0 P11 / IRQ0 NC 7 P12 / IRQ1 / P12 / IRQ1 / A18 P12 / A18 / P12 / IRQ1 / NC ADTRG ADTRG IRQ1 / ADTRG ADTRG 8 P13 / IRQ2 P13 / IRQ2 A17 P13 / A17 / IRQ2 P13 / IRQ2 NC 9 P14 / IRQ3 P14 / IRQ3 A16 P14 / A16 / IRQ3 P14 / IRQ3 NC 10 AS AS AS AS P15 NC 11 RD RD RD RD P16 NC 12 WR WR WR WR P17 NC 13 VCC VCC VCC VCC VCC VCC 14 MD0 MD0 MD0 MD0 MD0 VCC 15 MD1 MD1 MD1 MD1 MD1 VSS 16 MD2 MD2 MD2 MD2 MD2 VCC 17 RES RES RES RES RES VPP 18 NMI NMI NMI NMI NMI A9 19 VSS VSS VSS VSS VSS VSS 20 D0 D0 D0 D0 P20 00 21 D1 D1 D1 D1 P21 01 22 D2 D2 D2 D2 P22 02 23 D3 D3 D3 D3 P23 03 24 D4 D4 D4 D4 P24 04 Notes: 1. For the PROM mode, see section 16, "ROM." 2. Pins marked NC should be left unconnected. 14 Table 1-4 Pin Arrangements in Each Operating Mode (CP-68) (cont) Pin Name Expanded Minimum Pin Modes Expanded Maximum Single-Chip Modes Mode PROM No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Mode 25 D5 D5 D5 D5 P25 05 26 D6 D6 D6 D6 P26 06 27 D7 D7 D7 D7 P27 07 28 A0 A0 A0 A0 P30 A0 29 A1 A1 A1 A1 P31 A1 30 A2 A2 A2 A2 P32 A2 31 A3 A3 A3 A3 P33 A3 32 A4 A4 A4 A4 P34 A4 33 A5 A5 A5 A5 P35 A5 34 A6 A6 A6 A6 P36 A6 35 A7 A7 A7 A7 P37 A7 36 A8 P40 / A8 A8 P40 / A8 P40 A8 37 A9 P41 / A9 A9 P41 / A9 P41 OE 38 A10 P42 / A10 A10 P42 / A10 P42 A10 39 A11 P43 / A11 A11 P43 / A11 P43 A11 40 A12 P44 / A12 / IRQ4 A12 P44 / A12 / IRQ4 P44 / IRQ4 A12 41 A13 P45 / A13 / IRQ5 A13 P45 / A13 / IRQ5 P45 / IRQ5 A13 42 A14 P46 / A14 / IRQ6 A14 P46 / A14 / IRQ6 P46 / IRQ6 A14 43 A15 P47 / A15 / IRQ7 A15 P47 / A15 / IRQ7 P47 / IRQ7 CE 44 VCC VCC VCC VCC VCC VCC 45 P50 / TMCI P50 / TMCI P50 / TMCI P50 / TMCI P50 / TMCI VCC 46 P51 / FTI1 P51 / FTI1 P51 / FTI1 P51 / FTI1 P51 / FTI1 VCC 47 P52 / FTI2 / P52 / FTI2 / P52 / FTI2 / P52 / FTI2 / P52 / FTI2 / NC TMRI TMRI TMRI TMRI TMRI Notes: 1. For the PROM mode, see section 16, "ROM." 2. Pins marked NC should be left unconnected. 15 Table 1-4 Pin Arrangements in Each Operating Mode (CP-68) (cont) Pin Name Expanded Minimum Pin Modes Expanded Maximum Single-Chip Modes Mode PROM Mode 7 Mode No. Mode 1 Mode 2 Mode 3 48 P53 / TMO P53 / TMO P53 / TMO P53 / TMO P53 / TMO NC 49 P54 / FTOB1 / P54 / FTOB1 / P54 / FTOB1 / P54 / FTOB1 / P54 / FTOB1 / NC FTCI1 FTCI1 FTCI1 FTCI1 FTCI1 P55 / FTOB2 / P55 / FTOB2 / P55 / FTOB2 / P55 / FTOB2 / P55 / FTOB2 / FTCI2 FTCI2 FTCI2 FTCI2 FTCI2 51 P56 / FTOA1 P56 / FTOA1 P56 / FTOA1 P56 / FTOA1 P56 / FTOA1 NC 52 P57 / FTOA2 / o P57 / FTOA2 / o P57 / FTOA2 / o P57 / FTOA2 / o P57 / FTOA2 / o NC 53 VSS VSS VSS VSS VSS VSS 54 AVSS AVSS AVSS AVSS AVSS VSS 55 P60 / AN0 P60 / AN0 P60 / AN0 P60 / AN0 P60 / AN0 NC 56 P61 / AN1 P61 / AN1 P61 / AN1 P61 / AN1 P61 / AN1 NC 57 P62 / AN2 P62 / AN2 P62 / AN2 P62 / AN2 P62 / AN2 NC 58 P63 / AN3 P63 / AN3 P63 / AN3 P63 / AN3 P63 / AN3 NC 59 P64 / AN4 P64 / AN4 P64 / AN4 P64 / AN4 P64 / AN4 NC 60 P65 / AN5 P65 / AN5 P65 / AN5 P65 / AN5 P65 / AN5 NC 61 P66 / AN6 P66 / AN6 P66 / AN6 P66 / AN6 P66 / AN6 NC 62 P67 / AN7 P67 / AN7 P67 / AN7 P67 / AN7 P67 / AN7 NC 63 AVCC AVCC AVCC AVCC AVCC VCC 64 P70 / TXD2 P70 / TXD2 P70 / TXD2 P70 / TXD2 P70 / TXD2 NC 65 P71 / RXD2 P71 / RXD2 P71 / RXD2 P71 / RXD2 P71 / RXD2 NC 66 P72 / SCK2 P72 / SCK2 A19 P72 / SCK2 / A19 P72 / SCK2 NC 67 P73 / TXD1 P73 / TXD1 P73 / TXD1 P73 / TXD1 P73 / TXD1 NC 68 P74 / RXD1 P74 / RXD1 P74 / RXD1 P74 / RXD1 P74 / RXD1 NC 50 Mode 4 Notes: 1. For the PROM mode, see section 16, "ROM." 2. Pins marked NC should be left unconnected. 16 NC Pin Functions: Table 1-5 gives a concise description of the function of each pin. Table 1-5 Pin Functions Pin No. DC-64S FP-64A Type Symbol DP-64S Power VCC 42, 11 34, 3 CP-68 44, 13 I/O Name and Function I Power: Connected to the power supply (+5 V). Connect both VCC pins to the system power supply (+5 V). The chip will not operate if either pin is left unconnected. VSS 51, 17, 43, 9, 53, 19, 64 56 2 I Ground: Connected to ground (0 V). Connect all VSS pins to the system power supply (0 V). The chip will not operate if either pin is left unconnected. Clock XTAL 2 58 4 O Crystal: Connected to a crystal oscillator. The crystal frequency should be double the desired o clock frequency. If an external clock is input at the EXTAL pin, input an inverted clock signal at the XTAL pin. EXTAL 1 57 3 I External Crystal: Connected to a crystal oscillator or external clock. The frequency of the external clock should be double the desired o clock frequency. See section 8.2, "Oscillator Circuit", for examples of connections to a crystal and external clock. o 50 42 52 O System Clock: Supplies the o clock to peripheral devices. 17 Table 1-5 Pin Functions (cont) Pin No. DC-64S FP-64A Type Symbol DP-64S System RES 15 7 CP-68 17 I/O Name and Function I/O Reset: A low input causes the H8/520 chip to reset. control If the reset output enable bit (RSTOE) is set to 1, when the watchdog timer overflows, a low signal is output for 132 system clock cycles. Address A19 - A0 60, 52, 66, 5-7 61 - 63 7-9 41 - 26 33 - 18 43 - 28 D7 - D0 25 - 18 17 - 10 WAIT 3 59 bus Data O Address Bus: Address output pins. 27 - 20 I/O Data Bus: 8-Bit bidirectional data bus. 5 I Wait: Requests the CPU to insert one bus Bus control or more TW states when accessing an off-chip address. AS 8 64 10 O Address Strobe: Goes low to indicate that there is a valid address on the address bus. RD 9 1 11 O Read: Goes low to indicate that the CPU is reading an external address. WR 10 2 12 O Write: Goes low to indicate that the CPU is writing to an external address. 18 Table 1-5 Pin Functions (cont) Pin No. DC-64S FP-64A Type Symbol DP-64S Interrupt NMI 16 8 CP-68 18 I/O Name and Function I NonMaskable Interrupt: Highest-priority interrupt request signal. The non-maskable interrupt control register (NMICR) determines whether the interrupt is requested on the rising or falling edge of the NMI input. IRQ0 4 60 6 IRQ1 5 61 7 IRQ2 6 62 8 IRQ3 7 63 9 IRQ4 38 30 40 IRQ5 39 31 41 IRQ6 40 32 42 IRQ7 41 33 43 Operating MD2 14 6 16 mode MD1 13 5 15 control MD0 12 4 14 I Interrupt Request 0 to 7: Maskable interrupt request signals I Mode: Input pins for setting the MCU operating mode according to the table below MD2 MD1 MD0 Mode Description 0 0 0 Mode 0 -- 0 0 1 Mode 1 Expanded minimum mode (ROM disabled) 0 1 0 Mode 2 Expanded minimum mode (ROM enabled) 0 1 1 Mode 3 Expanded maximum mode (ROM disabled) 1 0 0 Mode 4 Expanded maximum mode (ROM enabled) 1 0 1 Mode 5 -- 1 1 0 Mode 6 Hardware standby mode 1 1 1 Mode 7 Single-chip mode The inputs at these pins are latched in mode select bits 2 to 0 (MDS2 - MDS0) of the mode control register (MDCR) on the rising edge of the RES signal. 19 Table 1-5 Pin Functions (cont) Pin No. DC-64S FP-64A Type CP-68 Symbol DP-64S 16-bit free- FTOA1 49 41 51 running 50 42 52 FTOA2 I/O Name and Function O FRT Output Compare A (channels 1 and 2): Output pins for the output compare A function of timer (FRT) free-running timer channels 1 and 2. FTOB1 47 39 49 FTOB2 48 40 50 O FRT Output Compare B (channels 1 and 2): Output pins for the output compare B function of free-running timer channels 1 and 2. FTCI1 47 39 49 FTCI2 48 40 50 I FRT Counter Clock Input (channels 1 and 2): External clock input pins for the free-running counters (FRCs) of free-running timer channels 1 and 2. 8-bit FTI1 44 36 46 FTI2 45 37 47 TMO 46 38 48 I FRT Input Capture (channels 1 and 2): Input capture pins for free-running timer channels 1 and 2. O timer 8-bit Timer Output: Compare-match output pin for the 8-bit timer. TMCI 43 35 45 I 8-bit Timer Clock Input: External clock input pin for the 8-bit timer counter. TMRI 45 37 47 I 8-bit Timer Counter Reset Input: A high input at this pin resets the 8-bit timer counter. 20 Table 1-5 Pin Functions (cont) Pin No. DC-64S FP-64A Type Symbol CP-68 DP-64S Serial com- TXD1 61 53 67 munication TXD2 58 50 64 I/O Name and Function O Transmit Data (channels 1 and 2): Data output pins for serial communication interface channels interface signals 1 and 2. RXD1 62 54 68 RXD2 59 51 65 I Receive Data (channels 1 and 2): Data input pins for serial communication interface channels 1 and 2. SCK1 63 55 1 SCK2 60 52 66 A/D AN3 - AN0 56 - 53 48 - 45 58 - 55 converter AN7 - AN4* AVCC I/O Serial Clock (channels 1 and 2): Input/output pins for the serial interface clock. I Analog Input: Analog signal input pins. I Analog Reference Voltage: Reference 62 - 59 57 49 63 voltage pin for the A/D converter. AVSS 52 44 54 I Analog Ground: Ground pin for the A/D converter. ADTRG 5 61 7 I A/D External Trigger: External trigger input pin for the A/D converter. Parallel P17 - P10 10 - 3 I/O 2 - 1, 12 - 5 I/O 64 - 59 Port 1: An 8-bit input/output port. The direction of each bit is determined by the port 1 data direction register (P1DDR). P27 - P20 25 - 18 17 - 10 27 - 20 I/O Port 2: An 8-bit input/output port. The direction of each bit is determined by the port 2 data direction register (P2DDR). P37 - P30 33 - 26 25 - 18 35 - 28 I/O Port 3: An 8-bit input/output port. The direction of each bit is determined by the port 3 data direction register (P3DDR). These pins have built-in MOS input pull-ups. They can drive LED indicators. P47 - P40 41 - 34 33 - 26 43 - 36 I/O Port 4: An 8-bit input/output port. The direction of each bit is determined by the port 4 data direction register (P4DDR). These pins have built-in MOS input pull-ups. Note: * CP-68 only 21 Table 1-5 Pin Functions (cont) Pin No. DC-64S FP-64A Type Symbol DP-64S Parallel P57 - P50 50 - 43 42 - 35 CP-68 52 - 45 I/O Name and Function I/O Port 5: An 8-bit input/output port. The direction I/O (cont) of each bit is determined by the port 5 data direction register (P5DDR). These pins have Schmitt inputs. P63 - P60 56 - 53 48 - 45 P67 - P64* P75 - P70 58 - 55 I Port 6: A 4-bit (or 8-bit*) input port. I/O Port 7: A 6-bit input/output port. The direction 62 - 59 63 - 58 55 - 50 2 - 1, 68 - 64, of each bit is determined by the port 7 data direction register (P7DDR). Note: * CP-68 package only 22 Section 2 MCU Operating Modes and Address Space 2.1 Overview The H8/520 microcomputer unit (MCU) operates in five modes numbered 1, 2, 3, 4, and 7. The mode is selected by the inputs at the mode pins (MD2 to MD0) at the instant when the chip comes out of a reset. As indicated in table 2-1, the MCU mode determines the size of the address space, the usage of on-chip ROM, and the operating mode of the CPU. The MCU mode also affects the functions of I/O pins. Table 2-1 Operating Modes MD2 MD1 MD0 MCU Mode Address Space On-Chip RAM On-Chip ROM CPU Mode 0 0 0 Mode 0 -- -- -- -- 0 0 1 Mode 1 Expanded minimum Enabled* Disabled Minimum mode 0 1 0 Mode 2 Expanded minimum Enabled* Enabled Minimum mode 0 1 1 Mode 3 Expanded maximum Enabled* Disabled Maximum mode 1 0 0 Mode 4 Expanded maximum Enabled* Enabled Maximum mode 1 0 1 Mode 5 -- -- -- -- 1 1 0 Mode 6 Hardware standby mode -- -- -- 1 1 1 Mode 7 Single-chip only Enabled* Enabled Minimum mode Notation: 0: Low level 1: High level --: Cannot be used Note: * On-chip RAM can be disabled by RAME bit to 0 in RAM control register (RAMCR). Modes 1 to 4 are referred to as "expanded" because they permit access to off-chip memory and peripheral addresses. The expanded minimum modes (modes 1 and 2) support a maximum address space of 64 kbytes. The expanded maximum modes (modes 3 and 4) support a maximum address space of 1 Mbyte. Interrupt service is slightly slower in the expanded maximum modes than in the other modes because the CPU has to save its code page register. The H8/520 cannot be set to modes 0 and 5. The mode pins should never be set to these values. The hardware standby mode (mode 6) is a power-down mode, not an operating mode. See section 17.4, "Hardware Standby Mode" for details. 23 2.2 Mode Descriptions The five MCU modes are described below. For further information on the I/O pin functions in each mode, see section 9, "I/O ports." Mode 1 (Expanded Minimum Mode): Mode 1 supports a maximum 64-kbyte address space which does not include any on-chip ROM. Ports 1 to 4 are used for bus lines and bus control signals as follows: Control signals: Port 1 (partly) Data bus: Port 2 Address bus: Ports 3 and 4 Mode 2 (Expanded Minimum Mode): Mode 2 supports a maximum 64-kbyte address space of which the first 16 kbytes are in on-chip ROM. Ports 1 to 4 are used for bus lines and bus control signals as follows: Control signals: Port 1 (partly) Data bus: Port 2 Address bus: Ports 3 and 4 Note: In mode 2, port 4 is initially a general-purpose input port. Software must change the desired pins to output before using them for the address bus. See section 9.5, "Port 4" for details. The following instruction makes all pins of port 4 into output pins: MOV.B #H'FF, @H'FF85 Mode 3 (Expanded Maximum Mode): Mode 3 supports a maximum 1-Mbyte address space which does not include any on-chip ROM. Ports 1 to 4 and one pin in port 7 are used for bus lines and bus control signals as follows: Control signals: Port 1 (partly) Data bus: Port 2 Address bus: Ports 1 (partly), 3, 4, and 7 (partly) 24 Mode 4 (Expanded Maximum Mode): Mode 4 supports a maximum 1-Mbyte address space of which the first 16 kbytes are in on-chip ROM. Ports 1 to 4 and one pin in port 7 are used for bus lines and bus control signals as follows: Control signals: Port 1 (partly) Data bus: Port 2 Address bus: Ports 1 (partly), 3, 4, and 7 (partly) Note: In mode 4, port 4, pins 2 to 4 of port 1, and pin 2 of port 7 are initially used for general-purpose input. Software must change the desired pins to output before using them for the address bus. See section 9, "I/O Ports" for details. Mode 7 (Single-Chip Mode): In this mode all memory is on-chip, in 16 kbytes of ROM and 512 bytes of RAM. It is not possible to access off-chip addresses. The single-chip mode provides the maximum number of ports. All the pins associated with the address and data buses in the expanded modes are available as general-purpose input/output ports in the singlechip mode. 2.3 Address Space Map 2.3.1 Page Segmentation The H8/520's address space is segmented into 64-kbyte pages. In the single-chip mode and expanded minimum modes there is just one page: page 0. In the expanded maximum modes there can be up to 16 pages. Figure 2-1 shows the address space in each mode and indicates which parts are on- and offchip. 25 Address H'00000 Expanded minimum modes Mode 1 Mode 2 Expanded maximum modes Mode 3 Mode 4 Single-chip mode Mode 7 Page 0 H'0FFFF H'10000 Page 1 H'1FFFF H'F0000 Page 15 H'FFFFF On-chip On- or off-chip (selectable) Off-chip Figure 2-1 Address Space in Each Mode Fig 2-1 26 2.3.2 Page 0 Address Allocations The high and low address areas in page 0 are reserved for registers and vector tables. Vector Tables: The low address contains the exception vector table and DTC vector table. The CPU accesses the exception vector table to obtain the addresses of user-coded exception-handling routines. The DTC vector table contains pointers to tables of register information used by the on-chip chip data transfer controller. The size of these tables depends on the CPU operating mode. Details are given in section 4.1.2, "Exception Sources and Vector Table," section 5.2.3, "Interrupt Vector Table," and section 6.3.2, "DTC Vector Table." In modes 2, 4, and 7 the vector tables are located in on-chip ROM. In modes 1 and 3 the vector tables are in external memory. Register Field: The highest 128 addresses in page 0 (addresses H'FF80 to H'FFFF) belong to control, status, and data registers used by the I/O ports and on-chip supporting modules. Program code cannot be located at these addresses. The CPU accesses addresses in this register field like other addresses in the address space. By reading and writing at these addresses the CPU controls the on-chip supporting modules and communicates via the I/O ports. A complete map of the register field is given in appendix B. On-Chip RAM: One of the control registers in the register field is a RAM control register (RAMCR) containing a RAM enable bit (RAME) that enables or disables the 512-byte on-chip RAM. When this bit is set to 1 (its default value), addresses H'FD80 to H'FF7F are located on-chip. When this bit is cleared to 0, these addresses are located in external memory and the on-chip RAM is not used. See section 15, "RAM", for further information. The RAME bit is bit 7 at address H'FFF9. Coding Example: To enable on-chip RAM: To disable on-chip RAM: BSET.B #7, H'FFF9 BCLR.B #7, H'FFF9 Note: If on-chip RAM is disabled in the single-chip mode, access to addresses H'FD80 to H'FF7F causes an address error. 27 Figure 2-2 is a map of page 0 of the address space. H'0000 Exception vector table DTC vector table On-chip ROM (modes 2, 4, and 7) or external memory (modes 1 and 3) H'03FFF H'04000 External memory (modes 1 to 4) H'FD80 H'FF7F H'FF80 On-chip RAM (when enabled) On-chip register field H'FFFF Figure 2-2 Map of Page 0 Fig 2-2 28 2.4 Mode Control Register (MDCR) Another control register in the register field in page 0 is the mode control register (MDCR). The inputs at the mode pins are latched in this register on the rising edge of the signal. The mode control register can be read by the CPU, but not written. Table 2-2 lists the attributes of this register. Table 2-2 Mode Control Register Name Abbreviation Read/Write Address Mode control register MDCR Read only H'FFFA The bit configuration of this register is shown below. Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- MDS2 MDS1 MDS0 Initial value 1 1 0 0 0 --* --* --* Read/Write -- -- -- -- -- R R R Note: * Initialized according to MD2 to MD0. Bits 7 and 6--Reserved: These bits cannot be modified and are always read as 1. Bits 5 to 3--Reserved: These bits cannot be modified and are always read as 0. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the values of the mode pins (MD2 to MD0) latched on the rising edge of the RES signal. MDS2 corresponds to MD2, MDS1 to MD1, and MDS0 to MD0. These bits can be read but not written. Coding example: To test whether the MCU is operating in mode 1: CMP:G.B #H'C1, @H'FFFA The comparison is with H'C1 instead of H'01 because bits 7 and 6 are always read as 1. 29 Section 3 CPU 3.1 Overview The H8/520 chip has the H8/500 Family CPU: a high-speed central processing unit designed for realtime control of a wide range of medium-scale office and industrial equipment. It features eight 16-bit general registers, internal 16-bit data paths, and an optimized instruction set. Section 3 summarizes the CPU architecture and instruction set. 3.1.1 Features The main features of the H8/500 CPU are listed below. * General-register machine -- Eight 16-bit general registers -- Seven control registers (two 16-bit registers, five 8-bit registers) * High speed: maximum 10-MHz clock At 10 MHz a register-register add operation takes only 200 ns. * Address space managed in 64-kbyte pages, expandable to 1 Mbyte* Page registers make four pages available simultaneously: a code page, stack page, data page, and extended page. * Two CPU operating modes: -- Minimum mode: Maximum 64-kbyte address space -- Maximum mode: Maximum 1-Mbyte address space* * Highly orthogonal instruction set Addressing modes and data sizes can be specified independently within each instruction. * 1.5 addressing modes Register-register and register-memory operations are supported. * Optimized for efficient programming in C language In addition to the general registers and orthogonal instruction set, the CPU has special short formats for frequently-used instructions and addressing modes. Note: * The CPU Architecture supports up to 16 Mbytes of external memory, but the H8/520 chip has only enough address pins to address 1 Mbyte. 31 3.1.2 Address Space The address space size depends on the operating mode. The H8/520 MCU has five operating modes, which are selected by the input to the mode pins (MD2 to MD0) when the chip comes out of a reset. The CPU, however, has only two operating modes. The MCU operating mode determines the CPU operating mode, which in turn determines the maximum address space size as indicated in figure 3-1. Minimum mode Maximum address space: 64 kbytes Highest address: H'0FFFF Maximum mode Maximum address space: 1 Mbyte Highest address: H'FFFFF CPU operating mode Figure 3-1 CPU Operating Modes Fig 3-1 32 3.1.3 Register Configuration Figure 3-2 shows the register structure of the CPU. There are two groups of registers: the general registers (Rn) and control registers (CR). General registers (Rn) 15 0 R0 R1 R2 R3 R4 R5 R6 (FP) R7 (SP) FP: Frame Pointer SP: Stack Pointer Control registers (CR) 15 0 PC PC: Program Counter SR CCR 15 8 7 0 T - - - - I2 I1 I0 - - - - N Z V C CP SR: Status Register CCR: Condition Code Register CP: Code Page register DP DP: Data Page register EP EP: Extended Page register TP TP: sTack Page register BR BR: Base Register Figure 3-2 Registers in the CPU Fig 3-2 33 3.2 CPU Register Descriptions 3.2.1 General Registers All eight of the 16-bit general registers are functionally alike; there is no distinction between data registers and address registers. When these registers are accessed as data registers, either byte or word size can be selected. R6 and R7, in addition to functioning as general registers, have special assignments. R7 is the stack pointer, used implicitly in exception handling and subroutine calls. It can be designated by the name SP, which is synonymous with R7. As indicated in figure 3-3, it points to the top of the stack. It is also used implicitly by the LDM and STM instructions, which load and store multiple registers from and to the stack and pre-decrement or post-increment R7 accordingly. R6 functions as a frame pointer (FP). The LINK and UNLK instructions use R6 implicitly to reserve or release a stack frame. Unused area SP Stack area Figure 3-3 Stack Pointer Fig 3-3 34 3.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC), a 16-bit status register (SR), four 8bit page registers, and one 8-bit base register (BR). Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. Status Register (SR): This 16-bit register contains internal status information. The lower half of the status register is referred to as the condition code register (CCR): it can be accessed as a separate condition code byte. CCR Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T -- -- -- -- I2 I1 I0 -- -- -- -- N Z V C Bit 15--Trace (T): When this bit is set to 1, the CPU operates in trace mode and generates a trace exception after every instruction. See section 4.4, "Trace", for a description of the trace exceptionhandling sequence. When the value of this bit is 0, instructions are executed in normal continuous sequence. This bit is cleared to 0 at a reset. Bits 14 to 11--Reserved: These bits cannot be modified and are always read as 0. Bits 10 to 8--Interrupt Mask (I2, I1, I0): These bits indicate the interrupt request mask level (0 to 7). As shown in table 3-1, an interrupt request is not accepted unless it has a higher level than the value of the mask. A nonmaskable interrupt (NMI), which has level 8, is accepted at any mask level. After an interrupt is accepted, I2, I1, and I0 are changed to the level of the interrupt. Table 3-2 indicates the values of the I bits after the interrupt is accepted. A reset sets all three bits (I2, I1, and I0) to 1, masking all interrupts except NMI. 35 Table 3-1 Interrupt Mask Levels Mask Mask Bits Priority Level I2 I1 I0 Interrupts Accepted High 7 1 1 1 NMI 6 1 1 0 Level 7 and NMI 5 1 0 1 Levels 6 to 7 and NMI 4 1 0 0 Levels 5 to 7 and NMI 3 0 1 1 Levels 4 to 7 and NMI 2 0 1 0 Levels 3 to 7 and NMI 1 0 0 1 Levels 2 to 7 and NMI 0 0 0 0 Levels 1 to 7 and NMI Low Table 3-2 Interrupt Mask Bits after an Interrupt is Accepted Level of Interrupt Accepted I2 I1 I0 NMI (8) 1 1 1 7 1 1 1 6 1 1 0 5 1 0 1 4 1 0 0 3 0 1 1 2 0 1 0 1 0 0 1 36 Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 0. Bit 3--Negative (N): This bit indicates the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero (Z): This bit is set to 1 to indicate a zero result and cleared to 0 to indicate a nonzero result. Bit 1--Overflow (V): This bit is set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry (C): This bit is set to 1 when a carry or borrow occurs at the most significant bit, and is cleared to 0 (or left unchanged) at other times. The specific changes that occur in the condition code bits when each instruction is executed are listed in appendix A.1 "Instruction Tables." See the H8/500 Series Programming Manual for further details. Page Registers: The code page register (CP), data page register (DP), extended page register (EP), and stack page register (TP) are 8-bit registers that are used only in the maximum mode. No use of their contents is made in the minimum mode. In the maximum mode, the page registers combine with the program counter and general registers to generate 24-bit effective addresses as shown in figure 3-4, thereby expanding the program area, data area, and stack area. 37 Page register PC or general register 8 bits 16 bits CP PC R0 R1 R2 DP R3 @ aa : 16 R4 EP R5 R6 TP R7 24 bits (effective address) Figure 3-4 Combinations of Page Registers with Other Registers Code Page Register (CP): The code page register and the program counter combine to generate at Fig 3-4 24-bit program code address. The code page register contains the upper 8 bits of the address. In the maximum mode, the code page register is initialized at a reset to a value loaded from the vector table, and both the code page register and program counter are saved and restored in exception handling. Data Page Register (DP): The data page register combines with general registers R0 to R3 to generate a 24-bit effective address. The data page register contains the upper 8 bits of the address. It is used to calculate effective addresses in the register indirect addressing mode using R0 to R3, and in the 16-bit absolute addressing mode (@aa:16), but not in the short absolute addressing mode (@aa:8). The data page register is rewritten by the LDC instruction. 38 Extended Page Register (EP): The extended page register combines with general register R4 or R5 to generate a 24-bit operand address. The extended page register contains the upper 8 bits of the address. It is used to calculate effective addresses in the register indirect addressing mode using R4 or R5. The extended page can be used as an additional data page. Stack Page Register (TP): The stack page register combines with R6 (FP) or R7 (SP) to generate a 24-bit stack address. The stack page register contains the upper 8 bits of the address. It is used to calculate effective addresses in the register indirect addressing mode using R6 or R7, in exception handling, and in subroutine calls. Base Register (BR): This 8-bit register stores the base address used in the short absolute addressing mode (@aa:8). In this addressing mode a 16-bit effective address in page 0 is generated by using the contents of the base register as the upper 8 bits and an address given in the instruction code as the lower 8 bits. See figure 3-5. In the short absolute addressing mode the address is always located in page 0. 8 bits 8 bits BR @ aa : 8 16 bits (effective address) Figure 3-5 Short Absolute Addressing Mode and Base Register Fig 3-5 39 3.2.3 Initial Register Values When the CPU is reset, its internal registers are initialized as shown in table 3-3. Note that the stack pointer (R7) and base register (BR) are not initialized to fixed values. Also, of the page registers used in maximum mode, only the code page register (CP) is initialized; the other three page registers come out of the reset state with undetermined values. Accordingly, in the minimum mode the first instruction executed after a reset should initialize the stack pointer. The base register must also be initialized before the short absolute addressing mode (@aa:8) is used. In the maximum mode, the first instruction executed after a reset should initialize the stack page register (TP) and the next instruction should initialize the stack pointer. Later instructions should initialize the base register and the other page registers as necessary. 40 Table 3-3 Initial Values of Registers Initial Value Register Minimum Mode Maximum Mode 0 Undetermined Undetermined 0 Loaded from vector table Loaded from vector table 0 H'070* H'070* (*: undetermined) (*: undetermined) Undetermined Loaded from vector table Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined General registers 15 R7 - R0 Control registers 15 PC SR CCR 15 8 7 T - - - - I2I1I0 - - - - NZVC 7 0 CP 7 0 DP 7 0 EP 7 0 TP 7 0 BR 3.3 Data Formats The H8/500 can process 1-bit data, 4-bit BCD data, 8-bit (byte) data, 16-bit (word) data, and 32-bit (longword) data. * Bit manipulation instructions operate on 1-bit data. * Decimal arithmetic instructions operate on 4-bit BCD data. * Almost all instructions operate on byte and word data. * Multiply and divide instructions operate on longword data. 41 3.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in table 3-4. Bit data locations are specified by bit number. Bit 15 is the most significant bit. Bit 0 is the least significant bit. BCD and byte data are stored in the lower 8 bits of a general register. Word data use all 16 bits of a general register. Longword data use two general registers: the upper 16 bits are stored in Rn (n must be an even number); the lower 16 bits are stored in Rn+1. Operations performed on BCD data or byte data do not affect the upper 8 bits of the register. Table 3-4 General Register Data Formats Data Type Register No. 1-Bit Data Structure 15 Rn BCD 0 15 14 13 12 11 10 15 Rn Byte 8 7 Don't-care Rn 6 Upper digit 8 7 Don't-care Longword MSB 3 2 1 0 0 Lower digit 0 LSB 0 MSB LSB 31 Rn* 4 4 3 15 Rn 5 8 7 15 Word 9 16 MSB Upper 16 bits Rn + 1* Lower 16 bits 15 LSB 0 Note: * For longword data, n must be even (0, 2, 4, or 6). 42 3.3.2 Data Formats in Memory Table 3-5 indicates the data formats in memory. Instructions that access bit data in memory have byte or word operands. The instruction specifies a bit number to indicate a specific bit in the operand. Access to word data in memory must always begin at an even address. Access to word data starting at an odd address causes an address error. The upper 8 bits of word data are stored in address n (where n is an even number); the lower 8 bits are stored in address n+1. Table 3-5 Data Formats in Memory Data Type Data Format 1-bit (in byte operand data) 0 7 2 1 0 1-bit (in word Even address 15 14 13 12 11 10 9 8 operand data) Odd address 7 1 0 Byte Address n MSB Word Even address MSB Upper 8 bits Odd address Lower 8 bits Address n 7 6 6 5 5 4 4 3 3 2 LSB LSB When the stack is accessed in exception processing (to save or restore the program counter, code page register, or status register), word access is always performed, regardless of the actual data size. Similarly, when the stack is accessed by an instruction using the pre-decrement or post-increment register indirect addressing mode specifying R7 (@-R7 or @R7+), which is the stack pointer, word access is performed regardless of the operand size specified in the instruction. An address error will therefore occur if the stack pointer indicates an odd address. Programs should be coded so that the stack pointer always indicates an even address. Table 3-6 shows the data formats on the stack. 43 Table 3-5 Table 3-6 Data Formats on the Stack Data Type Data Format Byte data on stack Even address Odd address Don't-care MSB LSB Word data on stack Even address MSB Upper 8 bits Odd address Lower 8 bits LSB 3.4 Instructions 3.4.1 Basic Instruction Formats There are two basic CPU instruction formats: the general format and the special format. General Format: This format consists of an effective address (EA) field, an effective address extension field, and an operation code (OP) field. The effective address is placed before the operation Table 3-6 code because this results in faster execution of the instruction. Effective address field Effective address extension Operation code * Effective address field: One byte containing information used to calculate the effective address of an operand. * Effective address extension: Zero to two bytes containing a displacement value, immediate data, or an absolute address. The size of the effective address extension is specified in the effective address field. * Operation code: Defines the operation to be carried out on the operand located at the address calculated from the effective address information. Some instructions (DADD, DSUB) have an extended format in which the operand code is preceded by a one-byte prefix code. 44 * Example of prefix code in DADD instruction Effective address Prefix code Operation code 10100rrr 00000000 10100rrr Special Format: In this format the operation code comes first, followed by the effective address field and effective address extension. This format is used in branching instructions, system control instructions, and other instructions that can be executed faster if the operation is specified before the operand. Operation code Effective address field Effective address extension * Operation code: One or two bytes defining the operation to be performed by the instruction. * Effective address field and effective address extension: Zero to three bytes containing information used to calculate an effective address. 3.4.2 Addressing Modes The CPU supports 7 addressing modes: (1) register direct; (2) register indirect; (3) register indirect with displacement; (4) register indirect with pre-decrement or post-increment; (5) immediate; (6) absolute; and (7) PC-relative. Due to the highly orthogonal nature of the instruction set, most instructions having operands can use any applicable addressing mode from (1) through (6). The PC-relative mode (7) is used by branching instructions. In most instructions, the addressing mode is specified in the effective address field. The effectiveaddress extension, if present, contains a displacement, immediate data, or an absolute address. Table 3-7 indicates how the addressing mode is specified in the effective address field. 45 Table 3-7 Addressing Modes No. Addressing Mode Mnemonic 1 Register direct Rn EA Field EA Extension 1 0 1 0 Sz r r r *1 None *2 2 Register indirect @Rn 1 1 0 1 Sz r r r None 3 Register indirect @(d:8,Rn) 1 1 1 0 Sz r r r Displacement (1 byte) @(d:16,Rn) 1 1 1 1 Sz r r r Displacement (2 bytes) @-Rn 1 0 1 1 Sz r r r with displacement 4 Register indirect with pre-decrement Register indirect None @Rn+ 1 1 0 0 Sz r r r #xx:8 00000100 Immediate data (1 byte) #xx:16 00001100 Immediate data (2 bytes) @aa:8 0 0 0 0 Sz 1 0 1 1-Byte absolute address with post-increment 5 6 Immediate Absolute*3 (offset from BR) @aa:16 7 PC-relative disp 0 0 0 1 Sz 1 0 1 No EA field. 2-Byte absolute address 1- or 2-byte displacement Addressing mode is specified in the operation code. Notes: 1. Sz: Specifies the operand size. When Sz = 0: byte operand When Sz = 1: word operand 2. r r r: Register number field, specifying a general register number. 0 0 0--R0 0 0 1--R1 0 1 0--R2 0 1 1 --R3 1 0 0--R4 1 0 1--R5 1 1 0--R6 1 1 1--R7 3. The @aa:8 addressing mode is also referred to as the short absolute addressing mode. 46 3.4.3 Effective Address Calculation Table 3-8 explains how the effective address is calculated in each addressing mode. Table 3-8 Effective Address Calculation No. Addressing Mode Effective Address Calculation Effective Address 1 Register direct Rn -- Operand is contents of Rn 1010Sz 2 rrr Register indirect @Rn 1101Sz -- 23 15 DP rrr 0 Rn Or TP or EP 3 Register indirect with displacement @(d:8, Rn) 1110Sz 8 Bits 15 23 0 Rn DP rrr 15 15 + 0 0 Result Or TP or EP Displacement with sign extension 16 Bits 15 @(d:16, Rn) 1111Sz rrr 23 0 Rn 15 15 DP + 0 0 Result Or TP or EP Displacement 4 Register indirect with pre-decrement 15 23 0 Rn Rn DP*1 @-Rn 1011Sz - rrr 0Table 15 Result 3-8 No. 2 Or TP or EP *2 1 or 2 *3 Rn is decremented by -1 or -2 before instruction execution. *4 Register indirect with post-increment -- Table 3-8 No. 3 23 15 DP*1 0 Result @Rn + Or TP or EP *2 1100Sz rrr Rn is incremented by +1 or +2 after instruction execution. *3, 4 Notes: 1. The page register is ignored in minimum mode. 2. The page register used in addressing modes 2, 3, and 4 depends on the general register: Table 3-8 DP for R0, R1, R2, or R3; EP for R4 or R5; TP for R6 or R7. 4 (1) 3. Decrement by -1 for a byte operand, and by -2 for a wordNo. operand. 4. The pre-decrement or post-increment is always 2 when R7 is specified, even if the operand is byte size. 47 Table 3-8 Table 3-8 Effective Address Calculation (cont) No. Addressing Mode Effective Address Calculation 5 Absolute address @aa:8 -- Effective Address 23 15 H'00 0000Sz101 @aa:16 EA extension data -- 23 0001Sz101 6 Immediate #xx:8 0 BR 15 DP 0 EA extension data -- Operand is 1-byte EA extension data -- Operand is 2-byte EA extension data 00000100 #xx:16 00001100 7 PC-relative disp:8 No EA code Specified in OP code 8 Bits 15 23 0 PC 15 CP 15 0 Result Table 3-8 No. 5 (1) + 0 Displacement with sign extension disp:16 No EA code Specified in OP code 16 Bits 15 Table 3-8 No. 5 (2) 23 0 Rn PC 15 CP 15 0 Result + 0 Displacement Table 3-8 Note: The drawing below shows what happens when the @-SP and @ SP+ addressing modes No. 7 are (1) used to save and restore the stack pointer. SP Old SP-2 (upper byte) SP Old SP-2 (lower byte) Table 3-8 No. 7 (2) SP MOV.W SP, @-SP MOV.W @SP+, SP 48 3.5 Instruction Set 3.5.1 Overview The main features of the CPU instruction set are: * * * * A general-register architecture. Orthogonality. Addressing modes and data sizes can be specified independently in each instruction. Register-register and register-memory operations are supported. Affinity for high-level languages, particularly C, with short formats for frequently-used instructions and addressing modes. The CPU instruction set includes 61 (63)*1 types of instructions, listed by function in table 3-9. Table 3-9 Instruction Classification Function Instructions Types Data transfer MOV, LDM, STM, XCH, SWAP, (MOVTPE, MOVFPE)*1 5 (7)*1 Arithmetic operations ADD, SUB, ADDS, SUBS, ADDX, SUBX, DADD, DSUB, 17 MULXU, DIVXU, CMP, EXTS, EXTU, TST, NEG, CLR, TAS Logic operations AND, OR, XOR, NOT 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, 8 ROTXR Bit manipulation BSET, BCLR, BTST, BNOT 4 Branch Bcc*2, JMP, PJMP, BSR, JSR, PJSR, RTS, PRTD, 11 PRTS, RTD, SCB (/F, /NE, /EQ) System control TRAPA, TRAP/VS, RTE, SLEEP, LDC, STC, ANDC, 12 ORC, XORC, NOP, LINK, UNLK Total 61 (63)*1 Notes: 1. The H8/520 chip does not have an E clock output pin, so it does not support the MOVTPE and MOVFPE instructions. H8/520 software should not use these instructions. 2. Bcc is a conditional branch instruction in which cc represents a condition code. Tables 3-10 to 3-16 give a concise summary of the instructions in each functional category. The MOV, ADD, and CMP instructions have special short formats, which are listed in table 3-17. For detailed descriptions of the instructions, refer to the H8/500 Series Programming Manual. 49 The notation used in tables 3-10 to 3-17 is defined below. Operation Notation Rd General register (destination) Rs General register (source) Rn General register (EAd) Destination operand (EAs) Source operand CCR Condition code register N N (negative) bit of CCR Z Z (zero) bit of CCR V V (overflow) bit of CCR C C (carry) bit of CCR CR Control register PC Program counter CP Code page register SP Stack pointer FP Frame pointer #IMM Immediate data disp Displacement + Addition - Subtraction x Multiplication / Division AND logical OR logical Exclusive OR logical Move Exchange Not 50 3.5.2 Data Transfer Instructions Table 3-10 describes the seven data transfer instructions. Table 3-10 Data Transfer Instructions Size*2 Instruction Data transfer Function (EAs) (EAd), #IMM (EAd) MOV MOV:G B/W Moves data between two general registers, or between MOV:E B a general register and memory, or moves immediate data MOV:I W to a general register or memory. MOV:F B/W MOV:L B/W MOV:S B/W LDM W Stack Rn (register list) Pops data from the stack to one or more registers. STM W Rn (register list) stack Pushes data from one or more registers onto the stack. XCH W Rs Rd Exchanges data between two general registers. SWAP B Rd (upper byte) Rd (lower byte) Exchanges the upper and lower bytes in a general register. (MOVTPE)*1 -- Not supported by the H8/520 (MOVFPE)*1 -- Not supported by the H8/520 Notes: 1. The H8/520 does not have an E clock output pin, so it does not support the MOVTPE and MOVFPE instructions. H8/520 software should not use these instructions. If the MOVTPE and MOVFPE instructions are used, the H8/520 executes them in the number of cycles indicated in figures A and B. From 7 to 14 wait states (TW) are automatically inserted between the T2 state and T3 state to synchronize the bus cycle with an internal E clock obtained by dividing the system clock (o) by eight. Accordingly, the number of cycles taken by a MOVTPE or MOVFPE instruction varies. Note that no wait states (TW) are inserted by the wait state controller. 2. B: Byte, W: Word 51 T1 Last state T2 TE TE TE TE TE TE TE TE TE TE TE TE TE TE T3 o A 19 - A 0 AS (read access) RD WR (write access) D7 - D0 (read access) D7 - D0 (write access) Figure A Execution Cycle Length of MOVTPE and MOVFPE Instructions in Expanded Modes (Maximum NumberFig ofACycles) Last state T1 T2 TE TE TE TE TE TE TE T3 o A 19 - A 0 AS (read access) RD WR (write access) D7 - D0 (read access) D7 - D0 (write access) Figure B Execution Cycle Length of MOVTPE and MOVFPE Instructions in Expanded Modes (Minimum Number Figof B Cycles) 52 3.5.3 Arithmetic Instructions Table 3-11 describes the 17 arithmetic instructions. Table 3-11 Arithmetic Instructions Instruction Arithmetic operations Size Function Rd (EAs) Rd, (EAd) #IMM (EAd) ADD ADD:G B/W Performs addition or subtraction on data in a general register and ADD:Q B/W data in another general register or memory, or on data in a general SUB B/W register or memory and immediate data. ADDS B/W SUBS B/W ADDX B/W Rd (EAs) C Rd SUBX B/W Performs addition or subtraction with carry or borrow on data in a general register and data in another general register or memory, or on data in a general register and immediate data. DADD B (Rd)10 (Rs)10 C (Rd)10 DSUB B Performs decimal addition or subtraction on data in two general registers. MULXU B/W Rn x (EAs) Rd Performs 8-bit x 8-bit or 16-bit x 16-bit unsigned multiplication on data in a general register and data in another general register or memory, or on data in a general register and immediate data. DIVXU B/W Rd / (EAs) Rd Performs 16-bit / 8-bit or 32-bit / 16-bit unsigned division on data in a general register and data in another general register or memory, or on data in a general register and immediate data. Rn - (EAs), (EAd) - #IMM CMP CMP:G B/W Compares data in a general register with data in another general CMP:E B register or memory, or with immediate data, or compares data in CMP:I W memory with immediate data. 53 Table 3-11 Arithmetic Instructions (cont) Instruction Arithmetic EXTS Size Function B (<bit 7> of <Rd>) (<bits 15 to 8>of <Rd>) operations Converts byte data in a general register to word data by extending the sign bit. EXTU B 0 (<bits 15 to 8> of <Rd>) Converts byte data in a general register to word data by padding with zero bits. TST B/W (EAd) - 0 Compares general register or memory contents with 0. NEG B/W 0 - (EAd) (EAd) Obtains the two's complement of general register or memory contents. CLR B/W 0 (EAd) Clears general register or memory contents to 0. TAS B (EAd) - 0, (1)2 (<bit 7> of <EAd>) Tests general register or memory contents, then sets the most significant bit (bit 7) to 1. 3.5.4 Logic Operations Table 3-12 lists the four instructions that perform logic operations. Table 3-12 Logic Operation Instructions Instruction Logical AND Size Function B/W Rd (EAs) Rd operations Performs a logical AND operation on a general register and another general register, memory, or immediate data. OR B/W Rd (EAs) Rd Performs a logical OR operation on a general register and another general register, memory, or immediate data. XOR B/W Rd (EAs) Rd Performs a logical exclusive OR operation on a general register and another general register, memory, or immediate data. NOT B/W (EAd) (EAd) Obtains the one's complement of general register or memory contents. 54 3.5.5 Shift Operations Table 3-13 lists the eight shift instructions. Table 3-13 Shift Instructions Instruction Size Function Shift SHAL B/W (EAd) shift (EAd) operations SHAR B/W Performs an arithmetic shift operation on general register or memory contents. SHLL B/W (EAd) shift (EAd) SHLR B/W Performs a logical shift operation on general register or memory contents. ROTL B/W (EAd) rotate (EAd) ROTR B/W Rotates general register or memory contents. ROTXL B/W (EAd) rotate through carry (EAd) ROTXR B/W Rotates general register or memory contents through the C (carry) bit. 55 3.5.6 Bit Manipulations Table 3-14 describes the four bit-manipulation instructions Table 3-14 Bit-Manipulation Instructions Instruction Bit BSET Size Function B/W (<bit-No.> of <EAd> Z, 1 (<bit-No.> of <EAd>) manipulations Tests a specified bit in a general register or memory, then sets the bit to 1. The bit is specified by a bit number given in immediate data or a general register. BCLR B/W (<bit-No.> of <EAd>) Z, 0 (<bit-No.> of <EAd>) Tests a specified bit in a general register or memory, then clears the bit to 0. The bit is specified by a bit number given in immediate data or a general register. BNOT B/W (<bit-No.> of <EAd>) Z, (<bit-No.> of <EAd>) Tests a specified bit in a general register or memory, then inverts the bit. The bit is specified by a bit number given in immediate data or a general register. BTST B/W (<bit-No.> of <EAd>) Z Tests a specified bit in a general register or memory. The bit is specified by a bit number given in immediate data or a general register. 56 3.5.7 Branching Instructions Table 3-15 describes the 11 branching instructions Table 3-15 Branching Instructions Instruction Branch Bcc Size Function -- Branches if condition cc is true. Mnemonic Description Condition BRA (BT) Always (true) True BRN (BF) Never (false) False BHI High CZ=0 BLS Low or Same CZ=1 BCC (BHS) Carry Clear C=0 (High or Same) BCS (BLO) Carry Set (Low) C=1 BNE Not Equal Z=0 BEQ Equal Z=1 BVC Overflow Clear V=0 BVS Overflow Set V=1 BPL Plus N=0 BMI Minus N=1 BGE Greater or Equal NV=0 BLT Less Than NV=1 BGT Greater Than Z (N V) = 0 BLE Less or Equal Z (N V) = 1 JMP -- Branches unconditionally to a specified address in the same page. PJMP -- Branches unconditionally to a specified address in a specified page. BSR -- Branches to a subroutine at a specified address in the same page. JSR -- Branches to a subroutine at a specified address in the same page. PJSR -- Branches to a subroutine at a specified address in a specified page. RTS -- Returns from a subroutine in the same page. 57 Table 3-15 Branching Instructions (cont) Instruction Branch Size Function PRTS -- Returns from a subroutine in a different page. RTD -- Returns from a subroutine in the same page and adjusts the stack pointer. PRTD -- Returns from a subroutine in a different page and adjusts the stack pointer. SCB/F -- Controls a loop using a loop counter and/or a specified termination SCB/NE -- condition. SCB/EQ 58 3.5.8 System Control Instructions Table 3-16 describes the 12 system control instructions. Table 3-16 System Control Instructions Instruction Size Function System TRAPA -- Generates a trap exception with a specified vector number. control TRAP/VS -- Generates a trap exception if the V bit is set to 1 when the instruction is executed. RTE -- Returns from an exception-handling routine. LINK -- FP @-SP; SP FP; SP + #IMM SP Creates a stack frame. UNLK -- FP SP; @SP + FP Deallocates a stack frame created by the LINK instruction. SLEEP -- Causes a transition to the power-down state. LDC B/W* (EAs) CR Moves immediate data or general register or memory contents to a specified control register. STC B/W* CR (EAd) Moves control register data to a specified general register or memory location. ANDC B/W* CR #IMM CR Logically ANDs a control register with immediate data. ORC B/W* CR #IMM CR Logically ORs a control register with immediate data. XORC B/W* CR #IMM CR Logically exclusive-ORs a control register with immediate data. NOP -- PC + 1 PC No operation. Only increments the program counter. Note: * The size depends on the control register. 59 When using the LDC and STC instructions to stack and unstack the BR, CCR, TP, DP, and EP control registers in the H8/500 family, note the following point. H8/500 hardware does not permit byte access to the stack. If the LDC.B or STC.B assembler mnemonic is coded with the @R7+ (@SP+) or @-R7 (@-SP) addressing mode, the stack-pointer addressing mode takes precedence and hardware automatically performs word access. Specifically, the LDC.B and STC.B instructions are executed as follows. The following applies only to the stack-pointer addressing modes. In addressing modes that do not use the stack pointer, byte data access is performed as specified by the assembler mnemonic. 1. STC.B EP, @-SP When word data access is applied to EP, both EP and DP are accessed. This instruction stores EP at address SP (old) - 2, and DP at address SP (old) - 1. EP a Old SP - 2 DP b Old SP - 1 Old SP New SP a New SP + 1 b New SP + 2 Before execution 2. After execution LDC.B @SP+, EP When word data access is applied to EP, both EP and DP are accessed. This instruction loads EP from address SP (old), and DP from address SP (old) + 1, updating the DP value as well as the EP value. EP Old SP a Old SP + 1 b EP a New SP - 2 DP DP b New SP - 1 Old SP + 2 New SP Before execution After execution H066 '90 Tsuika-(1) 60 H066 '90 3. STC.B CCR, @-SP When word data access is applied to CCR, only CCR is accessed. This instruction stores identical CCR contents at both address SP (old) - 2 and address SP (old) - 1. CCR a New SP a Old SP - 1 New SP + 1 a Old SP New SP + 2 Old SP - 2 Before execution 4. After execution LDC.B @SP+, CCR When word data access is applied to CCR, only CCR is accessed. This instruction loads CCR from address SP (old) + 1. Note that the value in address SP (old) is not loaded. CCR Old SP a New SP - 2 Old SP + 1 b New SP - 1 Old SP + 2 CCR b New SP Before execution After execution BR, DP, and TP are accessed in the same way as CCR. When EP is specified, both EP and DP are H066is'90 accessed, but when CCR, BR, DP, or TP is specified, only the specified register accessed. Tsuika-(3) H066 '90 Tsuika-(4) 61 3.5.9 Short-Format Instructions The ADD, CMP, and MOV instructions have special short formats. Table 3-17 lists these short formats together with the equivalent general formats. The short formats are a byte shorter than the corresponding general formats, and most of them execute one state faster. Table 3-17 Short-Format Instructions and Equivalent General Formats Short-Format Execution Equivalent General- Execution Instruction Length States*2 Format Instruction Length States*2 ADD:Q #xx,Rd*1 2 2 ADD:G #xx:8,Rd 3 3 CMP:E #xx:8,Rd 2 2 CMP:G.B #xx:8,Rd 3 3 CMP:I #xx:16,Rd 3 3 CMP:G.W #xx:16,Rd 4 4 MOV:E #xx:8,Rd 2 2 MOV:G.B #xx:8,Rd 3 3 MOV:I #xx:16,Rd 3 3 MOV:G.W #xx:16,Rd 4 4 MOV:L @aa:8,Rd 2 5 MOV:G @aa:8,Rd 3 5 MOV:S Rs,@aa:8 2 5 MOV:G Rs,@aa:8 3 5 MOV:F @(d:8,R6),Rd 2 5 MOV:G @(d:8,R6),Rd 3 5 MOV:F Rs,@(d:8,R6) 2 5 MOV:G Rs,@(d:8,R6) 3 5 Notes: 1. The ADD: Q instruction accepts other destination operands in addition to a general register, but the immediate data value (#xx) is limited to 1 or 2. 2. Number of execution states for access to on-chip memory. 3.6 Operating Modes The CPU operates in one of two modes: the minimum mode or the maximum mode. These modes are selected by the mode pins (MD2 to MD0). 3.6.1 Minimum Mode The minimum mode supports a maximum address space of 64 kbytes. The page registers are ignored. Instructions that branch across page boundaries (PJMP, PJSR, PRTS, PRTD) are invalid. 62 3.6.2 Maximum Mode In the maximum mode the page registers are valid, expanding the maximum address space to 1 Mbyte. The address space is divided into 64-kbyte pages. The pages are separate; it is not possible to move continuously across a page boundary. It is possible to move from one page to another with branching instructions (PJMP, PJSR, PRTS, PRTD). The TRAPA instruction and instructions that branch to interrupt-handling routines can also jump across page boundaries. It is not necessary for a program to be contained in a single 64-kbyte page. When data access crosses a page boundary, the program must rewrite the page register before it can access the data in the next page. For further information on the operating modes, see section 2, "MCU Operating Modes and Address Space." 3.7 Basic Operational Timing 3.7.1 Overview The CPU operates on a system clock (o) which is created by dividing the crystal oscillator frequency (fosc) by two. One period of the system clock is referred to as a "state." The CPU accesses memory in a cycle consisting of 2 or 3 states. The CPU uses different methods to access on-chip memory, the onchip register field, and external devices. Access to On-Chip Memory (RAM, ROM): For maximum speed, access to on-chip memory (RAM, ROM) is performed in two states, using a 16-bit-wide data bus. Figure 3-6 shows the on-chip memory access cycle. Figure 3-7 indicates the pin states. The bus control signals output from the H8/520 chip go to the nonactive state during the access. Access to On-Chip Register Field (Addresses H'FF80 to H'FFFF): The access cycle consists of three states. The data bus is 8 bits wide. Figure 3-8 shows the on-chip supporting module access cycle. Figure 3-9 indicates the pin states. 63 Access to External Devices: The access cycle consists of three states. The data bus is 8 bits wide. Figure 3-10 (a) and (b) shows the external access cycle. Additional wait states (TW) can be inserted by the wait-state controller (WSC). 3.7.2 On-Chip Memory Access Cycle Bus cycle T1 state T2 state o Internal address bus Address Internal read signal Internal data bus (Read access) Read data Internal write signal Internal data bus (Write access) Write data Figure 3-6 On-Chip Memory Access Timing Fig 3-6 64 3.7.3 Pin States during On-Chip Memory Access T1 T2 o A19 - A 0 Address High AS, RD, WR High-impedance D7 - D0 Figure 3-7 Pin States during to On-Chip Memory FigAccess 3-7 3.7.4 Register Field Access Cycle (Addresses H'FF80 to H'FFFF) Memory cycle T1 state T2 state o Internal address bus Address Internal read signal Internal data bus (Read access) Read data Internal write signal Internal data bus (Write access) Write data Figure 3-8 Register Field Access Timing Fig 3-8 65 T3 state 3.7.5 Pin States during Register Field Access (Addresses H'FF80 to H'FFFF) T1 state T2 state T3 state o A19 - A 0 Address High AS, RD, WR High-impedance D7 - D 0 Figure 3-9 Pin States during Register Field Access 3.7.6 External Access Cycle Fig 3-9 Read cycle T1 state T2 state T3 state o A 19 - A 0 Address AS RD High WR D7 - D 0 Read data Figure 3-10 (a) External Access Cycle (Read Access) Fig 3-10(a) 66 Write cycle T1 state T2 state T3 state o A 19 - A 0 Address AS RD High WR D7 - D 0 Write data Figure 3-10 (b) External Access Cycle (Write Access) Fig 3-10(b) 3.8 CPU States 3.8.1 Overview The CPU has four states: the program execution state, exception-handling state, reset state, and powerdown state. The power-down state is further divided into the sleep mode, software standby mode, and hardware standby mode. Figure 3-11 summarizes these sates, and figure 3-12 shows a map of the state transitions. 67 State Program execution state The CPU executes program instructions in sequence. Exception-handling state A transient state in which the CPU executes a hardware sequence (saving the program counter and status register, fetching a vector from the vector table, etc.) triggered by a reset, interrupt, or other exception. Reset state The state in which the CPU and all on-chip supporting modules have been initialized and are stopped. Power-down state Sleep mode A state in which some or all of the clock signals are stopped to conserve power. Software standby mode Hardware standby mode Note: H8/520 does not support the bus-release function. There is no bus-released state. Figure 3-11 Operating States 68 Program execution state SLEEP instruction SLEEP instruction with standby flag set End of exception handling Request for exception handling Sleep mode Interrupt request NMI Software standby mode RES = 1 Exception-handling state Reset state * 1 MD2 to MD 0 6, RES = 0 Hardware standby mode*2 Notes: 1. From any state except the hardware standby mode, a transition to the reset state occurs whenever RES goes low or the watchdog timer requests a reset. 2. A transition to the hardware standby mode from any state occurs when the mode pins (MD2 Fig 3-12 to MD0) are set to 6. Figure 3-12 State Transitions 3.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 69 3.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to an interrupt, trap instruction, address error, or other exception. In this state the CPU carries out a hardware-controlled sequence that prepares it to execute a user-coded exception-handling routine. In the hardware exception-handling sequence the CPU does the following: 1. Saves the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) to the stack. 2. Clears the T bit in the status register to 0. 3. Fetches the start address of the exception-handling routine from the exception vector table. 4. Branches to that address, returning to the program execution state. See section 4, "Exception Handling", for further information on the exception-handling state. 3.8.4 Reset State In the reset state, the CPU and all on-chip supporting modules are initialized and placed in the stopped state. The CPU enters the reset state whenever the RES pin goes low, unless the CPU is currently in the hardware standby mode. It remains in the reset state until the RES pin goes high. See section 4.2, "Reset", for further information on the reset state. 3.8.5 Power-Down State The power-down state comprises three modes: the sleep mode, software standby mode, and hardware standby mode. See section 17, "Power-Down State", for further information. 70 Section 4 Exception Handling 4.1 Overview 4.1.1 Types of Exception Handling and Their Priority As indicated in table 4-1 (a) and (b), exception handling can be initiated by a reset, address error, trace, interrupt, or instruction. An instruction initiates exception handling if the instruction is an invalid instruction, a trap instruction, or a DIVXU instruction with zero divisor. Exception handling begins with a hardware exception-handling sequence which prepares for the execution of a user-coded software exception-handling routine. There is a priority order among the different types of exceptions, as shown in table 4-1 (a). If two or more exceptions occur simultaneously, they are handled in their order of priority. An instruction exception cannot occur simultaneously with other types of exceptions. Table 4-1 (a) Exceptions and Their Priority Priority Exception Type Source Detection Timing Start of ExceptionHandling Sequence High Reset External, internal RES Low-to-High transition Immediately Address error Internal Instruction fetch or data read/write bus cycle End of instruction execution Trace Internal End of instruction execution, if T = 1 in status register End of instruction execution Interrupt External, internal End of instruction execution or end of exception-handling sequence End of instruction execution Low Table 4-1 (b) Instruction Exceptions Exception Type Start of Exception-Handling Sequence Invalid instruction Attempted execution of instruction with undefined code Trap instruction Started by execution of trap instruction Zero divide Attempted execution of DIVXU instruction with zero divisor 71 4.1.2 Hardware Exception-Handling Sequence The hardware exception-handling sequence varies depending on the type of exception. When exception handling is initiated by an exception other than a reset, the CPU: 1. Saves the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) to the stack. 2. Clears the T bit in the status register to 0. 3. Fetches the start address of the exception-handling routine from the exception vector table. 4. Branches to that address. For an interrupt, the CPU also alters the interrupt mask level in bits I2 to I0 of the status register. For a reset, step 1 is omitted. See section 4.2, "Reset", for the full reset sequence. 4.1.3 Exception Sources and Vector Table The sources that initiate exception handling can be classified as shown in figure 4-1. The starting addresses of the exception-handling routines for each source are contained in an exception vector table located in the low addresses of page 0. The vector addresses are listed in table 4-2. Note that there are different addresses for the minimum and maximum modes. 72 Reset NMI IRQ 0 .. . External interrupt IRQ 7 Interrupt Internal interrupt Internal interrupts requested by on-chip modules: 18 sources Exception Address error Trace Instruction Invalid instruction Zero divide TRAPA instruction TRAP/VS instruction Figure 4-1 Sources Causing Exception Handling Fig 4-1 73 Table 4-2 Exception Vector Table Vector Address Type of Exception Minimum Mode Maximum Mode Reset (initialize PC) H'0000 to H'0001 H'0000 to H'0003 H'0002 to H'0003 H'0004 to H'0007 Invalid instruction H'0004 to H'0005 H'0008 to H'000B DIVXU instruction (zero divide) H'0006 to H'0007 H'000C to H'000F TRAP/VS instruction H'0008 to H'0009 H'0010 to H'0013 H'000A to H'000B H'0014 to H'0017 to to H'000E to H'000F H'001C to H'001F Address error H'0010 to H'0011 H'0020 to H'0023 Trace H'0012 to H'0013 H'0024 to H'0027 H'0014 to H'0015 H'0028 to H'002B H'0016 to H'0017 H'002C to H'002F H'0018 to H'0019 H'0030 to H'0033 to to H'001E to H'001F H'003C to H'003F H'0020 to H'0021 H'0040 to H'0043 to to H'003E to H'003F H'007C to H'007F H'0040 to H'0041 H'0080 to H'0083 to to H'004E to H'004F H'009C to H'009F H'0050 to H'0051 H'00AO to H'00A3 to to -- (Reserved for system) -- (Reserved for system) -- (Reserved for system) Nonmaskable external interrupt (NMI) -- (Reserved for system) TRAPA instruction (16 vectors) External interrupts IRQ0 to IRQ7 Internal interrupts H'007E to H'007F Notes: 1. The exception vector table is located at the beginning of page 0. 2. For details of the internal interrupt vectors, see table 5-2. 74 H'00FC to H'00FF 4.2 Reset 4.2.1 Overview A reset has the highest exception-handling priority. A reset can be generated by a low input at the RES pin or by a watchdog timer (WDT) overflow. When the RES pin goes low, all current processing halts and the H8/520 chip enters the reset state. The internal status of the CPU and the contents of the registers of the on-chip supporting modules are initialized. When the RES pin returns from low to high, the hardware reset sequence described in the next section begins. To ensure that the H8/520 chip is reset correctly, the RES pin should be held low for at least 20 ms at power-up. To reset the H8/520 during operation, the RES pin should be held low for at least six system clock (o) cycles. When the RSTOE bit (see below) is set to 1, the RES input must be held low for at least 520 system clock (o) cycles to reset the H8/520 chip. When the watchdog timer operates in watchdog mode, if the watchdog timer counter (TCNT) overflows due to a program crash, for example, the watchdog timer generates an internal reset signal that resets the H8/520 chip. If in addition the reset output enable (RSTOE) bit in the reset control/status register (RSTCSR) is set to 1, a low output signal is generated at the RES pin for 132 system clock (o) cycles. This signal can be used to reset devices controlled by the H8/520. See section 12, "Watchdog Timer", for further information on the reset generated by the watchdog timer. See appendix E, "Pin Status in the Reset State", for the status of pins when a reset occurs. 4.2.2 Reset Sequence When the RES pin returns to the high state after being held low for the necessary time, the hardware reset exception-handling sequence begins, during which: 1. The value at the mode pins (MD2 to MD0) is latched in bits MDS2 to MDS0 of the mode control register (MDCR). 2. In the status register (SR), the T bit is cleared to disable the trace mode, and the interrupt mask level (bits I2 to I0) is set to 7. A reset disables all interrupts. 3. The CPU loads the reset start address from the vector table into the program counter and begins executing the program at that address. 75 The contents of the vector table differs between minimum mode and maximum mode as indicated in figure 4-2. This affects step 3 as described below. Minimum Mode: One word is copied from addresses H'0000 and H'0001 in the vector table to the program counter. Program execution then begins from the address in the program counter (PC). Maximum Mode: Two words are read from addresses H'0000 to H'0003 in the vector table. The byte in address H'0000 is ignored. The byte in address H'0001 is copied to the code page register (CP). The contents of addresses H'0002 and H'0003 are copied to the program counter. Program execution starts from the address indicated by the code page register and program counter. H'0000 PC (Upper) H'0000 Don't-care H'0001 PC (Lower) H'0001 CP H'0002 PC (Upper) H'0003 PC (Lower) (1) Minimum mode (2) Maximum mode Figure 4-2 Reset Vector 4-2 Figure 4-3 shows the timing of the reset sequence Fig in minimum mode. Figure 4-4 shows the timing of the reset sequence in maximum mode. 4.2.3 Stack Pointer Initialization The hardware reset sequence does not initialize the stack pointer, so this must be done by software. If an interrupt were to be accepted after a reset and before the stack pointer (SP) is initialized, the program counter and status register would not be saved correctly, causing a program crash. This danger can be avoided by coding the reset routine as explained next. When the chip comes out of the reset state all interrupts, including NMI, are disabled, so the instruction at the reset start address is always executed. In the minimum mode, this instruction should initialize the stack pointer (SP). In the maximum mode, this instruction should be an LDC instruction initializing the stack page register (TP), and the next instruction should initialize the stack pointer. Execution of the LDC instruction disables interrupts again, ensuring that the stack pointer initializing instruction is executed. 76 o 77 Figure 4-3 Reset Sequence (Minimum Mode, On-Chip Memory) RES Internal address bus Internal data bus (16 bits) Vector address (1) (2) Vector (3) (4) Internal read signal Internal write signal Minimum 6 states (See note 2) Internal processing cycle Reset vector (1) Instruction prefetch address (3) Program start address (2) Operation code (4) First instruction of program Prefetch first instruction of program Instruction execution cycle Notes: 1. This timing chart applies to the minimum mode when the program and stack areas are both in on-chip memory and the program starts at an even address. 2. Minimum 520 states when the RSTOE bit is set to 1. Fig 4-3 78 Figure 4-4 Reset Sequence (Maximum Mode, External Memory) o RES A 23 to A 0 Vector address D15 to D0 don't care Vector address + 1 Vector CP Vector address + 2 Vector address + 3 (1) Vector PC H Vector PC L (2) Read signal RD Write signal WR Internal processing cycle Reset vector Prefetch first instruction of program (1) Program start address (2) First instruction of program Note: This diagram applies to maximum mode when the program area and vector table are both in external memory. After a reset, the wait-state controller inserts three wait states in each bus cycle. Instruction execution cycle 4.3 Address Error There are three causes of address errors: * Instruction prefetch from illegal address * Word data access at odd address * Off-chip access in single-chip mode An address error initiates the address error exception-handling sequence. This sequence clears the T bit of the status register to 0 to disable the trace mode, but does not affect the interrupt mask level in bits I2 to I0. 4.3.1 Instruction Prefetch from Illegal Address An attempt to prefetch an instruction from the register field in memory addresses H'FF80 to H'FFFF causes an address error regardless of the MCU operating mode. Handling of this address error begins when the prefetch cycle that caused the error has been completed and execution of the current instruction has also been completed. The program counter value pushed on the stack is the address of the instruction immediately following the last instruction executed. See section 4.9, "Stack Status after Completion of Exception Handling", for a diagram of the stack. Program code should not be located in addresses H'FF7D to H'FF7F. If the CPU executes an instruction in these addresses, it will attempt to prefetch the next instruction from the register field, causing an address error. 4.3.2 Word Data Access at Odd Address If an attempt is made to access word data starting at an odd address, an address error occurs regardless of the MCU operating mode. The program counter value pushed on the stack in the handling of this error is the address of the next instruction after the instruction that attempted the illegal word access. 4.3.3 Off-Chip Address Access in Single-Chip Mode In the single-chip mode there is no external memory, so in addition to the address errors described above, the following two types of address errors can occur. 79 Access to Addresses H'4000 to H'FD7F: These addresses exist neither in on-chip ROM or RAM nor in the on-chip register field, so an address error occurs if they are accessed for any purpose: for instruction prefetch, byte data access, or word data access. Program code should not be located in the last three bytes of on-chip ROM (addresses H'3FFD to H'3FFF) in single-chip mode. If an instruction is located in these three bytes, the CPU will attempt to fetch the next instruction from addresses H'4000 to H'4002, causing an address error. Access to Disabled RAM Area: The on-chip RAM area (H'FD80 to H'FF7F) can be disabled by clearing the RAME bit in the RAM control register (RAMCR). If any type of RAM access is attempted in this state in the single-chip mode, an address error occurs. 4.4 Trace When the T bit of the status register is set to 1, the CPU operates in trace mode. A trace exception occurs at the completion of each instruction. The trace mode can be used to monitor program execution for debugging by a debugger. In the trace exception sequence the T bit of the status register is cleared to 0 to disable the trace mode while the trace routine is executing. The interrupt mask level in bits I2 to I0 is not changed. Interrupts are accepted as usual during the trace routine. In the status-register data saved on the stack, the T bit is set to 1. When the trace routine returns with the RTE instruction, the status register is popped from the stack and the trace mode resumes. If an address error occurs during execution of the first instruction after the return from the trace routine, since the address error has higher priority, the address error exception-handling sequence is initiated, clearing the T bit in the status register to 0 and making it impossible to trace this instruction. 4.5 Interrupts Interrupts can be requested from nine external sources (NMI and IRQ0 to IRQ7) and seven on-chip supporting modules: the 16-bit free-running timers (FRT1 and FRT2), the 8-bit timer, the serial communication interfaces (SCI1 and SCI2), the A/D converter, and the watchdog timer (WDT). The on-chip interrupt sources can request a total of eighteen different types of interrupts, each having its own interrupt vector. Figure 4-5 lists the interrupt sources and the number of different interrupts from each source. 80 Each interrupt source has a priority. NMI interrupts have the highest priority, and are normally accepted unconditionally. The priorities of the other interrupt sources are set in interrupt priority registers A to D (IPRA to IPRD) in the register field at the high end of page 0 and can be changed by software. Priority levels range from 0 (low) to 7 (high), with NMI considered to be on level 8. IRQ1 to IRQ7 always have the same priority. The priority of IRQ0 can be set independently. The on-chip interrupt controller decides whether an interrupt can be accepted by comparing its priority with the interrupt mask level, and determines the order in which to accept competing interrupt requests. Interrupts that are not accepted immediately remain pending until they can be accepted later. When it accepts an interrupt, the interrupt controller also decides whether to have the interrupt handled by the CPU or the on-chip data transfer controller (DTC). This decision is controlled by bits set in data transfer enable registers A to D (DTEA to DTED) in the register field. The DTC is started if the corresponding DTE bit is set to 1; otherwise a CPU interrupt is generated. DTC interrupts provide an efficient way to send and receive blocks of data via the serial communication interface, or to transfer data between memory and I/O without detailed CPU programming. The CPU halts while the DTC is executing. DTC interrupts are described in section 6, "Data Transfer Controller". The hardware exception-handling sequence for a CPU interrupt clears the T bit in the status register to 0 and sets the interrupt mask level in bits I2 to I0 to the level of the interrupt it has accepted. This prevents the interrupt-handling routine from being interrupted except by a higher-level interrupt. The previous interrupt mask level is restored on the return from the interrupt-handling routine. For further information on interrupts, see section 5, "Interrupt Controller". 81 NMI (1) IRQ 0 External interrupts to (8) IRQ 7 Interrupt sources 16-Bit FRT1 (4) 16-Bit FRT2 (4) 8-Bit timer (3) SCI1 (3) SCI2 (3) A/D converter (1) WDT * Internal interrupts NMI: NonMaskable Interrupt IRQ: Interrupt Request FRT: Free-Running Timer SCI: Serial Communication Interface WDT: WatchDog Timer Fig 4-5 Note: * Interrupts from the watchdog timer in the interval timer mode are handled as IRQ0. Figure 4-5 Interrupt Sources (and Number of Interrupt Types) 4.6 Invalid Instruction An invalid instruction exception occurs if an attempt is made to execute an instruction with an undefined operation code or illegal addressing mode specification. The program counter value pushed on the stack is the value of the program counter when the invalid instruction code was detected. In the invalid instruction exception-handling sequence the T bit of the status register is cleared to 0, but the interrupt mask level (I2 to I0) is not affected. If a normal interrupt is requested while a trap or zerodivide instruction is being executed, after the trap or zero-divide exception-handling sequence, the normal interrupt exception-handling sequence is carried out. 82 4.7 Trap Instructions and Zero Divide A trap exception occurs when the TRAPA or TRAP/VS instruction is executed. A zero divide exception occurs if an attempt is made to execute a DIVXU instruction with a zero divisor. In the exception-handling sequences for these exceptions the T bit of the status register is cleared to 0, but the interrupt mask level (I2 to I0) is not affected. TRAPA Instruction: The TRAPA instruction always causes a trap exception. The TRAPA instruction includes a vector number from 0 to 15, allowing the user to provide up to sixteen different traphandling routines. TRAP/VS Instruction: When the TRAP/VS instruction is executed, a trap exception occurs if the overflow (V) bit in the condition code register is set to 1. If the V bit is cleared to 0, no exception occurs and the next instruction is executed. DIVXU Instruction with Zero Divisor: An exception occurs if an attempt is made to divide by zero in a DIVXU instruction. 4.8 Cases in Which Exception Handling is Deferred In the case described next, the address error exception, trace exception, external interrupt (NMI and IRQ0 to IRQ7) requests, and internal interrupt requests (18 types) are not accepted immediately but are deferred until after the next instruction has been executed. 83 4.8.1 Instructions that Disable Interrupts Interrupts are disabled immediately after the execution of five instructions: XORC, ORC, ANDC, LDC, and RTE. Suppose that an internal interrupt is requested and the interrupt controller, after checking the interrupt priority and interrupt mask level, notifies the CPU of the interrupt, but the CPU is currently executing one of the five instructions listed above. After executing this instruction the CPU always proceeds to the next instruction. (And if the next instruction is one of these five, the CPU also proceeds to the next instruction after that.) The exception-handling sequence starts after the next instruction that is not one of these five has been executed. The following is an example: . . . . . LDC.B #H'00,TP MOV.W #H'FF80,SP Program flow Interrupt controller notifies CPU of interrupt request CPU executes next instruction before starting exception handling MOV.B #H'00,@WCR . . . To exception-handling sequence Note: When the LDC instruction alters the I bits in the status register (SR), the new I-bit values do not take effect until three states after the LDC instruction. If a program running in on-chip memory uses the LDC instruction to enable interrupts by modifying the I bits and the next instruction is a two-state instruction (NOP for example), interrupts will not be accepted after this next instruction; they will not be accepted until another instruction has been executed after that. The same applies to the ANDC, ORC, and XORC instructions. 4.8.1 Figure 4.8.2 Disabling of Exceptions Immediately after a Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the program counter and status register will not be saved correctly, leading to a program crash. To prevent this, when the chip comes out of the reset state all interrupts, including NMI, are disabled, so the first instruction of the reset routine is always executed. As noted earlier, in the minimum mode, this instruction should initialize the stack pointer (SP). In the maximum mode, the first instruction should be an LDC instruction that initializes the stack page register (TP); the next instruction should initialize the stack pointer. 84 4.8.3 Disabling of Interrupts after a Data Transfer Cycle If an interrupt starts the data transfer controller and another interrupt is requested during the data transfer cycle, when the data transfer cycle ends, the CPU always executes the next instruction before handling the second interrupt. Even if a nonmaskable interrupt (NMI) occurs during a data transfer cycle, it is not accepted until the next instruction has been executed. An example of this is shown below. (Example) . . . . ADD.W R2,R0 Program flow DTC interrupt request Data transfer cycle NMI interrupt request MOV.W R0,@H'FF00 After data transfer cycle, CPU executes next instruction before branching to exception handling MOV.W @H'FF02,R0 . . . To NMI exception-handling sequence 4.8.3 Figure 85 4.9 Stack Status after Completion of Exception Handling The status of the stack after an exception-handling sequence is described below. Table 4-3 shows the stack after completion of the exception-handling sequence for various types of exceptions in the minimum and maximum modes. Table 4-3 Stack after Exception Handling Sequence Exception Trace Minimum Mode SP Maximum Mode TP:SP SR (upper byte) SR (upper byte) SR (lower byte) SR (lower byte) Next instruction address (upper byte) Don't-care Next instruction address (lower byte) Next instruction page (8 bits) Interrupt Trap Next instruction address (upper byte) Next instruction address (lower byte) Zero divide (DIVXU) Note: The RTE instruction returns to the next instruction after the instruction being executed when the exception occurred. Table 4-3 (1) 86 Table 4-3 Stack after Exception Handling Sequence (cont) Exception Minimum Mode SP Invalid instruction Maximum Mode TP:SP SR (upper byte) SR (upper byte) SR (lower byte) SR (lower byte) PC when error occurred (upper byte) Don't-care PC when error occurred (lower byte) CP when error occurred (8 bits) PC when error occurred (upper byte) PC when error occurred (lower byte) Note: The program counter value pushed on the stack is not necessarily the address of the first byte of the invalid instruction. Exception Minimum Mode Maximum Mode Table 4-3 (2) upper SP Address error TP:SP SR (upper byte) SR (upper byte) SR (lower byte) SR (lower byte) PC when error occurred (upper byte) Don't-care PC when error occurred (lower byte) CP when error occurred (8 bits) PC when error occurred (upper byte) PC when error occurred (lower byte) Note: The program counter value pushed on the stack is the address of the next instruction after the last instruction successfully executed. Table 4-3 (2) lower 87 4.9.1 PC Value Pushed on Stack for Trace, Interrupts, Trap Instructions, and Zero Divide Exceptions The program counter value pushed on the stack for a trace, interrupt, trap, or zero divide exception is the address of the next instruction at the time when the interrupt or exception was accepted. The RTE instruction accordingly returns to the next instruction after the instruction executed before the exception-handling sequence. 4.9.2 PC Value Pushed on Stack for Address Error and Invalid Instruction Exceptions The program counter value pushed on the stack for an address error or invalid instruction exception differs depending on the conditions when the exception occurred. 4.10 Notes on Use of the Stack If the stack pointer is set to an odd address, an address error will occur when the stack is accessed during interrupt handling or for a subroutine call. The stack pointer should always point to an even address. To keep the stack pointer pointing to an even address, a program should use word data size when saving or restoring registers to and from the stack. In the @-SP or @SP+ addressing mode, the CPU performs word access even if the instruction specifies byte size. (This is not true in the @-Rn and @Rn+ addressing modes when Rn is a register from R0 to R6.) 88 Section 5 Interrupt Controller 5.1 Overview The interrupt controller decides which interrupts to accept, and how to deal with multiple interrupts and other exceptions. It also decides whether an interrupt should be served by the CPU or by the data transfer controller (DTC). This section explains the features of the interrupt controller, describes its internal structure and control registers, and details the handling of interrupts. For detailed information on the data transfer controller, see section 6, "Data Transfer Controller". 5.1.1 Features The main features of the interrupt controller are as follows: * Interrupt priorities are user-programmable. User programs can set priority levels from 7 (high) to 0 (low) in four interrupt priority (IPR) registers for IRQ0, IRQ1 to IRQ7, and each of the on-chip supporting modules--for every interrupt, that is, except the nonmaskable interrupt (NMI). NMI has the highest priority level (8) and is normally always accepted. An interrupt with priority level 0 is always masked. * Multiple interrupts on the same level are served in a default priority order. Lower-priority interrupts remain pending until higher-priority interrupts have been handled. * For most interrupts, software can select whether to have the interrupt served by the CPU or the onchip data transfer controller (DTC). User programs can make this selection by setting and clearing bits in four data transfer enable (DTE) registers. The data transfer controller can be started by any interrupts except NMI, IRQ4 to IRQ7, the error interrupt (ERI) from the on-chip serial communication interface, and the overflow interrupts (FOVI and OVI) from the on-chip timers. * Software can select the NMI edge and can enable or disable IRQ0 to IRQ7. The NMI control register (NMICR) determines whether a nonmaskable interrupt is triggered by the rising or falling edge of the NMI input signal. The IRQ control register (IRQCR) enables or disables IRQ0 to IRQ7. 89 5.1.2 Block Diagram Figure 5-1 shows the block configuration of the interrupt controller. Interrupt controller NMI NMI request NMICR Interrupt request signals from modules FRT2 8-bit timer SCI1 SCI2 Comparator FRT1 IPRA - IPRD IRQCR IRQ 1 - IRQ 7 Priority decision logic IRQ0 Interrupt request DTEA ~ DTED A/D converter DTC request I2 (Legend) FRT: SCI: SR: IPR: DTE: NMICR: IRQCR: I1 I0 SR (CPU) Free-Running Timer Fig 5-1 Serial Communication Interface Status Register Interrupt Priority Register Data Transfer Enable Register Nonmaskable Interrupt Control Register Interrupt Request Control Register Figure 5-1 Interrupt Controller Block Diagram 90 5.1.3 Register Configuration Table 5-1 lists the attributes of the registers used by the interrupt controller. Table 5-1 Interrupt Controller Registers Name Abbreviation Read/Write Initial Value Address Interrupt A IPRA R/W H'00 H'FFF0 priority register B IPRB R/W H'00 H'FFF1 C IPRC R/W H'00 H'FFF2 D IPRD R/W H'00 H'FFF3 Data transfer A DTEA R/W H'00 F'FFF4 enable register B DTEB R/W H'00 H'FFF5 C DTEC R/W H'00 H'FFF6 D DTED R/W H'00 H'FFF7 NMI control register NMICR R/W H'FE H'FFFC IRQ control register IRQCR R/W H'00 H'FFFD See section 6.2.5, "Data Transfer Enable Registers A to D", for detailed information about DTEA to DTED. 5.2 Interrupt Types There are 27 distinct types of interrupts: 9 external interrupts originating off-chip and 18 internal interrupts originating in the on-chip supporting modules. 5.2.1 External Interrupts The nine external interrupts are NMI and IRQ0 to IRQ7. NMI (Non Maskable Interrupt): This interrupt has the highest priority level (8) and cannot be masked. An NMI is generated by input to the NMI pin. The input at the NMI pin is edge-sensed. A user program can select whether to have the interrupt occur on the rising edge or falling edge of the NMI input by setting or clearing the nonmaskable interrupt edge bit (NMIEG) in the NMI control register (NMICR). 91 In the NMI exception-handling sequence, the T (Trace) bit in the CPU status register (SR) is cleared to 0, and the interrupt mask level in I2 to I0 is set to 7, masking all other interrupts. The interrupt controller holds the NMI request until the NMI exception-handling sequence begins, then clears the NMI request, so if another interrupt is requested at the NMI pin during the NMI exception-handling sequence, the NMI exception-handling sequence will be carried out again. Coding Examples: To select the rising edge of the NMI input: To select the falling edge of the NMI input: BSET.B #0, @H'FFFC BCLR.B #0, @H'FFFC IRQ0 (Interrupt Request 0): An IRQ0 interrupt can be requested by a low input to the IRQ0 pin and/or a watchdog timer overflow. A low IRQ0 input requests an IRQ0 interrupt if the interrupt request enable 0 bit (IRQ0 E) in the IRQ control register (IRQCR) is set to 1. The interrupt controller samples the level of the IRQ0 pin directly, so this pin must be held low until the interrupt is accepted. Otherwise the request will be ignored. A watchdog timer overflow requests an IRQ0 interrupt if the TME bit is set to 1 and the WT/IT bit is cleared to 0 in the watchdog timer's control/status register. See section 12, "Watchdog Timer", for details of the watchdog timer. The IRQ0 interrupt can be assigned any priority level from 7 to 0 by setting the corresponding value in the upper four bits of IPRA. If bit 4 of data transfer enable register A (DTEA) is set to 1, an IRQ0 interrupt starts the data transfer controller. Otherwise the interrupt is served by the CPU. In the CPU interrupt-handling sequence for IRQ0 the T bit of the status register is cleared to 0, and the interrupt mask level is set to the value in the upper four bits of IPRA. Coding Examples: To enable IRQ0 to be requested by IRQ0 input: To assign priority level 7 to IRQ0: To have IRQ0 start the DTC: BSET.B #0, @H'FFFD OR.B #70, @H'FFF0 BSET.B #4, @H'FFF4 IRQ1 to IRQ7 (Interrupt Request 1 to 7): An IRQ1 to IRQ7 interrupt is requested by a high-to-low transition at the IRQ1 to IRQ7 pin. The IRQ1 to IRQ7 interrupt is enabled only when the interrupt request enable bit IRQ1E to IRQ7E in the IRQ control register is set to 1. The IRQ1 to IRQ7 input is latched in the interrupt controller and held until the interrupt request is accepted. 92 The IRQ1 to IRQ7 interrupts can be assigned any priority level from 7 (high) to 0 (low) by setting the corresponding value in the lower four bits of IPRA. These seven interrupts always have the same priority. They cannot be assigned priorities separately. If bits 0 to 2 of data transfer enable register A (DTEA) are set to 1, IRQ1 to IRQ3 can start the data transfer controller. Otherwise the interrupt is served by the CPU. IRQ4 to IRQ7 cannot start the data transfer controller; they are always served by the CPU. The interrupt controller holds IRQ1 to IRQ7 requests until the corresponding exception-handling sequence begins, then clears the request. Contention among IRQ1 to IRQ7 is resolved when the CPU accepts the interrupt by taking the interrupt with the highest priority first and holding lower-priority interrupts pending. During the interrupt-handling routine, if the same external interrupt is requested again the request is held, but the exception-handling sequence is not carried out immediately because the interrupt is masked by bits I2 to I0 in the status register. On return from the interrupt-handling routine one more instruction is executed, then the pending exception-handling sequence is carried out. In the CPU interrupt-handling sequence for IRQ1 to IRQ7, the T bit of the CPU status register is cleared to 0, and the interrupt mask level is set to the value in the lower four bits of IPRA. Coding Examples: To enable IRQ1 to be requested by IRQ1 input: To assign priority level 7 to IRQ0 and level 5 to IRQ1 to IRQ7: To have IRQ1 start the DTC: BSET.B #1, @H'FFFD MOV.B #75, @H'FFF0 BSET.B #0, @H'FFF4 5.2.2 Internal Interrupts Eighteen types of internal interrupts can be requested by the on-chip supporting modules. Each interrupt is separately vectored in the exception vector table, so it is not necessary for the user-coded interrupt handler routine to determine which type of interrupt has occurred. Each of the internal interrupts can be enabled or disabled by setting or clearing an enable bit in the control register of the on-chip supporting module. 93 An interrupt priority level from 7 to 0 can be assigned to each on-chip supporting module by setting interrupt priority registers B to D. Within each module, different interrupts have a fixed priority order. For most of these interrupts, values set in data transfer enable registers B to D can select whether to have the interrupt served by the CPU or the data transfer controller. In the CPU interrupt-handling sequence, the T bit of the CPU status register is cleared to 0, and the interrupt mask level in bits I2 to I0 is set to the value in the IPR. 5.2.3 Interrupt Vector Table Table 5-2 lists the addresses of the exception vector table entries for each interrupt, and explains how their priority is determined. For the on-chip supporting modules, the priority level set in the interrupt priority register applies to the module as a whole: all interrupts from that module have the same priority level. A separate priority order is established among interrupts from the same module. If the same priority level is assigned to two or more modules and two interrupts are requested simultaneously from these modules, they are served in the priority order indicated in the rightmost column in table 5-2. A reset clears the interrupt priority registers so that all interrupts except NMI start with priority level 0, meaning that they are unconditionally masked. 94 Table 5-2 Interrupts, Vectors, and Priorities Assignable Priority Priority among Levels Priority Vector Table Entry Address Interrupts (Initial IPR within Minimum Maximum on Same Interrupt Level) Bits Module Mode Mode Level* NMI 8 -- -- H'0016 to H'0017 H'002C to H'002F High 7 to 0 IPRA -- H'0040 to H'0041 H'0080 to H'0083 (0) Upper 4 bits 7 to 0 IPRA 6 H'0042 to H'0043 H'0084 to H'0087 IRQ2 Lower 4 bits 5 H'0044 to H'0045 H'0088 to H'008B IRQ3 4 H'0046 to H'0047 H'008C to H'008F IRQ4 3 H'0048 to H'0049 H'0090 to H'0093 IRQ5 2 H'004A to H'004B H'0094 to H'0097 IRQ6 1 H'004C to H'004D H'0098 to H'009B 0 H'004E to H'004F H'009C to H'009F 3 H'0050 to H'0051 H'00A0 to H'00A3 OCIA Upper 4 bits 2 H'0052 to H'0053 H'00A4 to H'00A7 OCIB 1 H'0054 to H'0055 H'00A8 to H'00AB 0 H'0056 to H'0057 H'00AC to H'00AF 3 H'0058 to H'0059 H'00B0 to H'00B3 OCIA Lower 4 bits 2 H'005A to H'005B H'00B4 to H'00B7 OICB 1 H'005C to H'005D H'00B8 to H'00BB 0 H'005E to H'005F H'00BC to H'00BF 2 H'0060 to H'0061 H'00C0 to H'00C3 Upper 4 bits 1 H'0062 to H'0063 H'00C4 to H'00C7 0 H'0064 to H'0065 H'00C8 to H'00CB 2 H'0068 to H'0069 H'00D0 to H'00D3 Upper 4 bits 1 H'006A to H'006B H'00D4 to H'00D7 0 H'006C to H'006D H'00D8 to H'00DB 2 H'0070 to H'0071 H'00E0 to H'00E3 Upper 4 bits 1 H'0072 to H'0073 H'00E4 to H'00E7 0 H'0074 to H'0075 H'00E8 to H'00EB -- H'0078 to H'0079 H'00F0 to H'00F3 (8) IRQ IRQ0 IRQ1 FRT1 FRT2 IRQ7 (0) ICI 7 to 0 FOVI (0) ICI 7 to 0 FOVI (0) 8-Bit CMIA 7 to 0 timer CMIB SCI1 OVI (0) ERI 7 to 0 RXI SCI2 TXI (0) ERI 7 to 0 RXI A/D converter IPRB IPRB IPRC IPRC IPRD TXI (0) ADI 7 to 0 IPRD (0) Lower 4 bits Low Note: * If two or more interrupts are requested simultaneously, they are handled in order of priority level, as set in registers IPRA to IPRD. If they have the same priority level because they are requested from the same on-chip supporting module, they are handled in a fixed priority order within the module. If they are requested from different modules to which the same priority level is assigned, they are handled in the order indicated in the right-hand column. 95 5.3 Register Descriptions 5.3.1 Interrupt Priority Registers A to D (IPRA to IPRD) IRQ0, IRQ1 to IRQ7, and the on-chip supporting modules are each assigned three bits in one of the four interrupt priority registers (IPRA to IPRD). These bits specify a priority level from 7 (high) to 0 (low) for interrupts from the corresponding source. The drawing below shows the configuration of the interrupt priority registers. Table 5-3 lists their assignments to interrupt sources. Bit 7 6 5 4 -- 3 2 1 0 -- Initial value 0 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R R/W R/W R/W Note: Bits 7 and 3 are reserved. They cannot be modified and are always read as 0. Table 5-3 Assignment of Interrupt Priority Registers Interrupt Request Source Register Bits 6 to 4 Bits 2 to 0 IPRA IRQ0 IRQ1 to IRQ7 IPRB FRT1 FRT2 IPRC 8-Bit timer SCI1 IPRD SCI2 A/D converter As table 5-3 indicates, each interrupt priority register specifies priority levels for two interrupt sources. A user program can assign desired levels to these interrupt sources by writing 000 in bits 6 to 4 or bits 2 to 0 to set priority level 0, for example, or 111 to set priority level 7. A reset clears registers IPRA to IPRD to H'00, so all interrupts except NMI are initially masked. When the interrupt controller receives one or more interrupt requests, it selects the request with the highest priority and compares its priority level with the interrupt mask level set in bits I2 to I0 in the CPU status register. If the priority level is higher than the mask level, the interrupt controller passes the interrupt request to the CPU (or starts the data transfer controller). If the priority level is lower than the mask level, the interrupt controller leaves the interrupt request pending until the interrupt mask is altered to a lower level or the interrupt priority is raised. Similarly, if it receives two interrupt requests with the same priority level, the interrupt controller determines their priority as explained in table 5-2 and leaves the interrupt request with the lower priority pending. 96 The interrupt controller requires two system clock (o) periods to determine the priority level of an interrupt. Accordingly, when an instruction modifies an instruction priority register, the new priority does not take effect until after the next instruction has been executed. 5.3.2 NMI Control Register (NMICR)--H'FFFC Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- NMIEG Initial value 1 1 1 1 1 1 1 0 Read/Write -- -- -- -- -- -- -- R/W The NMI control register (NMICR) is an 8-bit register that selects the edge of the NMI input signal which triggers a nonmaskable interrupt. The NMICR is initialized to H'FF (falling edge) at a reset and in the hardware standby mode. It is not initialized in the software standby mode. Bit 7 to 0--Reserved: These bits cannot be modified and are always read as 1. Bit 0--Nonmaskable Interrupt Edge (NMIEG): This bit selects the valid edge of the NMI input signal. Bit 0 NMIEG Description 0 A nonmaskable interrupt is generated on the falling edge (Initial value) of the NMI input signal. 1 A nonmaskable interrupt is generated on the rising edge of the NMI input signal. 5.3.3 IRQ Control Register (IRQCR)--H'FFFD Bit 7 6 5 4 3 2 1 0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 97 The IRQ control register (IRQCR) enables or disables external interrupts on an individual basis. When an interrupt is enabled, the corresponding pin in port 1 or 4 can be used for interrupt request input. (The pin can also be read by the CPU as a port input pin.) The data direction bit in the port 1 or 4 data direction register must be cleared to 0 to designate the input mode. The IRQCR is initialized to H'00 at a reset and in the hardware standby mode, disabling all interrupt requests. It is not initialized in the software standby mode. Bit 7--Interrupt Request 7 Enable (IRQ7E): This bit determines whether a high-to-low transition at pin P47 is recognized as an IRQ7 interrupt request. Bit 7 IRQ7E Description 0 P47 is not used for IRQ7 input. 1 P47 can be used for IRQ7 input.* (Initial value) Bit 6--Interrupt Request 6 Enable (IRQ6E): This bit determines whether a high-to-low transition at pin P46 is recognized as an IRQ6 interrupt request. Bit 6 IRQ6E Description 0 P46 is not used for IRQ6 input. 1 P46 can be used for IRQ6 input.* (Initial value) Bit 5--Interrupt Request 5 Enable (IRQ5E): This bit determines whether a high-to-low transition at pin P45 is recognized as an IRQ5 interrupt request. Bit 5 IRQ5E Description 0 P45 is not used for IRQ5 input. 1 P45 can be used for IRQ5 input.* (Initial value) Note: * In modes 1 and 3 these pins cannot be used for IRQ7 to IRQ4 input because they are occupied by bits 15 to 12 of the address bus. 98 Bit 4--Interrupt Request 4 Enable (IRQ4E): This bit determines whether a high-to-low transition at pin P44 is recognized as an IRQ4 interrupt request. Bit 4 IRQ4E Description 0 P44 is not used for IRQ4 input. 1 P44 can be used for IRQ4 input.* (Initial value) Note: * In modes 1 and 3 these pins cannot be used for IRQ7 to IRQ4 input because they are occupied by bits 15 to 12 of the address bus. Bit 3--Interrupt Request 3 Enable (IRQ3E): This bit determines whether a high-to-low transition at pin P14 is recognized as an IRQ3 interrupt request. Bit 3 IRQ3E Description 0 P14 is not used for IRQ3 input. 1 P14 can be used for IRQ3 input.* (Initial value) Bit 2--Interrupt Request 2 Enable (IRQ2E): This bit determines whether a high-to-low transition at pin P13 is recognized as an IRQ2 interrupt request. Bit 2 IRQ2E Description 0 P13 is not used for IRQ2 input. 1 P13 can be used for IRQ2 input.* (Initial value) Bit 1--Interrupt Request 1 Enable (IRQ1E): This bit determines whether a high-to-low transition at pin P12 is recognized as an IRQ1 interrupt request. Bit 1 IRQ1E Description 0 P12 is not used for IRQ1 input. 1 P12 can be used for IRQ1 input.* (Initial value) Note: * In modes 3 these pins cannot be used for IRQ3 to IRQ1 input because they are occupied by the page address bus. 99 Bit 0--Interrupt Request 0 Enable (IRQ0E): This bit determines whether a low input at pin P11 is recognized as an IRQ0 interrupt request. Bit 0 IRQ0E Description 0 P11 is not used for IRQ0 input. 1 P11 can be used for IRQ0 input. (Initial value) 5.4 Interrupt-Handling Sequence 5.4.1 Interrupt-Handling Flow The interrupt-handling sequence follows the flowchart in figure 5-2, which also covers address-error and trace exceptions. Note that address error, trace exception, and NMI requests bypass the interrupt controller's priority decision logic and are routed directly to the CPU. 1. Interrupt requests are generated by one or more on-chip supporting modules or external interrupt sources. 2. The interrupt controller checks the interrupt priorities set in the IPRA to IPRD and selects the interrupt with the highest priority. Interrupts with lower priorities remain pending. Among interrupts with the same priority level, the interrupt controller determines priority as explained in table 5-2. 3. The interrupt controller compares the priority level of the selected interrupt request with the mask level in the CPU status register (bits I2 to I0). If the priority level is equal to or less than the mask level, the interrupt request remains pending. If the priority level is higher than the mask level, the interrupt controller accepts the interrupt request and proceeds to the next step. 4. The interrupt controller checks the corresponding bit (if any) in the data transfer enable registers (DTEA to DTEB). If this bit is set to 1, the data transfer controller is started. Otherwise, the CPU interrupt exception-handling sequence is started. When the data transfer controller is started, the interrupt request is cleared (except for interrupt requests from the serial communication interface, which are cleared by writing to the TDR or reading the RDR). If the data transfer enable bit is cleared to 0 (or is nonexistent), the sequence proceeds as follows. For the case in which the data transfer controller is started, see section 6, "Data Transfer Controller". 100 5. After the CPU has finished executing the current instruction, the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) are saved to the stack, leaving the stack in the condition shown in figure 5-3 (a) or (b). The program counter value saved on the stack is the address of the next instruction to be executed. 6. The T (Trace) bit of the status register is cleared to 0, and the priority level of the interrupt is copied to bits I2 to I0, thus masking further interrupts unless they have a higher priority level. When an NMI is accepted, the interrupt mask level in bits I2 to I0 is set to 7. 7. The interrupt controller generates the vector address of the interrupt, and the entry at this address in the exception vector table is read to obtain the starting address of the user-coded interrupt handling routine. In step 7, the same difference between the minimum and maximum modes exists as in the reset handling sequence. In the minimum mode, one word is copied from the vector table to the program counter, then the interrupt-handling routine starts executing from the address indicated in the program counter. In the maximum mode, two words are read. The lower byte of the first word is copied to the code page register. The second word is copied to the program counter. The interrupt-handling routine starts executing from the address indicated in the code page register and program counter. 101 Program execution state N Exception present? Address error? Y N Trace? Y N NMI? Y N Y N Level-7 interrupt? N Level-6 interrupt? Y N Level-1 interrupt? Y Y N Mask level in SR 6? Mask level in SR 5? Y N Mask level in SR = 0? Y N Y Interrupt remains pending Y Data transfer enabled? Start DTC N Read DTC vector Exception-handling sequence Read transfer mode Save PC Read source address Read data Y Maximum mode? N Source address increment mode? Save CP N Y Increment source address (+1 or +2) Save SR Write source address Read destination address Clear T bit N Write data Trace? Y Address error? Y Destination address increment mode? N N Update mask level Y Increment destination address (+1 or +2) Write destination address Read DTCR Vectoring DTCR-1 DTCR Write DTCR To user-coded exception-handling routine Y DTCR = 0? Figure 5-2 Interrupt Handling Flowchart Fig 5-2 102 N 5.4.2 Stack Status after Interrupt Exception-Handling Sequence Figure 5-3 (a) and (b) show the stack before and after the interrupt exception-handling sequence. Address Address 2m-4 2m-4 Upper 8 bits of SR 2m-3 2m-3 Lower 8 bits of SR 2m-2 2m-2 Upper 8 bits of PC 2m-1 Lower 8 bits of PC 2m-1 2m Stack area (Before) SP SP 2m (After) Save to stack Notes: 1. PC: The address of the next instruction to be executed is saved. 2. Register saving and restoring must start at an even address. Figure 5-3 (a) Stack before and after Interrupt Exception-Handling (Minimum Mode) Fig 5-3 (a) Address Address 2m-6 2m-6 Upper 8 bits of SR 2m-5 2m-5 Lower 8 bits of SR 2m-4 2m-4 Don't care 2m-3 2m-3 CP 2m-2 2m-2 Upper 8 bits of PC 2m-1 2m-1 Lower 8 bits of PC 2m Stack area (Before) SP SP 2m (After) Save to stack Notes: 1. PC: The address of the next instruction to be executed is saved. 2. Register saving and restoring must start at an even address. Figure 5-3 (b) Stack before and after Interrupt Exception-Handling (Maximum Mode) Fig 5-3 (b) 103 5.4.3 Timing of Interrupt Exception-Handling Sequence Figure 5-4 shows the timing in minimum mode when the program area and stack are both in on-chip memory and the user-coded interrupt-handling routine starts at an even address. Figure 5-5 shows the timing in maximum mode when the program area and stack are both in external memory. 5.5 Interrupts During Operation of the Data Transfer Controller If an interrupt is requested during a DTC data transfer cycle, the interrupt is not accepted until the data transfer cycle has been completed and the next instruction has been executed. This is true even if the interrupt is an NMI. An example is shown below. . . . . . . . . ADD.W R2, R0 Program flow DTC interrupt request Data transfer cycle request NMI interrupt MOV.W R0, @H'FF00 MOV.W @H'FF02, R0 . . . . After data transfer, CPU executes next instruction before starting exception sequence To NMI exception-handling sequence 5.5 Figure 104 o Internal address bus (1) (1) (2) (2) (1) SP-2 SP-4 Vector address (3) NMI, IRQ n, Internal data bus (16 bits) (2) PC SR Vector (4) Internal read signal 105 Internal write signal Priority level decision and wait for end of current instruction Interrupt accepted Stack access Get interrupt Prefetch first Start vector instruction of instruction interruptexecution handling routine (1) Instruction prefetch address (3) Starting address of interrupt-handling routine (2) Instruction code (4) First instruction of interrupt-handling routine Note: This timing chart applies to the minimum mode when the program and stack areas are both in on-chip memory and the interrupt-handling routine starts at an even address. Figure Interrupt Sequence (Minimum Mode, On-Chip Memory) Figure 5-4 5-4. Interrupt Sequence (Minimum Mode, On-Chip Memory) o 106 Figure 5-5. Interrupt Sequence (Maximum Mode, External Memory) External (1) address bus (1) SP-2 SP-1 PCH PC L SP-4 SP-3 SP-6 SP-5 Vector Vector Vector address address+1 Vector address+3 address+2 (3) NMI, IRQ n, External data bus (2) (2) don't care CP SRH SR L don't care Vector CP Vector PC H Vector PCL (4) RD WR Priority level decision and Internal wait for end of processing current cycle instruction Stack access Get interrupt vector Prefetch first instruction of interrupt-handling routine (1) Instruction prefetch address (2) Instruction code (3) Starting address of interrupt-handling routine (4) First instruction of interrupt-handling routine Note: This timing chart applies to the maximum mode when the program and stack areas are both in external memory. Instruction execution is preceded by an interrupt vector fetch and 4-byte (4 bus cycles) instruction prefetch. Figure 5-5 Interrupt Sequence (Maximum Mode, External Memory) Start instruction execution 5.6 Interrupt Response Time Table 5-4 indicates the number of states that may elapse between the generation of an interrupt request and the execution of the first instruction of the interrupt-handling routine, assuming that the interrupt is not masked and not preempted by a higher-priority interrupt. Since word access is performed to onchip memory areas, fastest interrupt service can be obtained by placing the program in on-chip ROM and the stack in on-chip RAM. Table 5-4 Number of States before Interrupt Service Number of States No. Reason for Wait Minimum Mode 1 Interrupt priority decision and comparison with mask level 2 states Maximum Mode in CPU status register 2 Maximum number of Instruction is in on-chip x states to completion memory (x = 38 for LDM instruction specifying all of current instruction registers) Instruction is in external y memory (y = 74 + 16m for LDM instruction specifying all registers) 3 Number of states from saving Stack is in on-chip RAM 16 21 and CP) until first instruction Stack is in external 28 + 6m 41 + 10m of interrupt-handling routine memory Instruction is in on-chip 18 + x 23 + x memory (56) (61) Instruction is in external 18 + y 23 + y memory (92 + 16m) (97 + 16m) Instruction is in on-chip 30 + 6m + x 43 + 10m + x memory (68 + 6m) (81 + 10m) Instruction is in external 30 + 6m + y 43 + 10m + y memory (104 + 22m) (117 + 26m) of PC and SR (or PC, SR, is prefetched. Total Stack is in on-chip RAM Stack is in external RAM Notes: m: Number of wait states inserted in external memory access. Values in parentheses are for the LDM instruction specifying all registers. 107 Section 6 Data Transfer Controller 6.1 Overview The H8/520 chip includes a data transfer controller (DTC) that can be started by designated interrupts to transfer data from a source address to a destination address located in page 0. These addresses include in particular the registers of the on-chip supporting modules and I/O ports. Typical uses of the DTC are to change the setting of a control register of an on-chip supporting module in response to an interrupt from that module, or to transfer data from memory to an I/O port or the serial communication interface. Once set up, the transfer is interrupt-driven, so it proceeds independently of program execution, although program execution temporarily stops while each byte or word is being transferred. The data transfer functions of the DTC could also be performed by the CPU, but the DTC offers three advantages: * It is faster. * It requires less program coding. * It has its own registers and does not require CPU registers to be used as pointers, etc. 6.1.1 Features The main features of the DTC are listed below: * The source address and destination address can be set anywhere in the 64-kbyte address space of page 0. * The DTC can be programmed to transfer one byte or one word of data per interrupt. * The DTC can be programmed to increment the source address and/or destination address after each byte or word is transferred. * After transferring a designated number of bytes or words, the DTC generates a CPU interrupt with the vector of the interrupt source that started the DTC. * This designated data transfer count can be set from 1 to 65,536 bytes or words. 6.1.2 Block Diagram Figure 6-1 shows a block diagram of the DTC. The four DTC control registers (DTMR, DTSR, DTDR, and DTCR) are invisible to the CPU, but corresponding information is kept in a register information table in memory. A separate table is maintained for each DTC interrupt type. When an interrupt requests DTC service, the DTC loads its 109 control registers from the table in memory, transfers the byte or word of data, and writes any altered register information back to memory. Internal data bus DTC request RAM Interrupt controller DTC Register information table 0 IRQ 0 Register information table 1 IRQ 1 DTEA DTMR DTEB DTSR DTEC DTDR DTED DTCR (Legend) DTMR: Data Transfer Mode Register DTSR: Data Transfer Source Address Register DTDR: Data Transfer Destination Address Register DTCR: Data Transfer Count Register DTEA - DTED: Data Transfer Enable Register A - D Figure 6-1 Block Diagram of Data Transfer Controller Fig 6-1 6.1.3 Register Configuration The four DTC control registers are listed in table 6-1. These registers are not located in the address space and cannot be written or read by the CPU. To set information in these registers, a program must write the information in a table in memory from which it will be loaded by the DTC. Table 6-1 Internal Control Registers of the DTC Name Abbreviation Read/Write Data transfer mode register DTMR Disabled Data transfer source address register DTSR Disabled Data transfer destination address register DTDR Disabled Data transfer count register DTCR Disabled 110 Starting of the DTC is controlled by the four data transfer enable registers, which are located in high addresses in page 0. Table 6-2 lists these registers. Table 6-2 Data Transfer Enable Registers Name Abbreviation Read/Write Initial Value Address Data transfer A DTEA R/W H'00 H'FFF4 enable register B DTEB R/W H'00 H'FFF5 C DTEC R/W H'00 H'FFF6 D DTED R/W H'00 H'FFF7 6.2 Register Descriptions 6.2.1 Data Transfer Mode Register (DTMR) Bit Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sz SI DI -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The data transfer mode register is a 16-bit register, the first three bits of which designate the data size and specify whether to increment the source and destination addresses. Bit 15--Sz (Size): This bit designates the size of the data transferred. Bit 15 Sz Description 0 Byte transfer 1 Word transfer* (two bytes at a time) Note: * For word transfer, the source and designation addresses must be even addresses. Bit 14--SI (Source Increment): This bit specifies whether to increment the source address. Bit 14 SI Description 0 Source address is not incremented. 1 1. If Sz = 0: Source address is incremented by +1 after each data transfer. 2. If Sz = 1: Source address is incremented by +2 after each data transfer. 111 Bit 13--DI (Destination Increment): This bit specifies whether to increment the destination address. Bit 13 DI Description 0 Destination address is not incremented. 1 1. If Sz = 0: Destination address is incremented by +1 after each data transfer. 2. If Sz = 1: Destination address is incremented by +2 after each data transfer. Bits 12 to 0--Reserved Bits: These bits are reserved. 6.2.2 Data Transfer Source Address Register (DTSR) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The data transfer source register is a 16-bit register that designates the data transfer source address. For word transfer this must be an even address. In the maximum mode, this address is implicitly located in page 0. 6.2.3 Data Transfer Destination Register (DTDR) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The data transfer destination register is a 16-bit register that designates the data transfer destination address. For word transfer this must be an even address. In the maximum mode, this address is implicitly located in page 0. 6.2.4 Data Transfer Count Register (DTCR) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 112 The data transfer count register is a 16-bit register that counts the number of bytes or words of data remaining to be transferred. The initial count can be set from 1 to 65,536. A register value of 0 designates an initial count of 65,536. The data transfer count register is decremented automatically after each byte or word is transferred. When its value reaches 0, indicating that the designated number of bytes or words have been transferred, a CPU interrupt is generated with the vector of the interrupt that requested the data transfer. 6.2.5 Data Transfer Enable Registers A to D (DTEA to DTED) These four registers designate whether an interrupt starts the DTC. The bits in these registers are assigned to interrupts as indicated in table 6-3. No bits are assigned to the NMI, IRQ4, IRQ5, IRQ6, IRQ7, FOVI, OVI, and ERI interrupts, which cannot request data transfers. Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Table 6-3 Assignment of Data Transfer Enable Registers Interrupt Source Register Module Interrupt Source Bits 7 to 4 Module 7 6 5 4 -- -- IRQ0 DTEA IRQ0 -- DTEB FRT1 -- DTEC 8-Bit timer -- -- DTED SCI2 -- TXI Bits 3 to 0 3 2 1 0 IRQ3 - IRQ1 -- IRQ3 IRQ2 IRQ1 FRT2 -- OCIB OCIA CMIB CMIA SCI1 -- TXI RXI -- -- -- -- ADI OCIB OCIA RXI ICI -- A/D converter ICI Note: Bits marked "--" should always be cleared to 0. If the bit for a certain interrupt is set to 1, that interrupt is regarded as a request for DTC service. If the bit is cleared to 0, the interrupt is regarded as a CPU interrupt request. Only the 16 interrupts indicated in table 6-3 can request DTC service. DTE bits not assigned to any interrupt (indicated by "--" in table 6-3) should be left cleared to 0. 113 Note on Timing of DTE Modifications: The interrupt controller requires two system clock (o) periods to determine the priority level of an interrupt. Accordingly, when an instruction modifies a data transfer enable register, the new setting does not take effect until after the next instruction has been executed. 6.3 Data Transfer Operation 6.3.1 Data Transfer Cycle When started by an interrupt, the DTC executes the following data transfer cycle: 1. 2. 3. 4. 5. 6. 7. From the DTC vector table, the DTC reads the address at which the register information table for that interrupt is located in memory. The DTC loads the data transfer mode register and source address register from this table and reads the data (one byte or word) from the source address. If so specified in the mode register, the DTC increments the source address register and writes the new source address back to the table in memory. The DTC loads the data transfer destination address register and writes the byte or word of data to the destination address. If so specified in the mode register, the DTC increments the destination address register and writes the new destination address back to the table in memory. The DTC loads the data transfer count register from the table in memory, decrements the data count, and writes the new count back to memory. If the data transfer count is now 0, the DTC generates a CPU interrupt. The interrupt vector is the vector of the interrupt type that started the DTC. At an appropriate point during this procedure the DTC also clears the interrupt request by clearing the corresponding flag bit in the status register of the on-chip supporting module to 0. (For IRQ1 to IRQ3, the DTC clears an internal latch.) But the DTC does not clear the data transfer enable bit in the data transfer enable register. This action, if necessary, must be taken by the user-coded interrupt-handling routine invoked at the end of the transfer. The data transfer cycle is shown in a flowchart in figure 6-2. For the steps from the occurrence of the interrupt up to the start of the data transfer cycle, see section 5.4.1, "Interrupt-Handling Flow". 114 INT Interrupt CPU N DTC interrupt? DTC Y Save PC and SR Read DTC vector Read vector Read transfer mode Read address from vector table Read source address Read data Start executing interrupt-handling routine at that address. Y Source address increment mode? N Increment source address (+1 or +2) Write source address Read destination address Write data Y Destination address increment mode? N Increment destination address (+1 or +2) Write destination address Read DTCR DTCR - 1 DTCR Write DTCR DTCR = 0? Y N DTC END Figure 6-2 Flowchart of Data Transfer Cycle Fig 6-2 115 6.3.2 DTC Vector Table The DTC vector table is located immediately following the exception vector table at the beginning of page 0 in memory. For each interrupt that can request DTC service, the DTC vector table provides a pointer to an address in memory where the table of DTC control register information for that interrupt is stored. The register information tables can be placed in any available locations in page 0. Vector table RAM DTMR0 Exception vector table TA 0 Register information table 0 DTSR0 DTDR0 DTCR0 DTMR1 TA 0 TA 1 TA 1 Register information table 1 DTSR1 DTDR1 DTCR1 DTC vector table Notes: 1. TA0, TA1, ...: Addresses of DTC register information tables in memory. Figshould 6-3 normally be located in RAM, but they may 2. The DTC register information tables be located in ROM if it is not necessary to update the register information. Specifically, DTC register information can be located in ROM if neither the source nor the destination address is incremented and the desired number of data transfers is one (DTCR = 0) or infinite (DTCR > 0). Figure 6-3 DTC Vector Table In minimum mode, each entry in the DTC vector table consists of two bytes, pointing to an address in page 0. In maximum mode, for hardware reasons, each DTC vector table entry consists of four bytes but the first two bytes are ignored; the last two bytes point to an address which is implicitly assumed to be in page 0, regardless of the current page specifications. Figure 6-4 shows one DTC vector table entry in minimum and maximum mode. 116 DTC vector table RAM DTC vector table Address Address m Address (H) m+1 Address (L) Register information 1. Minimum mode Don't-care 2m Don't-care 2m + 1 Address (H) 2m + 2 Address (L) 2m + 3 2. Maximum mode Figure 6-4 DTC Vector Table Entry Table 6-4 lists the addresses of the entries in the DTC vector table for each interrupt. Table 6-4 Addresses of DTC Vectors Address of DTC Vector Interrupt IRQ FRT1 FRT2 Minimum Mode Maximum Mode IRQ0 H'0080 to H'0081 H'0100 to H'0103 IRQ1 H'0082 to H'0083 H'0104 to H'0107 IRQ2 H'0084 to H'0085 H'0108 to H'010B IRQ3 H'0086 to H'0087 H'010C to H'010F ICI H'0090 to H'0091 H'0120 to H'0123 OCIA H'0092 to H'0093 H'0124 to H'0127 OCIB H'0094 to H'0095 H'0128 to H'012B ICI H'0098 to H'0099 H'0130 to H'0133 OCIA H'009A to H'009B H'0134 to H'0137 OCIB H'009C to H'009D H'0138 to H'013B 117 Fig 6-4 Table 6-4 Addresses of DTC Vectors (cont) Address of DTC Vector Interrupt Minimum Mode Maximum Mode CMIA H'00A0 to H'00A1 H'0140 to H'0143 CMIB H'00A2 to H'00A3 H'0144 to H'0147 Serial communication RXI H'00AA to H'00AB H'0154 to H'0157 interface 1 TXI H'00AC to H'00AD H'0158 to H'015B Serial communication RXI H'00B2 to H'00B3 H'0164 to H'0157 interface 2 TXI H'00B4 to H'00B5 H'0168 to H'016B A/D converter ADI H'00B8 to H'00B9 H'0170 to H'0173 8-Bit timer 6.3.3 Location of Register Information in Memory For each interrupt, the DTC control register information is stored in four consecutive words in memory in the order shown in figure 6-5. DTC vector table RAM TA DTMR Mode register TA + 2 DTSR Source address register TA + 4 DTDR Destination address register TA + 6 DTCR 8 Bits 8 Bits Count register Figure 6-5 Order of Register Information Fig 6-5 6.3.4 Length of Data Transfer Cycle 1. Register Information in On-Chip RAM Table 6-5 lists the number of states required per data transfer, assuming that the DTC control register information is stored in on-chip RAM. This is the number of states required for loading and saving the DTC control registers and transferring one byte or word of data. Two cases are considered: a transfer between on-chip RAM and a register belonging to an I/O port or on-chip supporting module (i.e., a register in the register field from addresses H'FF80 to H'FFFF); and a transfer between such a register and external RAM. 118 Table 6-5 Number of States per Data Transfer Increment Mode On-Chip RAM Module or I/O Register External RAM Module or I/O Register Source (SI) Destination (DI) Byte Transfer Word Transfer Byte Transfer Word Transfer 0 0 31 34 32 38 0 1 33 36 34 40 1 0 33 36 34 40 1 1 35 38 36 42 Note: Numbers in the table are the number of states. The values in table 6-5 are calculated from the formula: N = 26 + 2 x SI + 2 x DI + MS + MD Where MS and MD have the following meanings: MS: Number of states for reading source data MD: Number of states for writing destination data The values of MS and MD depend on the data location as follows: a. Byte or word data in on-chip RAM: 2 states b. Byte data in external RAM or register field: 3 states c. Word data in external RAM or register field: 6 states 2. Register Information in External RAM If the DTC control register information is stored in external RAM, 20 + 4 x SI + 4 x DI must be added to the values in table 6-5. 3. Interrupt Controller Wait The values given above do not include the time between the occurrence of the interrupt request and the starting of the DTC. This time includes two states for the interrupt controller to check priority and a variable wait until the end of the current CPU instruction. At maximum, this time equals the sum of the values indicated for items No. 1 and 2 in table 6-6. If the data transfer count is 0 at the end of a data transfer cycle, the number of states from the end of the data transfer cycle until the first instruction of the user-coded interrupt-handling routine is executed is the value given for item No. 3 in table 6-6. 119 Table 6-6 Number of States before Interrupt Service Number of States No. Reason for Wait Minimum Mode 1 2 states Interrupt priority decision and comparison with Maximum Mode mask level in CPU status register 2 Maximum number of Instruction is in on-chip x states to completion memory (x = 38 for LDM instruction specifying of current instruction all registers) Instruction is in external y memory (y = 74 + 16m for LDM instruction specifying all registers) 3 Number of states from saving Stack is in on-chip of PC and SR (or PC, SR, RAM and CP) until first instruction Stack is in external of interrupt-handling routine memory 16 21 28 + 6m 41 + 10m is prefetched. Note: m: Number of wait states inserted in external memory access. 6.4 Procedure for Using the DTC A program that uses the DTC to transfer data must do the following: 1. 2. 3. Set the appropriate DTMR, DTSR, DTDR, and DTCR register information in the memory location indicated in the DTC vector table. Set the data transfer enable bit of the pertinent interrupt to 1, and set the priority of the interrupt source (in the interrupt priority register) and the interrupt mask level (in the CPU status register) so that the interrupt can be accepted. Set the interrupt enable bit in the control register for the interrupt source. (For IRQ0 to IRQ3, the control register is the IRQ control register.) Following these preparations, the DTC will be started each time the interrupt occurs. When the number of bytes or words designated by the DTCR value have been transferred, after transferring the last byte or word, the DTC generates a CPU interrupt. 120 The user-coded interrupt-handling routine must take action to prepare for or disable further DTC data transfer: by readjusting the data transfer count, for example, or clearing the data transfer enable bit. If no action is taken, the next interrupt of the same type will start the DTC with an initial data transfer count of 65,536. 6.5 Example Purpose: To receive 128 bytes of serial data via serial communication interface 1. Conditions: * * * * * Operating mode: Minimum mode Received data are to be stored in consecutive addresses starting at H'FE00. DTC control register information for the RXI interrupt is stored at addresses H'FD80 to H'FD87. Accordingly, the DTC vector table contains H'FD at address H'00AA and H'80 at address H'00AB. The desired interrupt mask level in the CPU status register is 4, and the desired SCI1 interrupt priority level is 5. Procedure 1. The user program sets DTC control register information in addresses H'FD80 to H'FD87 as shown in table 6-7. Table 6-7 DTC Control Register Information Set in RAM Register Description DTMR Byte transfer Value Set Source address fixed H'2000 Increment destination address DTSR Address of SCI receive data register H'FEDD DTDR Address H'FE00 H'FE00 DTCR Number of bytes to be received: 128 H'0080 2. 3. The program sets the RXI (SCI Receive Interrupt) bit in the data transfer enable register (bit 1 of register DTEC) to 1. The program sets the interrupt mask in the CPU status register to 4, and the SCI1 interrupt priority in bits 2 to 0 of interrupt priority register IPRC to 5. 121 4. 5. 6. 7. The program sets SCI1 to the appropriate receive mode, and sets the receive interrupt enable (RIE) bit in the serial control register (SCR) to 1 to enable receive interrupts. Thereafter, each time the SCI1 receives one byte of data, it requests an RXI interrupt, which the interrupt controller directs toward the DTC. The DTC transfers the byte from SCI1's receive data register (RDR) into RAM, and clears the interrupt request before ending. When 128 bytes have been transferred (DTCR = 0), the DTC generates a CPU interrupt. The interrupt source is SCI1. The interrupt type is RXI. The user-coded RXI interrupt-handling routine processes the received data and disables further data transfer (by clearing the RIE bit, for example). 122 Figure 6-6 shows the DTC vector table and data in RAM for this example. DTC vector table Address H'00AA H'FD H'00AB H'80 RAM Address H'FD80 H'20 H'FD81 H'00 H'FF Mode Source address H'DD H'FC Destination address H'00 H'00 H'FD87 H'80 H'FE00 Receive data 1 Receive data 2 .. .. . .. .. . H'FE7F Counter Transferred by DTC Receive data 128 RDR SCI1 Figure 6-6 Use of DTC to Receive Data via Serial Communication Interface Fig 6-6 123 Section 7 Wait-State Controller 7.1 Overview To simplify interfacing to low-speed external devices, the H8/520 has an on-chip wait-state controller (WSC) that can insert wait states (TW) to prolong bus cycles. The wait-state function can be used in CPU and DTC access cycles to external addresses. It is not used in access to on-chip memory or registers. The TW states are inserted between the T2 state and T3 state in the bus cycle. The number of wait states can be selected by a value set in the wait-state control register (WCR), or by holding the WAIT pin low for the required interval. 7.1.1 Features The main features of the wait-state controller are as follows: * Selection of three operating modes Programmable wait mode, pin wait mode, or pin auto-wait mode * 0, 1, 2, or 3 wait states can be inserted. And in the pin wait mode, 4 or more states can be inserted by holding the WAIT pin low. 125 7.1.2 Block Diagram Figure 7-1 shows a block diagram of the wait-state controller. Internal data bus WCR - - - - WMS1 WMS0 WC1 WC0 Wait counter WAIT request WAIT input Control logic (Legend) WCR: Wait-state Control Register WMS1, 0: Wait Mode Select 1, 0 WC1, 0: Wait Count 1, 0 Figure 7-1 Block Diagram of Wait-State Controller Fig 7-1 7.1.3 Register Configuration The wait-state controller has one control register: the wait-state control register described in table 7-1. Table 7-1 Register Configuration Name Abbreviation Read/Write Initial Value Address Wait-state control register WCR R/W H'F3 H'FFF8 126 7.2 Wait-State Control Register The wait-state control register (WCR) is an 8-bit register that specifies the wait mode and the number of wait states to be inserted. A reset initializes the WCR to specify the programmable wait mode with three wait states. The WCR is not initialized in the software standby mode. Bit 7 6 5 4 3 2 1 0 -- -- -- -- WMS1 WMS0 WC1 WC0 Initial value 1 1 1 1 0 0 1 1 Read/Write -- -- -- -- R/W R/W R/W R/W Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1. Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1 and WMS0): These bits select the wait mode as shown below: Bit 3 Bit 2 WMS1 WMS0 Description 0 0 Programmable wait mode 0 1 No wait states are inserted, regardless of the wait count. 1 0 Pin wait mode 1 1 Pin auto-wait mode (Initial value) Bits 1 and 0--Wait Count (WC1 and WC0): These bits specify the number of wait states to be inserted. Wait states are inserted only in bus cycles in which the CPU or DTC accesses an external address. Bit 1 Bit 0 WC1 WC0 Description 0 0 No wait states are inserted, except in pin wait mode. 0 1 1 wait state is inserted. 1 0 2 wait states are inserted. 1 1 3 wait states are inserted. (Initial value) 127 7.3 Operation in Each Wait Mode Table 7-2 summarizes the operation of the three wait modes. Table 7-2 Wait Modes Mode WAIT Pin Function Insertion Conditions Number of Wait States Inserted Programmable Disabled Inserted on access to 0 to 3 wait states are inserted, as an off-chip address specified by bits WC0 and WC1. Inserted on access to 0 to 3 wait states are inserted, as an off-chip address specified by bits WC0 and WC1, wait mode WMS1 = 0 WMS0 = 0 Pin wait mode Enabled WMS1 = 1 WMS0 = 0 plus additional wait states while the WAIT pin is held low. Pin auto-wait Enabled Inserted on access to 0 to 3 wait states are inserted, as mode an off-chip address if specified by bits WC0 and WC1. WMS1 = 1 the WAIT pin is low WMS0 = 1 7.3.1 Programmable Wait Mode The programmable wait mode is selected when WMS1 = 0 and WMS0 = 0. Whenever the CPU or DTC accesses an off-chip address, the number of wait states set in bits WC1 and WC0 are inserted. The WAIT pin is not used for wait control; it is available as an I/O pin (P10). 128 Figure 7-2 shows the timing of the operation in this mode when the wait count is 1 (WC1 = 0, WC0 = 1). T2 or T3 T1 T2 TW T3 o A19 - A 0 Off-chip address RD, AS Read data Read data D7 - D0 WR Write data D7 - D0 Figure 7-2 Programmable Wait Mode Fig 7-2 7.3.2 Pin Wait Mode The pin wait mode is selected when WMS1 = 1 and WMS0 = 0. In this mode the WAIT function of the P10/WAIT pin is used automatically. The number of wait states indicated by bits WC1 and WC0 are inserted into any bus cycle in which the CPU or DTC accesses an off-chip address. In addition, wait states continue to be inserted as long as the WAIT pin is held low. In particular, if the wait count is 0 but the WAIT pin is low at the rising edge of the o clock in the T2 state, wait states are inserted until the WAIT pin goes high. This mode is useful for inserting four or more wait states, or when different external devices require different numbers of wait states. 129 Figure 7-3 shows the timing of the operation in this mode when the wait count is 1 (WC1 = 0, WC0 = 1) and the WAIT pin is held low to insert one additional wait state. T1 T2 Wait count TW WAIT pin TW * T3 * o WAIT pin A19 - A 0 Off-chip address RD, AS Read data D7 - D0 WR D7 - D0 Write data Note: * The arrowheads indicate the times at which the WAIT pin is sampled. Figure 7-3 Pin Wait Mode Fig 7-3 130 7.3.3 Pin Auto-Wait Mode The pin auto-wait mode is selected when WMS1 = 1 and WMS0 = 1. In this mode the WAIT function of the P10/WAIT pin is used automatically. In this mode, the number of wait states indicated by bits WC1 and WC0 are inserted, but only if there is a low input at the WAIT pin. Figure 7-4 shows the timing of this operation when the wait count is 1. In the pin auto-wait mode, the WAIT pin is sampled only once, on the falling edge of the o clock in the T2 state. If the WAIT pin is low at this time, the wait-state controller inserts the number of wait states indicated by bits WC1 and WC0. The WAIT pin is not sampled during the TW and T3 states, so no additional wait states are inserted even if the WAIT pin continues to be held low. This mode offers a simple way to interface a low-speed device: the wait states can be inserted by routing the address strobe (AS) signal to the WAIT pin and gating it with an address decode signal. T1 o T3 T2 T1 * T2 TW T3 * WAIT A19 - A 0 External address External address RD, AS Read data Read data D7 - D0 WR D7 - D0 Write data Write data Note: * The arrowheads indicate the times at which the WAIT pin is sampled. Figure 7-4 Pin Auto-Wait Mode Fig 7-4 131 Section 8 Clock Pulse Generator 8.1 Overview The H8/520 chip has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a system (o) clock divider, and a prescaler. The prescaler generates clock signals for the on-chip supporting modules. 8.1.1 Block Diagram CPG XTAL Oscillator EXTAL Divider /2 Prescaler o o/2 - o/4096 Figure 8-1 Block Diagram of Clock Pulse Generator 8.2 Oscillator Circuit Fig 8-1 If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit generates a clock signal for the system clock divider. Alternatively, an external clock signal can be applied directly. 1. Connecting an External Crystal Circuit Configuration: An external crystal can be connected as in the example in figure 8-2. An ATcut parallel resonating crystal should be used. 133 C L1 EXTAL XTAL C L2 CL1 = CL2 = 10 to 22 pF Figure 8-2 Connection of Crystal Oscillator (Example) Fig 8-2 Crystal Oscillator: The external crystal should have the characteristics listed in table 8-1. CL RS L XTAL EXTAL C0 AT-cut parallel resonating crystal Figure 8-3 Crystal Oscillator Equivalent Circuit Fig 8-3 Table 8-1 External Crystal Parameters Frequency (MHz) 2 4 8 12 16 20 Rs max () 500 120 60 40 30 20 C0 (pF) 7 pF max Note on Board Design: When an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. See figure 8-4. When the board is designed, the crystal and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. 134 Not allowed Signal A Signal B H8/520 C L1 XTAL EXTAL C L2 Figure 8-4 Notes on Board Design around External Crystal Fig 8-4 2. Input of External Clock Signal Circuit Configuration: An external clock signal can be input at the EXTAL pin as shown in the example in figure 8-5. EXTAL External clock input 74HC04, etc. XTAL Figure 8-5 External Clock Input (Example) Fig 8-5 Note: The masked ROM version can be driven by supplying an external clock signal to the EXTAL pin only, leaving the XTAL pin open. The PROM version can also be driven in this way, leaving the XTAL pin open, when the clock frequency is 16 MHz or less. 135 External Clock Input Frequency Double the system clock (o) frequency Duty factor 45% to 55% Note on Connection: Invert the clock signal provided to the EXTAL pin, with a 74HC04 for example, and input the inverted clock signal to the XTAL pin. 8.3 System Clock Divider The system clock divider divides the crystal oscillator or external clock frequency (fosc) by 2 to create the o clock. 136 Section 9 I/O Ports 9.1 Overview The H8/520 has seven parallel I/O ports. Ports 1 to 5 are eight-bit input/output ports. Port 6 is a fourbit (or eight-bit*) input-only port. Port 7 is a six-bit input/output port. Table 9-1 summarizes the functions of each port. Input and output are memory-mapped. The CPU views each port as a data register (DR) located in the register field at the high end of page 0 of the address space. Each port (except port 6) also has a data direction register (DDR) which determines which pins are used for input and which for output. To read data from an I/O port, the CPU selects input in the data direction register and reads the data register. This causes the input logic level at the pin to be placed directly on the internal data bus. There is no intervening input latch. To send data to an output port, the CPU selects output in the data direction register and writes the desired data in the data register, causing the data to be held in a latch. The latch output drives the pin through a buffer amplifier. If the CPU reads the data register of an output port, it obtains the data held in the latch rather than the actual level of the pin. As table 9-1 indicates, all of the I/O port pins have dual functions. For example, pin 0 of port 1 can be used either as a general-purpose I/O pin (P10), or for input of the WAIT signal. The function of a pin is determined by the MCU operating mode, or by a value set in a control register. Outputs from ports 1 to 4 can drive one TTL load and a 90-pF capacitive load. Outputs from ports 5 and 7 can drive one TTL load and a 30-pF capacitive load. Outputs from ports 1 to 5 and 7 can also drive a Darlington transistor pair. Outputs from port 3 can drive a light-emitting diode (with 10-mA current sink). Ports 3 and 4 have built-in MOS pull-ups for each input. Port 5 has Schmitt inputs. Schematic diagrams of the I/O port circuits are shown in appendix C. Note: * CP-68 package only 137 Table 9-1 I/O Port Summary Expanded Modes Port Description Pins Mode 1 Mode 2 Port 1 8-bit input/output P17/WR AS, RD, and WR output port P16/RD Mode 3 Single-Chip Mode Mode 4 Mode 7 P17, P16, and P15 input/output P15/AS P14/A16/IRQ3 IRQ3 and IRQ2 input and Page address IRQ3 and IRQ2 IRQ3 and IRQ2 P13/A17/IRQ2 P14 and P13 input/output output input, page input and (A16, A17) address (A16, P14 and P13 A17) output, input/output and P14 and P13 input 138 P12/A18/ IRQ1 input, ADTRG input, Page address IRQ1 input, IRQ1 input, IRQ1/ADTRG and P12 input/output output (A18) page address ADTRG input, and (A18) output, P12 input/output ADTRG input, and P12 input Port 2 Port 3 P11/IRQ0 IRQ0 input and P11 input/output P10/WAIT WAIT input and P10 input/output P10 input/output 8-bit input/output P27 - P20/ Data bus (D7 to D0) P27 to P20 port D7 - D0 8-bit input/output P37 - P30/ Low address Low address Low address Low address P37 to P30 port A7 - A0 bus output bus output bus output bus output input/output (A7 - A0) (A7 - A0) (A7 - A0) (A7 - A0) (Built-in MOS input pull-up. Can drive LEDs.) input/output Table 9-1 I/O Port Summary (cont) Expanded Modes Single-Chip Mode Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 7 Port 4 8-bit input/output P47/A15/IRQ7 High IRQ7 to High IRQ7 to IRQ7 to port P46/A14/IRQ6 address IRQ4 input, address IRQ4 input, IRQ4 input (Built-in MOS P45/A13/IRQ5 bus high address bus high address and P47 to P44 input pull-up) A44/A12/IRQ4 output bus output output bus output input/output (A15 to A8) (A15 to A12), (A15 to A8) (A15 to A12), 139 Port 5 and P47 to and P47 to P44 input P44 input P43/A11 High address High address P43 to P40 P42/A10 bus output bus output input/output P41/A9 (A11 to A8), (A11 to A8), P40/A8 and P43 to and P43 to P40 input P40 input 8-bit input/output P57/FTOA2/o General-purpose input/output pins (P57 to P50) also used for input and output by the 16-bit port P56/FTOA1 free-running timer module (FTOA2, FTOA1, FTOB1, FTCI2, FTCI1, FTI2, FTI1) (Schmit trigger P55/FTOB2/ and 8-bit timer module (TMO, TMRI, TMCI), and for output of the system clock (o). input) FTCI2 P54/FTOB1/ FTCI1 P53/TMO P52/FTI2/ TMRI P51/FTI1 P50/TMCI Table 9-1 I/O Port Summary (cont) Expanded Modes Port Description Pins Mode 1 Port 6 4-bit input port P63 - P60/ General-purpose input (P63 to P60) and analog input (AN0 to AN3) (8-bit input port) AN3 - AN0 (P67 - P60/ Mode 2 Mode 3 Single-Chip Mode Mode 4 Mode 7 [General-purpose input (P67 to P60) and analog input (AN7 to AN0)]* AN7 - AN0)* Port 7 6-bit input/output P75/SCK1 General-purpose input/output pins (P75 to P73), also used for input and output by serial port P74/RXD1 communication interface channel 1 (SCK1, RXD1, TXD1) P73/TXD1 SCK2 (serial communication Page address SCK2 input/ SCK2 input/ SCK2 interface channel 2 clock) output (A19) output, page output or P72 input/output and P72 address input/output input/output output (A19), 140 P72/A19/ or P72 input/output Note: * CP-68 package only. P71/RXD2 General-purpose input/output pins (P71, P70), also used for input and output by serial P70/TXD2 communication interface channel 2 (RXD2, TXD2) 9.2 Port 1 9.2.1 Overview Port 1 is an 8-bit input/output port with the pin configuration shown in figure 9-1. The pin functions depend on the MCU operating mode. Some pins can perform two or three functions simultaneously. Outputs from port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive a Darlington transistor pair. 141 Pin P17 / WR P16 / RD P15 / AS Port P14 / IRQ3 / A16 1 P13 / IRQ2 / A17 P12 / IRQ1 / A18 / ADTRG P11 / IRQ0 P10 / WAIT Modes 1 and 2 Mode 3 WR (output) WR (output) RD (output) RD (output) AS (output) AS (output) P14 (input/output) / IRQ3 (input) A16 (output) P13 (input/output) / IRQ2 (input) A17 (output) P12 (input/output) / IRQ1 (input) / A18 (output) ADTRG (input) P11 (input/output) / IRQ0 (input) P11 (input/output) / IRQ0 (input) P10 (input/output) / WAIT (input) P10 (input/output) / WAIT (input) Mode 4 Single-Chip Mode WR (output) P17 (input/output) RD (output) P16 (input/output) AS (output) P15 (input/output) P14 (input) / IRQ3 (input) / P14 (input/output) / IRQ3 (input) A16 (output) P13 (input) / IRQ2 (input) / P13 (input/output) / IRQ2 (input) A17 (output) P12 (input) / IRQ1 (input) / P12 (input/output) / IRQ1 (input) / A18 (output) / ADTRG (input) ADTRG (input) P11 (input/output) / IRQ0 (input) P11 (input/output) / IRQ0 (input) P10 (input/output) / WAIT (input) P10 (input/output) Figure 9-1 Pin Functions of Port 1 142 9.2.2 Port 1 Registers Table 9-2 lists the registers of port 1. Table 9-2 Port 1 Registers Name Abbreviation Read/Write Initial Value Address Port 1 data direction register P1DDR W H'00* H'FF80 Port 1 data register P1DR R/W H'00 H'FF82 Note: * In single-chip mode. 1. Port 1 Data Direction Register (P1DDR)--H'FF80 Bit 7 6 5 4 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value* 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Note: * In single-chip mode P1DDR is an 8-bit register that selects the direction of each pin in port 1. Details are given for each MCU operating mode below. Modes 1 and 2 (Expanded Minimum Modes): Bits 7 to 5 of P1DDR are fixed at 1 and cannot be written. Pins P17 to P15 are used for output of bus control signals. When bits 4 to 0 of P1DDR are set to 1, the corresponding pin of port 1 functions as an output pin. When these bits are cleared to 0, the corresponding pin functions as an input pin. Mode 3 (Expanded Maximum Mode with On-Chip ROM Disabled): Bits 7 to 2 of P1DDR are fixed at 1 and cannot be written. Pins P17 to P15 are used for output of bus control signals. Pins P14 to P12 are used for page address output. When bits 1 and 0 of P1DDR are set to 1, the corresponding pin of port 1 functions as an output pin. When these bits are cleared to 0, the corresponding pin functions as an input pin. Mode 4 (Expanded Maximum Mode with On-Chip ROM Enabled): Bits 7 to 5 of P1DDR are fixed at 1 and cannot be written. Pins P17 to P15 are used for output of bus control signals. 143 When bits 4 to 2 of P1DDR are set to 1, pins P14 to P12 are used for page address output. When these bits are cleared to 0, the corresponding pin becomes available for general-purpose input. When bits 1 and 0 of P1DDR are set to 1, pins P11 and P10 function as output pins. When these bits are cleared to 0, the corresponding pin functions as an input pin. Mode 7 (Single-Chip Mode): A pin functions as an output pin if the corresponding bit in P1DDR is set to 1, and as in input pin if the bit is cleared to 0. P1DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. P1DDR is initialized to H'00 by a reset and in the hardware standby mode. P1DDR is not initialized in the software standby mode, so if a P1DDR bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 1 data register. 2. Port 1 Data Register (P1DR)--H'FF82 Bit 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P1DR is an 8-bit register containing output data for pins P17 to P10. When port 1 is read, output pins return the value in the P1DR latch, regardless of the actual level at the pin. Input pins return the level at the pin, not the value in the P1DR latch. If any of the port 1 data direction bits are cleared to 0, selecting input, use only data transfer (MOV) instructions to write data in P1DR. Do not use arithmetic, logic, or bit manipulation instructions. These instructions read the input pins and may write unintended data in P1DR. 9.2.3 Pin Functions in Each Mode The functions of port 1 depend on the MCU operating mode. Table 9-3 shows the pin functions in modes 1 and 2. Table 9-4 shows the pin functions in mode 3. Table 9-5 shows the pin functions in mode 4. Table 9-6 shows the pin functions in the single-chip mode. 144 Table 9-3 Port 1 Pin Functions in Modes 1 and 2 Pin Functions WR Output of WR signal. RD Output of RD signal. AS Output of AS signal. P14 / IRQ3 The function depends on the IRQ3E bit in the IRQ control register (IRQCR) and the P14DDR bit as follows: IRQ3E P14DDR Pin function P13 / IRQ2 0 1 0 1 P14 input P14 output 0 1 IRQ3 input IRQ3 input and P14 input and P14 output The function depends on the IRQ2E bit and the P13DDR bit as follows: IRQ2E P13DDR Pin function 0 1 0 1 P13 input P13 output 145 0 1 IRQ2 input IRQ2 input and P13 input and P13 output Table 9-3 Port 1 Pin Functions in Modes 1 and 2 (cont) Pin Functions P12 / IRQ1 / The function depends on the IRQ1E bit, the P12DDR bit, and the trigger enable bit ADTRG (TRGE) in the A/D control register (ADCR) as follows: TRGE 0 IRQ1E P12DDR Pin function 0 1 0 1 P12 input P12 output TRGE Pin function P11 / IRQ0 IRQ1 input IRQ1 input and P12 input and P12 output 0 1 0 1 0 ADTRG input ADTRG input ADTRG input, ADTRG input, and P12 input and P12 output IRQ1 input, IRQ1 input, and P12 input and P12 output 1 The function depends on the IRQ0E bit and the P11DDR bit as follows: IRQ0E P11DDR Pin function P10 / WAIT 1 1 IRQ1E P12DDR 0 0 1 0 1 P11 input P11 output 0 1 IRQ0 input IRQ0 input and P11 input and P11 output The function depends on the wait mode select 1 bit (WMS1) of the wait-state control register (WCR) and the P10DDR bit as follows: WMS1 P10DDR Pin function 0 1 0 1 P10 input P10 output 146 0 1 WAIT input Table 9-4 Port 1 Pin Functions in Mode 3 Pin Functions WR Output of WR signal. RD Output of RD signal. AS Output of AS signal. A16 A16 output A17 A17 output A18 A18 output P11 / IRQ0 The function depends on the IRQ0E bit and the P11DDR bit as follows: IRQ0E P11DDR Pin function P10 / WAIT 0 1 0 1 P11 input P11 output 0 1 IRQ0 input IRQ0 input and P11 input and P11 output The function depends on the wait mode select 1 bit (WMS1) of the wait-state control register (WCR) and the P11DDR bit as follows: WMS1 P10DDR Pin function 0 1 0 1 P10 input P10 output 147 0 1 WAIT input Table 9-5 Port 1 Pin Functions in Mode 4 Pin Functions WR Output of WR signal. RD Output of RD signal. AS Output of AS signal. P14 / IRQ3 / The function depends on the IRQ3E bit in the IRQ control register (IRQCR) and the A16 P14DDR bit as follows: IRQ3E P14DDR Pin function 0 1 0 1 P14 input A16 output 0 1 IRQ3 input A16 output and P14 input P13 / IRQ2 / The function depends on the IRQ2E bit and the P13DDR bit as follows: A17 IRQ2E P13DDR Pin function 0 1 0 1 P13 input A17 output 0 1 IRQ2 input A17 output and P13 input P12 / IRQ1 / The function depends on the IRQ1E bit, the P12DDR bit, and the trigger enable bit A18 / (TRGE) in the A/D control register (ADCR) as follows: ADTRG TRGE 0 IRQ1E P12DDR Pin function 0 1 0 1 P12 input A18 output 0 1 IRQ1 input A18 output and P12 input TRGE 1 IRQ1E P12DDR Pin function 0 1 0 1 0 1 ADTRG input A18 output ADTRG input, A18 output and P12 input IRQ1 input, and P12 input 148 Table 9-5 Port 1 Pin Functions in Mode 4 (cont) Pin Functions P11 / IRQ0 The function depends on the IRQ0E bit and the P11DDR bit as follows: IRQ0E P11DDR Pin function P10 / WAIT 0 1 0 1 P11 input P11 output 0 1 IRQ0 input IRQ0 input and P11 input and P11 output The function depends on the wait mode select 1 bit (WMS1) of the wait-state control register (WCR) and the P10DDR bit as follows: WMS1 P10DDR Pin function 0 1 0 1 P10 input P10 output 149 0 1 WAIT input Table 9-6 Port 1 Pin Functions in Single-Chip Mode Pin Functions P17 P17DDR Pin function 0 1 P17 input P17 output 0 1 P16 input P16 output 0 1 P15 input P15 output P16 P16DDR Pin function P15 P15DDR Pin function P14 / IRQ3 The function depends on the IRQ3E bit in the IRQ control register (IRQCR) and the P14DDR bit as follows: IRQ3E P14DDR Pin function P13 / IRQ2 0 1 0 1 P14 input P14 output 0 1 IRQ3 input IRQ3 input and P14 input and P14 output The function depends on the IRQ2E bit and the P13DDR bit as follows: IRQ2E P13DDR Pin function 0 1 0 1 P13 input P13 output 150 0 1 IRQ2 input IRQ2 input and P13 input and P13 output Table 9-6 Port 1 Pin Functions in Single-Chip Mode (cont) Pin Functions P12 / IRQ1 / The function depends on the IRQ1E bit, the P12DDR bit, and the trigger enable bit ADTRG (TRGE) in the A/D control register (ADCR) as follows: TRGE 0 IRQ1E 0 P12DDR Pin function 1 0 1 P12 input P12 output TRGE IRQ1 input IRQ1 input and P12 input and P12 output 0 P12DDR P11 / IRQ0 1 1 IRQ1E Pin function 0 1 0 1 0 1 ADTRG input ADTRG input ADTRG input, ADTRG input, and P12 input and P12 output IRQ1 input, IRQ1 input, and P12 input and P12 output The function depends on the IRQ0E bit and the P11DDR bit as follows: IRQ0E 0 P11DDR Pin function 1 0 1 P11 input P11 output P10 P10DDR Pin function 0 1 P10 input P10 output 151 0 1 IRQ0 input IRQ0 input and P11 input and P11 output 9.3 Port 2 9.3.1 Overview Port 2 is an 8-bit input/output port with the pin configuration shown in figure 9-2. In the expanded modes it operates as the external data bus (D7 - D0). In the single-chip mode it operates as a generalpurpose input/output port. Outputs from port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive a Darlington transistor pair. Pin Expanded Modes Single-Chip Mode P27 / D7 D7 (input/output) P27 (input/output) P26 / D6 D6 (input/output) P26 (input/output) P25 / D5 D5 (input/output) P25 (input/output) Port P24 / D4 D4 (input/output) P24 (input/output) 2 P23 / D3 D3 (input/output) P23 (input/output) P22 / D2 D2 (input/output) P22 (input/output) P21 / D1 D1 (input/output) P21 (input/output) P20 / D0 D0 (input/output) P20 (input/output) Figure 9-2 Pin Functions of Port 2 9.3.2 Port 2 Registers Table 9-7 lists the registers of port 2. Table 9-7 Port 2 Registers Name Abbreviation Read/Write Initial Value Address Port 2 data direction register P2DDR W H'00 H'FF81 Port 2 data register P2DR R/W H'00 H'FF83 1. Port 2 Data Direction Register (P2DDR)--H'FF81 Bit 7 6 5 4 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value* 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W 152 P2DDR is an 8-bit register that selects the direction of each pin in port 2. Expanded Modes: P2DDR is not used. Single-Chip Mode: A pin functions as an output pin if the corresponding bit in P2DDR is set to 1, and as in input pin if the bit is cleared to 0. P2DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. At a reset and in the hardware standby mode, P2DDR is initialized to H'00, making all eight pins input pins. P2DDR is not initialized in the software standby mode, so if a P2DDR bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 2 data register. 2. Port 2 Data Register (P2DR)--H'FF83 Bit 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P2DR is an 8-bit register containing output data for pins P27 to P20. At a reset and in the hardware standby mode, P2DR is initialized to H'00. When port 2 is read, output pins return the value in the P2DR latch, regardless of the actual level at the pin. Input pins return the level at the pin, not the value in the P2DR latch. If any of the port 2 data direction bits are cleared to 0, selecting input, use only data transfer (MOV) instructions to write data in P2DR. Do not use arithmetic, logic, or bit manipulation instructions. These instructions read the input pins and may write unintended data in P2DR. 153 9.3.3 Pin Functions in Each Mode Port 2 has different functions in the expanded modes (modes 1, 2, 3, 4) and the single-chip mode (mode 7). Separate descriptions are given below. Pin Functions in Expanded Modes: In the expanded modes (modes 1, 2, 3, and 4), port 2 is automatically used as the data bus and P2DDR is ignored. Figure 9-3 shows the pin functions for the expanded modes. D7 (input/output) D6 (input/output) D5 (input/output) Port D4 (input/output) 2 D3 (input/output) D2 (input/output) D1 (input/output) D0 (input/output) Figure 9-3 Port 2 Pin Functions in Expanded Modes Pin Functions in Single-Chip Mode: In the single-chip mode (mode 7), each of the port 2 pins can be designated as an input pin or an output pin, as indicated in figure 9-4, by setting the corresponding bit in P2DDR to 1 for output or clearing it to 0 for input. P27 (input/output) P26 (input/output) P25 (input/output) Port P24 (input/output) 2 P23 (input/output) P22 (input/output) P21 (input/output) P20 (input/output) Figure 9-4 Port 2 Pin Functions in Single-Chip Mode 154 9.4 Port 3 9.4.1 Overview Port 3 is an 8-bit input/output port with the pin configuration shown in figure 9-5. In the expanded modes it provides the low bits (A7 - A0) of the address bus. In the single-chip mode it operates as a general-purpose input/output port. Port 3 has built-in MOS pull-ups that can be turned on or off under program control. Outputs from port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a Darlington transistor pair or LED (with 10-mA current sink). Pin Modes 1 to 4 Single-Chip Mode P37 / A7 A7 (output) P37 (input/output) P36 / A6 A6 (output) P36 (input/output) P35 / A5 A5 (output) P35 (input/output) Port P34 / A4 A4 (output) P34 (input/output) 3 P33 / A3 A3 (output) P33 (input/output) P32 / A2 A2 (output) P32 (input/output) P31 / A1 A1 (output) P31 (input/output) P30 / A0 A0 (output) P30 (input/output) Figure 9-5 Pin Functions of Port 3 9.4.2 Port 3 Registers Table 9-8 lists the registers of port 3. Table 9-8 Port 3 Registers Name Abbreviation Read/Write Initial Value Address Port 3 data direction register P3DDR W H'00* H'FF84 Port 3 data register P3DR R/W H'00 H'FF86 Note: * Initialized to H'00 in modes 2, 4, and 7. Fixed at H'FF in modes 1 and 3. 155 1. Port 3 Data Direction Register (P3DDR)--H'FF84 Bit 7 6 5 4 3 2 1 0 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value* 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Note: * In mode 2, 4, and 7 P3DDR is an 8-bit register that selects the direction of each pin in port 3. Modes 1, 2, 3, and 4: All bits of P3DDR are fixed at 1 and cannot be modified. Port 3 is used for address bus output. Single-Chip Mode: A pin functions as an output pin if the corresponding bit in P3DDR is set to 1, and as an input pin if the bit is cleared to 0. P3DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. At a reset and in the hardware standby mode, P3DDR is initialized to H'00, making all eight pins input pins. P3DDR is not initialized in the software standby mode, so if a P3DDR bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 3 data register. 2. Port 3 Data Register (P3DR)--H'FF86 Bit 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 156 P3DR is an 8-bit register containing output data for pins P37 to P30. At a reset and in the hardware standby mode, P3DR is initialized to H'00. When port 3 is read, output pins return the value in the P3DR latch, regardless of the actual level at the pin. Input pins return the level at the pin, not the value in the P3DR latch. If any of the port 3 data direction bits are cleared to 0, selecting input, use only data transfer (MOV) instructions to write data in P3DR. Do not use arithmetic, logic, or bit manipulation instructions. These instructions read the input pins and may write unintended data in P3DR. 9.4.3 Pin Functions in Each Mode Port 3 has different functions in the expanded modes (modes 1 to 4), and the single-chip mode (mode 7). Separate descriptions are given below. Pin Functions in Modes 1 to 4: In the expanded modes, port 3 is used for output of the low bits (A7 - A0) of the address bus. P3DDR is automatically set for output. Figure 9-6 shows the pin functions for the expanded modes. A7 (output) A6 (output) A5 (output) Port A4 (output) 3 A3 (output) A2 (output) A1 (output) A0 (output) Figure 9-6 Port 3 Pin Functions in Modes 1 and 3 157 Pin Functions in Single-Chip Mode: In the single-chip mode (mode 7), each of the port 3 pins can be designated as an input pin or an output pin, as indicated in figure 9-7, by setting the corresponding bit in P3DDR to 1 for output or clearing it to 0 for input. P37 (input/output) P36 (input/output) P35 (input/output) Port P34 (input/output) 3 P33 (input/output) P32 (input/output) P31 (input/output) P30 (input/output) Figure 9-7 Port 3 Pin Functions in Single-Chip Mode 9.4.4 Built-in MOS Pull-Up The MOS input pull-ups of port 3 are turned on by clearing the corresponding bit in P3DDR to 0 and writing a 1 in P3DR. These pull-ups are turned off at a reset and in the hardware standby mode. Table 9-9 indicates the status of the MOS pull-ups in various modes. Table 9-9 Status of MOS Pull-Ups for Port 3 Mode Reset Hardware Standby Mode Other Operating States* 1 OFF OFF OFF 2 3 4 7 ON/OFF Note: * Including the software standby mode. Notation: OFF: The MOS pull-up is always off. ON/OFF: The MOS pull-up is on when P3DDR = 0 and P3DR = 1, and off otherwise. 158 Note on Usage of MOS Pull-Ups: If a bit manipulation instruction (BSET, BCLR, or BNOT) is used to modify the port 3 data register, since the instruction rewrites the data register according to the levels of input pins, it may switch their built-in MOS pull-ups on or off unintentionally. The same precaution applies to port 4. Example (BSET Instruction): Suppose a BSET instruction is executed to set bit 0 in the port 3 data register (P3DR) under the following conditions. P37: P36: P35 - P30: Input pin, low, MOS pull-up transistor on Input pin, high, MOS pull-up transistor off Output pins, low The intended purpose of this BSET instruction is to switch the output level at P30 from low to high. Before Execution of BSET Instruction P37 P36 P35 P34 P33 P32 P31 P30 Input/output Input Input Output Output Output Output Output Output Pin state Low High Low Low Low Low Low Low DDR 0 0 1 1 1 1 1 1 DR 1 0 0 0 0 0 0 0 Pull-up On Off Off Off Off Off Off Off Execution of BSET Instruction BSET,B @PORT3 ;set bit 0 in port 3 data register #0, After Execution of BSET Instruction P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low High Low Low Low Low Low High DDR 0 0 1 1 1 1 1 1 DR 0 1 0 0 0 0 0 1 Pull-up Off On Off Off Off Off Off Off 159 Explanation: To execute the BSET instruction, the CPU begins by reading port 3. Since P37 and P36 are input pins, the CPU reads the level of these pins directly, not the value in the P3DR data register. It reads P37 as low (0) and P36 as high (1). Since P35 to P30 are output pins, for these pins the CPU reads the value in the data register (0). The CPU therefore reads the value of port 3 as H'40, although the actual value in P3DR is H'80. Next the CPU sets bit 0 of the read data to 1, changing the value to H'41. Finally, the CPU writes this value (H'41) back to P3DR to complete the BSET instruction. As a result, bit P30 is set to 1, switching pin P30 to high output. In addition, bits P37 and P36 are both modified, changing the on/off settings of the MOS pull-up transistors of pins P37 and P36. Programming Solution: The switching of the pull-ups for P37 and P36 in this example can be avoided by reserving a one-byte work area in RAM, performing bit manipulations in the work area, then transferring the work area contents to the port 3 data register. RAM0 is a symbol for the user-selected address of the work area below. Before Execution of BSET Instruction MOV.B MOV.B MOV.B R0 ;put write data (H'80) for port 3 data register in R0 @RAM0 ;transfer from R0 to work area (RAM0) @PORT3 ;transfer from R0 to port 3 data register #80, R0, R0, P37 P36 P35 P34 P33 P32 P31 Input/output Input Input Output Output Output Output Output Output Pin state Low High Low Low Low Low Low Low DDR 0 0 1 1 1 1 1 1 DR 1 0 0 0 0 0 0 0 Pull-up On Off Off Off Off Off Off Off RAM0 1 0 0 0 0 0 0 0 Execution of BSET Instruction BSET,B #0, @RAM0 ;set bit 0 in work area (RAM0) 160 P30 After Execution of BSET Instruction MOV.B MOV.B ;get value in work area (RAM0) ;write value to port 3 data register @RAM0, R0 R0, @PORT3 P37 P36 P35 P34 P33 P32 P31 P30 Input/output Input Input Output Output Output Output Output Output Pin state Low High Low Low Low Low Low High DDR 0 0 1 1 1 1 1 1 DR 1 0 0 0 0 0 0 1 Pull-up On Off Off Off Off Off Off Off RAM0 1 0 0 0 0 0 0 0 161 9.5 Port 4 9.5.1 Overview Port 4 is an eight-bit input/output port with the pin configuration shown in figure 9-8. In the expanded modes without on-chip ROM (modes 1 and 3), port 4 is used for output of bits A15 to A8 of the address bus. In the single-chip mode (mode 7) port 4 is a general-purpose input/output port which can also receive interrupt signals IRQ7 to IRQ4. In the expanded modes with on-chip ROM (modes 2 and 4), the pins of port 4 function either for output of bits A15 - A8 of the address bus, or for general-purpose input and/or output of IRQ7 to IRQ4. Port 4 has built-in MOS pull-ups that can be turned on or off under program control. Outputs from port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a Darlington transistor pair. Pin Port 4 Modes 1 and 3 Modes 2 and 4 P47 / A15 / IRQ7 A15 (output) P47 (input) / A15 (output) / IRQ7 (input) P46 / A14 / IRQ6 A14 (output) P46 (input) / A14 (output) / IRQ6 (input) P45 / A13 / IRQ5 A13 (output) P45 (input) / A13 (output) / IRQ5 (input) P44 / A12 / IRQ4 A12 (output) P44 (input) / A12 (output) / IRQ4 (input) P43 / A11 A11 (output) P43 (input) / A11 (output) P42 / A10 A10 (output) P42 (input) / A10 (output) P41 / A9 A9 (output) P41 (input) / A9 (output) P40 / A8 A8 (output) P40 (input) / A8 (output) Single-Chip Mode P47 (input/output) / IRQ7 (input) P46 (input/output) / IRQ6 (input) P45 (input/output) / IRQ5 (input) P44 (input/output) / IRQ4 (input) P43 (input/output) P42 (input/output) P41 (input/output) P40 (input/output) Figure 9-8 Pin Functions of Port 4 162 9.5.2 Port 4 Registers Table 9-10 lists the registers of port 4. Table 9-10 Port 4 Registers Name Abbreviation Read/Write Initial Value Address Port 4 data direction register P4DDR W H'00* H'FF85 Port 4 data register P4DR R/W H'00 H'FF87 Note: * Initialized to H'00 in modes 2, 4, and 7. Fixed at H'FF in modes 1 and 3. 1. Port 4 Data Direction Register (P4DDR)--H'FF85 Bit 7 6 5 4 3 2 1 0 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value* 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Note: * In modes 2, 4, and 7 P4DDR is an 8-bit register that selects the direction of each pin in port 4. Expanded Modes Not Using On-Chip ROM (Modes 1 and 3): All bits of P4DDR are fixed at 1 and cannot be modified. Port 4 is used for address output. Expanded Modes Using On-Chip ROM (Modes 2 and 4): If a bit in P4DDR is set to 1, the corresponding pin is used for address output. If a bit in P4DDR is cleared to 0, the pin is used for generalpurpose input. P4DDR is initialized to H'00 at a reset and in the hardware standby mode. Single-Chip Mode: A pin functions as an output pin if the corresponding bit in P4DDR is set to 1, and as an input pin if the bit is cleared to 0. P4DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. 163 At a reset and in the hardware standby mode, P4DDR is initialized to H'00, making all eight pins input pins. P4DDR is not initialized in the software standby mode, so if a P4DDR bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 4 data register. 2. Port 4 Data Register (P4DR)--H'FF87 Bit 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P4DR is an 8-bit register containing output data for pins P47 to P40. At a reset and in the hardware standby mode, P4DR is initialized to H'00. When port 4 is read, output pins return the value in the P4DR latch, regardless of the actual level at the pin. Input pins return the level at the pin, not the value in the P4DR latch. If any of the port 4 data direction bits are cleared to 0, selecting input, use only data transfer (MOV) instructions to write data in P4DR. Do not use arithmetic, logic, or bit manipulation instructions. These instructions read the input pins and may write unintended data in P4DR. 164 9.5.3 Pin Functions in Each Mode Port 4 operates in one way in modes 1 and 3, in another way in modes 2 and 4, and in a third way in mode 7. Separate descriptions are given below. Pin Functions in Modes 1 and 3: In modes 1 and 3 (expanded modes in which the on-chip ROM is not used), all bits of P4DDR are automatically set to 1 for output, and the pins of port 4 carry bits A15 - A8 of the address bus. Figure 9-9 shows the pin functions for modes 1 and 3. A15 (output) A14 (output) A13 (output) Port A12 (output) 4 A11 (output) A10 (output) A9 (output) A8 (output) Figure 9-9 Port 4 Pin Functions in Modes 1 and 3 Pin Functions in Modes 2 and 4: Table 9-11 shows the usage of port 4 in modes 2 and 4. 165 Table 9-11 Port 4 Pin Functions in Modes 2 and 4 Pin Functions P47 / A15 / IRQ7 The function depends on the IRQ7E bit and P47DDR bit as follows: IRQ7E P47DDR Pin function 0 1 0 1 P47 input A15 output 0 1 IRQ7 input A15 output and P47 input P46 / A14 / IRQ6 The function depends on the IRQ6E bit and P46DDR bit as follows: IRQ6E P46DDR Pin function 0 1 0 1 P46 input A14 output 0 1 IRQ6 input A14 output and P46 input P45 / A13 / IRQ5 The function depends on the IRQ5E bit and P45DDR bit as follows: IRQ5E P45DDR Pin function 0 1 0 1 P45 input A13 output 0 1 IRQ5 input A13 output and P45 input P44 / A12 / IRQ4 The function depends on the IRQ4E bit and P44DDR bit as follows: IRQ4E P44DDR Pin function 0 1 0 1 P44 input A12 output 0 IRQ4 input and P44 input 166 1 A12 output Table 9-11 Port 4 Pin Functions in Modes 2 and 4 (cont) Pin Functions P43 / A11 P43DDR Pin function 0 1 P43 input A11 output 0 1 P42 input A10 output 0 1 P41 input A9 output 0 1 P40 input A8 output P42 / A10 P42DDR Pin function P41 / A9 P41DDR Pin function P40 / A8 P40DDR Pin function 167 Pin Functions in Single-Chip Mode: Table 9-12 shows the usage of port 4 in the single-chip mode. Table 9-12 Port 4 Pin Functions in Single-Chip Mode Pin Functions P47 / IRQ7 The function depends on the IRQ7E bit and P47DDR bit as follows: IRQ7E P47DDR Pin function P46 / IRQ6 0 0 1 P47 input P47 output P46DDR Pin function 1 IRQ7 input IRQ7 input and P47 input and P47 output 0 1 0 1 P46 input P46 output 0 1 IRQ6 input IRQ6 input and P46 input and P46 output The function depends on the IRQ5E bit and P45DDR bit as follows: IRQ5E P45DDR Pin function P44 / IRQ4 0 The function depends on the IRQ6E bit and P46DDR bit as follows: IRQ6E P45 / IRQ5 1 0 1 0 1 P45 input P45 output 0 1 IRQ5 input IRQ5 input and P45 input and P45 output The function depends on the IRQ4E bit and P44DDR bit as follows: IRQ4E P44DDR Pin function 0 1 0 1 P44 input P44 output 168 0 1 IRQ4 input IRQ4 input and P44 input and P44 output Table 9-12 Port 4 Pin Functions in Single-Chip Mode (cont) Pin Functions P43 P43DDR Pin function 0 1 P43 input P43 output 0 1 P42 input P42 output 0 1 P41 input P41 output 0 1 P40 input P40 output P42 P42DDR Pin function P41 P41DDR Pin function P40 P40DDR Pin function 169 9.5.4 Built-In MOS Pull-Up The MOS input pull-ups of port 4 are turned on by clearing the corresponding bit in P4DDR to 0 and writing a 1 in P4DR. These pull-ups are turned off at a reset and in the hardware standby mode. Table 9-13 indicates the status of the MOS pull-ups in various modes. Table 9-13 Status of MOS Pull-Ups for Port 4 Mode Reset Hardware Standby Mode Other Operating States* 1 OFF OFF OFF 2 ON/OFF 3 OFF 4 ON/OFF 7 ON/OFF Notes: * Including the software standby mode. Notation: OFF: The MOS pull-up is always off. ON/OFF: The MOS pull-up is on when P4DDR = 0 and P4DR = 1, and off otherwise. Note on Usage of MOS Pull-Ups: See the note in section 9.4.4, "Built-in MOS Pull-up". 170 9.6 Port 5 9.6.1 Overview Port 5 is an eight-bit input/output port with the pin configuration shown in figure 9-10. Its pins also carry input and output signals for the free-running timers (FRT1 and FRT2) and 8-bit timer, and pin 7 can output the system clock (o). Port 5 has Schmitt inputs. Outputs from port 5 can drive one TTL load and a 30-pF capacitive load. They can also drive a Darlington transistor pair. P57 (input/output) / FTOA2 (output) / o (output) P56 (input/output) / FTOA1 (output) P55 (input/output) / FTOB2 (output) / FTCI2 (input) Port 5 P54 (input/output) / FTOB1 (output) / FTCI1 (input) P53 (input/output) / TMO (output) P52 (input/output) / FTI2 (input) / TMRI (input) P51 (input/output) / FTI1 (input) P50 (input/output) / TMCI (input) Figure 9-10 Pin Functions of Port 5 9.6.2 Port 5 Registers Table 9-14 lists the registers of port 5. Table 9-14 Port 5 Registers Name Abbreviation Read/Write Initial Value Address Port 5 data direction register P5DDR W H'00 H'FF88 Port 5 data register P5DR R/W H'00 H'FF8A 171 1. Port 5 Data Direction Register (P5DDR)--H'FF88 Bit 7 6 5 4 3 2 1 0 P57DDR P56DDR P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W P5DDR is an 8-bit register that selects the direction of each pin in port 5. A pin functions as an output pin if the corresponding bit in P5DDR is set to 1, and as an input pin if the bit is cleared to 0. P5DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. At a reset and in the hardware standby mode, P5DDR is initialized to H'00, setting all pins for input. P5DDR is not initialized in the software standby mode, so if a P5DDR bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 5 data register. A transition to the software standby mode initializes the on-chip supporting modules, so any pins of port 5 that were being used by an on-chip timer when the transition occurs revert to general-purpose input or output, controlled by P5DDR and P5DR. 2. Port 5 Data Register (P5DR)--H'FF8A Bit 7 6 5 4 3 2 1 0 P57 P56 P55 P54 P53 P52 P51 P50 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P5DR is an 8-bit register containing output data for pins P57 to P50. P5DR is initialized to H'00 by a reset and in the hardware standby mode. When port 5 is read, output pins return the value in the P5DR latch, regardless of the actual level at the pin. Input pins return the level at the pin, not the value in the P5DR latch. If any of the port 5 data direction bits are cleared to 0, selecting input, use only data transfer (MOV) instructions to write data in P5DR. Do not use arithmetic, logic, or bit manipulation instructions. These instructions read the input pins and may write unintended data in P5DR. 172 9.6.3 Pin Functions The pin functions of port 5 are the same in all MCU operating modes. As figure 9-10 indicated, these pins are used for input and output of on-chip timer signals as well as for general-purpose input and output. For some pins, two or more functions can be enabled simultaneously. Table 9-15 shows how the functions of the pins of port 5 are selected. Table 9-15 Port 5 Pin Functions Pin Functions P57 / The function depends on the output enable A bit (OEA) of the FRT1 timer control FTOA2 / o register (TCR), the P57DDR bit, and the system clock output enable bit (oOE) in the port 7 data direction register, as follows: oOE 1 OEA P57DDR Pin function 0 0 0 1 1 0 o output 0 1 0 1 1 0 P57 P57 FTOA2 input output output Note: A reset initializes oOE to 0 in mode 7 and to 1 in modes 1, 2, 3, and 4. 173 1 Table 9-15 Port 5 Pin Functions (cont) Pin Functions P56 / The function depends on the output enable A bit (OEA) of the FRT2 timer control FTOA2 register (TCR) and on the P56DDR bit as follows: OEB P56DDR Pin function 0 1 0 1 P56 input P56 output 0 1 FTOA1 output P55 / The function depends on the output enable B bit (OEB) of the FRT2 timer control FTOB2 / register (TCR) and on the P55DDR bit as follows: FTCI2 OEB P55DDR Pin function 0 1 0 1 P55 input P55 output 0 1 FTOB2 output FTCI2 input P54 / The function depends on the output enable B bit (OEB) of the FRT1 timer control FTOB1 / register (TCR) and on the P54DDR bit as follows: FTCI1 OEB P54DDR Pin function 0 1 0 1 P54 input P54 output FTCI1 input 174 0 1 FTOB1 output Table 9-15 Port 5 Pin Functions (cont) Pin Functions P53 / TMO The function depends on output select bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR) of the 8-bit timer, and on the P53DDR bit as follows: OS3 to OS0 All three bits are 0 P53DDR 0 1 P53 input P53 output Pin function At least one bit is set to 1 0 1 TMO output P52 / FTI2 / In addition to functioning for general-purpose input or output, this pin receives the TMRI input capture signal (FTI2) for free-running timer 2 and the reset input (TMRI) for the 8-bit timer. TMRI input is enabled when the counter clear bits (CCLR1 and CCLR0) in the timer control register (TCR) are both set to 1. P52DDR Pin function 0 1 P52 input P52 output FTI2 and TMRI input P51 / FTI1 P51DDR Pin function 0 1 P51 input P51 output FTI1 input P50 / TMCI In addition to functioning for general-purpose input or output, this pin can simultaneously be used for external clock input for the 8-bit timer, depending on clock select bits 2 to 0 (CKS2, CKS1, and CKS0) in the timer control register (TCR). P50DDR Pin function 0 1 P50 input P50 output TMCI input 175 9.7 Port 6 9.7.1 Overview Port 6 is a 4-bit input port that also receives inputs for the on-chip A/D converter. The pin functions are the same in all MCU operating modes, as shown in figure 9-11. P63 (input) / AN3 (input) Port P62 (input) / AN2 (input) 6 P61 (input) / AN1 (input) P60 (input) / AN0 (input) Figure 9-11 Pin Functions of Port 6 In the 68-pin CP-68 package, port 6 has eight pins for general-purpose input and analog input. Figure 9-12 shows the pin configuration of port 6 in the CP-68 package. P67 (input) / AN7 (input) P66 (input) / AN6 (input) P65 (input) / AN5 (input) Port P64 (input) / AN4 (input) 6 P63 (input) / AN3 (input) P62 (input) / AN2 (input) P61 (input) / AN1 (input) P60 (input) / AN0 (input) Figure 9-12 Pin Functions of Port 6 (CP-68 Package) 176 9.7.2 Port 6 Registers Port 6 has only the data register described in table 9-16. Since it is exclusively an input port, there is no data direction register. Table 9-16 Port 6 Registers Name Abbreviation Read/Write Address Port 6 data register P6DR R H'FF8B 1. Port 6 Data Register (P6DR)--H'FF8B Bit Read/Write 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 R R R R R R R R Note: Bits 7 to 4 are valid in the CP-68 package only. When the CPU reads P6DR it always reads the current status of each pin, except that during A/D conversion the pin currently being converted reads 1 regardless of the actual input voltage at that pin. In a 64-pin package, the data read from the upper four bits are indeterminate. 177 9.8 Port 7 9.8.1 Overview Port 7 is a 6-bit input/output port with the pin configuration shown in figure 9-13. In addition to general-purpose input and output, its pins are used for input and output by the on-chip serial communication interface (SCI). In the expanded maximum modes (modes 3 and 4), it also supplies bit A19 of the page address bus. Outputs from port 7 can drive one TTL load and a 30-pF capacitive load. They can also drive a Darlington transistor pair. 178 Pin P75 (input/output) / SCK1 (input/output) Port P74 (input/output) / RXD1 (input) 7 P73 (input/output) / TXD1 (output) P72 (input/output) / SCK2 (input/output) / A19 (output) P71 (input/output) / RXD2 (input) P70 (input/output) / TXD2 (output) Modes 1, 2, and 7 Mode 3 P75 (input/output) / SCK1 (input/output) P75 (input/output) / SCK1 (input/output) P74 (input/output) / RXD1 (input) P74 (input/output) / RXD1 (input) P73 (input/output) / TXD1 (output) P73 (input/output) / TXD1 (output) P72 (input/output) / SCK2 (input/output) A19 (output) P71 (input/output) / RXD2 (input) P71 (input/output) / RXD2 (input) P70 (input/output) / TXD2 (output) P70 (input/output) / TXD2 (output) Mode 4 P75 (input/output) / SCK1 (input/output) P74 (input/output) / RXD1 (input) P73 (input/output) / TXD1 (output) P72 (input/output) / SCK2 (input/output) / A19 (output) P71 (input/output) / RXD2 (input) P70 (input/output) / TXD2 (output) Figure 9-13 Pin Functions of Port 7 179 9.8.2 Port 7 Registers Table 9-17 lists the registers of port 7. Table 9-17 Port 7 Registers Name Abbreviation Read/Write Initial Value Address Port 7 data direction register P7DDR W H'40* H'FF8C Port 7 data register P7DR R/W H'00 H'FF8E Note: * Initialized to H'40 in modes 1, 2, 3, and 4, and to H'00 in mode 7. 1. Port 7 Data Direction Register (P7DDR)--H'FF8C Bit 7 6 5 4 3 2 1 0 -- oOE Initial value -- 1/0 0 0 0 0 0 0 Read/Write -- W W W W W W W P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR P7DDR is an 8-bit register that selects the direction of each pin in port 7. Bit 7 is reserved. Bit 6 selects whether the system clock (o) is output at pin P57 in port 5. The usage of P7DDR depends on the MCU operating mode as explained below. Modes 1, 2, and 4: A pin functions as an output pin if the corresponding bit in P7DDR is set to 1, and as an input pin if the bit is cleared to 0. P7DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. At a reset and in the hardware standby mode, P7DDR is initialized to H'40, setting all pins to the input state. P7DDR is not initialized in the software standby mode, so if a P7DDR bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 7 data register. A transition to the software standby mode initializes the serial communication interface module, so any pins of port 7 that were being used for serial communication when the transition occurs revert to general-purpose input or output, controlled by P7DDR and P7DR. 180 Mode 3: Bit 2 is fixed at the value 1 and pin P72 is used for page address output. Bits 5 to 3 and 1 to 0 can be set to 1 for output or cleared to 0 for input as in the other MCU modes. Mode 7: In single-chip mode, P7DDR is initialized to H'00 at a reset and in the hardware standby mode. 2. Port 7 Data Register (P7DR)--H'FF8E Bit 7 6 5 4 3 2 1 0 -- -- P75 P74 P73 P72 P71 P70 Initial value -- -- 0 0 0 0 0 0 Read/Write -- -- R/W R/W R/W R/W R/W R/W P7DR is an 8-bit register containing the data for pins P76 to P70. Bits 7 and 6 are reserved. When port 7 is read, output pins return the value in the P7DR latch, regardless of the actual level at the pin. Input pins return the level at the pin, not the value in the P7DR latch. If any of the port 7 data direction bits are cleared to 0, selecting input, use only data transfer (MOV) instructions to write data in P7DR. Do not use arithmetic, logic, or bit manipulation instructions. These instructions read the input pins and may write unintended data in P7DR. 9.8.3 Pin Functions The pin functions of port 7 depend on the MCU operating mode. Table 9-18 shows how the functions are selected in modes 1, 2, and 7. Table 9-19 shows how they are selected in mode 3. Table 9-20 shows how they are selected in mode 4. 181 Table 9-18 Port 7 Pin Functions in Modes 1, 2, and 7 Pin Functions P75 / SCK1 The function depends on the communication mode bit (C/A) and the clock enable 1 and 2 bits (CKE1 and CKE0) of the serial control register (SCR) of SCI1 as follows: C/A 0 CKE1 0 CKE0 Pin function 1 0 1 1 0 0 1 0 1 1 0 1 P75 SCI1 SCI1 external SCI1 internal SCI1 external input internal clock input clock output clock input or clock output* output Note: * Input or output is selected by the P75DDR bit. P74 / RXD1 The function depends on the receive enable bit (RE) of the serial control register (SCR) of SCI1 and on the P74DDR bit as follows: RE P74DDR Pin function P73 / TXD1 0 1 0 1 P74 input P74 output 0 1 RXD1 input The function depends on the transmit enable bit (TE) of the serial control register (SCR) of SCI1 and on the P73DDR bit as follows: TE P73DDR Pin function 0 1 0 1 P73 input P73 output 182 0 1 TXD1 output Table 9-18 Port 7 Pin Functions in Modes 1, 2, and 7 (cont) Pin Functions P72 / SCK2 The function depends on the communication mode bit (C/A) and the clock enable 1 and 2 bits (CKE1 and CKE0) of the serial control register (SCR) of SCI2 as follows: C/A 0 CKE1 0 CKE0 Pin function 1 0 1 1 0 0 1 0 1 1 0 1 P72 SCI2 SCI2 external SCI2 internal SCI2 external input internal clock input clock output clock input or clock output* output Note: * Input or output is selected by the P72DDR bit. P71 / RXD2 The function depends on the receive enable bit (RE) of the serial control register (SCR) of SCI2 and on the P71DDR bit as follows: RE P71DDR Pin function P70 / TXD2 0 1 0 1 P71 input P71 output 0 1 RXD2 input The function depends on the transmit enable bit (TE) of the serial control register (SCR) of SCI2 and on the P70DDR bit as follows: TE P70DDR Pin function 0 1 0 1 P70 input P70 output 183 0 1 TXD2 output Table 9-19 Port 7 Pin Functions in Mode 3 Pin Functions P75 / SCK1 The function depends on the communication mode bit (C/A) and the clock enable 1 and 2 bits (CKE1 and CKE0) of the serial control register (SCR) of SCI1 as follows: C/A 0 CKE1 0 CKE0 Pin function 1 0 1 1 0 0 1 0 1 1 0 1 P75 SCI1 SCI1 external SCI1 internal SCI1 external input internal clock input clock output clock input or clock output* output Note: * Input or output is selected by the P75DDR bit. P74 / RXD1 The function depends on the receive enable bit (RE) of the serial control register (SCR) of SCI1 and on the P74DDR bit as follows: RE P74DDR Pin function 0 1 0 1 P74 input P74 output 184 0 1 RXD1 input Table 9-19 Port 7 Pin Functions in Mode 3 (cont) Pin Functions P73 / TXD1 The function depends on the transmit enable bit (TE) of the serial control register (SCR) of SCI1 and on the P73DDR bit as follows: TE 0 P73DDR Pin function 1 0 1 P73 input P73 output 0 1 TXD1 output A19 A19 page address output. P71 / RXD2 The function depends on the receive enable bit (RE) of the serial control register (SCR) of SCI2 and on the P71DDR bit as follows: RE P71DDR Pin function P70 / TXD2 0 1 0 1 P71 input P71 output 0 1 RXD2 input The function depends on the transmit enable bit (TE) of the serial control register (SCR) of SCI2 and on the P70DDR bit as follows: TE P70DDR Pin function 0 1 0 1 P70 input P70 output 185 0 1 TXD2 output Table 9-20 Port 7 Pin Functions in Mode 4 Pin Functions P75 / SCK1 The function depends on the communication mode bit (C/A) and the clock enable 1 and 2 bits (CKE1 and CKE0) of the serial control register (SCR) of SCI1 as follows: C/A 0 CKE1 0 CKE0 Pin function 1 0 1 1 0 0 1 0 1 1 0 1 P75 SCI1 SCI1 external SCI1 internal SCI1 external input internal clock input clock output clock input or clock output* output Note: * Input or output is selected by the P75DDR bit. P74 / RXD1 The function depends on the receive enable bit (RE) of the serial control register (SCR) of SCI1 and on the P74DDR bit as follows: RE P74DDR Pin function 0 1 0 1 P74 input P74 output 186 0 1 RXD1 input Table 9-20 Port 7 Pin Functions in Mode 4 (cont) Pin Functions P73 / TXD1 The function depends on the transmit enable bit (TE) of the serial control register (SCR) of SCI1 and on the P73DDR bit as follows: TE 0 P73DDR Pin function 1 0 1 0 P73 input P73 output 1 TXD1 output P72 / A19 / The function depends on the C/A, CKE1, and CKE0 bits of the serial control register SCK2 (SCR) of SCI2 and on P72DDR as follows: P72DDR 0 C/A 0 CKE1 0 CKE0 Pin function 1 0 1 P72 input 0 SCI2 internal 1 SCI2 external clock input clock output P72DDR 0 C/A 1 CKE1 CKE0 Pin function 1 Don't care 0 0 1 1 0 Don't care 1 SCI2 internal SCI2 external clock output clock input 187 Don't care A19 output Table 9-20 Port 7 Pin Functions in Mode 4 (cont) Pin Functions P71 / RXD2 The function depends on the receive enable bit (RE) of the serial control register (SCR) of SCI2 and on the P71DDR bit as follows: RE P71DDR Pin function P70 / TXD2 0 1 0 1 P71 input P71 output 0 1 RXD2 input The function depends on the transmit enable bit (TE) of the serial control register (SCR) of SCI2 and on the P70DDR bit as follows: TE P70DDR Pin function 0 1 0 1 P70 input P70 output 188 0 1 TXD2 output Section 10 16-Bit Free-Running Timers 10.1 Overview The H8/520 has an on-chip 16-bit free-running timer (FRT) module with two independent channels (FRT1 and FRT2). Both channels are functionally identical. Each channel has a 16-bit free-running counter that it uses as a time base. Applications of the FRT module include rectangular-wave output (up to two independent waveforms per channel), input pulse width measurement, and measurement of external clock periods. 10.1.1 Features The features of the free-running timer module are listed below. * Selection of four clock sources The free-running counters can be driven by an internal clock source (o/4, o/8, or o/32), or an external clock input (enabling use as an external event counter). * Two independent comparators Each free-running timer channel can generate two independent waveforms. * Input capture function The current count can be captured on the rising or falling edge (selectable) of an input signal. * Four types of interrupts Compare-match A and B, input capture, and overflow interrupts can be requested independently. The compare-match and input capture interrupts can be served by the data transfer controller (DTC), enabling interrupt-driven data transfer with minimal CPU programming. * Counter can be cleared under program control The free-running counters can be cleared on compare-match A. 189 10.1.2 Block Diagram Figure 10-1 shows a block diagram of one free-running timer channel. External clock Internal clocks o/4 o/8 FTCI o/32 Clock Clock select OCRA Compare-match A Comparator A Bus interface FTOA Overflow FTOB FRC FTI Clear Compare-match B Comparator B Control OCRB logic Capture Module data bus ICR TCSR TCR ICI OCIA OCIB FOVI Interrupt signals OCRA: OCRB: FRC: ICR: TCSR: TCR: Output Compare Register A Output Compare Register B Free Running Counter Input Capture Register Timer Control/Status Register Timer Control Register Figure 10-1 Block Diagram of 16-Bit Free-Running Timer Figure 10-1 190 Internal data bus 10.1.3 Input and Output Pins Table 10-1 lists the input and output pins of the free-running timer module. Table 10-1 Input and Output Pins of Free-Running Timer Module Channel Name Abbreviation I/O Function 1 Output compare A FTOA1 Output Output controlled by comparator A of FRT1 Output compare B or FTOB1 / Output / Output controlled by comparator B of counter clock input FTCI1 Input FRT1, or input of external clock source for FRT1 Input capture FTI1 Input Trigger for capturing current count of FRT1 Output compare A* FTOA2 Output Output controlled by comparator A of FRT2 Output compare B or FTOB2 / Output / Output controlled by comparator B of FRT2, or counter clock input FTCI2 Input input of external clock source for FRT2 Input capture FTI2 Input Trigger for capturing current count of FRT2 2 Note: * When the oOE bit in P7DDR is set to 1, this pin is used for system clock (o) output and cannot be used for FTOA2. 191 10.1.4 Register Configuration Table 10-2 lists the registers of each free-running timer channel. Table 10-2 Register Configuration Initial Channel Name Abbreviation R/W Value Address 1 Timer control register TCR R/W H'00 H'FF90 Timer control/status register TCSR R/(W)* H'00 H'FF91 Free-running counter (High) FRC (H) R/W H'00 H'FF92 Free-running counter (Low) FRC (L) R/W H'00 H'FF93 Output compare register A (High) OCRA (H) R/W H'FF H'FF94 Output compare register A (Low) OCRA (L) R/W H'FF H'FF95 Output compare register B (High) OCRB (H) R/W H'FF H'FF96 Output compare register B (Low) OCRB (L) R/W H'FF H'FF97 Input capture register (High) ICR (H) R H'00 H'FF98 Input capture register (Low) ICR (L) R H'00 H'FF99 Timer control register TCR R/W H'00 H'FFA0 Timer control/status register TCSR R/(W)* H'00 H'FFA1 Free-running counter (High) FRC (H) R/W H'00 H'FFA2 Free-running counter (Low) FRC (L) R/W H'00 H'FFA3 Output compare register A (High) OCRA (H) R/W H'FF H'FFA4 Output compare register A (Low) OCRA (L) R/W H'FF H'FFA5 Output compare register B (High) OCRB (H) R/W H'FF H'FFA6 Output compare register B (Low) OCRB (L) R/W H'FF H'FFA7 Input capture register (High) ICR (H) R H'00 H'FFA8 Input capture register (Low) ICR (L) R H'00 H'FFA9 2 Note: * Software can write a 0 to clear bits 7 to 4, but cannot write a 1 in these bits. 192 10.2 Register Descriptions 10.2.1 Free-Running Counter (FRC)--H'FF92, H'FFA2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Each FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and CKS0) of the timer control register (TCR). The FRC can be cleared by compare-match A. When the FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. Because the FRC is a 16-bit register, a temporary register (TEMP) is used when the FRC is written or read. See section 10.3, "CPU Interface", for details. The FRCs are initialized to H'0000 at a reset and in the standby modes. 10.2.2 Output Compare Registers A and B (OCRA and OCRB)--H'FF94 and H'FF96, H'FFA4 and H'FFA6 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually compared with the value in the FRC. When a match is detected, the corresponding output compare flag (OCFA or OCFB) is set in the timer control/status register (TCSR). In addition, if the output enable bit (OEA or OEB) in the timer control register (TCR) is set to 1, when the output compare register and FRC values match, the logic level selected by the output level bit (OLVLA or OLVLB) in the timer control status register (TCSR) is output at the output compare pin (FTOA or FTOB). 193 Because OCRA and OCRB are 16-bit registers, a temporary register (TEMP) is used when they are written. See section 10.3, "CPU Interface", for details. OCRA and OCRB are initialized to H'FFFF at a reset and in the standby modes. 10.2.3 Input Capture Register (ICR)--H'FF98, H'FFA8 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R The ICR is a 16-bit read-only register. When the rising or falling edge of the signal at the input capture input pin is detected, the current value of the FRC is copied to the ICR. At the same time, the input capture flag (ICF) in the timer control/status register (TCSR) is set to 1. The input capture edge is selected by the input edge select bit (IEDG) in the TCSR. Because the ICR is a 16-bit register, a temporary register (TEMP) is used when the ICR is written or read. See section 10.3, "CPU Interface", for details. To ensure input capture, the pulse width of the input capture signal should be at least 1.5 system clock periods (1.5 o). ------- ------- o O FTI Minimum FTI Pulse Width The ICR is initialized to H'0000 at a reset and in the standby modes. Note: When input capture is detected, the FRC value is transferred to the ICR even if the input capture flag (ICF) is already set. 194 10.2.4 Timer Control Register (TCR)--H'FF90, H'FFAO Bit 7 6 5 4 3 2 1 0 ICIE OCIEB OCIEA OVIE OEB OEA CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The TCR is an 8-bit readable/writable register that selects the FRC clock source, enables the output compare signals, and enables interrupts. The TCR is initialized to H'00 at a reset and in the standby modes. Bit 7--Input Capture Interrupt Enable (ICIE): This bit selects whether to request an input capture interrupt (ICI) when the input capture flag (ICF) in the timer status/control register (TCSR) is set to 1. Bit 7 ICIE Description 0 The input capture interrupt request (ICI) is disabled. 1 The input capture interrupt request (ICI) is enabled. (Initial value) Bit 6--Output Compare Interrupt Enable B (OCIEB): This bit selects whether to request output compare interrupt B (OCIB) when output compare flag B (OCFB) in the timer status/control register (TCSR) is set to 1. Bit 6 OCIEB Description 0 Output compare interrupt request B (OCIB) is disabled. 1 Output compare interrupt request B (OCIB) is enabled. (Initial value) Bit 5--Output Compare Interrupt Enable A (OCIEA): This bit selects whether to request output compare interrupt A (OCIA) when output compare flag A (OCFA) in the timer status/control register (TCSR) is set to 1. Bit 5 OCIEA Description 0 Output compare interrupt request A (OCIA) is disabled. 1 Output compare interrupt request A (OCIA) is enabled. 195 (Initial value) Bit 4--Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a free-running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in the timer status/control register (TCSR) is set to 1. Bit 4 OVIE Description 0 The free-running timer overflow interrupt request (FOVI) is disabled. 1 The free-running timer overflow interrupt request (FOVI) is enabled. (Initial value) Bit 3--Output Enable B (OEB): This bit selects whether to enable or disable output of the logic level selected by the OLVLB bit in the timer status/control register (TCSR) at the output compare B pin when the FRC and OCRB values match. Bit 3 OEB Description 0 Output compare B output is disabled. 1 Output compare B output is enabled. (Initial value) Bit 2--Output Enable A (OEA): This bit selects whether to enable or disable output of the logic level selected by the OLVLA bit in the timer status/control register (TCSR) at the output compare A pin when the FRC and OCRA values match. Bit 2 OEA Description 0 Output compare A output is disabled. 1 Output compare A output is enabled. (Initial value) Bits 1 and 0--Clock Select (CKS1 and CKS0): These bits select external clock input or one of three internal clock sources for the FRC. External clock pulses are counted on the rising edge. Bit 1 Bit 0 CKS1 CKS0 Description 0 0 Internal clock source (o/4) 0 1 Internal clock source (o/8) 1 0 Internal clock source (o/32) 1 1 External clock source (counted on the rising edge)* (Initial value) Note: * Output enable B (bit 3) must be cleared to 0. 196 10.2.5 Timer Control/Status Register (TCSR)--H'FF91, H'FFA1 Bit 7 6 5 4 3 2 1 0 ICF OCFB OCFA OVF OLVLB OLVLA IEDG CCLRA Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W The TCSR is an 8-bit readable and partially writable* register that selects the input capture edge and output compare levels, and specifies whether to clear the counter on compare-match A. It also contains four status flags. The TCSR is initialized to H'00 at a reset and in the standby modes. Note: * Software can write a 0 in bits 7 to 4 to clear the flags, but cannot write a 1 in these bits. Bit 7--Input Capture Flag (ICF): This status flag is set to 1 to indicate an input capture event. It signifies that the FRC value has been copied to the ICR. Bit 7 ICF Description 0 This bit is cleared from 1 to 0 when: 1 (Initial value) 1. The CPU reads the ICF bit after the ICF bit has been set to 1, then writes a 0 in this bit. 2. The data transfer controller (DTC) serves an input capture interrupt . This bit is set to 1 when an input capture signal causes the FRC value to be copied to the ICR. Bit 6--Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value matches the OCRB value. Bit 6 OCFB Description 0 This bit is cleared from 1 to 0 when: 1 (Initial value) 1. The CPU reads the OCFB bit after the OCFB bit has been set to 1, then writes a 0 in this bit. 2. The data transfer controller (DTC) serves output compare interrupt B. This bit is set to 1 when FRC = OCRB. 197 Bit 5--Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value matches the OCRA value. Bit 5 OCFA Description 0 This bit is cleared from 1 to 0 when: 1 (Initial value) 1. The CPU reads the OCFA bit after the OCFA bit has been set to 1, then writes a 0 in this bit. 2. The data transfer controller (DTC) serves output compare interrupt A. This bit is set to 1 when FRC = OCRA. Bit 4--Timer Overflow Flag (OVF): This status flag is set to 1 when the FRC overflows (changes from H'FFFF to H'0000). Bit 4 OVF Description 0 This bit is cleared from 1 to 0 when the CPU reads (Initial value) the OVF bit after the OVF bit has been set to 1, then writes a 0 in this bit. 1 This bit is set to 1 when FRC changes from H'FFFF to H'0000. Bit 3--Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin when the FRC and OCRB values match. Bit 3 OLVLB Description 0 A 0 logic level (low) is output for compare-match B. 1 A 1 logic level (high) is output for compare-match B. (Initial value) Bit 2--Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin when the FRC and OCRA values match. Bit 2 OLVLA Description 0 A 0 logic level (low) is output for compare-match A. 1 A 1 logic level (high) is output for compare-match A. (Initial value) Bit 1--Input Edge Select (IEDG): This bit selects whether to capture the count on the rising or falling edge of the input capture signal. 198 Bit 1 IEDG Description 0 The FRC value is copied to the ICR on the falling edge (Initial value) of the input capture signal. 1 The FRC value is copied to the ICR on the rising edge of the input capture signal. Bit 0--Counter Clear A (CCLRA): This bit selects whether to clear the FRC at compare-match A (when the FRC and OCRA values match). Bit 0 CCLRA Description 0 The FRC is not cleared. 1 The FRC is cleared at compare-match A. (Initial value) 10.3 CPU Interface The FRC, OCRA, OCRB, and ICR are 16-bit registers, but they are connected to an 8-bit data bus. When the CPU accesses these four registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (TEMP). These registers are written and read as follows. * Register Write When the CPU writes to the upper byte, the upper byte of write data is placed in TEMP. Next, when the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP and all 16 bits are written in the register simultaneously. * Register Read When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP. Programs that access these four registers should normally use word access. Equivalently, they may access first the upper byte, then the lower byte. Data will not be transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed. The same considerations apply to access by the DTC. 199 Coding Examples 1. To write the contents of general register R0 to output compare register A in FRT1: MOV.W R0, @H'FF94 2. To read the FRT2 input capture register contents into general register R0: MOV.W @H'FFA8, R0 Figure 10-2 shows the data flow when the FRC is accessed. The other registers are accessed in the same way, except that when OCRA or OCRB is read, the upper and lower bytes are both transferred directly to the CPU without using the temporary register. < Upper byte write> CPU writes data H'AA Module data bus Bus interface TEMP [H'AA] FRC L [ ] FRC H [ ] < Lower byte write > CPU writes data H'55 Module data bus Bus interface TEMP [H'AA] FRC H [H'AA] FRC L [H'55] Figure 10-2 (a) Write Access to FRC (When CPU Writes H'AA55) 200 Figure 10-2 (a) < Upper byte read > CPU reads data H'AA Module data bus Bus interface TEMP [H'55] FRC H [H'AA] FRC L [H'55] < Lower byte read > CPU reads data H'55 Module data bus Bus interface TEMP [H'55] FRC H [ ] FRC L [ ] Figure 10-2 (b) Read Access to FRC (When FRC Contains H'AA55) 10.4 Operation 10.4.1 FRC Incrementation Timing The FRC increments on a pulse generated once for each period of the selected (internal or external) Figure 10-2 (b) clock source. 201 If external clock input is selected, the FRC increments on the rising edge of the clock signal. Figure 10-3 shows the increment timing. The pulse width of the external clock signal must be at least 1.5 o clock periods. The counter will not increment correctly if the pulse width is shorter than 1.5 o clock periods. oO .............. .............. .............. FTCI Minimum FTCI Pulse Width o External clock source FRC clock pulse FRC N N+1 Figure 10-3 Increment Timing for External Clock Input 10.4.2 Output Compare Timing Setting of Output Compare Flags A and B (OCFA and OCFB): The output compare flags are set Figure 10-3 to 1 by an internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just as the FRC increments to a new value. Accordingly, when the FRC and OCR values match, the compare-match signal is not generated until the next period of the clock source. Figure 10-4 shows the timing of the setting of the output compare flags. 202 o FRC N OCR N N+1 Internal comparematch signal OCF Figure 10-4 Setting of Output Compare Flags Output Timing: When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in the TCSR is output at the output compare pin (FTOA or FTOB). Figure 10-5 shows the timing of this operation for compare-match A. o Internal comparematch A signal Figure 10-4 OLVLA FTOA Figure 10-5 Timing of Output Compare A 203 Figure 10-5 FRC Clear Timing: If the CCLRA bit is set to 1, the FRC is cleared when compare-match A occurs. Figure 10-6 shows the timing of this operation. o Internal comparematch A signal FRC N H'0000 Figure 10-6 Clearing of FRC by Compare-Match A 10.4.3 Input Capture Timing Input Capture Timing: An internal input capture signal is generated from the rising or falling edge of the input at the input capture pin (FTI), as selected by the IEDG bit in the TCSR. Figure 10-7 shows the usual input capture timing when the rising edge is selected (IEDG = 1). o Figure 10-6 Input at FTI pin Internal input capture signal Figure 10-7 Input Capture Timing (Usual Case) But if the upper byte of the ICR is being read when the input capture signal arrives, the internal input capture signal is delayed by one state. Figure 10-8 shows the timing for this case. Figure 10-7 204 Read cycle: CPU reads upper byte of ICR T1 T2 T3 o Input at FTI pin Internal input capture signal Figure 10-8 Input Capture Timing (1-State Delay) Timing of Input Capture Flag (ICF) Setting: The input capture flag (ICF) is set to 1 by the internal input capture signal. Figure 10-9 shows the timing of this operation. o Internal input capture signal ICF FRC Figure 10-8 N-1 N N+1 N ICR Figure 10-9 Setting of Input Capture Flag Figure 10-9 205 10.4.4 Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to 1 when the FRC overflows (changes from H'FFFF to H'0000). Figure 10-10 shows the timing of this operation. o FRC H'FFFF H'0000 Internal overflow signal OVF Figure 10-10 Setting of Overflow Flag (OVF) 10.5 CPU Interrupts and DTC Interrupts Figure Each free-running timer channel can request four types of interrupts: input capture10-10 (ICI), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt is requested when the corresponding enable and flag bits are set. Independent signals are sent to the interrupt controller for each type of interrupt. Table 10-3 lists information about these interrupts. Table 10-3 Free-Running Timer Interrupts Interrupt Description DTC Service Available? ICI Requested when ICF is set Yes OCIA Requested when OCFA is set Yes OCIB Requested when OCFB is set Yes FOVI Requested when OVF is set No Priority High Low The ICI, OCIA, and OCIB interrupts can be directed to the data transfer controller (DTC) to have a data transfer performed in place of the usual interrupt-handling routine. When the DTC serves one of these interrupts, it automatically clears the ICF, OCFA, or OCFB flag to 0. See section 6, "Data Transfer Controller", for further information on the DTC. 206 10.6 Synchronization of Free-Running Timers 1 and 2 10.6.1 Synchronization after a Reset The two free-running timer channels are synchronized at a reset and remain synchronized until one of the following conditions is satisfied: * The clock source is changed. * FRC contents are rewritten. * An FRC is cleared. After a reset, each free-running counter operates on the o/4 internal clock source. 10.6.2 Synchronization by Writing to FRCs When synchronization between free-running timers 1 and 2 is lost, it can be restored by writing to the free-running counters. Synchronization on Internal Clock Source: When an internal clock is selected, free-running timers 1 and 2 can be synchronized by writing data to their free-running counters as indicated in table 10-4. Table 10-4 Synchronization by Writing to FRCs Clock Source Write Interval Write Data o/4 4n (states) m (FRC1) o/8 8n (states) m+n (FRC2) o/32 32n (states) m, n: Arbitrary integers After writing these data, synchronization can be checked by reading the two free-running counters at the same interval as the write interval. If the read data have the same relative difference as the write data, the free-running timers are synchronized. Examples of programs for synchronizing the free-running timers are given next. Examples a, b, and c apply when the program is stored in on-chip memory. Examples d, e, and f apply when the program is stored in external memory which is accessed with zero wait states (Tw), assuming that there is no NMI input. 207 Example a: o/4 clock source, 12-state write interval (n = 3), on-chip memory LA: LDC.B #H'FF,BR ; Initialize base register for short-format instruction (MOV:S) LDC.W #H'0700,SR ; Raise interrupt mask level to 7 MOV.W #m,R1 ; Data for free-running timer 1 MOV.W #m+3,R2 ; Data for free-running timer 2 (m + n = m + 3) BSR SET4 ; Call write routine . . . . . . .ALIGN 2 SET4: MOV:S.W R1,@H'92:8 BRN SET4:8 MOV:S.W R2,@H'A2:8 RTS ; Align write instructions (MOV:S) at even address ; Write to FRC 1 (address H'FF92) 9 states ; 2-Byte dummy instruction 3 states ; Write to FRC2 (address H'FFA2) Total 12 states Example b: o/8 clock source, 16-state write interval (n = 2), on-chip memory LB: LDC.B #H'FF,BR LDC.W #H'0700,SR MOV.W #m,R1 MOV.W #m+2,R2 BSR SET8 . . . . . . .ALIGN 2 SET8: MOV:S.W R1,@H'92:8 BRN SET8:8 XCH R1,R1 MOV:S.W R2,@H'A2:8 RTS ; 9 states ; 3 states ; 4 states Total 16 states 208 Example c: o/32 clock source, 32-state write interval (n = 1), on-chip memory LC: LDC.B #H'FF,BR LDC.W #H'0700,SR MOV.W #m,R1 MOV.W #m+1,R2 BSR SET32 . . . . . . .ALIGN 2 SET32: MOV:S.W R1,@H'92:8 BSR WAIT:8 MOV:S.W R2,@H'A2:8 RTS ; Align on even address ; 2 bytes, 9 states ; 2 bytes, 9 states .ALIGN 2 WAIT: NOP XCH R1,R1 RTS ; Align on even address ; 2 states ; 4 states ; 8 states Total 32 states Note: The stack is assumed to be in on-chip RAM. Example d: o/4 clock source, 20-state write interval (n = 5), external memory LD: LDC.B #H'FF,BR LDC.W #H'0700,SR CLR.B @H'F8:8 MOV.W #m,R1 MOV.W #m+5,R2 MOV:S.W R1,@H'92:8 BRN LD:8 MOV:S.W R2,@H'A2:8 ; Set interrupt mask level to 7 ; Disable wait states ; 13 states ; 2 bytes, 7 states 209 Total 20 states Example e: o/8 clock source, 24-state write interval (n = 3), external memory LE: LDC.B #H'FF,BR LDC.W #H'0700,SR CLR.B @H'F8:8 MOV.W #m,R1 MOV.W #m+3,R2 MOV:S.W R1,@H'92:8 ; 13 states BRN LE:8 ; 2 bytes, NOP ; 1 byte, MOV:S.W R2,@H'A2;8 7 states 4 states Total 24 states Example f: o/32 clock source, 32-state write interval (n = 1), external memory LF: LDC.B #H'FF,BR LDC.W #H'0700,SR CLR.B @H'F8:8 MOV.W #m,R1 MOV.W #m+1,R2 MOV:S.W R1,@H'92:8 XCH R0,R0 BRN LF:8 NOP MOV:S.W R2,@H'A2:8 ; External memory, so ; ; 2 bytes, ; 210 13 states 8 states 7 states 4 states Total 32 states Synchronization on External Clock Source: When the external clock source is selected, the freerunning timers can be synchronized by halting their external clock inputs, then writing identical values in their free-running counters. 10.7 Sample Application In the example below, one free-running timer channel is used to generate two square-wave outputs with a 50% duty factor and arbitrary phase relationship. The programming is as follows: 1. The CCLRA bit in the TCSR is set to 1. 2. Each time a compare-match interrupt occurs, software inverts the corresponding output level bit in the TCSR. FRC H'FFFF Clear counter OCRA OCRB H'0000 FTOA pin FTOB pin Figure 10-11 Square-Wave Output (Example) 10.8 Application Notes Application programmers should note that the following types of contention can occur in the free-runFigure 10-11 ning timers. Contention between FRC Write and Clear: If an internal counter clear signal is generated during the T3 state of a write cycle to the lower byte of a free-running counter, the clear signal takes priority and the write is not performed. 211 Figure 10-12 shows this type of contention. Write cycle: CPU write to lower byte of FRC T1 T2 T3 o Internal address bus FRC address Internal write signal FRC clear signal FRC N H'0000 Figure 10-12 FRC Write-Clear Contention Contention between FRC Write and Increment: If an FRC increment pulse is generated during the T3 state of a write cycle to the lower byte of a free-running counter, the write takes priority and the FRC is not incremented. Figure 10-12 212 Figure 10-13 shows this type of contention. Write cycle: CPU write to lower byte of FRC T1 T2 T3 o Internal address bus FRC address Internal write signal FRC clock pulse FRC N M Write data Figure 10-13 FRC Write-Increment Contention Figure 10-13 213 Contention between OCR Write and Compare-Match: If a compare-match occurs during the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes precedence and the compare-match signal is inhibited. Figure 10-14 shows this type of contention. Write cycle: CPU write to lower byte of OCRA or OCRB T1 T2 T3 o Internal address bus OCRA or OCRB address Internal write signal FRC N N+1 OCRA or OCRB N M Write data Compare-match A or B signal Inhibited Figure 10-14 Contention between OCR Write and Compare-Match Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause the FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 10-5. Figure 10-14 The pulse that increments the FRC is generated at the falling edge of the internal clock source. If clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 10-5, the changeover generates a falling edge that triggers the FRC increment pulse. Switching between an internal and external clock source can also cause the FRC to increment. 214 Table 10-5 Effect of Changing Internal Clock Sources No. Description 1 Low Low: CKS1 and CKS0 are Timing Chart Old clock source rewritten while both clock sources are low. New clock source FRC clock pulse FRC N N +1 CKS rewrite 2 Low High: CKS1 and CKS0 are Old clock source rewritten while old clock source is low and new clock source is high. New clock source FRC clock pulse N FRC N +1 N +2 CKS rewrite 3 High Low: CKS1 and CKS0 are Old clock source Table 10-5 No. 1 rewritten while old clock source is high and New clock source new clock source is low. * FRC clock pulse FRC N N+1 Table 10-5 No. 2 N+2 CKS rewrite Note: * The switching of clock sources is regarded as a falling edge that increments the FRC. 215 Table 10-5 No. 3 Table 10-5 Effect of Changing Internal Clock Sources (cont) No. Description 4 High High: CKS1 and CKS0 are Timing Chart Old clock source rewritten while both clock sources are high. New clock source FRC clock pulse FRC N N+1 N+2 CKS rewrite Table 10-5 No. 4 216 Section 11 8-Bit Timer 11.1 Overview The H8/520 chip includes a single 8-bit timer based on an 8-bit counter (TCNT). The timer has two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare-match events. One application of the 8-bit timer is to generate a rectangular-wave output with an arbitrary duty factor. 11.1.1 Features The features of the 8-bit timer are listed below. * Selection of four clock sources The counter can be driven by an internal clock signal (o/8, o/64, or o/1024) or an external clock input (enabling use as an external event counter). * Selection of three ways to clear the counter The counter can be cleared on compare-match A or B, or by an external reset signal. * Timer output controlled by two compare-match signals The single timer output (TMO) is controlled by two independent compare-match signals, enabling the timer to generate output waveforms with an arbitrary duty factor. * Three types of interrupts Compare-match A and B and overflow interrupts can be requested independently. The compare match interrupts can be served by the data transfer controller (DTC), enabling interrupt-driven data transfer with minimal CPU programming. 217 11.1.2 Block Diagram Figure 11-1 shows a block diagram of the 8-bit timer. External clock Internal clocks o/8 o/64 TMCI o/1024 Clock Clock select TCORA Compare-match A Comparator A TMO TMRI Bus interface Overflow TCNT Clear Control Control logic logic Comparator B Compare-match B TCORB TCSR TCR CMIA CMIB OVI Interrupt signals TCORA: TCORB: TCNT: TCSR: TCR: Time Constant Register A Time Constant Register B Timer Counter Timer Control/Status Register Timer Control Register Figure 11-1 Block Diagram of 8-Bit Timer 218 Figure 11-1 Module data bus Internal data bus 11.1.3 Input and Output Pins Table 11-1 lists the input and output pins of the 8-bit timer. Table 11-1 Input and Output Pins of 8-Bit Timer Name Abbreviation I/O Function Timer output TMO Output Output controlled by compare-match Timer clock input TMCI Input External clock source for the counter Timer reset input TMRI Input External reset signal for the counter 11.1.4 Register Configuration Table 11-2 lists the registers of the 8-bit timer. Table 11-2 8-Bit Timer Registers Name Abbreviation R/W Initial Value Address Timer control register TCR R/W H'00 H'FFD0 Timer control/status register TCSR R/(W)* H'10 H'FFD1 Timer constant register A TCORA R/W H'FF H'FFD2 Timer constant register B TCORB R/W H'FF H'FFD3 Timer counter TCNT R/W H'00 H'FFD4 Note: * Software can write a 0 to clear bits 7 to 5, but cannot write a 1 in these bits. 11.2 Register Descriptions 11.2.1 Timer Counter (TCNT)--H'FFD4 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from one of four clock sources. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer control register (TCR). The CPU can always read or write the timer counter. 219 The timer counter can be cleared by an external reset input or by an internal compare-match signal generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer control register select the method of clearing. When the timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. The timer counter is initialized to H'00 at a reset and in the standby modes. 11.2.2 Time Constant Registers A and B (TCORA and TCORB)--H'FFD2 and H'FFD3 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually compared with the constants written in these registers. When a match is detected, the corresponding comparematch flag (CMFA or CMFB) is set in the timer control/status register (TCSR). The timer output signal (TMO) is controlled by these compare-match signals as specified by output select bits 3 to 0 (OS3 to OS0) in the timer status/control register (TCSR). TCORA and TCORB are initialized to H'FF at a reset and in the standby modes. 11.2.3 Timer Control Register (TCR)--H'FFD0 Bit 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The TCR is an 8-bit readable/writable register that selects the clock source and the time at which the timer counter is cleared, and enables interrupts. The TCR is initialized to H'00 at a reset and in the standby modes. 220 Bit 7--Compare-Match Interrupt Enable B (CMIEB): This bit selects whether to request comparematch interrupt B (CMIB) when compare-match flag B (CMFB) in the timer status/control register (TCSR) is set to 1. Bit 7 CMIEB Description 0 Compare-match interrupt request B (CMIB) is disabled. 1 Compare-match interrupt request B (CMIB) is enabled. (Initial value) Bit 6--Compare-Match Interrupt Enable A (CMIEA): This bit selects whether to request compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in the timer status/control register (TCSR) is set to 1. Bit 6 CMIEA Description 0 Compare-match interrupt request A (CMIA) is disabled. 1 Compare-match interrupt request A (CMIA) is enabled. (Initial value) Bit 5--Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer overflow interrupt (OVI) when the overflow flag (OVF) in the timer status/control register (TCSR) is set to 1. Bit 5 OVIE Description 0 The timer overflow interrupt request (OVI) is disabled. 1 The timer overflow interrupt request (OVI) is enabled. (Initial value) Bits 4 and 3--Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer counter is cleared: by compare-match A or B or by an external reset input. Bit 4 Bit 3 CCLR1 CCLR0 Description 0 0 Not cleared. 0 1 Cleared on compare-match A. 1 0 Cleared on compare-match B. 1 1 Cleared on rising edge of external reset input signal. (Initial value) 221 Bits 2, 1, and 0--Clock Select (CKS2, CKS1, and CKS0): These bits select the internal or external clock source for the timer counter. For the external clock source they select whether to increment the count on the rising or falling edge of the clock input, or on both edges. Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Description 0 0 0 No clock source (timer stopped). 0 0 1 Internal clock source (o/8). 0 1 0 Internal clock source (o/64). 0 1 1 Internal clock source (o/1024). 1 0 0 No clock source (timer stopped). 1 0 1 External clock source, counted on the rising edge. 1 1 0 External clock source, counted on the falling edge. 1 1 1 External clock source, counted on both the rising (Initial value) and falling edges. 11.2.4 Timer Control/Status Register (TCSR) Bit 7 6 5 4 3 2 1 0 CMFB CMFA OVF -- OS3 OS2 OS1 OS0 Initial value 0 0 0 1 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* -- R/W R/W R/W R/W The TCSR is an 8-bit readable and partially writable* register that indicates compare-match and overflow status and selects the effect of compare-match events on the timer output signal (TMO). The TCSR is initialized to H'10 at a reset and in the standby modes. Note: * Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. Bit 7--Compare-Match Flag B (CMFB): This status flag is set to 1 when the timer count matches the time constant set in TCORB. 222 Bit 7 CMFB Description 0 This bit is cleared from 1 to 0 when: 1 (Initial value) 1. The CPU reads the CMFB bit after the CMFB bit has been set to 1, then writes a 0 in this bit. 2. Compare-match interrupt B is served by the data transfer controller (DTC). This bit is set to 1 when TCNT = TCORB. Bit 6--Compare-Match Flag A (CMFA): This status flag is set to 1 when the timer count matches the time constant set in TCORA. Bit 6 CMFA Description 0 This bit is cleared from 1 to 0 when: 1 (Initial value) 1. The CPU reads the CMFA bit after the CMFA bit has been set to 1, then writes a 0 in this bit. 2. Compare-match interrupt A is served by the data transfer controller (DTC). This bit is set to 1 when TCNT = TCORA. Bit 5--Timer Overflow Flag (OVF): This status flag is set to 1 when the timer count overflows (changes from H'FF to H'00). Bit 5 OVF Description 0 This bit is cleared from 1 to 0 when the CPU reads (Initial value) the OVF bit after the OVF bit has been set to 1, then writes a 0 in this bit. 1 This bit is set to 1 when TCNT changes from H'FF to H'00. Bit 4--Reserved: This bit cannot be modified and is always read as 1. Bits 3 to 0--Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of compare-match events on the timer output signal (TMO). Bits OS3 and OS2 control the effect of compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on the output level. When all four output select bits are cleared to 0 the TMO signal is not output. After a reset, the TMO output is low (0) until the first compare-match event. 223 Bit 3 Bit 2 OS3 OS2 Description 0 0 No change when compare-match B occurs. 0 1 Output changes to 0 when compare-match B occurs. 1 0 Output changes to 1 when compare-match B occurs. 1 1 Output inverts (toggles) when compare-match B occurs. Bit 1 Bit 0 OS1 OS0 Description 0 0 No change when compare-match A occurs. 0 1 Output changes to 0 when compare-match A occurs. 1 0 Output changes to 1 when compare-match A occurs. 1 1 Output inverts (toggles) when compare-match A occurs. (Initial value) (Initial value) 11.3 Operation 11.3.1 TCNT Incrementation Timing The timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source. If external clock input (TMCI) is selected, the timer counter can increment on the rising edge, the falling edge, or both edges of the external clock signal. The external clock pulse width must be at least 1.5 o clock periods for incrementation on a single edge, and at least 2.5 o clock periods for incrementation on both edges. The counter will not increment correctly if the pulse width is shorter than these values. 224 o TMCI Minimum TMCI Pulse Width (Single-Edge Incrementation) o TMCI Minimum TMCI Pulse Width (Double-Edge Incrementation) Figure 11-2 shows the timing of incrementation on both edges of an external clock signal. o External clock source Figure 11-2 Upper TCNT clock pulse TCNT N-1 N Figure 11-2 Count Timing for External Clock Input Figure 11-2 225 N+1 11.3.2 Compare Match Timing Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are set to 1 by an internal compare-match signal generated when the timer count matches the time constant in TCORA or TCORB. The compare-match signal is generated at the last state in which the match is true, just as the timer counter increments to a new value. Accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. Figure 11-3 shows the timing of the setting of the compare-match flags. o TCNT N TCOR N N+1 Internal compare-match signal CMF Figure 11-3 Setting of Compare-Match Flags Output Timing: When a compare-match event occurs, the timer output (TMO) changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits, the output can remain Figure 11-3 the same, change to 0, change to 1, or toggle. 226 Figure 11-4 shows the timing when the output is set to toggle on compare-match A. o Internal compare-match A signal Timer output (TMO) Figure 11-4 Timing of Timer Output Timing of Compare-Match Clear Depending on the CCLR1 and CCLR0 bits in the TCR, the timer counter can be cleared when compare-match A or B occurs. Figure 11-5 shows the timing of this operation. Figure 11-4 o Internal compare-match signal TCNT N H'00 Figure 11-5 Timing of Compare-Match Clear 11.3.3 External Reset of TCNT When the CCLR1 and CCLR0 bits in the TCR are both set to 1, the timer counter is cleared on the rising edge of an external reset input (TMRI). To ensure resetting, the TMRI pulse width must be at least 1.5 o clock periods. Figure 11-6 shows the timing of this operation. Figure 11-5 227 o External reset input (TMRI) Internal clear pulse N-1 TCNT N H'00 Figure 11-6 Timing of External Reset 11.3.4 Setting of TCNT Overflow Flag The overflow flag (OVF) is set to 1 when the timer count overflows (changes from11-6 H'FF to H'00). Figure Figure 11-7 shows the timing of this operation. o TCNT H'FF H'00 Internal overflow signal OVF Figure 11-7 Setting of Overflow Flag (OVF) Figure 11-7 228 11.4 CPU Interrupts and DTC Interrupts The 8-bit timer can generate three types of interrupts: compare-match A and B (CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding enable and flag bits are set in the TCR and TCSR. Independent signals are sent to the interrupt controller for each type of interrupt. Table 11-3 lists information about these interrupts. Table 11-3 8-Bit Timer Interrupts Interrupt Description DTC Service Available? Priority CMIA Requested when CMFA is set Yes High CMIB Requested when CMFB is set Yes OVI Requested when OVF is set No Low The CMIA and CMIB interrupts can be served by the data transfer controller (DTC) to have a data transfer performed. When the DTC serves one of these interrupts, it automatically clears the CMFA or CMFB flag to 0. See section 6, "Data Transfer Controller", for further information on the DTC. 229 11.5 Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty factor. The control bits are set as follows: 1. In the TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. 2. In the TCSR, bits OS3 to OS0 are set to 0110, causing the output to change to 1 on compare-match A and to 0 on compare-match B. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required. H'FF TCNT Clear counter TCORA TCORB H'00 TMO pin Figure 11-8 Example of Pulse Output Figure 11-8 230 11.6 Application Notes Application programmers should note that the following types of contention can occur in the 8-bit timer. Contention between TCNT Write and Clear: If an internal counter clear signal is generated during the T3 state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed. Figure 11-9 shows this type of contention. Write cycle: CPU writes to TCNT T1 T2 T3 o Internal address bus TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 11-9 TCNT Write-Clear Contention Figure 11-9 231 Contention between TCNT Write and Increment: If a timer counter increment pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. Figure 11-10 shows this type of contention. Write cycle: CPU writes to TCNT T1 T2 T3 o Internal address bus TCNT address Internal write signal TCNT clock pulse TCNT N M Write data Figure 11-10 TCNT Write-Increment Contention Figure 11-10 232 Contention between TCOR Write and Compare-Match: If a compare-match occurs during the T3 state of a write cycle to TCORA or TCORB, the write takes precedence and the compare-match signal is inhibited. Figure 11-11 shows this type of contention. Write cycle: CPU writes to TCORA or TCORB T1 T2 T3 o Internal address bus TCOR address Internal write signal TCNT N TCORA or TCORB N N+1 M TCOR write data Compare-match A or B signal Inhibited Figure 11-11 Contention between TCOR Write and Compare-Match Contention between Compare-Match A and Compare-Match B: If identical time constants are written in TCORA and TCORB, causing compare-match A and B to occur simultaneously, any conflict between the output selections for compare-match A and B is resolved by following the priority order in table 11-4. Figure 11-11 233 Table 11-4 Priority Order of Timer Output Output Selection Priority Toggle High 1 Output 0 Output No change Low Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause the timer counter to increment. This depends on the time at which the clock select bits (CKS2 to CKS0) are rewritten, as shown in table 11-5. The pulse that increments the timer counter is generated at the falling edge of the internal clock source signal. If clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 11-5, the changeover generates a falling edge that triggers the TCNT clock pulse and increments the timer counter. Switching between an internal and external clock source can also cause the timer counter to increment. Table 11-5 Effect of Changing Internal Clock Sources No. Description 1 Low Low*: CKS1 and CKS0 are rewritten while both Timing Chart Old clock source clock sources are low. New clock source TCNT clock pulse TCNT N+1 N CKS rewrite Note: * Including a transition from low to the stopped state (CKS1 = 0, CKS0 = 0), or a transition from the stopped state to low. 234 Table 11-5 Effect of Changing Internal Clock Sources (cont) No. Description 2 Low High*1: Timing Chart CKS1 and CKS0 are rewritten while old Old clock source clock source is low and new clock source is high. New clock source TCNT clock pulse TCNT N N+1 N+2 CKS rewrite 3 High Low*2: CKS1 and CKS0 are rewritten while old Old clock source clock source is high and new clock source is low. New clock source Table 11-5 No. 2 *3 TCNT clock pulse TCNT N N+1 N+2 CKS rewrite Notes: 1. Including a transition from the stopped state to high. 2. Including a transition from high to the stopped state. 3. The switching of clock sources is regarded as a falling edge that increments the TCNT. Table 11-5 No. 3 235 Table 11-5 Effect of Changing Internal Clock Sources (cont) No. Description 4 High High: Timing Chart CKS1 and CKS0 are rewritten while both Old clock source clock sources are high. New clock source TCNT clock pulse TCNT N N+1 N+2 CKS rewrite Table 11-5 No. 4 236 Section 12 Watchdog Timer 12.1 Overview The H8/520 has an on-chip watchdog timer (WDT) module. This module can monitor system operation by generating a signal that resets the H8/520 chip if a system crash allows the timer count to overflow. When this watchdog function is not needed, the WDT module can be used as an interval timer. In the interval timer mode, an IRQ0 interrupt is requested at each counter overflow. The WDT module is also used in recovering from the software standby mode. 12.1.1 Features The basic features of the watchdog timer module are summarized as follows: * Selection of eight clock sources * Selection of two modes: watchdog timer mode and interval timer mode * Counter overflow generates a reset signal or interrupt request Reset signal in the watchdog timer mode; IRQ0 request in the interval timer mode. * External output of reset signal Depending on a reset output enable bit, the reset signal can be output externally to reset devices controlled by the H8/520, as well as the H8/520 itself. 237 12.1.2 Block Diagram Figure 12-1 is a block diagram of the watchdog timer. Overflow Interrupt signals TCNT Interrupt control Read/ write control IRQ 0 (Interval timer mode) Internal data bus TCSR Internal clock sources RSTCSR o/2 o/32 Clock o/64 Reset control Clock select Reset signal (internal, external) o/128 o/256 o/512 o/2048 o/4096 TNCT: Timer Counter TSCR: Timer Control/Status Register RSTCSR: Reset Control/Status Register Figure 12-1 Block Diagram of Timer Counter Figure 12-1 238 12.1.3 Register Configuration Table 12-1 lists information on the watchdog timer registers. Table 12-1 Register Configuration Initial Addresses Name Abbreviation R/W value Write Read Timer control/status register TCSR R/(W)* H'18 H'FFEC H'FFEC Timer counter TCNT R/W H'00 H'FFEC H'FFED Reset control/status register RSTCSR R/(W)* H'3F H'FFFE H'FFFF Note: * Software can write a 0 to clear bit 7, but cannot write a 1. 12.2 Register Descriptions 12.2.1 Timer Counter (TCNT)--H'FFED Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The watchdog timer counter (TCNT) is a readable/writable* 8-bit up-counter. When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in the TCSR. When the count overflows (changes from H'FF to H'00), a reset or interrupt signal is generated. The watchdog timer counter is initialized to H'00 at a reset and when the TME bit is cleared to 0. Note: * TCNT is write-protected by a password. See section 12.2.4, "Notes on Register Access", for details. 239 12.2.2 Timer Control/Status Register (TCSR)--H'FFEC (Read), H'FFED (Write) Bit 7 6 5 4 3 2 1 0 OVF WT/IT TME -- -- CKS2 CKS1 CKS0 Initial value 0 0 0 1 1 0 0 0 Read/Write R/W*1 R/W R/W -- -- R/W R/W R/W The watchdog timer control/status register (TCSR) is an 8-bit readable/writable*2 register that selects the timer mode and clock source and performs other functions. Bits 7 to 5 are initialized to 0 at a reset and in the standby modes. Bits 2 to 0 are initialized to 0 at a reset, but retain their values in the software standby mode. Notes: 1. Software can write a 0 in bit 7 to clear the flag, but cannot set this bit to 1. 2. The TCSR is write-protected by a password. See section 12.2.4, "Notes on Register Access", for details. Bit 7--Overflow Flag (OVF): This bit indicates that the watchdog timer count has overflowed. Bit 7 OVF Description 0 To clear this bit, the CPU must read this bit after it has been set to 1, (Initial value) then write a 0 in this bit. 1 This bit is set to 1 when TCNT changes from H'FF to H'00.* Note: * The OVF bit is not set in the watchdog timer mode. Bit 6--Timer Mode Select (WT/IT): This bit selects whether to operate in the watchdog timer mode or interval timer mode. If the watchdog timer mode is selected, a watchdog timer overflow resets the chip. If the interval timer mode is selected, a watchdog timer overflow generates an IRQ0 interrupt request. Bit 6 WT/IT Description 0 Interval timer mode (IRQ0 request) 1 Watchdog timer mode (Reset) (Initial value) 240 Bit 5--Timer Enable (TME): This bit enables or disables the timer. Bit 5 TME Description 0 TCNT is initialized to H'00 and stopped. 1 TCNT runs. A reset or interrupt is requested when the count overflows. (Initial value) Bits 4 and 3--Reserved: These bits cannot be modified and are always read as 1. Bits 2, 1, and 0--Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight clock sources obtained by dividing the system clock (o). The overflow interval listed in the table below is the time from when the watchdog timer counter begins counting from H'00 until an overflow occurs. In the interval timer mode, IRQ0 interrupts are requested at this interval. Bit 2 Bit 1 Bit 0 Description CKS2 CKS1 CKS0 Clock Source Overflow Interval (o = 10 MHz) 0 0 0 o/2 51.2 s 0 0 1 o/32 819.2 s 0 1 0 o/64 1.6 ms 0 1 1 o/128 3.3 ms 1 0 0 o/256 6.6 ms 1 0 1 o/512 13.1 ms 1 1 0 o/2048 52.4 ms 1 1 1 o/4096 104.9 ms (Initial value) 12.2.3 Reset Control/Status Register (RSTCSR)--H'FFFF (Read), H'FFFE (Write) Bit 7 6 5 4 3 2 1 0 WRST RSTOE -- -- -- -- -- -- Initial value 0 0 1 1 1 1 1 1 Read/Write R/(W)*1 R/W -- -- -- -- -- -- The reset control/status register (RSTCSR) is an 8-bit readable/writable*2 register that indicates when a reset has been caused by a watchdog timer overflow, and controls external output of the reset signal. 241 Bit 6 is not initialized by the reset caused by the watchdog timer overflow. It is initialized, however, by a reset caused by input at the RES pin. Notes: 1. Software can write a 0 in bit 7 to clear the flag, but cannot set this bit to 1. 2. The RSTCSR is write-protected by a password. See section 12.2.4, "Notes on Register Access", for details. Bit 7--Watchdog Timer Reset (WRST): This bit indicates that a reset signal has been generated by a watchdog timer overflow in the watchdog timer mode. The reset signal generated by the overflow resets the entire H8/520 chip. In addition, if the reset output enable (RSTOE) bit is set to 1, a reset signal (low) is ouput at the RES pin to reset devices connected to the H8/520. The WRST bit can be cleared by software by writing a 0. It is also cleared when a reset signal from an external device is received at the RES pin. Bit 7 WRST Description 0 This bit is cleared to 0 by a reset signal input from the RES pin, (Initial state) or when software writes a 0. 1 This bit is set to 1 when the watchdog timer overflows in the watchdog timer mode and an internal reset signal is generated. Bit 6--Reset Output Enable (RSTOE): This bit selects whether to output a reset signal from the RST pin when the timer counter overflows in the watchdog timer mode. Bit 6 RSTOE Description 0 The reset signal generated by a watchdog timer overflow is not (Initial state) output to external devices. 1 The reset signal generated by a watchdog timer overflow is output to external devices. Bits 5 to 0--Reserved: These bits cannot be modified and are always read as 1. 12.2.4 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write. The procedures for writing and reading these registers are given below. 242 Writing to TCNT and TCSR: These registers must be written by word access. Programs cannot write to them by byte access. The word must contain the write data and a password. The watchdog timer's TCNT and TCSR registers both have the same write address. The write data must be contained in the lower byte of the word written at this address. The upper byte must contain H'5A (password for TCNT) or H'A5 (password for TCSR). See figure 12-2. The result of the access depicted in figure 12-2 is to transfer the write data from the lower byte to the TCNT or TCSR. 15 Write to TCNT Address: H'FFEC 8 7 H'5A 15 Write to TCSR Address: H'FFEC 0 Write data 8 7 H'A5 0 Write data Figure 12-2 Writing to TCNT and TCSR Coding Examples: To clear TCNT to 00: To write H'4F in TCSR: MOV.W #H'5A00, @H'FFEC MOV.W #H'A54F, @H'FFEC Writing to RSTCSR: The RSTCSR must be written by moving word data to address H'FFFE. It cannot be written by byte access. The upper byte of the word must contain a password. Separate passwords are used for clearing the WRST bit and for writing a 1 or 0 to the RSTOE bit. To clear the WRST bit, the word written at address H'FFFE must contain the password H'A5 in the upper byte and the data H'00 in the lower byte. This clears the WRST bit to 0 without affecting other bits. To set or clear the RSTOE bit, the word written at address H'FFFE must contain the password H'5A in the upper byte and the write data in the lower byte. This writes the desired data in the RSTOE bit without affecting other bits. These write operations are illustrated in figure 12-3. 243 To write 0 to the WRST bit 15 Address: H'FFFE H'A5 To write to the RSTOE bit Address: H'FFFE 8 7 15 0 H'00 8 7 H'5A 0 Write data Figure 12-3 Writing to RSTCSR Coding Examples: To clear WRST to 0: To set RSTOE to 1: MOV.W #H'A500, @H'FFFE MOV.W #H'5AFF, @H'FFFE Reading TCNT, TCSR, and RSTCSR: The read addresses are H'FFEC for TCSR, H'FFED for TCNT, and H'FFFF for RSTCSR as indicated in table 12-2. These three registers are read like other registers. Byte access instructions can be used. Table 12-2 Read Addresses of TCNT and TCSR Read Address Register H'FFEC TCSR H'FFED TCNT H'FFFF RSTCSR 12.3 Operation 12.3.1 Watchdog Timer Mode The watchdog timer function begins operating when software sets the WT/IT and TME bits to 1 in the TCSR. Thereafter, software should periodically rewrite the contents of the timer counter (normally by writing H'00) to prevent the count from overflowing. If a program crash allows the timer count to overflow, the watchdog timer generates a reset as shown in figure 12-4. The reset signal from the watchdog timer can also be output from the RES pin to reset external devices. This reset output signal is a low pulse with a duration of 132 o clock periods. The reset signal is output only if the RSTOE bit in the TCSR is set to 1. 244 The reset signal from the watchdog timer has the same vector as a reset generated by low input at the RES pin. Software should check the WRST bit in the RSTCSR to determine the source of the reset. If a watchdog timer overflow occurs at the same time as a low input at the RES pin, priority is given to one type of reset or the other depending on the value of the RSTOE bit in the RSTCSR. If the RSTOE bit is set to 1 when both types of reset occur simultaneously, the watchdog timer's reset signal takes precedence. The internal state of the H8/520 chip is reset, the RSTOE bit remains set to 1, the WRST bit is also set to 1, and the RES pin is held low for 132 o clock periods. If at the end of 520 o clock periods there is still an external low input to the RES pin, the external reset takes effect, clearing the WRST and RSTOE bits to 0. Note that if the external reset occurs before the watchdog timer overflows, it takes effect immediately and clears the RSTOE bit. If the RSTOE bit is cleared to 0 when both types of reset occur simultaneoualy, the reset signal input from the RES pin takes precedence and the WRST bit is cleared to 0. Watchdog timer overflow H'FF TCNT count H'00 OVF = 1 Start H'00 written to TCNT Reset Start Internal reset signal External reset signal * (RES) Note: The external reset signal is output for 132 system clock (o) cycles. The internal reset signal lasts for 520 system clock (o) cycles. Figure 12-4 Operation in Watchdog Timer Mode 245 H'00 written to TCNT 12.3.2 Interval Timer Mode Interval timer operation begins when the WT/IT bit is cleared to 0 and the TME bit is set to 1. In the interval timer mode, an IRQ0 request is generated each time the timer count overflows. This function can be used to generate IRQ0 requests at regular intervals. See figure 12-5. IRQ0 requests from the watchdog timer module have the same vector as IRQ0 requests from the IRQ0 pin, so the IRQ0 interrupt-handling routine must check the OVF bit in the TCSR to determine the source of the interrupt. H'FF TCNT count Time t H'00 WR/IT = 0 TME = 1 IRQ 0 request IRQ 0 request IRQ 0 request IRQ 0 request IRQ 0 request Figure 12-5 Operation in Interval Timer Mode 12.3.3 Operation in Software Standby Mode Figuremode. 12-5Specific watchdog timer setThe watchdog timer has a special function in the software standby tings are required when the software standby mode is used. Before Transition to the Software Standby Mode: The TME bit must be cleared to 0 to stop the watchdog timer counter before a transition to the software standby mode. The chip cannot enter the software standby mode while the TME bit is set to 1. Before entering the software standby mode, software should also set the clock select bits (CKS2 to CKS0) to a value that makes the timer overflow interval equal to or greater than the settling time of the clock oscillator. Recovery from the Software Standby Mode: Recovery from the software standby mode can be triggered by an NMI request. In this case the recovery proceeds as follows: 246 When an NMI request signal is received, the clock oscillator starts running and the watchdog timer starts counting at the rate selected by the clock select bits before the software standby mode was entered. When the count overflows from H'FF to H'00, the o clock is presumed to be stable and usable, clock signals are supplied to all modules on the chip, and the NMI interrupt-handling routine starts executing. 12.3.4 Setting of Overflow Flag The OVF bit is set to 1 when the timer count overflows in the interval timer mode. Simultaneously, the WDT module requests an IRQ0 interrupt. The timing is shown in figure 12-6. o TCNT H'FF H'00 Internal overflow signal OVF Figure 12-6 Setting of OVF Bit Figure 12-6 247 12.3.5 Setting of Watchdog Timer Reset (WRST) Bit The WRST bit is valid when WT/IT = 1 and TME = 1. The WRST bit is set to 1 when the timer count overflows. An internal reset signal is simultaneously generated for the entire H8/520 chip. The timing is shown in figure 12-7. o H'FF TCNT H'00 Overflow signal WRST Internal reset signal Figure 12-7 Setting of WRST Bit and Internal Reset Signal 12.4 Application Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. See figure 12-8. Figure12-7 248 Write cycle: CPU writes to TCNT T1 T2 T3 o Internal address bus TCNT address Internal write signal TCNT clock pulse TCNT N M Write data Figure 12-8 TCNT Write-Increment Contention Changing the Clock Select Bits (CKS2 to CKS0): Software should stop the watchdog timer (by clearing the TME bit to 0) before changing the value of the clock select bits. If the clock select bits are modified while the watchdog timer is running, the timer count may be incremented incorrectly. Figure 12-8 249 Section 13 Serial Communication Interface 13.1 Overview The H8/520 chip includes a two-channel serial communication interface (SCI) for transferring serial data to and from other chips. The two channels are independent but are functionally identical. Synchronous and asynchronous data transfer are supported on both channels. 13.1.1 Features The features of the on-chip serial communication interface are as follows: * Selection of asynchronous or synchronous mode -Asynchronous mode The SCI can communicate with a UART (Universal Asynchronous Receiver/Transmitter), ACIA (Asynchronous Communication Interface Adapter), or other chip that employs standard asynchronous serial communication. Eight data formats are available. - Data length: 7 or 8 bits - Stop bit length: 1 or 2 bits - Parity: Even, odd, or none - Error detection: Parity, overrun, and framing errors -Synchronous mode The SCI can communicate with chips able to synchronize data transfers with clock pulses. - Data length: 8 bits - Error detection: Overrun errors * Full duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both the transmit and receive sections use double buffering, so continuous data transfer is possible in either direction. * Built-in baud rate generator Any specified baud rate can be generated. * Internal or external clock source The baud rate generator can operate on an internal clock source, or an external clock signal input at the SCK pin. * Three interrupts Transmit-end, receive-end, and receive-error interrupts are requested independently. The transmitend and receive-end interrupts can be served by the on-chip data transfer controller (DTC), providing a convenient way to transfer data with minimal CPU programming. 251 13.1.2 Block Diagram Bus interface Figure 13-1 shows a block diagram of one serial communication interface channel. Module data bus RDR TDR SSR Internal clock source o BRR SCR RSR o/4 Baud-rate generator SMR RXD TSR o/16 Communication control TXD Internal data bus o/64 Parity generator Clock Parity check External clock SCK TXI RDR: RSR: TDR: TSR: SSR: SCR: SMR: BRR: RXI Receive Data Register Receive Shift Register Transmit Data Register Transmit Shift Register Serial Status Register Serial Control Register Serial Mode Register Bit Rate Register ERI Interrupt signals Figure 13-1 Block Diagram of Serial Communication Interface Figure 13-1 252 13.1.3 Input and Output Pins Table 13-1 lists the input and output pins used by the SCI module. Table 13-1 SCI Input/Output Pins Channel Name Abbreviation I/O Function 1 Serial clock SCK1 Input/output Serial clock input and output for channel 1 Receive data RXD1 Input Receive data input for channel 1 Transmit data TXD1 Output Transmit data output for channel 1 Serial clock SCK2 Input/output Serial clock input and output for channel 2 Receive data RXD2 Input Receive data input for channel 2 Transmit data TXD2 Output Transmit data output for channel 2 2 13.1.4 Register Configuration Table 13-2 lists the SCI registers. These registers specify the communication mode (synchronous or asynchronous), data format, and bit rate, and control the transmit and receive sections. Table 13-2 SCI Registers Channel Name Abbreviation R/W Initial Value Address 1 Receive shift register RSR -- -- -- Receive data register RDR R H'00 H'FFDD Transmit shift register TSR -- -- -- Transmit data register TDR R/W H'FF H'FFDB Serial mode register SMR R/W H'04 H'FFD8 Serial control register SCR R/W H'0C H'FFDA Serial status register SSR R/(W)* H'87 H'FFDC Bit rate register BRR R/W H'FF H'FFD9 Receive shift register RSR -- -- -- Receive data register RDR R H'00 H'FFC5 Transmit shift register TSR -- -- -- Transmit data register TDR R/W H'FF H'FFC3 Serial mode register SMR R/W H'04 H'FFC0 Serial control register SCR R/W H'0C H'FFC2 Serial status register SSR R/(W)* H'87 H'FFC4 Bit rate register BRR R/W H'FF H'FFC1 2 Note: * Software can write a 0 to clear the status flag bits, but cannot write a 1. 253 13.2 Register Descriptions 13.2.1 Receive Shift Register (RSR) Bit 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- The RSR receives incoming data bits. When one character (one byte) has been received, it is transferred to the receive data register (RDR). The CPU cannot read or write the RSR directly. 13.2.2 Receive Data Register (RDR)--H'FFDD (Channel 1), H'FFC5 (Channel 2) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R The RDR stores received data. As each character is received, it is transferred from the RSR to the RDR, enabling the RSR to receive the next character. This double-buffering allows the SCI to receive data continuously. The CPU can read but not write the RDR. The RDR is initialized to H'00 at a reset and in the standby modes. 13.2.3 Transmit Shift Register (TSR) Bit 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- The TSR holds the character currently being transmitted. When transmission of this character is completed, the next character is moved from the transmit data register (TDR) to the TSR and transmission of that character begins. If the TDR does not contain valid data, the SCI stops transmitting. The CPU cannot read or write the TSR directly. 254 13.2.4 Transmit Data Register (TDR)--H'FFDB (Channel 1), H'FFC3 (Channel 2) Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The TDR is an 8-bit readable/writable register that holds the next character to be transmitted. When the TSR becomes empty, the character written in the TDR is transferred to the TSR. Continuous data transmission is possible by writing the next byte in the TDR while the current byte is being transmitted from the TSR. The TDR is initialized to H'FF at a reset and in the standby modes. 13.2.5 Serial Mode Register (SMR)--H'FFD8 (Channel 1), H'FFC0 (Channel 2) Bit 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP -- CKS1 CKS0 Initial value 0 0 0 0 0 1 0 0 Read/Write R/W R/W R/W R/W R/W -- R/W R/W The SMR is an 8-bit readable/writable register that controls the communication format and selects the clock rate for the internal clock source. It is initialized to H'04 at a reset and in the standby modes. Bit 7--Communication Mode (C/A): This bit selects the asynchronous or synchronous communication mode. Bit 7 C/A Description 0 Asynchronous communication. 1 Communication is synchronized with the serial clock. (Initial value) Bit 6--Character Length (CHR): This bit selects the character length in asynchronous mode. It is ignored in synchronous mode. 255 Bit 6 CHR Description 0 8 bits per character. 1 7 bits per character. (Initial value) Bit 5--Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode. It is ignored in synchronous mode. Bit 5 PE Description 0 Transmit: No parity bit is added. (Initial value) Receive: Parity is not checked. 1 Transmit: A parity bit is added. Receive: Parity is checked. Bit 4--Parity Mode (O/E): In asynchronous mode, when parity is enabled (PE = 1), this bit selects even or odd parity. Even parity means that a parity bit is added to the data bits for each character to make the total number of 1s even. Odd parity means that the total number of 1s is made odd. This bit is ignored when PE = 0 and in the synchronous mode. Bit 4 O/E Description 0 Even parity. 1 Odd parity. (Initial value) Bit 3--Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in the synchronous mode. Bit 3 STOP Description 0 1 stop bit. 1 2 stop bits. (Initial value) Bit 2--Reserved: This bit cannot be modified and is always read as 1. 256 Bits 1 and 0--Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock source when the baud rate generator is clocked from within the H8/520 chip. Bit 1 Bit 0 CKS1 CKS0 Description 0 0 o clock 0 1 o/4 clock 1 0 o/16 clock 1 1 o/64 clock (Initial value) 13.2.6 Serial Control Register (SCR)--H'FFDA (Channel 1), H'FFC2 (Channel 2) Bit 7 6 5 4 3 2 1 0 TIE RIE TE RE -- -- CKE1 CKE0 Initial value 0 0 0 0 1 1 0 0 Read/Write R/W R/W R/W R/W -- -- R/W R/W The SCR is an 8-bit readable/writable register that enables or disables various SCI functions. It is initialized to H'0C at a reset and in the standby modes. Bit 7--Transmit Interrupt Enable (RIE): This bit enables or disables the transmit-end interrupt (TXI) request when the transmit data register empty (TDRE) bit in the serial status register (SSR) is set to 1. Bit 7 TIE Description 0 The transmit-end interrupt request (TXI) is disabled. 1 The transmit-end interrupt request (TXI) is enabled. (Initial value) Bit 6--Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt (RXI) request when the receive data register full (RDRF) bit in the serial status register (SSR) is set to 1. It also enables and disables the receive-error interrupt (ERI) request. Bit 6 RIE Description 0 The receive-end interrupt (RXI) and receive-error interrupt (ERI) (Initial value) requests are disabled. 1 The receive-end interrupt (RXI) and receive-error interrupt (ERI) requests are enabled. 257 Bit 5--Transmit Enable (TE): This bit enables or disables the transmit function. When the transmit function is enabled, the TXD pin is automatically used for output. When the transmit function is disabled, the TXD pin can be used as a general-purpose I/O port. Bit 5 TE Description 0 The transmit function is disabled. The TXD pin can be (Initial value) used as a general-purpose I/O port. 1 The transmit function is enabled. The TXD pin is used for output. Bit 4--Receive Enable (RE): This bit enables or disables the receive function. When the receive function is enabled, the RXD pin is automatically used for input. When the receive function is disabled, the RXD pin is available as a general-purpose I/O port. Bit 4 RE Description 0 The receive function is disabled. The RXD pin can be (Initial value) used as a general-purpose I/O port. 1 The receive function is enabled. The RXD pin is used for input. Bits 3 and 2--Reserved: These bits cannot be modified and are always read as 1. Bit 1--Clock Enable 1 (CKE1): This bit selects the SCI clock source: either the internal baud rate generator or an external clock signal input at the SCK pin. When the external clock source is selected, the SCK pin is automatically used for input of the external clock signal. Bit 1 CKE1 Description 0 Internal clock source. 1 External clock source. (The SCK pin is used for input.) (Initial value) Bit 0--Clock Enable 0 (CKE0): When an internal clock source is used in synchronous mode, this bit enables or disables serial clock output at the SCK pin. This bit is ignored when the external clock is selected, or when the asynchronous mode is selected. For further information on the communication format and clock source selection, see tables 13-5 and 13-6 in section 13.3, "Operation". 258 Bit 0 CKE0 Description 0 The SCK pin is not used by the SCI (and is available as (Initial value) a general-purpose I/O port). 1 The SCK pin is used for serial clock output. 13.2.7 Serial Status Register (SSR)--H'FFDC (Channel 1), H'FFC4 (Channel 2) Bit 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER -- -- -- Initial value 1 0 0 0 0 1 1 1 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R Note: * Software can write a 0 to clear the flags, but cannot write a 1 in these bits. The SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'87 at a reset and in the standby modes. Bit 7--Transmit Data Register Empty (TDRE): This bit indicates when the TDR contents have been transferred to the TSR and the next character can safely be written in the TDR. Bit 7 TDRE Description 0 This bit is cleared from 1 to 0 when: 1 1. The CPU reads the TDRE bit after the TDRE bit has been set to 1, then writes a 0 in this bit. 2. The data transfer controller (DTC) writes data in the TDR. This bit is set to 1 at the following times: (Initial value) 1. The chip is reset or enters a standby mode. 2. When TDR contents are transferred to the TSR. 3. When TDRE = 0 and the TE bit is cleared to 0. Bit 6--Receive Data Register Full (RDRF): This bit indicates when one character has been received and transferred to the RDR. 259 Bit 6 RDRF Description 0 This bit is cleared from 1 to 0 when: 1 (Initial value) 1. The CPU reads the RDRF bit after the RDRF bit has been set to 1, then writes a 0 in this bit. 2. The data transfer controller (DTC) reads the RDR. 3. The chip is reset or enters a standby mode. This bit is set to 1 when one character is received without error and transferred from the RSR to the RDR. Bit 5--Overrun Error (ORER): This bit indicates an overrun error during reception. Bit 5 ORER Description 0 This bit is cleared from 1 to 0 when: 1 (Initial value) 1. The CPU reads the ORER bit after the ORER bit has been set to 1, then writes a 0 in this bit. 2. The chip is reset or enters a standby mode. This bit is set to 1 if reception of the next character ends while the receive data register is still full (RDRF = 1). Bit 4--Framing Error (FER): This bit indicates a framing error during data reception in the asynchronous mode. It has no meaning in the synchronous mode. Bit 4 FER Description 0 This bit is cleared from 1 to 0 when: 1 (Initial value) 1. The CPU reads the FER bit after the FER bit has been set to 1, then writes a 0 in this bit. 2. The chip is reset or enters a standby mode. This bit is set to 1 if a framing error occurs (stop bit = 0). Bit 3--Parity Error (PER): This bit indicates a parity error during data reception in the asynchronous mode, when a communication format with parity bits is used. This bit has no meaning in the synchronous mode, or when a communication format without parity bits is used. 260 Bit 3 PER Description 0 This bit is cleared from 1 to 0 when: 1 (Initial value) 1. The CPU reads the PER bit after the PER bit has been set to 1, then writes a 0 in this bit. 2. The chip is reset or enters a standby mode. This bit is set to 1 when a parity error occurs (the parity of the received data does not match the parity selected by the O/E bit in the SMR). Bits 2 to 0--Reserved: These bits cannot be modified and are always read as 1. 13.2.8 Bit Rate Register (BRR)--H'FFD9 (Channel 1), H'FFC1 (Channel 2) Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines the baud rate output by the baud rate generator. The BRR is initialized to H'FF (the slowest rate) at a reset and in the standby modes. Tables 13-3 and 13-5 show examples of BRR (N) and CKS (n) settings for commonly used bit rates. Different values can be set for each SCI channel. Table 13-4 indicates the maximum bit rates for various crystal oscillator frequencies in the asynchronous mode. 261 Table 13-3 Examples of BRR Settings in Asynchronous Mode (1) XTAL Frequency (MHz) 2 2.4576 4 4.194304 Bit Rate n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 -0.04 150 0 207 +0.16 0 255 0 1 103 +0.16 1 108 +0.21 300 0 103 +0.16 0 127 0 0 207 +0.16 0 217 +0.21 600 0 51 +0.16 0 63 0 0 103 +0.16 0 108 +0.21 1200 0 25 +0.16 0 31 0 0 51 +0.16 0 54 -0.70 2400 0 12 +0.16 0 15 0 0 25 +0.16 0 26 +1.14 4800 -- -- -- 0 7 0 0 12 +0.16 0 13 -2.48 9600 -- -- -- 0 3 0 -- -- -- -- -- -- 19200 -- -- -- 0 1 0 -- -- -- -- -- -- 31250 -- -- -- -- -- -- 0 1 0 -- -- -- 38400 -- -- -- 0 0 0 -- -- -- -- -- -- Table 13-3 Examples of BRR Settings in Asynchronous Mode (2) XTAL Frequency (MHz) 4.9152 6 7.3728 8 Bit Rate n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 174 -0.26 2 52 +0.50 2 64 +0.70 2 70 +0.03 150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16 300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16 600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16 1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16 2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16 4800 0 15 0 0 19 -2.34 0 23 0 0 25 +0.16 9600 0 7 0 -- -- -- 0 11 0 0 12 +0.16 19200 0 3 0 -- -- -- 0 5 0 -- -- -- 31250 -- -- -- 0 2 0 -- -- -- 0 3 0 38400 0 1 0 -- -- -- 0 2 0 -- -- -- 262 Table 13-3 Examples of BRR Settings in Asynchronous Mode (3) XTAL Frequency (MHz) 9.8304 10 12 12.288 Bit Rate n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 86 +0.31 2 88 -0.25 2 106 -0.44 2 108 +0.88 150 1 255 0 2 64 +0.16 2 77 0 2 79 0 300 1 127 0 1 129 +0.16 1 155 0 1 159 0 600 0 255 0 1 64 +0.16 1 77 0 1 79 0 1200 0 127 0 0 129 +0.16 0 155 +0.16 0 159 0 2400 0 63 0 0 64 +0.16 0 77 +0.16 0 79 0 4800 0 31 0 0 32 -1.36 0 38 +0.16 0 39 0 9600 0 15 0 0 15 +1.73 0 19 -2.34 0 19 0 19200 0 7 0 0 7 +1.73 -- -- -- 0 9 0 31250 0 4 -1.70 0 4 0 0 5 0 0 5 +2.40 38400 0 3 0 0 3 +1.73 -- -- -- 0 4 0 263 Table 13-3 Examples of BRR Settings in Asynchronous Mode (4) XTAL Frequency (MHz) 14.7456 16 19.6608 20 Bit Rate n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 130 -0.07 2 141 +0.03 2 174 -0.26 3 43 +0.88 150 2 95 0 2 103 +0.16 2 127 0 2 129 +0.16 300 1 191 0 1 207 +0.16 1 255 0 2 64 +0.16 600 1 95 0 1 103 +0.16 1 127 0 1 129 +0.16 1200 0 191 0 0 207 +0.16 0 255 0 1 64 +0.16 2400 0 95 0 0 103 +0.16 0 127 0 0 129 +0.16 4800 0 47 0 0 51 +0.16 0 63 0 0 64 +0.16 9600 0 23 0 0 25 +0.16 0 31 0 0 32 -1.36 19200 0 11 0 0 12 +0.16 0 15 0 0 15 +1.73 31250 -- -- -- 0 7 0 0 9 -1.70 0 9 0 38400 0 5 0 -- -- -- 0 7 0 0 7 +1.73 307200 -- -- -- -- -- -- 0 0 0 -- -- -- 312500 -- -- -- -- -- -- -- -- -- 0 0 0 Note: If possible, the error should be within 1%. B = OSC x 106/[64 x 22n x (N + 1)] B: N: OSC: n: Bit rate (bits/s) BRR value (0 N 255) Crystal oscillator frequency in MHz Internal clock source (0, 1, 2, or 3) The meaning of n is given by the table below: n CKS1 CKS0 Clock 0 0 0 o 1 0 1 o/4 2 1 0 o/16 3 1 1 o/64 264 Table 13-4 Maximum Bit Rate for Various Crystal Oscillator Frequencies (In Asynchronous Mode) CKS and BRR XTAL (MHz) Maximum Bit Rate (bits/s) n N 2 31250 0 0 2.4576 38400 0 0 4 62500 0 0 4.194304 65536 0 0 4.9152 76800 0 0 6 93750 0 0 7.3728 115200 0 0 8 125000 0 0 9.8304 153600 0 0 10 156250 0 0 12 187500 0 0 12.288 192000 0 0 14.7456 230400 0 0 16 250000 0 0 19.6608 307200 0 0 20 312500 0 0 265 Table 13-5 Examples of BRR Settings in Synchronous Mode XTAL Frequency (MHz) Bit 2 4 8 10 16 20 Rate n N n N n N n N n N n N 100 -- -- -- -- -- -- -- -- -- -- -- -- 250 1 249 2 124 2 249 -- -- 3 124 -- -- 500 1 124 1 249 2 124 -- -- 2 249 -- -- 1k 0 249 1 124 1 249 -- -- 2 124 -- -- 2.5 k 0 99 0 199 1 99 1 124 1 199 1 249 5k 0 49 0 99 0 199 0 249 1 99 1 124 10 k 0 24 0 49 0 99 0 124 0 199 0 249 25 k 0 9 0 19 0 39 0 49 0 79 0 99 50 k 0 4 0 9 0 19 0 24 0 39 0 49 100 k -- -- 0 4 0 9 -- -- 0 19 0 24 250 k 0 0* 0 1 0 3 0 4 0 7 0 9 0 0* 0 1 -- -- 0 3 0 4 0 0* -- -- 0 1 -- -- 0 0* 500 k 1M 2.5 M Notes: Blank: No setting is available. --: A setting is available, but the bit rate is inaccurate. *: Continuous transfer is not possible. B = OSC/[8 x 22n x (N + 1)] B: N: OSC: n: Bit rate (bits/s) BRR value (0 N 255) Crystal oscillator frequency in MHz Internal clock source (0, 1, 2, or 3) The meaning of n is given by the table below: n CKS1 CKS0 Clock 0 0 0 o 1 0 1 o/4 2 1 0 o/16 3 1 1 o/64 266 13.3 Operation 13.3.1 Overview The SCI supports serial data transfer in both asynchronous and synchronous modes. The communication format depends on settings in the SMR as indicated in table 13-6. The clock source and usage of the SCK pin depend on settings in the SMR and SCR as indicated in table 13-7. Table 13-6 Communication Formats Used by SCI SMR Stop Bit C/A CHR PE STOP Mode Format Parity Length 0 0 0 0 Asynchronous 8-Bit data None 1 1 1 2 0 Yes 1 1 0 2 0 7-Bit data None 1 1 -- 0 -- -- 1 2 Yes 1 1 1 1 2 Synchronous 8-Bit data -- -- Table 13-7 SCI Clock Source Selection SMR SCR Clock C/A CKE1 CKE0 Source SCK Pin 0 0 0 Internal I/O port* (Async mode) 1 1 0 Clock output at same frequency as bit rate External Clock input at 16 times the bit rate frequency Internal Serial clock output External Serial clock input 1 1 0 (Sync mode) 0 1 1 0 1 Note: * Not used by the SCI. Transmitting and receiving operations in the two modes are described next. 267 13.3.2 Asynchronous Mode In asynchronous mode, each character is individually synchronized by framing it with a start bit and stop bit. Full duplex data transfer is possible because the SCI has independent transmit and receive sections. Double buffering in both sections enables the SCI to be programmed for continuous data transfer. Figure 13-2 shows the general format of one character sent or received in the asynchronous mode. The communication channel is normally held in the mark state (high). Character transmission or reception starts with a transition to the space state (low). The first bit transmitted or received is the start bit (low). It is followed by the data bits, in which the least significant bit (LSB) comes first. The data bits are followed by the parity bit, if present, then the stop bit or bits (high) confirming the end of the frame. In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate). Idle state Start bit 1 bit D0 D1 Dn 7 or 8 bits Parity bit Stop bit 0 or 1 bit 1 or 2 bits One character Figure 13-2 Data Format in Asynchronous Mode Data Format: Table 13-8 lists the data formats that can be sent and received in asynchronous mode. Eight formats can be selected by bits in the SMR. Figure 13-2 268 Table 13-8 Data Formats in Asynchronous Mode SMR Bits CHR PE STOP Data Format 0 0 0 START 8-Bit data STOP 0 0 1 START 8-Bit data STOP STOP 0 1 0 START 8-Bit data P STOP 0 1 1 START 8-Bit data P STOP 1 0 0 START 7-Bit data STOP 1 0 1 START 7-Bit data STOP STOP 1 1 0 START 7-Bit data P STOP 1 1 1 START 7-Bit data P STOP STOP STOP Note: START: Start bit STOP: Stop bit P: Parity bit Clock: In the asynchronous mode it is possible to select either an internal clock created by the on-chip baud rate generator, or an external clock input at the SCK pin. Refer to table 13-7. If an external clock is input at the SCK pin, its frequency should be 16 times the desired bit rate. If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is used for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises at the center of the transmit data bits. Figure 13-3 shows the phase relationship between the output clock and transmit data. D0 D1 D2 ...... Start bit ...... Transmit data ...... Output clock Figure 13-3 Phase Relationship Between Clock Output and Transmit Data Figure 13-3 269 SCI Initialization: Before data can be transmitted or received, the SCI must be initialized by software. To initialize the SCI, software must clear the TE and RE bits to 0, then execute the following procedure. 1. Set the desired communication format in the SMR. 2. Write the value corresponding to the desired bit rate in the BRR. (This step is not necessary if an external clock is used.) 3 Select the clock and enable desired interrupts in the SCR. 4. Set the TE and/or RE bit in the SCR to 1. The TE and RE bits must both be cleared to 0 whenever the operating mode or data format is changed. After changing the operating mode or data format, before setting the TE and RE bits to 1 software must wait for at least 1 bit transfer time at the selected communication speed, to make sure the SCI is initialized. If an external clock is used, the clock must not be stopped. When clearing the TDRE bit during data transmission, to assure transfer of the correct data, do not clear the TDRE bit until after writing data in the TDR. Similarly, in receiving data, do not clear the RDRF bit until after reading data from the RDR. Data Transmission: The procedure for transmitting data in the asynchronous mode is as follows. 1. Set up the desired transmitting conditions in the SMR, SCR, and BRR. 2. Set the TE bit in the SCR to 1. The TXD pin will automatically be switched to output and one frame* of all 1s will be transmitted, after which the SCI is ready to transmit data. Note: * A frame is the data for one character, including the start bit and stop bit(s). 3. Check that the TDRE bit is set to 1, then write the first byte of transmit data in the TDR. Next clear the TDRE bit to 0. 4. The first byte of transmit data is transferred from the TDR to the TSR and sent in the designated format as follows. a. Start bit (one 0 bit). b. Transmit data (seven or eight bits, starting from bit 0) 270 c. Parity bit (odd or even parity bit, or no parity bit) d. Stop bit (one or two consecutive 1 bits) 5. Transfer of the transmit data from the TDR to the TSR makes the TDR empty, so the TDRE bit is set to 1. If the TIE bit is set to 1, a transmit-end interrupt (TXI) is requested. When the transmit function is enabled but the TDR is empty (TDRE = 1), the output at the TXD pin is held at 1 until the TDRE bit is cleared to 0. Data Reception: The procedure for receiving data in the asynchronous mode is as follows. 1. Set up the desired receiving conditions in the SMR, SCR, and BRR. 2. Set the RE bit in the SCR to 1. The RXD pin will automatically be switched to input and the SCI is ready to receive data. 3. The SCI synchronizes with the incoming data by detecting the start bit, and places the received bits in the RSR. At the end of the data, the SCI checks that the stop bit is 1. If the stop bit length is 2 bits, the SCI checks that both bits are 1. 4. When a complete frame has been received, the SCI transfers the received data to the RDR so that it can be read. If the character length is 7 bits, the most significant bit of the RDR is cleared to 0. At the same time, the SCI sets the RDRF bit in the SSR to 1. If the RIE bit is set to 1, a receiveend interrupt (RXI) is requested. 5. The RDRF bit is cleared to 0 when the CPU reads the SSR, then writes a 0 in the RDRF bit, or when the RDR is read by the data transfer controller (DTC). The RDR is then ready to receive the next character from the RSR. When a frame is not received correctly, a receive error occurs. There are three types of receive errors, listed in table 13-9. If a receive error occurs, the RDRF bit in the SSR is not set to 1. The corresponding error flag is set to 1 instead. If the RIE bit in the SCR is set to 1, a receive-error interrupt (ERI) is requested. When a framing or parity error occurs, the RSR contents are transferred to the RDR. If an overrun error occurs, however, the RSR contents are not transferred to the RDR. 271 If multiple receive errors occur simultaneously, all the corresponding error flags are set to 1. See section 13.5, "Application Notes". To clear a receive-error flag (ORER, FER, or PER), software must read the SSR, then write a 0 in the flag bit. Table 13-9 Receive Errors Name Abbreviation Description Overrun error ORER Reception of the next frame ends while the RDRF bit is still set to 1. The RSR contents are not transferred to the RDR. Framing error FER A stop bit is 0. The RSR contents are transferred to the RDR. Parity error PER The parity of a frame does not match the value selected by the bit in the SMR. The RSR contents are transferred to the RDR. 13.3.3 Synchronous Mode The synchronous mode is suited for high-speed, continuous data transfer. Each bit of data is synchronized with a serial clock pulse. Continuous data transfer is enabled by the double buffering employed in both the transmit and receive sections of the SCI. Full duplex communication (with the same clock) is possible because the transmit and receive sections are independent. Data Format: Figure 13-4 shows the communication format used in the synchronous mode. The data length is 8 bits for both the transmit and receive directions. The least significant bit (LSB) is sent and received first. Each bit of transmit data is output from the falling edge of the serial clock pulse to the next falling edge. Received bits are latched on the rising edge of the serial clock pulse. 272 Transmission direction Serial clock Data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't-care Don't-care Figure 13-4 Data Format in Synchronous Mode Clock: Either the internal serial clock created by the on-chip baud rate generator or an external clock input at the SCK pin can be selected in the synchronous mode. See table 13-7 for details. Figure 13-4 SCI Initialization: Before data can be transmitted or received, the SCI must be initialized by software. To initialize the SCI, software must clear the TE and RE bits to 0 to disable both the transmit and receive functions, then execute the following procedure. 1. Write the value corresponding to the desired bit rate in the BRR. (This step is not necessary if an external clock is used.) 2. Select the clock and enable desired interrupts in the SCR. 3. Select the synchronous mode in the SMR. 4. Set the TE and/or RE bit in the SCR to 1. Note: The input/output status of the SCK pin depends on the C/A bit in the SMR and the CKE0 and CKE1 bits in the SCR. (See table 13-7.) To prevent incorrect output from the SCK pin, set the SCR before the SMR. The TE and RE bits must both be cleared to 0 whenever the operating mode or data format is changed. After changing the operating mode or data format, before setting the TE and RE bits to 1 software must wait for at least 1 bit transfer time at the selected communication speed, to make sure the SCI is initialized. 273 When clearing the TDRE bit during data transmission, to assure correct data transfer, do not clear the TDRE bit until after writing data in the TDR. Similarly, in receiving data, do not clear the RDRF bit until after reading data from the RDR. Data Transmission: The procedure for transmitting data in the synchronous mode is as follows. 1. Set up the desired transmitting conditions in the SMR, BRR, and SCR. 2. Set the TE bit in the SCR to 1. The TXD pin will automatically be switched to output, after which the SCI is ready to transmit data. 3. Check that the TDRE bit in the SSR is set to 1, then write the first byte of transmit data in the TDR. Next clear the TDRE bit to 0. 4. The first byte of transmit data is transferred from the TDR to the TSR and sent, each bit synchronized with a clock pulse. Bit 0 is sent first. Transfer of the transmit data from the TDR to the TSR makes the TDR empty, so the TDRE bit is set to 1. If the TIE bit is set to 1, a transmit-end interrupt (TXI) is requested. The TDR and TSR function as a double buffer. Continuous data transmission can be achieved by writing the next transmit data in the TDR and clearing the TDRE bit to 0 while the SCI is transmitting the current data from the TSR. If an internal clock source is selected, after transferring the transmit data from the TDR to the TSR, while transmitting the data from the TSR the SCI also outputs a serial clock signal at the SCK pin. When all data bits in the TSR have been transmitted, if the TDR is empty (TDRE = 1), serial clock output is suspended until the next data byte is written in the TDR and the TDRE bit is cleared to 0. During this interval the TXD pin is held at the value of the last bit transmitted. If the external clock source is selected, data transmission is synchronized with the clock signal input at the SCK pin. When all data bits in the TSR have been transmitted, if the TDR is empty (TDRE = 1) but external clock pulses continue to arrive, the TXD pin outputs a string of bits equal to the last bit transmitted. Data Reception: The procedure for receiving data in the synchronous mode is as follows. 1. Set up the desired receiving conditions in the SMR, BRR, and SCR. 274 2. Set the RE bit in the SCR to 1. The RXD pin will automatically be switched to input and the SCI is ready to receive data. 3. Incoming data bits are latched in the RSR on eight clock pulses. When 8 bits of data have been received, the SCI sets the RDRF bit in the SSR to 1. If the RIE bit is set to 1, a receive-end interrupt (RXI) is requested. 4. The SCI transfers the received data byte to the RDR so that it can be read. The RDRF bit is cleared when the program reads the RDRF bit in the SSR, then writes a 0 in the RDRF bit, or when the data transfer controller (DTC) reads the RDR. The RDR and RSR function as a double buffer. Data can be received continuously by reading each byte of data from the RDR and clearing the RDRF bit to 0 before the last bit of the next byte is received. In general, an external clock source should be used for receiving data. If an internal clock source is selected, the SCI starts receiving data as soon as the RE bit is set to 1. The serial clock is also output at the SCK pin. The SCI continues receiving until the RE bit is cleared to 0. If the last bit of the next data byte is received while the RDRF bit is still set to 1, an overrun error occurs and the ORER bit is set to 1. If the RIE bit is set to 1, a receive-error interrupt (ERI) is requested. The data received in the RSR are not transferred to the RDR when an overrun error occurs. After an overrun error, reception of the next data is enabled when the ORER bit is cleared to 0. Simultaneous Transmit and Receive: The procedure for transmitting and receiving simultaneously in the synchronous mode is as follows: 1. Set up the desired communication conditions in the SMR, BRR, and SCR. 2. Set the TE and RE bits in the SCR to 1. The TXD and RXD pins are automatically switched to output and input, respectively, and the SCI is ready to transmit and receive data. 3. Data transmitting and receiving start when the TDRE bit in the SSR is cleared to 0. 275 4. Data are sent and received in synchronization with eight clock pulses. 5. First, the transmit data are transferred from the TDR to the TSR. This makes the TDR empty, so the TDRE bit is set to 1. If the TIE bit is set to 1, a transmit-end interrupt (TXI) is requested. If continuous data transmission is desired, the CPU must read the TDRE bit in the SSR, write the next transmit data in the TDR, then clear the TDRE bit to 0. Alternatively, the DTC can write the next transmit data in the TDR, in which case the TDRE bit is cleared automatically. If the TDRE bit is not cleared to 0 by the time the SCI finishes sending the current byte from the TSR, the TXD pin continues to output the last bit in the TSR. 6. In the receiving section, when 8 bits of data have been received they are transferred from the RSR to the RDR, and the RDRF bit in the SSR is set to 1. If the RIE bit is set to 1, a receive-end interrupt (RXI) is requested. 7. To clear the RDRF bit software must read the RDRF bit in the SSR, then write a 0 in the RDRF bit. Alternatively, the DTC can read the RDR, in which case the RDRF bit is cleared automatically. For continuous data reception, the RDRF bit must be cleared to 0 before the last bit of the next byte of data is received. If the last bit of the next data byte is received while the RDRF bit is still set to 1, an overrun error occurs and the ORER bit is set to 1. If the RIE bit is set to 1, a receive-error interrupt (ERI) is requested. The data received in the RSR are not transferred to the RDR when an overrun error occurs. After an overrun error, reception of the next data is enabled when the ORER bit is cleared to 0. An overrun error does not affect the transmit section of the SCI, which continues to transmit normally. 13.4 CPU Interrupts and DTC Interrupts The SCI can request three types of interrupts: transmit-end (TXI), receive-end (RXI), and receiveerror (ERI). Interrupt requests are enabled or disabled by the TIE and RIE bits in the SCR. Independent signals are sent to the interrupt controller for each type of interrupt. The transmit-end and receive-end interrupt request signals are obtained from the TDRE and RDRF flags. The receive-error interrupt request signal is the logical OR of the three error flags: overrun error (ORER), framing error (FER), and parity error (PER). Table 13-10 lists information about these interrupts. 276 Table 13-10 SCI Interrupts DTC Service Interrupt Description Available? Priority ERI Receive-error interrupt, requested when No High ORER, FER, or PER is set. RXI Receive-end interrupt, requested when Yes RDRF is set. TXI Transmit-end interrupt, requested when Yes TDRE is set. Low The TXI and RXI interrupts can be served by the data transfer controller (DTC) to have a data transfer performed. When the DTC serves one of these interrupts, it clears the TDRE or RDRF bit to 0 under the following conditions, which differ between the two bits. When invoked by a TXI request, if the DTC writes to the TDR, it automatically clears the TDRE bit to 0. When invoked by an RXI request, if the DTC reads from the RDR, it automatically clears the RDRF bit to 0. See section 6, "Data Transfer Controller", for further information on the DTC. 13.5 Application Notes Application programmers should note the following features of the SCI. TDR Write: The TDRE bit in the SSR is simply a flag that indicates that the TDR contents have been transferred to the TSR. The TDR contents can be rewritten regardless of the TDRE value. If a new byte is written in the TDR while the TDRE bit is 0, before the old TDR contents have been moved into the TSR, the old byte will be lost. Normally, software should check that the TDRE bit is set to 1 before writing to the TDR. Multiple Receive Errors: Table 13-11 lists the values of flag bits in the SSR when multiple receive errors occur, and indicates whether the RSR contents are transferred to the RDR. 277 Table 13-11 SSR Bit States and Data Transfer When Multiple Receive Errors Occur SSR Bits Receive Error RDRF ORER FER PER RSR to RDR*2 Overrun error 1*1 1 0 0 No Framing error 0 0 1 0 Yes Parity error 0 0 0 1 Yes Overrun + framing errors 1*1 1 1 0 No Overrun + parity errors 1*1 1 0 1 No Framing + parity errors 0 0 1 1 Yes Overrun + framing + parity errors 1*1 1 1 1 No Notes: 1. Set to 1 before the overrun error occurs. 2. Yes: The RSR contents are transferred to the RDR. No: The RSR contents are not transferred to the RDR. Line Break Detection: When the RXD pin receives a continuous stream of 0s in the asynchronous mode (line-break state), a framing error occurs because the SCI detects a 0 stop bit. The value H'00 is transferred from the RSR to the RDR. Software can detect the line-break state as a framing error accompanied by H'00 data in the RDR. The SCI continues to receive data, so if the FER bit is cleared to 0 another framing error will occur. Sampling Timing and Receive Margin in Asynchronous Mode: The serial clock used by the SCI in asynchronous mode runs at 16 times the bit rate. The falling edge of the start bit is detected by sampling the RXD input on the falling edge of this clock. After the start bit is detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is sampled on the rising edge of the serial clock pulse at the center of the bit. See figure 13-5. It follows that the receive margin can be calculated as in equation (1). When the absolute frequency deviation of the clock signal is 0 and the clock duty factor is 0.5, data can theoretically be received with distortion up to the margin given by equation (2). This is a theoretical limit, however. In practice, system designers should allow a margin of 20% to 30%. 278 0 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 0 1 2 3 4 5 6 7 8 9 10 11 121314 15 0 1 2 3 4 5 Basic clock -7.5 pulses Receive data +7.5 pulses D0 Start bit Sync sampling Data sampling Figure 13-5 Sampling Timing (Asynchronous Mode) M = {(0.5 - 1/2N) - (D - 0.5)/N - (L - 0.5)F} x 100 [%] (1) M: Receive margin N: Ratio of serial clock to bit rate (N = 16) D: Duty cycle of high or low clock pulses, whichever is longer (0.5 to 1.0) L: Frame length (9 to 12) F: Absolute value of clock frequency deviation Figure 13-5 When D = 0.5 and F= 0: M = (0.5 - 1/2 x 16) x 100 [%] = 46.875% 279 (2) D1 Section 14 A/D Converter 14.1 Overview The H8/520 chip includes an analog-to-digital converter module which can be programmed for input of analog signals on up to four (or eight*) channels. A/D conversion is performed by the successive approximations method with 10-bit resolution. 14.1.1 Features The features of the on-chip A/D module are as follows: * Four (or eight*) analog input channels * External trigger A/D conversion can be started by an external trigger input. * Sample and hold circuit * 10-Bit resolution * Rapid conversion Conversion time is 13.8 s per channel (at o = 10 MHz) * Single and scan modes -Single mode: A/D conversion is performed once. -Scan mode: A/D conversion is performed in a repeated cycle on one to four channels. * Four 16-bit data registers These registers store A/D conversion results for up to four channels. * A CPU interrupt (ADI) can be requested at the completion of each A/D conversion cycle. This interrupt can also be served by the on-chip data transfer controller (DTC), providing a convenient way to move results into memory. Note: * CP-68 package only 281 14.1.2 Block Diagram Bus interface Figure 14-1 shows a block diagram of A/D converter. AVss Internal data bus ADCR ADCSR ADDRD ADDRC 10-Bit D/A ADDRB AVcc ADDRA Successive approximations register Module data bus AN0 AN2 AN3 AN4* AN5* AN6* + Analog multiplexer multiplexor AN1 o/8 - Control circuit o/16 ADTRG External trigger input Sample & hold circuit AN7* ADI Interrupt signal ADDRA: ADDRB: ADDRC: ADDRD: ADCSR: ADCR: Note: A/D Data Register A A/D Data Register B A/D Data Register C A/D Data Register D A/D Control/Status Register A/D Control Register * CP-68 package only Figure 14-1 Block Diagram of A/D Converter 282 Figure 14-1 14.1.3 Input Pins Table 14-1 lists the input pins used by the A/D converter module. The eight analog input pins provided in the CP-68 package are divided into two groups, consisting of analog inputs 0 to 3 (AN0 to AN3) and analog inputs 4 to 7 (AN4 to AN7), respectively. Table 14-1 A/D Input Pins Name Abbreviation I/O Function Analog supply voltage AVCC Input Power supply and reference voltage for the analog circuits. Analog ground AVSS Input Ground and reference voltage for the analog circuits. Analog input 0 AN0 Input Analog input pins, group 0 Analog input 1 AN1 Input Analog input 2 AN2 Input Analog input 3 AN3 Input Analog input 4 AN4 Input Analog input 5 AN5 Input Analog input 6 AN6 Input Analog input 7 AN7 Input A/D external trigger input ADTRG Input Analog input pins, group 1*1 External trigger for starting A/D conversion*2 Notes: 1. CP-68 package only. 2. Not available in MCU mode 3 because this pin is used for the page address bus (A18). 283 14.1.4 Register Configuration Table 14-2 lists the registers of the A/D converter module. Table 14-2 A/D Registers Name Abbreviation R/W Initial Value Address A/D data register A (High) ADDRA (H) R H'00 H'FFE0 A/D data register A (Low) ADDRA (L) R H'00 H'FFE1 A/D data register B (High) ADDRB (H) R H'00 H'FFE2 A/D data register B (Low) ADDRB (L) R H'00 H'FFE3 A/D data register C (High) ADDRC (H) R H'00 H'FFE4 A/D data register C (Low) ADDRC (L) R H'00 H'FFE5 A/D data register D (High) ADDRD (H) R H'00 H'FFE6 A/D data register D (Low) ADDRD (L) R H'00 H'FFE7 A/D control/status register ADCSR R/(W)* H'00 H'FFE8 A/D control register ADCR R/W H'7F H'FFE9 Note: * Software can write a 0 to clear the status flag in bit 7 but cannot write a 1. 14.2 Register Descriptions 14.2.1 A/D Data Registers (ADDR)--H'FFE0 to H'FFE7 Bit 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R ADDRn H (n = A to D) Bit 7 6 5 4 3 2 1 0 AD1 AD0 -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R ADDRn L (n = A to D) The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. 284 Each result consist of 10 bits. The first 8 bits are stored in the upper byte of the data register corresponding to the selected channel. The last two bits are stored in the lower data register byte. The data registers are assigned to analog input channels as indicated in table 14-3. The A/D data registers are always readable by the CPU. The upper byte can be read directly. The lower byte is read via a temporary register. See section 14-3, "CPU Interface", for details. The unused bits (bits 5 to 0) of the lower data register byte are always read as 0. The A/D data registers are initialized to H'0000 at a reset and in the standby modes. Table 14-3 Assignment of Data Registers to Analog Input Channels Analog Input Channel Group 0 Group 1 * A/D Data Register AN0 AN4 ADDRA AN1 AN5 ADDRB AN2 AN6 ADDRC AN3 AN7 ADDRD Note: * CP-68 package only. 14.2.2 A/D Control/Status Register (ADCSR)--H'FFE8 Bit 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit. The A/D control/status register (ADCSR) is an 8-bit readable/writable register that controls the operation of the A/D converter module. The ADCSR is initialized to H'00 at a reset and in the standby modes. 285 Bit 7--A/D End Flag (ADF): This status flag indicates the end of one cycle of A/D conversion. Bit 7 ADF Description 0 This bit is cleared from 1 to 0 when: 1 (Initial value) 1. The chip is reset or placed in a standby mode. 2. The CPU reads the ADF bit after the ADF bit is set to 1, then writes a 0 in this bit. 3. An A/D interrupt is served by the data transfer controller (DTC). This bit is set to 1 at the following times: 1. Single mode: when one A/D conversion is completed. 2. Scan mode: when inputs on all selected channels have been converted. Bit 6--A/D Interrupt Enable (ADI): This bit selects whether to request an A/D interrupt (ADI) when A/D conversion is completed. Bit 6 ADIE Description 0 The A/D interrupt request (ADI) is disabled. 1 The A/D interrupt request (ADI) is enabled. (Initial value) Bit 5--A/D Start (ADST): The A/D converter operates while this bit is set to 1. In the single mode, this bit is automatically cleared to 0 at the end of each A/D conversion. Bit 5 ADST Description 0 A/D conversion is halted. 1 1. (Initial value) Single mode: One A/D conversion is performed. The ADST bit is automatically cleared to 0 at the end of the conversion. 2. Scan mode: A/D conversion starts and continues cyclically on the selected channels until the ADST bit is cleared to 0. Bit 4--Scan Mode (SCAN): This bit selects the scan mode or single mode of operation. See section 14.4, "Operation", for descriptions of these modes. The mode should be changed only when the ADST bit is cleared to 0. Bit 4 SCAN Description 0 Single mode 1 Scan mode (Initial value) 286 Bit 3--Clock Select (CKS): This bit controls the A/D conversion time. The conversion time should be changed only when the ADST bit is cleared to 0. Bit 3 CKS Description 0 Conversion time = 274 states (maximum) 1 Conversion time = 138 states (maximum) (Initial value) Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit combine to select one or more analog input channels. The channel selection should be changed only when the ADST bit is cleared to 0. Group Select Channel Select CH2 CH1 CH0 Single Mode Scan Mode 0 0 0 AN0 AN0 0 1 AN1 AN0 and AN1 1 0 AN2 AN0 to AN2 1 1 AN3 AN0 to AN3 0 0 AN4* AN4* 0 1 AN5* AN4 and AN5* 1 0 AN6* AN4 to AN6* 1 1 AN7* AN4 to AN7* 1 Selected Channels Note: * CP-68 package only 14.2.3 A/D Control Register (ADCR)--H'FFE9 Bit 7 6 5 4 3 2 1 0 TRGE -- -- -- -- -- -- -- Initial value 0 1 1 1 1 1 1 1 Read/Write R/W -- -- -- -- -- -- -- The A/D control register (ADCR) is an 8-bit readable/writable register that enables or disables the A/D external trigger signal. The ADCR is initialized to H'7F at a reset and in the standby modes. 287 Bit 7--Trigger Enable (TRGE): This bit enables the ADTRG (A/D external trigger) signal. When enabled, a high-to-low transition of ADTRG sets the ADST bit, starting A/D conversion. Bit 7 TRGE Description 0 A/D external trigger is disabled. ADTRG does not set the ADST bit. 1 A/D external trigger is enabled. A high-to-low transition of ADTRG sets the ADST bit. (Initial value) Bits 6 to 0--Reserved: These bits cannot be modified and are always read as 1. 14.3 CPU Interface The A/D data registers (ADDRA to ADDRD) are 16-bit registers, but they are accessed via an 8-bit module data bus. Accordingly, the upper byte of each register can be read directly, but the lower byte is accessed through an 8-bit temporary register (TEMP). When the CPU or DTC reads the upper byte of an A/D data register, at the same time as the upper byte is placed on the internal data bus, the lower byte is transferred to TEMP. When the lower byte is accessed, the value in TEMP is placed on the internal data bus. A program that requires all 10 bits of an A/D result should perform word access, or should read first the upper byte, then the lower byte of the A/D data register. Either way, it is assured of obtaining consistent data. Consistent data are not assured if the program reads the lower byte first. A program that requires only 8-bit A/D accuracy should perform byte access to the upper byte of the A/D data register. The value in TEMP can be left unread. Figure 14-2 shows the data flow when the CPU (or DTC) reads an A/D data register. 288 < Upper byte read > Module data bus CPU receives data H'AA Bus interface TEMP [H'40] ADDRn H [H'AA] ADDRn L [H'40] (n = A to D) < Lower byte read > Module data bus CPU receives data H'40 Bus interface TEMP [H'40] ADDRn H [H'AA] ADDRn L [H'40] (n = A to D) Figure 14-2 Read Access to A/D Data Register (When Register Contains H'AA40) 14.4 Operation The A/D converter performs 10 successive approximations to obtain a result ranging from H'0000 (corresponding to AVSS) to H'FFC0 (corresponding to AVCC). Only the first 10 bits of the result are significant. Figure 14-2 289 The response of the A/D converter is shown below. H'FFC0 corresponds to voltages of approximately 0.999AVCC and above. The A/D converter module can be programmed to operate in single mode or scan mode as explained below. 14.4.1 Single Mode The single mode is suitable for obtaining a single data value from a single channel. A/D conversion starts when the ADST bit is set to 1 by software or external trigger input. During the conversion process the ADST bit remains set to 1. When conversion is completed, the ADST bit is automatically cleared to 0. When the conversion is completed, the ADF bit is set to 1. If the interrupt enable bit (ADIE) is also set to 1, an A/D conversion end interrupt (ADI) is requested, so that the converted data can be processed by an interrupt-handling routine. Alternatively, the interrupt can be served by the data transfer controller (DTC). When an A/D interrupt is served by the DTC, the DTC automatically clears the ADF bit to 0. When an A/D interrupt is served by the CPU, however, the ADF bit remains set until the CPU reads the ADCSR, then writes a 0 in the ADF bit. Before selecting the single mode, clock, and analog input channel, software should clear the ADST bit to 0 to make sure the A/D converter is stopped. Changing the mode, clock, or channel selection while A/D conversion is in progress can lead to conversion errors. The following example explains the A/D conversion process in single mode when channel 1 (AN1) is selected and external triggering is not used. Figure 14-3 shows the corresponding timing chart. 1. Software clears the ADST bit to 0, then selects the single mode (SCAN = 0) and channel 1 (CH2 to CH0 = 001), enables the A/D interrupt request (ADIE = 1), and sets the ADST bit to 1 to start A/D conversion. Coding Example: (when using the slow clock, CKS = 0) BCLR #7, @H'FFE9 BCLR #5, @H'FFE8 MOV.B #H'61, @H'FFE8 290 2. The A/D converter samples the AN1 input and converts the voltage level to a digital value. At the end of the conversion process the A/D converter transfers the result to register ADDRB, sets the ADF bit to 1, clears the ADST bit to 0, and halts. 3. ADF = 1 and ADIE = 1, so an A/D interrupt is requested. 4. The user-coded A/D interrupt-handling routine is started. 5. The interrupt-handling routine reads the ADCSR value, then writes a 0 in the ADF bit to clear this bit to 0. The reading and writing can be done with a single BCLR #7, @H'FFE8 instruction. 6. The interrupt-handling routine reads and processes the A/D conversion result. 7. The routine ends. Steps 2 to 7 can now be repeated by setting the ADST bit to 1 again. If the ADI bit in data transfer enable register D (bit 0 at address H'FFF7) is set to 1, the interrupt is served by the data transfer controller (DTC). Steps 4 to 7 then change as follows. 4'. 5'. 6'. 7'. The DTC is started. The DTC automatically clears the ADF bit to 0. The DTC transfers the A/D conversion result from ADDRB to a specified destination address. The DTC ends. 291 Interrupt (ADI) Set* Set* ADIE A/D conversion starts Set* ADST Clear* Clear* ADF 292 Channel 0 (AN 0) Waiting Channel 1 (AN 1) Waiting Channel 2 (AN 2) Waiting Channel 3 (AN 3) Waiting A/D conversion Waiting A/D conversion Waiting ADDRA A/D conversion result ADDRB Read result Read result A/D conversion result ADDRC ADDRD * indicates execution of a software instruction Figure 14-3 Figure 14-3 A/D Operation in Single Mode (When Channel 1 is Selected) 14.4.2 Scan Mode The scan mode can be used to monitor analog inputs on one or more channels. When the ADST bit is set to 1 by software or by external trigger input, A/D conversion starts from the first channel (AN0) in the scan group.* If the scan group includes more than one channel (i.e., if bit CH1 or CH0 is set), conversion of the next channel begins as soon as conversion of the first channel ends. Conversion of the selected channels continues cyclically until the ADST bit is cleared to 0. The conversion results are placed in the data registers corresponding to the selected channels. Before selecting the scan mode, clock, and analog input channels, software should clear the ADST bit to 0 to make sure the A/D converter is stopped. Changing the mode, clock, or channel selection while A/D conversion is in progress can lead to conversion errors. The following example explains the A/D conversion process when three channels in group 0 are selected (AN0, AN1, and AN2) and external triggering is not used. Figure 14-4 shows the timing. 1. Software clears the ADST bit to 0, then selects the scan mode (SCAN = 1), scan group 0 (CH2 = 0), and analog input channels AN0 to AN2 (CH1 = 1, CH0 = 0) and sets the ADST bit to 1 to start A/D conversion. Coding Example: (with slow clock and ADI interrupt enabled) BCLR #7, @H'FFE9 BCLR #5, @H'FFE8 MOV.B #H'72, @FFE8 2. The A/D converter samples the input at AN0, converts the voltage level to a digital value, and transfers the result to register ADDRA. 3. Next the A/D converter samples and converts AN1 and transfers the result to ADDRB. Then it samples and converts AN2 and transfers the result to ADDRC. 4. After all selected channels (AN0 to AN2) have been converted, the AD converter sets the ADF bit to 1. If the ADIE bit is set to 1, an A/D interrupt (ADI) is requested. Then the A/D converter begins converting AN0 again. 5. Steps 2 to 4 are repeated cyclically as long as the ADST bit remains set to 1. To stop the A/D converter, software must clear the ADST bit to 0. The data currently undergoing conversion when the ADST bit is cleared are ignored. The A/D data registers retain the last completed conversion results. Regardless of which channel is being converted when the ADST bit is cleared to 0, when the ADST bit is set to 1 again, conversion begins from the the first selected channel (AN0 or AN4). Note: * In the CP-68 package, the first channel is AN0 if CH2 = 0, and AN4 if CH2 = 1. 293 Continuous A/D conversion Set* Clear* ADST A/D conversion time ADF Channel 0 (AN 0) Channel 1 (AN 1) Channel 2 (AN 2) Waiting A/D conversion Waiting Waiting A/D conversion Waiting A/D conversion Waiting Waiting Waiting A/D conversion A/D conversion 294 Channel 3 (AN 3) Waiting Waiting Transfer A/D conver- ADDRA A/D conversion sion (When Figure 14-3 A/D Operation in Single Mode Channel 1 is Selected) A/D conversion ADDRB ADDRC A/D conversion ADDRD Note: * indicates execution of a software instruction Figure 14-4 Figure 14-4 A/D Operation in Scan Mode (When Channels 0 to 2 are Selected) Clear* 14.4.3 Input Sampling Time and A/D Conversion Time The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a time tD after the ADST bit is set to 1. The sampling process lasts for a time tSPL. The actual A/D conversion begins after sampling is completed. Figure 14-5 shows the timing of these steps, and table 15-4 lists the total conversion times (tCONV) for the single mode. The total conversion time includes tD and tSPL. The purpose of tD is to synchronize the ADCSR write time with the A/D conversion process, so the length of tD is variable. The total conversion time therefore varies within the minimum to maximum ranges indicated in table 14-4. In the scan mode, the ranges given in table 14-4 apply to the first conversion. The length of the second and subsequent conversion processes is fixed at 256 states (when CKS = 0) or 128 states (when CKS = 1). 295 (1) o Internal address bus (2) Write signal Input sampling timing ADF tSPL tD tCONV (1) (2) tD tSPL tCONV : : : : : ADCSR write cycle ADCSR address Synchronization delay Input sampling time Total A/D conversion time Figure 14-5 A/D Conversion Timing Table 14-4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol min typ max min typ max Synchronization delay tD 18 -- 33 10 -- 17 Input sampling time tSPL -- 63 -- -- 31 -- Total A/D conversion time tCONV 259 -- 274 131 -- 138 Note: Values in the table are numbers of states. Figure 14-5 296 14.4.4 External Triggering of A/D Conversion The A/D conversion process can be started by an external trigger input. External trigger input is enabled at the ADTRG pin when the TRGE bit in the ADCR is set to 1. 1.0 o clock cycles after the ADTRG input is sampled, the ADST bit in the ADCSR is set to 1 and A/D conversion commences. The timing of external triggering is shown in figure 14-6. o tTRGS ADTRG 2.0 cycles (max) ADST A/D conversion Figure 14-6 Timing of Setting of ADST Bit 14.5 Interrupts and the Data Transfer Controller The ADI interrupt request is enabled or disabled by the ADIE bit in the ADCSR. When the ADI bit in data transfer enable register DTED (bit 0 at address H'FFF7) is set to 1, the ADI interrupt is served by the data transfer controller. The DTC can be used to transfer A/D results to a buffer in memory, or to an I/O port. The DTC automatically clears the ADF bit to 0. Figure 14-6 Note: In scan mode, the DTC can transfer data for only one channel per interrupt, even if two or more channels are selected. 297 Section 15 RAM 15.1 Overview The H8/520 includes 512 bytes of on-chip static RAM, connected to the CPU by a 16-bit data bus. Both byte and word access to the on-chip RAM are performed in two states, enabling rapid data transfer and instruction execution. The on-chip RAM is assigned to addresses H'FD80 to H'FF7F in the chip's address space. A RAM control register (RAMCR) can enable or disable the on-chip RAM, permitting these addresses to be allocated to external memory instead, if so desired. 15.1.1 Block Diagram Figure 15-1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Address H'FD80 RAMCR H'FD82 On-chip RAM H'FF7E Even addresses Odd addresses RAMCR: RAM Control Register Figure 15-1 Block Diagram of On-Chip RAM Figure 15-1 299 15.1.2 Register Configuration The on-chip RAM is controlled by the register described in table 15-1. Table 15-1 RAM Control Register Name Abbreviation R/W Initial Value Address RAM control register RAMCR R/W H'FF H'FFF9 15.2 RAM Control Register (RAMCR) Bit 7 6 5 4 3 2 1 0 RAME -- -- -- -- -- -- -- Initial value 1 1 1 1 1 1 1 1 Read/Write R/W -- -- -- -- -- -- -- The RAM control register (RAMCR) is an 8-bit register that enables or disables the on-chip RAM. Bit 7--RAM Enable (RAME): This bit enables or disables the on-chip RAM. The RAME bit is initialized by a reset. It is not initialized in the software standby mode. Bit 7 RAME Description 0 On-chip RAM is disabled. 1 On-chip RAM is enabled. (Initial value) Bits 6 to 0--Reserved: These bits cannot be modified and are always read as 1. 15.3 Operation 15.3.1 Expanded Modes (Modes 1, 2, 3, and 4) If the RAME bit is set to 1, accesses to addresses H'FD80 to H'FF7F are directed to the on-chip RAM. If the RAME bit is cleared to 0, accesses to addresses H'FD80 to H'FF7F are directed to the external data bus. 300 15.3.2 Single-Chip Mode (Mode 7) If the RAME bit is set to 1, accesses to addresses H'FD80 to H'FF7F are directed to the on-chip RAM. If the RAME bit is cleared to 0, access of any type (instruction fetch or data read or write) to addresses H'FD80 to H'FF7F causes an address error and initiates the CPU's exception-handling sequence. 301 Section 16 ROM 16.1 Overview The H8/520 includes 16 kbytes of high-speed on-chip ROM. The on-chip ROM is connected to the CPU via a 16-bit data bus and is accessed in two states. Users wishing to program the chip themselves can request electrically programmable ROM (PROM). The PROM version of the H8/520 has a PROM mode in which the chip can be programmed with a standard, external PROM writer. The chip is also available with masked ROM. The on-chip ROM is enabled or disabled depending on the MCU operating mode, which is determined by the inputs at the mode pins when the chip comes out of the reset state. See table 16-1. Table 16-1 ROM Usage in Each MCU Mode Mode Pins Mode MD2 MD1 MD0 ROM Mode 1 (expanded minimum mode) 0 0 1 Disabled (external addresses) Mode 2 (expanded minimum mode) 0 1 0 Enabled Mode 3 (expanded maximum mode) 0 1 1 Disabled (external addresses) Mode 4 (expanded maximum mode) 1 0 0 Enabled Mode 7 (single-chip mode) 1 1 1 Enabled 16.1.1 Block Diagram Figure 16-1 shows the block diagram of the on-chip ROM. 303 Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Address H'0000 H'0002 On-chip ROM H'3FFF Even addresses Odd addresses Figure 16-1 Block Diagram of On-Chip ROM Figure 16-1 16.2 PROM Mode 16.2.1 PROM Mode Setup The PROM version of the H8/520 has a PROM mode in which the usual microcomputer functions are halted to allow the on-chip PROM to be programmed. The programming method is the same as for the HN27C256. To select the PROM mode, apply the signal inputs listed in table 16-2 to the mode pins (MD2 to MD0) and pins P51 and P50. Table 16-2 Selection of PROM Mode Pin Input MD1 Low MD2 and MD0 High P51 and P50 High 304 16.2.2 Socket Adapter Pin Arrangements and Memory Map The H8/520 can be programmed with a general-purpose PROM writer by attaching a socket adapter as listed in table 16-3. The socket adapter depends on the type of package. Figure 16-2 shows the socket adapter pin arrangements by giving the correspondence between H8/520 pins and HN27C256 pin functions. Figure 16-3 is a memory map. Table 16-3 Socket Adapter Package Socket Adapter 64-Pin windowed shrink DIP (DC-64S) HS528ESS01H 64-Pin shrink DIP (DP-64S) 64-Pin QFP (FP-64A) HS528ESH01H 68-Pin PLCC (CP-68) HS528ESC01H 305 H8/520 EPROM Socket FP-64A 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 4 6 35 36 49 3 34 5 44 9 43 56 CP-68 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 14 16 45 46 63 13 44 15 54 2 19 53 DC-64S DP-64S 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 12 14 43 44 57 11 42 13 52 17 51 64 -- -- -- OE: Output enable -- -- -- CE: Chip enable -- -- -- -- -- -- Pin RES NMI P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 MD0 MD2 P50 P51 AVCC VCC VCC MD1 AVss Vss Vss Vss * * * * * * * * * * VPP: Pin VPP EA9 EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 OE EA10 EA11 EA12 EA13 EA14 CE VCC HN27C256 1 24 11 12 13 15 16 17 18 19 10 9 8 7 6 5 4 3 25 22 21 23 2 26 27 20 28 VSS 14 Programming power (12.5 V) EO7 to EO0: Data input/output EA14 to EA0: Address input Note: All pins not shown in this figure should be left open. Figure 16-2 Socket Adapter Pin Arrangements 306 Address in MCU mode Address in PROM mode H'0000 H'0000 On-chip ROM H'3FFF H'3FFF Figure 16-3 Memory Map in PROM Mode 16.3 Programming The write, verify, and inhibited sub-modes of the PROM mode are selected as shown in table 16-4. Table 16-4 Selection of Sub-Modes in PROM Mode Pins Mode CE OE VPP VCC 07 to 00 A14 to A0 Write Low High VPP VCC Data input Address input Verify High Low VPP VCC Data output Address input Programming inhibited High High VPP VCC High-impedance Address input Read Low Low VPP VCC Data output Address input Note: The VPP and VCC pins must be held at the VPP and VCC voltage levels. The H8/520 PROM uses the same, standard read/write specifications as the HN27C256 and HN27256. 16.3.1 Writing and Verifying An efficient, high-speed programming procedure can be used to write and verify PROM data. This procedure writes data quickly without subjecting the chip to voltage stress and without sacrificing data reliability. It leaves the data H'FF written in unused addresses. 307 Figure 16-4 shows the basic high-speed programming flowchart. Tables 16-5 and 16-6 list the electrical characteristics of the chip in the PROM mode. Figure 16-5 shows a write/verify timing chart. START Set write/verify mode VCC = 6.0 V 0.25 V, V PP = 12.5 V 0.3 V Address = 0 n=0 n + 1 n Y N Write time tpw = 1 ms 5% n<S S = 25 N Verify OK? Address + 1 Address GO Write topw = 3 n ms Last address? N Y Set read mode VCC = 5.0 V 0.5 V, V PP = V CC Error NO GO All addresses read OK? GO END Figure 16-4 High-Speed Programming Flowchart 308 Figure 16-4 Table 16-5 DC Characteristics (When VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Measurement Item Symbol min typ max Unit O7 to O0, A14 to A0, OE, CE VIH 2.2 -- VCC + 0.3 V O7 to O0, A14 to A0, OE, CE VIL -0.3 -- 0.8 V O7 to O0 VOH 2.4 -- -- V IOH = -200 A O7 to O0 VOL -- -- 0.45 V IOL = 1.6 mA O7 to O0, A14 to A0, OE, CE |ILI| -- -- 2 A Vin = 5.25 V/0.5 V VCC current ICC -- -- 50 mA VPP current IPP -- -- 40 mA Input high Conditions voltage Input low voltage Output high voltage Output low voltage Input leakage current Table 16-6 AC Characteristics (When VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Measurement Item Symbol min typ max Unit Conditions Address setup time tAS 2 -- -- s See figure 16-5* OE setup time tOES 2 -- -- s Data setup time tDS 2 -- -- s Address hold time tAH 0 -- -- s Data hold time tDH 2 -- -- s Data output disable time tDF -- -- 130 ns VPP setup time tVPS 2 -- -- s Program pulse width tPW 0.95 1.0 1.05 ms OE pulse width for tOPW 2.85 -- 78.75 ms VCC setup time tVCS 2 -- -- s Data output delay time tOE 0 -- 500 ns overwrite-programming Note: * Input pulse level: 0.8 V to 2.2 V Input rise/fall time 20 ns Timing reference levels: input--1.0 V, 2.0 V; output--0.8 V, 2.0 V 309 Write Verify Address tAS Data tAH Input data tDS Output data tDF tDH VPP VPP VCC VCC tVPS VCC GND tVCS CE tPW OE tOES tOE tOPW Figure 16-5 PROM Write/Verify Timing 16.3.2 Notes on Writing 1. Write with the specified voltages and timing. The programming voltage (VPP) in the PROM mode is 12.5 V. Caution: Applied voltages in excess of the specified values can permanently destroy the chip. Be particularly careful about the PROM writer's overshoot characteristics. Figure 16-5 If the PROM writer is set to Intel specifications or Hitachi HN27256 or HN27C256 specifications, VPP will be 12.5 V. 2. Before writing data, check that the socket adapter and chip are correctly mounted in the PROM writer. Overcurrent damage to the chip can result if the index marks on the PROM writer, socket adapter, and chip are not correctly aligned. 310 3. Don't touch the socket adapter or chip while writing. Touching either of these can cause contact faults and write errors. 16.3.3 Reliability of Written Data An effective way to assure the data holding characteristics of the programmed chips is to bake them at 150C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 16-6 shows the recommended screening procedure. Write program and verify Bake with power off 150C, 48 hours Read and check program VCC = 4.5 V and 5.5 V Install Figure 16-6 Recommended Screening Procedure If a series of write errors occurs while the same PROM writer is in use, stop programming and check the PROM writer and socket adapter for defects, using a microcomputer with a windowed package and on-chip EPROM. Please inform Hitachi of any abnormal conditions noted during programming or in screening of program data after high-temperature baking. 311 16.3.4 Erasing of Data The windowed package enables data to be erased by illuminating the window with ultraviolet light. Table 16-7 lists the erasing conditions. Table 16-7 Erasing Conditions Item Value Ultraviolet wavelength 2537 A Minimum illumination 15 W*s/cm2 The conditions in table 16-7 can be satisfied by placing a 12000 W/cm2 ultraviolet lamp 2 or 3 centimeters directly above the chip and leaving it on for about 20 minutes. 16.4 Handling of Windowed Packages Glass Erasing Window: Rubbing the glass erasing window of a windowed package with a plastic material or touching it with an electrically charged object can create a static charge on the window surface which may cause the chip to malfunction. If the erasing window becomes charged, the charge can be neutralized by a short exposure to ultraviolet light. This returns the chip to its normal condition, but it also reduces the charge stored in the floating gates of the PROM, so it is recommended that the chip be reprogrammed afterward. Accumulation of static charge on the window surface can be prevented by the following precautions: 1. When handling the package, ground yourself. Don't wear gloves. Avoid other possible sources of static charge. 2. Avoid friction between the glass window and plastic or other materials that tend to accumulate static charge. 3. Be careful when using cooling sprays, since they may have a slight ion content. 4. Cover the window with an ultraviolet-shield label, preferably a label including a conductive material. Besides protecting the PROM contents from ultraviolet light, the label protects the chip by distributing static charge uniformly. Handling after Programming: Fluorescent light and sunlight contain small amounts of ultraviolet, so prolonged exposure to these types of light can cause programmed data to invert. In addition, exposure to any type of intense light can induce photoelectric effects that may lead to chip malfunction. It is recommended that after programming the chip, cover the erasing window with a light-proof label (such as an ultraviolet-shield label). 312 Section 17 Power-Down State 17.1 Overview The H8/520 has a power-down state that greatly reduces power consumption by stopping the CPU functions. The power-down state includes three modes: 1. Sleep mode: software-triggered mode in which the CPU halts but the rest of the chip remains active. 2. Software standby mode: software-triggered mode in which the entire chip is inactive. 3. Hardware standby mode: hardware-triggered mode in which the entire chip is inactive. The sleep mode and software standby mode are entered from the program execution state by executing the SLEEP instruction under the conditions given in table 17-1. The hardware standby mode is entered from any other state by setting mode 6 at the mode pins (MD2 to MD0). Table 17-1 lists the conditions for entering and leaving the power-down modes. It also indicates the status of the CPU, on-chip supporting modules, etc. in each power-down mode. Table 17-1 Power-Down State Entering CPU Peripheral I/O Exiting Mode Procedure Clock CPU Registers Functions RAM Ports Methods Sleep Execute Run Held Run Held Held * Interrupt mode SLEEP * RES low instruction * Mode 6 Soft- Set SSBY bit ware in SBYCR to Halt Halt Halt Held Halt standby 1, then mode Held Held * NMI and * RES low initialized * Mode 6 execute SLEEP instruction* Hard- Set mode ware pins to Halt Halt Not Halt held standby mode 6 mode Notes: * The watchdog timer must also be stopped. SBYCR: Software standby control register SSBY: Software standby bit 313 Held High * Mode 1,2,3, and impe- 4, or 7 then initialized dance RES low state high 17.2 Sleep Mode 17.2.1 Transition to Sleep Mode Execution of the SLEEP instruction causes a transition from the program execution state to the sleep mode. After executing the SLEEP instruction, the CPU halts, but the contents of its internal registers remain unchanged. The functions of the on-chip supporting modules do not stop in the sleep mode. 17.2.2 Exit from Sleep Mode The chip wakes up from the sleep mode when it receives an internal or external interrupt request or a low input at the RES pin, or when mode 6 is set at the mode pins. Wake-Up by Interrupt: An interrupt releases the sleep mode and starts either the CPU's interrupthandling sequence or the data transfer controller (DTC). If the interrupt is served by the DTC, after the data transfer is completed the CPU executes the instruction following the SLEEP instruction, unless the count in the data transfer count register (DTCR) is 0. If an interrupt on a level equal to or less than the mask level in the CPU's status register (SR) is requested, the interrupt is left pending and the sleep mode continues. Also, if an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable bit in the module's control register, the interrupt cannot be requested, so it cannot wake the chip up. Wake-Up by RES pin: When the RES pin goes low, the chip exits from the sleep mode to the reset state. Wake-Up by Mode 6: When the mode pins are set to mode 6, the chip exits from the sleep mode to the hardware standby mode. 17.3 Software Standby Mode 17.3.1 Transition to Software Standby Mode A program enters the software standby mode by setting the standby bit (SSBY) in the software standby control register (SBYCR) to 1, then executing the SLEEP instruction. Table 17-2 lists the attributes of the software standby control register. 314 Table 17-2 Software Standby Control Register Name Abbreviation R/W Initial Value Address Software standby control register SBYCR R/W H'7F H'FFFB In the software standby mode, the CPU, clock, and the on-chip supporting module functions all stop, reducing power consumption to an extremely low level. The on-chip supporting modules and their registers are reset to their initial state, but as long as a minimum necessary voltage supply is maintained (at least 2 V), the contents of the CPU registers and on-chip RAM remain unchanged. The I/O ports also remain in their current states. 17.3.2 Software Standby Control Register (SBYCR) Bit 7 6 5 4 3 2 1 0 SSBY -- -- -- -- -- -- -- Initial value 0 1 1 1 1 1 1 1 Read/Write R/W -- -- -- -- -- -- -- The software standby control register (SBYCR) is an 8-bit register that controls the action of the SLEEP instruction. Bit 7--Software Standby (SSBY): This bit enables or disables the transition to the software standby mode. Bit 7 SSBY Description 0 The SLEEP instruction causes a transition to the sleep mode. 1 The SLEEP instruction causes a transition to the software standby mode. (Initial value) The watchdog timer must be stopped before the chip can enter the software standby mode. To stop the watchdog timer, clear the timer enable bit (TME) in the watchdog timer's timer control/status register (TCSR) to 0. The SSBY bit cannot be set to 1 while the TME bit is set to 1. When the chip is recovered from the software standby mode by a nonmaskable interrupt (NMI), the SSBY bit is automatically cleared to 0. It is also cleared to 0 by a reset or transition to the hardware standby mode. Bits 6 to 0--Reserved: These bits cannot be modified and are always read as 1. 315 17.3.3 Exit from Software Standby Mode The chip can be brought out of the software standby mode by an input at the NMI pin, RES pin, or mode pins. Recovery by NMI Pin: When an NMI request signal is received, the clock oscillator begins operating but clock pulses are supplied only to the watchdog timer (WDT). The watchdog timer begins counting from H'00 at the rate determined by the clock select bits (CKS2 to CKS0) in its timer status/control register (TCSR). This rate should be set slow enough to allow the clock oscillator to stabilize before the count reaches H'FF. When the count overflows from H'FF to H'00, clock pulses are supplied to the whole chip, the software standby mode ends, and execution of the NMI interrupt-handling sequence begins. The clock select bits (CKS2 to CKS0) should be set as follows. Crystal Oscillator: Set CKS2 to CKS0 to a value that makes the watchdog timer interval equal to or greater than 10 ms, which is the clock stabilization time. External Clock Input: CKS2 to CKS0 can be set to any value. The minimum value (CKS2 = CKS1 = CKS0 = 0) is recommended. Recovery by RES Pin: When the RES pin goes low, the clock oscillator starts. Next, when the RES pin goes high, the CPU begins executing the reset sequence. When the chip recovers from the software standby mode by a reset, clock pulses are supplied to the entire chip at once. Be sure to hold the RES pin low long enough for the clock to stabilize. Recovery by Mode 6: When the mode pins are set to mode 6, the chip exits from the software standby mode to the hardware standby mode. 17.3.4 Sample Application of Software Standby Mode In this example the chip enters the software standby mode on the falling edge of the NMI input and recovers from the software standby mode on the rising edge of NMI. Figure 17-1 shows a timing chart of the transitions. The nonmaskable interrupt edge bit (NMIEG) in the NMI control register (NMICR) is originally cleared to 0, selecting the falling edge as the NMI trigger. After accepting an NMI interrupt in this 316 condition, software changes the NMIEG bit to 1, sets the SSBY bit to 1, and executes the SLEEP instruction to enter the software standby mode. The chip recovers from the software standby mode on the next rising edge at the NMI pin. Oscillator o NMI NMIEG SSBY Clock settling time NMI interrupt handling Software standby mode WDT interval NMIEG = 1 (Power-down state) SSBY = 1 Clock start-up SLEEP instruction time NMI interrupt handling WDT overflow Figure 17-1 NMI Timing of Software Standby Mode (Application Example) 17.3.5 Application Notes The I/O ports remain in their current states in the software standby mode. If a port is in the high output state, the output current is not reduced in the software standby mode. Figure 17-1 17.4 Hardware Standby Mode 17.4.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters the hardware standby mode whenever the mode pins are set to mode 6 (MD2 and MD1 high, MD0 low). The hardware standby mode reduces power consumption drastically by halting the CPU, stopping all the functions of the on-chip supporting modules, and placing I/O ports in the high-impedance state. 317 The registers of the on-chip supporting modules are reset to their initial values. Only the on-chip RAM is held unchanged, provided the minimum necessary voltage supply is maintained (at least 2 V).* Notes: 1. The RAME bit in the RAM control register should be cleared to 0 before the mode pins are set to mode 6, to disable the on-chip RAM during the hardware standby mode. 2. Do not change the inputs at the mode pins (MD2, MD1, MD0) during hardware standby mode. Be particularly careful not to let all three mode inputs go low, since that would place the chip in PROM mode, causing increased current dissipation. 17.4.2 Recovery from Hardware Standby Mode Recovery from the hardware standby mode requires inputs at both the mode and RES pins. When the mode pins are set to mode 1, 2, 3, 4, or 7, the clock oscillator begins running. The RES pin should be low at this time and should be held low long enough for the clock to stabilize. When the RES pin changes from low to high, the reset sequence is executed and the chip returns to the program execution state. 17.4.3 Timing Sequence of Hardware Standby Mode Figure 17-2 shows the usual sequence for entering and leaving the hardware standby mode. First the RES pin goes low, placing the chip in the reset state. Then the mode pins are set to mode 6, placing the chip in the hardware standby mode and stopping the clock. In the recovery sequence first the mode pins are set to mode 1, 2, 3, 4, or 7; then after the clock stabilizes, the RES pin is returned to the high level. 318 Oscillator RES MD2 to MD 0 Mode 1, 2, 3, 4, or 7 Mode 1, 2, 3, 4, or 7 Mode 6 Clock settling time Restart Figure 17-2 Hardware Standby Sequence Figure 17-2 319 Section 18 Electrical Specifications 18.1 Absolute Maximum Ratings Table 18-1 lists the absolute maximum ratings. Table 18-1 Absolute Maximum Ratings Item Symbol Rating Unit Supply voltage VCC -0.3 to +0.7 V Programming voltage VPP -0.3 to +13.5 V Input voltage (except port 6) Vin -0.3 to VCC + 0.3 V Input voltage (port 6) Vin -0.3 to AVCC + 0.3 V Analog supply voltage AVCC -0.3 to +7.0 V Analog input voltage VAN -0.3 to AVCC + 0.3 V Operating temperature Topr Regular specifications: -20 to +75 C Wide-range specifications: -40 to +85 C -55 to +125 C Storage temperature Tstg Note: Permanent damage to the chip may result if the absolute maximum ratings shown in table 18-1 are exceeded. 18.2 Electrical Characteristics 18.2.1 DC Characteristics Table 18-2 lists the DC characteristics. 321 Table 18-2 DC Characteristics Conditions: VCC = AVCC = 5.0 V 10%*1, VSS = AVSS = 0 V, Ta = -20 to 75C (Regular specifications) Ta = -40 to 85C (Wide-range specifications) Test Item Input high voltage Symbol min typ max Unit VIH VCC - 0.7 -- VCC + 0.3 V EXTAL VCC x 0.7 -- VCC + 0.3 V Port 6 2.2 -- AVCC + 0.3 V Other input pins 2.2 -- VCC + 0.3 V -0.3 -- 0.5 V -0.3 -- 0.8 1.0 -- 2.5 V 2.0 -- 3.5 V 0.4 -- -- V -- -- 10.0 A Vin = 0.5 to -- -- 1.0 A VCC - 0.5 V -- -- 1.0 A Vin = 0.5 to RES, MD2, Conditions MD1, MD0 (except port 5) Input low voltage RES, MD2, VIL MD1, MD0 Other input pins (except port 5) Schmitt trigger Port 5 VTVT+ input voltage VT+ Input leakage current RES - | Iin | NMI, MD2, VT- MD1, MD0, Port 6 AVCC - 0.5 V Leakage current Port 7, in 3-state ports 5 to 1 | ITSI | -- -- 1.0 A Vin = 0.5 to VCC - 0.5 V (off state) Input pull-up Ports 3 and 4 -IP 50 -- 200 A Vin = 0 V All output pins VOH VCC - 0.5 -- -- V IOH = -200 A 3.5 -- -- V IOH = -1 mA -- -- 0.4 V IOL = 1.6 mA -- -- 1.0 V IOL = 8 mA -- -- 1.2 V IOL = 10 mA -- -- 0.4 V IOL = 2.6 mA -- -- 60 pF Vin = 0 V NMI -- -- 30 pF f = 1 MHz All input pins -- -- 15 pF Ta = 25C MOS current Output high voltage Output low voltage All output pins VOL (except RES) Port 3 RES Input capacitance RES Cin except RES 322 Table 18-2 DC Characteristics (cont) Test Item Current dissipation* Normal operation Symbol min typ max Unit Conditions ICC -- 20 30 mA f = 6 MHz -- 25 40 mA f = 8 MHz -- 30 50 mA f = 10 MHz -- 12 20 mA f = 6 MHz -- 16 25 mA f = 8 MHz -- 20 30 mA f = 10 MHz -- 0.01 5.0 A -- 0.6 2.0 mA -- 0.01 5.0 A 2.0 -- -- V Sleep mode Standby Analog supply During A/D current conversion AICC While waiting RAM standby voltage VRAM Note: AVCC must be connected to a power supply even when the A/D converter is not used. * Current dissipation values assume that VIH min = VCC - 0.5 V, VIL max = 0.5 V, all output pins are in the no-load state, and all MOS input pull-ups are off. Table 18-3 Allowable Output Current Sink Values Conditions: VCC = AVCC = 5.0 V 10%, VSS = AVSS = 0 V, Ta = -20 to 75C (Regular specifications) Ta = -40 to 85C (Wide-range specifications) Item Symbol min typ max Unit IOL -- -- 10 mA Allowable output low Port 3 current sink (per pin) RES -- -- 2.6 mA Other output pins -- -- 2.0 mA -- -- 40 mA -- -- 80 mA Allowable output low Port 3, total of 8 pins current sink (total) Total of all other IOL output pins Allowable output high All output pins -IOH -- -- 2.0 mA Allowable output high Total of all output -IOH -- -- 40 mA current sink (total) pins current sink (per pin) Note: To avoid degrading the reliability of the chip, be careful not to exceed the output current sink values in table 18-3. In particular, when driving a Darlington transistor pair or LED directly, be sure to insert a current-limiting resistor in the output path. See figures 18-1 and 18-2. 323 H8/520 H8/520 Vcc 2 k Port 600 Darlington pair Port 3 LED Darlington Transistor Pair Figure 18-1 Example of Circuit for Driving a 18.2.2 AC Characteristics The AC characteristics of the H8/520 chip are listed in three tables. Bus timing parameters are given in table 18-4, control signal timing parameters in table 18-5, and timing parameters of the on-chip supporting modules in table 18-6. See figure 18-3 for the output load circuit. Table 18-4 Bus Timing Conditions: VCC = 5.0 V 10%, o = 0.5 to 10 MHz, VSS = 0 V Ta = -20 to 75C (Regular specifications) Ta = -40 to 85C (Wide-range specifications) 6 MHz 8 MHz Figure 18-1 Item Symbol min Clock cycle time 10 MHz Test max min max min max Unit Conditions tcyc 166.7 2000 125 2000 100 2000 ns See figure 18-4 Clock pulse width low tCL 65 -- 45 -- 35 -- ns Clock pulse width high tCH 65 -- 45 -- 35 -- ns Clock rise time tCr -- 15 -- 15 -- 15 ns Clock fall time tCf -- 15 -- 15 -- 15 ns Address delay time tAD -- 70 -- 60 -- 55 ns Address hold time tAH 30 -- 25 -- 20 -- ns RD delay time 1 tRDD1 -- 70 -- 60 -- 40 ns RD delay time 2 tRDD2 -- 70 -- 60 -- 50 ns WR delay time 1 tWRD1 -- 70 -- 60 -- 50 ns WR delay time 2 tWRD2 -- 70 -- 60 -- 50 ns Write data strobe pulse width tDSWW 200 -- 150 -- 120 -- ns Address setup time 1 tAS1 25 -- 20 -- 15 -- ns Address setup time 2 tAS2 105 -- 80 -- 65 -- ns Read data setup time tRDS 60 -- 50 -- 40 -- ns 324 See figure 18-4 Table 18-4 Bus Timing (cont) 6 MHz 8 MHz 10 MHz Test Item Symbol min max min max min max Unit Conditions Read data hold time tRDH 0 -- 0 -- 0 -- ns Read data access time tACC -- 280 -- 190 -- 160 ns Write data delay time tWDD -- 70 -- 60 -- 60 ns Write data setup time tWDS 30 -- 15 -- 10 -- ns Write data hold time tWDH 30 -- 25 -- 20 -- ns Wait setup time tWTS 40 -- 40 -- 40 -- ns Wait hold time tWTH 10 -- 10 -- 10 -- ns See figure 18-4 See figure 18-5 Table 18-5 Control Signal Timing Conditions: VCC = 5.0 V 10%, o = 0.5 to 10 MHz, VSS = 0 V Ta = -20 to 75C (Regular specifications) Ta = -40 to 85C (Wide-range specifications) 6 MHz 8 MHz 10 MHz Test Item Symbol min max min max min max Unit Conditions RES setup time tRESS 200 -- 200 -- 200 -- ns RES pulse width 1* tRESW1 6.0 -- 6.0 -- 6.0 -- tcyc RES pulse width 2* tRESW2 520 -- 520 -- 520 -- tcyc RES output delay time tRESD -- 100 -- 100 -- 100 ns RES output pulse width tRESOW 132 -- 132 -- 132 -- tcyc Mode programming setup time tMDS 4.0 -- 4.0 -- 4.0 -- tcyc See figure 18-6 NMI setup time tNMIS 150 -- 150 -- 150 -- ns See figure 18-8 NMI hold time tNMIH 10 -- 10 -- 10 -- ns IRQ0 setup time tIRQ0S 50 -- 50 -- 50 -- ns IRQ1 to IRQ7 setup time tIRQ1S 50 -- 50 -- 50 -- ns IRQ1 to IRQ7 hold time tIRQ1H 10 -- 10 -- 10 -- ns NMI pulse width (for recovery from software standby mode) tNMIW 200 -- 200 -- 200 -- ns A/D trigger setup time tTRGS 50 -- 50 -- 50 -- ns A/D trigger hold time tTRGH 10 -- 10 -- 10 -- ns Crystal oscillator settling time (reset) tOSC1 20 -- 20 -- 20 -- ms See figure 18-9 Crystal oscillator settling time (software standby) tOSC2 10 -- 10 -- 10 -- ms See figure 17-1 See figure 18-6 See figure 18-7 See figure 18-18 Note: * tRESW2 applies when the RSTOE bit in the reset control/status register (RSTCR) is set to 1. tRESW1 applies when RSTOE is cleared to 0. tRESW1 also applies at power-up. 325 Table 18-6 Timing Conditions of On-Chip Supporting Modules Conditions: VCC = 5.0 V 10%, o = 0.5 to 10 MHz, VSS = 0 V Ta = -20 to 75C (Regular specifications) Ta = -40 to 85C (Wide-range specifications) 6 MHz Item FRT 8 MHz 10 MHz Test Symbol min max min max min max Unit Conditions Timer output delay time tFTOD -- 100 -- 100 -- 100 ns Timer input setup time tFTIS 50 -- 50 -- 50 -- ns Timer clock input setup time tFTCS 50 -- 50 -- 50 -- ns Timer clock pulse width tFTCW 1.5 -- 1.5 -- 1.5 -- tcyc TMR Timer output delay time tTMOD -- 100 -- 100 -- 100 ns See figure 18-13 Timer clock input setup time tTMCS 50 -- 50 -- 50 -- ns See figure 18-14 Timer clock pulse width tTMCW 1.5 -- 1.5 -- 1.5 -- tcyc Timer reset input setup time tTMRS 50 -- 50 -- 50 -- ns See figure 18-15 (Async) tScyc 2 -- 2 -- 2 -- tcyc See figure 18-16 (Sync) 4 -- 4 -- 4 -- tcyc tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 tScyc 100 -- 100 -- 100 ns SCI Input clock cycle Input clock pulse width Transmit data delay time (Sync) tTXD -- Receive data setup time (Sync) tRXS 100 -- 100 -- 100 -- ns Receive data hold time (Sync) tRXH -- 100 -- 100 -- 100 ns tPWD -- 100 -- 100 -- 100 ns Input data setup time tPRS 50 -- 50 -- 50 -- ns Input data hold time tPRH 50 -- 50 -- 50 -- ns Ports Output data delay time * Measurement Conditions for AC Characteristics 5V RL H8/520 output pin C = 90 pF: P1, P2, P3, P4, = 30 pF: P5, P7 RL = 2.4 k RH = 12 k C RH Figure 18-3 Output Load Circuit Input/output timing reference levels Low: 0.8 V High: 2.0 V 326 See figure 18-11 See figure 18-12 See figure 18-17 See figure 18-10 18.2.3 A/D Converter Characteristics Table 18-7 lists the characteristics of the on-chip A/D converter. Table 18-7 (1) A/D Converter Characteristics Conditions: VCC = AVCC = 5.0 V 10%, VSS = AVSS = 0 V, Ta = -40 to 85C (Wide-range specifications) 6 MHz 8 MHz 10 MHz Item min typ max min typ max min typ max Unit Resolution 10 10 10 10 10 10 10 10 10 Bits Conversion time -- -- 23.0 -- -- 17.25 -- -- 13.8 s Analog input capacitance -- -- 20 -- -- 20 -- -- 20 pF Allowable signal-source impedance -- -- 10 -- -- 10 -- -- 10 k Nonlinearity error -- -- 2.0 -- -- 2.0 -- -- 2.0 LSB Offset error -- -- 2.0 -- -- 2.0 -- -- 2.0 LSB Full-scale error -- -- 2.0 -- -- 2.0 -- -- 2.0 LSB Quantizing error -- -- 0.5 -- -- 0.5 -- -- 0.5 LSB Absolute accuracy -- -- 2.5 -- -- 2.5 -- -- 2.5 LSB Table 18-7 (2) A/D Converter Characteristics Conditions: VCC = AVCC = 5.0 V 10%, VSS = AVSS = 0 V, Ta = -20 to 75C (Regular specifications) 6 MHz 8 MHz 10 MHz Item min typ max min typ max min typ max Unit Resolution 10 10 10 10 10 10 10 10 10 Bits Conversion time -- -- 23.0 -- -- 17.25 -- -- 13.8 s Analog input capacitance -- -- 20 -- -- 20 -- -- 20 pF Allowable signal-source impedance -- -- 10 -- -- 10 -- -- 10 k Nonlinearity error -- -- 3.5 -- -- 3.5 -- -- 3.5 LSB Offset error -- -- 3.5 -- -- 3.5 -- -- 3.5 LSB Full-scale error -- -- 3.5 -- -- 3.5 -- -- 3.5 LSB Quantizing error -- -- 0.5 -- -- 0.5 -- -- 0.5 LSB Absolute accuracy -- -- 4.0 -- -- 4.0 -- -- 4.0 LSB 327 18.3 MCU Operational Timing This section provides the following timing charts: 18.3.1 18.3.2 18.3.3 18.3.4 18.3.5 18.3.6 18.3.7 Bus timing Control Signal Timing Clock Timing I/O Port Timing 16-Bit Free-Running Timer Timing 8-Bit Timer Timing SCI Timing Figures 18-4 and 18-5 Figures 18-6 to 18-8 Figure 18-9 Figure 18-10 Figures 18-11 and 18-12 Figures 18-13 to 18-15 Figures 18-16 and 18-17 18.3.1 Bus Timing 1. Basic Bus Cycle (without Wait States) in Expanded Modes T1 tcyc tCH T2 T3 tCL o tAD tCf tCr A19 to A0 tRDD1 tASI tAH tRDD2 AS, RD tACC D7 to D 0 (Read) tRDS tWRD1 tAS2 tDSWW tWRD2 tRDH tAH WR tWDD tWDS tWDH D7 to D 0 (Write) Figure 18-4 Basic Bus Cycle (without Wait States) in Expanded Modes 328 2. Basic Bus Cycle (with 1 Wait State) in Expanded Modes T1 T2 TW T3 o A19 to A0 AS, RD D7 to D 0 (Read) WR D7 to D 0 (Write) tWTS tWTH tWTS tWTH WAIT Figure 18-5 Basic Bus Cycle (with 1 Wait State) in Expanded Modes Figure 18-5 329 18.3.2 Control Signal Timing 1. Reset Input Timing o tRESS tRESS RES tMDS tRESW1, tRESW2 MD2 to MD 0 Figure 18-6 Reset Input Timing 2. Reset Output Timing Figure 18-6 o tRESD tRESD RES tRESOW Figure 18-7 Reset Output Timing 3. Interrupt Input Timing o tNMIS tNMIH Figure 18-7 NMI tIRQIS tIRQIH IRQ1 to IRQ7 tIRQ0S IRQ0 Figure 18-8 Interrupt Input Timing 330 Figure 18-8 331 tOSC1 Hardware standby mode Figure 18-9 Clock Oscillator Stabilization Note: The H8/520 enters hardware standby mode when MD 2 and MD 1 are driven high and MD 0 is driven low. RES MD0 MD2, MD1 VCC o tOSC1 18.3.3 Clock Oscillator Stabilization Timing Figure 18-9 18.3.4 I/O Port Timing Port read/write cycle T1 T2 T3 o tPRS Port 1 to port 7 tPRH (Input) tPWD Port 1* to (Output) port 7 Note: * Except P67 and P6 7 to P60 Figure 18-10 I/O Port Input/Output Timing Figure 18-10 332 18.3.5 16-Bit Free-Running Timer Timing 1. Free-Running Timer Input/Output Timing o Free-running timer counter Compare-match tFTOD FTOA1, FTOB1, FTOA2, FTOB2 tFTIS FTI1, FTI2 Figure 18-11 Free-Running Timer Input/Output Timing 2. External Clock Input Timing for Free-Running Timers Figure 18-11 o tFTCS FTCI1 FTCI2 tFTCWL tFTCWH Figure 18-12 External Clock Input Timing for Free-Running Timers Figure 18-12 333 18.3.6 8-Bit Timer Timing 1. 8-Bit Timer Output Timing o Timer counter Compare-match tTMOD TMO Figure 18-13 8-Bit Timer Output Timing 2. 8-Bit Timer Clock Input Timing Figure 18-13 o tTMCS TMCI tTMCS tTMCWL tTMCWH Figure 18-14 8-Bit Timer Clock Input Timing 3. 8-Bit Timer Reset Input Timing o tTMRS Figure 18-14 TMRI Timer counter N H'00 Figure 18-15 8-Bit Timer Reset Input Timing 334 Figure 18-15 18.3.7 Serial Communication Interface Timing tSCKW tScyc Figure 18-16 SCI Input Clock Timing tScyc Serial clock tTXD Transmit data Figure 18-16 tRXS tRXH Receive data Figure 18-17 SCI Input/Output Timing (Synchronous Mode) 18.3.8 A/D External Trigger Input Timing Figure 18-17 o tTRGS tTRGH ADTRG Figure 18-18 A/D External Trigger Input Timing Figure 18-18 335 Appendix A Instructions A.1 Instruction Set Operation Notation Rd General register (destination operand) FP Frame pointer Rs General register (source operand) #IMM Immediate data Rn General register disp Displacement (EAd) Destination operand + Add (EAs) Source operand - Subtract CCR Condition code register x Muliply N N (Negative) flag in CCR / Divide Z Z (Zero) flag in CCR Logical AND V V (Overflow) flag in CCR Logical OR C C (Carry) flag in CCR Logical exclusive OR CR Control register Move PC Program counter Swap CP Code page register Logical NOT SP Stack pointer Condition Code Symbols Changed after instruction execution 0 Cleared to zero 1 Set to 1 -- Value before operation is retained Varies depending on conditions 337 Instruction set Size Mnemonic Data MOV: G CCR Bit Operation B/W N Z V C (EAs) Rd B/W 0 -- B 0 -- B/W 0 -- W 0 -- Rs (EAd) transfer #IMM (EAd) MOV: E #IMM Rd MOV: F @ (d: 8, FP) Rd (short format) Rs @ (d: 8, FP) (short format) MOV: I #IMM Rd MOV: L (@aa: 8) Rd (short format) B/W 0 -- MOV: S Rs (@aa: 8) (short format) B/W 0 -- LDM @ SP + Rn W -- -- -- -- STM Rn (register list) @ - SP W -- -- -- -- XCH Rs Rd W -- -- -- -- SWAP Rd (upper byte) Rd (lower byte) B 0 -- (MOVTPE) Cannot be used in the H8/520 (MOVFPE) Cannot be used in the H8/520 Arithmetic ADD: G Rd + (EAs) Rd B/W operations ADD: Q (EAd) + #IMM (EAd) B/W B/W -- -- -- -- (short format) (register list) (#IMM = 1, 2) ADDS (short format) Rd + (EAs) Rd (Rd is always word size) ADDX Rd + (EAs) + C Rd B/W DADD (Rd)10 + (Rs)10 + C (Rd)10 B -- -- SUB Rd - (EAs) Rd B/W SUBS Rd - (EAs) Rd B/W -- -- -- -- SUBX Rd - (EAs) - C Rd B/W DSUB (Rd)10 - (Rs)10 - C (Rd)10 B -- -- MULXU Rd x (EAs) Rd B/W 0 0 B/W 0 B/W (Unsigned) DIVXU CMP: G 16 x 16 Rd / (EAs) Rd (Unsigned) 8x8 16 / 8 32 / 16 Rd - (EAs), Set CCR (EAd) - #IMM, Set CCR CMP: E Rd - #IMM, Set CCR (short format) B CMP: I Rd - #IMM, Set CCR (short format) W 338 Size Mnemonic Arithmetic EXTS CCR Bit Operation B/W N Z V C (< Bit 7 > of < Rd >) B 0 0 (< Bit 15 to 8 > of < Rd >) operations EXTU 0 (<Bit 15 to 8 > of < Rd >) B 0 0 0 TST (EAd) - 0, Set CCR B/W 0 0 NEG 0 - (EAd) (EAd) B/W 0 CLR 0 (EAd) B/W 0 1 0 0 TAS (EAd) - 0, Set CCR B 0 0 B/W B/W 0 B/W 0 B/W 0 0 B/W 0 B/W 0 B/W 0 B/W 0 (1)2 (< Bit 7 > of < EAd >) Shift SHAL MSB LSB C 0 operations SHAR MSB LSB C SHLL MSB LSB C SHLR 0 MSB LSB 0 ROTL C ROTR C MSB LSB MSB LSB C ROTXL ROTXR MSB LSB MSB LSB C C Logic AND Rd (EAs) Rd B/W 0 -- operations OR Rd (EAs) Rd B/W 0 -- XOR Rd (EAs) Rd B/W 0 -- NOT (EAd) (EAd) B/W 0 -- BSET (< Bit number > of < EAd >) Z B/W -- -- -- B/W -- -- -- Bit 1 (< Bit number > of < Rn >) manipulations BCLR (< Bit number > of < EAd >) Z 0 (< Bit number > of < Rn >) BTST (< Bit number > of < EAd >) Z B/W -- -- -- BNOT (< Bit number > of < EAd >) Z B/W -- -- -- (< Bit number > of < Rn >) 339 Mnemonic Branching BCC instructions JMP PJMP BSR JSR PJSR RTS PRTS RTD PRTD SCB SCB/F SCB/NE SCB/EQ Size B/W -- Operation If condition is true then PC + disp PC else next; Mnemonic Description Condition BRA (BT) Always (True) True BRN (BF) Never (False) False BHI HIgh CZ=0 BLS Low or Same CZ=0 BCC (BHS) Carry Clear (High or Same) C=0 N -- CCR Bit Z V -- -- C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BCS (BLO) Carry Set (LOw) C=1 BNE Not Equal Z=0 BEQ EQual Z=1 BVC oVerflow Clear V=0 BVS oVerflow Set V=1 BPL PLus N=0 BMI MInus N=1 BGE Greater or Equal NV=0 BLT Less Than NV=1 BGT Greater Than Z (N V) = 0 BLE Less or Equal Z (N V) = 1 Effective address PC Effective address CP, PC PC @ - SP PC + disp PC PC @ - SP Effective address PC PC @ - SP CP @ - SP Effective address CP, PC @ SP + PC @ SP + CP @ SP + PC @ SP + PC SP + #IMM SP @ SP + CP @ SP + PC SP + #IMM SP If condition is true then next; else Rn - 1 Rn; If Rn = -1 then next; else PC + disp PC; Mnemonic Description SCB/F Condition False SCB/NE Not Equal Z=0 SCB/EQ Equal Z=1 340 Size Mnemonic System TRAPA CCR Bit Operation B/W N Z V C PC @ - SP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (If MAX MODE CP @ - SP) control SR @ - SP (If MAX MODE < vector > CP) < vector > PC TRAP/VS If V bit = 1 then TRAP else next; RTE @ SP + SR (If MAX MODE @ SP + CP) @ SP + PC LINK FP (R6) @ - SP SP FP (R6) SP + #IMM SP UNLK FP (R6) SP @SP + FP SLEEP Normal running mode power-down state -- -- -- -- -- LDC (EAs) CR B/W* STC CR (EAd) B/W* -- -- -- -- ANDC CR #IMM CR B/W* ORC CR #IMM CR B/W* XORC CR #IMM CR B/W* NOP PC + 1 PC -- -- -- -- -- Note: * Depends on the CR. 341 A.2 Instruction Codes Table A-1 shows the machine-language coding of each instruction. * How to read table A-1 (a) to (d). The general operand format consists of an effective address (EA) field and operation-code (OP) field specified in the following order: EA field 1 2 Op field 3 4 5 Bytes 2, 3, 5, and 6 are not present in all instructions. 342 6 address (L) address address (H) data data (H) 00001100 00001100 1 0 1 0 Sz r r r 1 1 0 1 Sz r r r 1 1 1 0 Sz r r r Rn @Rn @(d:8, Rn) @(d:16, Rn) @-Rn @Rn+ @aa:8 @aa:16 #xx:8 #xx:16 data (L) disp (L) disp disp (H) 1 1 1 1 Sz r r r 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r 0 0 0 0 Sz 1 0 1 0 0 0 1 Sz 1 0 1 3 Operation code (EA) 2 1 Addressing mode Instruction Instruction MOV:G.B <EAs>,Rd 2 2 3 4 2 2 3 4 3 MOV:G.W <EAs>,Rd 2 2 3 4 2 2 3 4 MOV:G.B Rs,<EAd> 2 2 3 4 2 2 3 4 3 MOV:G.W Rs,<EAd> 2 2 3 4 2 2 3 4 Byte length of instruction Operation code (OP) 4 5 1 0 0 0 0 r drdrd 4 1 0 0 0 0 r drdrd 1 0 0 1 0 r srsrs 4 1 0 0 1 0 r srsrs Shading indicates addressing modes not available for this instruction. Some instructions have a special format in which the operation code comes first. The following notation is used in the tables. * Sz: Operand size (byte or word) Byte: Sz = 0 Word: Sz = 1 343 6 * r r r: General register number field rrr Sz = 0 (Byte) 15 8 7 Sz = 1 (Word) 0 15 0 000 Not used R0 R0 001 Not used R1 R1 010 Not used R2 R2 011 Not used R3 R3 100 Not used R4 R4 101 Not used R5 R5 110 Not used R6 R6 111 Not used R7 R7 * c c c: Control register number field ccc Sz = 0 (Byte) 000 (Not allowed*) 15 001 010 8 7 Not used Sz = 1 (Word) 15 0 0 SR CCR (Not allowed) (Not allowed) (Not allowed) 011 Not used BR (Not allowed) 100 Not used EP (Not allowed) 101 Not used DP (Not allowed) 110 111 (Not allowed) Not used (Not allowed) TP (Not allowed) Note: * "Disallowed" means that this combination of bits must not be specified. Specifying a disallowed combination may cause abnormal results. 344 * Register list: A byte in which bits indicate general registers as follows. Bit 7 6 5 4 3 2 1 0 R7 R6 R5 R4 R3 R2 R1 R0 * #VEC: Four bits designating a vector number from 0 to 15. The vector numbers correspond to addresses of entries in the exception vector table as follows: Vector Address Vector Address #VEC Minimum Mode Maximum Mode #VEC Minimum Mode Maximum Mode 0 H'0020 - H'0021 H'0040 - H'0043 8 H'0030 - H'0031 H'0060 - H'0063 1 H'0022 - H'0023 H'0044 - H'0047 9 H'0032 - H'0033 H'0064 - H'0067 2 H'0024 - H'0025 H'0048 - H'004B A H'0034 - H'0035 H'0068 - H'006B 3 H'0026 - H'0027 H'004C - H'004F B H'0036 - H'0037 H'006C - H'006F 4 H'0028 - H'0029 H'0050 - H'0053 C H'0038 - H'0039 H'0070 - H'0073 5 H'002A - H'002B H'0054 - H'0057 D H'003A - H'003B H'0074 - H'0077 6 H'002C - H'002D H'0058 - H'005B E H'003C - H'003D H'0078 - H'007B 7 H'002E - H'002F H'005C - H'005F F H'003E - H'003F H'007C - H'007F * Examples of machine-language coding Example 1: ADD:G.B @R0,R1 EA Field OP Field Table A-1 (1) 1 1 0 1 Sz r r r 00100rrr Machine code 11010000 00100001 H'D021 Notes Machine code for ADD:G.B @Rs, Rd Sz = 0 (byte) Rs = R0, Rd = R1 Example 2: ADD:G.W @H'11:8,R1 EA Field OP Field Table A-1 (1) 0 0 0 0 Sz 1 0 1 00010001 00100rrr Machine code 00001101 00010001 00100001 H'0D1121 Notes Machine code for ADD:G.W @aa:8, Rd Sz = 1 (word) aa = H'11, Rd = R1 345 disp (L) address (L) data (L) disp disp (H) address address (H) data data (H) @Rn @(d:8, Rn) @(d:16, Rn) @-Rn @Rn+ @aa:8 @aa:16 #xx:8 #xx:16 1 1 1 0 Sz r r r 1 1 1 1 Sz r r r 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r 0 0 0 0 Sz 1 0 1 0 0 0 1 Sz 1 0 1 00000100 00001100 2 Rn Instruction Addressing mode 1 1 0 1 0 Sz r r r 1 1 0 1 Sz r r r Operation code (EA) 3 Table A-1 (a) Machine Language Coding [General Format] Arithmetic operation instruction Data transfer instruction MOV:G.B <EAs>,Rd 2 2 3 4 2 2 MOV:G.W <EAs>,Rd 2 2 3 4 2 2 MOV:G.B Rs,<EAd> 2 3 4 2 2 MOV:G.W Rs,<EAd> 2 3 4 2 2 MOV:G.B #xx:8,<EAd> 3 4 5 3 3 MOV:G.W #xx:16,<EAd> 4 5 6 4 4 LDM.W @SP+,<register list> 2 STM.W <register list>,@-SP 2 XCH.W Rs,Rd 2 2 SWAP.B Rd (MOVTPE.B Rs,<EAd>)*1 3 4 5 3 3 (MOVFPE.B <EAs>,Rd)*1 3 4 5 3 3 ADD:G.B <EAs>,Rd 2 2 3 4 2 2 ADD:G.W <EAs>,Rd 2 2 3 4 2 2 ADD:Q.B #1,<EAd>*2 2 2 3 4 2 2 ADD:Q.W #1,<EAd>*2 2 2 3 4 2 2 *2 ADD:Q.B #2,<EAd> 2 2 3 4 2 2 ADD:Q.W #2,<EAd>*2 2 2 3 4 2 2 ADD:Q.B #-1,<EAd>*2 2 2 3 4 2 2 ADD:Q.W #-1,<EAd>*2 2 2 3 4 2 2 ADD:Q.B #-2,<EAd>*2 2 2 3 4 2 2 ADD:Q.W #-2,<EAd>*2 2 2 3 4 2 2 ADDS.B <EAs>,Rd 2 2 3 4 2 2 ADDS.W <EAs>,Rd 2 2 3 4 2 2 ADDX.B <EAs>,Rd 2 2 3 4 2 2 ADDX.W <EAs>,Rd 2 2 3 4 2 2 Notes: 1. Cannot be used in the H8/520. 2. Short format instruction. 3 3 3 3 4 5 4 3 4 4 3 4 5 6 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 5 5 4 3 4 4 4 4 4 4 4 4 4 4 4 3 4 4 4 3 4 4 346 4 4 Operation code (OP) 4 100d0r r r 100d0r r r 100d0r r r 100d0r r r 00000110 00000111 00000010 00010010 10010r r r 00010000 00000000 00000000 00100r r r 00100r r r 00001000 00001000 00001001 00001001 00001100 00001100 00001101 00001101 00101r r r 00101r r r 10100r r r 10100r r r 5 data data (H) register list register list 10010r r r 10000r r r 6 data (L) Table A-1 (a) Machine Language Coding [General Format] (2) Arithmetic operation instruction DADD.B Rs,Rd SUB.B <EAs>,Rd SUB.W <EAs>,Rd SUBS.B <EAs>,Rd SUBS.W <EAs>,Rd SUBX.B <EAs>,Rd SUBX.W <EAs>,Rd DSUB.B Rs,Rd MULXU.B <EAs>,Rd MULXU.W <EAs>,Rd DIVXU.B <EAs>,Rd DIVXU.W <EAs>,Rd CMP:G.B <EAs>,Rd CMP:G.W <EAs>,Rd CMP:G.B #xx,<EAd> CMP:G.W #xx,<EAd> EXTS.B Rd EXTU.B Rd TST.B <EAd> TST.W <EAd> NEG.B <EAd> NEG.W <EAd> CLR.B <EAd> CLR.W <EAd> TAS.B <EAd> 3 2 2 2 2 2 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 address (L) data (L) address address (H) data data (H) 00001100 disp (L) disp (H) 1 1 1 0 Sz r r r 1 1 1 1 Sz r r r 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r 0 0 0 0 Sz 1 0 1 0 0 0 1 Sz 1 0 1 00000100 @(d:8, Rn) @(d:16, Rn) @-Rn @Rn+ @aa:8 @aa:16 #xx:8 #xx:16 Instruction Rn @Rn Addressing mode 1 1 0 1 0 Sz r r r 1 1 0 1 Sz r r r disp Operation code (EA) 2 3 Table A-1 (a) Machine Language Coding [General Format] (cont) 3 3 3 3 3 3 4 4 4 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 4 3 4 4 4 3 4 4 4 3 4 4 2 2 2 2 2 2 3 4 3 3 3 3 3 3 4 5 4 4 4 4 4 4 5 6 2 2 2 2 2 2 3 4 2 2 2 2 2 2 3 4 3 3 3 3 3 3 4 5 4 3 4 4 4 3 4 4 4 3 4 4 5 6 2 2 2 2 2 2 2 3 3 3 3 3 3 3 4 4 4 4 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 4 4 4 4 4 4 4 347 Operation code (OP) 4 00000000 00110r r r 00110r r r 00111r r r 00111r r r 10110r r r 10110r r r 00000000 10101r r r 10101r r r 10111r r r 10111r r r 01110r r r 01110r r r 00000100 00000101 00010001 00010010 00010110 00010110 00010100 00010100 00010011 00010011 00010111 5 1 0 1 0 0 r drdrd 6 1 0 1 1 0 r drdrd data data (H) data (L) disp (L) address (L) data (L) address address (H) data data (H) @Rn @(d:8, Rn) @(d:16, Rn) @-Rn @Rn+ @aa:8 @aa:16 #xx:8 #xx:16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Logic operation instruction Shift instruction Instruction SHAL.B <EAd> SHAL.W <EAd> SHAR.B <EAd> SHAR.W <EAd> SHLL.B <EAd> SHLL.W <EAd> SHLR.B <EAd> SHLR.W <EAd> ROTL.B <EAd> ROTL.W <EAd> ROTR.B <EAd> ROTR.W <EAd> ROTXL.B <EAd> ROTXL.W <EAd> ROTXR.B <EAd> ROTXR.W <EAd> AND.B <EAs>,Rd AND.W <EAs>,Rd OR.B <EAs>,Rd OR.W <EAs>,Rd XOR.B <EAs>,Rd XOR.W <EAs>,Rd NOT.B <EAd> NOT.W <EAd> 1 1 0 1 Sz r r r 1 1 1 0 Sz r r r 1 1 1 1 Sz r r r 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r 0 0 0 0 Sz 1 0 1 0 0 0 1 Sz 1 0 1 00000100 00001100 Rn Addressing mode 1 1 0 1 0 Sz r r r Operation code (EA) 2 3 disp disp (H) Table A-1 (a) Machine Language Coding [General Format] (cont) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 4 4 3 4 4 3 4 4 4 348 Operation code (OP) 4 00011000 00011000 00011001 00011001 00011010 00011010 00011011 00011011 00011100 00011100 00011101 00011101 00011110 00011110 00011111 00011111 01010r r r 4 01010r r r 01000r r r 4 01000r r r 01100r r r 4 01100r r r 00010101 00010101 5 6 Table A-1 (a) Machine Language Coding [General Format] (4) System control instruction Bit manipulation instruction BSET.B #xx,<EAd> BSET.W #xx,<EAd> BSET.B Rs,<EAd> BSET.W Rs,<EAd> BCLR.B #xx,<EAd> BCLR.W #xx,<EAd> BCLR.B Rs,<EAd> BCLR.W Rs,<EAd> BTST.B #xx,<EAd> BTST.W #xx,<EAd> BTST.B Rs,<EAd> BTST.W Rs,<EAd> BNOT.B #xx,<EAd> BNOT.W #xx,<EAd> BNOT.B Rs,<EAd> BNOT.W Rs,<EAd> LDC.B <EAs>,CR LDC.W<EAs>,CR STC.B CR,<EAd> STC.W CR,<EAd> ANDC.B #xx:8, CR ANDC.W #xx:16, CR ORC.B #xx:8, CR ORC.W #xx:16, CR XORC.B #xx:8, CR XORC.W #xx:16, CR 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 data (L) data (H) address (L) address address (H) data disp (L) disp (H) 1 1 0 1 Sz r r r 1 1 1 0 Sz r r r 1 1 1 1 Sz r r r 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r 0 0 0 0 Sz 1 0 1 0 0 0 1 Sz 1 0 1 00000100 00001100 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @(d:8, Rn) @(d:16, Rn) @-Rn @Rn+ @aa:8 @aa:16 #xx:8 #xx:16 Rn @Rn Instruction Addressing mode 1 1 0 1 0 Sz r r r disp Operation code (EA) 2 3 Table A-1 (a) Machine Language Coding [General Format] (cont) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Operation code (OP) 4 4 1 1 0 0 (data) 4 1 1 0 0 (data) 4 01001r r r 4 01001r r r 4 1 1 0 1 (data) 4 1 1 0 1 (data) 4 01011r r r 4 01011r r r 4 1 1 1 1 (data) 4 1 1 1 1 (data) 4 01111r r r 4 01111r r r 4 1 1 1 0 (data) 4 1 1 1 0 (data) 4 01101r r r 4 01101r r r 4 3 10001ccc 4 4 10001ccc 4 10011ccc 4 10011ccc 3 01011ccc 4 01011ccc 3 01001ccc 4 01001ccc 3 01101ccc 4 01101ccc 349 5 6 Table A-1 (b) Machine Language Coding [Special Format: Short Format] Table A-1 (b) Machine Language Coding [Special Format: Short Format] Instruction Byte MOV:E #xx:8,Rd 2 MOV:I #xx:16,Rd MOV:L.B @aa:8,Rd MOV:L.W @aa:8,Rd MOV:S.B Rs,@aa:8 MOV:S.W Rs,@aa:8 MOV:F.B @(d:8,R6),Rd 3 2 2 2 2 2 MOV:F.W @(d:8,R6),Rd MOV:F.B Rs,@(d:8,R6) 2 2 MOV:F.W Rs,@(d:8,R6) CMP:E #xx:8,Rd CMP:I #xx:16,Rd 2 2 3 Operation Code 1 01010r 01011r 01100r 01101r 01110r 01111r 10000r r r r r r r r r r r r r r r 10001r 10010r 10011r 01000r 01001r r r r r r r r r r r 2 data data (H) address (L) address (L) address (L) address (L) disp 3 data (L) disp disp disp data data (H) 350 data (L) 4 Table A-1 (c) Machine Language Coding [Special Format: Branch Instructions] (1) Table A-1 (c) Machine Language Coding [Special Format: Branch Instructions] Instruction Bcc d:8 Bcc d:16 JMP @Rn JMP @aa:16 BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Operation Code Byte 2 3 2 3 1 00100000 00100001 00100010 00100011 00100100 00100101 00100110 00100111 00101000 00101001 00101010 00101011 00101100 00101101 00101110 00101111 00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 00111010 .00111011 00111100 00111101 00111110 00111111 00010001 00010000 2 disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) 11010r r r address (H) 351 3 disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp( L) disp (L) disp (L) address (L) 4 Table A-1 (c) Machine Language Coding [Special Format: Branch Instructions] (2) Table A-1 (c) Machine Language Coding [Special Format: Branch Instructions] (cont) Instruction Operation Code Byte JMP @(d:8,Rn) 3 1 00010001 2 11100r r r JMP @(d:16,Rn) BSR d:8 BSR d:16 JSR @Rn JSR @aa:16 JSR @(d:8,Rn) JSR @(d:16,Rn) RTS RTD #xx:8 4 2 3 2 3 3 4 1 2 00010001 00001110 00011110 00010001 00011000 00010001 00010001 00011001 00010100 11110r r disp disp(H) 11011r r address(H) 11101r r 11111r r RTD #xx:16 SCB/cc Rn, disp SCB/F SCB/NE 3 3 00011100 00000001 00000110 data (H) 10111r r r 10111r r r data (L) disp disp 10111r r r page 11000r r r page 11001r r r 00011001 disp address (H) address (L) address (H) address (L) 00010100 00011100 data data (H) data (L) SCB/EQ PJMP @aa:24 PJMP @Rn PJSR @aa:24 PJSR @Rn PRTS 4 2 4 2 2 00000111 00010011 00010001 00000011 00010001 00010001 PRTD #xx:8 PRTD #xx:16 3 4 00010001 00010001 r 3 4 disp disp (H) disp (L) disp (L) r r r address (L) disp disp (H) disp (L) data Table A-1(d)(d)Machine Machine Language Coding System Control Instructions] Table A-1 Language Coding [Special[Special Format: Format: System Control Instructions] Instruction TRAPA #xx TRAP/VS RTE LINK FP,#xx:8 LINK FP,#xx:16 UNLK FP SLEEP NOP Operation Code Byte 2 1 1 2 3 1 1 1 1 00001000 00001001 00001010 00010111 00011111 00001111 00011010 00000000 2 0 0 0 1 #VEC data data (H) 352 3 data (L) 4 A.4 Instruction Execution Cycles Tables A-7 (1) through (6) list the number of cycles required by the CPU to execute each instruction in each addressing mode. The meaning of the symbols in the tables is explained below. The values of I, J, and K are used to calculate the number of execution cycles when off-chip memory is accessed for an instruction fetch or operand read/write. The formulas for these calculations are given next. A.4.1 Calculation of Instruction Execution States Instruction Fetch Operand Read/Write Number of States On-chip memory*1 On-chip memory or general register (Value given in table A-7) + (Value in table A-8) On-chip supporting module Byte (Value in table A-7) + (Value in table A-8) + I or off-chip memory*2 Word (Value in table A-7) + (Value in table A-8) + 2 I Off-chip memory*2 On-chip memory or general register (Value given in table A-7) + 2(J + K) On-chip supporting module Byte (Value in table A-7) + I + 2(J + K) or off-chip memory*2 Word (Value in table A-7) + 2(I + J + K) Notes: 1. When the instruction is fetched from on-chip memory (ROM or RAM), the number of execution states varies by 1 or 2 depending of whether the instruction is stored at an even or odd address. This difference must be noted when software is used for timing, and in other cases in which the exact number of states is important. 2. If wait states are inserted in access to external memory, add the necessary number of cycles. 358 A.4.2 Tables of Instruction Execution Cycles Tables A-7 (1) through (6) should be read as shown below: J + K: Number of instruction fetch cycles. Addressing Mode @(d:16,Rn) @-Rn @Rn+ @aa:8 @aa:16 #xx:8 #xx:16 K J @(d:8,Rn) I @Rn Instruction Rn I: Total number of bytes written and read when operand is in memory. 1 1 2 3 1 1 2 3 2 3 3 ADD.B 1 1 2 5 5 6 5 6 5 6 ADD.W 2 1 2 5 5 6 5 6 5 6 ADD:Q.B 2 1 2 7 7 8 7 8 7 8 ADD:Q.W 4 1 2 7 7 8 7 8 7 8 2 4 DADD Shading in the I column means the operand cannot be in memory. 4 Shading indicates addressing modes that cannot be used with this instruction. 359 * Examples of Calculation of Number of States Required for Execution (Example 1) Instruction fetch from on-chip memory Operand Start Assembler Notation Number Read/Write Addr. Address Code Mnemonic Table A-7 + Table A-8 of States On-chip memory Even H'0100 H'D821 ADD:G.W @R0, R1 5+1 6 or general register Odd H'0101 H'D821 ADD:G.W @R0, R1 5+0 5 Table A-7 + Number (Example 2) Instruction fetch from on-chip memory Operand Start Assembler Notation Read/Write Addr. Address Code Mnemonic Table A-8 + 2I of States On-chip supporting Even H'FC00 H'11D8 JSR @R0 9+0+2x2 13 module or external Odd H'FC01 H'11D8 JSR @R0 9+1+2x2 14 memory (word) (Example 3) Instruction fetch from external memory Operand Assembler Notation Number Read/Write Address Code Mnemonic Table A-7 + 2(J + K) of States On-chip memory or general H'9002 ADD:G.W @R0, R1 5 + 2 x (1 + 1) 9 H'D821 register 360 Table A-7 Instruction Execution Cycles (1) Table A-7 Instruction Execution Cycles (1) @(d:16,Rn) @-Rn @Rn+ @aa:8 @aa:16 #xx:8 #xx:16 J @(d:8,Rn) I @Rn Instruction Rn Addressing Mode K 1 1 2 3 1 1 2 3 2 3 3 ADD:G.B <EAs>, Rd 1 1 2 5 5 6 5 6 5 6 ADD:G.W <EAs>, Rd 2 1 2 5 5 6 5 6 5 6 ADD:Q.B #xx, <EAd> 2 1 2 7 7 8 7 8 7 8 ADD:Q.W #xx, <EAd> 4 1 2 7 7 8 7 8 7 8 ADDS.B <EAs>, Rd 1 1 3 5 5 6 5 6 5 6 ADDS.W <EAs>, Rd 2 1 3 5 5 6 5 6 5 6 ADDX.B <EAs>, Rd 1 1 2 5 5 6 5 6 5 6 ADDX.W <EAs>, Rd 2 1 2 5 5 6 5 6 5 6 AND.B <EAs>, Rd 1 1 2 5 5 6 5 6 5 6 AND.W <EAs>, Rd 2 1 2 5 5 6 5 6 5 6 ANDC #xx, CR 1 2 1 4 7 7 8 7 8 7 8 BCLR.W #xx, <EAd>* 4 1 4 7 7 8 7 8 7 8 BNOT.B #xx, <EAd>* 2 1 4 7 7 8 7 8 7 8 BNOT.W #xx, <EAd>* 4 1 4 7 7 8 7 8 7 8 BSET.B #xx, <EAd>* 2 1 4 7 7 8 7 8 7 8 BSET.W #xx, <EAd>* 4 1 4 7 7 8 7 8 7 8 BTST.B #xx, <EAd>* 1 1 3 5 5 6 5 6 5 6 BTST.W #xx, <EAd>* 2 1 3 5 5 6 5 6 5 6 CLR.B <EAd> 1 1 2 5 5 6 5 6 5 6 CLR.W <EAd> 2 1 2 5 5 6 5 6 5 6 CMP:G.B <EAs>, Rd 1 1 2 5 5 6 5 6 5 6 CMP:G.W <EAs>, Rd 2 1 2 5 5 6 5 6 5 6 CMP:G.B #xx:8,<EA> 1 2 6 6 7 6 7 6 7 CMP:G.B #xx:16,<EA> 2 3 7 7 8 7 8 7 8 361 3 4 3 4 3 4 5 BCLR.B #xx, <EAd>* Note: * Rs can be specified in the source operand. 4 9 3 4 Table A-7 Instruction Execution Cycles (2) Table A-7 Instruction Execution Cycles (2) @(d:16,Rn) @-Rn @Rn+ @aa:8 @aa:16 #xx:8 #xx:16 J @(d:8,Rn) I @Rn Instruction Rn Addressing Mode K 1 1 2 3 1 1 2 3 2 3 CMP:E #xx:8,Rd 0 2 CMP:I #xx:16,Rd 0 DADD Rs, Rd 2 4 3 DIVXU.B <EAs>, Rd 1 1 20 23 23 24 23 24 23 24 21 DIVXU.W <EAs>, Rd 2 1 26 29 29 30 29 30 29 30 DSUB Rs, Rd EXTS Rd 2 1 4 3 EXTU Rd 1 3 LDC.B <EAs>, CR 1 1 3 6 6 7 6 7 6 7 LDC.W <EAs>, CR 2 1 4 7 7 8 7 8 7 8 MOV:G.B 1 1 2 5 5 6 5 6 5 6 MOV:G.W 2 1 2 5 5 6 5 6 5 6 MOV:G.B #xx:8,<EAd> 1 2 7 7 8 7 8 7 8 MOV:G.W #xx:16,<EAd> 2 3 8 8 9 8 9 8 9 MOV:E #xx:8,Rd 0 MOV:I #xx:16,Rd 0 4 6 3 4 2 3 MOV:L.B @aa:8,Rd 1 0 5 MOV:L.W @aa:8,Rd 2 0 5 MOV:S.B Rs,@aa:8 1 0 5 MOV:S.W Rs,@aa:8 2 0 5 MOV:F.B @(d:8, R6), Rd 1 0 5 MOV:F.W @(d:8, R6), Rd 2 0 5 MOV:F.B Rs, @(d:8, R6) 1 0 5 MOV:F.W Rs, @(d:8, R6) 2 0 5 362 28 Table A-7 Instruction Execution Cycles (3) Table A-7 Instruction Execution Cycles (3) @(d:8,Rn) @(d:16,Rn) @-Rn @Rn+ @aa:8 @aa:16 #xx:8 #xx:16 K 1 @Rn Rn Addressing Mode 1 2 3 1 1 2 3 2 3 Instruction I (MOVFPE <EAs>, Rd)* 0 2 13 13 14 13 14 13 14 (MOVTPE Rs, <EAd>)* 0 2 20 20 21 20 21 20 21 13 13 14 13 14 13 14 J MULXU.B <EAs>, Rd 1 1 20 20 21 20 21 20 21 16 19 19 20 19 20 19 20 18 MULXU.W <EAs>, Rd 2 1 23 25 25 26 25 26 25 26 NEG.B <EAd> 2 1 2 7 7 8 7 8 7 8 NEG.W <EAd> 4 1 2 7 7 8 7 8 7 8 NOT.B <EAd> 2 1 2 7 7 8 7 8 7 8 NOT.W <EAd> 4 1 2 7 7 8 7 8 7 8 OR.B <EAs>, Rd 1 1 2 5 5 6 5 6 5 6 OR.W <EAs>, Rd 2 1 2 5 5 6 5 6 5 6 ORC #xx, CR 1 25 3 4 5 ROTL.B <EAd> 2 1 2 7 7 8 7 8 7 8 ROTL.W <EAd> 4 1 2 7 7 8 7 8 7 8 ROTR.B <EAd> 2 1 2 7 7 8 7 8 7 8 ROTR.W <EAd> 4 1 2 7 7 8 7 8 7 8 ROTXL.B <EAd> 2 1 2 7 7 8 7 8 7 8 ROTXL.W <EAd> 4 1 2 7 7 8 7 8 7 8 ROTXR.B <EAd> 2 1 2 7 7 8 7 8 7 8 ROTXR.W <EAd> 4 1 2 7 7 8 7 8 7 8 SHAL.B <EAd> 2 1 2 7 7 8 7 8 7 8 SHAL.W <EAd> 4 1 2 7 7 8 7 8 7 8 SHAR.B <EAd> SHAR.W <EAd> 2 4 1 1 2 2 7 7 7 7 8 8 7 7 8 8 7 7 8 8 SHLL.B <EAd> 2 1 2 7 7 8 7 8 7 8 SHLL.W <EAd> 4 1 2 7 7 8 7 8 7 8 9 Note: * MOVFPE and MOVTPE are executed synchronous with the E-clock, so the number of execution states will change depending on timing of the execution. 363 Table A-7 Instruction Execution Cycles (4) Table A-7 Instruction Execution Cycles (4) @(d:16,Rn) @-Rn @Rn+ @aa:8 @aa:16 #xx:8 #xx:16 J @(d:8,Rn) I @Rn Instruction Rn Addressing Mode K 1 1 2 3 1 1 2 3 2 3 SHLR.B <EAd> 2 1 2 7 7 8 7 8 7 8 SHLR.W <EAd> 4 1 2 7 7 8 7 8 7 8 STC.B CR, <EAd> 1 1 4 7 7 8 7 8 7 8 STC.W CR, <EAd> 2 1 4 7 7 8 7 8 7 8 SUB.B <EAs>, Rd 1 1 2 5 5 6 5 6 5 6 SUB.W <EAs>, Rd 2 1 2 5 5 6 5 6 5 6 SUBS.B <EAs>, Rd 1 1 3 5 5 6 5 6 5 6 SUBS.W <EAs>, Rd 2 1 3 5 5 6 5 6 5 6 SUBX.B <EAs>, Rd 1 1 2 5 5 6 5 6 5 6 SUBX.W <EAs>, Rd 2 1 2 5 5 6 5 6 5 6 1 3 SWAP Rd TAS <EAd> 2 1 4 7 7 8 7 8 7 8 TST.B <EAd> 1 1 2 5 5 6 5 6 5 6 TST.W <EAd> 2 1 2 5 5 6 5 6 5 6 1 4 XCH Rs, Rd XOR.B <EAs>, Rd 1 1 2 5 6 5 5 6 5 6 XOR.W <EAs>, Rd 2 1 2 5 6 5 5 6 5 6 XORC #xx, CR 1 3 4 3 4 3 4 3 4 5 9 * DIVXU.B Zero divide, minimum mode DIVXU.B Zero divide, maximum mode DIVXU.W Zero divide, minimum mode DIVXU.W Zero divide, maximum mode DIVXU.B Overflow DIVXU.W Overflow * 6 7 10 11 6 8 10 12 1 2 For register and immediate operands For memory operand 364 1 20 23 23 24 23 24 23 24 21 1 25 28 28 29 28 29 28 29 21 1 20 23 23 24 23 24 23 24 27 1 25 28 28 29 28 29 28 29 27 1 8 11 11 12 11 12 11 12 9 1 8 11 11 12 11 12 11 12 10 Table A-7 Instruction Execution Cycles (5) Instruction Bcc d:8 Bcc d:16 BSR JMP JSR LDM LINK NOP RTD RTE (Condition) Condition false, branch not taken Condition true, branch taken Condition false, branch not taken Condition true, branch taken d:8 d:16 @aa:16 @Rn @(d:8, Rn) @(d:16, Rn) Execution Cycles SLEEP J + K 2 5 3 6 9 9 7 6 7 8 2 2 4 5 5 5 5 6 @aa:16 @Rn @(d:8, Rn) @(d:16, Rn) 9 9 9 10 6 + 4n* 6 7 2 9 9 13 15 8 2 2 2 2 2n 2 2 5 5 5 6 2 2 3 1 4 5 4 4 4 3 7 3 7 #xx:8 #xx:16 #xx:8 #xx:16 Minimum mode Maximum mode RTS SCB I Condition false, branch not taken Count = -1, branch not taken Other than the above, branch taken Cycles preceding transition to powerdown mode STM 3 3 6 0 3 4 8 2 6 + 3n* 2n 2 6 10 4 4 6 10 1 4 4 TRAPA Minimum mode Maximum mode 17 22 TRAP/VS V = 0, branch not taken V = 1, branch taken, minimum mode V = 1, branch taken, maximum mode 3 18 23 Note: * n is the number of registers specified in the register list. 365 2 2 4 6 2 Table A-7 Instruction Execution Cycles (6) Instruction UNLK PJMP PJSR PRTS PRTD (Condition) @aa:24 @Rn @aa:24 @Rn #xx:8 #xx:16 Execution Cycles I J + K 5 2 9 8 15 13 12 13 13 4 4 4 4 4 1 6 5 6 5 5 5 6 Table A-8 (a) Adjusted Value (Branch instructions) Instruction Address Adjusted Value BSR, JMP, JSR, RTS, RTD, RTE even 0 TRAPA, PJMP, PJSR, PRTS, PRTD odd 1 BCC, SCB, TRAP/VS (When branches) even 0 odd 1 @(d:8,Rn) @(d:16,Rn) @-Rn @Rn+ @aa:8 @aa:16 even 1 1 1 1 1 1 1 odd 1 1 1 1 1 1 1 even 2 0 2 2 2 0 2 odd 0 2 0 0 0 2 0 #xx:8 #xx:16 Start address even 0 1 0 1 1 1 0 1 0 0 odd 0 0 1 0 0 0 1 0 0 0 Rn Instruction @Rn Table A-8 (b) Adjusted Value (Other instructions by addressing modes) MOV.B #xx:8, <EA> MOV.W #xx:16, <EA> Instructions other than above Table A-8 (b) 366 Appendix B Register Field B.1 Register Addresses and Bit Names Addr. (last Register Bit Names byte) Name Bit 7 H'80 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 1 H'81 P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Port 2 H'82 P1DR P17 P16 P15 P14 P13 P12 P11 P10 Port 1 H'83 P2DR P27 P26 P25 P24 P23 P22 P21 P20 Port 2 H'84 P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3 H'85 P4DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Port 4 H'86 P3DR P37 P36 P35 P34 P33 P32 P31 P30 Port 3 H'87 P4DR P47 P46 P45 P44 P43 P42 P41 P40 Port 4 H'88 P5DDR P57DDR P56DDR P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR Port 5 H'89 -- -- -- -- -- -- -- -- -- -- H'8A P5DR P57 P56 P55 P54 P53 P52 P51 P50 Port 5 H'8B P6DR P67* P66* P65* P64* P63 P62 P61 P60 Port 6 H'8C P7DDR -- oOE P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR Port 7 H'8D -- -- -- -- -- -- -- -- -- -- H'8E P7DR -- -- P75 P74 P73 P72 P71 P70 Port 7 H'8F -- -- -- -- -- -- -- -- -- -- H'90 TCR ICIE OCIEB OCIEA OVIE OEB OEA CKS1 CKS0 FRT1 H'91 TCSR ICF OCFB OCFA OVF OLVLB OLVLA IEDG CCLRA H'92 FRC (H) H'93 FRC (L) H'94 OCRA (H) H'95 OCRA (L) H'96 OCRB (H) H'97 OCRB (L) H'98 ICR (H) H'99 ICR (L) H'9A -- -- -- -- -- -- -- -- -- H'9B -- -- -- -- -- -- -- -- -- H'9C -- -- -- -- -- -- -- -- -- H'9D -- -- -- -- -- -- -- -- -- H'9E -- -- -- -- -- -- -- -- -- H'9F -- -- -- -- -- -- -- -- -- Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module (Continued on next page) Notes: FRT1: 16-bit Free-Running Timer channel 1 * CP-68 package only. 367 (Continued from preceding page) Addr. (last Register Bit Names byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'A0 TCR ICIE OCIEB OCIEA OVIE OEB OEA CKS1 CKS0 FRT2 H'A1 TCSR ICF OCFB OCFA OVF OLVLB OLVLA IEDG CCLRA H'A2 FRC (H) H'A3 FRC (L) H'A4 OCRA (H) H'A5 OCRA (L) H'A6 OCRB (H) H'A7 OCRB (L) H'A8 ICR (H) H'A9 ICR (L) H'AA -- -- -- -- -- -- -- -- -- H'AB -- -- -- -- -- -- -- -- -- H'AC -- -- -- -- -- -- -- -- -- H'AD -- -- -- -- -- -- -- -- -- H'AE -- -- -- -- -- -- -- -- -- H'AF -- -- -- -- -- -- -- -- -- H'B0 -- -- -- -- -- -- -- -- -- H'B1 -- -- -- -- -- -- -- -- -- H'B2 -- -- -- -- -- -- -- -- -- H'B3 -- -- -- -- -- -- -- -- -- H'B4 -- -- -- -- -- -- -- -- -- H'B5 -- -- -- -- -- -- -- -- -- H'B6 -- -- -- -- -- -- -- -- -- H'B7 -- -- -- -- -- -- -- -- -- H'B8 -- -- -- -- -- -- -- -- -- H'B9 -- -- -- -- -- -- -- -- -- H'BA -- -- -- -- -- -- -- -- -- H'BB -- -- -- -- -- -- -- -- -- H'BC -- -- -- -- -- -- -- -- -- H'BD -- -- -- -- -- -- -- -- -- H'BE -- -- -- -- -- -- -- -- -- H'BF -- -- -- -- -- -- -- -- -- -- (Continued on next page) Note: FRT2: 16-bit Free-Running Timer channel 2 368 (Continued from preceding page) Addr. (last Register Bit Names byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'C0 SMR C/A CHR PE O/E STOP -- CKS1 CKS0 SCI2 H'C1 BRR H'C2 SCR TIE RIE TE RE -- -- CKE1 CKE0 H'C3 TDR -- -- -- -- -- -- -- -- H'C4 SSR TDRE RDRF ORER FER PER -- -- -- H'C5 RDR H'C6 -- -- -- -- -- -- -- -- -- H'C7 -- -- -- -- -- -- -- -- -- H'C8 -- -- -- -- -- -- -- -- -- H'C9 -- -- -- -- -- -- -- -- -- H'CA -- -- -- -- -- -- -- -- -- H'CB -- -- -- -- -- -- -- -- -- H'CC -- -- -- -- -- -- -- -- -- H'CD -- -- -- -- -- -- -- -- -- H'CE -- -- -- -- -- -- -- -- -- H'CF -- -- -- -- -- -- -- -- -- H'D0 TCR CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 H'D1 TCSR CMFB CMFA OVF -- OS3 OS2 OS1 OS0 H'D2 TCORA H'D3 TCORB H'D4 TCNT H'D5 -- -- -- -- -- -- -- -- -- H'D6 -- -- -- -- -- -- -- -- -- H'D7 -- -- -- -- -- -- -- -- -- H'D8 SMR C/A CHR PE O/E STOP -- CKS1 CKS0 H'D9 BRR H'DA SCR TIE RIE TE RE -- -- CKE1 CKE0 H'DB TDR H'DC SSR TDRE RDRF ORER FER PER -- -- -- H'DD RDR H'DE -- -- -- -- -- -- -- -- -- H'DF -- -- -- -- -- -- -- -- -- -- TMR SCI1 (Continued on next page) Notes: TMR: 8-Bit Timer SCI1: Serial Communication Interface channel 1 SCI2: Serial Communication Interface channel 2 369 (Continued from preceding page) Addr. (last Register byte) Name Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module A/D H'E0 ADDRA (H) AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'E1 ADDRA (L) AD1 AD0 -- -- -- -- -- -- H'E2 ADDRB (H) AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'E3 ADDRB (L) AD1 AD0 -- -- -- -- -- -- H'E4 ADDRC (H) AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'E5 ADDRC (L) AD1 AD0 -- -- -- -- -- -- H'E6 ADDRD (H) AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'E7 ADDRD (L) AD1 AD0 -- -- -- -- -- -- H'E8 ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0 H'E9 ADCR TRGE -- -- -- -- -- -- -- H'EA -- -- -- -- -- -- -- -- -- H'EB -- -- -- -- -- -- -- -- -- WT/IT TME -- -- CKS2 CKS1 CKS0 WDT -- H'EC Password OVF TCSR* H'ED TCSR/TCNT* TCNT* H'EE -- -- -- -- -- -- -- -- -- H'EF -- -- -- -- -- -- -- -- -- (Continued on next page) Notes: A/D: Analog-to-Digital converter WDT: Watchdog Timer * Read addresses are shown. Write addresses of both TCSR and TCNT are H'FFED, preceded by a password at H'FFEC. See section 13.2.3, "Notes on Register Access", for details. 370 (Continued from preceding page) Addr. (last Register Bit Names byte) Name Bit 7 H'F0 IPRA -- IRQ0 priority -- IRQ1 - IRQ7 priority H'F1 IPRB -- FRT1 interrupt priority -- FRT2 interrupt priority H'F2 IPRC -- TMR interrupt priority -- SCI1 interrupt priority H'F3 IPRD -- SCI2 interrupt priority -- A/D interrupt priority H'F4 DTEA -- -- -- IRQ0 -- IRQ3 IRQ2 IRQ1 H'F5 DTEB -- OCIB1 OCIA1 ICI -- OCIB OCIA ICI H'F6 DTEC -- -- CMIB CMIA -- TXI RXI -- H'F7 DTED -- TXI RXI -- -- -- -- ADI H'F8 WCR -- -- -- -- WMS1 WMS0 WC1 WC0 WSC H'F9 RAMCR RAME -- -- -- -- -- -- -- RAM H'FA MDCR -- -- -- -- -- MDS2 MDS1 MDS0 H'FB SBYCR SSBY -- -- -- -- -- -- -- H'FC NMICR -- -- -- -- -- -- -- NMIEG H'FD IRQCR IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E H'FE Password* H'FF RSTCSR WRST Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module INTC INTC WDT RSTOE -- -- -- -- -- -- Notes: INTC: Interrupt Controller WSC: Wait State Controller WDT: Watchdog Timer * The password is required for write access to RSTCSR. See section 12.2.3 for details. 371 B.2 Register Descriptions * How to Read the Register Descriptions WCR--Wait-State Control Register Acronym of the register H'FFF8 Register name WSC Address to which the register is mapped Bit numbers Initial bit values Bit Name of the on-chip supporting module Names of the bits. Dashes (--) indicate reserved bits. 7 6 5 4 3 2 1 0 -- -- -- -- WMS1 WMS0 WC1 WC0 Initial value 1 1 1 1 0 0 1 1 Read/Write -- -- -- -- R/W R/W R/W R/W Type of access permitted Wait Count 1 and 0 R Read only W Write only 0 0 No wait states (TW) are inserted. 0 1 1 wait state is inserted. R/W Both read and write 1 0 2 wait states are inserted. 1 1 3 wait states are inserted. Full name of the bit Wait Mode Select 1 and 0 0 0 Programmable wait mode 0 1 No wait states are inserted, regardless Functions of the bit settings of the wait count. 1 0 Pin wait mode 1 1 Pin auto-wait mode 372 P1DDR--Port 1 Data Direction Register Bit 7 6 5 H'FF80 4 3 Port 1 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 1 Input/Output Selection P1DR--Port 1 Data Register Bit 0 Input port 1 Output port H'FF82 Port 1 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P2DDR--Port 2 Data Direction Register Bit 7 6 5 H'FF81 4 3 Port 2 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 2 Input/Output Selection 373 0 Input port 1 Output port P2DR--Port 2 Data Register Bit H'FF83 Port 2 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P3DDR--Port 3 Data Direction Register Bit 7 6 5 H'FF84 4 3 Port 3 2 1 0 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 3 Input/Output Selection P3DR--Port 3 Data Register Bit 0 Input port 1 Output port H'FF86 Port 3 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P4DDR--Port 4 Data Direction Register Bit 7 6 5 H'FF85 4 3 Port 4 2 1 0 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 4 Input/Output Selection 374 0 Input port 1 Output port P4DR--Port 4 Data Register Bit H'FF87 Port 4 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P5DDR--Port 5 Data Direction Register Bit 7 6 5 H'FF88 4 3 Port 5 2 1 0 P57DDR P56DDR P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 5 Input/Output Selection P5DR--Port 5 Data Register Bit 0 Input port 1 Output port H'FF8A Port 5 7 6 5 4 3 2 1 0 P57 P56 P55 P54 P53 P52 P51 P50 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 375 P6DR--Port 6 Data Register Bit Read/Write H'FF8B Port 6 7 6 5 4 3 2 1 0 P67* P66* P65* P64* P63 P62 P61 P60 R R R R R R R R Note: * CP-68 package only. P7DDR--Port 7 Data Direction Register Bit 5 H'FF8C 4 3 Port 7 7 6 2 1 0 -- oOE Initial value -- 1 0 0 0 0 0 0 Read/Write -- W W W W W W W P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR Port 7 Input/Output Selection 0 Input port 1 Output port o Clock Output Selection 0 P57 is not used as a o clock pin. 1 P57 is used as a o clock pin. P7DR--Port 7 Data Register Bit H'FF8E Port 7 7 6 5 4 3 2 1 0 -- -- P75 P74 P73 P72 P71 P70 Initial value -- -- 0 0 0 0 0 0 Read/Write -- -- R/W R/W R/W R/W R/W R/W 376 TCR--Timer Control Register Bit H'FF90 FRT1 7 6 5 4 3 2 1 0 ICIE OCIEB OCIEA OVIE OEB OEA CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 0 Internal clock source: o/4 0 1 Internal clock source: o/8 1 0 Internal clock source: o/32 1 1 External clock source: counted on rising edge Output Enable A 0 Compare-A output is disabled. 1 Compare-A output is enabled. Output Enable B 0 Compare-B output is disabled. 1 Compare-B output is enabled. Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Output Compare Interrupt Enable A 0 Compare-match A interrupt request is disabled. 1 Compare-match A interrupt request is enabled. Output Compare Interrupt Enable B 0 Compare-match B interrupt request is disabled. 1 Compare-match B interrupt request is enabled. Input Capture Interrupt Enable 0 Input capture interrupt request is disabled. 1 Input capture interrupt request is enabled. 377 TCSR--Timer Control/Status Register Bit H'FF91 FRT1 7 6 5 4 3 2 1 0 ICF OCFB OCFA OVF OLVLB OLVLA IEDG CCLRA Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W Counter Clear A 0 FRC count is not cleared. 1 FRC count is cleared by compare-match A. Input Edge Select 0 Count is captured on falling edge of input capture signal (FTI). 1 Count is captured on rising edge of input capture signal. Output Level A 0 Compare-match A causes 0 output. 1 Compare-match A causes 1 output. Output Level B 0 Compare-match B causes 0 output. 1 Compare-match B causes 1 output. Timer Overflow 0 Cleared from 1 to 0 when CPU reads OVF = 1, then writes 0 in OVF. 1 Set to 1 when FRC changes from H'FFFF to H'0000. Output Compare Flag A 0 Cleared from 1 to 0 when: 1. CPU reads OCFA = 1, then writes 0 in OCFA. 2. OCIA interrupt is served by DTC. 1 Set to 1 when FRC = OCRA. Output Compare Flag B 0 Cleared from 1 to 0 when: 1. CPU reads OCFB = 1, then writes 0 in OCFB. 2. OCIB interrupt is served by DTC. 1 Set to 1 when FRC = OCRB. Input Capture Flag 0 Cleared from 1 to 0 when: 1. CPU reads ICF = 1, then writes 0 in ICF. 2. ICI interrupt is served by DTC. 1 Set to 1 when input capture signal is received and FRC count is copied to ICR. Note: * Only writing of a 0 to clear the flag is enabled. 378 FRC (H and L)--Free-Running Counter H'FF92, H'FF93 FRT1 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Count value OCRA (H and L)--Output Compare Register A H'FF94, H'FF95 FRT1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Continually compared with FRC. OCFA is set to 1 when OCRA = FRC. OCRB (H and L)--Output Compare Register B H'FF96, H'FF97 FRT1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Continually compared with FRC. OCFB is set to 1 when OCRB = FRC. ICR (H and L)--Input Capture Register H'FF98, H'FF99 FRT1 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Contains FRC count captured when external input capture signal changes. 379 TCR--Timer Control Register Bit H'FFA0 FRT2 7 6 5 4 3 2 1 0 ICIE OCIEB OCIEA OVIE OEB OEA CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for FRT1. TCSR--Timer Control/Status Register Bit H'FFA1 FRT2 7 6 5 4 3 2 1 0 ICF OCFB OCFA OVF OLVLB OLVLA IEDG CCLRA Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W Note: Bit functions are the same as for FRT1. * Only writing of a 0 to clear the flag is enabled. FRC (H and L)--Free-Running Counter H'FFA2, H'FFA3 FRT2 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for FRT1. 380 OCRA (H and L)--Output Compare Register A H'FFA4, H'FFA5 FRT2 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for FRT1. OCRB (H and L)--Output Compare Register B H'FFA6, H'FFA7 FRT2 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for FRT1. ICR (H and L)--Input Capture Register H'FFA8, H'FFA9 FRT2 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Note: Bit functions are the same as for FRT1. 381 TCR--Timer Control Register Bit H'FFD0 TMR 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 0 0 No clock source; timer stops. 0 0 1 Internal clock source: o/8. 0 1 0 Internal clock source: o/64. 0 1 1 Internal clock source: o/1024. 1 0 0 No clock source; timer stops. 1 0 1 External clock source, counted on rising edge. 1 1 0 External clock source, counted on falling edge. 1 1 1 External clock source, counted on both rising and falling edges. Counter Clear 0 0 Counter is not cleared. 0 1 Cleared by compare-match A. 1 0 Cleared by compare-match B. 1 1 Cleared on rising edge of external reset input. Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Compare-Match Interrupt Enable A 0 Compare-match A interrupt request is disabled. 1 Compare-match A interrupt request is enabled. Compare-Match Interrupt Enable B 0 Compare-match B interrupt request is disabled. 1 Compare-match B interrupt request is enabled. 382 TCSR--Timer Control/Status Register Bit H'FFD1 TMR 7 6 5 4 3 2 1 0 CMFB CMFA OVF -- OS3*2 OS2*2 OS1*2 OS0*2 Initial value 0 0 0 1 0 0 0 0 Read/Write R/(W)*1 R/(W)*1 R/(W)*1 -- R/W R/W R/W R/W Output Select 0 0 No change on compare-match A. 0 1 Output 0 on compare-match A. 1 0 Output 1 on compare-match A. 1 1 Invert (toggle) output on comparematch A. Output Select 0 0 No change on compare-match B. 0 1 Output 0 on compare-match B. 1 0 Output 1 on compare-match B. 1 1 Invert (toggle) output on compare-match B. Timer Overflow Flag 0 Cleared from 1 to 0 when CPU reads OVF = 1, then writes 0 in OVF. 1 Set to 1 when TCNT changes from H'FF to H'00. Compare-Match Flag A 0 Cleared from 1 to 0 when: 1. CPU reads CMFA = 1, then writes 0 in CMFA. 2. CMIA interrupt is served by the DTC. 1 Set to 1 when TCNT = TCORA. Compare-Match Flag B 0 Cleared from 1 to 0 when: 1. CPU reads CMFB = 1, then writes 0 in CMFB. 2. CMIB interrupt is served by the DTC. 1 Set to 1 when TCNT = CMFB. Notes: 1. Only writing of 0 to clear the flag is enabled. 2. When all four bits (OS3 to OS0) are cleared to 0, output is disabled. 383 TCORA--Time Constant Register A H'FFD2 TMR Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The CMFA bit is set to 1 when TCORA = TCNT. TCORB--Time Constant Register B H'FFD3 TMR Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The CMFB bit is set to 1 when TCORB = TCNT. TCNT--Timer Counter H'FFD4 TMR Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Count value 384 SMR--Serial Mode Register Bit H'FFD8 SCI1 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP -- CKS1 CKS0 Initial value 0 0 0 0 0 1 0 0 Read/Write R/W R/W R/W R/W R/W -- R/W R/W Clock Select 0 0 o clock 0 1 o/4 clock 1 0 o/16 clock 1 1 o/64 clock Stop Bit Length 0 One stop bit 1 Two stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Transmit: No parity bit added. Receive: Parity bit not checked. 1 Transmit: Parity bit added. Receive: Parity bit checked. Character Length 0 8-Bit data length 1 7-Bit data length Communication Mode 0 Asynchronous 1 Synchronous 385 BRR--Bit Rate Register H'FFD9 SCI1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Constant that determines the baud rate SCR--Serial Control Register Bit H'FFDA SCI1 7 6 5 4 3 2 1 0 TIE RIE TE RE -- -- CKE1 CKE0 Initial value 0 0 0 0 1 1 0 0 Read/Write R/W R/W R/W R/W -- -- R/W R/W Clock Enable 0 0 SCK pin is not used. 1 SCK pin is used for output. Clock Enable 1 0 Internal clock 1 External clock, input at SCK pin Receive Enable 0 Receive disabled 1 Receive enabled Transmit Enable 0 Transmit disabled 1 Transmit enabled Receive Interrupt Enable 0 Receive interrupt request (RXI) is disabled. 1 Receive interrupt request (RXI) is enabled. Transmit Interrupt Enable 0 Transmit interrupt request (TXI) is disabled. 1 Transmit interrupt request (TXI) is enabled. 386 TDR--Transmit Data Register H'FFDB SCI1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Transmit data 387 SSR--Serial Status Register Bit H'FFDC SCI1 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER -- -- -- Initial value 1 0 0 0 0 1 1 1 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* -- -- -- Parity Error 0 Cleared from 1 to 0 when: 1. CPU reads PER = 1, then writes 0 in PER. 2. The chip is reset or enters a standby mode. 1 Set to 1 when a parity error occurs (parity of receive data does not match parity selected by O/E bit in SMR). Framing Error 0 Cleared from 1 to 0 when: 1. CPU reads FER = 1, then writes 0 in FER. 2. The chip is reset or enters a standby mode. 1 Set to 1 when a framing error occurs (stop bit is 0). Overrun Error 0 Cleared from 1 to 0 when: 1. CPU reads ORER = 1, then writes 0 in ORER. 2. The chip is reset or enters a standby mode. 1 Set to 1 when an overrun error occurs (next data is completely received while RDRF bit is set to 1). Receive Data Register Full 0 Cleared from 1 to 0 when: 1. CPU reads RDRF = 1, then writes 0 in RDRF. 2. RDR is read by the DTC. 3. The chip is reset or enters a standby mode. 1 Set to 1 when one character is received normally and transferred from RSR to RDR. Transmit Data Register Empty 0 Cleared from 1 to 0 when: 1. CPU reads TDRE = 1, then writes 0 in TDRE. 2. The DTC writes data in TDR. 1 Set to 1 when: 1. The chip is reset or enters a standby mode. 2. Data is transferred from TDR to TSR. 3. TE is cleared to 0 when TDRE = 0. Note: * Only writing of 0 to clear the flag is enabled. 388 RDR--Receive Data Register H'FFDD SCI1 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Receive data SMR--Serial Mode Register Bit H'FFC0 SCI2 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP -- CKS1 CKS0 Initial value 0 0 0 0 0 1 0 0 Read/Write R/W R/W R/W R/W R/W -- R/W R/W Note: Bit functions are the same as for SCI1. BRR--Bit Rate Register H'FFC1 SCI2 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for SCI1. 389 SCR--Serial Control Register Bit H'FFC2 SCI2 7 6 5 4 3 2 1 0 TIE RIE TE RE -- -- CKE1 CKE0 Initial value 0 0 0 0 1 1 0 0 Read/Write R/W R/W R/W R/W -- -- R/W R/W Note: Bit functions are the same as for SCI1. TDR--Transmit Data Register H'FFC3 SCI2 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for SCI1. SSR--Serial Status Register Bit H'FFC4 SCI2 7 6 5 4 3 2 1 RDRF ORER FER PER -- -- -- Initial value 0 0 0 0 0 1 1 1 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* -- -- -- TDRE Note: Bit functions are the same as for SCI1. * Only writing of 0 to clear the flag is enabled. 390 0 RDR--Receive Data Register H'FFC5 SCI2 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Note: Bit functions are the same as for SCI1. ADDRn (H)--A/D Data Register n (High H'FFE0, H'FFE2, H'FFE4, H'FFE6 Bit (n = A, B, C, D) A/D 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Upper 8 bits of 10-bit A/D conversion result ADDRn (L)--A/D Data Register n (Low) H'FFE1, H'FFE3, H'FFE5, H'FFE7 Bit (n = A, B, C, D) A/D 7 6 5 4 3 2 1 0 AD1 AD0 -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Lower 2 bits of 10-bit A/D conversion result 391 ADCSR--A/D Control/Status Register Bit H'FFE8 A/D 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)*1 R/W R/W R/W R/W R/W R/W R/W Channel Select CH2 CH1 CH0 Single mode Scan mode 0 1 0 0 AN0 AN0 0 1 AN1 AN0, AN1 1 0 AN2 AN0 to AN2 1 1 AN3 AN0 to AN3 0 0 AN4*2 AN4*2 0 1 AN5*2 AN4, AN5*2 1 0 AN6*2 AN4 to AN6*2 1 1 AN7*2 AN4 to AN7*2 Clock Select 0 Conversion time = 274 states (max) 1 Conversion time = 138 states (max) Scan Mode 0 Single mode 1 Scan mode A/D Start 0 A/D conversion is halted. 1 1. Single mode: One A/D conversion is performed, then this bit is automatically cleared to 0. 2. Scan mode: A/D conversion starts and continues cyclically on all selected channels until 0 is written in this bit. A/D Interrupt Enable 0 The A/D interrupt request (ADI) is disabled. 1 The A/D interrupt request (ADI) is enabled. A/D End Flag 0 Cleared from 1 to 0 when: 1. The chip is reset or enters a standby mode. 2. CPU reads ADF = 1, then writes 0 in ADF. 3. An A/D interrupt is served by the DTC. 1 Set to 1 at the following times: 1. Single mode: at the completion of A/D conversion 2. Scan mode: when all selected channels have been converted. Notes: 1. Only writing of 0 to clear the flag is enabled. 2. CP-68 package only. 392 ADCR--A/D Control Register Bit H'FFE9 A/D 7 6 5 4 3 2 1 0 TRGE -- -- -- -- -- -- -- Initial value 0 1 1 1 1 1 1 1 Read/Write R/W -- -- -- -- -- -- -- Trigger Enable 0 The A/D external trigger is disabled. 1 The A/D external trigger is enabled. A/D conversion starts on the falling edge of ADTRG. 393 ADCR--A/D Control Register: See next page. H'FFEC*1, H'FFED*2 TCSR--Timer Status/Control Register Bit WDT 7 6 5 4 3 2 1 0 OVF WT/IT TME -- -- CKS2 CKS1 CKS0 Initial value 0 0 0 1 1 0 0 0 Read/Write R/(W)*3 R/W R/W -- -- R/W R/W R/W Clock Select 0 0 0 o/2 (51.2 s)*4 0 0 1 o/32 (819.2 s) 0 1 0 o/64 (1.6 ms) 0 1 1 o/128 (3.3 ms) 1 0 0 o/256 (6.6 ms) 1 0 1 o/512 (13.1 ms) 1 1 0 o/2048 (52.4 ms) 1 1 1 o/4096 (104.9 ms) Timer Enable 0 Timer is disabled. * TCNT is initialized to H'00 and stopped. 1 Timer is enabled. * TCNT starts incrementing. * Reset or interrupt request is enabled. Timer Mode Select 0 Interval timer mode (IRQ0 interrupt request) 1 Watchdog timer mode (reset output) Overflow Flag Notes: 1. 2. 3. 4. 0 Cleared from 1 to 0 when CPU reads OVF = 1, then writes 0 in OVF. 1 Set to 1 when TCNT changes from H'FF to H'00. Write address Read address Only writing of 0 to clear the flag is enabled. Times in parentheses are the times for TCNT to increment from H'00 to H'FF and change to H'00 again when o = 10 MHz. 394 TCNT--Timer Counter H'FFED WDT Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Count value H'FFFF*2 RSTCSR--Reset Status/Control Register Bit WDT 7 6 5 4 3 2 1 0 WRST RSTOE -- -- -- -- -- -- Initial value 0 0 1 1 1 1 1 1 Read/Write R/(W)*1 R/W -- -- -- -- -- -- Reset Output Enable 0 The reset signal is not output externally. 1 The reset signal is output externally. Watchdog Timer Reset 0 Cleared from 1 to 0 by software, or by a low input at the RES pin. 1 Set to 1 when TCNT overflows and a reset signal is generated. Notes: 1. Software can write a 0 in bit 7 to clear the flag but cannot write a 1. 2. Read address: H'FFFF Write address: H'FFFE 395 IPRA--Interrupt Priority Register A Bit 7 6 H'FFF0 5 4 -- INTC 3 2 1 0 -- Initial value 0 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R R/W R/W R/W IRQ1 to IRQ7 interrupt priority level (0 to 7) IRQ0 interrupt priority level (0 to 7) IPRB--Interrupt Priority Register B Bit 7 6 H'FFF1 5 4 -- 3 INTC 2 1 0 -- Initial value 0 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R R/W R/W R/W 16-Bit FRT2 interrupt priority level (0 to 7) 16-Bit FRT1 interrupt priority level (0 to 7) 396 IPRC--Interrupt Priority Register C Bit 7 6 H'FFF2 5 4 -- INTC 3 2 1 0 -- Initial value 0 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R R/W R/W R/W SCI1 interrupt priority level (0 to 7) 8-Bit timer interrupt priority level (0 to 7) IPRD--Interrupt Priority Register D Bit 7 6 H'FFF3 5 4 -- INTC 3 2 1 0 -- Initial value 0 0 0 0 0 0 0 0 Read/Write R R/W R/W R/W R R/W R/W R/W A/D interrupt priority level (0 to 7) SCI2 interrupt priority level (0 to 7) 397 DTEA--Data Transfer Enable Register Bit H'FFF4 7 6 5 4 -- -- -- Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W INTC 3 2 1 0 0 0 0 0 R/W R/W R/W R/W -- IRQ1 0 Served by CPU 1 Served by DTC IRQ2 0 Served by CPU 1 Served by DTC IRQ3 IRQ0 0 Served by CPU 1 Served by DTC 398 0 Served by CPU 1 Served by DTC DTEB--Data Transfer Enable Register B Bit 7 6 H'FFF5 5 4 3 -- INTC 2 1 0 -- Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 16-Bit FRT channel 1 16-Bit FRT channel 2 ICI 0 Served by CPU 1 Served by DTC OCIA 0 Served by CPU 1 Served by DTC OCIB ICI 0 Served by CPU 1 Served by DTC OCIA 0 Served by CPU 1 Served by DTC OCIB 0 Served by CPU 1 Served by DTC 399 0 Served by CPU 1 Served by DTC DTEC--Data Transfer Enable Register C Bit H'FFF6 5 4 INTC 7 6 3 2 1 0 -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W -- -- 8-Bit timer SCI1 RXI 0 Served by CPU 1 Served by DTC TXI CMIA 0 Served by CPU 1 Served by DTC CMIB 0 Served by CPU 1 Served by DTC 400 0 Served by CPU 1 Served by DTC DTED--Data Transfer Enable Register D Bit 7 6 H'FFF7 5 -- INTC 4 3 2 1 -- -- -- -- 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SCI2 A/D converter ADI 0 Served by CPU 1 Served by DTC RXI 0 Served by CPU 1 Served by DTC TXI 0 Served by CPU 1 Served by DTC NMICR--NMI Control Register Bit H'FFFC NMIC 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- NMIEG Initial value 1 1 1 1 1 1 1 0 Read/Write -- -- -- -- -- -- -- R/W Nonmaskable Interrupt Edge 401 0 Interrupt requested on falling edge of NMI signal. 1 Interrupt requested on rising edge of NMI signal. IRQCR--IRQ Control Register Bit H'FFFD INTC 7 6 5 4 3 2 1 0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Interrupt Request 1 Enable Interrupt Request 0 Enable 0 P12 is not used for IRQ1 signal input. 0 P11 is not used for IRQ0 signal input. 1 P12 is used for IRQ1 signal input. 1 P11 is used for IRQ0 signal input. Interrupt Request 2 Enable 0 P13 is not used for IRQ2 signal input. 1 P13 is used for IRQ2 signal input. Interrupt Request 3 Enable 0 P14 is not used for IRQ3 signal input. 1 P14 is used for IRQ3 signal input. Interrupt Request 4 Enable 0 P44 is not used for IRQ4 signal input. 1 P44 is used for IRQ4 signal input. Interrupt Request 5 Enable 0 P45 is not used for IRQ5 signal input. 1 P45 is used for IRQ5 signal input. Interrupt Request 6 Enable 0 P46 is not used for IRQ6 signal input. 1 P46 is used for IRQ6 signal input. Interrupt Request 7 Enable 0 P47 is not used for IRQ7 signal input. 1 P47 is used for IRQ7 signal input. 402 WCR--Wait-State Control Register Bit H'FFF8 WSC 7 6 5 4 3 2 1 0 -- -- -- -- WMS1 WMS0 WC1 WC0 Initial value 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W R/W R/W R/W Wait Count 1 and 0 0 0 No wait states (TW) are inserted 0 1 1 wait state is inserted. 1 0 2 wait states are inserted. 1 1 3 wait states are inserted. Wait Mode Select 1 and 0 0 0 Programmable wait mode 0 1 No wait states are inserted, regardless of the wait count. 1 0 Pin wait mode 1 1 Pin auto-wait mode RAMCR--RAM Control Register Bit H'FFF9 RAM 7 6 5 4 3 2 1 0 RAME -- -- -- -- -- -- -- Initial value 1 1 1 1 1 1 1 1 Read/Write R/W -- -- -- -- -- -- -- RAM Enable 0 On-chip RAM is disabled. 1 On-chip RAM is enabled. 403 MDCR--Mode Control Register Bit H'FFFA 7 6 5 4 3 2 1 0 -- -- -- -- -- MDS2 MDS1 MDS0 Initial value 1 1 0 0 0 --* --* --* Read/Write -- -- -- -- -- R R R Mode Select Value input at mode pins Note: * Initialized according to the inputs at pins MD2, MD1, and MD0. SBYCR--Software Standby Control Register Bit H'FFFB 7 6 5 4 3 2 1 0 SSBY -- -- -- -- -- -- -- Initial value 0 1 1 1 1 1 1 1 Read/Write R/W -- -- -- -- -- -- -- Software Standby 0 SLEEP instruction causes transition to sleep mode. 1 SLEEP instruction causes transition to software standby mode. 404 Appendix C I/O Port Schematic Diagrams C.1 Schematic Diagrams of Port 1 Figure C-1 (a) to (g) gives a schematic view of the port 1 input/output circuits. WP1D: Write to P1DDR WP1: Write to port 1 RP1: Read port 1 Reset R D P10DDR C WP1D Reset R P10 Q D P10DR C WP1 Mode 1, 2, 3, or 4 Internal data bus (PDB8) Q Wait state control register, bit 3 WMS1 Q RP1 WAIT to CPU Figure C-1 (a) Schematic Diagram of Port 1, Pin P10 Table C-1 (a) Data Read from Port 1 (Pin P10) Mode Setting Port Read Data Mode 1, 2, 3, or 4 WMS1 = 1 Pin value WMS1 = 0 Mode 7 DDR = 0 Pin value DDR = 1 Value written in DR DDR = 0 Pin value DDR = 1 Value written in DR Figure C-1 (a) 405 Reset WP1D: Write to P1DDR WP1: Write to port 1 RP1: Read port 1 R D P11DDR C WP1D Reset R P11 Q D P11DR C Internal data bus (PDB9) Q WP1 IRQ control register bit 0 IRQ0E Q RP1 IRQ0 to CPU Figure C-1 (b) Schematic Diagram of Port 1, Pin P11 Table C-1 (b) Data Read from Port 1 (Pin P11) Setting Port Read Data DDR = 0 Pin value DDR = 1 Value written in DR Figure C-1 (b) 406 Mode 3 or 4 Software standby WP1D: Write to P1DDR WP1: Write to port 1 RP1: Read port 1 Mode 3 R D P12DDR C WP1D Reset Mode 1, 2, or 7 R Q P12 D P12DR C WP1 Mode 3 or 4 Internal address bus (IAB18) S Q Internal data bus (PDB10) Reset MOS pull-up RP1 IRQ control register bit 1 IRQ1E Q Falling-edge detector IRQ1 to CPU A/D converter module A/D control register bit 7 TGRE Q ADTRG to A/D converter module Figure C-1 (c) Schematic Diagram of Port 1, Pin P12 Table C-1 (c) Data Read from Port 1 (Pin P12) Mode Setting Mode 1, 2, or 7 TRGE = 1 TRGE = 0 Port Read Data Figure C-1 (c) Value written in DR DDR = 0 Pin value DDR = 1 Mode 3 Mode 4 Value written in DR Value written in DR DDR = 0 Pin value DDR = 1 Value written in DR 407 Mode 3 or 4 Reset MOS pull-up S Q R D P1nDDR C WP1D Reset Mode 1, 2, or 7 R Q P1n D P1nDR C WP1 Mode 3 or 4 Internal data bus (PDB11, PDB12) Mode 3 WP1D: WP1: RP1: n: Write to P1DDR Write to port 1 Read port 1 3 or 4 Internal address bus (IAB17, IAB16) Software standby RP1 .............................. Falling-edge detector IRQ control register bit 2 or 3 IRQ2E Q IRQ3E IRQ2, IRQ3, to CPU Figure C-1 (d) Schematic Diagram of Port 1, Pins P13 and P14 Table C-1 (d) Data Read from Port 1 (Pins P13 and P14) Mode Setting Mode 3 Mode 1, 2, 4, or 7 Port Read Data Value written in DR DDR = 0 DDR = 1 Pin value Figure C-1 (d) Value written in DR 408 Mode 1, 2, 3, or 4 Software standby Reset R D P1nDDR C WP1D Reset Mode 7 S Q P1n R D P1nDR C Mode 1, 2, 3, or 4 WP1 Internal data bus (PDB15 to PDB17) S Q WP1D: Write to P1DDR WP1: Write to port 1 RP1: Read port 1 n: 5, 6, or 7 RP1 Bus control signal Figure C-1 (e) Schematic Diagram of Port 1, Pins P15, P16, and P17 Table C-1 (e) Data Read from Port 1 (Pins P15, P16, and P17) Mode Setting Mode 1, 2, 3, or 4 Mode 7 Port Read Data Value written in DR DDR = 0 Pin value DDR = 1 Value written in DR Figure C-1 (e) 409 C.2 Schematic Diagram of Port 2 Figure C-2 gives a schematic view of the port 2 input/output circuits. Data write WP2D: WP2: RP2: n: Mode 1, 2, 3, or 4 Reset R Q Mode 7 D P2nDDR C Internal data bus (PDB8 to PDB15) WP2D Reset Mode 1, 2, 3, or 4 R P2n Q Mode 7 D P2nDR C WP2 Mode 1, 2, 3, or 4 RP2 External address read Figure C-2 Schematic Diagram of Port 2 Table C-2 Data Read from Port 2 Mode Setting Mode 1, 2, 3, or 4 Mode 7 Port Read Data Always read as 1 DDR = 0 Pin value DDR = 1 Value written in DR 410 Figure C-2 Write to P2DDR Write to port 2 Read port 2 0 to 7 C.3 Schematic Diagram of Port 3 Figure C-3 gives a schematic view of the port 3 input/output circuits. MOS pull-up Mode 1, 2, 3, or 4 Reset S Q R D P3nDDR C WP3D Reset Mode 7 R Q P3n D P3nDR C WP3 Mode 1, 2, 3, or 4 RP3 Figure C-3 Schematic Diagram of Port 3 Table C-3 Data Read from Port 3 Mode Setting Mode 1, 2, 3, or 4 Mode 7 Port Read Data Value written in DR DDR = 0 Pin value DDR = 1 Value written in DR Figure C-3 411 WP3D: WP3: RP3: n: Internal address bus (IAB0 to IAB7) Software standby Internal data bus (PDB8 to PDB15) Mode 1, 2, 3, or 4 Write to P3DDR Write to port 3 Read port 3 0 to 7 C.4 Schematic Diagram of Port 4 Figure C-4 (a) and (b) gives a schematic view of the port 4 input/output circuits. Mode 1,2,3, or 4 Mode 1 or 3 S Q R D P4nDDR C WP4D Reset Mode 7 R Q P4n D P4nDR C WP4 Mode 1,2,3, or 4 Internal data bus (PDB8 to PDB11) Reset MOS pull-up Internal address bus (IAB8 to IAB11) WP4D: WP4: RP4: n: Software standby RP4 Figure C-4 (a) Schematic Diagram of Port 4, Pins 40 to 43 Table C-4 (a) Data Read from Port 4 (Pins 40 to 43) Mode Setting Mode 1 or 3 Mode 2, 4, or 7 Port Read Data Value written in DR DDR = 0 Pin value DDR = 1 Value written in DR Figure C-4 (a) 412 Write to P4DDR Write to port 4 Read port 4 0 to 3 Mode 1, 2, 3, or 4 Reset S Q R D P4nDDR C WP4D Reset Mode 7 R Q P4n D P4nDR C WP4 Mode 1, 2, 3, or 4 Internal data bus (PDB12 to PDB15) Mode 1 or 3 MOS pull-up WP4D: WP4: RP4: n: Write to P4DDR Write to port 4 Read port 4 4 to 7 Internal address bus (IAB12 to IAB15) Software standby RP4 IRQ control register bit 4 to 7 IRQ4E Q IRQ5E IRQ6E IRQ7E Falling-edge detector IRQ4 to IRQ7, to CPU Figure C-4 (b) Schematic Diagram of Port 4, Pins 44 to 47 Table C-4 (b) Data Read from Port 4 (Pins 44 to 47) Mode Setting Mode 1 or 3 Mode 2, 4, or 7 Port Read Data Value written in DR DDR = 0 DDR = 1 Pin value Figure C-4 (b) Value written in DR 413 C.5 Schematic Diagram of Port 5 Figure C-5 (a) to (g) gives a schematic view of the port 5 input/output circuits. Reset R1 Q WP5D Reset R Q D P50DR C Internal data bus (PDB8) D P50DDR C P50 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 WP5 8-Bit timer module RP5 Counter reset input Figure C-5 (a) Schematic Diagram of Port 5, Pin P50 Table C-5 (a) Data Read from Port 5 (Pin P50) Setting Port Read Data DDR = 0 Pin value DDR = 1 Value written in DR Figure C-5 (a) 414 Reset D P51DDR C WP5D Reset R Q P51 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 D P51DR C Internal data bus (PDB9) R1 Q WP5 Free-running timer module RP5 Input capture signal Figure C-5 (b) Schematic Diagram of Port 5, Pins P51 and P52 Table C-5 (b) Data Read from Port 5 (Pins P51 and P52) Setting Output disable Port Read Data Figure C-5 (b) DDR = 0 Pin value DDR = 1 Value written in DR 415 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Reset D P52DDR C WP5D Reset R Q P52 P52DR C WP5 D Internal data bus (PDB10) R1 Q RP5 8-Bit timer module Counter reset input Free-running timer module Input capture signal Figure C-5 (c) Schematic Diagram of Port 5, Pin P52 Table C-5 (c) Data Read from Port 5 (Pin P52) Setting Port Read Data DDR = 0 Pin value DDR = 1 Value written in DR Figure C-5 (c) 416 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Reset D P53DDR C WP5D Reset R Q P53 D P53DR C WP5 Internal data bus (PDB11) R Q 8-Bit timer module Output enable 8-Bit timer output RP5 Figure C-5 (d) Schematic Diagram of Port 5, Pin P53 Table C-5 (d) Data Read from Port 5 (Pin P53) Mode Setting 8-Bit timer output enabled 8-Bit timer output disabled Port Read Data 8-Bit timer output DDR = 0 Pin value DDR = 1 Value written in DR Figure C-5 (d) 417 Internal data bus (PDB12, PDB 13) Reset R Q D P5nDDR C WP5D Reset R Q P5n D P5nDR C WP5D: WP5: RP5: n: Write to P5DDR Write to port 5 Read port 5 4 or 5 Free-running timer module WP5 Output enable Output compare B RP5 Counter clock input Figure C-5 (e) Schematic Diagram of Port 5, Pins P54 and P55 Table C-5 (e) Data Read from Port 5 (Pins P54 and P55) Setting Port Read Data Output compare B enabled Free-running timer output (output compare B) Output compare B disabled DDR = 0 Pin value DDR = 1 Value written in DR 418 Figure C-5 (e) Reset D P56DDR C WP5D Reset R Q P56 D P56DR C WP5 Internal data bus (PDB14) R Q WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Free-running timer module Output enable Output compare A RP5 Figure C-5 (f) Schematic Diagram of Port 5 (Pin P56) Table C-5 (f) Data Read from Port 5 (Pin P56) Setting Port Read Data Output compare A enabled Free-running timer output (output compare A) Output compare A disabled DDR = 0 Pin value Figure C-5 (f) DDR = 1 Value written in DR 419 (Mode 1, 2, 3, 4) reset Reset (Mode 7) WP7D: WP5D: WP5: RP5: WP7D Reset R Q P57 DD P57DDR C WP5D Internal data bus (PDB14) oOE C Internal data bus (PDB15) S R Q D Write to oOE Write to P5DDR Write to port 5 Read port 5 Reset R Q D P57DR C Free-running timer module WP5 Output enable Output compare A System clock (o) Figure C-5 (g) Schematic Diagram of Port 5, Pin P57 Table C-5 (g) Data Read from Port 5 (Pin 57) Setting Port Read Data oOE = 1 System clock value (o) oOE = 0 Output compare A enabled Free-running timer output (Output compare A) Output compare A disabled DDR = 0 Pin value DDR = 1 Value written in DR 420 Figure C-5 (g) C.6 Schematic Diagram of Port 6 Internal data bus (PDB8 to PDB11) (PDB8 to PDB15)* Figure C-6 gives a schematic view of the port 6 input circuits. RP6 P6n RP6: Read port 6 0 to 3 n: (0 to 7)* ............ A/D converter module ........................... Input multiplexer Note: * CP-68 package only Figure C-6 Schematic Diagram of Port 6 Figure C-6 421 C.7 Schematic Diagrams of Port 7 Figure C-7 (a) to (d) gives a schematic view of the port 7 input/output circuits. R Q D P7nDDR C WP7D Reset R Q P7n D P7nDR C WP7 Internal data bus (PDB8, PDB11) Reset WP7D: WP7: RP7: n: Write to P7DDR Write to port 7 Read port 7 0 or 3 SCI module Output enable Serial transmit data RP7 Figure C-7 (a) Schematic Diagram of Port 7, Pins P70 and P73 Table C-7 (a) Data Read from Port 7 (Pins P70 and P73) Setting Port Read Data Serial output enabled Serial transmit data Serial output disabled DDR = 0 Pin value DDR = 1 Value written in DR 422 Figure C-7 (a) Reset WP7D: WP7: RP7: n: R D P7nDDR C WP7D P7n Reset R Q D P7nDR C Internal data bus (PDB9, PDB12) Q Write P7DDR Write to port 7 Read port 7 1 or 4 WP7 SCI module RP7 Input enable Serial receive data Figure C-7 (b) Schematic Diagram of Port 7, Pins P71 and P74 Table C-7 (b) Data Read from Port 7 (Pins P71 and P74) Setting Port Read Data Serial input enabled Serial receive data Serial input disabled DDR = 0 Pin value DDR = 1 Value written in DR Figure C-7 (b) 423 Software standby Mode 3 or 4 WP7D: Write to P7DDR WP7: Write to port 7 RP7: Read port 7 Mode 3 Reset P72DDR C WP7D Reset R P72DR Q C P72 D WP1 Internal address bus (IAB19) R D Internal data bus (PDB10) S SCI timer module Clock output Mode 3 or 4 Clock input enable Clock output enable Mode 3 Mode 4 RP7 Clock input Figure C-7 (c) Schematic Diagram of Port 7, Pin P72 Table C-7 (c) Data Read from Port 7 (Pin P72) Mode Setting Port Read Data Mode 3 IAB19 value Mode 4 DDR = 1 IAB19 value Mode 1, 2, or 7, or Pin value Mode 4 with DDR = 0 Serial clock input enabled Figure C-7 (c) Serial clock output enabled Mode 4 with DDR = 0 Serial clock input and output disabled Pin value Mode 1, 2, or 7 Serial clock input DDR = 0 Pin value and output disabled DDR = 1 Value written in DR 424 Output clock value Reset WP7D: Write to P7DDR WP7: Write to port 7 RP7: Read port 7 R D P75DDR C WP7D Reset R Q P75 D Internal data bus (PDB13) Q SCI timer module P75DR C WP7 Clock input enable Clock output enable Clock output RP7 Clock input Figure C-7 (d) Schematic Diagram of Port 7, Pin P75 Table C-7 (d) Data Read from Port 7 (Pin P75) Setting Port Read Data Serial clock input enabled Input clock value Serial clock output enabled Output clock value Serial clock input and output disabled Figure C-7 (d) DDR = 0 Pin value DDR = 1 Value written in DR 425 Appendix D Memory Map Expanded Maximum Mode Mode 1 Expanded Maximum Mode Mode 2 H'0000 Mode 3 H'0000 Vector tables H'FD7F H'FD80 426 H'FF7F H'FF80 External memory On-chip ROM 16 kbytes H'FFFF Page 0 H'0FD7F H'0FD80 H'FF7F H'FF80 External memory H'FD80 On-chip RAM 512 bytes H'0FF7F H'0FF80 On-chip RAM 512 bytes H'FF7F H'FF80 H'0FF7F H'0FF80 Register field 128 bytes Register field 128 bytes H'0FFFF H'10000 Register field 128 bytes H'FFFF H'0FFFF H'10000 Page 1 Page 1 H'1FFFF H'1FFFF External memory H'F0000 External memory H'F0000 Page 15 Page 15 H'FFFFF Page 0 Page 0 H'0FD7F H'0FD80 On-chip RAM 512 bytes Register field 128 bytes H'FFFF On-chip ROM 16 kbytes H'3FFF Page 0 On-chip RAM 512 bytes Register field 128 bytes H'00BF H'00C0 H'03FFF H'04000 External memory On-chip RAM 512 bytes Vector tables H'0017F H'00180 H'3FFF H'4000 H'FD7F H'FD80 H'0000 Vector tables H'0017F H'00180 On-chip ROM 16 kbytes Page 0 Mode 7 H'00000 Vector tables H'00BF H'00C0 External memory Mode 4 H'00000 Vector tables H'00BF H'00C0 Single-Chip Mode H'FFFFF Appendix E Pin States E.1 Port State of Each Pin State Table E-1 Port Pin States in Each Mode Port Pin Name Hardware Standby Mode Reset Mode Software Standby Mode Sleep Mode Program Execution State (Normal Operation) P10 / WAIT 1 keep keep Control signal input or P10 / IRQ0 2 T T Notes input/output port 3 4 7 P14 to P12 1 T IRQ3 / IRQ1 2 (A16 to A18) 3 L (ADTRG) 4 T T keep keep T 7 keep Control signal input or In the program input/output port execution L A16 to A18 state, P12 also *2 Address bus, control receives the signal input, or A/D trigger input port ADTRG keep Control signal input or input/output port P17 to P15 1 AS, RD,WR, 2 H T T H AS, RD,WR, keep keep input/output port T T D7 to D0 keep keep Input/output port T L A7 to A0 3 4 7 T P27 to P20 1 T D7 to D0 2 T 3 4 7 P37 to P30 1 L T A7 to A0 2 MOS input 3 pull-ups 4 7 T keep keep 427 Input/output port Programmable Table E-1 Port Pin States in Each Mode (cont) Port Pin Name Hardware Standby Mode Reset Mode Software Standby Mode Sleep Mode Program Execution State (Normal Operation) Notes P43 to P40 1 L T L A11 to A8 Programmable A11 to A8 2 T *2 Address bus MOS input or input port pull-ups T 3 L L A11 to A8 4 T *2 Address bus or input port 7 P47 to P44 1 L A15 to A12 2 T T keep keep Input/output port T L A15 to A12 Programmable *2 Address bus, IRQ MOS input or input port pull-ups (IRQ7 to IRQ4) 3 L L A15 to A12 4 T *2 Address bus, IRQ or input port 7 keep keep IRQ or input/ output port P57/ 1 o o FTOA8/o 2 output output 3 keep*1 keep Input/output port keep Input/Output port (including o output 4 7 T T P56 to P50 1 T T Timer 2 input pins 3 keep*1 Schmitt trigger input 4 7 P63 to P60 1 T T T T Input port [P67 to P60] 2 apply to CP-68 AN3 to AN0 3 package [AN7 toAN0] 4 7 P71 to P70 1 P75 to P73 2 TXD2, RXD2 3 TXD1, RXD1 4 SCK1 7 T T keep*1 keep 428 Input/output port Brackets [ ] Table E-1 Port Pin States in Each Mode (cont) Port Pin Name Hardware Standby Mode Reset Mode Software Standby Mode Sleep Mode Program Execution State (Normal Operation) P72 / SCK2 / 1 keep*1 keep Input/output port A19 2 T L A19 *2 Address bus or T 3 L 4 T T Notes input/output port 7 H: L: T: keep: keep*1 keep Input/output port High Low Three-state (high impedance) Output pins retain their previous states. Input pins go to the high-impedance state. In ports 3 and 4, if DDR = 0 and DR = 1, input MOS pull-ups remain on. Notes: 1. On-chip supporting modules are reset, so these pins become input or output ports controlled by DDR and DR. 2. Input ports go to the high-impedance state. Address outputs go to low. 429 Table E-2 MOS Pull-Up States Port Mode Reset Hardware Standby Mode Other Operating States* P37 to P30 1 OFF OFF OFF A7 to A0 2 3 4 7 ON/OFF P47 to P40 1 OFF OFF A15 to A8 2 ON/OFF 3 OFF 4 ON/OFF 7 OFF: Pull-up MOS pull-up is always off. ON/OFF: MOS pull-up is on when DDR = 0 and DR = 1 off at other times. Note: * Including software standby mode 430 OFF E.2 Pin Status in the Reset State 1. Mode 1 Figure E-1 shows how the pin states change when the RES pin goes low during external memory access in mode 1. As soon as RES goes low, all ports are initialized to the input state. The AS, RD, and WR signals all go high. The data bus (D7 to D0) is placed in the high-impedance state. The address bus is initialized 1.5 o clock periods after the low state of the RES pin is sampled. All address bus signals are driven low. The clock output pin P57/o is initialized to the clock output state and begins clock output 0.5 o clock periods after the low state of the RES pin is sampled. 431 External memory access T1 T2 T3 P57/o* RES Internal reset signal A15 to A0 H'0000 AS, RD (read) WR (write) High impedance D7 to D 0 (write) High impedance I/O ports Note: * The dotted line indicates that P57/o is an input port or timer output pin if the oOE bit is 0, but a clock output pin if the oOE bit is 1. Figure E-1 Reset During Memory Access (Mode 1) 2. Mode 2 Figure E-2 shows how the pin states change when the RES pin goes low during external memory Figure E-1 access in mode 2. As soon as RES goes low, all ports are initialized to the input state. The AS, RD, and WR signals all go high. The data bus (D7 to D0) is placed in the high-impedance state. Pins P47/A15 to P40/A8 of the address bus are initialized as input ports. 432 Pins A7 to A0 of the address bus are initialized to the low state 1.5 o clock periods after the low state of the RES pin is sampled. The clock output pin P57/o is initialized to the clock output state and begins clock output 0.5 o clock periods after the low state of the RES pin is sampled. External memory access T1 T2 T3 P57/o* RES Internal reset signal A7 to A0 H'00 High impedance P47/A15 to P40/A8 AS, RD (read) WR (write) High impedance D7 to D 0 (write) High impedance I/O ports Note: * The dotted line indicates that P57/o is an input port or timer output pin if the oOE bit is 0, but a clock output pin if the oOE bit is 1. Figure E-2 Reset During Memory Access (Mode 2) 433 Figure E-2 3. Mode 3 Figure E-3 shows how the pin states change when the RES pin goes low during external memory access in mode 3. As soon as RES goes low, all ports are initialized to the input state. The AS, RD, and WR signals all go high. The data bus (D7 to D0) is placed in the high-impedance state. The address bus is initialized 1.5 o clock periods after the low state of the RES pin is sampled. All address bus signals are driven low. The clock output pin P57/o is initialized to the clock output state and begins clock output 0.5 o clock periods after the low state of the RES pin is sampled. 434 External memory access T1 T2 P57/o* RES Internal reset signal A19 to A0 H'00000 AS, RD (read) WR (write) High impedance D7 to D 0 (write) High impedance I/O ports Note: * The dotted line indicates that P57/o is an input port or timer output port if the oOE bit is 0, but a clock output pin if the oOE bit is 1. Figure E-3 Reset During Memory Access (Mode 3) 4. Mode 4 Figure E-4 shows how the pin states change when the RES pin goes low during external memory access in mode 4. As soon as RES goes low, all ports are initialized to the input state. The AS, RD, and WR signals all go high. The data bus (D7 to D0) is placed in the high-impedance state. Pins P47/A15 to P40/A8 of the page address address bus and pins P72/A19 and P12/A18 to P14/A16 of theFigure E-3 bus are initialized as input ports. 435 Pins A7 to A0 of the address bus are initialized to the low state 1.5 o clock periods after the low state of the RES pin is sampled. The clock output pin P57/o is initialized to the clock output state and begins clock output 0.5 o clock periods after the low state of the RES pin is sampled. T1 T2 T3 T1 P57/o* RES Internal reset signal A7 to A0 H'00 High impedance P72/A19, P12/A18 to P14/A16, and P47/A15 to P40/A8 AS, RD (read) WR (write) High impedance D7 to D 0 (write) High impedance I/O ports Note: * The dotted line indicates that P57/o is an input port or timer output port if the oOE bit is 0, but a clock output pin if the oOE bit is 1. Figure E-4 Reset During Memory Access (Mode 4) Figure E-4 436 5. Mode 7 Figure E-5 shows how the pin states change when the RES pin goes low in mode 7. As soon as RES goes low, all ports are initialized to the input state. The clock output pin P57/o is also initialized to the input state. P57/o* RES Internal reset signal High impedance I/O ports Note: * The dotted line indicates that P57/o is an input port or timer output port if the oOE bit is 0, but a clock output pin if the oOE bit is 1. Figure E-5 Reset During Memory Access (Mode 7) Figure E-5 437 Appendix F Package Dimensions Figure F-1 shows the dimensions of the DC-64S package. Figure F-2 shows the dimensions of the DP-64S package. Figure F-3 shows the dimensions of the FP-64A package. Figure F-4 shows the dimensions of the CP-68 package. 57.30 64 18.92 33 1.778 0.250 2.54 Min 5.60 Max 32 0.9 0.51 Min 1 0.48 0.10 19.05 0.11 0.25 +- 0.05 Figure F-1 Package Dimensions (DC-64S) 33 17.0 18.6 Max 64 57.6 58.50 Max 1.78 0.25 0.48 0.10 2.54 Min 5.08 Max 32 1.0 0.51 Min 1 19.05 + 0.11 0.25 - 0.05 0 - 15 Figure F-2 Package Dimensions (DP-64S) 438 17.2 0.3 14 33 48 32 0.80 17.2 0.3 49 64 17 1 +0.08 -0.05 0.17 1.6 0-5 0.1 2.70 0.15 M 3.05 Max 0.35 0.10 +0.20 -0.16 16 0.1 0.8 - 0.3 Figure F-3 Package Dimensions (FP-64A) 25.15 0.12 24.20 44 60 43 9 27 10 26 0.75 0.42 0.10 2.55 0.15 68 1 4.40 0.20 25.15 0.12 61 1.27 23.12 0.50 23.12 0.50 0.10 Figure F-4 Package Dimensions (CP-68) 439