Section 11 8-Bit Timer............................................................................................................ 217
11.1 Overview.............................................................................................................................. 217
11.1.1 Features .................................................................................................................... 217
11.1.2 Block Diagram ......................................................................................................... 218
11.1.3 Input and Output Pins............................................................................................... 219
11.1.4 Register Configuration............................................................................................. 219
11.2 Register Descriptions........................................................................................................... 219
11.2.1 Timer Counter (TCNT)—H'FFD4 ........................................................................... 219
11.2.2 Time Constant Registers A and B
(TCORA and TCORB)—H'FFD2 and H'FFD3....................................................... 220
11.2.3 Timer Control Register (TCR)—H'FFD0 ................................................................ 220
11.2.4 Timer Control/Status Register (TCSR).................................................................... 222
11.3 Operation.............................................................................................................................. 224
11.3.1 TCNT Incrementation Timing.................................................................................. 224
11.3.2 Compare Match Timing ........................................................................................... 226
11.3.3 External Reset of TCNT........................................................................................... 227
11.3.4 Setting of TCNT Overflow Flag .............................................................................. 228
11.4 CPU Interrupts and DTC Interrupts..................................................................................... 229
11.5 Sample Application.............................................................................................................. 230
11.6 Application Notes ................................................................................................................ 231
Section 12 Watchdog Timer.................................................................................................. 237
12.1 Overview.............................................................................................................................. 237
12.1.1 Features .................................................................................................................... 237
12.1.2 Block Diagram ......................................................................................................... 238
12.1.3 Register Configuration............................................................................................. 239
12.2 Register Descriptions........................................................................................................... 239
12.2.1 Timer Counter (TCNT)—H'FFED........................................................................... 239
12.2.2 Timer Control/Status Register (TCSR)—H'FFEC (Read), H'FFED (Write)........... 240
12.2.3 Reset Control/Status Register (RSTCSR)—H'FFFF (Read), H'FFFE (Write)........ 241
12.2.4 Notes on Register Access......................................................................................... 242
12.3 Operation.............................................................................................................................. 244
12.3.1 Watchdog Timer Mode............................................................................................. 244
12.3.2 Interval Timer Mode ................................................................................................ 246
12.3.3 Operation in Software Standby Mode...................................................................... 246
12.3.4 Setting of Overflow Flag.......................................................................................... 247
12.3.5 Setting of Watchdog Timer Reset (WRST) Bit........................................................ 248
12.4 Application Notes ................................................................................................................ 248
Section 13 Serial Communication Interface ..................................................................... 251
13.1 Overview.............................................................................................................................. 251
13.1.1 Features .................................................................................................................... 251
13.1.2 Block Diagram ......................................................................................................... 252
13.1.3 Input and Output Pins............................................................................................... 253
13.1.4 Register Configuration............................................................................................. 253
13.2 Register Descriptions........................................................................................................... 254
13.2.1 Receive Shift Register (RSR)................................................................................... 254
13.2.2 Receive Data Register (RDR)—H'FFDD (Channel 1), H'FFC5 (Channel 2).......... 254
13.2.3 Transmit Shift Register (TSR) ................................................................................. 254
13.2.4 Transmit Data Register (TDR)—H'FFDB (Channel 1), H'FFC3 (Channel 2)......... 255
13.2.5 Serial Mode Register (SMR)—H'FFD8 (Channel 1), H'FFC0 (Channel 2)............ 255