INTEGRATED CIRCUITS DATA Sil 74LV165 = = | 8-bit parallel-in/serial-out shift register Product specification Supersedes data of 1997 May 15 IC24 Data Handbook Philips Semiconductors Di 1998 May 07 PHILIPSPhilips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels between Voc = 2.7 V and Voc = 3.6 V Typical Vo_p (output ground bounce) < 0.8 V at Voc = 3.3 V, Tamb = 25C Typical Voyy (output Voy undershoot) > 2 V at Voc = 3:3 V, Tamb = 25C Asynchronous 8-bit parallel load Synchronous serial input Output capability: standard loc category: MSI QUICK REFERENCE DATA GND = 0 V; Tamb = 25C; t= t}<2.5ns DESCRIPTION The 74LV165 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT165. The 74LV165 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the Do to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the Dg input and shifts one place to the right (Qo >Q,Qz, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the Dg input of the succeeding stage. The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay C_ = 15 pF; tpi /teLy PrioG, G, Q7 Veo =33V is ns D7 to Q7, Q7 14 fmax Maximum clock frequency 78 MHz Cc Input capacitance 3.5 pF Cpp Power dissipation capacitance per gate yoo SND to Vert 35 pF |= Oo Vcc NOTES: 1. Cpp is used to determine the dynamic power dissipation (Pp in uW) Pp =Cpp x Voc? x fi iy (CL x Voc? x fy) where: f, = input frequency in MHz; C_ = output load capacitance in pF; fy = output frequency in MHz; Vcc = supply voltage in V; (CL x Voc? x fo) = sum of the outputs. ORDERING INFORMATION 1998 May 07 PACKAGES TEMPERATURE RANGE | OUTSIDE NORTH AMERICA | NORTH AMERICA PKG. DWG. # 16-Pin Plastic DIL 40C to +125C 74LV165 N 74LV165 N SOT38-4 16-Pin Plastic SO 40C to +125C 74LV165 D 74LV165 D SOT109-1 16-Pin Plastic SSOP Type Il 40C to +125C 74LV165 DB 74LV165 DB SOT338-1 16-Pin Plastic TSSOP Type | 40C to +125C 74LV165 PW 74LV165PW DH SOT403-1 PIN CONFIGURATION PIN DESCRIPTION VS PIN NUMBER SYMBOL FUNCTION PL| 1 16 | Yoo 1 PL Asynchronous parallel load cP[ 2 | 15 | CE input (active LOW) Clock input (LOW to o4[ 3 | 14 | Ds 2 cP HIGH, edge-triggered) Ds| 4 13 ~ : - : 7 a the lest stage output from ee 2 | 8 GND Ground (0 V) 6 1 o7[ 8 | Do 9 Q; Serial output from last stage Q7| 7 10 | Ds 10 Ds Serial data input GND| 8 9 |a, 11, 12, 13, 14,3, 4,5,6 |DotoD7 | Parallel data inputs aE Clock enable input SV00585 15 CE (active LOW) 16 Voc Positive supply voltage 853-1915 19349Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 LOGIC SYMBOL FUNCTIONAL DIAGRAM 10 4 l12 [13 1a [a Ja [5 [oe D 11]Do ~ Do D1 |}Dz |Dg |D4 |Ds jDg | D7 12D, 13]Do 1 PL 14 I Pt Ey ty 4ps 5De Q7F 9 10 Dg 61D7 Q7p7 Qz 9 8-BIT SHIFT REGISTER j< _ PL 2 cP PARALLEL~ IN / SERIAL OUT a;| 7 cP CE A | 15 CE |2 his ~~] s SV00586 SV00588 LOGIC SYMBOL (IEEE/IEC) 1 SRGB + C2 [LOAD] Gt [SHIFT] 15 a 2 2 E> C3/ > 10 I cr 3D 1 oD 12 2D 13 14 3 4 5 5 9 NZ SV00587 LOGIC DIAGRAM Do Dy PSPS0 fo a a cP Sp Sp _ | D qQ D Qa c CP. ICP. Py FFO FFI Rp SV00589 1998 May 07 3Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 FUNCTION TABLE INPUTS Qn REGISTERS OUTPUTS OPERATING MODES = PL CE CP Ds Dg-D7 Qo Qi-Q6 Q; Q; L x x x L L-L H Parallel load L x x x H H H-H H L H L tT I x q Serial Shift os 6 6 H L T h X H qo-45 6 de Hold do nothing H H x x x do 1-6 q7 q7 NOTES: H = _ HIGH voltage level h = _ HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level | = LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition X = dontcare T = LOW-to-HIGH clock transition RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Voc DC supply voltage See Note 1 1.0 3.3 5.5 Vv V| Input voltage 0 - Voc Vv Vo Output voltage 0 - Voc Vv . : : : See DC and AC 40 +85 Tamb Operating ambient temperature range in free air characteristics _A0 4125 Cc Voc = 1.0V to 2.0V - - 500 : : Voc = 2.0V to 2.7V - - 200 tht Input rise and fall times Veo =2.7V to 3.6V _ _ 100 ns/V Voc = 3.6V to 5.5V - - 50 NOTE: 1. The LV is guaranteed to function down to Voc = 1.0V (input levels GND or Voc); DC characteristics are guaranteed from Voc = 1.2V to Voc = 5.5V. ABSOLUTE MAXIMUM RATINGS" 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS RATING UNIT Voc DC supply voltage 0.5 to +7.0 Vv tlk DC input diode current V, <-0.5 or Vi > Voc + 0.5V 20 mA tlok DC output diode current Vo < 0.5 or Vo > Veco + 0.5V 50 mA DC output source or sink current 4 tlo standard outputs 0.5V <Vo < Voc + 0.5V 25 mA DC Vcc or GND current for types with HNGND standard outputs 50 mA Tstg Storage temperature range 65 to +150 C Power dissipation per package for temperature range: 40 to +125C Pp plastic DIL above +70C derate linearly with 12 mW/K 750 mW TOT plastic mini-pack (SC) above +70C derate linearly with 8 mW/K 500 plastic shrink mini-pack (SSOP and TSSOP) above +60C derate linearly with 5.5 mW/K 400 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 May 07Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS -40C to +85C -40C to +125C UNIT MIN TYP! MAX MIN MAX Veo =1.2V 0.9 0.9 V HIGH level Input | Voc = 2.0 V 1.4 1.4 V IH | voltage Voc = 2.7 to 3.6 V 2.0 2.0 Voc =4.5to5.5V 0.7* Voc 0.7* Voc Veo =1.2V 0.3 0.3 V LOW level Input Voc =2.0V 0.6 0.6 Vv | | voltage Voc = 2.7 to 3.6 V 0.8 08 Voc = 4.5 to 5.5 0.3* Voc 0.3 * Voc Voc = 1.2 V;V)= Vin or Vit.-lo= 100A 1.2 Vec =2.0V; V| = Vin or Vi; -lo = 100A 1.8 2.0 18 HIGH level output Vou voltage: all outputs Voc = 2.7 V; V) = Vin or ViL-lo = 100pA 2.5 2.7 2.5 Vv Vec = 3.0 V; V| = Vin or Vi; -lo = 100A 2.8 3.0 2.8 Vec =45V; V| = Vin or Vi; -lo = 100A 43 45 43 HIGH level output | Vg = 3.0 V; Vi = Viq or ViL:-lo = 6MA 2.40 2.82 2.20 V voltage; Vv OH | STANDARD outputs Vec =45V; V| = Vin or Vi; -lo =12mA 3.60 4.20 3.50 Voc = 1.2 V;V)= Vin or Vi_- lo = 100A 0 Vec =2.0V; V| = Vin or Vi; lo = 100A 0 0.2 0.2 LOW level output VoL voltage: all outputs Voc = 2.7 V; Vj = Viq or ViL:lo = 100nA 0 0.2 0.2 Vv Vec = 3.0 V; V| = Vin or Vi; lo = 100A 0 0.2 0.2 Vec =45 V; V| = Vin or Vi; lo = 100A 0 0.2 0.2 LOW level output | v4, = 3.0 V; V, = Viy or Vi_-lo = 6MA 0.25 0.40 0.50 V voltage; : V OL | STANDARD outputs Vec =45V; V| = Vin or Vi; lo =12mA 0.35 0.55 0.65 i, _| Input leakage Voc = 5.5 V; V) = Voc or GND 1.0 1.0 LA loc Culeseo ty Voc = 5.5 V; Vi = Vo or GND: Ip = 0 20.0 160 LA Additional Alec quiescent supply Voo = 2.7 Vto3.6 V; Vi = Voc - 0.6 V 500 850 pA current per input NOTE: 1. All typical values are measured at Tamp = 25C. 1998 May 07Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 AC CHARACTERISTICS GND = OV; t, = t < 2.5ns; C_ = 50pF; RL = 1KQ LIMITS SYMBOL PARAMETER WAVEFORM CONDITION 40 to +85 C 40 to +125 C | UNIT Voc(V) MIN | TYP | MAX | MIN | MAX 1.2 - 115 - 2.0 - 38 61 - 76 tpLy/tpHL ed Figures 1, 2 27 - 27 43 - 54 ns 3.00 3.6 - 202 36 - 45 4.5 to 5.5 - 15 24 - 30 1.2 - 110 - 2.0 - 35 56 - 70 te_y/teHL ree a Figures 1, 2 27 - 24 39 - 49 ns 3.00 3.6 - 202 33 - 44 4.5 05.5 - 14 22 - 27 1.2 - 90 - 2.0 - 28 45 - 56 teLytere Propagation olay Figures 1, 2 27 - 20 32 - 40 ns 3.0 to 3.6 - 172 27 - 33 4.5 05.5 - 11 18 - 22 2.0 34 10 - 44 - tw har Pulse wan Figures 1, 2 a . = _ * _ ns 3.0 to 3.6 20 7 - 24 - 4.5 05.5 15 5 - 18 - 2.0 34 10 - 44 - ty Parallel load pulse Figures 1, 2 27 25 8 ~ 30 ~ ns width LOW 3.0 to 3.6 20 72 - 24 - 4.5 05.5 15 5 - 18 - 1.2 - 40 - - - 2.0 24 15 - 30 - trom Prison, ae Figures 1, 2 27 18 11 - 23 - ns 3.00 3.6 17 102 - 24 - 4.5 to 5.5 12 7 - 15 - 1.2 - -8 - - - 2.0 22 -2 - 26 - teu Deter CE Figures 1, 2 27 16 4 - 19 - ns 3.00 3.6 13 12 - 15 - 4.5 to 5.5 9 0 - 10 - 1.2 - 20 - - - 2.0 22 7 - 26 - teu SE OP Cr toCE | Figures 1,2 27 16 5 - 19 - i 3.00 3.6 13 42 - 15 - 4.5 to 5.5 9 3 - 10 - 1998 May 07 6Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 AC CHARACTERISTICS (Continued) GND = OV; t, = } <2.5ns; C_ = 50pF; R, = 1KQ CONDITION 40 to +85 C 40 to +125 C SYMBOL PARAMETER WAVEFORM UNIT VectV) MIN | TYP | MAX | MIN | MAX 1.2 - 25 - - - 2.0 22 8 - 26 - Set-up time . tsu D, to PL Figures 1, 2 2.7 16 6 - 19 - ns 3.0 to 3.6 13 52 - 15 - 4.5 to 5.5 9 4 - 10 - 1.2 - 20 - - - ; 2.0 22 7 - 26 - Holdtime th Dg to CP, CE Figures 1, 2 2.7 16 5 - 19 - ns D, to PL 3.0 to 3.6 13 4 - 15 - 4.5 to 5.5 9 3 - 10 - 1.2 - -30 - - - Hold time 2.0 5 -8 = 5 = th CE to CP, Figures 1, 2 2.7 5 -6 - 5 - ns CP to CE 3.010 3.6 5 62 - 5 - 4.5 to 5.5 5 4 - 5 - 2.0 14 40 - 12 - Maximum clock . 27 19 60 7 16 7 'max | pulse frequency Figures 1, 2 3.010 3.6 24 652 20 MHz 4.5 to 5.5 36 75 - 30 - NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25C 2. Typical values are measured at Voc = 3.3 V. AC WAVEFORMS Vu = 1.5 V at Voc 2 2.7 V. Vu = 0.5 x Voc at Voc < 2.7 V; VoL and Voy are the typical output voltage drop that occur with the output load. vi Vo--- PL INPUT CP INPUT GND - - - 4 GND Vp--- CE, CP INPUT Vou Q7 or Q7 GND OUTPUT VoL Vou The changing to output assumes internal Qg opposite state from Q7. Q7 or Q7 OUTPUT SV00590 Figure 1. Clock (CP) to output (Q; or Q7) propagation delays, the clock pulse width and the maximum clock frequency. Note to Figures 1 and 2 The changing to output assumes internal Qg opposite state from Qz. 1998 May 07 The changing to output assumes internal Qg opposite state from Q7. SV00591 Figure 2. Parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel load to clock (CP) and clock enable (CE) removal time.Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 AC WAVEFORMS Vu = 1.5 V at Voc 2 2.7 V. Vu = 0.5 x Voc at Voc < 2.7 V; VoL and Voy are the typical output voltage drop that occur with the output load. vi Dy INPUT GND Vou @, OUTPUT VoL Vou Q7 OUTPUT Vo. 777 e 800592 Figure 3. Data input (D,) to output (Q7 or Q;) propagation delays when PL is LOW. vi CP, CE INPUT GND vi Dg INPUT GND vi CP, CE INPUT GND CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is permitted to change for predictable output rf - performance. 800595 Figure 4. Set-up and hold times from the serial data input (Ds) to the clock (CP) and the clock enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable input (CE). Note to Figure 4 CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is permitted to change for predictable output performance. 1998 May 07 vi Dn INPUT Vn GND - - tsu tH vi PL INPUT GND SV00593 Figure 5. Set-up and hold times from the data inputs (D,) to the parallel load input (PL). TEST CIRCUIT Vee vi Vo PULSE GENERATOR D.U.T. BOPF 2 4k eT a Test Circuit for Outputs DEFINITIONS R_ = Load resistor C. = Load capacitance includes jig and probe capacitiance Rr = Termination resistance should be equal to Zgut of pulse generators. TEST Veco vi tPLHAPHL <2.7V Vec 2.7-3.6V 2.7V 245V Voc svo0g902 Figure 6. Load circuitry for switching times.Philips Semiconductors 8-bit parallel-in/serial-out shift register Product specification 74LV165 DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 o Cc & Qa D & 3S oO a 0 5 10 mm be scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A Ay Ao (1) (1) zi) UNIT | wax | min. | max. b b, bo c D E e e, L Me My w max. 1.73 0.53 1.25 0.36 19.50 | 6.48 3.60 8.25 10.0 mm 4.2 0.54 3.2 1.30 0.38 0.85 0.23 18.55 6.20 2.54 7.62 3.05 7.80 8.3 0.254 0.76 ; 0.068 | 0.021 | 0.049 | 0.014 0.77 0.26 0.14 0.32 0.39 inches 0.17 | 0.020 | 0.13 | 4051 | 0.015 | 0.033 | 0.009 | 0.73 | 0.24 | %19 | 98 | o42 | 0.31 | 0.33 | 207 | 9-030 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ 92-44-44 SOT38-4 E+ 95-01-14 9 1998 May 07Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 t | f CN e | 8 | Tin: index : : ! : : of jy ;) 4 | , pr pH H ut i: H HE an FI +! co 0 2.5 5mm De scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT max. A, | Ao | Az bp c DM | EM | e He L Lp Q v w y z) | 9 mm | +78 | oa0 | 125 | 929 | 036 | o19| 98 | a8 | t2 | 55 |] o4 | o6 | 22] 9] 1 | 05 | ge ncnes | 0069208] 8957] oo [O12 [00088) 038 1 978 | yaso] 824 aoa [2002/28 o01 | oor [oone| Ome) Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE REFERENCES [EUROPEAN ISSUE DATE IEC JEDEC EIAJ $OT109-1 076E07S MS-012AG eo Sep as 1998 May 07 10Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 aN [ \ T ] | LJ T{ aI) r SS =~ aly He VOR) _ 6 | 9 ' I | | 1 : ff eo | Ao pp ---+---- Ay \ 4 (As) A ! 7 oy" 1 index t | i-~ 6 1 | Lp << i a L +l 0 2.5 5mm scale DIMENSIONS (mm are the original dimensions) UNIT max. A, | Ao | Ags | bp | | DO] EM] e He | L Lp | @ v w y | 2] 6 0.21 | 1.80 0.38 | 0.20] 6.4 | 54 7.9 1.03 | 0.9 1.00 | 8 mm | 20 | 905 | 165 | ?5 | 0.25} 009} 60 | 52 | F] 76 | 175} oes] a7 | %? | 21] OT | O55] oe Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC EIAJ PROJECTION SOT338-1 MO-150AC --} cnop oe 11 1998 May 07Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 Lt CT detail X Jbod 0 2.5 5mm scale DIMENSIONS (mm are the original dimensions) A 1 2 1 UNIT | ax. | At Ao | A3 bp c pM | EA] e He L Lp Q v w y Zz] 6 0.15 | 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.40 8 mm | 119) 905 | o80} 7] 019] 01 | 49 | 43 | 28] 62 | 1 | oso] o3 | %? | 2] OT | oo6 | 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. REFERENCES VERSION PROJECTION | 'SSUEDATE IEC JEDEC EIAJ 0407 42 SOT403-1 MO-153 os 95.04.04 1998 May 07 12Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 NOTES 1998 May 07 13Philips Semiconductors Product specification 8-bit parallel-in/serial-out shift register 74LV165 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published ata later date. Philips Preliminary Specification Preproduction Product Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. seine, . This data sheet contains Final Specifications. Philips Semiconductors reserves the rightto make changes Product Specification Full Production . . oo | | F at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors Copyright Philips Electronics North America Corporation 1998 811 East Arques Avenue All rights reserved. Printed in U.S.A. P.O. Box 3409 Sunnyvale, California 94088-3409 print code Date of release: 05-96 Telephone 800-234-7381 Document order number: 9397-750-04432 Lett make things betew Semiconductors E> PH I LI PS