GBU6B-E3/72 - VISHAY - Datasheet.Live

1. General description

The HEF40193B is a 4-bit synchronous up/down binary counter. The counter has a

count-up clock input (CPU), a count-down clock input (CPD), an asynchronous parallel

load input (PL), four parallel data inputs (D0 to D3), an asynchronous master reset input

(MR), four counter outputs (Q0 to Q3), an active LOW terminal count-up (carry) output

(TCU), and an active LOW terminal count-down (borrow) output (TCD).

The counter outputs change state on the LOW-to-HIGH transition of either clock input.

However, for correct counting, both clock inputs cannot be LOW simultaneously. The

outputs TCU and TCD are normally HIGH. When the circuit has reached the maximum

count state of ‘15’, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.

TCU will stay LOW until CPU goes HIGH again. Likewise, output TCD will go LOW when

the circuit is in the zero state and CPD goes LOW. When PL is LOW, the information on

D0 to D3 is asynchronously loaded into the counter. A HIGH on MR resets the counter

independent of all other input conditions. The counter stages are of a static toggle type

flip-flop.

It operates over a recommended VDD power supply r ange of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is

also suita ble for use over the industrial (−40 °C to +85 °C) temperature range.

2. Features

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Operates across the automotive temperature range −40 °C to +85 °C

Complies with JEDEC standard JESD 13-B

3. Applications

Industrial

HEF40193B

4-bit up/down binary counter

Rev. 06 — 22 December 2009 Product data sheet

Product data sheet Rev. 06 — 22 December 2009 2 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

4. Ordering information

5. Functional diagram

Table 1. Ordering information

All types operate from

−

C to +85

Type number Package

Name Description Version

HEF40193BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

HEF40193BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Fig 1. Functional di agram

001aae58

D0 D1 D2

PARALLEL LOAD CIRCUITRY

Q0 Q1 Q2 Q3

15 1 10 9

3267

CPU CD/SD

UP/DOWN

COUNTER

TCU

TCD

CPD

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 06 — 22 December 2009 3 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

Fig 2. Logic diag ram

001aak06

FF3

TCU TCD

FF4

D3 CPD CPU

FF1

Q1Q0

FF2

D0 D1PL

Product data sheet Rev. 06 — 22 December 2009 4 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 3. Pin configuratio n

HEF40193B

D1 V

Q1 D0

Q0 MR

CPD TCD

CPU TCU

Q2 PL

Q3 D2

001aae581

Table 2. Pin description

Symbol Pin Description

D0 to D3 15, 1, 10, 9 parallel data input

CPU 5 count-up clock pulse input (LOW-to-HIGH, edge-triggered)

CPD 4 count-down clock pulse input (LOW-to-HIGH, edge-triggered)

PL 11 parallel load input (active LOW)

MR 14 master reset input (asynchronous)

Q0 to Q3 3, 2, 6, 7 buffered counter output

TCU 12 buffered terminal count-up (carry) output (active LOW)

TCD 13 buffered terminal count-down (borrow) output (active LOW)

VDD 16 supply voltage

VSS 8 ground supply voltage

Product data sheet Rev. 06 — 22 December 2009 5 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

7. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition.

Table 3. Function table [1]

MR PL CPU CPD Mode

HXXXreset (asynchronous)

L L X X parallel load

LH↑H count-up

LHH↑count-down

Fig 4. Timing diagram

001aae5

015012141310151413

CPU

CPD

TCU

TCD

COUNT

Product data sheet Rev. 06 — 22 December 2009 6 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

8. Limiting values

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.

[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.

9. Recommended operating conditions

Logic equations for terminal count:

Fig 5. Sta t e di agram

001aae58

count up

count down

1 2 3 4

11 10 9 8

TCU Q0 Q1•Q2•Q3•CPU•=

TCD Q0 Q1•Q2•Q3•CPD•=

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +18 V

IIK input clamping current VI<−0.5 V or VI>V

DD + 0.5 V - ±10 mA

VIinput voltage −0.5 VDD + 0.5 V

IOK output clamping current VO<−0.5 V or VO>V

DD + 0.5 V - ±10 mA

II/O input/output current - ±10 mA

IDD supply current - 50 mA

Tstg storage temperature −65 +150 °C

Tamb ambient temperature −40 +85 °C

Ptot total power dissipation DIP16 package [1] -750mW

SO16 package [2] -500mW

P power dissipation per output - 100 mW

Table 5. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air −40 - +85 °C

Product data sheet Rev. 06 — 22 December 2009 7 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

10. Static characteristics

Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 μs/V

VDD = 10 V - - 0.5 μs/V

VDD = 15 V - - 0.08 μs/V

Table 5. Recommended operating con ditions …continued

Symbol Parameter Conditions Min Typ Max Unit

Table 6. Static characteristics

VSS = 0 V; VI = VSS or VDD unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = 25 °C Tamb = 85 °CUnit

Min Max Min Max Min Max

VIH HIGH-level input voltage |IO| < 1 μA 5 V 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - V

15 V 11 .0 - 11.0 - 11.0 - V

VIL LOW-level input voltage |IO| < 1 μA 5 V - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 V

15 V - 4.0 - 4.0 - 4.0 V

VOH HIGH-level output voltage |IO| < 1 μA 5 V 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - V

VOL LOW-level output voltage |IO| < 1 μA 5 V - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 V

IOH HIGH-level output current VO = 2.5 V 5 V −1.7 - −1.4 - −1.1 - mA

VO = 4.6 V 5 V −0.52 - −0.44 - −0.36 - mA

VO = 9.5 V 10 V −1.3 - −1.1 - −0.9 - mA

VO = 13.5 V 15 V −3.6 - −3.0 - −2.4 - mA

IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA

VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA

VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA

IIinput leakage current 15 V - ±0.3 - ±0.3 - ±1.0 μA

IDD supply current IO = 0 A 5 V - 20 - 20 - 150 μA

10 V - 40 - 40 - 300 μA

15 V - 80 - 80 - 600 μA

CIinput capacitance - - - - 7.5 - - pF

Product data sheet Rev. 06 — 22 December 2009 8 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

11. Dynamic characteristics

Table 7. Dynamic characteristics

VSS = 0 V; Tamb = 25

C; for test circuit see Figure 7; unless otherwise speci fied.

Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit

tPHL HIGH to LOW

propagation delay CPU to Qn;

see Figure 6 5 V 183 ns + (0.55 ns/pF)CL- 210 415 ns

10 V 74 ns + (0.23 ns/pF)CL- 85 165 ns

15 V 52 ns + (0.16 ns/pF)CL- 60 120 ns

CPD to Qn;

see Figure 6 5 V 183 ns + (0.55 ns/pF)CL- 210 425 ns

10 V 74 ns + (0.23 ns/pF)CL- 85 170 ns

15 V 57 ns + (0.16 ns/pF)CL- 60 125 ns

CPU to TCU ;

see Figure 6 5 V 98 ns + (0.55 ns/pF)CL- 125 250 ns

10 V 39 ns + (0.23 ns/pF)CL- 50 100 ns

15 V 27 ns + (0.16 ns/pF)CL-3570ns

CPD to TCD ;

see Figure 6 5 V 113 ns + (0.55 ns/pF)CL- 140 280 ns

10 V 44 ns + (0.23 ns/pF)CL-55110ns

15 V 32 ns + (0.16 ns/pF)CL-4080ns

MR to Qn;

see Figure 6 5 V 168 ns + (0.55 ns/pF)CL- 195 390 ns

10 V 69 ns + (0.23 ns/pF)CL- 80 160 ns

15 V 52 ns + (0.16 ns/pF)CL- 60 120 ns

MR to TCD 5 V 338 ns + (0.55 ns/pF)CL- 365 730 ns

10 V 119 ns + (0.23 ns/pF)CL- 130 265 ns

15 V 92 ns + (0.16 ns/pF)CL- 100 205 ns

PL → Qn 5 V 158 ns + (0.55 ns/pF)CL- 185 360 ns

10 V 64 ns + (0.23 ns/pF)CL- 75 150 ns

15 V 47 ns + (0.16 ns/pF)CL-55110ns

Product data sheet Rev. 06 — 22 December 2009 9 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

tPLH LOW to HIGH

propagation delay CPU to Qn;

see Figure 6 5 V 143 ns + (0.55 ns/pF)CL- 170 340 ns

10 V 59 ns + (0.23 ns/pF)CL- 70 140 ns

15 V 42 ns + (0.16 ns/pF)CL- 50 100 ns

CPD to Qn;

see Figure 6 5 V 143 ns + (0.55 ns/pF)CL- 170 340 ns

10 V 59 ns + (0.23 ns/pF)CL- 70 140 ns

15 V 42 ns + (0.16 ns/pF)CL- 50 100 ns

CPU to TCU ;

see Figure 6 5 V 68 ns + (0.55 ns/pF)CL- 95 185 ns

10 V 29 ns + (0.23 ns/pF)CL-4080ns

15 V 22 ns + (0.16 ns/pF)CL-3060ns

CPD to TCD ;

see Figure 6 5 V 73 ns + (0.55 ns/pF)CL- 100 195 ns

10 V 29 ns + (0.23 ns/pF)CL-4085ns

15 V 22 ns + (0.16 ns/pF)CL-3065ns

MR to TCU 5 V 118 ns + (0.55 ns/pF)CL- 145 285 ns

10 V 49 ns + (0.23 ns/pF)CL-60115ns

15 V 37 ns + (0.16 ns/pF)CL-4590ns

PL to Qn 5 V 118 ns + (0.55 ns/pF)CL- 145 290 ns

10 V 49 ns + (0.23 ns/pF)CL- 60 120 ns

15 V 37 ns + (0.16 ns/pF)CL-4590ns

tttransition time see Figure 6 5 V 10 ns + (1.00 ns/p F)CL- 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL-3060ns

15 V 6 ns + (0.28 ns/pF)CL-2040ns

fmax maximum frequency see Figure 6 5 V 2.5 5 - MHz

10 V 7 14 - MHz

15 V 9 18 - MHz

tWpulse width CPU or CPD LOW;

minimum width;

see Figure 6

5 V 150 75 - ns

10 V 50 25 - ns

15 V 35 20 - ns

MR input HIGH;

minimum width;

see Figure 6

5 V 180 90 - ns

10 V 70 35 - ns

15 V 60 30 - ns

PL input LOW;

minimum width;

see Figure 6

5 V 120 60 - ns

10 V 45 20 - ns

15 V 30 15 - ns

trec recovery time MR input;

see Figure 6 5 V 125 65 - ns

10 V 70 35 - ns

15 V 50 25 - ns

PL input

see Figure 6 5 V 90 45 - ns

10 V 35 15 - ns

15 V 25 10 - ns

Table 7. Dynamic characteristics …continued

VSS = 0 V; Tamb = 25

C; for test circuit see Figure 7; unless otherwise speci fied.

Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit

Product data sheet Rev. 06 — 22 December 2009 10 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas show n (CL in pF).

tsu set-up time Dn to PL;

see Figure 6 5 V 160 80 - ns

10 V 60 30 - ns

15 V 50 25 - ns

thhold time Dn to PL;

see Figure 6 5 V +10 −70 - ns

10 V +5 −25 - ns

15 V +5 −20 - ns

Table 7. Dynamic characteristics …continued

VSS = 0 V; Tamb = 25

C; for test circuit see Figure 7; unless otherwise speci fied.

Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit

Table 8. Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf

≤

20 ns; Tamb = 25

Symbol Parameter VDD Typical formula for PD (μW) where:

PDdynamic power dissipation 5 V PD = 600 × fi + Σ(fo × CL) × VDD2fi = input frequency in MHz,

fo = output frequency in MHz,

CL = output load capacitance in pF,

VDD = supply voltage in V,

Σ(fo × CL) = sum of the outputs.

10 V PD = 2700 × fi + Σ(fo × CL) × VDD2

15 V PD = 7500 × fi + Σ(fo × CL) × VDD2

Product data sheet Rev. 06 — 22 December 2009 11 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

12. Waveforms

a. Propagation delays and output transition times

b. PL and MR recovery times, CPU, CPD, PL and MR minimum pulse widths, and Dn to PL set-up and hold times

VOH and VOL are typical output voltage levels that occur with the output load.

Set-up and hold times are shown as positive values but may be specified as negative values.

The shaded area is where the data can change for predictable performance.

Measurement points are given in Table 9.

Fig 6. Waveforms showing switching times

001aak07

MR input

0 V

CPU or CPD

input

0 V

tPLH

tPHL

tttt

0 V

Qn output 90 %

10 %

VOH

VOL

TCU input

TCD input

001aae5

CPU or CPD

input

PL input

Dn input

0 V

MR input

trec

tsu th

0 V

Product data sheet Rev. 06 — 22 December 2009 12 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

a. Input waveforms

b. Test circuit

Test data is given in Table 9.

Definitions for test circuit:

CL = Load capacitance including jig and probe capacitance;

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

Fig 7. Test circuit for switching times

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aaj78

VDD

VIVO

001aag18

DUT

Table 9. Measurement points and test data

Supply voltage Input Load

VIVMtr, tfCL

5Vto15V V

DD 0.5VI≤ 20 ns 50 pF

Product data sheet Rev. 06 — 22 December 2009 13 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

13. Application information

Some examples of applications for the HEF40193B are:

•Up/down difference cou nt ing

•Multistage ripple counting

•Multistage synchronous counting

Fig 8. Example of cascaded HEF40193B ICs

001aae58

CPU

CPD

clock up

D1 D2 D3

Q0 Q1 Q2 Q3 MR

HEF40193B

clock down

CARRY

BORROW

TCU

TCD

CPU

CPD

D1 D2 D3

Q0 Q1 Q2 Q3 MR

HEF40193B

TCU

TCD

Product data sheet Rev. 06 — 22 December 2009 14 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

14. Package outline

Fig 9. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05 0.2542.54 7.62 8.25

7.80

10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051

0.021

0.015

0.014

0.009

1.25

0.85

0.049

0.033

0.77

0.73

0.26

0.24

0.14

0.12 0.010.1 0.3 0.32

0.31

0.39

0.33 0.030.17 0.02 0.13

IP16: plastic dual in-line package; 16 leads (300 mil) SOT38

-4

Product data sheet Rev. 06 — 22 December 2009 15 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

Fig 10. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8 1.27 6.2

5.8

0.7

0.6

0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15 0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

O16: plastic small outline package; 16 leads; body width 3.9 mm SOT109

-1

Product data sheet Rev. 06 — 22 December 2009 16 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

15. Revision history

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF40193B_6 20091222 Product data sheet - HEF40193B_5

Modifications: •Section 2 “Features” ESD data removed.

•Section 9 “Recommended operating conditions” Δt/ΔV values updated.

•Abbreviations section removed.

HEF40193B_5 20090615 Product data sheet - HEF40193B_4

HEF40193B_4 20090505 Product data sheet - HEF40193B_CNV_3

HEF40193B_CNV_3 19950101 Product specification - HEF40193B_CNV_2

HEF40193B_CNV_2 19950101 Product specification - -

Product data sheet Rev. 06 — 22 December 2009 17 of 18

NXP Semiconductors HEF40193B

4-bit up/down binary counter

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short dat a sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

16.3 Disclaimers

General — In formation in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any repr esenta tions or

warranties, expressed or impli ed, as to the accuracy or completeness of such

information and shall have no liability for th e co nsequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, milit ary, aircraft,

space or life support equipment, nor in app lications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ra tings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other co nditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may af fect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertain i ng to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between inf ormation in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Not hing in this document may be interpret ed or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, paten ts or

other industrial or intellectual property right s.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

16.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respective ow ners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

NXP Semiconductors HEF40193B

4-bit up/down binary counter

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 22 December 2009

Document identifier: HEF40193B_6

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 5

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

9 Recommended operating conditions. . . . . . . . 6

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

13 Application information. . . . . . . . . . . . . . . . . . 13

14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

17 Contact information. . . . . . . . . . . . . . . . . . . . . 17

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18