Quad-Channel, 5 kV Isolators with
Integrated DC-to-DC Converter
Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Rev. A
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FEATURES
isoPower integrated, isolated dc-to-dc converter
Regulated 5 V or 3.3 V output
Up to 400 mW output power
16-lead SOIC wide body package (RW-16)
16-lead SOIC wide body package with enhanced
creepage (RI-16-1)
Quad dc-to-25 Mbps (NRZ) signal isolation channels
Schmitt triggered inputs
High temperature operation: 105°C maximum
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals (RI-16-1 package)
UL recognition
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A (pending)
IEC 60601-1: 250 V rms
IEC 60950-1: 400 V rms
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 846 V peak
APPLICATIONS
RS-232/RS-422/RS-485 transceivers
Medical isolation
AC/DC power supply start-up bias and gate drives
Isolated sensor interfaces
GENERAL DESCRIPTION
The ADuM6400/ADuM6401/ADuM6402/ADuM6403/
ADuM64041 are quad-channel digital isolators with isoPower®,
an integrated, isolated dc-to-dc converter. Based on the Analog
Devices, Inc., iCoupler® technology, the dc-to-dc converter provides
up to 400 mW of regulated, isolated power at either 5.0 V or 3.3 V
from a 5.0 V input supply, or at 3.3 V from a 3.3 V supply at the
power levels shown in Table 1. These devices eliminate the need
for a separate, isolated dc-to-dc converter in low power, isolated
designs.
The ADuM6400/ADuM6401/ADuM6402/ADuM6403/
ADuM6404 isolators provide four independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide for more information).
isoPower uses high frequency switching elements to transfer power
through its transformer. Special care must be taken during printed
circuit board (PCB) layout to meet emissions standards. See the
AN-0971 Application Note for board layout recommendations.
FUNCTIONAL BLOCK DIAGRAMS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OSC RECT
4-CHANNEL iCOUPLER CO RE
V
DD1
REG
GND
1
V
IA
/V
OA
V
IB
/V
OB
V
IC
/V
OC
V
ID
/V
OD
V
DDL
GND
1
V
ISO
GND
ISO
V
IA
/V
OA
V
IB
/V
OB
V
IC
/V
OC
V
ID
/V
OD
V
SEL
GND
ISO
ADuM6400/ADuM6401/
ADuM6402/ADuM6403/
ADuM6404
08141-001
Figure 1.
3
4
5
6
14
13
12
11
V
IA
V
IB
V
IC
V
ID
V
OA
V
OB
V
OC
V
OD
ADuM6400
08141-002
Figure 2. ADuM6400
3
4
5
6
14
13
12
11
V
IA
V
IB
V
IC
V
OD
V
OA
V
OB
V
OC
V
ID
ADuM6401
08141-003
Figure 3. ADuM6401
3
4
5
6
14
13
12
11
V
IA
V
IB
V
OC
V
OD
V
OA
V
OB
V
IC
V
ID
ADuM6402
08141-004
Figure 4. ADuM6402
3
4
5
6
14
13
12
11
V
IA
V
OB
V
OC
V
OD
V
OA
V
IB
V
IC
V
ID
ADuM6403
08141-005
Figure 5. ADuM6403
3
4
5
6
14
13
12
11
V
OA
V
OB
V
OC
V
OD
ADuM6404
V
IA
V
IB
V
IC
V
ID
08141-006
Figure 6. ADuM6404
Table 1. Power Levels
Input Voltage Output Voltage Output Power
5.0 V 5.0 V 400 mW
5.0 V 3.3 V 330 mW
3.3 V 3.3 V 132 mW
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet
Rev. A | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—5 V Primary Input Supply/
5 V Secondary Isolated Supply ................................................... 3
Electrical Characteristics—3.3 V Primary Input Supply/
3.3 V Secondary Isolated Supply ................................................ 5
Electrical Characteristics—5 V Primary Input Supply/
3.3 V Secondary Isolated Supply ................................................ 6
Package Characteristics ............................................................... 8
Regulatory Information ............................................................... 9
Insulation and Safety-Related Specifications ............................ 9
Insulation Characteristics .......................................................... 10
Recommended Operating Conditions .................................... 10
Absolute Maximum Ratings .......................................................... 11
ESD Caution ................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Truth Table .................................................................................. 16
Typical Performance Characteristics ........................................... 17
Terminology .................................................................................... 20
Applications Information .............................................................. 21
PCB Layout ................................................................................. 21
Start-Up Behavior....................................................................... 21
EMI Considerations ................................................................... 22
Propagation Delay Parameters ................................................. 22
DC Correctness and Magnetic Field Immunity ..................... 22
Power Consumption .................................................................. 23
Current Limit and Thermal Overload Protection ................. 24
Power Considerations ................................................................ 24
Thermal Analysis ....................................................................... 25
Insulation Lifetime ..................................................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 27
REVISION HISTORY
4/12—Rev. 0 to Rev. A
Changes to Features Section, General Description Section,
and Table 1 ......................................................................................... 1
Changes to Table 2 and Table 3 ....................................................... 3
Changes to Endnote 1 in Table 5 .................................................... 4
Changes to Table 6 and Table 7 ....................................................... 5
Change to Propagation Delay Parameter in Table 8 .................... 5
Changes to Endnote 1 in Table 9; Changes to Table 10 ............... 6
Changes to Table 11 .......................................................................... 7
Changes to Endnote 1 in Table 13; Changes to Table 14 ............. 8
Changes to Regulatory Information Section, Table 15,
and Table 16 ....................................................................................... 9
Changes to Insulation Characteristics Section, Table 17,
and Table 18 ..................................................................................... 10
Changes to Table 20 ........................................................................ 11
Changes to Table 26 ........................................................................ 16
Changes to Figure 13, Figure 14, Figure 15, Figure 17,
and Figure 18 ................................................................................... 17
Changes to Figure 19 and Figure 20............................................. 18
Added Figure 21 and Figure 22; Renumbered
Figures Sequentially ....................................................................... 18
Added Definition of IISO(LOAD) to Terminology Section .............. 20
Changes to PCB Layout Section ................................................... 21
Added Start-Up Behavior Section ................................................ 21
Changes to EMI Considerations Section .................................... 22
Moved Propagation Delay Parameters Section .......................... 22
Changes to Power Consumption Section .................................... 23
Added Current Limit and Thermal Overload Protection
Sect ion .............................................................................................. 24
Moved Thermal Analysis Section ................................................ 25
Changes to Insulation Lifetime Section and Figure 33 ............. 25
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 27
5/09—Revision 0: Initial Version
Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Rev. A | Page 3 of 28
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = VSEL = VISO = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range, which is 4.5 V ≤ VDD1, VSEL, VISO ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are
tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 2. DC-to-DC Converter Static Specifications
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER SUPPLY
Setpoint VISO 4.7 5.0 5.4 V IISO = 0 mA
Line Regulation VISO(LINE) 1 mV/V IISO = 40 mA, VDD1 = 4.5 V to 5.5 V
Load Regulation VISO(LOAD) 1 5 % IISO = 8 mA to 72 mA
Output Ripple VISO(RIP) 75 mV p-p 20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 72 mA
Output Noise VISO(NOISE) 200 mV p-p CBO = 0.1 μF||10 μF, IISO = 72 mA
Switching Frequency fOSC 180 MHz
PWM Frequency fPWM 625 kHz
Output Supply Current IISO(MAX) 80 mA VISO > 4.5 V
Efficiency at IISO(MAX) 34 % IISO = 80 mA
IDD1, No VISO Load IDD1(Q) 13 35 mA
IDD1, Full VISO Load IDD1(MAX) 290 mA
Table 3. DC-to-DC Converter Dynamic Specifications
Parameter Symbol
1 Mbps—A or C Grade 25 Mbps—C Grade
Unit
Test Conditions/
Comments
Min Typ Max Min Typ Max
SUPPLY CURRENT
Input IDD1(D)
ADuM6400 12 64 mA No VISO load
ADuM6401 12 68 mA No VISO load
ADuM6402 13 71 mA No VISO load
ADuM6403 14 75 mA No VISO load
ADuM6404 14 78 mA No VISO load
Available to Load IISO(LOAD)
ADuM6400 80 69 mA
ADuM6401 80 67 mA
ADuM6402 80 65 mA
ADuM6403 80 63 mA
ADuM6404 80 61 mA
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet
Rev. A | Page 4 of 28
Table 4. Switching Specifications
Parameter Symbol
A Grade C Grade
Unit
Test Conditions/
Comments Min Typ Max Min Typ Max
SWITCHING SPECIFICATIONS
Data Rate 1 25 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 55 100 45 60 ns 50% input to 50% output
Pulse Width Distortion PWD 40 6 ns |tPLH − tPHL|
Change vs. Temperature 5 ps/°C
Pulse Width PW 1000 40 ns Within PWD limit
Propagation Delay Skew tPSK 50 15 ns Between any two units
Channel Matching
Codirectional1
tPSKCD 50 6 ns
Opposing Directional2
tPSKOD 50 15 ns
1 7Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the
isolation barrier.
Table 5. Input and Output Characteristics
Parameter Symbol Min Typ Max Unit
Test Conditions/
Comments
DC SPECIFICATIONS
Logic High Input Threshold VIH 0.7 × VISO or 0.7 × VDD1 V
Logic Low Input Threshold VIL 0.3 × VISO or 0.3 × VDD1 V
Logic High Output Voltages VOH V
DD1 − 0.3 or VISO − 0.3 5.0 V IOx = −20 μA, VIx = VIxH
V
DD1 − 0.5 or VISO − 0.5 4.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
Undervoltage Lockout UVLO VDD1, VDDL, VISO supplies
Positive-Going Threshold VUV+ 2.7 V
Negative-Going Threshold VUV− 2.4 V
Hysteresis VUVH 0.3 V
Input Currents per Channel II −20 +0.01 +20 μA 0 V ≤ VIx ≤ VDDx
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient
Immunity1
|CM| 25 35 kV/μs
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.0 Mbps
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high input or VO < 0.3 × VDD1 or 0.3 × VISO for a low
input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Rev. A | Page 5 of 28
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire
recommended operation range, which is 3.0 V ≤ VDD1, VSEL, VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 6. DC-to-DC Converter Static Specifications
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER SUPPLY
Setpoint VISO 3.0 3.3 3.6 V IISO = 0 mA
Line Regulation VISO(LINE) 1 mV/V IISO = 20 mA, VDD1 = 3.0 V to 3.6 V
Load Regulation VISO(LOAD) 1 5 % IISO = 4 mA to 36 mA
Output Ripple VISO(RIP) 50 mV p-p 20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 54 mA
Output Noise VISO(NOISE) 130 mV p-p CBO = 0.1 μF||10 μF, IISO = 54 mA
Switching Frequency fOSC 180 MHz
PWM Frequency fPWM 625 kHz
Output Supply Current IISO(MAX) 40 mA VISO > 3 V
Efficiency at IISO(MAX) 33 % IISO = 40 mA
IDD1, No VISO Load IDD1(Q) 15 28 mA
IDD1, Full VISO Load IDD1(MAX) 175 mA
Table 7. DC-to-DC Converter Dynamic Specifications
Parameter Symbol
1 Mbps—A or C Grade 25 Mbps—C Grade
Unit
Test Conditions/
Comments Min Typ Max Min Typ Max
SUPPLY CURRENT
Input IDD1(D)
ADuM6400 8 41 mA No VISO load
ADuM6401 8 44 mA No VISO load
ADuM6402 8 46 mA No VISO load
ADuM6403 9 47 mA No VISO load
ADuM6404 9 51 mA No VISO load
Available to Load IISO(LOAD)
ADuM6400 40 33 mA
ADuM6401 40 31 mA
ADuM6402 40 30 mA
ADuM6403 40 29 mA
ADuM6404 40 28 mA
Table 8. Switching Specifications
Parameter Symbol
A Grade C Grade
Unit
Test Conditions/
Comments Min Typ Max Min Typ Max
SWITCHING SPECIFICATIONS
Data Rate 1 25 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 60 100 45 65 ns 50% input to 50% output
Pulse Width Distortion PWD 40 6 ns |tPLH − tPHL|
Change vs. Temperature 5 ps/°C
Pulse Width PW 1000 40 ns Within PWD limit
Propagation Delay Skew tPSK 50 45 ns Between any two units
Channel Matching
Codirectional1
tPSKCD 50 6 ns
Opposing Directional2
tPSKOD 50 15 ns
1 7Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the
isolation barrier.
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet
Rev. A | Page 6 of 28
Table 9. Input and Output Characteristics
Parameter Symbol Min Typ Max Unit
Test Conditions/
Comments
DC SPECIFICATIONS
Logic High Input Threshold VIH 0.7 × VISO or 0.7 × VDD1 V
Logic Low Input Threshold VIL 0.3 × VISO or 0.3 × VDD1 V
Logic High Output Voltages VOH V
DD1 − 0.2 or VISO − 0.2 3.3 V IOx = −20 μA, VIx = VIxH
V
DD1 − 0.5 or VISO − 0.5 3.1 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.0 0.4 V IOx = 4 mA, VIx = VIxL
Undervoltage Lockout UVLO VDD1, VDDL, VISO supplies
Positive-Going Threshold VUV+ 2.7 V
Negative-Going Threshold VUV− 2.4 V
Hysteresis VUVH 0.3 V
Input Currents per Channel II −10 +0.01 +10 μA 0 V ≤ VIx ≤ VDDx
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient
Immunity1
|CM| 25 35 kV/μs
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.0 Mbps
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high input or VO < 0.3 × VDD1 or 0.3 × VISO for a low
input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = 5.0 V, VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire
recommended operation range, which is 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 10. DC-to-DC Converter Static Specifications
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER SUPPLY
Setpoint VISO 3.0 3.3 3.6 V IISO = 0 mA
Line Regulation VISO(LINE) 1 mV/V IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
Load Regulation VISO(LOAD) 1 5 % IISO = 10 mA to 90 mA
Output Ripple VISO(RIP) 50 mV p-p 20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 90 mA
Output Noise VISO(NOISE) 130 mV p-p CBO = 0.1 μF||10 μF, IISO = 90 mA
Switching Frequency fOSC 180 MHz
PWM Frequency fPWM 625 kHz
Output Supply Current IISO(MAX) 100 mA VISO > 3 V
Efficiency at IISO(MAX) 30 % IISO = 100 mA
IDD1, No VISO Load IDD1(Q) 11 20 mA
IDD1, Full VISO Load IDD1(MAX) 230 mA
Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Rev. A | Page 7 of 28
Table 11. DC-to-DC Converter Dynamic Specifications
Parameter Symbol
1 Mbps—A or C Grade 25 Mbps—C Grade
Unit
Test Conditions/
Comments Min Typ Max Min Typ Max
SUPPLY CURRENT
Input IDD1(D)
ADuM6400 6 43 mA No VISO load
ADuM6401 6 44 mA No VISO load
ADuM6402 7 45 mA No VISO load
ADuM6403 7 46 mA No VISO load
ADuM6404 7 47 mA No VISO load
Available to Load IISO(LOAD)
ADuM6400 100 93 mA
ADuM6401 100 92 mA
ADuM6402 100 91 mA
ADuM6403 100 89 mA
ADuM6404 100 88 mA
Table 12. Switching Specifications
Parameter Symbol
A Grade C Grade
Unit
Test Conditions/
Comments Min Typ Max Min Typ Max
SWITCHING SPECIFICATIONS
Data Rate 1 25 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 60 100 45 60 ns 50% input to 50% output
Pulse Width Distortion PWD 40 6 ns |tPLH − tPHL|
Change vs. Temperature 5 ps/°C
Pulse Width PW 1000 40 ns Within PWD limit
Propagation Delay Skew tPSK 50 15 ns Between any two units
Channel Matching
Codirectional1
tPSKCD 50 6 ns
Opposing Directional2
tPSKOD 50 15 ns
1 7Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposite sides of the
isolation barrier.
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet
Rev. A | Page 8 of 28
Table 13. Input and Output Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Logic High Input Threshold VIH 0.7 × VISO or
0.7 × VDD1
V
Logic Low Input Threshold VIL 0.3 × VISO or
0.3 × VDD1
V
Logic High Output Voltages VOH VDD1 − 0.2 or
VISO − 0.2
VDD1 or VISO V IOx = −20 μA, VIx = VIxH
VDD1 − 0.5 or
VISO − 0.5
VDD1 − 0.2 or
VISO − 0.2
V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.0 0.4 V IOx = 4 mA, VIx = VIxL
Undervoltage Lockout UVLO VDD1, VDDL, VISO supplies
Positive-Going Threshold VUV+ 2.7 V
Negative-Going Threshold VUV− 2.4 V
Hysteresis VUVH 0.3 V
Input Currents per Channel II −10 +0.01 +10 μA 0 V ≤ VIx ≤ VDDx
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient
Immunity1
|CM| 25 35 kV/μs
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.0 Mbps
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high input or VO < 0.3 × VDD1 or 0.3 × VISO for a low
input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
PACKAGE CHARACTERISTICS
Table 14.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
RESISTANCE AND CAPACITANCE
Resistance (Input-to-Output)1
RI-O 1012 Ω
Capacitance (Input-to-Output)1
CI-O 2.2 pF f = 1 MHz
Input Capacitance2
CI 4.0 pF
IC Junction-to-Ambient Thermal
Resistance
θJA 45 °C/W
Thermocouple is located at the center of
the package underside; test conducted
on a 4-layer board with thin traces3
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSSD 150 °C TJ rising
Thermal Shutdown Hysteresis TSSD-HYS 20 °C
1 This device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
3 Refer to the section for thermal model definitions. Thermal Analysis
Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Rev. A | Page 9 of 28
REGULATORY INFORMATION
The ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 are approved by the organizations listed in Table 1 5. Refer to Tabl e 20
and the Insulation Lifetime section for more information about the recommended maximum working voltages for specific cross-insulation
waveforms and insulation levels.
Table 15.
UL1CSA (Pending) VDE
Recognized under UL 1577 component
recognition program
Approved under CSA Component Acceptance Notice #5A RW-16 package:2
Certified according to IEC 60747-5-2
(VDE 0884 Part 2):2003-01 (pending)
Basic insulation, 846 V peak
Single protection, 5000 V rms isolation
voltage
Basic insulation per CSA 60950-1-07 and IEC 60950-1,
600 V rms (848 V peak) maximum working voltage
RI-16-1 package:3
Certified according to DIN V VDE V
0884-10 (VDE V 0884-10):2006-12
Reinforced insulation, 846 V peak
RW-16 package:
Reinforced insulation per CSA 60950-1-07 and IEC 60950-1,
380 V rms (537 V peak) maximum working voltage
Reinforced insulation per IEC 60601-1, 125 V rms (176 V peak)
maximum working voltage
RI-16-1 package:
Reinforced insulation per CSA 60950-1-07 and IEC 60950-1,
400 V rms (565 V peak) maximum working voltage
Reinforced insulation per IEC 60601-1, 250 V rms (353 V peak)
maximum working voltage
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 is proof-tested by applying an insulation test voltage ≥ 6000 V rms for
1 sec (current leakage detection limit = 20 μA).
2 In accordance with IEC 60747-5-2 (VDE 0884 Part 2):2003-01, each ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 in the RW-16 package is proof-tested
by applying an insulation test voltage ≥ 1590 V peak for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates
IEC 60747-5-2 (VDE 0884 Part 2):2003-01 approval.
3 In accordance with DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, each ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 in the RI-16-1 package is proof-tested
by applying an insulation test voltage ≥ 1590 V peak for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 16.
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 5000 V rms 1-minute duration
Minimum External Air Gap (Clearance) L(I01) 8.0 mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(I02) Measured from input terminals to output terminals,
shortest distance path along body
RW-16 Package 7.6 mm
RI-16-1 Package 8.3 mm
Minimum Internal Distance (Internal Clearance) 0.017 min mm Distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303, Part 1
Material Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet
Rev. A | Page 10 of 28
INSULATION CHARACTERISTICS
IEC 60747-5-2 (VDE 0884 Part 2):2003-01 and DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking branded on the components designates IEC 60747-5-2 (VDE 0884 Part 2):2003-01 or DIN V
VDE V 0884-10 (VDE V 0884-10):2006-12 approval.
Table 17.
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 450 V rms I to II
For Rated Mains Voltage ≤ 600 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 846 V peak
Input-to-Output Test Voltage
Method b1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VPR 1590 V peak
Method a VPR
After Environmental Tests Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC 1375 V peak
After Input and/or Safety Tests
Subgroup 2 and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 1018 V peak
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 sec VIOTM 6000 V peak
Safety-Limiting Values Maximum value allowed in the event of a failure
(see Figure 7)
Case Temperature TS 150 °C
Side 1 Current (IDD1) IS1 555 mA
Insulation Resistance at TS V
IO = 500 V RS >109 Ω
Thermal Derating Curve
0
100
200
300
400
500
600
0 50 100 150 200
AMBIENT T E M P E RATURE (°C)
SAFE OPERATI NG V
DD1
CURRENT ( mA)
08141-007
Figure 7. Thermal Derating Curve, Dependence of Safety-Limiting Values on Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 18.
Parameter Symbol Min Max Unit Test Conditions/Comments
TEMPERATURE
Operating Temperature TA −40 +105 °C
Operation at 105°C requires reduction of the
maximum load current as specified in Table 19
SUPPLY VOLTAGES VDD1 Each voltage is relative to its respective ground
VDD1 @ VSEL = GNDISO 3.0 5.5 V
VDD1 @ VSEL = VISO 4.5 5.5 V
Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Rev. A | Page 11 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 19.
Parameter Rating
Storage Temperature Range (TST) −55°C to +150°C
Ambient Operating Temperature
Range (TA)
−40°C to +105°C
Supply Voltages (VDD1, VDDL, VISO)1 −0.5 V to +7.0 V
Input Voltage (VIA, VIB, VIC, VID, VSEL)1, 2 −0.5 V to VDDI + 0.5 V
Output Voltage (VOA, VOB, VOC, VOD)1, 2 −0.5 V to VDDO + 0.5 V
Average Output Current per Pin3 −10 mA to +10 mA
Common-Mode Transients4 −100 kV/μs to +100 kV/μs
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1 Each voltage is relative to its respective ground.
2 VDDI and VDDO refer to the supply voltages on the input and output sides of
a given channel, respectively. See the PCB Layout section.
3 See Figure 7 for maximum rated current values for various temperatures.
4 Common-mode transients exceeding the absolute maximum ratings may
cause latch-up or permanent damage.
Table 20. Maximum Continuous Working Voltage1
Parameter Max Unit Applicable Certification
AC Voltage, Bipolar Waveform 424 V peak All certifications, 50-year operation
AC Voltage, Unipolar Waveform
Basic Insulation 600 V peak
Reinforced Insulation 565 V peak Working voltage per IEC 60950-1
DC Voltage
Basic Insulation 600 V peak
Reinforced Insulation 565 V peak Working voltage per IEC 60950-1
1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet
Rev. A | Page 12 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD1 1
GND
12
V
IA 3
V
IB 4
V
ISO
16
GND
ISO
15
V
OA
14
V
OB
13
V
IC 5
V
OC
12
V
ID 6
V
OD
11
V
DDL 7
V
SEL
10
GND
18
GND
ISO
9
ADuM6400
TOP VIEW
(Not to Scale)
08141-008
Figure 8. ADuM6400 Pin Configuration
Table 21. ADuM6400 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
2, 8 GND1 Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other, and
it is recommended that both pins be connected to a common ground.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 VID Logic Input D.
7 VDDL Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
9, 15 GNDISO Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each other,
and it is recommended that both pins be connected to a common ground.
10 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11 VOD Logic Output D.
12 VOC Logic Output C.
13 VOB Logic Output B.
14 VOA Logic Output A.
16 VISO Secondary Supply Voltage Output for External Loads: 3.3 V (VSEL = GNDISO) or 5.0 V (VSEL = VISO).
Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Rev. A | Page 13 of 28
V
DD1 1
GND
12
V
IA 3
V
IB 4
V
ISO
16
GND
ISO
15
V
OA
14
V
OB
13
V
IC 5
V
OC
12
V
OD 6
V
ID
11
V
DDL 7
V
SEL
10
GND
18
GND
ISO
9
ADuM6401
TOP VIEW
(Not to Scale)
08141-009
Figure 9. ADuM6401 Pin Configuration
Table 22. ADuM6401 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
2, 8 GND1 Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other, and
it is recommended that both pins be connected to a common ground.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 VOD Logic Output D.
7 VDDL Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
9, 15 GNDISO Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each other,
and it is recommended that both pins be connected to a common ground.
10 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11 VID Logic Input D.
12 VOC Logic Output C.
13 VOB Logic Output B.
14 VOA Logic Output A.
16 VISO Secondary Supply Voltage Output for External Loads: 3.3 V (VSEL = GNDISO) or 5.0 V (VSEL = VISO).
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet
Rev. A | Page 14 of 28
V
DD1 1
GND
12
V
IA 3
V
IB 4
V
ISO
16
GND
ISO
15
V
OA
14
V
OB
13
V
OC 5
V
IC
12
V
OD 6
V
ID
11
V
DDL 7
V
SEL
10
GND
18
GND
ISO
9
ADuM6402
TOP VIEW
(Not to Scale)
08141-010
Figure 10. ADuM6402 Pin Configuration
Table 23. ADuM6402 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
2, 8 GND1 Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other, and
it is recommended that both pins be connected to a common ground.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VOC Logic Output C.
6 VOD Logic Output D.
7 VDDL Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
9, 15 GNDISO Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each other,
and it is recommended that both pins be connected to a common ground.
10 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11 VID Logic Input D.
12 VIC Logic Input C.
13 VOB Logic Output B.
14 VOA Logic Output A.
16 VISO Secondary Supply Voltage Output for External Loads: 3.3 V (VSEL = GNDISO) or 5.0 V (VSEL = VISO).
Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Rev. A | Page 15 of 28
V
DD1 1
GND
12
V
IA 3
V
OB 4
V
ISO
16
GND
ISO
15
V
OA
14
V
IB
13
V
OC 5
V
IC
12
V
OD 6
V
ID
11
V
DDL 7
V
SEL
10
GND
18
GND
ISO
9
ADuM6403
TOP VIEW
(Not to Scale)
08
Figure 11. ADuM6403 Pin Configuration
ble 24. A Pin
. nic
141-011
Ta DuM6403 Function Descriptions
Pin No Mnemo Description
1 VDD1 the same external voltage source. Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to
2, 8 GND1
ded that both pins be connected to a common ground.
Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other, and
it is recommen
3 VIA Logic Input A.
4 VOB Logic Output B.
5 VOC Logic Output C.
6 VOD Logic Output D.
7 VDDL Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.
9, 15 GNDISO Ground Reference for the Secondary Side of the Isolator. Pin 9 and Pin 15 are internally connected to each other,
and it is recommended that both pins be connected to a common ground.
10 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11 VID Logic Input D.
12 VIC Logic Input C.
13 VIB Logic Input B.
14 VOA Logic Output A.
16 VISO Secondary Supply Voltage Output for External Loads: 3.3 V (VSEL = GNDISO) or 5.0 V (VSEL = VISO).
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet
Rev. A | Page 16 of 28
V
DD1 1
GND
12
V
OA 3
V
OB 4
V
ISO
16
GND
ISO
15
V
IA
14
V
IB
13
V
OC 5
V
IC
12
V
6
OD
V
11 ID
V
DDL 7
V
SEL
10
GND
18
GND
ISO
9
ADuM6404
TOP VIEW
(Not to Scale)
08
Figure 12. ADuM6404 Pin Configuration
141-012
Table 25. AD Pin F riptions
.
uM6404 unction Desc
Pin No M emonic n Description
1 VDD1 oltage source. Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external v
2, 8 GND1 Ground Reference for the Primary Side of the Isolator. Pin 2 and Pin 8 are internally connected to each other, and
it is recommended that both pins be connected to a common ground.
3 VOA Logic Output A.
4 VOB Logic Output B.
5 VOC Logic Output C.
6 VOD ic OuLog tput D.
7 VDDL Data Cha pply Voltag nected to the same external voltage source. nnel Su e, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be con
9, 15 GNDIGround R e for the S e internally connected to each other,
and it is r ended tha ound.
SO eferenc econdary Side of the Isolator. Pin 9 and Pin 15 ar
ecomm t both pins be connected to a common gr
10 VSEL Output V e Selection. W V. oltag hen VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3
11 VID Logic Input D.
12 VIC Logic Input C.
13 VIB Logic Input B.
14 VIA Logic Input A.
16 VISO Secondary Supply Voltage Output for External Loads: 3.3 V (VSEL = GNDISO) or 5.0 V (VSEL = VISO).
TRUTH TABLE
Table 26. Power Control Truth Table (Positive Logic)
VSEL Input VDD1 Input VISO Output Operation
High 5 V 5 V Self-regulation mode, normal operation
Low 5 V 3.3 V Self-regulation mode, normal operation
Low 3.3 V 3.3 V Self-regulation mode, normal operation
High 3.3 V 5 V This supply configuration is not recommended due to extremely poor efficiency
Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Rev. A | Page 17 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
0
5
10
15
20
25
30
35
0 20 40 60 80 100 120
08141-033
I
ISO
CURRENT ( mA)
EFFICIENCY ( %)
5.0V INPUT/5.0V O UTP UT
5.0V INPUT/3.3V O UTP UT
3.3V INPUT/3.3V O UTP UT
Figure 13. Typical Power Supply Efficiency
in All Supported Power Configurations
0
20
40
60
80
100
120
0 50 100 150 200 250 300
I
DD1
CURRENT (mA)
I
ISO
CURRENT ( mA)
08141-035
5.0V INPUT/ 5.0V OUTPUT
5.0V INPUT/ 3.3V OUTPUT
3.3V INPUT/ 3.3V OUTPUT
Figure 14. Typical Isolated Output Supply Current vs. Input Current
in All Supported Power Configurations
0
200
400
600
800
1000
1200
0 20406080100120
I
ISO
CURRENT ( mA)
TOTAL POW ER DISSIPATION (mW)
5.0V INPUT/5.0V OUTPUT
5.0V INPUT/3.3V OUTPUT
3.3V INPUT/3.3V OUTPUT
08141-034
Figure 15. Typical Total Power Dissipation vs. Isolated Output Supply Current
in All Supported Power Configurations
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
INPUT SUPPLY VOLTAGE (V)
INPUT CURRENT (A)
POWER (W)
I
DD1
POWER
08141-036
Figure 16. Typical Short-Circuit Input Current and Power
vs. VDD1 Supply Voltage
TIME (ms)
0
40
4.6
4.8
5.0
5.2
5.4
20
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VISO (V)
IISO (mA)
10% LOAD
90% LO AD
10% LOAD
08141-107
Figure 17. Typical VISO Transient Load Response, 5 V Output,
10% to 90% Load Step
TIME (ms)
0
40
60
3.1
3.3
3.5
3.7
20
00.51.01.52.02.53.03.54.0
VISO (V)
IISO (mA)
10% LOAD
90% LOAD
10% LOAD
08141-108
Figure 18. Typical VISO Transient Load Response, 3.3 V Output,
10% to 90% Load Step
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet
Rev. A | Page 18 of 28
TIME (µs)
RC
SIG NAL (V) V
ISO
(V)
5.02
5.00
4.98
4.96
4.94
4.92
4.90
5.0
2.5
00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
08141-109
Figure 19. Typical Output Voltage Ripple at 90% Load, VISO = 5 V
TIME (µs)
RC
SIG NAL ( V) V
ISO
(V)
3.34
3.30
3.32
3.28
3.26
3.24
4
2
00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
08141-110
Figure 20. Typical Output Voltage Ripple at 90% Load, VISO = 3.3 V
0
1
2
3
4
5
6
7
–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0
V
ISO
(V)
TIME (ms)
90% LOAD
10% LOAD
08141-112
Figure 21. Typical Output Voltage Start-Up Transient
at 10% and 90% Load, VISO = 5 V
0
1
2
3
4
5
–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0
V
ISO
(V)
Time ( ms)
90% L OAD
10% L OAD
08141-113
Figure 22. Typical Output Voltage Start-Up Transient
at 10% and 90% Load, VISO = 3.3 V
0
4
8
12
16
20
051015
DATA RATE (Mbps)
SUPPLY CURRENT (mA)
20 25
08141-041
5.0V INP UT/ 5.0V OUT P UT
5.0V INP UT/ 3.3V OUT P UT
3.3V INP UT/ 3.3V OUT P UT
Figure 23. Typical ICHn Supply Current per Forward Data Channel
(15 pF Output Load)
0
4
8
12
16
20
051015
DATA RATE (Mbps)
SUPPL Y CURRE NT (mA)
20 25
5.0V INPUT/5 .0V OUTPUT
5.0V INPUT/3 .3V OUTPUT
3.3V INPUT/3 .3V OUTPUT
08141-042
Figure 24. Typical ICHn Supply Current per Reverse Data Channel
(15 pF Output Load)
Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Rev. A | Page 19 of 28
051015
DATA RATE (Mbps)
SUPPL Y CURRE NT (mA)
20 25
5V
3.3V
08141-043
0
2
1
3
4
5
Figure 25. Typical IISO(D) Dynamic Supply Current per Input
0
1.0
0.5
1.5
2.0
2.5
3.0
051015
DATA RATE (Mbps)
SUPPL Y CURRE NT (mA)
20 25
5V
3.3V
08141-044
Figure 26. Typical IISO(D) Dynamic Supply Current per Output
(15 pF Output Load)
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet
Rev. A | Page 20 of 28
TERMINOLOGY
IDD1(Q)
IDD1(Q) is the minimum operating current drawn at the VDD1
pin when there is no external load at VISO and the I/O pins are
operating below 2 Mbps, requiring no additional dynamic
supply current. IDD1(Q) reflects the minimum current operating
condition.
IDD1(D)
IDD1(D) is the typical input supply current with all channels
simultaneously driven at a maximum data rate of 25 Mbps
with full capacitive load representing the maximum dynamic
load conditions. Resistive loads on the outputs should be
treated separately from the dynamic load.
IDD1(MAX)
IDD1(MAX) is the input current under full dynamic and VISO load
conditions.
IISO(LOAD)
IISO(LOAD) is the current available to the load.
tPHL Propagation Delay
The tPHL propagation delay is measured from the 50% level of
the falling edge of the VIx signal to the 50% level of the falling
edge of the VOx signal.
tPLH Propagation Delay
The tPLH propagation delay is measured from the 50% level of
the rising edge of the VIx signal to the 50% level of the rising
edge of the VOx signal.
Propagation Delay Skew (tPSK)
tPSK is the magnitude of the worst-case difference in tPHL and/
or tPLH that is measured between units at the same operating
temperature, supply voltages, and output load within the
recommended operating conditions.
Channel-to-Channel Matching (tPSKCD/tPSKOD)
Channel-to-channel matching is the absolute value of the
difference in propagation delays between two channels when
operated with identical loads.
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed.
Maximum Data Rate
The maximum data rate is the fastest data rate at which the
specified pulse width distortion is guaranteed.
Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Rev. A | Page 21 of 28
APPLICATIONS INFORMATION
The dc-to-dc converter section of the ADuM640x works on
principles that are common to most switching power supplies. It
has a secondary side controller architecture with isolated pulse-
width modulation (PWM) feedback. VDD1 power is supplied to
an oscillating circuit that switches current into a chip scale air
core transformer. Power transferred to the secondary side is
rectified and regulated to either 3.3 V or 5 V. The secondary
(VISO) side controller regulates the output by creating a PWM
control signal that is sent to the primary (VDD1) side by a dedicated
iCoupler data channel. The PWM modulates the oscillator
circuit to control the power being sent to the secondary side.
Feedback allows for significantly higher power and efficiency.
The ADuM640x implements undervoltage lockout (UVLO)
with hysteresis on the VDD1 power input. This feature ensures
that the converter does not enter oscillation due to noisy input
power or slow power-on ramp rates.
A minimum load current of 10 mA is recommended to ensure
optimum load regulation. Smaller loads can generate excess noise
on chip due to short or erratic PWM pulses. Excess noise that is
generated in this way can cause data corruption, in some cases.
PCB LAYOUT
The ADuM640x digital isolators with 0.4 W isoPower integrated
dc-to-dc converter require no external interface circuitry for the
logic interfaces. Power supply bypassing is required at the input
and output supply pins (see Figure 27). Note that low ESR bypass
capacitors are required between Pin 1 and Pin 2 and between
Pin 15 and Pin 16, as close to the chip pads as possible.
The power supply section of the ADuM640x uses a 180 MHz
oscillator frequency to pass power efficiently through its chip
scale transformers. In addition, the normal operation of the data
section of the iCoupler introduces switching transients on the
power supply pins. Bypass capacitors are required for several
operating frequencies. Noise suppression requires a low induc-
tance, high frequency capacitor, whereas ripple suppression and
proper regulation require a large value capacitor. These capacitors
are most conveniently connected between Pin 1 and Pin 2 for
VDD1, and between Pin 15 and Pin 16 for VISO.
To suppress noise and reduce ripple, a parallel combination of
at least two capacitors is required. The recommended capacitor
values are 0.1 μF and 10 μF for VDD1 and VISO. The smaller
capacitor must have a low ESR; for example, use of a ceramic
capacitor is advised.
The total lead length between the ends of the low ESR capacitor
and the input power supply pin must not exceed 2 mm. Installing
the bypass capacitor with traces more than 2 mm in length may
result in data corruption. Consider bypassing between Pin 1
and Pin 8 and between Pin 9 and Pin 16 unless both common
ground pins are connected together close to the package.
V
DD1
GND
1
V
ISO
GND
ISO
V
IA
/V
OA
V
IB
/V
OB
V
IC
/V
OC
V
DDL
V
ID
/V
OD
V
IA
/V
OA
V
IB
/V
OB
V
IC
/V
OC
V
ID
/V
OD
V
SEL
GND
1
BYPASS < 2mm
GND
ISO
08141-025
Figure 27. Recommended PCB Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling that
does occur affects all pins equally on a given component side.
Failure to ensure this can cause voltage differentials between
pins exceeding the absolute maximum ratings for the device
as specified in Table 19, thereby leading to latch-up and/or
permanent damage.
The ADuM640x is a power device that dissipates approximately
1 W of power when fully loaded and running at maximum speed.
Because it is not possible to apply a heat sink to an isolation
device, the device primarily depends on heat dissipation into
the PCB through the GND pins. If the device is used at high
ambient temperatures, provide a thermal path from the GND
pins to the PCB ground plane. The board layout in Figure 27
shows enlarged pads for Pin 8 (GND1) and Pin 9 (GNDISO).
Multiple vias should be implemented from the pad to the ground
plane to significantly reduce the temperature inside the chip.
The dimensions of the expanded pads are at the discretion of
the designer and depend on the available board space.
START-UP BEHAVIOR
The ADuM640x devices do not contain a soft start circuit.
Therefore, the start-up current and voltage behavior must be
taken into account when designing with this device.
When power is applied to VDD1, the input switching circuit begins
to operate and draw current when the UVLO minimum voltage
is reached. The switching circuit drives the maximum available
power to the output until it reaches the regulation voltage where
PWM control begins. The amount of current and the time
required to reach regulation voltage depends on the load and
the VDD1 slew rate.
With a fast VDD1 slew rate (200 μs or less), the peak current draws
up to 100 mA/V of VDD1. The input voltage goes high faster than
the output can turn on, so the peak current is proportional to
the maximum input voltage.
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet
Rev. A | Page 22 of 28
With a slow VDD1 slew rate (in the millisecond range), the input
voltage is not changing quickly when VDD1 reaches the UVLO
minimum voltage. The current surge is approximately 300 mA
because VDD1 is nearly constant at the 2.7 V UVLO voltage. The
behavior during startup is similar to when the device load is a
short circuit; these values are consistent with the short-circuit
current shown in Figure 16.
When starting the device for VISO = 5 V operation, do not limit
the current available to the VDD1 power pin to less than 300 mA.
The ADuM640x devices may not be able to drive the output to
the regulation point if a current-limiting device clamps the VDD1
voltage during startup. As a result, the ADuM640x devices can
draw large amounts of current at low voltage for extended
periods of time.
The output voltage of the ADuM640x devices exhibits VISO
overshoot during startup. If this overshoot could potentially
damage components attached to VISO, a voltage-limiting device
such as a Zener diode can be used to clamp the voltage. Typical
behavior is shown in Figure 21 and Figure 22.
EMI CONSIDERATIONS
The dc-to-dc converter section of the ADuM640x devices must
operate at 180 MHz to allow efficient power transfer through the
small transformers. This creates high frequency currents that can
propagate in circuit board ground and power planes, causing
edge emissions and dipole radiation between the primary and
secondary ground planes. Grounded enclosures are recommended
for applications that use these devices. If grounded enclosures
are not possible, follow good RF design practices in the layout
of the PCB. See the AN-0971 Application Note for board layout
recommendations.
PROPAGATION DELAY PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output may differ from the propagation
delay to a logic high output.
INPUT (
V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
08141-026
Figure 28. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM640x component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM640x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than 1 μs, a
periodic set of refresh pulses indicative of the correct input state
is sent to ensure dc correctness at the output. If the decoder
receives no internal pulses for more than approximately 5 μs, the
input side is assumed to be unpowered or nonfunctional, and
the isolator output is forced to a default state by the watchdog
timer circuit. This situation should occur in the ADuM640x
devices only during power-up and power-down operations.
The limitation on the magnetic field immunity of the ADuM640x
is set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this may occur. The 3.3 V operating condition of the
ADuM640x is examined because it represents the most suscept-
ible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at approximately
0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt) ∑ πrn2; n = 1, 2, … , N
where:
β is the magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the total number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM640x and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 29.
MAGNETIC FIELD FREQUENCY (Hz)
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
0.001 1M
10
0.01
1k 10k 10M
0.1
1
100M100k
08141-027
Figure 29. Maximum Allowable External Magnetic Flux Density
Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Rev. A | Page 23 of 28
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This voltage is approxi-
mately 50% of the sensing threshold and does not cause a faulty
output transition. Similarly, if such an event occurs during a
transmitted pulse (and is of the worst-case polarity), it reduces
the received pulse from >1.0 V to 0.75 V—still well above the
0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM640x transformers. Figure 30 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown in Figure 30, the ADuM640x is extremely
immune and can be affected only by extremely large currents
operated at high frequency very close to the component. For the
1 MHz example noted, a 0.5 kA current placed 5 mm away from
the ADuM640x is required to affect the operation of the device.
MAG NETI C F IEL D FREQ UENCY (Hz)
MAXI M UM ALLOWABLE CURRENT (kA)
1k
100
10
1
0.1
0.011k 10k 100M100k 1M 10M
DIST ANCE = 5mm
DIST ANCE = 1m
DIS T ANCE = 100mm
08141-028
Figure 30. Maximum Allowable Current
for Various Current-to-ADuM640x Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce error
voltages sufficiently large to trigger the thresholds of succeeding
circuitry. Exercise care in the layout of such traces to avoid this
possibility.
POWER CONSUMPTION
The VDD1 power supply input provides power to the iCoupler data
channels as well as to the power converter. For this reason, the
quiescent currents drawn by the data converter and the primary
and secondary input/output channels cannot be determined
separately. All of these quiescent power demands are combined
into the IDD1(Q) current shown in Figure 31. The total IDD1 supply
current is the sum of the quiescent operating current, the dynamic
current IDD1(D) demanded by the I/O channels, and any external
IISO load.
CONVERTER
PRIMARY CONVERTER
SECONDARY
PRIMARY
DATA
INPUT/OUTPUT
4-CHANNEL
I
DDP(D)
SECONDARY
DATA
INPUT/OUTPUT
4-CHANNEL
I
ISO(D)
I
ISO
I
DD1(Q)
I
DD1(D)
0
8141-029
Figure 31. Power Consumption Within the ADuM640x
Both dynamic input and output current is consumed only
when operating at channel speeds higher than the refresh
rate, fr. Each channel has a dynamic current determined by
its data rate. Figure 23 shows the current for a channel in the
forward direction, which means that the input is on the primary
side of the part. Figure 24 shows the current for a channel in the
reverse direction, which means that the input is on the secondary
side of the part. Both figures assume a typical 15 pF load. The
following relationship allows the total IDD1 current to be calculated:
IDD1 = (IISO × VISO)/(E × VDD1) + ∑ ICHn; n = 1 to 4 (1)
where:
IDD1 is the total supply input current.
IISO is the current drawn by the secondary side external loads.
E is the power supply efficiency at the maximum load from
Figure 13 at the VISO and VDD1 condition of interest.
ICHn is the current drawn by a single channel, determined from
Figure 23 or Figure 24, depending on channel direction.
Calculate the maximum external load by subtracting the
dynamic output load from the maximum allowable load.
IISO(LOAD) = IISO(MAX) − ∑ IISO(D)n; n = 1 to 4 (2)
where:
IISO(LOAD) is the current available to supply an external secondary
side load.
IISO(MAX) is the maximum external secondary side load current
available at VISO.
IISO(D)n is the dynamic load current drawn from VISO by an input
or output channel, as shown in Figure 23 and Figure 24 for a
typical 15 pF load.
This analysis assumes a 15 pF capacitive load on each data output.
If the capacitive load is larger than 15 pF, the additional current
must be included in the analysis of IDD1 and IISO(LOAD).
To determin e IDD1 in Equation 1, additional primary side
dynamic output current (IAOD) is added directly to IDD1.
Additional secondary side dynamic output current (IAOD)
is added to IISO on a per-channel basis.
To determin e IISO(LOAD) in Equation 2, additional secondary
side output current (IAOD) is subtracted from IISO(MAX) on a
per-channel basis.
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet
Rev. A | Page 24 of 28
For each output channel with CL greater than 15 pF, the
additional capacitive supply current is given by
IAOD = 0.5 × 10−3 × ((CL − 15) × VISO) × (2f − fr); f > 0.5 fr (3)
where:
CL is the output load capacitance (pF).
VISO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half the input
data rate expressed in units of Mbps.
fr is the input channel refresh rate (Mbps).
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADuM640x is protected against damage due to excessive
power dissipation by thermal overload protection circuits.
Thermal overload protection limits the junction temperature to
a maximum of 150°C (typical). Under extreme conditions (that
is, high ambient temperature and power dissipation), when the
junction temperature starts to rise above 150°C, the PWM is
turned off, turning off the output current. When the junction
temperature drops below 130°C (typical), the PWM turns on
again, restoring the output current to its nominal value.
Consider the case where a hard short from VISO to ground occurs.
At first, the ADuM640x reaches its maximum current, which is
proportional to the voltage applied at VDD1. Power dissipates on
the primary side of the converter (see Figure 16). If self-heating
of the junction becomes great enough to cause its temperature
to rise above 150°C, thermal shutdown is activated, turning off
the PWM and turning off the output current. As the junction
temperature cools and drops below 130°C, the PWM turns on
and power dissipates again on the primary side of the converter,
causing the junction temperature to rise to 150°C again. This
thermal oscillation between 130°C and 150°C causes the part
to cycle on and off as long as the short remains at the output.
Thermal limit protections are intended to protect the device
against accidental overload conditions. For reliable operation,
externally limit device power dissipation to prevent junction
temperatures from exceeding 130°C.
POWER CONSIDERATIONS
The ADuM6400/ADuM6401/ADuM6402/ADuM6403/
ADuM6404 power input, data input channels on the primary
side, and data input channels on the secondary side are all
protected from premature operation by undervoltage lockout
(UVLO) circuitry. Below the minimum operating voltage, the
power converter holds its oscillator inactive, and all input channel
drivers and refresh circuits are idle. Outputs remain in a high
impedance state to prevent transmission of undefined states
during power-up and power-down operations.
During application of power to VDD1, the primary side circuitry
is held idle until the UVLO preset voltage is reached. At that
time, the data channels initialize to their default low output
state until they receive data pulses from the secondary side.
When the primary side is above the UVLO threshold, the data
input channels sample their inputs and begin sending encoded
pulses to the inactive secondary output channels. The outputs
on the primary side remain in their default low state because no
data comes from the secondary side inputs until secondary side
power is established. The primary side oscillator also begins to
operate, transferring power to the secondary power circuits.
The secondary VISO voltage is below its UVLO limit at this point;
the regulation control signal from the secondary side is not being
generated. The primary side power oscillator is allowed to free
run under these conditions, supplying the maximum amount of
power to the secondary side.
As the secondary side voltage rises to its regulation setpoint,
a large inrush current transient is present at VDD1. When the
regulation point is reached, the regulation control circuit pro-
duces the regulation control signal that modulates the oscillator
on the primary side. The VDD1 current is then reduced and is
proportional to the load current. The inrush current is less than
the short-circuit current shown in Figure 16. The duration of
the inrush current depends on the VISO loading conditions and
on the current and voltage available at the VDD1 pin.
As the secondary side converter begins to accept power from
the primary, the VISO voltage starts to rise. When the secondary
side UVLO is reached, the secondary side outputs are initialized
to their default low state until data is received from the corre-
sponding primary side input. It can take up to 1 μs after the
secondary side is initialized for the state of the output to
correlate to the primary side input.
Secondary side inputs sample their state and transmit it to the
primary side. Outputs are valid about 1 μs after the secondary
side becomes active.
Because the rate of charge of the secondary side power supply is
dependent on loading conditions, the input voltage, and the output
voltage level selected, take care that the design allows the con-
verter sufficient time to stabilize before valid data is required.
When power is removed from VDD1, the primary side converter
and coupler shut down when the UVLO level is reached. The
secondary side stops receiving power and starts to discharge.
The outputs on the secondary side hold the last state that they
received from the primary side. Either the UVLO level is reached
and the outputs are placed in their high impedance state, or the
outputs detect a lack of activity from the primary side inputs
and the outputs are set to their default low value before the
secondary power reaches UVLO.
Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Rev. A | Page 25 of 28
THERMAL ANALYSIS Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the bipolar ac condition
determines the maximum working voltage recommended by
Analog Devices.
The ADuM640x devices consist of four internal silicon die
attached to a split lead frame with two die attach paddles. For
the purposes of thermal analysis, the device is treated as a thermal
unit with the highest junction temperature reflected in the θJA
value from Table 14. The value of θJA is based on measurements
taken with the part mounted on a JEDEC standard 4-layer board
with fine width traces and still air. Under normal operating
conditions, the ADuM640x operates at full load across the full
temperature range without derating the output current. How-
ever, following the recommendations in the PCB Layout section
decreases the thermal resistance to the PCB, allowing increased
thermal margin at high ambient temperatures.
In the case of unipolar ac or dc voltage, the stress on the insu-
lation is significantly lower. This allows operation at higher
working voltages while still achieving a 50-year service life.
The working voltages listed in Table 20 can be applied while
maintaining the 50-year minimum lifetime, provided that the
voltage conforms to either the unipolar ac or dc voltage cases.
Any cross-insulation voltage waveform that does not conform
to Figure 33 or Figure 34 should be treated as a bipolar ac wave-
form and its peak voltage limited to the 50-year lifetime voltage
value listed in Table 20. The voltage presented in Figure 33 is
shown as sinusoidal for illustration purposes only. It is meant to
represent any voltage waveform varying between 0 V and some
limiting value. The limiting value can be positive or negative,
but the voltage cannot cross 0 V.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insu-
lation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog Devices
carries out an extensive set of evaluations to determine the life-
time of the insulation structure within the ADuM640x devices.
0V
R
A
TED PE
A
K
V
OLTAGE
08141-030
Figure 32. Bipolar AC Waveform
0V
R
A
TED PE
A
K
V
OLTAGE
08141-032
Figure 33. Unipolar AC Waveform
0V
R
A
TED PE
A
K
V
OLTAGE
08141-031
Figure 34. DC Waveform
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Accel-
eration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage. The values shown in Table 20 summarize the
peak voltage for 50 years of service life for a bipolar ac operating
condition and the maximum CSA/VDE approved working vol-
tages. In many cases, the approved working voltage is higher than
the 50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
The insulation lifetime of the ADuM640x devices depends on
the voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 32, Figure 33, and Figure 34 illustrate these
different isolation voltage waveforms.
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404 Data Sheet
Rev. A | Page 26 of 28
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
C
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 35. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AC
10-12-2010-A
13.00 (0.5118)
12.60 (0.4961)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
8°
0°
16 9
8
1
1.27
(0.0500)
BSC
SEATING
PLANE
Figure 36. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-16-1)
Dimensions shown in millimeters and (inches)
Data Sheet ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404
Rev. A | Page 27 of 28
ORDERING GUIDE
Model1, 2
Number
of Inputs,
VDD1 Side
Number
of Inputs,
VISO Side
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay, 5 V (ns)
Maximum
Pulse Width
Distortion (ns)
Temperature
Range
Package
Description
Package
Option
ADuM6400ARWZ 4 0 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6400CRWZ 4 0 25 60 6 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6401ARWZ 3 1 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6401CRWZ 3 1 25 60 6 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6402ARWZ 2 2 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6402CRWZ 2 2 25 60 6 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6403ARWZ 1 3 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6403CRWZ 1 3 25 60 6 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6404ARWZ 0 4 1 100 40 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6404CRWZ 0 4 25 60 6 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM6400ARIZ 4 0 1 100 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM6400CRIZ 4 0 25 60 6 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM6401ARIZ 3 1 1 100 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM6401CRIZ 3 1 25 60 6 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM6402ARIZ 2 2 1 100 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM6402CRIZ 2 2 25 60 6 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM6403ARIZ 1 3 1 100 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM6403CRIZ 1 3 25 60 6 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM6404ARIZ 0 4 1 100 40 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM6404CRIZ 0 4 25 60 6 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
1 Z = RoHS Compliant Part.
2 Tape and reel are available. The additional -RL suffix designates a 13-inch (1,000 units) tape and reel option.
