AS7C1024-10TPC - Alliance Semiconductor

ALLIANCE SEMICONDUCTOR

High Performance

128K×8

CMOS SRAM

AS7C1024

AS7C1024L

128K×8 CMOS SRAM

Features

• Organization: 131,072 words × 8 bits

• High speed

- 10/12/15/20/25/35 ns address access time

- 3/3/4/5/6/8 ns output enable access time

• Low power consumption

- Active: 770 mW max (10 ns cycle)

- Standby:55 mW max, CMOS I/O

11 mW max, CMOS I/O, L version

- Very low DC component in active power

• 2.0V data retention (L version)

• Equal access and cycle times

• Easy memory expansion with CE1, CE2, OE inputs

• TTL-compatible, three-state I/O

• 32-pin JEDEC standard packages

- 300 mil PDIP and SOJ

Socket compatible with 7C256 and 7C512

- 400 mil PDIP and SOJ

-8

× 20 TSOP

• ESD protection >2000 volts

• Latch-up current > 200 mA

Logic block diagram

512×256×8

Array

(1,048,576)

Sense amp

Input buffer

10 A

11 A

12 A

13 A

14 A

15 A

I/O0

I/O7

CE1

Column decoder

Row decoder

Control

circuit

Vcc

GND

CE2

Pin arrangement

Vcc

A15

CE2

A13

A11

A10

CE1

I/O7

I/O6

I/O5

I/O4

I/O3

A16

A14

A12

I/O0

I/O1

I/O2

GND

AS7C1024

DIP, S OJ

Vcc

A15

CE2

A13

A11 OE

A10

CE1

I/O7

I/O6

I/O5

A16

A14

A12

A4 A3

I/O0

I/O1

T SOP 8×20

I/O2

GND

I/O4

I/O3

AS7C1024

16 18

Selection guide

Shaded areas contain advance information.

7C1024-10 7C1024-12 7C1024-15 7C1024-20 7C1024-25 7C1024-35 Unit

Maximum address access time 10 12 15 20 25 35 ns

Maximum output enable access time 334568ns

Maximum operating current 140 130 120 110 100 90 mA

Maximum CMOS standby current 10.0 10.0 10.0 10.0 10.0 10.0 mA

L2.0 2.0 2.0 2.0 2.0 2.0 mA

AS7C1024

Functional description

The AS7C1024 is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) organized as 131,072 words × 8 bits. It

is designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20/25/35 ns with output enable access times (tOE) of 3/3/4/5/6/8 ns

are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-

bank memory systems.

When CE1 is HIGH or CE2 is LOW the device enters standby mode. The standard AS7C1024 is guaranteed not to exceed 55 mW power

consumption in standby mode; the L version is guaranteed not to exceed 11 mW, and typically requires only 5 mW. The L version also

offers 2.0V data retention.

A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written

on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external

devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) HIGH. The chip

drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is

active, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C1024 is packaged in common industry

standard packages.

Absolute maximum ratings

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-

imum rating conditions for extended periods may affect reliability.

Truth table

Key: X = Don’t Care, L = LOW, H = HIGH

Recommended operating conditions (Ta = 0°C to +70°C)

†VIL min = –3.0V for pulse width less than tRC/2.

Parameter Symbol Min Max Unit

Voltage on any pin relative to GND Vt–0.5 +7.0 V

Power dissipation PD–1.0W

Storage temperature (plastic) Tstg –55 +150 oC

Temperature under bias Tbias –10 +85 oC

DC output current Iout –20mA

CE1 CE2 WE OE Data Mode

H X X X High Z Standby (ISB, ISB1)

X L X X High Z Standby (ISB, ISB1)

L H H H High Z Output disable

LHHLD

out Read

LHLXD

in Write

Parameter Symbol Min Typ Max Unit

Supply voltage VCC 4.5 5.0 5.5 V

GND 0.0 0.0 0.0 V

Input voltage VIH 2.2 – VCC+1 V

VIL –0.5†–0.8V

AS7C1024

DC operating characteristics1(VCC = 5V±10%, GND = 0V, Ta = 0°C to +70°C)

Shaded areas contain advance information.

Capacitance2(f = 1 MHz, Ta = Room Temperature, VCC = 5V)

Read cycle3,9,12 (VCC = 5V±10%, GND = 0V, Ta = 0°C to +70°C)

Parameter Symbol Test Conditions

-10 -12 -15 -20 -25 -35

Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Input leakage

current | ILI | VCC = Max,

Vin = GND to VCC –1–1–1–1–1–1µA

Output leakage

current | ILO | CE1 = VIH or CE2 = VIL,

VCC = Max,

Vout = GND to VCC

–1–1–1–1–1–1µA

Operating power

supply current ICC CE1 = VIL, CE2 = VIH,

f = fmax, Iout = 0 mA

–140 – 130 – 120 – 110 – 100 – 90 mA

L– 135 – 125 – 115 – 105 – 95 – 75 mA

Standby

power supply

current

ISB CE1 = VIH or CE2 = VIL,

f = fmax

– 55 – 50 – 40 – 40 – 35 – 35 mA

L– 50 – 45 – 35 – 35 – 30 – 30 mA

ISB1

CE1 ≥ VCC–0.2V or CE2 ≤0.2V,

Vin ≤ 0.2V or Vin ≥ VCC–0.2V,

f = 0

–10 – 10 – 10 – 10 – 10 – 10 mA

L– 2.0 – 2.0 – 2.0 – 2.0 – 2.0 – 2.0 mA

Output voltage VOL IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 – 0.4 – 0.4 – 0.4 V

VOH IOH = –4 mA, VCC = Min 2.4 – 2.4 –2.4–2.4–2.4–2.4– V

Parameter Symbol Signals Test Conditions Max Unit

Input capacitance CIN A, CE1, CE2, WE, OE Vin = 0V 5 pF

I/O capacitance CI/O I/O Vin = Vout = 0V 7 pF

Parameter Symbol

-10 -12 -15 -20 -25 -35

Unit Notes

Min Max Min Max Min Max Min Max Min Max Min Max

Read cycle time tRC 10 – 12 –15–20–25–35– ns

Address access time tAA –10 – 12 – 15 – 20 – 25 – 35 ns 3

Chip enable (CE1) access time tACE1 –10 – 12 – 15 – 20 – 25 – 35 ns 3, 12

Chip enable (CE2) access time tACE2 –10 – 12 – 15 – 20 – 25 – 35 ns 3, 12

Output enable (OE) access time tOE –3–3–4–5–6–8 ns

Output hold from address change tOH 2–3–3–3–3–3– ns 5

CE1 LOW to output in Low Z tCLZ1 3–3–3–3–3–3– ns4, 5, 12

CE2 HIGH to output in Low Z tCLZ2 3–3–3–3–3–3– ns4, 5, 12

CE1 HIGH to output in High Z tCHZ1 –3–3–4–5–6–8 ns4, 5, 12

CE2 LOW to output in High Z tCHZ2 –3–3–4–5–6–8 ns4, 5, 12

OE LOW to output in Low Z tOLZ 0–0–0–0–0–0– ns 4, 5

OE HIGH to output in High Z tOHZ –3–3–4–5–6–8 ns 4, 5

Power up time tPU 0–0–0–0–0–0– ns4, 5, 12

Power down time tPD – 10 – 12 – 15 – 20 – 25 – 35 ns 4, 5, 12

AS7C1024

Key to switching waveforms

Read waveform 13,6,7,9,12 Address controlled

Read waveform 23,6,8,9,12 CE1 and CE2 controlled

Write cycle11, 12 (VCC = 5V±10%, GND = 0V, Ta = 0°C to +70°C)

Shaded areas contain advance information.

Parameter Symbol

-10 -12 -15 -20 -25 -35

Unit Notes

Min Max Min Max Min Max Min Max Min Max Min Max

Write cycle time tWC 10 – 12 –15–20–20–30– ns

Chip enable (CE1) to write end tCW1 9 – 10 –12–12–15–20– ns 12

Chip enable (CE2) to write end tCW2 9 – 10 –12–12–15–20– ns 12

Address setup to write end tAW 9 – 10 –12–12–15–20– ns

Address setup time tAS 0 – 0 –0–0–0–0– ns 12

Write pulse width tWP 7 – 8 – 9 –12–15–17– ns

Address hold from end of write tAH 0 – 0 –0–0–0–0– ns

Data valid to write end tDW 6 – 6 – 9 –10–10–12– ns

Data hold time tDH 0 – 0 –0–0–0–0– ns 4, 5

Write enable to output in High Z tWZ –5–5–5–5–5–5 ns 4, 5

Output active from write end tOW 3 – 3 –3–3–3–3– ns 4, 5

AAA

AAAA

AAA

Undefined output/don’t care

AAA

AAAA

AAA

Falling input

AAA

AAAA

AAA

Rising input

AAAA

Address

Dout Data Valid

tOH

tAA

tRC

AAAA

supply

Current

CE2

Dout

tOE

tOLZ

tACE1, tACE2 tCHZ1, tCHZ2

tCLZ1, tCLZ2

tPU

tPD ICC

ISB

50% 50%

tOHZ

AAAA

AAA

Data Valid

AAAA

tRC1

CE1

AS7C1024

Write waveform 110,11,12 WE controlled

Write waveform 210,11,12 CE1 and CE2 controlled

Data retention characteristics L version only

Data retention waveform L version only

Parameter Symbol Test Conditions Min Max Unit

VCC for data retention VDR VCC = 2.0V

CE1 ≥ VCC–0.2V or

CE2 ≤ 0.2V

Vin ≥ VCC–0.2V or

Vin ≤ 0.2V

2.0 – V

Data retention current ICCDR –500µA

Chip deselect to data retention time tCDR 0–ns

Operation recovery time tRtRC –ns

Input leakage current | ILI | –1µA

AW tAH

tWC

AAAA

Address

Dout

tDH

tOW

tDW

tWZ

tWP

tAS

Dat a Vali d

Din

tAW

AAAA

AAA

Address

CE1

Dout

tCW1, tCW2

tWP

tDW tDH

tAH

tWZ

tWC

AAAA

AAA

tAS

CE2

Dat a Vali dDin

AAAA

AAA

VCC

tCDR

Data retention mode

4.5V 4.5V

VDR ≥ 2.0V

VIH VIH

VDR

AS7C1024

AC test conditions

Notes

1 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.

2 This parameter is sampled and not 100% tested.

3 For test conditions, see AC Test Conditions, Figures A, B, C.

CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.

5 This parameter is guaranteed but not tested.

6WE

is HIGH for read cycle.

7 CE1 and OE are LOW and CE2 is HIGH for read cycle.

8 Address valid prior to or coincident with CE transition LOW.

9 All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE1 or WE must be HIGH or CE2 LOW during address transitions.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 CE1 and CE2 have identical timing.

255Ω

– Output load: see Figure B,

except for tCLZ and tCHZ see Figure C.

– Input pulse level: GND to 3.0V. See Figure A.

– Input rise and fall times: 5 ns. See Figure A.

– Input and output timing reference levels: 1.5V.

5 pF*

480Ω

Dout

GND

+5V

168Ω

Thevenin E q uivalent:

Dout +1.728V

Figure C: Output load for tCLZ, tCHZ

255Ω30 pF*

480Ω

Dout

GND

+5V

Figure B: Output load

*including sco pe

10%

90%

10%

90%

GND

+3.0V

Figure A: Input waveform

and jig capacitance

AS7C1024

Typical DC and AC characteristics

Supply voltage (V)

4.0 5.5 6.0

5.04.5

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized ICC, ISB

Normalized supply current ICC, ISB

Am bi ent temper at ure (°C)

–55 80 125

35–10

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized ICC, ISB

Normalized supply curr ent ICC, ISB

vs. ambient temperature Ta

vs. supply voltage VCC

ICC

ISB

ICC

ISB

Ambient temperature (°C)

-55 80 125

35-10

0.2

0.04

625

Normalized ISB1 (log scale)

Normalize d supply curre nt ISB1

vs. ambient te mper atur e Ta

VCC = 5. 0V

Supply voltage (V)

4.0 5.5 6.0

5.04.5

0.8

0.9

1.1

1.2

1.0

1.3

1.4

1.5

Nor malized acces s time

Normalized acc ess time tAA

Ambient te mper ature (°C)

–55 80 125

35–10

0.8

0.9

1.1

1.2

1.0

1.3

1.4

1.5

Nor malized acces s time

Normaliz e d acc es s time tAA

Cycle frequency (MHz)

075

100

5025

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Nor malized ICC

Normalize d supply curre nt ICC

vs. ambient te mper atur e Tavs. cycle frequency 1/tRC, 1/tWC

vs. supply voltage VCC

VCC = 5.0V

Ta = 25°C

VCC = 5.0VTa = 25°C

Output voltage (V)

0.0 3.75 5.0

2.51.25

100

120

140

Output source current (mA)

Output source current IOH

Output voltage (V)

0.0 3.75 5.0

2.51.25

Out put sink current (mA)

Output sink current IOL

vs. output vol tage VOL

vs. output voltage VOH

100

120

140

VCC = 5.0V

Ta = 25°C VCC = 5.0V

Ta = 25°C

Capacitance (pF)

0750

1000

500250

Change in tAA (ns)

Typical access time change ∆tAA

vs. output capacitive loading

VCC = 4.5V

AS7C1024

AS7C1024L

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3099 North First Street San Jose, CA 95134 Tel (408) 383-4900 Fax (408) 383-4999 www.alsc.com

Alliance Semiconductor reserves the right to make changes in this data sheet at any time to improve design and supply the best product possible. Publication of advance information does not constitute a

committment to produce or supply the product described. The company cannot assume responsibility for circuits shown or represent that they are free from patent infringement. Alliance products are not

authorized for use as critical components in life support devices or systems without the express written approval of the president of Alliance. ProMotion® and the Alliance logo are registered trademarks

of Alliance Semiconductor Corporation. All other trademarks are property of their respective holders.

Ordering codes

Shaded areas contain advance information.

Part numbering system

Representatives, distributors, and sales offices

Package \ Access Time 10 ns 12 ns 15 ns 20 ns 25 ns 35 ns

Plastic DIP, 300 mil AS7C1024-10TPC

AS7C1024L-10TPC

AS7C1024-12TPC

AS7C1024L-12TPC

AS7C1024-15TPC

AS7C1024L-15TPC

AS7C1024-20TPC

AS7C1024L-20TPC

AS7C1024-25TPC

AS7C1024L-25TPC

AS7C1024-35TPC

AS7C1024L-35TPC

Plastic DIP, 400 mil AS7C1024-10PC

AS7C1024L-10PC

AS7C1024-12PC

AS7C1024L-12PC

AS7C1024-15PC

AS7C1024L-15PC

AS7C1024-20PC

AS7C1024L-20PC

AS7C1024-25PC

AS7C1024L-25PC

AS7C1024-35PC

AS7C1024L-35PC

Plastic SOJ, 300 mil AS7C1024-10TJC

AS7C1024L-10TJC

AS7C1024-12TJC

AS7C1024L-12TJC

AS7C1024-15TJC

AS7C1024L-15TJC

AS7C1024-20TJC

AS7C1024L-20TJC

AS7C1024-25TJC

AS7C1024L-25TJC

AS7C1024-35TJC

AS7C1024L-35TJC

Plastic SOJ, 400 mil AS7C1024-10JC

AS7C1024L-10JC

AS7C1024-12JC

AS7C1024L-12JC

AS7C1024-15JC

AS7C1024L-15JC

AS7C1024-20JC

AS7C1024L-20JC

AS7C1024-25JC

AS7C1024L-25JC

AS7C1024-35JC

AS7C1024L-35JC

TSOP 8×20 AS7C1024-10TC

AS7C1024L-10TC

AS7C1024-12TC

AS7C1024L-12TC

AS7C1024-15TC

AS7C1024L-15TC

AS7C1024-20TC

AS7C1024L-20TC

AS7C1024-25TC

AS7C1024L-25TC

AS7C1024-35TC

AS7C1024L-35TC

AS7C 1024 X –XX X C

SRAM Prefix Device Number Blank = Standard Power

L = Low Power

Access Time Package: TP = PDIP 300 mil P = PDIP 400 mil

TJ = SOJ 300 mil J = SOJ 400 mil

T = TSOP 8¥20

Commercial Temperature Range,

0°C to 70 °C