Femtoampere Input Bias Current
Electrometer Amplifier
Data Sheet
ADA4530-1
Rev. B Document Feedback
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FEATURES
Low input bias current
±20 fA maximum at TA = 25°C (guaranteed at production test)
±20 fA maximum at −40°C < TA < +85°C
±250 fA maximum at −40°C < TA < +125°C (guaranteed at
production test)
Low offset voltage: 50 µV maximum over specified CMRR range
Offset voltage drift: ±0.13 µV/°C typical, ±0.5 µV/°C maximum
Integrated guard buffer with 100 µV maximum offset
Low voltage noise density: 14 nV/√Hz at 10 kHz
Wide bandwidth: 2 MHz unity-gain crossover
Supply voltage: 4.5 V to 16 V (±2.25 V to ±8 V)
Operating temperature: −40°C to +125°C
Long-term offset voltage drift (10,000 hours): 0.5 µV typical
Temperature hysteresis: 1.5 µV typical
APPLICATIONS
Laboratory and analytical instrumentation: spectrophoto-
meters, chromatographs, mass spectrometers, and
potentiostatic and amperostatic coulometry
Instrumentation: picoammeters and coulombmeters
Transimpedance amplifier (TIA) for photodiodes, ion
chambers, and working electrode measurements
High impedance buffering for chemical sensors and
capacitive sensors
PIN CONNECTION DIAGRAM
+IN
1
GRD
2
IC
3
V–
4
–IN
8
GRD
7
OUT
6
V+
5
ADA4530-1
13405-001
NOTES
1. IC = INT E RNAL CO NNE CTI ON. THI S
PIN M US T BE CONNECTED TO V –
OR L E FT UNCONNECTED.
Figure 1.
GENERAL DESCRIPTION
The ADA4530-1 is a femtoampere (10−15 A) level input bias
current operational amplifier suitable for use as an electrometer
that also includes an integrated guard buffer. It has an operating
voltage range of 4.5 V to 16 V, enabling it to operate in conven-
tional 5 V and 10 V single supply systems as well as ±2.5 V and
±5 V dual supply systems.
It provides ultralow input bias currents that are production
tested at 25°C and at 125°C to ensure the device meets its perfor-
mance goals in user systems. The integrated guard buffer
isolates the input pins from leakage in the printed circuit board
(PCB), minimizes board component count, and enables easy
system design. The ADA4530-1 is available in an industry-
standard surface-mount 8-lead SOIC package with a unique
pinout optimized to prevent signals from coupling between the
sensitive input pins, the power supplies, and the output pin
while enabling easy routing of the guard ring traces.
The ADA4530-1 also offers low offset voltage, low offset drift,
and low voltage and current noise needed for the types of
applications that require such low leakages.
To maximize the dynamic range of the system, the ADA4530-1
has a rail-to-rail output stage that can typically drive to within
30 mV of the supply rails under a 10 kΩ load.
The ADA4530-1 operates over the −40°C to +125°C industrial
temperature range and is available in an 8-lead SOIC package.
13405-202
1000
0.001
0.01
0.1
1
10
100
010 3020 40 50 60 70 80 90 100 110 120 130
I
B
(fA)
TEMPERATURE (°C)
V
SY
= 10V
V
CM
= V
SY
/2
RH < 10%
–40°C TO + 85°C L IMIT
–40°C TO + 125°C L IMIT
I
B
+
I
B
–
Figure 2. Input Bias Current (IB) vs. Temperature, VSY = 10 V
ADA4530-1 Data Sheet
Rev. B | Page 2 of 52
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Connection Diagram ................................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
5 V Nominal Electrical Characteristics ..................................... 4
10 V Nominal Electrical Characteristics ................................... 6
15 V Nominal Electrical Characteristics ................................... 8
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 12
Main Amplifier, DC Performance ............................................ 12
Main Amplifier, AC Performance ............................................ 21
Guard Amplifier ......................................................................... 27
Theory of Operation ...................................................................... 29
ESD Structure .............................................................................. 29
Input Stage ................................................................................... 29
Gain Stage .................................................................................... 30
Output Stage ................................................................................ 30
Guard Buffer ............................................................................... 30
Applications Information .............................................................. 31
Input Protection .......................................................................... 31
Single-Supply and Rail-to-Rail Output ................................... 31
Capacitive Load Stability ........................................................... 31
EMI Rejection Ratio ................................................................... 32
High Impedance Measurements ................................................... 33
Input Bias Current ...................................................................... 33
Input Resistance.......................................................................... 34
Input Offset Voltage ................................................................... 34
Insulation Resistance ................................................................. 34
Guarding ...................................................................................... 35
Dielectric Relaxation .................................................................. 35
Humidity Effects ......................................................................... 37
Contamination ............................................................................ 38
Cleaning and Handling ............................................................. 39
Solder Paste Selection ................................................................ 39
Current Noise Considerations ...................................................... 40
Layout Guidelines ........................................................................... 43
Physical Implementation of Guarding Techniques................ 43
Guard Ring .................................................................................. 43
Guard Plane ................................................................................. 43
Via Fence ..................................................................................... 44
Cables and Connectors .............................................................. 44
Electrostatic Interferance .......................................................... 44
Photodiode Interface ...................................................................... 45
DC Error Analysis ...................................................................... 45
AC Error Analysis ...................................................................... 45
Noise Analysis ............................................................................. 46
Design Recommendations ........................................................ 47
Design Example .......................................................................... 47
Power Supply Recommendations ................................................. 50
Power Supply Considerations ................................................... 50
Long-Term Drift ......................................................................... 51
Temperature Hysteresis ............................................................. 51
Outline Dimensions ....................................................................... 52
Ordering Guide .......................................................................... 52
Data Sheet ADA4530-1
Rev. B | Page 3 of 52
REVISION HISTORY
5/2017—Rev. A to Rev. B
Changes to Features Section and General Description Section ....... 1
Changed Offset Voltage Parameter to Input Offset Voltage
Parameter, Table 1 ............................................................................. 4
Changed Offset Voltage Parameter to Input Offset Voltage
Parameter, Table 2 ............................................................................. 6
Changed Offset Voltage Parameter to Input Offset Voltage
Parameter, Table 3 ............................................................................. 8
Changes to EMI Rejection Ratio Section and Figure 102 .......... 32
Moved Figure 114 ............................................................................ 38
Changes to Current Noise Considerations Section .................... 41
Added Long-Term Drift Section, Temperature Hysteresis
Section, Figure 136, Figure 137, and Figure 138; Renumbered
Sequentially ...................................................................................... 51
Changes to Ordering Guide ........................................................... 52
3/2016—Rev. 0 to Rev. A
Changed DNC Pin to IC Pin ........................................ Throughout
Changes to Figure 1 .......................................................................... 1
Changes to Figure 3 and Table 6 ................................................... 10
Changes to Figure 29 ...................................................................... 15
Changes to Theory of Operation Section .................................... 28
Changes to Humidity Effects Section and Figure 112................ 36
Added Power Supply Recommendations Section, Power
Supply Considerations Section, Table 16, and Figure 133 to
Figure 135 ......................................................................................... 49
10/2015—Revision 0: Initial Version
ADA4530-1 Data Sheet
Rev. B | Page 4 of 52
SPECIFICATIONS
5 V NOMINAL ELECTRICAL CHARACTERISTICS
Supply voltage (VSY) = 4.5 V, common-mode voltage (VCM) = VSY/2, TA = 25°C, unless otherwise specified. Typical specifications are equal
to the average of the distribution from characterization, unless otherwise noted. Minimum and maximum specifications are tested in
production, unless otherwise noted.
Table 1.
Parameter
1
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Input Bias Current
2, 3
I
B
RH < 50%
<1
±20
fA
−40°C < TA < +85°C, RH < 50% ±20 fA
−40°C < TA < +125°C, RH < 50% ±250 fA
Input Offset Current3 IOS RH < 50% <1 ±20 fA
−40°C < TA < +125°C, RH < 50% ±150 fA
Input Offset Voltage2, 4 VOS +8 ±40 µV
VCM = 1.5 V to 3 V +9 ±50 µV
VCM = 1.5 V to 3 V, 0°C < TA < 125°C ±70 µV
VCM = 1.5 V to 3 V, −40°C < TA < 0°C
±150 µV
VCM = 0 V to 3 V
±300 µV
Offset Voltage Drift2, 4 ΔVOS/ΔT 0°C < TA < 125°C +0.13 ±0.5 µV/°C
−40°C < TA < 0°C −0.7 ±2.8 µV/°C
Input Voltage Range IVR 0 3 V
Common-Mode Rejection Ratio CMRR VCM = 1.5 V to 3 V 92 114 dB
−40°C < TA < +125°C 90 dB
VCM = 0 V to 3 V 73 dB
Large Signal Voltage Gain
A
VO
R
L
= 2 kΩ to V
CM
, V
OUT
= 0.2 V to 4.3 V
120
143
dB
−40°C < T
A
< +125°C
120
dB
Input Resistance RIN −40°C < TA < +125°C >100 TΩ
Input Capacitance CIN 8 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 4.47 4.49 V
−40°C < TA < +125°C 4.46 V
RL = 2 kΩ to VCM 4.4 4.45 V
−40°C < TA < +125°C 4.38 V
Output Voltage Low VOL RL = 10 kΩ to VCM 10 30 mV
−40°C < TA < +125°C 40 mV
RL = 2 kΩ to VCM 30 100 mV
−40°C < TA < +125°C 120 mV
Short-Circuit Current ISC
Source
15
mA
Sink
−30
mA
Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = 1 20 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 4.5 V to 16 V 130 150 dB
−40°C < TA < +125°C 130 dB
Supply Current ISY IOUT = 0 mA 0.9 1.3 mA
−40°C < TA < +125°C 1.5 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ, CL = 10 pF, AV = 1 1.4 V/µs
Gain Bandwidth Product GBP VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AV = 100
2 MHz
Unity-Gain Crossover UGC VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AVO = 1
2 MHz
Data Sheet ADA4530-1
Rev. B | Page 5 of 52
Parameter1 Symbol Test Conditions/Comments Min Typ Max Unit
−3 dB Closed-Loop Bandwidth f−3dB VIN=10 mV rms, RL = 10 kΩ, CL = 10 pF,
AV = 1
6 MHz
Phase Margin ΦM VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AVO = 1
62 Degrees
Settling Time to 0.1%
t
S
V
IN
= 0.5 V step, R
L
= 10 kΩ, C
L
= 10 pF,
AV = −1
5
µs
EMI Rejection Ratio of +IN EMIRR VIN = 100 mV peak, f = 400 MHz 50 dB
VIN = 100 mV peak, f = 900 MHz 60 dB
VIN = 100 mV peak, f = 1800 MHz 80 dB
VIN = 100 mV peak, f = 2400 MHz 90 dB
NOISE PERFORMANCE
Peak-to-Peak Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 4 µV p-p
Voltage Noise Density eN f = 10 Hz 80 nV/√Hz
f = 1 kHz
16
nV/√Hz
f = 10 kHz 14 nV/√Hz
Current Noise Density IN f = 0.1 Hz 0.07 fA/√Hz
Total Harmonic Distortion + Noise THD + N AV = 1, f = 1 kHz, VIN = 0.5 V rms
Bandwidth = 90 kHz 0.003 %
Bandwidth = 500 kHz
0.0045
%
GUARD BUFFER
Guard Offset Voltage2, 4, 5 VGOS VCM = 1.5 V to 3 V 15 100 µV
VCM = 1.5 V to 3 V, 0°C < TA < 125°C 120 µV
VCM = 1.5 V to 3 V, −40°C < TA < 0°C
250 µV
VCM = 0.1 V to 3 V
150 µV
Guard Offset Voltage Drift2, 4 ΔVGOS/ΔT 0°C < TA < +125°C 0.18 1 µV/°C
−40°C < TA < 0°C 1.4 7 µV/°C
Output Impedance ZGOUT 1 kΩ
Output Voltage Range VGOS < 150 µV 0.1 3 V
−3 dB Bandwidth f−3dBGUARD VIN = 10 mV rms, CL = 10 pF 5.5 MHz
1 These specifications represent the performance for 5 V ± 10% power supplies. All specifications are measured at the worst case 4.5 V supply voltage.
2 The maximum specifications at −40°C < TA < +85°C and −40°C < TA < 0°C are guaranteed from characterization.
3 RH is relative humidity (see the Humidity Effects section for more information).
4 The typical specifications are equal to the average plus the standard deviation of the distribution from characterization.
5 The guard offset voltage is the voltage difference between the guard output and the noninverting input.
ADA4530-1 Data Sheet
Rev. B | Page 6 of 52
10 V NOMINAL ELECTRICAL CHARACTERISTICS
VSY = 10 V, VCM = VSY/2, TA = 25°C, unless otherwise noted. Typical specifications are equal to the average of the distribution from
characterization, unless otherwise noted. Minimum and maximum specifications are tested in production, unless otherwise noted.
Table 2.
Parameter1 Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Input Bias Current2, 3 IB RH < 50% <1 ±20 fA
−40°C < TA < +85°C, RH < 50% ±20 fA
−40°C < TA < +125°C, RH < 50% ±250 fA
Input Offset Current
3
I
OS
RH < 50%
<1
±20
fA
−40°C < TA < +125°C, RH < 50% ±150 fA
Input Offset Voltage2, 4 VOS +8 ±40 µV
VCM = 1.5 V to 8.5 V +9 ±50 µV
VCM = 1.5 V to 8.5 V, 0°C < TA < 125°C ±70 µV
VCM = 1.5 V to 8.5 V, −40°C < TA < 0°C
±150 µV
VCM = 0 V to 8.5 V
±300 µV
Offset Voltage Drift2, 4 ΔVOS/ΔT 0°C < TA < 125°C +0.13 ±0.5 µV/°C
−40°C < TA < 0°C −0.7 ±2.8 µV/°C
Input Voltage Range IVR 0 8.5 V
Common-Mode Rejection Ratio CMRR VCM = 1.5 V to 8.5 V 105 114 dB
−40°C < TA < +125°C 100 dB
VCM = 0 V to 8.5 V 87 dB
Large Signal Voltage Gain AVO RL = 2 kΩ to VCM, VOUT = 0.5 V to 9.5 V 125 150 dB
−40°C < TA < +125°C 125 dB
Input Resistance RIN −40°C < TA < +125°C >100 TΩ
Input Capacitance
C
IN
8
pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 9.96 9.97 V
−40°C < TA < +125°C 9.94 V
RL = 2 kΩ to VCM 9.93 9.87 V
−40°C < TA < +125°C 9.75 V
Output Voltage Low VOL RL = 10 kΩ to VCM 15 40 mV
−40°C < TA < +125°C 60 mV
RL = 2 kΩ to VCM 70 170 mV
−40°C < TA < +125°C 250 mV
Short-Circuit Current ISC
Source 15 mA
Sink −30 mA
Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = 1 20 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 4.5 V to 16 V 130 150 dB
−40°C < TA < +125°C 130 dB
Supply Current ISY IOUT = 0 mA 0.9 1.3 mA
−40°C < TA < +125°C 1.5 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ, CL = 10 pF, AV = 1 1.4 V/µs
Gain Bandwidth Product GBP VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AV = 100
2 MHz
Unity-Gain Crossover UGC VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AVO = 1
2 MHz
−3 dB Closed-Loop Bandwidth f−3dB VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AV = 1
6 MHz
Phase Margin ΦM VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AVO = 1
62 Degrees
Data Sheet ADA4530-1
Rev. B | Page 7 of 52
Parameter1 Symbol Test Conditions/Comments Min Typ Max Unit
Settling Time to 0.1% tS VIN = 1 V step, RL = 10 kΩ, CL = 10 pF,
AV = −1
6 µs
EMI Rejection Ratio of +IN EMIRR VIN = 100 mV peak, f = 400 MHz 50 dB
VIN = 100 mV peak, f = 900 MHz 60 dB
VIN = 100 mV peak, f = 1800 MHz 80 dB
VIN = 100 mV peak, f = 2400 MHz 90 dB
NOISE PERFORMANCE
Peak-to-Peak Voltage Noise
e
N
p-p
f = 0.1 Hz to 10 Hz
4
µV p-p
Voltage Noise Density eN f = 10 Hz 80 nV/√Hz
f = 1 kHz 16 nV/√Hz
f = 10 kHz 14 nV/√Hz
Current Noise Density IN f = 0.1 Hz 0.07 fA/√Hz
Total Harmonic Distortion + Noise THD + N AV = 1, f = 1 kHz, VIN = 2 V rms
Bandwidth = 90 kHz 0.0015 %
Bandwidth = 500 kHz 0.0025 %
GUARD BUFFER
Guard Offset Voltage2, 4, 5 VGOS VCM = 1.5 V to 8.5 V 15 100 µV
VCM = 1.5 V to 8.5 V, 0°C < TA < 125°C 120 µV
VCM = 1.5 V to 8.5 V, −40°C < TA < 0°C
250 µV
VCM = 0.1 V to 8.5 V
150 µV
Guard Offset Voltage Drift2, 4 ΔVGOS/ΔT 0°C < TA < 125°C 0.18 1 µV/°C
−40°C < T
A
< 0°C
1.4
7
µV/°C
Output Impedance ZGOUT 1 kΩ
Output Voltage Range VGOS < 150 µV 0.1 8.5 V
−3 dB Bandwidth f−3dBGUARD VIN = 10 mV rms, CL = 10 pF 5.5 MHz
1 These specifications represent the performance for 10 V ± 10% power supplies. All specifications are measured at the 10 V supply voltage.
2 The maximum specifications at −40°C < TA < +85°C and −40°C < TA < 0°C are guaranteed from characterization.
3 RH is relative humidity (see the Humidity Effects section for more information).
4 These typical specifications are equal to the average plus the standard deviation of the distribution from characterization.
5 The guard offset voltage is the voltage difference between the guard output and the noninverting input.
ADA4530-1 Data Sheet
Rev. B | Page 8 of 52
15 V NOMINAL ELECTRICAL CHARACTERISTICS
VSY = 16 V, VCM = VSY/2, TA = 25°C, unless otherwise noted. Typical specifications are equal to the average of the distribution from
characterization, unless otherwise noted. Minimum and maximum specifications are tested in production, unless otherwise noted.
Table 3.
Parameter1 Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Input Bias Current2, 3 IB RH < 50% <1 ±20 fA
−40°C < TA < +85°C, RH < 50% ±20 fA
−40°C < TA < +125°C, RH < 50% ±250 fA
Input Offset Current IOS RH < 50% <1 ±20 fA
−40°C < TA < +125°C, RH < 50% ±150 fA
Input Offset Voltage2, 4 VOS +8 ±40 µV
VCM = 1.5 V to 14.5 V +9 ±50 µV
VCM = 1.5 V to 14.5 V, 0°C < TA < 125°C ±70 µV
VCM = 1.5 V to 14.5 V, −40°C < TA < 0°C
±150 µV
V
CM
= 0 V to 14.5 V
±300
µV
Offset Voltage Drift2, 4 ΔVOS/ΔT 0°C < TA < 125°C +0.13 ±0.5 µV/°C
−40°C < TA < 0°C −0.7 ±2.8 µV/°C
Input Voltage Range IVR 0 14.5 V
Common-Mode Rejection Ratio CMRR VCM = 1.5 V to 14.5 V 110 114 dB
−40°C < TA < +125°C 105 dB
VCM = 0 V to 14.5 V 93 dB
Large Signal Voltage Gain AVO RL = 2 kΩ to VCM, VOUT = 0.5 V to 15.5 V 130 155 dB
−40°C < TA < +125°C 125 dB
Input Resistance RIN −40°C < TA < +125°C >100 TΩ
Input Capacitance CIN 8 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 10 kΩ to VCM 15.93 15.95 V
−40°C < TA < +125°C 15.9 V
R
L
= 2 kΩ to V
CM
15.72
15.78
V
−40°C < TA < +125°C 15.58 V
Output Voltage Low VOL RL = 10 kΩ to VCM 25 70 mV
−40°C < TA < +125°C 100 mV
RL = 2 kΩ to VCM 115 280 mV
−40°C < TA < +125°C 420 mV
Short-Circuit Current ISC
Source 15 mA
Sink −30 mA
Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = 1 20 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 4.5 V to 16 V 130 150 dB
−40°C < TA < +125°C 130 dB
Supply Current ISY IOUT = 0 mA 0.9 1.3 mA
−40°C < T
A
< +125°C
1.5
mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ, CL = 10 pF, AV = 1 1.4 V/µs
Gain bandwidth Product GBP VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AV = 100
2 MHz
Unity-Gain Crossover UGC VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AVO = 1
2 MHz
−3 dB Closed-Loop Bandwidth f−3 dB VIN = 10 mV rms, RL = 10 kΩ, CL = 10 pF,
AV = 1
6 MHz
Phase Margin ΦM VIN =10 mV rms, RL = 10 kΩ, CL = 10 pF,
AVO = 1
62 Degrees
Data Sheet ADA4530-1
Rev. B | Page 9 of 52
Parameter1 Symbol Test Conditions/Comments Min Typ Max Unit
Settling Time to 0.1% tS VIN = 1 V step, RL = 10 kΩ, CL = 10 pF,
AV = −1
6 µs
EMI Rejection Ratio of +IN EMIRR VIN = 100 mV peak, f = 400 MHz 50 dB
VIN = 100 mV peak, f = 900 MHz 60 dB
VIN = 100 mV peak, f = 1800 MHz 80 dB
VIN = 100 mV peak, f = 2400 MHz 90 dB
NOISE PERFORMANCE
Peak-to-Peak Voltage Noise
e
N
p-p
f = 0.1 Hz to 10 Hz
4
µV p-p
Voltage Noise Density eN f = 10 Hz 80 nV/√Hz
eN f = 1 kHz 16 nV/√Hz
eN f = 10 kHz 14 nV/√Hz
Current Noise Density IN f = 0.1 Hz 0.07 fA/√Hz
Total Harmonic Distortion + Noise THD + N AV = 1, f = 1 kHz, VIN = 4.5 V rms
Bandwidth = 90 kHz 0.0012 %
Bandwidth = 500 kHz 0.003 %
GUARD BUFFER
Guard Offset Voltage4, 5 VGOS VCM = 1.5 V to 14.5 V 15 100 µV
VCM = 1.5 V to 14.5 V, 0°C < TA < 125°C 120 µV
VCM = 1.5 V to 14.5 V, −40°C < TA < 0°C
250 µV
VCM = 0.1 V to 14.5 V
150 µV
Guard Offset Voltage Drift2, 4 ΔVGOS/ΔT 0°C < TA < +125°C 0.18 1 µV/°C
−40°C < T
A
< 0°C
1.4
7
µV/°C
Output Impedance ZGOUT 1 kΩ
Output Voltage Range VGOS < 150 µV 0.1 14.5 V
−3 dB Bandwidth f−3 dB GUARD VIN = 10 mV rms, CL = 10 pF 5.5 MHz
1 These specifications represent the performance for 15 V ± 1 V power supplies. All specifications are measured at the worst case 16 V supply voltage.
2 The maximum specifications at −40°C < TA < +85°C and −40°C < TA < 0°C are guaranteed from characterization.
3 RH is relative humidity (see the Humidity Effects section for more information).
4 These typical specifications are equal to the average plus the standard deviation of the distribution from characterization.
5 The guard offset voltage is the voltage difference between the guard output and the noninverting input.
ADA4530-1 Data Sheet
Rev. B | Page 10 of 52
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 17 V
Input Voltage
(V−) − 0.3 V to (V+) + 0.3 V
Input Current1 10 mA
Differential Input Voltage ±0.7 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Electrostatic Discharge (ESD)
Human Body Model2 4 kV
Field Induced Charged Device
Model (FICDM)3
1.25 kV
1 The input pins have clamp diodes to the power supply pins. Limit the input
current to 10 mA or less whenever input signals exceed the power supply
rail by 0.3 V.
2 Applicable Standard ESDA/JEDEC JS-001-2012.
3 Applicable Standard JESD22-C101-E (ESD FICDM standard of JEDEC).
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages using a
standard 4-layer JEDEC board.
Table 5. Thermal Resistance
Package Type θJA θJC Unit
8-Lead SOIC 122 41 °C/W
ESD CAUTION
Data Sheet ADA4530-1
Rev. B | Page 11 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
+IN
1
GRD
2
IC
3
V–
4
–IN
8
GRD
7
OUT
6
V+
5
ADA4530-1
13405-003
NOTES
1. IC = INT E RNAL CO NNE CTI ON. THI S
PIN MUST BE CONNECTED TO V –
OR LEF T UNCO NNE CTED.
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 +IN Noninverting Input.
2 GRD Guard.
3 IC Internal Connection. This pin must be connected to V− or left unconnected.
4 V− Negative Supply Voltage.
5 V+ Positive Supply Voltage.
6 OUT Output.
7 GRD Guard.
8 −IN Inverting Input.
ADA4530-1 Data Sheet
Rev. B | Page 12 of 52
TYPICAL PERFORMANCE CHARACTERISTICS
MAIN AMPLIFIER, DC PERFORMANCE
TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
–40
–36
–32
–28
–24
–20
–16
–12
–8
–4
0
4
8
12
16
20
24
28
32
36
40
NUMBER O F AMP LI FI E RS
V
OS
(µV)
V
SY
= 4.5V
V
CM
= V
SY
/2
590 CHANNEL S
x = 2.31µV
σ = 5.48µV
13405-004
Figure 4. Input Offset Voltage Distribution, VSY = 4.5 V
100
90
80
70
60
50
40
30
20
10
0
–40
–36
–32
–28
–24
–20
–16
–12
–8
–4
0
4
8
12
16
20
24
28
32
36
40
NUMBER O F AMP LI FI E RS
V
OS
(µV)
V
SY
= 10V
V
CM
= V
SY
/2
590 CHANNEL S
x = 2.27µV
σ = 5.45µV
13405-005
Figure 5. Input Offset Voltage Distribution, VSY = 10 V
100
90
80
70
60
50
40
30
20
10
0
–40
–36
–32
–28
–24
–20
–16
–12
–8
–4
0
4
8
12
16
20
24
28
32
36
40
NUMBER O F AMP LI FI E RS
V
OS
(µV)
V
SY
= 16V
V
CM
= V
SY
/2
590 CHANNEL S
x = 2.15µV
σ = 5.47µV
13405-006
Figure 6. Input Offset Voltage Distribution, VSY = 16 V
80
60
40
20
0
–20
–40
–60
–50 –25 025 50 75 100 125
V
OS
(µV)
TEMPERATURE (°C)
VSY = 4.5V
VCM = VSY/2
574 CHANNELS
13405-007
Figure 7. Input Offset Voltage (VOS) vs. Temperature, VSY = 4.5 V
80
60
40
20
0
–20
–40
–60
–50 –25 025 50 75 100 125
V
OS
(µV)
TEMPERATURE (°C)
V
SY
= 10V
V
CM
= V
SY
/2
574 CHANNEL S
13405-008
Figure 8. Input Offset Voltage (VOS) vs. Temperature, VSY = 10 V
80
60
40
20
0
–20
–40
–60
–50 –25 025 50 75 100 125
V
OS
(µV)
TEMPERATURE (°C)
V
SY
= 16V
V
CM
= V
SY
/2
574 CHANNEL S
13405-009
Figure 9. Input Offset Voltage (VOS) vs. Temperature, VSY = 16 V
Data Sheet ADA4530-1
Rev. B | Page 13 of 52
TCVOS (µV/°C)
120
100
80
60
40
20
0
NUMBER O F AMP LI FI E RS
–2.8
–2.4
–2.0
–1.6
–1.2
–0.8
–0.4
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
V
SY
= 4.5V
V
CM
= V
SY
/2
574 CHANNEL S
–40°C ≤ T
A
≤ 0°C
x = –0.29µV/° C
σ = 0.42µV/°C
13405-013
Figure 10. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 4.5 V
TCV
OS
(µV/°C)
120
100
80
60
40
20
0
NUMBER O F AMP LI FI E RS
–2.8
–2.4
–2.0
–1.6
–1.2
–0.8
–0.4
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
V
SY
= 10V
V
CM
= V
SY
/2
574 CHANNEL S
–40°C ≤ T
A
≤ 0°C
x = –0.29µV/° C
σ = 0.42µV/°C
13405-014
Figure 11. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 10 V
TCV
OS
(µV/°C)
120
100
80
60
40
20
0
NUMBER O F AMP LI FI E RS
–2.8
–2.4
–2.0
–1.6
–1.2
–0.8
–0.4
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
V
SY
= 16V
V
CM
= V
SY
/2
574 CHANNEL S
–40°C ≤ T
A
≤ 0°C
x = –0.29µV/° C
σ = 0.41µV/°C
13405-015
Figure 12. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 16 V
120
100
80
60
40
20
0
–0.5 –0.4 –0.3 –0.2 –1.0 00.1 0.2 0.3 0.4 0.5
NUMBER O F AMP LI FI E RS
TCV
OS
(µV/°C)
V
SY
= 4.5V
V
CM
= V
SY
/2
574 CHANNEL S
0°C ≤ T
A
≤ 125°C
x = –0.025µV/° C
σ = 0.107µV/°C
13405-010
Figure 13. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 4.5 V
120
100
80
60
40
20
0
–0.5 –0.4 –0.3 –0.2 –1.0 00.1 0.2 0.3 0.4 0.5
NUMBER O F AMP LI FI E RS
TCV
OS
(µV/°C)
V
SY
= 10V
V
CM
= V
SY
/2
574 CHANNEL S
0°C ≤ T
A
≤ 125°C
x = –0.025µV/° C
σ = 0.107µV/°C
13405-011
Figure 14. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 10 V
120
100
80
60
40
20
0
–0.5 –0.4 –0.3 –0.2 –1.0 00.1 0.2 0.3 0.4 0.5
NUMBER O F AMP LI FI E RS
TCV
OS
(µV/°C)
V
SY
= 16V
V
CM
= V
SY
/2
574 CHANNEL S
0°C ≤ T
A
≤ 125°C
x = –0.024µV/° C
σ = 0.107µV/°C
13405-012
Figure 15. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 16 V
ADA4530-1 Data Sheet
Rev. B | Page 14 of 52
60
40
20
0
–20
–40
–60 00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
OS
(µV)
V
CM
(V)
V
SY
= 4.5V
590 CHANNEL S
T
A
= 25° C
PREFERRED
COMMON-MODE
RANGE
13405-016
Figure 16. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = 4.5 V
60
40
20
0
–20
–40
–60 0 1 2 3 4 5 6 7 8 9 10
V
OS
(µV)
V
CM
(V)
V
SY
= 10V
590 CHANNEL S
T
A
= 25° C
PREFERRED
COMMON-MODE
RANGE
13405-017
Figure 17. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
VSY = 10 V
60
40
20
0
–20
–40
–60 012345678910 11 12 13 14 1615
V
OS
(µV)
V
CM
(V)
V
SY
= 16V
590 CHANNEL S
T
A
= 25° C
PREFERRED
COMMON-MODE
RANGE
13405-018
Figure 18. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
VSY = 16 V
10
–10
–8
–6
–4
–2
0
2
4
6
8
045004000350030002500200015001000500
INPUT OFFSET VOLTAGE (µV)
TIME (Hours)
V
SY
= 10V
27 CHANNEL S
T
A
= 25° C
13405-219
Figure 19. VOS Long-Term Drift
2.5
0
0.5
1.0
1.5
2.0
0 54321
INPUT OFFSET VOLTAGE (µV)
TIME AFT ER POW ER-ON (Min u tes)
V
SY
= 10V
T
A
= 25° C
13405-220
Figure 20. VOS Warm-Up Time
0
–200
–180
–160
–140
–120
–100
–80
–60
–40
–20
010987654321
SMALL S IG NAL CMRR ( dB)
VCM (V)
VSY = 10V
ΔVCM = 400mV
PREF E RRE D COMM ON-M ODE RANGE
13405-221
Figure 21. Small Signal CMRR vs. Common-Mode Voltage (VCM)
Data Sheet ADA4530-1
Rev. B | Page 15 of 52
20
–20
–15
–10
–5
0
5
10
15
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
I
B–
(fA)
V
CM
(V)
V
SY
= 4.5V
27 CHANNEL S
T
A
= 85° C
PREFERRED
COMMON-MODE
RANGE
13405-022
Figure 22. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM),
VSY = 4.5 V, TA = 85°C
20
–20
–15
–10
–5
0
5
10
15
0 1 2 3 4 5 6 7 8 109
I
B–
(fA)
V
CM
(V)
V
SY
= 10V
27 CHANNELS
T
A
= 85° C
PREFERRED
COMM ON-M ODE RANGE
13405-023
Figure 23. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM),
VSY = 10 V, TA = 85°C
20
–20
–15
–10
–5
0
5
10
15
0246810 12 14 16
I
B–
(fA)
V
CM
(V)
V
SY
= 16V
27 CHANNELS
T
A
= 85° C
PREFERRED
COMM ON-M ODE RANGE
13405-024
Figure 24. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM),
VSY = 16 V, TA = 85°C
20
–20
–15
–10
–5
0
5
10
15
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
IB+ (fA)
VCM (V)
VSY = 4.5V
27 CHANNELS
TA = 85° C
PREFERRED
COMMON-MODE
RANGE
13405-025
Figure 25. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 4.5 V, TA = 85°C
20
–20
–15
–10
–5
0
5
10
15
012345678 109
I
B+
(fA)
V
CM
(V)
V
SY
= 10V
27 CHANNELS
T
A
= 85° C
PREFERRED
COMM ON-M ODE RANGE
13405-026
Figure 26. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 10 V, TA = 85°C
20
–20
–15
–10
–5
0
5
10
15
0246810 12 14 16
I
B+
(fA)
V
CM
(V)
V
SY
= 16V
27 CHANNELS
T
A
= 85° C
PREFERRED
COMM ON-M ODE RANGE
13405-027
Figure 27. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 16 V, TA = 85°C
ADA4530-1 Data Sheet
Rev. B | Page 16 of 52
300
–300
–200
–100
0
100
200
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
I
B–
(fA)
V
CM
(V)
V
SY
= 4.5V
27 CHANNELS
T
A
= 125° C
PREFERRED
COMMON-MODE
RANGE
13405-028
Figure 28. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM),
VSY = 4.5 V, TA = 125°C
300
–600
–500
–400
–300
–200
–100
0
100
200
012345678 109
I
B–
(fA)
V
CM
(V)
V
SY
= 10V
27 CHANNELS
T
A
= 125° C
PREFERRED
COMM ON-M ODE RANGE
13405-029
Figure 29. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM),
VSY = 10 V, TA = 125°C
300
–300
–200
–100
0
100
200
0246810 12 14 16
I
B–
(fA)
V
CM
(V)
V
SY
= 16V
27 CHANNELS
T
A
= 125° C
PREFERRED
COMM ON-M ODE RANGE
13405-030
Figure 30. Inverting Input Bias Current (IB−) vs. Common-Mode Voltage (VCM),
VSY = 16 V, TA = 125°C
300
–300
–200
–100
0
100
200
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
IB+ (fA)
VCM (V)
VSY = 4.5V
27 CHANNELS
TA = 125° C
PREFERRED
COMMON-MODE
RANGE
13405-031
Figure 31. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 4.5 V, TA = 125°C
300
–600
–500
–400
–300
–200
–100
0
100
200
012345678 109
I
B+
(fA)
V
CM
(V)
V
SY
= 10V
27 CHANNELS
T
A
= 125° C
PREFERRED
COMM ON-M ODE RANGE
13405-032
Figure 32. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 10 V, TA = 125°C
300
–600
–500
–400
–300
–200
–100
0
100
200
0246810 12 14 16
I
B+
(fA)
V
CM
(V)
V
SY
= 16V
27 CHANNELS
T
A
= 125° C
PREFERRED
COMM ON-M ODE RANGE
13405-033
Figure 33. Noninverting Input Bias Current (IB+) vs. Common-Mode Voltage (VCM),
VSY = 16 V, TA = 125°C
Data Sheet ADA4530-1
Rev. B | Page 17 of 52
1000
0.001
0.01
0.1
1
10
100
010 3020 40 50 60 70 80 90 100 110 120 130
I
B
(fA)
TEMPERATURE (°C)
V
SY
= 4.5V
V
CM
= V
SY
/2
RH < 10%
–40°C TO + 85°C L IMIT
–40°C TO + 125°C L IMIT
I
B
+
I
B
–
13405-234
Figure 34. Input Bias Current (IB) vs. Temperature, VSY = 4.5 V
1000
0.001
0.01
0.1
1
10
100
010 3020 40 50 60 70 80 90 100 110 120 130
I
B
(fA)
TEMPERATURE (°C)
V
SY
= 10V
V
CM
= V
SY
/2
RH < 10%
–40°C TO + 85°C L IMI T
–40°C TO + 125°C L IMIT
13405-235
I
B
+
I
B
–
Figure 35. Input Bias Current (IB) vs. Temperature, VSY = 10 V
1000
0.001
0.01
0.1
1
10
100
010 3020 40 50 60 70 80 90 100 110 120 130
I
B
(fA)
TEMPERATURE (°C)
V
SY
= 16V
V
CM
= V
SY
/2
RH < 10%
–40°C TO + 85°C L IMI T
–40°C TO + 125°C L IMIT
13405-236
I
B
+
I
B
–
Figure 36. Input Bias Current (IB) vs. Temperature, VSY = 16 V
120
100
80
60
40
20
0
–250 –200 –150 –100 –50 050 100 150 200 250
NUMBER O F AMP LI FI E RS
I
B
– (fA)
V
SY
= 10V
V
CM
= V
SY
/2
590 CHANNELS
T
A
= 125° C
x = –40.69fA
σ = 24.54fA
13405-019
Figure 37. Inverting Input Bias Current Histogram, TA = 125°C, VSY = 10 V
120
100
80
60
40
20
0
–250 –200 –150 –100 –50 050 100 150 200 250
NUMBER O F AMP LI FI E RS
IB+ (fA)
VSY = 10V
VCM = VSY/2
590 CHANNELS
TA = 125° C
x = –74.59fA
σ = 23.66fA
13405-020
Figure 38. Noninverting Input Bias Current Histogram, TA = 125°C, VSY = 10 V
160
120
140
100
80
60
40
20
0
–150 –120 –90 –60 –30 030 60 90 120 150
NUMBER O F AMP LI FI E RS
I
OS
(fA)
V
SY
= 10V
V
CM
= V
SY
/2
590 CHANNELS
T
A
= 125° C
x = 33.9fA
σ = 17.9fA
13405-239
Figure 39. Input Offset Current Histogram
ADA4530-1 Data Sheet
Rev. B | Page 18 of 52
10
0.0001
0.001
0.01
0.1
1
0.01 0.1 110 100
OUTPUT VOLTAGE LOW (VOL) TO SUPPLY RAIL (V)
LOAD CURRENT (mA)
–40°C
+25°C
+85°C
+125°C
VSY = 4. 5V
13405-037
Figure 40. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD),
VSY = 4.5 V
10
0.0001
0.001
0.01
0.1
1
0.01 0.1 110 100
OUTPUT VOLTAGE LOW (V
OL
) TO SUPPLY RAIL (V)
LO AD CURRE NT (mA)
–40°C
+25°C
+85°C
+125°C
V
SY
= 10V
13405-038
Figure 41 Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD),
VSY = 10 V
10
0.0001
0.001
0.01
0.1
1
0.01 0.1 110 100
OUTPUT VOLTAGE LOW (V
OL
) TO SUPPLY RAIL (V)
LO AD CURRE NT (mA)
–40°C
+25°C
+85°C
+125°C
V
SY
= 16V
13405-039
Figure 42. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD),
VSY = 16 V
10
0.001
0.01
0.1
1
0.01 0.1 110 100
OUTPUT VOLTAGE HIGH (VOH) TO SUPPLY RAIL (V)
LOAD CURRENT (mA)
–40°C
+25°C
+85°C
+125°C
VSY = 4. 5V
13405-040
Figure 43. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD),
VSY = 4.5 V
10
0.001
0.01
0.1
1
0.01 0.1 110 100
OUTPUT VOLTAGE HIGH (VOH) TO SUPPLY RAIL (V)
LO AD CURRE NT (mA)
–40°C
+25°C
+85°C
+125°C
VSY = 10V
13405-041
Figure 44. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD),
VSY = 10 V
10
0.001
0.01
0.1
1
0.01 0.1 110 100
OUTPUT VOLTAGE HIGH (V
OH
) TO SUPPLY RAIL (V)
LO AD CURRE NT (mA)
–40°C
+25°C
+85°C
+125°C
V
SY
= 16V
13405-042
Figure 45. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD),
VSY = 16 V
Data Sheet ADA4530-1
Rev. B | Page 19 of 52
100
90
80
70
60
50
40
30
20
10
0
–50 –25 025 50 75 100 125
TEMPERATURE (°C)
OUTPUT VOLTAGE LOW (V
OL
) TO SUPPLY RAIL (mV)
V
SY
= 4.5V
R
L
= 2kΩ
R
L
= 10kΩ
13405-043
Figure 46. Output Voltage Low (VOL) to Supply Rail vs. Temperature,
VSY = 4.5 V
225
200
175
125
150
75
100
25
50
0
TEMPERATURE (°C)
–50 –25 025 50 75 100 125
OUTPUT VOLTAGE LOW (V
OL
) TO SUPPLY RAIL (mV)
V
SY
= 10V
R
L
= 2kΩ
R
L
= 10kΩ
13405-044
Figure 47. Output Voltage Low (VOL) to Supply Rail vs. Temperature,
VSY = 10 V
360
330
300
270
240
210
180
150
120
90
60
30
0
–50 –25 025 50 75 100 125
TEMPERATURE (°C)
OUTPUT VOLTAGE LOW (V
OL
) TO SUPPLY RAIL (mV)
V
SY
= 16V
R
L
= 2kΩ
R
L
= 10kΩ
13405-045
Figure 48. Output Voltage Low (VOL) to Supply Rail vs. Temperature,
VSY = 16 V
100
90
80
70
60
50
40
30
20
10
0
–50 –25 025 50 75 100 125
TEMPERATURE (°C)
OUTPUT VOLTAGE HIGH (V
OH
) TO SUPPLY RAIL (mV)
V
SY
= 4.5V
R
L
= 2kΩ
R
L
= 10kΩ
13405-046
Figure 49. Output Voltage High (VOH) to Supply Rail vs. Temperature,
VSY = 4.5 V
225
200
175
125
150
75
100
25
50
0
TEMPERATURE (°C)
–50 –25 025 50 75 100 125
V
SY
= 10V
OUTPUT VOLTAGE HIGH (V
OH
) TO SUPPLY RAIL (mV)
R
L
= 2kΩ
R
L
= 10kΩ
13405-047
Figure 50. Output Voltage High (VOH) to Supply Rail vs. Temperature,
VSY = 10 V
360
330
300
270
240
210
180
150
120
90
60
30
0
–50 –25 025 50 75 100 125
TEMPERATURE (°C)
OUTPUT VOLTAGE HIGH (V
OH
) TO SUPPLY RAIL (mV)
V
SY
= 16V
R
L
= 2kΩ
R
L
= 10kΩ
13405-048
Figure 51. Output Voltage High (VOH) to Supply Rail vs. Temperature,
VSY = 16 V
ADA4530-1 Data Sheet
Rev. B | Page 20 of 52
1.4
1.2
1.0
0.8
0.6
0.4
0.2
00 4 8 11 162 6 10 14
I
SY
PER AMPLIFIER (mA)
SUPPLY VOLTAGE (V)
–40°C
+25°C
+85°C
+125°C
V
CM
= V
SY
/2
13405-049
Figure 52. Supply Current (ISY) per Amplifier vs. Supply Voltage (VSY)
1.4
0
0.2
0.4
0.6
0.8
1.0
1.2
TEMPERATURE (°C)
–50 –25 025 50 75 100 125
I
SY
PER AMPLIFIER (mA)
V
CM
= V
SY
/2
4.5V
10V
16V
13405-050
Figure 53. Supply Current (ISY) per Amplifier vs. Temperature
0
–200
–180
–140
–120
–60
–160
–100
–80
–40
–20
0 1 32 4 5 6 7 8 9 10
SMALL S IG NAL PS RR ( dB)
VCM (V)
VSY = 10V
ΔVCM = 400mV
PREF E RRE D INPUT VOL TAG E
RANGE
PSRR–
PSRR+
13405-254
Figure 54. Small Signal PSRR vs. Common-Mode Voltage (VCM)
Data Sheet ADA4530-1
Rev. B | Page 21 of 52
MAIN AMPLIFIER, AC PERFORMANCE
VSY = 4.5 V to 16 V, data taken at VSY = 10 V, TA = 25°C, unless otherwise noted.
120
100
80
60
40
20
0
–20
–40
–60
10k 100k 1M 10M
OPEN-LOOP GAIN (dB)
FREQUENCY ( Hz )
120
100
80
60
40
20
0
–20
–40
–60
PHASE M ARGI N ( Degrees)
10pF
10pF
100pF
100pF
VSY = 10V
RL = 10kΩ
13405-055
Figure 55. Open-Loop Gain and Phase Margin vs. Frequency
10k 100k 10M1M
FREQUENCY ( Hz )
100
90
80
70
60
50
40
30
20
10
0
CMRR (dB)
V
SY
= 10V
V
CM
= V
SY
/2
R
L
= 10kΩ
C
L
= 10pF
13405-056
Figure 56. CMRR vs. Frequency
10k 100k 10M1M
60
50
40
30
20
10
0
PSRR (dB)
FREQUENCY ( Hz )
PSSR+
PSSR–
V
SY
= 10V
V
CM
= V
SY
/2
R
L
= 10kΩ
C
L
= 10pF
13405-057
Figure 57. PSRR vs. Frequency
60
–20
0
–10
10
30
50
20
40
1k 10k 100k 1M 10M
CLOSED-LOOP GAIN (dB)
FREQUENCY ( Hz )
V
SY
= 10V
R
L
= 10kΩ
C
L
= 10pF
A
V
= +1
A
V
= +10
A
V
= +100
13405-058
Figure 58. Closed-Loop Gain vs. Frequency
10k
0.0001
0.01
0.001
0.1
10
1k
1
100
100 1k 10k 100k 1M 10M
CLOSED-LOOP OUTPUT IMPEDANCE (Ω)
FREQUENCY ( Hz )
A
V
= +10
A
V
= +100
A
V
= +1
V
SY
= 10V
V
CM
= V
SY
/2
13405-059
Figure 59. Closed-Loop Output Impedance vs. Frequency
60
50
40
30
20
10
0030 60 90 120 150 180 210 240 270
OVERSHOOT (%)
LO AD CAP ACIT ANCE ( pF )
V
SY
= 10V
V
IN
= 100mV p - p
A
V
= +1
R
L
= 10kΩ
OS–
OS+
13405-060
Figure 60. Small Signal Overshoot vs. Load Capacitance
ADA4530-1 Data Sheet
Rev. B | Page 22 of 52
80
–80
–40
20
60
0
–60
–20
40
VOLT AGE (mV)
TIME (2µs/DIV)
V
SY
= 4.5V
V
IN
= 100mV p - p
A
V
= +1
R
L
= 10kΩ
C
L
= 10pF
R
S
= 1kΩ
13405-061
Figure 61. Small Signal Transient Response, VSY = 4.5 V
80
–80
–40
20
60
0
–60
–20
40
VOLT AGE (mV)
TIME (2µs/DIV)
V
SY
= 10V
V
IN
= 100mV p - p
A
V
= +1
R
L
= 10kΩ
C
L
= 10pF
R
S
= 1kΩ
13405-062
Figure 62. Small Signal Transient Response, VSY = 10 V
80
–80
–40
20
60
0
–60
–20
40
VOLT AGE (mV)
TIME (2µs/DIV)
V
SY
= 16V
V
IN
= 100mV p - p
A
V
= +1
R
L
= 10kΩ
C
L
= 10pF
R
S
= 1kΩ
13405-063
Figure 63. Small Signal Transient Response, VSY = 16 V
1.0
–2.5
–2.0
–1.5
–0.5
0.5
–1.0
0
VOLT AGE (V)
V
SY
= 4.5V
V
IN
= 2.75V p-p
A
V
= +1
R
L
= 10kΩ
C
L
= 10pF
R
S
= 1kΩ
TIME (2µs/DIV)
13405-064
Figure 64. Large Signal Transient Response, VSY = 4.5 V
6
–6
–4
0
4
–2
2
VOLT AGE (V)
V
SY
= 10V
V
IN
= 8.25V p-p
A
V
= +1
R
L
= 10kΩ
C
L
= 10pF
R
S
= 1kΩ
TIME (5µs/DIV)
13405-065
Figure 65. Large Signal Transient Response, VSY = 10 V
10
8
6
4
2
0
–2
–4
–6
–8
–10
VOLT AGE (V)
V
SY
= 16V
V
IN
= 14.25V p-p
A
V
= +1
R
L
= 10kΩ
C
L
= 10pF
R
S
= 1kΩ
TIME ( 20µs/ DIV)
13405-066
Figure 66. Large Signal Transient Response, VSY = 16 V
Data Sheet ADA4530-1
Rev. B | Page 23 of 52
VOUT
–1.4
INPUT VOLTAGE (V)
0.2
0
–1.0
–0.4
–0.6
–1.2
–0.8
–0.2
TIME (2µs/DIV)
7
6
5
3
4
1
2
0
–1
OUTPUT VOLTAGE (V)
VSY = 4.5V
VIN = 450mV
AV = –10
RL = 10kΩ
CL = 10p F
VIN
13405-067
Figure 67. Positive Overload Recovery, VSY = 4.5 V
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–2.0
–2.2
–2.4
–2.6
–2.8
–3.0
–3.2
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
V
SY
= 10V
V
IN
= 900mV
A
V
= –10
R
L
= 10kΩ
C
L
= 10pF
16
14
15
12
13
8
9
10
11
3
2
4
5
6
7
1
0
–1
V
IN
V
OUT
TIME (2µs/DIV)
13405-068
Figure 68. Positive Overload Recovery, VSY = 10 V
1
–8
–6
–3
–1
0
–4
–7
–5
–2
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (2µs/DIV)
24
21
18
15
9
0
3
6
12
–3
V
SY
= 16V
V
IN
= 1.5V
A
V
= –10
R
L
= 10kΩ
C
L
= 10pF
V
IN
V
OUT
13405-069
Figure 69. Positive Overload Recovery, VSY = 16 V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (2µs/DIV)
V
SY
= 4.5V
V
IN
= 400mV
A
V
= –10
R
L
= 10kΩ
C
L
= 10pF
V
IN
V
OUT
2.5
2.0
1.5
1.0
–0.5
–2.0
–1.5
–1.0
0
0.5
–2.5
13405-070
Figure 70. Negative Overload Recovery, VSY = 4.5 V
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (2µs/DIV)
V
SY
= 10V
V
IN
= 900mV
A
V
= –10
R
L
= 10kΩ
C
L
= 10pF
V
IN
V
OUT
7
5
3
1
–1
–5
–3
–7
13405-071
Figure 71. Negative Overload Recovery, VSY = 10 V
2
1
0
–1
–2
–3
–4
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
TIME (2µs/DIV)
V
SY
= 16V
V
IN
= 1.5V
A
V
= –10
R
L
= 10kΩ
C
L
= 10pF
V
IN
V
OUT
12
8
4
0
–4
–8
–12
13405-072
Figure 72. Negative Overload Recovery, VSY = 16 V
ADA4530-1 Data Sheet
Rev. B | Page 24 of 52
INPUT VOL TAG E S ( 250mV /DI V )
OUTPUT VOLTAGE (5mV/DIV)
TIME (1µs/DIV)
V
SY
= 4. 5V
DUT A
V
= –1
R
L
= 10kΩ
C
L
= 10p F
ERRO R BAND
POST GAIN = 20
INPUT
OUTPUT
13405-273
Figure 73. Negative Settling Time to 0.1%, VSY = 4.5 V
INP UT VO LT AGES ( 250mV /DI V )
TIME (1µs/DIV)
V
SY
= 10V
DUT A
V
= –1
R
L
= 10kΩ
C
L
= 10p F
ERRO R BAND
POST GAIN = 20
OUTPUT VOLTAGE (5mV/DIV)
INPUT
OUTPUT
13405-274
Figure 74. Negative Settling Time to 0.1%, VSY = 10 V
INP UT VO LT AGES ( 250mV /DI V )
TIME (1µs/DIV)
VSY = 16V
DUT A V = –1
RL = 10kΩ
CL = 10p F
ERRO R BAND
POST GAIN = 20
OUTPUT VOLTAGE (5mV/DIV)
INPUT
OUTPUT
13405-275
Figure 75. Negative Settling Time to 0.1%, VSY = 16 V
TIME (1µs/DIV)
V
SY
= 4.5V
DUT A
V
= –1
R
L
= 10kΩ
C
L
= 10pF
ERROR BAND
POST GAIN = 20
OUTPUT VOLTAGE (5mV/DIV)
INPUT
OUTPUT
13405-276
INPUT VOL TAG E S ( 250mV /DI V )
Figure 76. Positive Settling Time to 0.1%, VSY = 4.5 V
TIME (1µs/DIV)
V
SY
= 10V
DUT A
V
= –1
R
L
= 10kΩ
C
L
= 10p F
ERRO R BAND
POST GAIN = 20
OUTPUT VOLTAGE (5mV/DIV)
INPUT
OUTPUT
13405-277
INPUT VOL TAG E S ( 250mV /DI V )
Figure 77. Positive Settling Time to 0.1%, VSY = 10 V
TIME (1µs/DIV)
V
SY
= 16V
DUT A
V
= –1
R
L
= 10kΩ
C
L
= 10p F
ERRO R BAND
POST GAIN = 20
OUTPUT VOLTAGE (5mV/DIV)
INPUT
OUTPUT
13405-278
INPUT VOL TAG E S ( 250mV /DI V )
Figure 78. Positive Settling Time to 0.1%, VSY = 16 V
Data Sheet ADA4530-1
Rev. B | Page 25 of 52
0.1
0.001
0.01
10 100 10k1k 100k
THD + N ( %)
FREQUENCY ( Hz )
90kHz LOW-PASS FI L T ER
500kHz LOW - P AS S FI LT E R V
SY
= 4.5V
A
V
= +1
R
L
= 10kΩ
V
IN
= 0.5V rms
13405-279
Figure 79. THD + N vs. Frequency, VSY = 4.5 V
0.1
0.001
0.01
10 100 10k1k 100k
THD + N ( %)
FREQUENCY ( Hz )
90kHz LOW-PASS FI L T ER
500kHz LOW - P AS S FI LT E R V
SY
= 10V
A
V
= +1
R
L
= 10kΩ
V
IN
= 2V rms
13405-280
Figure 80. THD + N vs. Frequency, VSY = 10 V
1
0.1
0.001
0.01
10 100 10k1k 100k
THD + N ( %)
FREQUENCY ( Hz )
90kHz LOW-PASS FI L T ER
500kHz LOW - P AS S FI LT E R V
SY
= 16V
A
V
= +1
R
L
= 10kΩ
V
IN
= 4.5V rms
13405-281
Figure 81. THD + N vs. Frequency, VSY = 16 V
10
1
0.1
0.001
0.01
0.001 0.01 0.1 1
THD + N ( %)
AMPL IT UDE ( V rms)
90kHz LOW-PASS FI L T ER
500kHz LOW - P AS S FI LT E R
VSY = 4.5V
AV = +1
RL = 10kΩ
f = 1kHz
13405-282
Figure 82. THD + N vs. Amplitude, VSY = 4.5 V
10
1
0.1
0.0001
0.001
0.01
0.001 0.01 0.1 101
THD + N (%)
AMPL IT UDE ( V rms)
90kHz LOW-PASS FI L T ER
500kHz LOW - P AS S FI LT E R
V
SY
= 10V
A
V
= +1
R
L
= 10kΩ
f = 1kHz
13405-283
Figure 83. THD + N vs. Amplitude, VSY = 10 V
10
1
0.1
0.001
0.01
0.001 0.01 0.1 101
THD + N (%)
AMPL IT UDE ( V rms)
90kHz LOW-PASS FI L T ER
500kHz LOW - P AS S FI LT E R
V
SY
= 16V
A
V
= +1
R
L
= 10kΩ
f = 1kHz
13405-284
Figure 84. THD + N vs. Amplitude, VSY = 16 V
ADA4530-1 Data Sheet
Rev. B | Page 26 of 52
1000
100
10
1
0.1 100M10M1M100k10k1k100101
VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY ( Hz )
VSY = 10V
AV = +1
RL = 10kΩ
CL = 10pF
13405-285
Figure 85. Voltage Noise Density vs. Frequency, VSY = 10 V
3
1
–1
2
0
–2
–3
INPUT REFERRED VOLTAGE (µV)
TIME (1s/DIV)
VSY = 10V
NOISE = 4µV p-p
13405-286
Figure 86. 0.1 Hz to 10 Hz Noise
Data Sheet ADA4530-1
Rev. B | Page 27 of 52
GUARD AMPLIFIER
TA = 25°C, unless otherwise noted.
120
100
80
60
40
20
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
NUMBER O F AMP LI FI E RS
V
OS
(µV)
V
SY
= 4.5V
V
CM
= V
SY
/2
590 CHANNEL S
T
A
= 25° C
x = –3. 68µ V
σ = 12.35µV
13405-091
Figure 87. Input Offset Voltage Distribution, VSY = 4.5 V
120
100
80
60
40
20
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
NUMBER O F AMP LI FI E RS
V
OS
(µV)
V
SY
= 10V
V
CM
= V
SY
/2
590 CHANNEL S
T
A
= 25° C
x = –3. 8µ V
σ = 12.4µV
13405-092
Figure 88. Input Offset Voltage Distribution, VSY = 10 V
120
100
80
60
40
20
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
NUMBER O F AMP LI FI E RS
V
OS
(µV)
V
SY
= 16V
V
CM
= V
SY
/2
590 CHANNEL S
T
A
= 25° C
x = –3. 86µ V
σ = 12.2µV
13405-093
Figure 89. Input Offset Voltage Distribution, VSY = 16 V
100
50
–50
0
–100
–150
–50 –25 025 50 75 100 125
V
OS
(µV)
TEMPERATURE (°C)
V
SY
= 4.5V
V
CM
= V
SY
/2
574 CHANNELS
13405-094
Figure 90. Input Offset Voltage (VOS) vs. Temperature, VSY = 4.5 V
100
50
–50
0
–100
–150
–50 –25 025 50 75 100 125
V
OS
(µV)
TEMPERATURE (°C)
V
SY
= 10V
V
CM
= V
SY
/2
574 CHANNELS
13405-095
Figure 91. Input Offset Voltage (VOS) vs. Temperature, VSY = 10 V
100
50
–50
0
–100
–150
–50 –25 025 50 75 100 125
V
OS
(µV)
TEMPERATURE (°C)
V
SY
= 16V
V
CM
= V
SY
/2
574 CHANNELS
13405-096
Figure 92. Input Offset Voltage (VOS) vs. Temperature, VSY = 16 V
ADA4530-1 Data Sheet
Rev. B | Page 28 of 52
TCV
OS
(µV/°C)
120
100
80
60
40
20
0
NUMBER O F AMP LI FI E RS
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
7
V
SY
= 4. 5V
V
CM
= V
SY
/2
574 CHANNEL S
–40°C ≤ T
A
≤ 0°C
x = 0. 26µ V /° C
σ = 1.14µV/°C
13405-097
Figure 93. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 4.5 V
TCV
OS
(µV/°C)
120
100
80
60
40
20
0
NUMBER O F AMP LI FI E RS
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
7
V
SY
= 10V
V
CM
= V
SY
/2
574 CHANNEL S
–40°C ≤ T
A
≤ 0°C
x = 0. 26µ V /° C
σ = 1.14µV/°C
13405-098
Figure 94. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 10 V
TCV
OS
(µV/°C)
120
100
80
60
40
20
0
NUMBER O F AMP LI FI E RS
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
7
V
SY
= 16V
V
CM
= V
SY
/2
574 CHANNEL S
–40°C ≤ T
A
≤ 0°C
x = 0. 27µ V /° C
σ = 1.14µV/°C
13405-099
Figure 95. Input Offset Voltage Drift Distribution, −40°C ≤ TA ≤ 0°C, VSY = 16 V
160
0
40
100
140
80
20
60
120
–1.0 –0.6 –0.2 0.2 0.6–0.8 –0.4 00.4 0.8 1.0
TCV
OS
(µV/°C)
NUMBER O F AMP LI FI E RS
V
SY
= 4. 5V
V
CM
= V
SY
/2
574 CHANNEL S
0°C ≤ T
A
≤ 125°C
x = 0. 014µ V /° C
σ = 0.168µV/°C
13405-100
Figure 96. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 4.5 V
160
0
40
100
140
80
20
60
120
–1.0 –0.6 –0.2 0.2 0.6–0.8 –0.4 00.4 0.8 1.0
TCV
OS
(µV/°C)
NUMBER O F AMP LI FI E RS
V
SY
= 10V
V
CM
= V
SY
/2
574 CHANNEL S
0°C ≤ T
A
≤ 125°C
x = 0. 017µ V /° C
σ = 0.168µV/°C
13405-101
Figure 97. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 10 V
160
0
40
100
140
80
20
60
120
–1.0 –0.6 –0.2 0.2 0.6–0.8 –0.4 00.4 0.8 1.0
TCV
OS
(µV/°C)
NUMBER O F AMP LI FI E RS
V
SY
= 16V
V
CM
= V
SY
/2
574 CHANNEL S
0°C ≤ T
A
≤ 125°C
x = 0. 02µ V /° C
σ = 0.168µV/°C
13405-102
Figure 98. Input Offset Voltage Drift Distribution, 0°C ≤ TA ≤ 125°C, VSY = 16 V
Data Sheet ADA4530-1
Rev. B | Page 29 of 52
THEORY OF OPERATION
The ADA4530-1 is an operational amplifier designed to
interface with the extremely high impedance sensors used in
electrometer applications.
A metal-oxide semiconductor field effect transistor (MOSFET)
input stage eliminates the gate leakage currents associated with
legacy junction gate field effect transistor (JFET) electrometers.
The ADA4530-1 achieves extremely low input bias currents while
simultaneously providing robust protection against ESD damage.
A unique ESD diode structure provides protection while also
allowing the diodes to be guarded to minimize leakage currents
to the input pins. The ADA4530-1 integrates the precision
buffer that guards internal ESD diode leakage paths. The output
of this guard buffer also connects to external pins, allowing the
user to guard external components against leakage currents.
The input bias current is determined by the accuracy of the
guard voltage applied across the ESD diodes. The offset voltages
of the amplifier and guard buffer set the accuracy of the guard
voltage and, therefore, the input bias current.
The ADA4530-1 uses Analog Devices, Inc., DigiTrim®
technology to achieve superior performance.
DigiTrim trims the offset voltage of the amplifier and guard
buffer to reject changes in the common-mode voltage, power
supply voltage, and temperature. This technique significantly
improves VOS, CMRR, PSRR, and offset voltage temperature
coefficient (TCVOS) specifications.
Figure 99 shows the simplified schematic of the ADA4530-1.
The amplifier uses a three-stage architecture with a fully
differential input stage to achieve excellent dc performance
specifications.
ESD STRUCTURE
The input ESD structure consists of Diode D1 to Diode D6.
The noninverting input is coupled to the guard pins (GRD)
by the D1 and D2 antiparallel diodes. The inverting input is
coupled to the guard pins by the D3 and D4 antiparallel diodes.
The guard pins are connected to the power supplies through
Diode D5 and Diode D6. During ESD events, the transient
current flows from the input pins through one of the antiparallel
diodes and harmlessly into the supplies through one of the power
supply diodes. During normal operation, the guard buffer (BUF1)
forces the voltage across the antiparallel diodes to 0 V. Resistor R1
shields the guard buffer from potentially large capacitances
connected to the guard pins. Its value is nominally 1 kΩ.
INPUT STAGE
The input stage comprises a P-channel metal-oxide semi-
conductor (PMOS) differential pair (M1, M2), folded cascode
transistors (M5 to M12), and current source (I1).
The ADA4530-1 achieves its high performance specifications by
using low voltage MOS devices for its differential inputs. These
low voltage MOS devices offer better 1/f noise and bandwidth per
unit current compared to high voltage devices. The input stage is
isolated from the high system voltages with proprietary protection
circuitry. This regulation circuitry protects the input devices
from the high supply voltages in which the amplifier can operate.
The proprietary high voltage protection circuitry in the
ADA4530-1 operates to minimize the common-mode voltage
changes seen by the amplifier input stage for most of the input
common-mode range. This circuitry results in excellent
disturbance rejection when operating in this preferred input
common-mode range. The performance benefits of operating
within this preferred range are shown in the VOS vs. VCM graphs
(see Figure 16 to Figure 18), the small signal CMRR vs. VCM
graph (see Figure 21), and the small signal PSRR vs. VCM graph
(see Figure 54).
The input devices are protected from large differential input
voltages by the antiparallel ESD diodes (D1 to D4). The diodes
can conduct significant current when the differential voltage
exceeds 700 mV. The user must ensure that the current flowing
into the input pins is limited to the absolute maximum of 10 mA.
V–
V+
+IN
–IN
GRD
GRD D1
D5
D6
D2
D3 D4
M1 M2
M11
M7
M12
M10
M8
M6M5
M9
M15 M16
M14M13
M21
M19 M20
M18M17
M22
R1
BUF1
HIGH VOLTAGE PROTECTION
HIGH VOLTAGE PROTECTION
I1
I2
M3 M4
V1
C1 C2
C3
OUT
13405-299
Figure 99. Simplified Schematic
ADA4530-1 Data Sheet
Rev. B | Page 30 of 52
GAIN STAGE
The second stage of the amplifier comprises an n-channel
metal-oxide semiconductor (NMOS) differential pair (M3, M4)
and folded cascode transistors (M13 to M20). The amplifier
features nested Miller compensation (C1 to C3).
OUTPUT STAGE
The ADA4530-1 features a complementary common-source
output stage consisting of the M21 and M22 transistors. These
transistors are configured in a Class AB topology and are biased
by the voltage source, V1. This topology allows the output voltage
to be within tens of millivolts of the supply rails, achieving a
rail-to-rail output swing. The output voltage is limited by the
output impedance of the transistors. The output voltage swing is
a function of the load current and can be estimated using the
output voltage to the supply rail vs. load current graphs (see
Figure 40 to Figure 45).
GUARD BUFFER
The guard buffer (BUF1) is a unity-gain amplifier that creates a
low impedance replica of the input common-mode voltage. The
buffer input is connected to the noninverting input (IN+). The
noninverting input voltage is approximately equal to the input
common-mode voltage when the main amplifier feedback loop
is settled.
The guard buffer uses a three-stage architecture similar to that
of the amplifier. The guard buffer uses a rail-to-rail output stage
that allows the guard voltage to swing within 100 mV of the
supply rails. Because the guard buffer output follows the input
common-mode voltage, this output swing limits the effectiveness
of the guard buffer at low input common-mode voltages. This
limit can be seen as a significant increase in the input bias
current at low common-mode voltages shown in the input bias
current vs. common-mode voltage graphs (see Figure 22 to
Figure 33). For this reason, it is not recommended to operate the
circuit with an input common-mode voltage of less than 100 mV
from the V− supply rail.
The guard buffer output voltage can be degraded from excessive
loading. The 1 kΩ output resistance adds 1 μV of guard voltage
error per 1 nA of load current. It is possible to drive the guard
offset voltage out of its specifications with a few tens of nano-
amperes of load current. For this reason, it is not recommended
to drive anything except insulation resistance (see the Insulation
Resistance section and the Guarding section) with the guard
buffer. If more drive strength is needed, the guard voltage can
be buffered with a low offset, low input bias current op amp
such as the ADA4661-2.
Data Sheet ADA4530-1
Rev. B | Page 31 of 52
APPLICATIONS INFORMATION
The ADA4530-1 is a single, electrometer grade, complementary
metal-oxide semiconductor (CMOS) operational amplifier with
femtoampere input bias current and ultralow offset voltage. It
operates over a wide supply voltage range of 4.5 V (or ±2.25 V
dual supply) to 16 V (or ±8 V dual supply). It is a single-supply
amplifier; its input voltage range includes the lower supply rail
and has a rail-to-rail output. The ADA4530-1 also achieves a
low offset voltage of ±40 µV maximum and offset voltage drift
of ±0.5 µV/°C maximum.
The ADA4530-1 has ultralow input bias currents that are
production tested at 25°C and 125°C to ensure the device meets
its performance goals in a system application. An integrated
guard buffer is provided to minimize input pin leakage in a PCB
design, minimize board component count, and enable ease of
system design. The guard buffer output pins are also strategically
placed next to the input pins to enable easy routing of the guard
ring and to prevent coupling between the inputs, power
supplies, and the output pin.
The ADA4530-1 is suited for applications requiring very low
input bias current and low offset voltage, including, but not
limited to, preamplifier applications, for a wide variety of
current output transducers (such as photodiodes and
photomultiplier tubes), spectrometry, chromatography, and
high impedance buffering for chemical sensors.
INPUT PROTECTION
When either input of the ADA4530-1 exceeds one of the supply
rails by more than 300 m V, the input ESD diodes become
forward-biased and large amounts of current begin to flow
through them. Without current limiting, this excessive fault
current causes permanent damage to the device. If the inputs
are expected to be subject to overvoltage conditions, insert a
resistor in series with each input to limit the input current to
10 mA maximum. However, consider the resistor thermal noise
effect on the entire circuit.
SINGLE-SUPPLY AND RAIL-TO-RAIL OUTPUT
The ADA4530-1 is a single-supply amplifier with an input
voltage range (IVR) from V− to V+ − 1.5 V. The amplifier has a
small keep alive input stage that allows it to function properly
when the input common-mode voltage is greater than the
specified IVR. This feature allows the ADA4530-1 to start up
and recover quickly in certain types of circuits where the IVR is
violated at power-up. The ac and dc performance of this keep
alive stage is poor; do not rely upon this keep alive stage for
normal use.
Figure 100 shows the input and output waveforms of the
ADA4530-1 configured as a unity-gain buffer with a supply
voltage of ±8 V. The output tracks the input voltage over the
entire range until the output voltage is clamped at its maximum
output swing. The amplifier still operates even when the signal
is outside the specified input voltage range (−8 V ≤ IVR ≤ +6.5 V);
this is due to the keep alive stage. Additionally, the amplifier
output does not phase reverse. It is not recommended to apply
an input voltage that is outside of the input voltage range.
10
2
–2
6
4
8
0
–6
–4
–8
–10
VOLT AGE (V)
TI ME (200µs/ DIV)
VSY = ± 8V
VIN = ±8.3V
AV = +1
RL = 10kΩ
CL = 10pF
VIN
VOUT
13405-300
Figure 100. No Phase Reversal
CAPACITIVE LOAD STABILITY
The ADA4530-1 can safely drive capacitive loads of up to
250 pF in any configuration. Driving larger capacitive loads
than specified can cause excessive overshoot, ringing, or
oscillation. A heavy capacitive load reduces phase margin and
causes the amplifier frequency response to peak. Peaking
corresponds to overshooting or ringing in the time domain.
Therefore, it is recommended that external compensation be
used if the ADA4530-1 must drive a load exceeding 250 pF.
This compensation is particularly important in the unity-gain
configuration, which is the worst case for stability.
A quick and easy way to stabilize the op amp for capacitive load
drive is by adding a series resistor, RISO, between the amplifier
output terminal and the load capacitance, as shown in Figure 101.
RISO isolates the amplifier output and feedback network from
the capacitive load. However, with this compensation scheme,
the output impedance as seen by the load increases, and this
reduces gain accuracy.
–V
SY
V
IN
+V
SY
V
OUT
C
L
ADA4530-1
R
ISO
13405-201
Figure 101. Stability Compensation with Isolating Resistor, RISO
ADA4530-1 Data Sheet
Rev. B | Page 32 of 52
Figure 102 shows the phase margin of the ADA4530-1 with
different values of output isolating resistors and capacitive
loads. Figure 103 shows the frequency response with 1 nF
capacitive load and different isolating resistors.
80
60
50
70
40
PHASE M ARGI N ( Degrees)
VSY = 10V
AV = +1
RISO = 301Ω
RISO = 499Ω
RISO = 732Ω
100 1000 10000
LOAD CAPACI TANCE ( pF )
13405-302
Figure 102. Phase Margin vs. Load Capacitance with Various Output
Isolating Resistors
100
40
0
80
20
–20
60
–40
100
40
0
80
20
–20
60
–40
GAI N ( dB)
PHASE ( Degrees)
VSY = 10V
AV = +1
CL = 1nF
PHASE
GAIN
1k 100k10k 1M 10M
FREQUENCY ( Hz )
13405-303
GAI N ( RISO = 0Ω)
GAI N ( RISO = 301Ω)
GAI N ( RISO = 732Ω)
PHASE (RISO = 0Ω)
PHASE (RISO = 301Ω)
PHASE (RISO = 732Ω)
Figure 103. Frequency Response with CL = 1 nF and Various Isolating
Resistors
EMI REJECTION RATIO
Circuit performance is often adversely affected by high frequency
electromagnetic interference (EMI). When the signal strength is
low and transmission lines are long, an op amp must accurately
amplify the input signals. However, all op amp pins—the
noninverting input, inverting input, positive supply, negative
supply, and output pins—are susceptible to EMI signals. These high
frequency signals are coupled into an op amp by various means,
such as conduction, near field radiation, or far field radiation. For
example, wires and PCB traces can act as antennas and pick up
high frequency EMI signals.
Amplifiers do not amplify EMI or RF signals due to their
relatively low bandwidth. However, due to the nonlinearities of
the input devices, op amps can rectify these out of band signals.
When these high frequency signals are rectified, they appear as
a dc offset at the output.
To describe the ability of the ADA4530-1 to perform as intended
in the presence of electromagnetic energy, the electromagnetic
interference rejection ratio (EMIRR) of the noninverting pin is
specified in Table 1, Table 2, and Table 3 of the Specifications
section. A mathematical method of measuring EMIRR is
defined as follows:
EMIRR = 20log(VIN_PEAK/ΔVOS)
where VIN_PEAK is the peak amplitude of the input voltage.
Figure 104 shows the typical EMIRR vs. frequency performance
for each of the specified supply voltages.
120
100
70
20
40
90
60
30
110
80
50
10M 100M 1G 10G
EMI RR (dB)
FREQUENCY ( Hz )
V
SY
= 4.5V
V
SY
= 10V
V
SY
= 16V
V
SY
= 4.5V TO 16V
13405-304
Figure 104. EMIRR vs. Frequency
Data Sheet ADA4530-1
Rev. B | Page 33 of 52
HIGH IMPEDANCE MEASUREMENTS
The ADA4530-1 is designed to maximize the performance of very
high impedance circuits. Its performance advantages make it useful
for circuit impedances ranging from 100 MΩ to over 10 TΩ.
Measurements of high impedance circuits are subject to a number
of error sources. General information about making measurements
from high resistance sources can be found in the Low Level
Measurements Handbook, sixth edition (Keithley Instruments,
Inc., 2004).
The ADA4530-1 is typically used in two kinds of circuits: a buffer
and a transimpedance amplifier (TIA). Buffer circuits are useful for
measuring voltage output sensors with high output resistance.
Some example sensors include pH probes and reference
electrodes (RE) in coulometry control loops. TIA circuits are
useful for converting the signal from a current output sensor to an
output voltage. Some example sensors include photodiodes and
ion chambers.
The following sections describe some of the most important
error sources when using the ADA4530-1 in these circuits.
Simplified models with error sources are provided for the buffer
(see Figure 105) and the TIA (see Figure 106).
The buffer circuit models the voltage output sensor as a voltage
source (VSRC) with an output resistance (RSRC). The voltage on
the A terminal is sensed by Pin 1 of the ADA4530-1 in a
noninverting gain configuration (or a unity-gain configuration).
The B terminal is driven to a suitable reference voltage (signal
ground in this case).
If all error sources are ignored, the output of the circuit is as follows:
+=
S
F
SRC
OUT
R
R
VV 1
ADA4530-1
R
F
R
SRC
V
SRC
R
S
I
B
+
R
IN
V
OS
1
8
6
V
OUT
B
A
VOLTAGE
SENSOR
13405-310
R
SHUNT
+IN
OUT
–IN
Figure 105. Voltage Buffer Circuit
The TIA circuit models the current output sensor as a current
source (ISRC) with a shunt resistance (RSRC). The current from
the A terminal is connected to the inverting input pin of the
ADA4530-1 and the feedback resistor (RF). The B terminal and
the noninverting input of the amplifier are driven to a suitable
reference voltage (signal ground in this case). The negative
feedback of the circuit suppresses any voltage changes at the
A terminal. This suppression is accomplished by forcing all
current through the feedback resistor.
If all error sources are ignored, the output of the circuit is as
follows:
VOUT = ISRC × RF
ADA4530-1
R
SRC
ISRC IB–
RIN
RSHUNT
VOS
8
1
6
VOUT
B
A
CURRENT
SENSOR
RF
V+ IRF
13405-311
Figure 106. TIA Circuit
INPUT BIAS CURRENT
The input bias current of the amplifier is a major error source in
high impedance electrometer circuits.
Like other semiconductor amplifiers, the input bias current of
the ADA4530-1 has an exponential dependence on temperature.
The input bias current of the ADA4530-1 increases by a factor
of 2.5 for every 10°C increase in temperature. Refer to the input
bias current vs. temperature graphs (see Figure 34 to Figure 36)
for typical temperature performance. Notice that the
exponential diode currents cease to be the dominant
contributor to the input bias current at temperatures below
60°C to 70°C. The residual 100 aA to 200 aA (aA = 10−18 A) bias
currents are dominated by other leakage paths that are highly
sensitive to environmental conditions. These vanishingly small
bias currents require highly controlled laboratory conditions to
measure. Most practical applications are dominated by other
errors, and the ADA4530-1 input bias current can be considered
to be zero for temperatures less than 70°C. The input bias
current of the ADA4530-1 can only be guaranteed to ±20 fA
due to the measurement limitations of a production
environment, even though the achievable input bias currents
are more than an order of magnitude lower.
The input bias current affects the buffer circuit by loading down the
voltage sensor. The input bias current is forced to flow through the
output resistance of the sensor, which creates an error voltage, VERR.
VERR = IB+(RSRC)
The magnitude of this voltage error can be significant with very
high impedance sensors operating at high temperature. For
example, the input bias current can generate a maximum voltage
error of 25 mV from a 100 GΩ sensor operating at 125°C.
The input bias current affects the TIA circuit by summing
together with the sensor current. Both of these currents flow
through the feedback resistor to generate the output voltage as
follows:
VOUT = (ISRC + IB−)RF
ADA4530-1 Data Sheet
Rev. B | Page 34 of 52
The magnitude of the input bias current limits how small of a
signal current can be resolved accurately. For example, if the
acceptable error level is 10%, the minimum measurable signal
current is 2.25 pA for a circuit operating at 125°C.
ISRC = IB−(1/err – 1)
where err is the error level.
−= 1
1.0
1
fA250pA25.2
INPUT RESISTANCE
The input resistance of the amplifier is another error source that
must be considered. Input resistance typically has two compo-
nents: differential and common mode. The differential input
resistance is suppressed by the negative feedback of the circuit.
The ADA4530-1 has enough gain that the differential input
resistance is much too large to measure. The common-mode
input resistance (hereafter referred to as input resistance) is a
more important error source.
The input resistance is equal to the change in input bias current
relative to the change in input voltage. This change is not caused
by a physical resistance inside the ADA4530-1; it is the result of
a complex relationship between the accuracy of the guard voltage
across the ESD structures and the input common-mode voltage;
that is, the input resistance changes with common mode voltage. It
is also possible for the input resistance to be negative. Negative
input resistance means the input bias current decreases as the
common-mode voltage increases.
The input resistance, RIN, can be approximated by calculating
the slope of the input bias current vs. common-mode voltage
graphs (see Figure 22 to Figure 33). For example, the noninverting
input resistance can be calculated at 125°C from Figure 32. The
input bias current changes by approximately 20 fA for common-
mode voltages from 4 V to 6 V.
+
∆
∆
=
B
CM
IN
I
V
R
TΩ100
fA20
V2 ==
IN
R
The slope of the curves in the input bias current vs. common-
mode voltage graphs increases rapidly outside the preferred
common-mode range (see Figure 22 to Figure 33). The input
resistance drops rapidly outside this range. This drop in input
resistance must be considered before operating these circuits
with input voltages close to the V− power supply.
Like the input bias current, the input resistance has a strong
temperature dependence. At lower temperatures, the amplifier
input resistance is so high that it is dominated by other error
sources. It is important to recognize the limitations of calculating
input resistance at lower temperatures. Measurement uncertain-
ties make it difficult to accurately calculate the ΔIB term. Consider
the 85°C input bias current vs. common-mode voltage graphs
(see Figure 22 to Figure 27): the measurement uncertainties are
equal to a few fA, which is the same magnitude as the input bias
current itself. These uncertainties make it impossible to calcu-
late input resistances higher than a few hundred teraohms.
The input resistance affects the buffer circuit by loading down
the voltage sensor. This resistance acts as a voltage divider so
the voltage measured by the amplifier is some fraction of the
unloaded voltage of the sensor. This voltage drop is calculated
as follows:
SRC
IN
IN
SRCA RR
R
VV +
=
Consider the previous example of a 100 GΩ sensor operating at
125°C. The 100 TΩ input resistance causes the measured
voltage to equal 99.9% of the actual voltage, a 0.1% gain error.
The input resistance has much less of an effect on the TIA
circuit. The input common-mode voltage does not change in
this circuit; therefore, the error created is vanishingly small.
The input resistance affects the noise gain of the circuit, which
changes the input offset voltage error (see the Photodiode
Interface section for more information).
INPUT OFFSET VOLTAGE
The input offset voltage of the amplifier affects the buffer circuit
by adding directly to the voltage output of the sensor. This error
is typically much smaller than other errors.
The input offset voltage affects the TIA circuit in a different
manner. The burden voltage of the TIA is equal to the input
offset voltage. This burden voltage appears between the A and B
terminals. An error current is created by applying this burden
voltage across the sensor shunt resistance. For sensors with low
output resistances such as photodiodes, this error can be signifi-
cant. Consider a sensor with a 1 GΩ output resistance. The
50 µV maximum offset voltage of the ADA4530-1 creates a
50 fA error current.
INSULATION RESISTANCE
The ADA4530-1 has such low input bias current and such high
input resistance that the insulation resistance of the materials
that are used to construct the circuit is often the largest error
source. Any insulators with finite resistance that come in
contact with the high impedance conductor contribute to the
error current. Some examples include the PCB laminate
material, cable, and connector insulation.
The physical insulation resistance is distributed across the
entire contact surface of the high impedance conductor, and it
can end at several different conductors at different potentials. It
is useful to make a simple model where all of these resistance
paths are lumped into a single resistor. This lumped element is
shown as RSHUNT in the voltage buffer circuit (see Figure 105).
The insulation resistance affects the buffer circuit in the same
way as the amplifier input resistance. This resistance acts as a
voltage divider so that the voltage measured by the amplifier is
some fraction of the unloaded voltage of the sensor.
Data Sheet ADA4530-1
Rev. B | Page 35 of 52
This error is significant because it is very difficult to maintain
high insulation resistance values in glass epoxy (such as FR-4)
PCB materials. Resistance values of 10 TΩ to 100 TΩ are
achievable. A 10 TΩ insulation resistance creates a 1% error with
the 100 GΩ sensor used in previous examples. Insulation
resistance does not have an exponential temperature
dependence like the amplifier errors previously discussed in the
Input Bias Current section and the Input Resistance section,
which makes insulation resistance the dominate error source at
lower temperatures (less than 70°C).
The effect on the insulation resistance on the TIA circuit depends
on the leakage path. The insulation resistance between the A
terminal and B terminal of the current sensor affects the circuit
in the same way as the amplifier input resistance. This error is
extremely small because the voltage across the insulation is
equal to the offset voltage of the amplifier. A much more
significant error is created from insulation paths to conductors
with significantly different potentials. This type of leakage path
is shown as a lumped element, RSHUNT, in the TIA circuit (see
Figure 106). In this example, the leakage path is created from
the positive supply voltage (V+) to the A terminal. If the
positive supply voltage is 5 V relative to signal ground, 500 fA
flows through the insulation resistance of 10 TΩ. This large
error dominates the amplifier input bias current and input
resistance errors over the entire temperature range.
Leakage paths to high voltages can also affect the buffer circuit
with equally ruinous results.
GUARDING
High source impedances and low error requirements can create
insulation resistance requirements that are unrealistically high.
Fortunately, a technique called guarding can reduce these
requirements to a reasonable level. The concept of guarding is
to surround the high impedance conductor with another
conductor (guard) that is driven to the same voltage potential.
If there is no voltage across the insulation resistance (between
high impedance conductor and guard), there cannot be any
current flowing through it.
The ADA4530-1 uses guarding techniques internally, and it has
a very high performance guard buffer integrated. The output of
this buffer is made available externally to simplify the imple-
mentation of guarding at the circuit level.
The voltage buffer circuit (see Figure 105) has been modified to
show the implementation of the guard (see Figure 107). In this
model, a conductor (VGRD) is added, and it completely separates
the high impedance (A) node from the low impedance (B) node
at a different voltage. The insulation resistance is modeled as
two resistances: all of the insulation between the A conductor
and the guard conductor (RSHUNT1), and all of the insulation
between the guard conductor and the B conductor (RSHUNT2).
The ADA4530-1 guard buffer then drives this guard conductor
(through Pin 2 and Pin 7) to the A terminal voltage. If the A node
and VGRD node are exactly the same voltage, no current flows
through the RSHUNT1 insulation resistance.
In practice, the voltage across RSHUNT1 cannot be 0 V, the guard
buffer offset voltage contributes to the difference in voltage
potential between the A node and VGRD node. For the ADA4530-1,
this offset voltage is trimmed to provide offsets less than 100 µV
when the input common-mode voltage is 1.5 V from the supply
rails. The guard buffer offset voltage and drift are specified in
Table 1, Table 2, and Table 3.
For example, assume that the voltage sensor produces an output
of 1 V. Without guarding, the 10 TΩ insulation resistance
creates an error current of 100 fA. With the guard, the voltage
across the insulation resistance is limited to 100 µV. The guard
limits the error current to 0.01 fA. In this example, the guard
reduces the error by a factor of 104 to an insignificant level.
ADA4530-1
RF
RSHUNT1
RSHUNT2
RSRC
VSRC
RS
1
2
8
6VOUT
B
A
VOLTAGE
SENSOR
7
VGRD
13405-313
Figure 107. Voltage Buffer Circuit with Guard
DIELECTRIC RELAXATION
Dielectric relaxation (also known as dielectric absorption or
soakage) is a property of all insulating materials that can limit
the performance of electrometer circuits that need to settle to a
few femtoamperes.
Dielectric relaxation is the delay in polarization of the dielectric
molecules in response to a changing electric field. This delay is
a property of all insulating materials. The magnitude and the
time constant of the delay depend on the specific dielectric
material. The delays in some materials can be minutes or even
hours.
Dielectric relaxation is a problem for electrometer circuits
because small displacement currents flow through the insulator
in response to the polarization of the molecules. Delays in
polarization cause delays in the dissipation of these currents,
which can dominate the settling time in these circuits.
In the context of capacitors, dielectric relaxation is called
dielectric absorption. Capacitors are specified with a test that
measures the residual open-circuit voltage after a specific
charge/discharge cycle. For electrometer circuits, it is more
useful to consider the short-circuit currents produced from step
changes in a test voltage.
A simple lumped circuit model of an insulator is connected to
the test voltage source (see Figure 108). The majority of the
dielectric polarizes instantly; this is modeled as Capacitor C1.
A small percentage of the dielectric polarizes slowly with a time
constant of τ2, modeled as Capacitor C2 and Resistor R2.
ADA4530-1 Data Sheet
Rev. B | Page 36 of 52
The size of C2 reflects the proportion of slow molecules. The
size depends on the material but it is typically 100 to 10,000
times smaller than C1. The size of R2 sets the time constant.
τ2 = R2 × C2
INSULATOR
MODEL
R
S
R2
C2C1
V
SRC
I
SRC
13405-326
Figure 108. Dielectric Relaxation Model Test Circuit
The current step response (ISRC) of the insulator to a voltage step
is shown in Figure 108. A large initial current charges Capacitor C1
with a fast time constant. This time constant, τ1, equals the source
resistance RS × C1 (see Figure 109). Long after Capacitor C1 is
charged, a much smaller current continues to flow, which charges
Capacitor C2. The time constant of charging is not affected by
the external circuitry; it depends only on the material proper-
ties of the insulator. The magnitude of the current depends on
the magnitude of the voltage change across the insulator.
VSRC
ISRC
TIME
1 = RS × C1
2 = R2 × C2
13405-314
Figure 109. Step Response of Dielectric Relaxation Model
The dielectric relaxation performance was measured for a
variety of PCB laminates using the test circuit in Figure 108.
An electrometer grade source measurement unit (SMU),
Keithley 6430, applies a ±100 V test stimulus and measures the
resulting current. The large alternating polarity test voltage
distinguishes the small dielectric relaxation current from the
input offset current of the SMU.
The first PCB laminate tested is the industry-standard FR-4
glass epoxy. The measurement results are shown in Figure 110.
The glass epoxy laminate requires 1 hour to dissipate the
dielectric relaxation current to less than 10 fA. This result shows
that glass epoxy laminates are unsuitable for the highest
performance electrometer circuits.
125
–125
–100
–75
–50
–25
0
25
50
75
100
20
–20
–16
–12
–8
–4
0
4
8
12
16
04.03.0 3.52.52.01.51.00.5
APPLIED VOLT AGE (V)
CURRENT (fA)
ELAPSED TIME (Hours)
V
SRC
I
SRC
13405-315
Figure 110. Glass Epoxy Dielectric Relaxation Performance
An alternative PCB laminate to consider is Rogers 4350B.
Rogers 4350B is a ceramic laminate designed for RF/microwave
circuits. Rogers 4350B is compatible with standard PCB produc-
tion techniques and is widely available. The measurement
results for the Rogers 4350B material are shown in Figure 111.
This material requires less than 20 sec to dissipate the dielectric
relaxation current to less than 1 fA.
Based on its superior performance, it is recommended to use
Rogers 4350B laminates with the ADA4530-1 in the highest
performance applications. All of the critical characterization
measurements of the ADA4530-1 are taken using Rogers 4350B.
125
–125
–100
–75
–50
–25
0
25
50
75
100
10
–10
–8
–6
–4
–2
0
2
4
6
8
0200120 140 160 18010080604020
APPLIED VOLT AGE (V)
CURRENT (fA)
ELAPSED TIME (Seconds)
VSRC
ISRC
13405-316
Figure 111. Rogers 4350B Dielectric Relaxation Performance
Data Sheet ADA4530-1
Rev. B | Page 37 of 52
HUMIDITY EFFECTS
The insulation resistance of the materials used to construct
circuits is sensitive to moisture. At lower temperatures (<70°C)
the insulation resistance creates more significant leakage
current errors than the amplifier itself. This means that the
relative humidity of the air is the most important error source at
lower temperatures. The dependence on humidity is evident in
the input bias current vs. temperature graphs (see Figure 34 to
Figure 36). There is significant deviation in the low temperature
measurements due to the difficulty maintaining a consistently
low relative humidity at low temperatures.
To evaluate the humidity sensitivity of insulation resistance,
there are two mechanisms which must be considered:
adsorption and absorption.
Adsorption is a process where thin films of molecules adhere to
the surface of a material. Water molecules are subject to this
process. The magnitude of the effect depends on the insulating
material and the relative humidity. Thin films of moisture are
conductive, and they act as leakage resistances in parallel with
the insulation resistance of the material. Because this is a
surface effect, guard ring techniques are effective at reducing it.
Absorption is a process where molecules enter the bulk of a
material. Water molecules can diffuse into a material and affect
the bulk conductivity of that material. Because the leakage paths
are through the bulk of the material, guard rings are not
effective at reducing it.
It is not possible to completely guard all the leakage paths: bulk
or surface. A relevant example of this limitation is the molding
compound of the SOIC package housing the ADA4530-1.
Surface and bulk paths exist from the input pins to all other
pins of the package. The nature of the resulting current depends
on the specific leakage path: paths to V+ increase the bias
current flowing out of the amplifier, paths to V− increase the
bias current flowing into the amplifier, and paths to VOUT lower
the effective feedback resistance in TIA circuits.
Consider the example of a circuit powered from ±5 V power
supplies with an input common-mode voltage of 0 V. Assume
that all leakage resistance between the input and V+ is
effectively 100 TΩ. This resistance creates a current equal to
50 fA flowing from V+. Assume that the leakage resistance
between the input and V− is effectively 250 TΩ. This resistance
creates a current equal to 20 fA flowing to V−. The net current
equals −30 fA flowing out of the input pin.
All of these leakage currents can be combined with the
amplifier input bias current and treated as an effective input
bias current. The effective input bias current sensitivity to
relative humidity of the ADA4530-1 is characterized for several
units. The test amplifiers are configured in TIA and unity buffer
circuits with 100 GΩ, hermetically sealed resistors (RX-1M1009FE)
as the feedback and source resistors, respectively. These glass
bodied resistors have a silicone coating (glass has poor humidity
adsorption properties).
The ADA4530-1 amplifiers are mounted on Rogers 4350B PCBs
(glass epoxy boards have poor humidity absorption properties).
Figure 112 shows the effective input bias current vs. relative
humidity for seven characterization units. Figure 112 is plotted
with a split log axis to effectively show the magnitude and polarity
of the bias current. The magnitude of the leakage currents
changes by more than a factor of 100 across the relative humidity
span from 5% to 80%. The effective bias current is much less
than 1 fA for typical conditioned environments (RH < 50%).
I
B
(fA)
100
10
1
0.1
–0.1
020 40 60 80
RELATIVE HUMIDITY (%)
–1
–10
–100
–1000
13405-112
V
SY
= 10V
T
A
= 25° C
V
CM
= V
SY
/2
7 UNIT S
Figure 112. Effective Input Bias Current vs. Relative Humidity
The magnitude of the effective input bias current becomes very
sensitive to the relative humidity at higher humidity levels
(>60%). Some of the units show an exponential dependence on
humidity (see the blue curve in Figure 112). Other units show a
less predictable dependence; the leakage current magnitude
increases rapidly, but the polarity can change. The net leakage
current is the sum of the currents sourced from higher voltages
(like V+) with the currents sunk by lower voltages (like V−). As
the humidity changes, the relative magnitudes of each of these
leakage paths can change, which can result in changes in the
polarity of the leakage current (see the red and green curves in
Figure 112).
The response time of these leakage currents depends on the
physical process that causes them. Because adsorption is a
surface effect, the film thickness rapidly achieves equilibrium
with changes in the relative humidity of the air. Because
absorption is a bulk diffusion process, it is very slow compared
to the adsorption process.
These widely different time constants mean that the effective
input bias current responds quickly to a step change in relative
humidity, but has a very long settling time. The step response of
one amplifier to a 50% to 60% relative humidity change is
shown in Figure 113. The high frequency response of the initial
humidity step (and the overshoot recovery) is on the order of
seconds to tens of seconds. Complete settling takes over a week
as the moisture slowly diffuses through the PCB insulation and
package molding compound. Each data point in Figure 112 was
taken after one week of settling time.
ADA4530-1 Data Sheet
Rev. B | Page 38 of 52
In practical applications, the relative humidity of the air changes
rapidly with daily and seasonal variations. The effective input
bias current response to these humidity changes has two parts.
The response due to the adsorption process follows the rapid
changes immediately. The response due to the absorption
process low-pass filters the humidity changes. This low-pass
response causes the effective input bias current to have long-
term memory of the relative humidity fluctuations.
In this environment, measurements of the effective input bias
current appear to drift with time because the leakage currents
depend on the relative humidity for the previous week. This
long-term memory due to the absorption process may need to
be taken in account in certain circumstances (such as long-term
product storage in an unconditioned high humidity environ-
ment prior to use).
The rapid adsorption response can change the effective bias
current in response to local fluctuations in humidity. These
current fluctuations can be much larger than the low frequency
current noise of the amplifier and thermal noise of the resistors.
The sensitive circuitry can be isolated from these local humidity
fluctuations by restricting the airflow around the circuitry with
an air baffle. Electrostatic shielding added to reduce interfer-
ence can also function as an air baffle. Remove or reduce the
sources of humidity fluctuations whenever possible. Avoid
breathing on the high impedance circuitry, for example.
6
–8
–6
–4
–2
0
2
4
70
0
10
20
30
40
50
60
0175150125100755025
IB (fA)
RELATI V E HUM IDI TY ( %)
ELAPSED TIME (Hours)
VSY = 10V
TA = 25° C
VCM = VSY/2
13405-402
IB
RELATIVE HUMIDITY
Figure 113. Effective Input Bias Current Transient Response to Humidity Step
It is important to note that all electrometer circuits are subject
to humidity effects. The legacy circuits constructed with TO-99
packages using air wiring techniques have insulator leakage paths
such as the epoxy between the pins and the Teflon® standoffs that
support the air wired components. The input bias currents of
legacy amplifiers are high enough to mask the humidity effects.
In summary, the ADA4530-1 can be designed using the specified
performance for normal laboratory (<60%) relative humidity
conditions. In applications that must operate in uncontrolled or
high humidity environments, some additional derating of the
input bias current is prudent. Characterize the amount of derating
on a per product basis because the net leakage depends on the
material types and physical dimensions of the insulators.
CONTAMINATION
The effective insulation resistance of an electrometer circuit can
be substantially degraded if the insulators are contaminated.
Solder flux, body oils, dust, and dirt are all possible sources of
contamination. Some of these contaminants form a parallel
leakage path across the surface of the existing insulator, effec-
tively lowering the insulation resistance. Guarding techniques
help to suppress these effects.
The effects are more severe when the source of contamination
contains ionic compounds. In the presence of humidity, these
contaminants act as an electrolyte, which can form a weak
battery. Flux residue and body oils are particularly effective at
creating these parasitic batteries.
As an example, the PCB insulation between two high imped-
ance nodes was purposefully contaminated with a 3 mm drop of
rosin mildly activated (RMA) type solder flux. This sample was
dried and allowed to stabilize in laboratory conditions (25°C,
40% RH) for several days. After this time, the voltage vs. current
relationship was measured with an electrometer grade SMU
(see Figure 114).
400
–400
–300
–200
–100
0
100
200
300
–100 10020 40 60 800–20–40–60–80
OUTPUT CURRE NT (f A)
APPLIED VOLTAGE (mV)
13405-319
Figure 114. Current to Voltage Response of RMA Contaminated Insulation
This contamination formed a weak battery with an open circuit
voltage (VBATT) of 15 mV and an output resistance (RBATT) of
300 GΩ. This sort of contamination is disastrous in electrome-
ter circuits because guarding techniques cannot suppress it. A
simplified model is made with the contamination battery applied
across the A terminal and B terminal of a TIA circuit (see
Figure 115). The A terminal and B terminal are both driven to
the same voltage, which creates an error current (IBATT) because
the open circuit battery voltage is dropped across the output
resistance as follows:
IBATT = VBATT ÷ RBATT
This battery current flows through the feedback resistance,
where it is summed with the signal and other error currents in
the circuit. The error current in this example is 50 fA. The battery
characteristics are subject to the environmental conditions;
therefore, the error current drifts with time, temperature, and
humidity.
Data Sheet ADA4530-1
Rev. B | Page 39 of 52
13405-312
ADA4530-1
RBATT
VBATT
8
1
6
VOUT
B
A
RF
IBATT
BATTERY
MODEL
Figure 115. TIA Circuit with Contamination Battery
CLEANING AND HANDLING
The contamination described in the Contamination section can
usually be removed by an appropriate cleaning process. Solvents
like isopropyl alcohol (IPA) are effective at removing the residue
from solder fluxes and body oils. Use high purity cleanroom
grade solvents to ensure that there is no additional
contamination from the solvent itself.
Insulators that are severely contaminated benefit from mechani-
cal abrasion in addition to the solvent. Ultrasonic cleaners are
highly effective. Scrubbing the area around the high impedance
insulators with an acid brush also works. Flush the insulators
with a final wash of fresh IPA to remove any contaminants
suspended in the solvent.
The residual moisture must completely evaporate before the
insulator can be used. This evaporation can take many hours at
room temperature; the process can be accelerated by baking the
insulators in an oven at elevated temperature.
For detailed cleaning and handling procedures, refer to the
ADA4530-1R-EBZ user guide.
SOLDER PASTE SELECTION
Solder paste selection can drastically impact the performance of
the board if not cleaned properly. Solder flux residue on a PCB
degrades the low IB performance of the amplifier. An experiment
was performed to evaluate the cleaning procedure for different
solder paste types. Table 7 shows the result of the experiment.
The recommended cleaning procedure column lists the times
required to restore the effective input bias currents to less than
1 fA. The suggested solder paste of choice is the RMA type.
Table 7. Recommended Cleaning Procedures for Different Solder Paste Material
Solder Paste Type Solder Paste Part Number Recommended Cleaning Procedure1
RMA AIM RMA258-15R 15 min clean time in an ultrasonic cleaner with fresh IPA, followed by 1.5 hours of bake
time at 125°C
Water Soluble SAC305 Shenmao 1.5 hours clean time in an ultrasonic cleaner with fresh IPA, followed by 1.5 hours of
bake time at 125°C
No Clean SAC 305 AMTECH LF4300 3 hours clean time in an ultrasonic cleaner with fresh IPA, followed by 3 hours of bake
time at 125°C
1 Bake time was not optimized and was set equal to the cleaning time.
ADA4530-1 Data Sheet
Rev. B | Page 40 of 52
CURRENT NOISE CONSIDERATIONS
The current noise from an amplifier input pin is important
when it flows through an impedance and generates a voltage
noise. If the current noise and impedance are large enough, the
resulting voltage noise can dominate the other noise sources in
the circuit, such as the voltage noise of the resistors and amplifier.
For an electrometer amplifier, such as the ADA4530-1, the
typical circuit impedances are so large that the current noise of
the amplifier can be the most important noise source.
To measure current noise, it is necessary to flow the noise
current through a test impedance large enough that the
resulting noise voltage is larger than the other noise voltages in
the circuit. Practically, this test impedance is usually a resistor.
All resistors have thermal noise. The value of thermal noise is
usually presented as an output referred voltage noise spectral
density (NSD), VNRTO.
VNRTO = √(4kTR)
where:
k is Boltzmann’s constant.
T is the temperature in Kelvin.
R is the resistance value.
The resistor thermal noise can be interpreted as a current NSD
by dividing the thermal noise with the resistance value, R, per
Ohm’s Law.
Table 8 shows the thermal noise of a series of resistor values
presented as both voltage and current noise. The current noise
of a resistor decreases as the resistance increases. This surprising
result illustrates that it is necessary to use high valued resistors
to measure low levels of current noise.
Table 8. Resistor Thermal Noise
Resistor Value Voltage Noise Current Noise
1 MΩ 128 nV/√Hz 128 fA/√Hz
100 MΩ 1.28 µV/√Hz 12.8 fA/√Hz
10 GΩ 12.8 µV/√Hz 1.28 fA/√Hz
1 TΩ 128 µV/√Hz 128 aA/√Hz
The measurement setup used to gather the current noise data is
shown in Figure 116. The ADA4530-1 is configured as a TIA
with a large value feedback resistor, RF. All amplifier current
noise from the inverting input flows through Resistor RF to
produce a voltage noise at VOUT.
RF
CF
ADA4530-1
SR785
DSA
VOUT
13405-305
Figure 116. Current Noise Measurement Setup
The output referred voltage NSD, VNRTO, is sampled by the SR785
high performance dynamic signal analyzer (DSA), and is equal
to the root-sum-square of the amplifier current noise multiplied by
RF, the resistor thermal noise, and amplifier voltage noise.
VNRTO = √((IN−RF)2 + 4kTRF + VN2)
where:
IN− is the amplifier inverting current noise.
4kTRF is the resistor thermal noise.
VN2 is the amplifier voltage noise.
Calculate the current noise of the amplifier from VNRTO as follows:
F
NF
NRTO
N
R
VkTRV
I
22
4−−
=
−
(1)
For Equation 1 to be valid, the measured noise must be somewhat
larger than the resistor thermal noise plus the amplifier voltage
noise. In practice, ensure that the resistor current noise is less
than or equal to the amplifier current noise. For example, if the
amplifier noise is expected to be 2 fA/√Hz, use a value of RF that
is at least 10 GΩ, according to Table 8.
The amplifier voltage noise is not a concern at most frequencies
because the resistor thermal noise is much larger than the amplifier
voltage noise. At very low frequencies, this assumption is not
valid due to the 1/f characteristic of the amplifier voltage noise.
It is important to consider the bandwidth limitations of the
current noise measurement system shown in Figure 116. The
presence of stray capacitance makes it impossible to maintain
the high impedances required for the measurement. All stray
capacitances that couple the amplifier output to the inverting
input can be lumped into a single capacitor, CF, as shown in
Figure 116.
The current noise must pass through RF to become voltage
noise. However, in practice, the current noise passes through
the parallel combination of RF and CF to become voltage noise.
At frequencies higher than the RFCF pole, most of the noise current
flows through the capacitor and current noise calculations at
these frequencies are error prone due to the distributed parasitic
nature of CF. A good guideline is to set the measurement band-
width limit equal to the RFCF pole frequency.
The measurement bandwidth limitations for high valued resistors
can be surprisingly low. Table 9 shows the −3 dB bandwidth of a
series of resistor values with a practical minimum stray capacitance
value.
Table 9. Bandwidth Limitations
Resistor Value Capacitor Value −3 dB Bandwidth
1 MΩ 100 fF 1.59 MHz
100 MΩ 100 fF 15.9 kHz
10 GΩ
100 fF
159 Hz
1 TΩ 100 fF 1.59 Hz
Data Sheet ADA4530-1
Rev. B | Page 41 of 52
Reconsider the example amplifier with 2 fA/√Hz of current
noise. The required RF value of 10 GΩ also limits the
measurement bandwidth to 159 Hz according to Table 9.
It is useful to construct a table that combines the resistor noise
and measurement bandwidth guidelines. Table 10 shows the
approximate bandwidth limitations for a variety of input
current noise measurements.
Table 10. Measurement Current Noise Density vs. Bandwidth
Current Noise Density Bandwidth
128 aA/√Hz 1.59 Hz
1.28 fA/√Hz 159 Hz
12.8 fA/√Hz 15.9 kHz
128 fA/√Hz 1.59 MHz
Table 10 demonstrates the error of the often claimed 0.1 fA/√Hz
at 10 kHz presented in the specifications of low input bias
current amplifiers. Measuring this value requires a 1 TΩ resistor
with less than 15.9 aF (15.9 × 10−18 F) of stray capacitance,
which is impossible.
These kinds of claims are simply shot noise calculations based
on the specified input bias currents of a few tens of femtoamperes.
Calculate the shot noise of a semiconductor as follows:
Shot Noise = √(2qIB)
where:
q is the charge on an electron.
IB is the current flowing through a junction.
Shot noise calculations are appropriate only for some legacy
JFET-based electrometer amplifiers, where only a single junction is
connected to the amplifier input pins. Modern high impedance
amplifiers have several semiconductor junctions connected to
the amplifier input pins. The most significant of these junctions
are the ESD diode structures. The input bias currents are equal
to the sum of these diode currents. The diode currents are
designed to cancel each other, but the shot noise currents are
uncorrelated and cannot cancel, which makes calculating the
shot noise from the input bias current impossible.
Even when appropriate, these shot noise calculations neglect all
capacitive coupling effects so that they are valid only at very low
frequencies. The gate to source capacitance of the input transis-
tors couples noise currents from sources other than the input
junctions for frequencies above a few tens of hertz. This blowback
noise effect is present in all amplifiers, and it ensures that the
current NSD always increases as frequency increases.
The complex relationship between current noise, feedback
resistance, and bandwidth means that the correct way to
characterize the current noise of an electrometer amplifier is by
measuring the output NSD with a variety of feedback resistors
that cover the entire span of values used in the end applications.
Each feedback resistor establishes a boundary for the minimum
measurable current noise over a range of frequencies.
It is critically important to use high quality resistors during this
measurement. Many high valued resistors designed for high
voltage operation are nonlinear at low voltage levels and are not
suitable for electrometer work. Inferior resistors can also have
their own 1/f noise that corrupts the measurement results. Table 11
lists the resistors used for the characterization of the ADA4530-1.
Table 11. Test Resistor Device Numbers
Resistor Value Manufacturer Device Number
100 MΩ Vishay RNX050100MDHLB
1 GΩ Ohmite RX-1M1007GE
10 GΩ Ohmite RX-1M1008JE
100 GΩ Ohmite RX-1M1009FE
1 TΩ Ohmite RX-1M100AKE
Figure 117 shows the output referred voltage NSD (VNRTO) of
the transimpedance test circuit for the test resistors listed in
Table 11. The calculated thermal noise for each resistor is
represented with the dashed line. The black dashed line
represents the 1/f voltage noise of the amplifier.
100
1
10
100
10
1
0.001 100k10k1k1001010.10.01
TOTAL OUTPUT VOLTAGE NOISE DENSITY (µV/√Hz)
INPUT SERIES RESISTOR THERMAL NOISE (µV/√Hz)
FRE QUENCY ( Hz )
VSY = 10V
AV = +1
1/f
1TΩ
100GΩ
10GΩ
1GΩ
100MΩ
13405-306
Figure 117. Transimpedance NSD Referred to Output
VNRTO is dominated by the resistor noise for all of the test
resistors up 1 TΩ. This means that the current noise contribu-
tion from the ADA4530-1 is insignificant relative to the thermal
noise of these resistors.
ADA4530-1 Data Sheet
Rev. B | Page 42 of 52
It is possible to calculate the current noise of the ADA4530-1
with the 1 TΩ resistor. This result is shown in Figure 118. It is
impossible to calculate the amplifier current noise for all of the
other resistors, because, at those resistor values, the resistor
noise is much greater than the amplifier current noise. The
current noise densities of each of the test resistors are plotted as
dashed lines in Figure 118. The current noise of the ADA4530-1
is below the resistor noise values.
100
0.01
0.1
1
10
0.001 100k10k1k1001010.10.01
CURRENT NOISE DENSITY (fA/√Hz)
FREQUENCY ( Hz )
V
SY
= 10V
A
V
= +1
1TΩ
100GΩ
10GΩ
1GΩ
100MΩ
13405-307
Figure 118. Current Noise Spectral Density
The current noise of the ADA4530-1 originates from the
saturation current of the ESD diodes. The diode saturation
current has an exponential dependence on temperature;
therefore, it is expected that the current noise tracks this
temperature behavior. The current noise of the ADA4530-1 is
characterized over temperature using the transimpedance
measurement circuit with a 1 TΩ resistor. The measurements
are limited to 85°C because of the maximum operating
temperature of the resistor. Figure 119 shows the current noise
density at a frequency of 0.1 Hz for all of the test temperatures.
It can be useful to calculate an equivalent noise resistance from
the current noise density data in Figure 119. This conversion
facilitates comparisons between the current noise generated by
the ADA4530-1 and the thermal noise of the feedback resistor
used in the circuit.
800
0
200
400
600
700
100
300
500
0908070605040302010
CURRENT NOISE DENSITY (aA/√Hz)
TEMPERATURE (°C)
V
SY
= 10V
f = 0. 1Hz
13405-308
Figure 119. Current Noise Density vs. Temperature
Figure 120 shows the equivalent noise resistance vs. temperature.
From Figure 120, it is easy to determine that the ADA4530-1
contributes less noise than a 1 TΩ resistor for temperatures less
than 40°C. If the application requires an 85°C operation, the
ADA4530-1 contributes as much noise as a 30 GΩ resistor. This
example illustrates the considerable impact of the temperature
in determining the noise performance of an application.
10T
10G
100G
1T
0908070605040302010
EQUIVALENT NOISE RESISTANCE (Ω)
TEMPERATURE (°C)
f = 0. 1Hz
13405-309
Figure 120. Equivalent Noise Resistance vs. Temperature
In summary, the excellent noise performance of the ADA4530-1
makes it ideal for electrometer applications. For impedances
less than 1 TΩ, the amplifier noise is negligible. Also, unlike
other amplifiers, the current noise is fully characterized and is
free of excessive blowback noise.
Data Sheet ADA4530-1
Rev. B | Page 43 of 52
LAYOUT GUIDELINES
PHYSICAL IMPLEMENTATION OF GUARDING
TECHNIQUES
In the Guarding section, guarding is introduced as a technique
fundamental to high impedance work. The goal of guarding is
to completely surround the insulation of the high impedance
node with another conductor that is driven to the guard voltage.
This ideal is impossible to achieve in practice; however, there
are several practical structures that provide good performance.
GUARD RING
A guard ring is a structure typically used to implement the
guarding technique on the surface of the PCB. A simplified
layout of the buffer circuit implements the guard ring around
the high impedance (A) trace (see Figure 121). The output of
the voltage sensor is wired directly to the A and B pads in
Figure 121. The guard ring is a filled copper shape that
completely surrounds the high impedance (A) trace from the
sensor connection to the noninverting input (Pin 1). The guard
ring is driven directly from the ADA4530-1 guard buffer (Pin 2)
through a thermal relief shape connection. It is not necessary to
connect the other guard buffer output (Pin 7).
The solder mask is removed from the high impedance trace and
the guard trace to ensure that the guard makes electrical contact
with any surface leakage paths. For the same reason, avoid
printing any silkscreen in this section.
VOUT
V–
V+
B
A
GUARD
RF
GND
C+
C–
RS
13405-320
ADA4530-1
Figure 121. Buffer Circuit Layout
There is not a large amount of exposed insulation between the
A trace and the guard ring. It is often counterproductive to
increase this spacing to try to increase the insulation resistance
because the exposed insulator tends to accumulate surface
charges generated from piezoelectric or triboelectric effects.
These charges are eventually swept across the insulator toward
the high impedance conductor.
The magnitude of this error current is dependent on the area of
the exposed high impedance insulation. A gap of 15 mil
between the A trace and the guard ring is sufficient.
Another simplified layout demonstrates the implementation of
a guard ring in the TIA circuit (see Figure 122). The guard ring
is implemented in the same manner as the buffer circuit. The
primary difference is that the left half of the feedback resistor
(RF) and feedback capacitor (CF) are connected to the high
impedance node. The guard ring shape is extended around
these passive components to ensure that the entire high
impedance node is surrounded by guard. The guard ring is
directly driven from the ADA4530-1 guard buffer (Pin 7).
ADA4530-1
VOUT
V–
V+
B
A
GUARD
RF
CF
GND
C+
C–
13405-321
Figure 122. TIA Circuit Layout
The guard voltage in the TIA circuit is nominally equal to the B
voltage, which makes it possible to drive the guard ring directly
from the B voltage without using the ADA4530-1 guard buffer.
When implementing the guard ring this way, do not make any
connection to the guard buffer outputs (Pin 2 and Pin 7).
GUARD PLANE
A guard plane is a structure used to implement the guarding
technique through the bulk of the PCB. The structure of the
guard plane is shown in a cross section of the PCB (see Figure 123).
The guard plane is a filled copper shape that is placed directly
below the high impedance (A) trace. This plane is connected to
the guard ring on the surface layer with vias.
If the circuit board is constructed using high performance PCB
laminates such as Rogers 4350B, a hybrid stackup is required for
mechanical strength. The outside layers are ceramic, whereas the
core layers are conventional glass epoxy laminate. It is important to
place the guard shield on the boundary of the ceramic and glass
epoxy materials to protect the high impedance node from the
poor dielectric relaxation characteristics of the glass epoxy
materials.
ADA4530-1 Data Sheet
Rev. B | Page 44 of 52
13405-322
AGUARD
GUARD
GUARD
FR-4
ROGERS
4350B
SOLDER MASK SOLDER MASK
Figure 123. Layout Cross Section with Guard Plane
VIA FENCE
A via fence is an additional structure that guards the lateral
leakage paths in the laminate between the guard ring and the
guard plane (see Figure 123). The fence is implemented by
surrounding the entire guard ring with vias that connect the
guard ring to the guard plane (see Figure 121 and Figure 122).
CABLES AND CONNECTORS
Guarding techniques are required for all high impedance
wiring—not just on the PCB. Frequently, the high impedance
sensor is not directly mounted on the PCB with the electrome-
ter amplifier and external cables are used to make the connection.
The typical way to guard a cable connecting to a current output
sensor is by using a coaxial cable. A coaxial cable consists of an
inner conductor surrounded with insulation, which is, in turn,
surrounded by a braided conductor. Use the inner conductor
for the high impedance (A) terminal and the outer braided
shield conductor for the low impedance (B) terminal. Conven-
iently, this arrangement effectively guards the coaxial insulation
resistance because the A terminal and B terminal are nominally
at the same voltage (when attached to a TIA interface circuit).
Voltage output sensors are more problematic because the A
terminal and B terminal are not at the same voltage. The typical
way to guard the voltage output sensor cable is to use a triaxial
cable. A triaxial cable is constructed with an inner conductor
with two separate braided conductors. Each of these braided
conductors is separated from each other with insulation. Use
the inner conductor for the high impedance (A) terminal and
the inner braided conductor for the guard (VGRD) connection,
and use the outer braided conductor for the low impedance (B)
terminal. All the insulation around the inner conductor is
completely surrounded by the guard conductor, which keeps the
voltage drop across this insulation equal to zero.
ELECTROSTATIC INTERFERANCE
Very high impedance electrometer circuits are susceptible to
interference through capacitive coupling. The amount of capaci-
tance required to couple low frequency signals is surprisingly
small. For example, line frequency (60 Hz) interference is
coupled (with a −3 dB loss) to a 1 TΩ impedance with only 3 fF
of coupling capacitance.
Traditional electrical interferers are not the only sources of concern.
Calculate the displacement current, I, in a capacitor as follows:
t
C
V
t
V
CI ∂
∂
+
∂
∂
=
(2)
The second term in this equation is frequently ignored in most
circuits, but it can generate some unusual problems in electrome-
ter circuits. The problem is that the movement of any charged
object changes the coupling capacitance between the object and
the electrometer, and this change in capacitance injects small
currents into the circuit. The ADA4530-1 is so sensitive that it
easily detects the movement of a hand or the movement of a
piece of paper. These types of effects are not periodic or predic-
table, and they can appear as erratic dc shifts on the time scales
of interest.
Both of these types of interference can be reduced by the
addition of a shield. A shield is a piece of conductive material
placed between the high impedance input and the interference
source. This shield must be electrically connected to a low
impedance source (such as signal ground). If the shield physi-
cally interrupts all of the capacitive coupling paths, all of the
displacement current from the interference source is shunted to
the low impedance source.
The construction of a shield is almost the same as the construc-
tion of a guard. Because of this similarity, many guard structures
also provide shielding as well. The primary difference is that the
dc voltage of the shield is not important, whereas the guard
must have a voltage equal to that of the high impedance input.
Shields that are driven by the guard buffer have the added benefit
of bootstrapping the capacitance between the high impedance
input and the shield. The disadvantage of this approach is that
the guard buffer output impedance is 1 kΩ, which makes the
shield less effective than a signal ground or a chassis ground
connection. The most effective systems typically use the box
within a box construction: the outer shield is driven with
ground and the inner shield is driven with guard.
There is another capacitive interference effect that typically
cannot be shielded. This displacement current is generated from
a change in capacitance with respect to time (the second term of
Equation 2). This change is due to the mechanical movement of
the circuit components. This movement, which can be caused
by mechanical impact or vibration, generates electrical interference.
This interference typically appears at unexpected frequencies
that are equal to the mechanical resonances of the components.
This effect must be considered when using traditional air wiring
techniques for large feedback resistors or relays. It is important
to ensure solid mechanical connections to Teflon standoffs for
this type of construction.
Data Sheet ADA4530-1
Rev. B | Page 45 of 52
PHOTODIODE INTERFACE
The low input bias current and low input offset voltage makes
the ADA4530-1 an excellent choice for signal conditioning
photodiodes at extremely low illumination levels. Figure 124
shows the ADA4530-1 configured in a transimpedance ampli-
fier interfacing with a photodiode operating in photovoltaic
mode (photodiode is zero biased). A photodiode produces an
output current proportional to the illumination level. The
amplifier converts the signal current, IPD, into an output voltage
with the following equation:
VOUT = IPD × RF
R
F
C
F
V
OUT
PHOTODIODE
I
PD
13405-323
Figure 124. Transimpedance Amplifier with Photodiode
Figure 125 replaces the photodiode with an equivalent circuit
model. IPD is the photo current generated by incident light and
is proportional to the light level. The shunt capacitance (CSHUNT)
models the depletion capacitance of the diode. This capacitance
depends on the area of the photodiode and the voltage bias. The
shunt resistance (RSHUNT) represents the voltage vs. current slope
of the exponential diode curve near zero bias voltage.
13405-324
R
F
C
F
V
OUT
PHOTODIODE
R
SHUNT
C
SHUNT
I
PD
Figure 125. Transimpedance Amplifier with Photodiode Model
DC ERROR ANALYSIS
All of the errors described in the High Impedance Measurements
section related to TIA circuits are applicable to photodiode
interfaces.
The inverting input bias current, IB−, sums directly with the
photodiode current for a referred to input (RTI) error equal to
IB−. This current flows through the feedback resistor, creating a
referred to output (RTO) error, VIB_TRO, equal to
VIB_RTO = IB− × RF
The amplifier offset voltage, VOS, is a major error source in
photodiode interface circuits because of the relatively low shunt
resistance of large area photodiodes. Typical values are in the
range of 1 GΩ to 100 GΩ at 25°C.
More importantly, the shunt resistance decreases by half for
every 10°C increase in temperature. An error current is created
because the amplifier offset voltage is applied across this shunt
resistance, resulting in an RTI error (IVOS_RTI) equal to
IVOS_RTI = VOS/RSHUNT
It is equivalent to think that the shunt resistance increases the
DC noise gain (NG), which multiplies the offset voltage to the
output. The RTO error due to VOS is equal to
VOS_RTO = VOS × Noise Gain
VOS_RTO = VOS × (1 + RF/RSHUNT)
The amplifier input resistance and insulation resistance appear
in parallel with the photodiode shunt resistance. These addi-
tional resistances reduce the effective shunt resistance, but they
are much larger than the photodiode shunt resistance and can
usually be ignored.
AC ERROR ANALYSIS
Photodiode TIA circuits typically require external compensation to
give satisfactory dynamic performance. The large feedback
resistor (RF) interacts with the large photodiode capacitance
(CSHUNT) to create a low frequency pole in the feedback network.
Photodiode shunt capacitance, amplifier input capacitance, and
trace capacitance are lumped into a single element, CSHUNT. The
phase shift due to this pole must be recovered prior to the
crossover frequency for the feedback loop to be stable. The
usual method to recover this phase shift is to create a zero in the
feedback factor with the addition of the feedback capacitor (CF).
The classic way of analyzing this circuit is by examining the
noise gain vs. frequency (see Figure 126). At low frequencies,
the noise gain is determined by the ratio of the feedback to the
shunt resistance.
SHUNT
1
R
RF
NG +=1
The troublesome low frequency pole (which is a zero in the
noise gain) occurs at Frequency f1. From this frequency onward,
the noise gain increases. If there is no feedback capacitor in the
circuit, the noise gain follows the dotted line until it intersects
with the amplifier open-loop gain curve. If these curves
intersect at the 20 dB/decade slopes shown in Figure 126, the
circuit is unstable.
The addition of CF adds a zero to the feedback factor (which is a
pole in the noise gain) at Frequency f2. Beyond Frequency f2, the
noise gain is determined by the ratio of the shunt capacitance to
the feedback capacitance.
F
SHUNT
2
C
C
NG +=1
ADA4530-1 Data Sheet
Rev. B | Page 46 of 52
GAIN (dB)
FREQUENCY (Hz)
CLOSED-LOOP BANDWIDTHSIGNAL BANDWIDTH
IF C
F
= 0fF
NG
2
NG
1
NOISE GAIN
OPEN-LOOP GAIN
f1fUGC
f2f3
13405-325
Figure 126. Transimpedance Noise Gain vs. Frequency
For completeness, the noise gain equations are as follows:
+
+
+=
1
2
1
2
1)(
2
1
S
F
f
f
f
f
R
R
fNG
π
π
( )
SHUNT
F
SHUNT
F
SHUNT
F
1
CC
RR
RR
f
+
+
=1
FF
2
CR
f1
=
For simplicity, bandwidth limitations are ignored in the noise
gain equations. The noise gain starts to roll-off when it
intersects with the open-loop gain of the amplifier. This pole
frequency (f3) is determined by the unity gain crossover
frequency (fUGC) of the amplifier and the high frequency noise
gain, NG2, as follows:
+
=
F
SHUNT
UGC
C
C
f
f
1
3
(3)
The addition of CF has an impact on the signal frequency
response. At low frequencies, the transimpedance gain is equal
to RF. As the frequency increases, the impedance of CF drops
below RF and starts to reduce this transimpedance gain. This
signal gain equation is as follows:
+
π
=
1
2
1
)(
2
F
f
f
RfGainSignal
NOISE ANALYSIS
Photodiode TIA circuits have four noise sources that must be
considered:
•The thermal noise of the feedback resistor (RF)
•The saturation current noise of the photodiode
•The current noise of the amplifier
•The voltage noise of the amplifier
The noise contributions of these sources are typically referred to
output for analysis. The thermal noise of RF appears directly at
the output. This noise is filtered by the feedback capacitance so
that its −3 dB bandwidth is the same as the signal bandwidth (f2).
The photocurrent of a photodiode, IPD, produces shot noise equal to
INPD = √(2qIPD)
It is a mistake to assume that the noise goes to zero as the diode
current goes to zero. Zero net current out of the diode simply
means that the saturation current flowing in one direction is at
thermal equilibrium with the saturation current flowing in the
opposite direction. These currents are uncorrelated and add in a
root sum square fashion. This net current noise is equivalent to
the thermal noise of a physical resistor with a value of RSHUNT.
This convenient fact allows the photodiode to be accurately
modeled with a simple resistor, RSHUNT. The thermal noise of
RSHUNT is amplified by the ratio of the feedback resistance to the
shunt resistance. This noise is also filtered to the signal bandwidth.
The current noise of the amplifier flows through the feedback
resistor to become a noise voltage at the output. It is subject to
the same bandwidth limitations as the previous noise contributors.
The voltage noise of the amplifier is multiplied by the noise gain
of the circuit to the output. This noise source is significant for
two reasons. First, the high frequency noise gain can be high
due to the large ratio between the shunt capacitance and the
feedback capacitance. Second, the voltage noise bandwidth is
much higher than the other contributors. The noise bandwidth
is limited only by bandwidth of the amplifier.
Data Sheet ADA4530-1
Rev. B | Page 47 of 52
Each of these noise contributors is graphed vs. frequency in
Figure 127. A summary of the noise sources and their RTO
contributions is shown in Table 12. The total RTO noise adds
the contributions of each noise source in root sum square.
13405-404
FREQUENCY
NSD (µV/√Hz)
1
10
100
0.1
110 100 1k
f1f2f3
RF
RSHUNT
IN–
VN
Figure 127. Photodiode TIA RTO Noise Spectral Density
Table 12. Photodiode Interface Noise Sources
Noise Source
RTO Noise
Noise Bandwidth
R
F
√(4kTR
F
)
π/2 × f
2
Photodiode (RF/RSHUNT)√(4kTRSHUNT) π/2 × f2
IN− Amplifier RF × IN− π/2 × f2
VN Amplifier VN × noise gain π/2 × f3
DESIGN RECOMMENDATIONS
The design goal for a large area photodiode TIA circuit is
usually to maximize signal-to-noise ratio (SNR) and minimize
dc errors. Increasing the feedback resistor size accomplishes
both goals. The signal gain increases directly with RF, whereas
the noise increases in a square root fashion. High gains also
make the output signal large relative to output voltage errors
(such as VOS).
The upper limit for RF is typically determined by one of the
following:
•Amplifier output swing. The maximum photocurrent
multiplied by RF must be less than amplifier swing
limitations.
•Signal bandwidth (or settling time). Signal bandwidth is
dependent on RF × CF. Achieving high signal bandwidths
with large feedback resistors can require vanishingly small
feedback capacitors to implement. The ultimate limitation
is due to the parasitic feedback capacitance from the
fringing electric fields in the circuit. Parasitic capacitances
in the 50 fF to 100 fF range are possible. For example, a
100 fF parasitic capacitance limits the signal bandwidth of
a 100 GΩ TIA to 16 Hz.
•The thermal noise of the photodiode (RSHUNT). When RF is
significantly larger than RSHUNT, the total noise is domi-
nated by the photodiode and the SNR stops improving.
•The current noise of the amplifier. When the current noise
of the amplifier is larger than the noise of RF, the SNR stops
improving. The photodiode noise is higher than the
amplifier current noise in nearly all practical photodiodes.
•The low frequency noise gain due to RSHUNT. When RF is
larger than RSHUNT, the noise gain multiplies VOS and TCVOS
errors and the signal to error ratio stops improving.
The signal bandwidth increases as the feedback capacitance (CF)
decreases. The lower limit for CF is typically limited by one of
the following:
•Parasitic feedback capacitances limit the minimum value of
CF to 50 fF to 100 fF.
•Available component values. Physical components can be
found in surface mount packages for values from 0.1 pF to
1 pF in 100 fF increments.
•Feedback loop stability. CF must be large enough to recover
enough phase shift prior to the loop crossover for stable
operation. This capacitance value can be a significant
consideration for smaller values of RF. Large values
(>1 GΩ) tend to be self compensating through the parasitic
feedback capacitance.
•High frequency noise gain. The high frequency noise gain
is set by the ratio of CSHUNT to CF. For very large noise gains,
it is possible for the amplifier voltage noise to be greater
than the feedback resistor noise.
DESIGN EXAMPLE
In this section, an example TIA circuit is designed using a
photometry grade photodiode (Hamamatsu S1226-18BQ). This
medium area (1.2 mm2) silicon photodiode is responsive in the
ultraviolet (UV) through visible frequency range. The mini-
mum shunt resistance (RSHUNT) is specified at 5 GΩ at 25°C. The
shunt capacitance (CSHUNT) is specified at 35 pF. The quartz
window limits the maximum operating temperature to 60°C.
Based on the specified minimum shunt resistance and the
recommendations in the Design Recommendations section, a
value of 10 GΩ is chosen for RF. This example circuit is powered
from ±5 V with the input common-mode voltage set at 0 V, which
allows a maximum photocurrent of approximately 500 pA.
An error budget is constructed based on the DC Error Analysis
section (see Table 13). The amplifier offset voltage applies the
maximum temperature drift limit to the maximum room
temperature offset limit. The photo diode shunt resistance limit
is reduced by half for every 10°C.
ADA4530-1 Data Sheet
Rev. B | Page 48 of 52
Table 13. Photodiode Interface DC Error Budget
Error Source 25°C 45°C 60°C
VOS 40 μV 40 μV + 10 μV 40 μV + 18 μV
RSHUNT 5 GΩ 1.25 GΩ 442 MΩ
Noise Gain 3 9 23
VOS Error RTO 120 μV 450 μV 1.3 mV
IB 20 fA 20 fA 20 fA
IB Error RTO 200 μV 200 μV 200 μV
Total Error RTO 320 μV 650 μV 1.5 mV
Total Error RTI 32 fA 65 fA 150 fA
The total RTI error over the entire temperature range is less
than 150 fA, which is equal to 300 ppm of the 500 pA full-scale
range. The low input bias current of the ADA4530-1 is not a
significant contributor to the total error over temperature. The
interaction of the offset voltage with the shunt resistance of the
photodiode is the most significant error source.
This circuit was constructed as described with a 10 GΩ feed-
back resistor (Ohmite RX-1M1008JE). The dc error performance
was measured over the 25°C to 60°C temperature range (see
Figure 128). The error increases rapidly with temperature as the
shunt resistance changes the noise gain exponentially. The total
RTI error ranges from +2 fA to −10 fA, considerably lower than
the worst case error budget, as expected.
20
–120
–100
–80
–60
–40
–20
0
2
–12
–10
–8
–6
–4
–2
0
070605040302010
RTO ERROR (µV)
RTI ERROR (fA)
TEMPERATURE (°C)
V
SY
= 10V
V
CM
= V
SY
/2
13405-401
Figure 128. DC Error vs. Temperature
The ac performance of the circuit was also measured. The
circuit was initially constructed without a physical feedback
capacitor as a baseline. The transimpedance gain vs. frequency
is shown in Figure 129. The 30% frequency peaking seen in the
frequency response (red curve) indicates that the feedback loop
is marginally compensated with parasitic capacitance.
A physical capacitor was added to improve the loop compensa-
tion. This capacitor is a 300 fF C0G ceramic in a Size 0805,
surface-mount package (AVX UQCFVA0R3BAT2A\500). C0G
ceramic capacitors are good candidates for electrometer circuits
because they have adequate insulation resistance and dielectric
absorption performance.
These low valued capacitors are designed for RF use and are
readily available. The 300 fF capacitor eliminates the frequency
peaking completely (blue curve) but it reduces the −3 dB
bandwidth from 390 Hz to 50 Hz.
0.1
1
10
0.1 1 10 100 1k 10k 100k
TRANSIMPEDANCE GAIN (GΩ)
FREQUENCY (Hz)
V
SY
= 10V
V
CM
= V
SY
/2
T
A
= 25°C
13405-407
C
F
= 0fF
C
F
= 300fF
Figure 129. Transimpedance Gain vs. Frequency
The stability improvement can be seen in the time domain as
well. The circuits step response to a 10 pA photocurrent is
shown in Figure 130. The uncompensated circuit (red curve)
shows considerable (20%) overshoot. The compensated circuit
(blue curve) is overdamped.
40
–140
–120
–100
–80
–60
–40
–20
0
20
4
–14
–12
–10
–8
–6
–4
–2
0
2
0403530252015105
OUTPUT VOLTAGE (mV)
INPUT REFERRED CURRENT (pA)
TIME (ms)
V
SY
= 10V
T
A
= 25°C
I
PD
= 10pA
13405-400
C
F
= 0fF
C
F
= 300fF
Figure 130. 10 pA Step Response
A noise budget is constructed based on the Noise Analysis
section. The RTO noise budget is separated into noise sources
integrated with a low bandwidth (see Table 14) and those
integrated with a high bandwidth (see Table 15).
The low frequency noise contributors include the feedback
resistance, the shunt resistance and the amplifier current noise.
Each of these sources has a −3 dB bandwidth equal to the signal
bandwidth (50 Hz); this is equivalent to a noise bandwidth of
79 Hz. The most significant noise source is the photodiode
shunt resistance by a large margin. The second most significant
source is the feedback resistor. The amplifier current noise is so
low that it can be ignored.
Data Sheet ADA4530-1
Rev. B | Page 49 of 52
Table 14. Low Frequency Noise Budget
Error Source 25°C 45°C 60°C
VNRF 12.8 μV/√Hz 13.2 μV/√Hz 13.5 μV/√Hz
RSHUNT 5 GΩ 1.25 GΩ 442 MΩ
VNRSHUNT 9 μV/√Hz 4.7 μV/√Hz 2.8 μV/√Hz
RF/RSHUNT 2 8 22
VNRSHUNT_RTO 18 μV/√Hz 37 μV/√Hz 61 μV/√Hz
IN− 0.07 fA/√Hz 0.15 fA/√Hz 0.24 fA/√Hz
IN−_RTO 700 nV/√Hz 1.5 μV/√Hz 2.4 μV/√Hz
Low Frequency
NSD Total
22 μV/√Hz 39 μV/√Hz 62 μV/√Hz
Low Frequency
RMS Total
194 μV rms 345 μV rms 549 μV rms
The sole high frequency noise contributor is the amplifier
voltage noise, which is multiplied by the high frequency noise
gain and band limited only by the amplifier gain. The −3 dB
bandwidth of the amplifier is 17 kHz (refer to Equation 3,
where f3 = fUGC ÷ NG2 = 2 MHz ÷ 118). The equivalent noise
bandwidth is 27 kHz. The high bandwidth is the reason the
high frequency noise is significant even though the noise
spectral density is much lower than the low frequency noise.
Table 15. High Frequency Noise Budget
Error Source 25°C 45°C 60°C
VN 14 nV/√Hz 14.5 nV/√Hz 14.8 nV/√Hz
High Frequency
Noise Gain
118 118 118
VN_RTO 1.6 μV/√Hz 1.7 μV/√Hz 1.7 μV/√Hz
High Frequency
RMS Total
271 μV rms 281 μV rms 286 μV rms
At low temperatures, the amplifier voltage noise is more signifi-
cant than any other noise source. This is important because the
majority of this noise occurs outside the useful bandwidth of
the circuit. For this reason, it is recommended to add a low-pass
filter to the output of a photodiode TIA circuit. This filter can
be active or passive depending on the needs of the system. A
simple resistor capacitor (RC) filter with a −3 dB cutoff of 500 Hz
has an insignificant impact on the frequency response of the
signal path, but it lowers the integrated noise from 271 μV rms to
45 μV rms (a 6× reduction).
The NSD was measured for this circuit with (blue curve) and
without (red curve) the 300 fF CF capacitor (see Figure 131). At
low frequencies, the NSD is approximately equal to the noise
from the feedback resistor alone (12.8 μV/√Hz). The value of
the low frequency NSD shows that the shunt resistance is much
larger than the specified minimum (which is expected). As
frequency increases, the resistor noise rolls off at the signal
bandwidth (50 Hz). The NSD then plateaus at the amplifier
voltage noise level until the bandwidth limitations of the
amplifier roll off the NSD toward zero.
110
10 100
100 1000
0.1 100k10k1k100101
VOLTAGE NOISE SPECTRAL DENSITY (µV/√Hz)
INTEGRATED VOTLAGE NOISE (µV rms)
FREQUENCY (Hz)
V
SY
= 10V
V
CM
= V
SY
/2
T
A
= 25°C
13405-405
NSD, C
F
= 0fF
NSD, C
F
= 300fF
RMS, C
F
= 0fF
RMS, C
F
= 300fF
Figure 131. RTO Noise Spectral Density (25°C)
The dashed curves show the integration of the NSD across the
frequency spectrum. These are useful to calculate the rms noise
over a variety of bandwidths. For example, the rms noise over
the entire 100 kHz measurement bandwidth is 400 μV rms,
which is approximately the same as the calculated total noise of
333 μV rms. If a postfilter is added with a noise bandwidth of
1 kHz, Figure 131 shows that the integrated noise is 200 μV rms
(a 2× improvement).
The uncompensated circuit (red curves) shows considerably
worse noise performance. The frequency peaking due to the
marginal loop stability multiplies the noise as well as the signal.
In addition, the high frequency noise gain is larger, which adds
much more noise outside the signal bandwidth. Both of these
effects together generate 1.2 mV rms of total noise. Even if the
transient and frequency response of an undercompensated TIA
are acceptable, the large noise penalty may not be.
Lastly, the NSD was measured for this circuit at 60°C (see
Figure 132). As expected, the low frequency noise increased as a
result of the photodiode shunt resistance. The average low
frequency NSD is 22 μV/√Hz. Removing the contribution of RF
gives an RTO contribution of 17 μV/√Hz, which is equivalent to
an RTI current noise of 1.7 fA/√Hz. RSHUNT must be approxi-
mately 6.5 GΩ at 60°C to generate this noise.
110
10 100
100 1000
0.1 100k10k1k100101
VOLTAGE NOISE SPECTRAL DENSITY (µV/√Hz)
INTEGRATED VOTLAGE NOISE (µV rms)
FREQUENCY (Hz)
V
SY
= 10V
V
CM
= V
SY
/2
T
A
= 60°C
13405-406
NSD, C
F
= 300fF
RMS, C
F
= 300fF
Figure 132. RTO Noise Spectral Density (60°C)
ADA4530-1 Data Sheet
Rev. B | Page 50 of 52
POWER SUPPLY RECOMMENDATIONS
Analog Devices offers a wide range of power management
products to meet the requirements of most high performance
signal chains.
Examples of a single- and dual-supply solution is shown in
Figure 133. The ADP2370 and ADP5075, cascaded with the
ADP7118 or ADM7170, and the ADP7182 generate clean
positive and negative rails. These rails power the ADA4530-1,
electrometer amplifier and/or the precision converter in a
typical signal chain.
+5V
3.3V
INPUT ADP5070
BOOST AND
INVERTING
REGULATOR
ADP7118
LDO
ADP7182
LDO
ADP2370
BUCK
REGULATOR
+7.5V
OR +5V
+8.5V
OR +6V ADP7118
LDO
ADP5075
INVERTING
REGULATOR
–8.5V
OR –6V
+6V
–6V –5V
ADP7182
LDO
15V/12V/6V
INPUT ADM7170/
ADP7118
LDO
+12V/+10V/+5V
12V
INPUT
–7.5V
OR –5V
13405-533
Figure 133. Recommended Power Solutions
Table 16. Recommended Power Management Devices
Product Description
ADP5075
800 mA, dc-to-dc inverting regulator
ADP2370
High voltage, 1.2 MHz/600 kHz, 800 mA, low
quiescent current buck regulator
ADP5070
1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
ADM7170
6.5 V, 500 mA, ultralow noise, high PSRR, CMOS LDO
ADP7118
20 V, 200 mA, low noise, high PSRR, CMOS LDO
ADP7182 −28 V, −200 mA, low noise, linear regulator
POWER SUPPLY CONSIDERATIONS
The PSRR of the ADA4530-1 is excellent at dc (approximately
150 dB); however, it decreases as frequency increases. To achieve
the best performance of the ADA4530-1, a low-noise supply is
necessary. If switching supplies are used for input rails, a low
dropout regulator (LDO) is essential to attenuate the switching
spurs to a level that does not affect the ADA4530-1 output.
Switching power supply noise typically spans a frequency range
from 300 kHz and up. The switching spurs can effectively be
attenuated using the LDO. Additional filtering around the LDO
may be necessary, especially when using a switching regulator to
generate an intermediate rail. Switching regulators also generate
high frequency noise content (>100 MHz), even when running
in the 100 kHz range, because of the high dv/dt of the switch
node. In this case, ferrite beads can be used, as described in the
AN-1120 Application Note and the AN-1368 Application Note.
For a single-supply application, the ADA4530-1 typically needs
a 5 V, 1 0 V, or 12 V supply, although a 4.5 V to 16 V supply can
also be used. An LDO like the ADM7170 or ADP7118 is ideal
to generate the low noise rail.
For a dual-supply application, the ADA4530-1 typically needs a
±5 V supply, although in some applications, a ±2.5 V to ±8 V
supply can be used. LDOs like the ADP7118 or ADM7170 are the
optimum choices for the positive supply, and the ADP7182 for
the negative supply. In addition, if a negative supply is not already
available, the ADP5075 or the ADP5070 can generate the
negative supply from a positive supply, as shown in Figure 133.
Figure 134 shows the combined PSRR of using the ADP7118 to
provide +5 V on +VSY of the ADA4530-1, and the ADP7182 to
provide –5 V on–VSY, from a 9 V battery main supply. Figure 135
shows the maximum allowable ripple at the input so that the
combined PSRR of the LDO and the amplifier can still attenuate
the noise level down to the noise floor.
For example, if the main supply to the ADP7118 and ADA4530-1
has a switching noise of 20 mV p-p at 300 kHz, Figure 135 shows
that it is below the maximum value of 90 mV p-p. Therefore,
the combined PSRR of the system can still attenuate and bring
the noise level down to the noise floor, in effect, the 300 kHz
noise at the input is not seen at the output of the amplifier.
0
–120
–100
–80
–60
–40
–20
10k 10M1M100k
PSRR (dB)
FREQUENCY ( Hz )
+PSRR
–PSRR
13405-534
Figure 134. Positive and Negative PSRR for the ADP7118 and ADP7182
Powering ADA4530-1, ±VSY = ±5 V, +IN = 0 V
100
1000
0.01
0.1
1
10
1010.10.01
ADP7118
ADP7182
FREQUENCY (Hz)
(mV p-p)
13405-535
Figure 135. Maximum Allowable Ripple at the Input of the LDOs to Bring
Spurs To Noise Floor Level (−120 dB)
Data Sheet ADA4530-1
Rev. B | Page 51 of 52
LONG-TERM DRIFT
The stability of a precision signal path over its lifetime or
between calibration procedures is dependent on the long-term
stability of the analog components in the path, such as op amps,
references, and data converters. To help system designers
predict the long-term drift of circuits that use the ADA4530-1,
Analog Devices measured the offset voltage of multiple units for
10,000 hours (more than 13 months) using a high precision
measurement system, including an ultrastable oil bath. To
replicate real-world system performance, the devices under test
(DUTs) were soldered onto an FR4 PCB using a standard reflow
profile (as defined in the JEDEC J-STD-020D standard), as
opposed to testing them in sockets. This manner of testing is
important because expansion and contraction of the PCB can
apply stress to the integrated circuit (IC) package and contribute to
shifts in the offset voltage.
The ADA4530-1 have extremely low long-term drift, as shown
in Figure 136. The red, blue, and green traces show sample
units. Note that the ADA4530-1 has a mean drift over 10,000 hours
of less than 0.5 µV, or less than 2% of its maximum specified
offset voltage of 40 µV at room temperature.
TIME (Hours)
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10,000
CHANGE IN OFFSET VOLTAGE (µV)
–25
–20
–15
–10
–5
0
5
10
15
20
25
V
SY
= 10V
27 UNITS
T
A
= 25° C
MEAN
MEAN P L US ONE S TANDARD DEV IAT IO N
MEAN M INUS O NE S TANDARD DEV IAT IO N
SAMPLE 1
SAMPLE 2
SAMPLE 3
13405-136
Figure 136. Measured Long-Term Drift of the ADA4530-1 Offset Voltage over
10,000 Hours
TEMPERATURE HYSTERESIS
In addition to stability over time as described in the Long-Term
Drift section, it is useful to know the temperature hysteresis,
that is, the stability vs. cycling of temperature. Hysteresis is an
important parameter because it tells the system designer how
closely the signal returns to its starting amplitude after the
ambient temperature changes and subsequent return to room
temperature. Figure 137 shows the change in input offset
voltage as the temperature cycles three times from room
temperature to 125°C to −40°C and back to room temperature.
The dotted line is an initial preconditioning cycle to eliminate
the original temperature induced offset shift from exposure to
production solder reflow temperatures. In the three full cycles,
the offset hysteresis is typically only 1.5 µV. The histogram in
Figure 138 shows that the hysteresis is larger when the device is
cycled through only a half cycle, from room temperature to
125°C and back to room temperature.
TEMPERATURE (°C)
–40 –20 020 40 60 80 100 120
CHANGE IN OFFSET VOLTAGE (µV)
0
VSY = 10V
13405-137
-25
-20
-15
-10
-5
0
5
10
15
20
25 PRECONDITION
CYCL E 1
CYCL E 2
CYCL E 3
Figure 137. Change in Offset Voltage over Three Full Temperature Cycles
OFFSET VOLTAGE HYSTERESIS (µV)
NUMBER O F DEV ICES
13405-138
0
35
30
40
25
20
15
10
5
0
35
30
40
25
20
15
10
5
–12 –6–9 –3 0 3 6 9 12
HALF CYCLE
FULL CYCLE
V
SY
= 10V
27 UNITS × 3 CYCL ES
HALF CYCLE = + 26°C, + 1 25°C, +26°C
FULL CYCLE = +2 6° C, +125° C, + 26°C, –40°C, + 26°C
Figure 138. Histogram Showing the Temperature Hysteresis of the Offset
Voltage over Three Full Cycles and over Three Half Cycles
ADA4530-1 Data Sheet
Rev. B | Page 52 of 52
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONSARE IN M I LL IME TERS ; INCH DI M E NS IO NS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REF ERE NCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JE DE C S TANDARDS MS-012-AA
012407-A
0.25 ( 0.0098)
0.17 ( 0.0067)
1.27 ( 0.0500)
0.40 ( 0.0157)
0.50 ( 0.0196)
0.25 ( 0.0099) 45°
8°
0°
1.75 ( 0.0688)
1.35 ( 0.0532)
SEATING
PLANE
0.25 ( 0.0098)
0.10 ( 0.0040)
4
1
8 5
5.00 (0.1968)
4.80 (0.1890)
4.00 ( 0.1574)
3.80 ( 0.1497)
1.27 ( 0.0500)
BSC
6.20 ( 0.2441)
5.80 ( 0.2284)
0.51 ( 0.0201)
0.31 ( 0.0122)
COPLANARITY
0.10
Figure 139. 8-Lead Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADA4530-1ARZ −40°C to +125°C 8-Lead Small Outline Package [SOIC_N] R-8
ADA4530-1ARZ-R7 −40°C to +125°C 8-Lead Small Outline Package [SOIC_N] R-8
ADA4530-1ARZ-RL −40°C to +125°C 8-Lead Small Outline Package [SOIC_N] R-8
ADA4530-1R-EBZ-BUF Evaluation Board Buffer Configuration for 8-Lead SOIC
ADA4530-1R-EBZ-TIA Evaluation Board Transimpedance Configuration for 8-Lead SOIC
EVAL-CN0407-SDPZ Ultrahigh Sensitivity Femtoampere Measurement Platform
1 Z = RoHS Compliant Part.
©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13405-0-5/17(B)
