SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D2-V to 5.5-V VCC Operation
DSupport Mixed-Mode Voltage Operation on
All Ports
DHigh On-Off Output-Voltage Ratio
DLow Crosstalk Between Switches
DIndividual Switch Controls
DExtremely Low Input Current
DLatch-Up Performance Exceeds 250 mA Per
JESD 17
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
These triple 2-channel CMOS analog
multiplexers/demultiplexers are designed for 2-V
to 5.5-V VCC operation.
The ’LV4053A devices handle both analog and
digital signals. Each channel permits signals with
amplitudes up to 5.5 V (peak) to be transmitted in
either direction.
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and
digital-to-analog conversion systems.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N Tube of 25 SN74LV4053AN SN74LV4053AN
QFN − RGY Reel of 1000 SN74LV4053ARGYR LW053A
SOIC D
Tube of 40 SN74LV4053AD
LV4053A
SOIC − D Reel of 2500 SN74LV4053ADR LV4053A
40°Cto85°C
SOP − NS Reel of 2000 SN74LV4053ANSR 74LV4053A
−40°C to 85°CSSOP − DB Reel of 2000 SN74LV4053ADBR LW053A
Tube of 90 SN74LV4053APW
TSSOP − PW Reel of 2000 SN74LV4053APWR LW053A
TSSOP
PW
Reel of 250 SN74LV4053APWT
LW053A
TVSOP − DGV Reel of 2000 SN74LV4053ADGVR LW053A
55°C to 125°C
CDIP − J Tube of 25 SNJ54LV4053AJ SNJ54LV4053AJ
−55°C to 125°CCFP − W Tube of 150 SNJ54LV4053AW SNJ54LV4053AW
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright © 2005, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Y1
2Y0
3Y1
3-COM
3Y0
INH
GND
GND
VCC
2-COM
1-COM
1Y1
1Y0
A
B
C
SN54LV4053A ...J OR W PACKAGE
SN74LV4053A . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
SN74LV4053A . . . RGY PACKAGE
(TOP VIEW)
116
89
2
3
4
5
6
7
15
14
13
12
11
10
2-COM
1-COM
1Y1
1Y0
A
B
2Y0
3Y1
3-COM
3Y0
INH
GND
2Y1
CV
GND
CC
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
ON CHANNELS
INH C B A ON CHANNELS
L L L L 1Y0, 2Y0, 3Y0
LL L H 1Y1, 2Y0, 3Y0
LL H L 1Y0, 2Y1, 3Y0
LL H H 1Y1, 2Y1, 3Y0
LH L L 1Y0, 2Y0, 3Y1
LH L H 1Y1, 2Y0, 3Y1
LH H L 1Y0, 2Y1, 3Y1
LH H H 1Y1, 2Y1, 3Y1
H X X X None
logic diagram (positive logic)
1Y0
1Y1
2Y0
2Y1
3Y0
1-COM
INH
B
A
3-COM
3Y1
2-COM
C
11
10
9
6
15
14
12
13
2
1
5
3
4
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch I/O voltage range, VIO (see Notes 1 and 2) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O diode current, IIOK (VIO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch through current, IT (VIO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 4): RGY package 39°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 5)
SN54LV4053A SN74LV4053A
UNIT
MIN MAX MIN MAX UNIT
VCC Supply voltage 2‡5.5 2‡5.5 V
VCC = 2 V 1.5 1.5
V
High level input voltage control inputs
VCC = 2.3 V to 2.7 V VCC ×0.7 VCC ×0.7
V
VIH High-level input voltage, control inputs VCC = 3 V to 3.6 V VCC ×0.7 VCC ×0.7 V
VCC = 4.5 V to 5.5 V VCC ×0.7 VCC ×0.7
VCC = 2 V 0.5 0.5
V
Low level input voltage control inputs
VCC = 2.3 V to 2.7 V VCC ×0.3 VCC ×0.3
V
VIL Low-level input voltage, control inputs VCC = 3 V to 3.6 V VCC ×0.3 VCC ×0.3 V
VCC = 4.5 V to 5.5 V VCC ×0.3 VCC ×0.3
VIControl input voltage 0 5.5 0 5.5 V
VIO Input/output voltage 0 VCC 0 VCC V
VCC = 2.3 V to 2.7 V 200 200
Δt/ΔvInput transition rise or fall rate VCC = 3 V to 3.6 V 100 100 ns/V
Δt/Δv
Input
transition
rise
or
fall
rate
VCC = 4.5 V to 5.5 V 20 20
ns/V
TAOperating free-air temperature −55 125 −40 85 °C
‡With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals
be transmitted at these low supply voltages.
NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST
V
TA = 25°C SN54LV4053A SN74LV4053A
UNIT
PARAMETER
TEST
CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT
IT = 2 mA, 2.3 V 41 180 225 225
ron On-state
T,
VI = VCC or GND,
VINH =V
IL
3 V 30 150 190 190 Ω
on
sw
c
res
s
ance
V
INH =
V
IL
(see Figure 1) 4.5 V 23 75 100 100
IT
=
2 mA,
2.3 V 139 500 600 600
ron
(p)
Peak on-state resistance
I
T =
2
mA
,
VI = VCC to GND, 3 V 63 180 225 225 Ω
ron(p)
VI
VCC
to
GND,
VINH = VIL 4.5 V 35 100 125 125
Ω
IT
=
2 mA,
2.3 V 2 30 40 40
Δron
on-state resistance
I
T =
2
mA
,
VI = VCC to GND, 3 V 1.6 20 30 30 Ω
Δron
between switches
VI
VCC
to
GND,
VINH = VIL 4.5 V 1.3 15 20 20
Ω
IIControl input current VI = 5.5 V or GND 0 to
5.5 V ±0.1 ±1±1μA
IS(off)
Off-state
switch leakage current
VI = VCC and
VO = GND, or
VI = GND and
VO = VCC,
VINH = VIH
(see Figure 2)
5.5 V ±0.1 ±1±1μA
IS(on)
On-state
switch leakage current
VI = VCC or GND,
VINH = VIH
(see Figure 3)
5.5 V ±0.1 ±1±1μA
ICC Supply current VI = VCC or GND 5.5 V 20 20 μA
CIC Control input capacitance 2 pF
CIS
Common
terminal capacitance 8.2 pF
COS
Switch
terminal capacitance 5.6 pF
CFFeedthrough capacitance 0.5 pF
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ±0.2 V (unless otherwise noted)
PARAMETER
FROM TO TEST TA = 25°C SN54LV4053A SN74LV4053A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS MIN TYP MAX MIN MAX MIN MAX UNIT
tPLH
tPHL
Propagation
delay time COM or Yn Yn or COM CL = 15 pF
(see Figure 4) 2.5 10 16 16 ns
tPZH
tPZL
Enable
delay time INH COM or Yn CL = 15 pF
(see Figure 5) 7.6 18 23 23 ns
tPHZ
tPLZ
Disable
delay time INH COM or Yn CL = 15 pF
(see Figure 5) 7.7 18 23 23 ns
tPLH
tPHL
Propagation
delay time COM or Yn Yn or COM CL = 50 pF
(see Figure 4) 4.4 12 18 18 ns
tPZH
tPZL
Enable
delay time INH COM or Yn CL = 50 pF
(see Figure 5) 8.8 28 35 35 ns
tPHZ
tPLZ
Disable
delay time INH COM or Yn CL = 50 pF
(see Figure 5) 11.7 28 35 35 ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ±0.3 V (unless otherwise noted)
PARAMETER
FROM TO TEST TA = 25°C SN54LV4053A SN74LV4053A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS MIN TYP MAX MIN MAX MIN MAX UNIT
tPLH
tPHL
Propagation
delay time COM or Yn Yn or COM CL = 15 pF
(see Figure 4) 1.6 6 10 10 ns
tPZH
tPZL
Enable
delay time INH COM or Yn CL = 15 pF
(see Figure 5) 5.3 12 15 15 ns
tPHZ
tPLZ
Disable
delay time INH COM or Yn CL = 15 pF
(see Figure 5) 6.1 12 15 15 ns
tPLH
tPHL
Propagation
delay time COM or Yn Yn or COM CL = 50 pF
(see Figure 4) 2.9 9 12 12 ns
tPZH
tPZL
Enable
delay time INH COM or Yn CL = 50 pF
(see Figure 5) 6.1 20 25 25 ns
tPHZ
tPLZ
Disable
delay time INH COM or Yn CL = 50 pF
(see Figure 5) 8.9 20 25 25 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ±0.5 V (unless otherwise noted)
PARAMETER
FROM TO TEST TA = 25°C SN54LV4053A SN74LV4053A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS MIN TYP MAX MIN MAX MIN MAX UNIT
tPLH
tPHL
Propagation
delay time COM or Yn Yn or COM CL = 15 pF
(see Figure 4) 0.9 4 7 7 ns
tPZH
tPZL
Enable delay
time INH COM or Yn CL = 15 pF
(see Figure 5) 3.8 8 10 10 ns
tPHZ
tPLZ
Disable
delay time INH COM or Yn CL = 15 pF
(see Figure 5) 4.6 8 10 10 ns
tPLH
tPHL
Propagation
delay time COM or Yn Yn or COM CL = 50 pF
(see Figure 4) 1.8 6 8 8 ns
tPZH
tPZL
Enable delay
time INH COM or Yn CL = 50 pF
(see Figure 5) 4.3 14 18 18 ns
tPHZ
tPLZ
Disable
delay time INH COM or Yn CL = 50 pF
(see Figure 5) 6.3 14 18 18 ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
analog switch characteristics
PARAMETER
FROM TO
TEST CONDITIONS
V
TA = 25°C
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) TEST CONDITIONS VCC TYP UNIT
CL = 50 pF, 2.3 V 30
Frequency response
(switch on)
COM or Yn Yn or COM
Lp,
RL = 600 Ω,
fi= 1 MHz (sine wave)
3 V 35 MHz
(
sw
it
c
h
on
)
f
in =
1
MH
z
(
s
i
ne wave
)
(see Note 6 and Figure 6) 4.5 V 50
CL = 50 pF, 2.3 V −45
Crosstalk
(between any switches)
COM or Yn Yn or COM
CL50 p ,
RL = 600 Ω,
fin = 1 MHz (sine wave)
3 V −45 dB
(between
any
switches)
f
in =
1
MH
z
(
s
i
ne wave
)
(see Note 7 and Figure 7) 4.5 V −45
CL = 50 pF, 2.3 V 20
Crosstalk
(control input to signal output)
INH COM or Yn
CL50 p ,
RL = 600 Ω,
fin = 1 MHz (square wave)
3 V 35 mV
(control
input
to
signal
output)
f
in =
1
MH
z
(
square wave
)
(see Figure 8) 4.5 V 65
CL = 50 pF, 2.3 V −45
Feedthrough attenuation
(switch off)
COM or Yn Yn or COM
CL50 p ,
RL = 600 Ω,
fin = 1 MHz
3 V −45 dB
(switch
off)
f
in =
1
MH
z
(see Note 7 and Figure 9) 4.5 V −45
CL = 50 pF,
RL=10kΩ
VI = 2 Vp-p 2.3 V 0.1
Sine-wave distortion COM or Yn Yn or COM
RL = 10 kΩ,
fin = 1 kHz
(i )
VI = 2.5 Vp-p 3 V 0.1 %
(sine wave)
(see Figure 10) VI = 4 Vp-p 4.5 V 0.1
NOTES: 6. Adjust fin voltage to obtain 0-dBm output. Increase fin frequency until dB meter reads −3 dB.
7. Adjust fin voltage to obtain 0-dBm input.
operating characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance CL = 50 pF, f = 10 MHz 5.3 pF
PARAMETER MEASUREMENT INFORMATION
VCC
VI = VCC or GND
VINH = VIL
2 mA
VO
ron +
VI–V
O
2 10–3 W
VI − VO
VCC
GND
(ON)
V
Figure 1. On-State Resistance Test Circuit
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VINH = VIH
VIVO
Condition 1: VI = 0, VO = VCC
Condition 2: VI = VCC, VO = 0
A
VCC
VCC
GND
(OFF)
Figure 2. Off-State Switch Leakage-Current Test Circuit
VCC
VINH = VIL
VIOpen
VCC
GND
(ON)
A
VI = VCC or GND
Figure 3. On-State Switch Leakage-Current Test Circuit
VCC
VINH = VIL
Input Output
CL
50 Ω
VCC
GND
(ON)
Figure 4. Propagation Delay Time, Signal Input to Signal Output
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CL
VCC
VO
TEST CIRCUIT
VOLTAGE WAVEFORMS
1 kΩ
S1 S2
tPLZ/tPZL
tPHZ/tPZH
GND
VCC
TEST S1 S2
VCC
GND
VINH
50 Ω
50%
VOL + 0.3 V
tPZH
tPHZ
50%
50%
50%
tPZL
50%
VCC
VO50%
0 V
VOL
VINH
(tPZL, tPZH)
(tPLZ, tPHZ)
VCC
VO
0 V
VOL
VINH
VCC
0 V
VOH
VCC
0 V
≈0 V
VOH VOH − 0.3 V
≈0 V
≈VCC
≈VCC
GND
VCC
VI
tPLZ
Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output
VO
RLCL
VCC
50 Ω
fin
VINH = GND
0.1 μF
VCC
GND
(ON)
NOTE A: fin is a sine wave.
VCC/2
Figure 6. Frequency Response (Switch On)
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VO1
RLCL
VCC
50 Ω
fin
VCC/2
VINH = GND
0.1 μF
VO2
VCC
VCC/2
VINH = VCC
600 Ω
VCC
GND
(ON)
VCC
GND
(OFF)
RLCL
600 Ω
fin
Figure 7. Crosstalk Between Any Two Switches
VO
VCC
VCC
GND RLCL
VCC/2 VCC/2
50 Ω
VINH
600 Ω
Figure 8. Crosstalk Between Control Input and Switch Output
VO
RLCL
VCC
VCC/2
VINH = VCC
0.1 μF
fin
VCC/2
600 Ω
50 Ω
VCC
GND
(OFF)
Figure 9. Feedthrough Attenuation (Switch Off)
SN54LV4053A, SN74LV4053A
TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
SCLS430K − MAY 1999 − REVISED APRIL 2005
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VO
RLCL
VCC
VCC/2
VINH = GND
10 μF
fin
VCC
GND
(ON)
600 Ω
10 μF
Figure 10. Sine-Wave Distortion
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LV4053AD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053ADBR ACTIVE SSOP DB 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053ADBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053ADBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053ADE4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053ADG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053ADGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053ADR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053AN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74LV4053ANE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74LV4053ANSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053APW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053APWE4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053APWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053APWT ACTIVE TSSOP PW 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 21-Dec-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LV4053APWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LV4053ARGYR ACTIVE VQFN RGY 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LV4053ARGYRG4 ACTIVE VQFN RGY 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV4053A :
•Automotive: SN74LV4053A-Q1
•Enhanced Product: SN74LV4053A-EP
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 21-Dec-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LV4053ADBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LV4053ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74LV4053ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LV4053APWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
SN74LV4053APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV4053APWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV4053APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV4053ARGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV4053ADBR SSOP DB 16 2000 367.0 367.0 38.0
SN74LV4053ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0
SN74LV4053ANSR SO NS 16 2000 367.0 367.0 38.0
SN74LV4053APWR TSSOP PW 16 2000 364.0 364.0 27.0
SN74LV4053APWR TSSOP PW 16 2000 367.0 367.0 35.0
SN74LV4053APWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
SN74LV4053APWT TSSOP PW 16 250 367.0 367.0 35.0
SN74LV4053ARGYR VQFN RGY 16 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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