Features
Performance speci ed for common IPM applications
over automotive temperature range: -40°C to 125°C
Fast maximum propagation delays
- tPHL & tPLH = 550 ns
Minimized Pulse Width Distortion (PWD = 370 ns)
Very high Common Mode Rejection (CMR):
15 kV/µs at VCM = 1500 V
CTR > 44% at IF = 10 mA
Quali ed to AEC-Q100 Test Guidelines
Safety approval
- UL recognized per UL1577 ( le no. E55361)
4000 Vrms for 1 minute
- IEC/EN/DIN EN 60747-5-2 Approved
- CSA Approved
Applications
Automotive IPM isolation for battery management
system and motor control
Isolated IGBT/MOSFET gate drive
AC and brushless dc motor drives
Industrial inverters for power supplies and motor
controls
The connection of a 0.1 µF bypass capacitor between pins 4 and 6 is
recommended.
Truth Table
LED VO
ON L
OFF H
Description
The ACPL-M46T consists of a AlGaAs optically coupled
to an integrated high gain photo detector. Minimized
propagation delay di erence between devices make
these optocouplers excellent solutions for improving au-
tomotive inverter e ciency through reduced switching
dead time.
Speci cation and performance plots are given for typical
IPM applications.
Avago R2Coupler isolation products provide the rein-
forced insulation and reliability needed for critical in au-
tomotive and high temperature industrial applications.
Schematic Diagram
ACPL-M46T
Automotive Intelligent Power Module
with R2Coupler™ Isolation and Small Outline, 5 Lead Package
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
6
5
4
1
3SHIELD
VCC
VOUT
GND
CATHODE
ANODE
2
2
Ordering Information
Part Number
Option
Package
Surface
Mount
Tape &
Reel
IEC/EN/DIN EN
60747-5-2 Quantity(RoHS) Compliant
ACPL-M46T -000E SO-5 X 100 per tube
-060E X X 100 per tube
-500E X X 1500 per reel
-560E X X X 1500 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-M46T-500E to order product of SO-5 Surface Mount package in Tape and Reel packaging with RoHS
compliant.
Example 2:
ACPL-M46T-000E to order product of SO-5 Surface Mount package in tube packaging with RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Package Outline Drawing
ACPL-M46T-000E Small Outline SO-5 Package (JEDEC MO-155)
M46T
YWW
EE
7.0 ± 0.2
(0.276 ± 0.008)
2.5 ± 0.1
(0.098 ± 0.004)
0.102 ± 0.102
(0.004 ± 0.004)
4.4 ± 0.1
(0.173 ± 0.004)
1.27
(0.050)BSC
0.20 ± 0.025
(0.008 ± 0.001)
0.71
(0.028) MIN
0.4 ± 0.05
(0.016 ± 0.002)
3.6 ± 0.1*
(0.142 ± 0.004)
DIMENSIONS IN MILLIMETERS (INCHES)
* MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006)
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
Extended
Datecode
for lot tracking
7° MAX.
MAX. LEAD COPLANARITY
= 0.102 (0.004)
8.27
(0.325)
2.0
(0.080)
2.5
(0.10)
1.3
(0.05)
0.64
(0.025)
4.4
(0.17)
DIMENSION IN MILLIMETERS (INCHES)
Land Pattern Recommendation
3
Recommended Pb-Free IR Pro le
Recommended re ow condition as per JEDEC Standard, J-STD-020 (latest revision).
Note: Non-halide ux should be used
Regulatory Information
The ACPL-M46T is approved by the following organizations:
UL
Approved under UL 1577, component recognition pro-
gram up to VISO = 4000 VRMS
CSA
Approved under CSA Component Acceptance Notice
#5.
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:2007
EN 60747-5-2:2001 + A1
DIN EN 60747-5-2 (VDE 0884 Teil 2)
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*
Description Symbol Characteristic Unit
Installation classi cation per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
I – IV
I – III
I – II
Climatic Classi cation 55/125/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 567 Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC
VPR 1063 Vpeak
Input to Output Test Voltage, Method a*
VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC
VPR 907 Vpeak
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 6000 Vpeak
Safety-limiting values – maximum values allowed in the event of a failure.
Case Temperature
Input Current
Output Power
TS
IS, INPUT
PS, OUTPUT
175
230
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V RS>109 W
* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/
EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test pro les.
4
Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Power Supply Voltage VCC 4.5 30 Volts
Output Voltage VO 0 30 Volts
Input Current (ON) IF(on) 10 20 mA
Input Voltage (OFF) VF(o ) -5 0.8 V
Operating Temperature TA -40 125 °C
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units
Storage Temperature TS -55 150 °C
Operating Temperature TA -40 125 °C
Average Input Current IF(avg) 20 mA
Peak Input Current IF(peak) 40 mA
(50% duty cycle, <1 ms pulse width)
Peak Transient Input Current IF(tran) 1.0 A
(<1 µs pulse width, 300 pps)
Reverse Input Voltage (Pin 3-1) VR 5 Volts
Average Output Current (Pin 5) IO(avg) 15 mA
Output Voltage (Pin 5-4) VO -0.5 30 Volts
Supply Voltage (Pin 6-4) VCC -0.5 30 Volts
Output Power Dissipation PO 100 mW
Total Power Dissipation PT 130 mW
Infrared and Vapor Phase Re ow Temperature See Re ow Thermal Pro le below.
Insulation Related Speci cations
Parameter Symbol Value Units Conditions
Minimum External Air Gap L(101) ≥5 mm Measured from input terminals to output
(Clearance) terminals, shortest distance through air.
Minimum External Tracking L(102) ≥5 mm Measured from input terminals to output
(Creepage) terminals, shortest distance path along body.
Minimum Internal Plastic Gap 0.08 mm Through insulation distance conductor to
(Internal Clearance) conductor, usually the straight line distance
thickness between the emitter and detector.
Tracking Resistance CTI 200 Volts DIN IEC 112/VDE 0303 Part 1
(ComparativeTracking Index)
Isolation Group IIIa Material Group (DIN VDE 0110)
5
Electrical Speci cations
Over recommended operating conditions unless otherwise speci ed:
TA = -40°C to +125°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(o ) = -5 V to 0.8 V
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Current Transfer Ratio CTR 44 90 % IF = 10 mA, VO = 0.6 V 1
Low Level Output IOL 4.4 9.0 mA IF = 10 mA, VO = 0.6 V 2,3
Current
Low Level Output Voltage VOL 0.3 0.6 V IO = 2.4 mA
Input Threshold Current ITH 1.5 5.0 mA VO = 0.8 V, IO = 0.75 mA 2 4
High Level Output IOH 5 50 µA VF = 0.8 V 4
Current
High Level Supply Current ICCH 0.6 1.3 mA VF = 0.8 V, VO = Open 4
Low Level Supply Current ICCL 0.6 1.3 mA IF = 10 mA, VO = Open 4
Input Forward Voltage VF 1.45 1.5 1.75 V TA = 25°C , IF = 10 mA 5
1.25 1.5 1.85 V IF = 10 mA
Temperature Coe cient ∆VF/∆TA -1.5 mV/°C IF = 10 mA
of Forward Voltage
Input Reverse Breakdown BVR 5 V IR = 10 µA
Voltage
Input Capacitance CIN 90 pF f = 1 MHz, VF = 0 V
Input-Output VISO 4000 VRMS RH < 50%, t = 1 min, 2, 3
Insulation Voltage TA = 25°C
Resistance (Input - Output) RI-O 1014 Ω VI-O = 500 Vdc 6
Capacitance CI-O 0.6 pF f = 1 MHz 6
(Input - Output)
*All typical values at 25°C, VCC = 15 V.
6
Switching Speci cations (RL= 20 kΩ)
Over recommended operating conditions unless otherwise speci ed:
TA = -40°C to +125°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(o ) = -5 V to 0.8 V
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Propagation Delay tPHL I
F(on) = 10 mA, 6, 4, 5
Time to Low VF(o ) = 0.8 V, 8-12
Output Level
Propagation Delay tPLH
Time to High
Output Level
Pulse Width PWD 200 450 ns CL = 100 pF 9
Distortion
Propagation Delay tPLH-tPHL -150 200 450 ns 6
Di erence Between
Any 2 Parts
Output High Level |CMH| 15 30 kV/µs IF = 0 mA, VCC = 15.0 V, 7 7
Common Mode VO > 11.0 V CL = 100 pF,
Transient Immunity VCM = 1500 V
P-P,
Output Low Level |CML| 15 30 kV/µs IF = 10 mA, 8
Common Mode VO < 1.0 V
Transient Immunity
*All typical values at 25°C, VCC = 15 V.
TA = 25°C
VCC = 15.0 V,
VTHLH = 2.0 V,
VTHHL = 1.5 V
130 CL = 10 pF
30 200 550 ns CL = 100 pF
100 ns CL = 10 pF
270 400 550 ns CL = 100 pF
Notes:
1. CURRENT TRANSFER RATIO in per cent is de ned as the ratio of output collector current (IO) to the forward LED input current (IF) times 100.
2. Device considered a two-terminal device: Pins 1 and 3 shorted together and Pins 4, 5 and 6 shorted together.
3. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4800 VRMS for 1 second.
4. Pulse: f = 20 kHz, Duty Cycle = 10%.
5. Use of a 0.1 µF bypass capacitor connected between pins 4 and 6 can improve performance by ltering power supply line noise.
6. The di erence between tPLH and tPHL between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay
Speci cations section.)
7. Common mode transient immunity in a Logic High level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a Logic High state (i.e., VO > 11.0 V).
8. Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a Logic Low state (i.e., VO < 1.0 V).
9. Pulse Width Distortion (PWD) is de ned as |tPHL - tPLH| for any given device.
7
LED Drive Circuit Considerations For Ultra High CMR
Performance
Without a detector shield, the dominant cause of op-
tocoupler CMR failure is capacitive coupling from the
input side of the optocoupler, through the package, to
the detector IC as shown in Figure 14. The ACPL-M46T
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts
the capacitively coupled current away from the sensitive
IC circuitry. However, this shield does not eliminate the
capacitive coupling between the LED and the optocou-
pler output pin and output ground as shown in Figure
15. This capacitive coupling causes perturbations in the
LED current during common mode transients and be-
comes the major source of CMR failures for a shielded
optocoupler. The main design objective of a high CMR
LED drive circuit becomes keeping the LED in the proper
state (on or o ) during common mode transients. For ex-
ample, the recommended application circuit (Figure 13),
can achieve 15 kV/s CMR while minimizing component
complexity. Note that a CMOS gate is recommended in
Figure 13 to keep the LED o when the gate is in the high
state.
Another cause of CMR failure for a shielded optocoupler
is direct coupling to the optocoupler output pins through
CLEDO1 in Figure 15. Many factors in uence the e ect and
magnitude of the direct coupling including: the position
of the LED current setting resistor and the value of the
capacitor at the optocoupler output (CL).
Techniques to keep the LED in the proper state and mini-
mize the e ect of the direct coupling are discussed in the
next two sections.
CMR with the LED on (CMRL)
A high CMR LED drive circuit must keep the LED on dur-
ing common mode transients. This is achieved by over-
driving the LED current beyond the input threshold so
that it is not pulled below the threshold during a tran-
sient. The recommended minimum LED current of 10 mA
provides adequate margin over the maximum ITH of 4.0
mA (see Figure 2) to achieve 15 kV/s CMR.
The placement of the LED current setting resistor e ects
the ability of the drive circuit to keep the LED on dur-
ing transients and interacts with the direct coupling to
the optocoupler output. For example, the LED resistor in
Figure 16 is connected to the anode. Figure 17 shows the
AC equivalent circuit for Figure 16 during common mode
transients. During a +dVCM/dt in Figure 17, the current
available at the LED anode (Itotal) is limited by the series
resistor. The LED current (IF) is reduced from its DC value
by an amount equal to the current that ows through
CLEDP and CLEDO1. The situation is made worse because the
current through CLEDO1 has the e ect of trying to pull the
output high (toward a CMR failure) at the same time the
LED current is being reduced. For this reason, the recom-
mended LED drive circuit (Figure 13) places the current
setting resistor in series with the LED cathode. Figure 18
is the AC equivalent circuit for Figure 13 during common
mode transients. In this case, the LED current is not re-
duced during a +dVCM/dt transient because the current
owing through the package capacitance is supplied by
the power supply. During a dVCM/dt transient, however,
the LED current is reduced by the amount of current
owing through CLEDN. But, better CMR performance
is achieved since the current owing in CLEDO1 during a
negative transient acts to keep the output low.
CMR with the LED O (CMRH)
A high CMR LED drive circuit must keep the LED o (VF
≤ VF(OFF)) during common mode transients. For example,
during a +dVCM/dt transient in Figure 18, the current
owing through CLEDN is supplied by the parallel combi-
nation of the LED and series resistor. As long as the volt-
age developed across the resistor is less than VF(OFF) the
LED will remain o and no common mode failure will oc-
cur. Even if the LED momentarily turns on, the 100 pF ca-
pacitor from pins 5-4 will keep the output from dipping
below the threshold. The recommended LED drive cir-
cuit (Figure 13) provides about 10 V of margin between
the lowest optocoupler output voltage and a 3 V IPM
threshold during a 15kV/s transient with VCM = 1500 V.
Additional margin can be obtained by adding a diode
in parallel with the resistor, as shown by the dashed line
connection in Figure 18, to clamp the voltage across the
LED below VF(OFF).
Since the open collector drive circuit, shown in Figure 19,
cannot keep the LED o during a +dVCM/dt transient, it is
not desirable for applications requiring ultra high CMRH
performance. Figure 20 is the AC equivalent circuit for
Figure 19 during common mode transients. Essentially
all the current owing through CLEDN during a +dVCM/
dt transient must be supplied by the LED. CMRH failures
can occur at dv/dt rates where the current through the
LED and CLEDN exceeds the input threshold. Figure 21 is
an alternative drive circuit which does achieve ultra high
CMR performance by shunting the LED in the o state.
8
0.80
0.85
0.90
0.95
1.00
1.05
-40 -20 0 20 40 60 80 100 120 140
TA - TEMPERATURE - °C
NORMALIZED OUTPUT CURRENT
0
2
4
6
8
10
12
0 5 10 15 20
IO - OUTPUT CURRENT - mA
IF - FORWARD CURRENT - mA
25°C
125°C
-40°C
VO =0.6V IF = 10mA
VO = 0.6V
Figure 2. Typical Transfer Characteristics. Figure 3. Normalized Output Current vs. Temperature.
IPM Dead Time and Propagation Delay Speci cations
The ACPL-M46T includes a Propagation Delay Di erence
speci cation intended to help designers minimize “dead
time” in their power inverter designs. Dead time is the
time period during which both the high and low side
power transistors (Q1 and Q2 in Figure 22) are o . Any
overlap in Q1 and Q2 conduction will result in large cur-
rents owing through the power devices between the
high and low voltage motor rails.
To minimize dead time the designer must consider the
propagation delay characteristics of the optocoupler as
well as the characteristics of the IPM IGBT gate drive cir-
cuit. Considering only the delay characteristics of the op-
tocoupler (the characteristics of the IPM IGBT gate drive
circuit can be analyzed in the same way) it is important
to know the minimum and maximum turn-on (tPHL) and
turn-o (tPLH) propagation delay speci cations, prefer-
ably over the desired operating temperature range.
The limiting case of zero dead time occurs when the in-
put to Q1 turns o at the same time that the input to Q2
turns on. This case determines the minimum delay be-
tween LED1 turn-o and LED turn-on, which is related
to the worst case optocoupler propagation delay wave-
forms, as shown in Figure 23. A minimum dead time of
zero is achieved in Figure 23 when the signal to turn on
LED is delayed by (tPLH max - tPHL min) from the LED1 turn
o . Note that the propagation delays used to calculate
PDD are taken at equal temperatures since the optocou-
plers under consideration are typically mounted in close
proximity to each other. (Speci cally, tPLH max and tPHL min
in the previous equation are not the same as the tPLH max
and tPHL min, over the full operating temperature range,
speci ed in the data sheet.) This delay is the maximum
value for the propagation delay di erence speci cation
which is speci ed at 370 ns for the ACPL-M46T over an
operating temperature range of -40°C to 125°C.
Delaying the LED signal by the maximum propagation
delay di erence ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time occurs in
the highly unlikely case where one optocoupler with
the fastest tPLH and another with the slowest tPHL are in
the same inverter leg. The maximum dead time in this
case becomes the sum of the spread in the tPLH and tPHL
propagation delays as shown in Figure 24. The maximum
dead time is also equivalent to the di erence between
the maximum and minimum propagation delay di er-
ence speci cations. The maximum dead time (due to the
optocouplers) for the ACPL-M46T is 520 ns (= 370 ns -
(-150 ns)) over an operating temperature range of -40°C
to 125°C.
9
0.1 µF
V
CC
= 15 V
20 kΩ
6
5
4
1
3SHIELD
I
F(ON)
=10 mA
V
OUT
C
L
*
+
–
*TOTAL LOAD
CAPACITANCE
+
–
I
f
V
O
V
THHL
t
PHL
t
PLH
t
f
t
r
90%
10%
90%
10%
V
THLH
Figure 5. Input Current vs. Forward Voltage.
Figure 7. CMR Test Circuit.
Figure 6. Propagation Delay Test Circuit.
Typical CMR Waveform.
0.1 µF V
CC
=15 V
20 kΩ
6
5
4
1
3SHIELD
A
I
F
V
OUT
100 pF*
+
–
*100 pF TOTAL
CAPACITANCE
+
–
+
–
B
V
FF
V
CM
= 1500 V
VCM
Δt
OV
VO
VO
SWITCH AT A: I
F
= 0 mA
SWITCH AT B: I
F
= 10 mA
VCC
VOL
VCM
Δt
δV
δt=
Figure 4. High Level Output Current vs. Temperature.
IF
VF
+
–
0.00
0.50
1.00
1.50
2.00
-40 -20 0 20 40 60 80 100 120 140
TA - TEMPERATURE - °C
IOH - HIGH LEVEL OUTPUT CURRENT - uA
VF=0.8V
VCC = VO = 30V
0.01
0.10
1.00
10.00
100.00
1.20 1.30 1.40 1.50 1.60
VF - FORWARD VOLTAGE - VOLTS
I
F
- FORWARD CURRENT - mA
TA = 25°C
10
t
P
– PROPAGATION DELAY – ns
RL – LOAD RESISTANCE – KΩ
600
400
200
30 50
800
01020 40
t
P
– PROPAGATION DELAY – n
CL – LOAD CAPACITANCE – pF
t
P
– PROPAGATION DELAY – ns
VCC – SUPPLY VOLTAGE – V
0
100
200
300
400
500
-40 -20 0 20 40 60 80 100 120 140
TA - TEMPERATURE - °C
T
P
- PROPOGATION DELAY - ns
tPLH
tPHL
0
100
200
300
400
500
5101520
IF - LED FORWARD CURRENT - mA
T
P
- PROPAGATION DELAY - ns
VCC = 15V CL = 100pF
RL = 20kΩ TA = 25°C
tPLH
tPHL
I
F
= 10mA V
CC
= 15V
C
L
= 100pF R
L
= 20kΩ
IF = 10 mA
VCC = 15 V
CL = 100 pF
TA = 25 °C
tPLH
tPHL
0
200
400
600
800
1000
1200
0 100 200 300 400 500
IF = 10 mA
VCC = 15 V
RL = 20 KΩ
TA = 25 °C
tPLH
tPHL
0
200
400
600
800
1000
1200
51015202530
IF = 10 mA
CL = 100 pF
RL = 20 kΩ
TA = 25 °C
tPLH
tPHL
Figure 8. Propagation Delay with External 20 kΩ RL vs. Temperature. Figure 9. Propagation Delay vs. Load Resistance.
Figure 10. Propagation Delay vs. Load Capacitance.
Figure 12. Propagation Delay vs. Input Current.
Figure 11. Propagation Delay vs. Supply Voltage.
11
0.1 μFVCC
=15 V
20 kΩ
6
5
4
1
3SHIELD
CMOS
310 W
+5 V
VOUT
100 pF
+
–
*100 pF TOTAL
CAPACITANCE
6
5
4
1
3
CLEDP
CLEDN
6
5
4
1
3
CLEDP
CLEDN SHIELD
CLED01 0.1 μFVCC
=15 V
20 kΩ
6
5
4
1
3SHIELD
CMOS
310 Ω
+5 V
VOUT
100 pF
+
–
*100 pF TOTAL
CAPACITANCE
20 kΩ
6
5
4
1
3
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
300 Ω
VOUT
100 pF
ICLEDP
CLEDN SHIELD
CLED01
+
–
ITOTAL*
ICLED01
IF
VCM
20 kΩ
6
5
4
1
3
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH
PERFORMANCE. VR < VF (OFF) DURING +dVCM/dt.
VOUT
100 pF
CLEDP
CLEDN
SHIELD
CLED01
+
–
ICLEDN*
300 Ω
+ VR** –
VCM
Figure 14. Optocoupler Input to Output Capacitance Model for Unshielded
Optocouplers.
Figure 13. Recommended LED Drive Circuit.
Figure 17. AC Equivalent Circuit for Figure 16 during Common Mode
Transients.
Figure 18. AC Equivalent Circuit for Figure 13 during Common Mode
Transients.
Figure 15. Optocoupler Input to Output Capacitance Model for Shielded
Optocouplers.
Figure 16. LED Drive Circuit with Resistor Connected to LED Anode (Not
Recommended).
12
6
5
4
1
3
SHIELD
Q1
+5 V
6
5
4
1
3
SHIELD
+5 V
0.1 μF20 kΩ
6
5
4
1
3SHIELD
CMOS
310 Ω
+5 V
VOUT1
ACPL-M46T
ILED1 VCC1
0.1 μF20 kΩ
6
5
4
1
3SHIELD
CMOS
310 Ω
+5 V
VOUT2
ACPL-M46T
ILED2 VCC2
M
Q2
Q1
-HV
+HV
IPM
ACPL-M46T
ACPL-M46T
ACPL-M46T
ACPL-M46T
ACPL-M46T
20 kΩ
6
5
4
1
3
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
VOUT
100 pF
CLEDP
CLEDN
SHIELD
CLED01
+
–
ICLEDN*
Q1
VCM
Figure 21. Recommended LED Drive Circuit for Ultra High CMR.
Figure 19. Not Recommended Open Collector LED Drive Circuit. Figure 20. AC Equivalent Circuit for Figure 19 during Common Mode
Transients.
Figure 22. Typical Application Circuit.
Figure 23. Minimum LED Skew for Zero Dead Time.
Figure 24. Waveforms for Deadtime Calculation.
V
OUT1
V
OUT2
I
LED2
t
PLH MAX.
PDD* MAX. =
(t
PLH-
t
PHL) MAX. =
t
PLH MAX. -
t
PHL MIN.
t
PHL
MIN.
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE
PDD ARE TAKEN AT EQUAL TEMPERATURES.
VOUT1
VOUT2
ILED2 tPLH
MIN.
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
= (tPLH MAX. - tPLH MIN.) + (tPHL MAX. - tPHL MIN.)
= (tPLH MAX. - tPHL MIN.) - (tPLH MIN. - tPHL MAX.)
= PDD* MAX. - PDD* MIN.
tPHL
MIN.
ILED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
*PDD = PROPAGATION DELAY DIFFERENCE
tPLH
MAX.
tPHL
MAX.
PDD*
MAX.
MAX.
DEAD TIME
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, the A logo and R2Coupler™ are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. Obsoletes 5989-2118EN
AV02-0822EN - December 1, 2011
