935284881151 - NXP SEMICONDUCTORS

1. General description

The LPC2194 is based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and

embedded trace support, together with 256 kB of embedded high-speed flash memory. A

128-bit wide memory interface and a unique accelerator architecture enable 32-bit code

execution at maximum clock rate. For critical code size application s, the alte rnative 16-bit

Thumb mode reduces code by more than 30 % with minimal performance penalty.

With its compact 64-pin package, low power consumption, various 32-bit timers,

4-channel 10-bit ADC, four advanced CAN channels, PWM channels and 46 fast GPIO

lines with up to nine external interrupt pins this microcontroller is particularly suitable for

automotive applications such as a CAN gateway that connects several CAN busses or a

CAN bridge between sub networks at different speeds. Sensors with CAN interface or

debugging via CAN are additional applica tions that need more than two CAN interfaces. It

is also an adequate solution for industrial control, medical systems and fault-tolerant

maintenance buses. With a wide ran ge of additional serial communication s interfaces, it is

also suited for comm un ica tio n ga te wa ys an d protocol convert er s as we ll as man y ot he r

general-purpose applications.

Remark: Throughout the data sheet, the term LPC2194 will apply to devices with and

without the /00 or /01 suffixes. The /00 or the /01 suffix will be used to differentiate from

other devices only wh en nec es sar y.

2. Features and benefits

2.1 Key features brought by LPC2194/01 devices

Fast GPIO port s enable port pin toggling u p to 3.5 times faster than the original device.

They also allow for a port pin to be read at any time regardless of its function.

Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are

5 V tolerant when configured for digital I/O function(s).

UART0/1 include fractional baud rate generat or, auto-bauding capabilities and

handshake flow-control fully implemented in hardware.

Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.

SPI programmable data length and master mode enhancement.

Diversified Code Read Protection (CRP) enables different security levels to be

implemented. This feature is available in LPC2194/00 devices as well.

General purpose timers can operate as external event counters.

LPC2194

Single-chip 16/32-bit microcontroller; 256 kB ISP/IAP flash

with 10-bit ADC and CAN

Rev. 6 — 14 June 2011 Product data sheet

Product data sheet Rev. 6 — 14 June 2011 2 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

2.2 Key features common for all devices

16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

16 kB on-chip SRAM and 256 kB on-chip flash program memory. 128-bit wide

interface/accelerator enables high speed 60 MHz operation.

In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or

full chip erase takes 400 ms.

EmbeddedICE-RT and Embedded Trace interfaces offer re al-time debugging with

on-chip RealMonitor software as well as high speed real-time tracing of instruction

execution.

Four interconne cted CAN interfaces with advanced accept ance filters. Additional serial

interfaces are two UARTs (16C550), Fast I2C-bus (400 kbit/s) and two SPIs.

Four channel 10-bit ADC with conversion time as low as 2.44 s.

Two 32-bit timers (with four capture and four compare channels), PWM unit (six

outputs), Real-Time Cloc k and Watchdog.

Vectored Interrupt Controller with configurable priorities and ve cto r ad dresses.

Up to forty-six 5 V tolerant gene ral purpose I/O pin s. Up to nin e edge or level se nsitive

external interrupt pins available.

Operating temperature range from 40 C to +125 C.

60 MHz maximum CPU clock available from programmable on-chip Phase-Locked

Loop with settling time of 100 s.

On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.

Two low power mod es , Idle and Power-down.

Processor wake-up from Power-down mode via external interrupt.

Individual enable/disable of peripheral functions for power optimization.

Dual power suppl y:

CPU operating voltage range of 1.65 V to 1.95 V (1.8 V  0.15 V).

I/O power supply range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads.

3. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

LPC2194HBD64 LQFP64 plastic low profile quad flat package; 64 leads;

body 10 10 1.4 mm SOT314-2

LPC2194HBD64/00 LQFP64 plastic low profile quad flat package; 64 leads;

body 10 10 1.4 mm SOT314-2

LPC2194HBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

body 10 10 1.4 mm SOT314-2

Product data sheet Rev. 6 — 14 June 2011 3 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

4. Block diagram

(1) Shared with GPIO.

(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.

(3) SSP interface and high-speed GPIO are available on LPC2194/01 only.

Fig 1. Block diagram

SCL(1)

P0[30:27],

P0[25:0]

TRST(2)

TMS(2)

TCK(2)

TDI(2)

TDO(2) XTAL2

XTAL1

EINT[3:0](1)

AIN[3:0](1)

AHB BRIDGE

PLL

PWM0

ARM7TDMI-S

LPC2194

RESET

4 × CAP0(1)

4 × CAP1(1)

4 × MAT0(1)

TD[4:1](1)

RD[4:1](1)

4 × MAT1(1)

P1[31:16]

SDA(1)

DSR1(1), CTS1(1),

RTS1(1), DTR1(1),

DCD1(1), RI1(1)

RTCK

ARM7 LOCAL BUS

INTERNAL

SRAM

CONTROLLER

INTERNAL

FLASH

CONTROLLER

16 kB

SRAM 256 kB

FLASH

EXTERNAL

INTERRUPTS

CAPTURE/

COMPARE

TIMER 0/TIMER 1

A/D CONVERTER

GENERAL

PURPOSE I/O

CAN INTERFACE 1, 2, 3 AND 4

ACCEPTANCE FILTERS

TEST/DEBUG

INTERFACE

EMULATION

TRACE MODULE

AMBA Advanced High-performance

Bus (AHB)

system

clock

SYSTEM

FUNCTIONS

VECTORED

INTERRUPT

CONTROLLER

AHB

DECODER

I2C-BUS SERIAL

INTERFACE

AHB T O APB

BRIDGE APB

DIVIDER

SPI0 SERIAL

INTERFACE

UART0/UART1

WATCHDOG

TIMER

SYSTEM

CONTROL

REAL-TIME CLOCK

002aad178

VDD(3V3)

VSS

VDD(1V8)

PWM[6:1](1)

SCK0(1)

MOSI0(1)

MISO0(1)

SSEL0(1)

SPI1/SSP(3) SERIAL

INTERFACE

SCK1(1)

MOSI1(1)

MISO1(1)

SSEL1(1)

RXD[1:0](1)

TXD[1:0](1)

P0[30:27],

P0[25:0]

P1[31:16]

HIGH-SPEED

GPI/O(3)

46 PINS TOTAL

Product data sheet Rev. 6 — 14 June 2011 4 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

5. Pinning information

5.1 Pinning

Fig 2. Pin configuratio n

LPC2194

LPC2194/00

LPC2194/01

P0[21]/PWM5/RD3/CAP1[3] P1[20]/TRACESYNC

P0[22]/TD3/CAP0[0]/MAT0[0] P0[17]/CAP1[2]/SCK1/MAT1[2]

P0[23]/RD2 P0[16]/EINT0/MAT0[2]/CAP0[2]

P1[19]/TRACEPKT3 P0[15]/RI1/EINT2

P0[24]/TD2 P1[21]/PIPESTAT0

DD(3V3)

DDA(3V3)

P1[18]/TRACEPKT2 P0[14]/DCD1/EINT1

P0[25]/RD1 P1[22]/PIPESTAT1

TD1 P0[13]/DTR1/MAT1[1]/TD4

P0[27]/AIN0/CAP0[1]/MAT0[1] P0[12]/DSR1/MAT1[0]/RD4

P1[17]/TRACEPKT1 P0[11]/CTS1/CAP1[1]

P0[28]/AIN1/CAP0[2]/MAT0[2] P1[23]/PIPESTAT2

P0[29]/AIN2/CAP0[3]/MAT0[3] P0[10]/RTS1/CAP1[0]

P0[30]/AIN3/EINT3/CAP0[0] P0[9]/RXD1/PWM6/EINT3

P1[16]/TRACEPKT0 P0[8]/TXD1/PWM4

DD(1V8)

P1[27]/TDO

DDA(1V8)

P0[0]/TXD0/PWM1 XTAL1

P1[31]/TRST XTAL2

P0[1]/RXD0/PWM3/EINT0 P1[28]/TDI

P0[2]/SCL/CAP0[0] V

SSA

DD(3V3)

SSA(PLL)

P1[26]/RTCK RESET

P1[29]/TCK

P0[3]/SDA/MAT0[0]/EINT1 P0[20]/MAT1[3]/SSEL1/EINT3

P0[4]/SCK0/CAP0[1] P0[19]/MAT1[2]/MOSI1/CAP1[2]

P1[25]/EXTIN0 P0[18]/CAP1[3]/MISO1/MAT1[3]

P0[5]/MISO0/MAT0[1] P1[30]/TMS

P0[6]/MOSI0/CAP0[2] V

DD(3V3)

P0[7]/SSEL0/PWM2/EINT2 V

P1[24]/TRACECLK V

DD(1V8)

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Product data sheet Rev. 6 — 14 June 2011 5 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

5.2 Pin description

Table 2. Pin de scription

Symbol Pin Type Description

P0[0] to P0[31] I/O Port 0 is a 32-bit bidirectional I/O port with individual direction control s for each bit.

The operation of port 0 pins depe nds upon the pin function selected via the Pin

Connect Block. Pins 26 and 31 of port 0 are not available.

P0[0]/TXD0/

PWM1 19 O TXD0 — Transmitter output for UART0.

OPWM1 — Pulse Width Modulator output 1.

P0[1]/RXD0/

PWM3/EINT0 21 I RXD0 — Receiver input for UART0.

OPWM3 — Pulse Width Modulator output 3.

IEINT0 — External interrupt 0 input.

P0[2]/SCL/

CAP0[0] 22 I/O SCL — I2C-bus clock input/output. Open-drain output (for I2C-bus compliance).

ICAP0[0] — Capture input for Timer 0, channel 0.

P0[3]/SDA/

MAT0[0]/EINT1 26 I/O SDA — I2C-bus data input/output. Open-drain output (for I2C-bus compliance).

OMAT0[0] — Match output for Timer 0, channel 0.

IEINT1 — External interrupt 1 input.

P0[4]/SCK0/

CAP0[1] 27 I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.

ICAP0[1] — Capture input for Timer 0, channel 1.

P0[5]/MISO0/

MAT0[1] 29 I/O MISO0 — Master In Slav e Out for SPI0. Data input to SPI master or data output

from SPI slave.

OMAT0[1] — Match output for Timer 0, channel 1.

P0[6]/MOSI0/

CAP0[2] 30 I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data input

to SPI slave.

ICAP0[2] — Capture input for Timer 0, channel 2.

P0[7]/SSEL0/

PWM2/EINT2 31 I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.

OPWM2 — Pulse Width Modulator output 2.

IEINT2 — External interrupt 2 input.

P0[8]/TXD1/

PWM4 33 O TXD1 — Transmitter output for UART1.

OPWM4 — Pulse Width Modulator output 4.

P0[9]/RXD1/

PWM6/EINT3 34 I RXD1 — Receiver input for UART1.

OPWM6 — Pulse Width Modulator output 6.

IEINT3 — External interrupt 3 input.

P0[10]/RTS1/

CAP1[0] 35 O RTS1 — Request to Send output for UART1.

ICAP1[0] — Capture input for Timer 1, channel 0.

P0[11]/CTS1/

CAP1[1] 37 I CTS1 — Clear to Send input for UART1.

ICAP1[1] — Capture input for Timer 1, channel 1.

P0[12]/DSR1/

MAT1[0]/RD4 38 I DSR1 — Data Set Ready input for UART1.

OMAT1[0] — Match output for Timer 1, channel 0.

ORD4 — CAN4 receiver input.

P0[13]/DTR1/

MAT1[1]/TD4 39 O DTR1 — Data Terminal Ready output for UART1.

OMAT1[1] — Match output for Timer 1, channel 1.

OTD4 — CAN4 transmitter output.

Product data sheet Rev. 6 — 14 June 2011 6 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

P0[14]/DCD1/

EINT1 41 I DCD1 — Data Carrier Detect input for UART1.

IEINT1 — External interrupt 1 input.

Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take

control of the part after reset.

P0[15]/RI1/EINT2 45 I RI1 — Ring Indicator input for UART1.

IEINT2 — External interrupt 2 input.

P0[16]/EINT0/

MAT0[2]/CAP0[2] 46 I EINT0 — External interrupt 0 input.

OMAT0[2] — Match output for Timer 0, channel 2.

ICAP0[2] — Capture input for Timer 0, channel 2.

P0[17]/CAP1[2]/

SCK1/MAT1[2] 47 I CAP 1[2] — Capture in put for Timer 1, channel 2.

I/O SCK1 — Serial Clock for SPI1/SSP[1]. SPI clock output fr om master or input to

slave.

OMAT1[2] — Match output for Timer 1, channel 2.

P0[18]/CAP1[3]/

MISO1/MAT1[3] 53 I CAP1[3] — Capture input for Timer 1, channel 3.

I/O MISO1 — Master In Slave Out for SPI1/SSP[1]. Data input to SPI master or data

output from SPI slave.

OMAT1[3] — Match output for Timer 1, channel 3.

P0[19]/MAT1[2]/

MOSI1/CAP1[2] 54 O MAT1[2] — Match output for Timer 1, channel 2.

I/O MOSI1 — Master Out Slave In for SPI1/SSP[1]. Dat a output from SPI master or data

input to SPI slave.

ICAP1[2] — Capture input for Timer 1, channel 2.

P0[20]/MAT1[3]/

SSEL1/EINT3 55 O MAT1[3] — Match output for Timer 1, channel 3.

ISSEL1 — Slave Select for SPI1/SSP[1]. Selects the SPI in te rf ace as a slave .

IEINT3 — External interrupt 3 input.

P0[21]/PWM5/

RD3/CAP1[3] 1OPWM5 — Pulse Width Modulator output 5.

IRD3 — CAN3 receiver input.

ICAP1[3] — Capture input for Timer 1, channel 3.

P0[22]/TD3/

CAP0[0]/MAT0[0] 2OTD3 — CAN3 transmitter output.

ICAP0[0] — Capture input for Timer 0, channel 0.

OMAT0[0] — Match output for Timer 0, channel 0.

P0[23]/RD2 3 I CAN2 receiver input.

P0[24]/TD2 5 O CAN2 transmitter output.

P0[25]/RD1 9 O CAN1 receiver input.

P0[27]/AIN0/

CAP0[1]/MAT0[1] 11 I AIN0 — A/D converter, input 0. This analog input is always connected to its pin.

ICAP0[1] — Capture input for Timer 0, channel 1.

OMAT0[1] — Match output for Timer 0, channel 1.

P0[28]/AIN1/

CAP0[2]/MAT0[2] 13 I AIN1 — A/D converter, input 1. This analog input is always connected to its pin.

ICAP0[2] — Capture input for Timer 0, channel 2.

OMAT0[2] — Match output for Timer 0, channel 2.

P0[29]/AIN2/

CAP0[3]/MAT0[3] 14 I AIN2 — A/D converter, input 2. This analog input is always connected to its pin.

ICAP0[3] — Capture input for Timer 0, Channel 3.

OMAT0[3] — Match output for Timer 0, channel 3.

Table 2. Pin de scription …continued

Symbol Pin Type Description

Product data sheet Rev. 6 — 14 June 2011 7 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

P0[30]/AIN3/

EINT3/CAP0[0] 15 I AIN3 — A/D converter, input 3. This analog input is always connected to its pin.

IEINT3 — External interrupt 3 input.

ICAP0[0] — Capture input for Timer 0, channel 0.

P1[0] to P1[31] I/O Port 1 is a 32-bit bidirectional I/O port with individual direction control s for each bit.

The operation of port 1 pins depe nds upon the pin function selected via the Pin

Connect Block. Pins 0 through 15 of port 1 are not available.

P1[16]/

TRACEPKT0 16 O Trace Packet, bit 0. Standard I/O port with internal pull-up.

P1[17]/

TRACEPKT1 12 O Trace Packet, bit 1. Standard I/O port with internal pull-up.

P1[18]/

TRACEPKT2 8 O Trace Packet, bit 2. Standard I/O port with internal pull-up.

P1[19]/

TRACEPKT3 4 O Trace Packet, bit 3. Standard I/O port with internal pull-up.

P1[20]/

TRACESYNC 48 O Trace Synchronization. Standard I/O port with internal pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1[25:1 6] to operate as

Trace port after reset.

P1[21]/

PIPESTAT0 44 O Pipeline Status, bit 0. Standard I/O port with internal pull-up.

P1[22]/

PIPESTAT1 40 O Pipeline Status, bit 1. Standard I/O port with internal pull-up.

P1[23]/

PIPESTAT2 36 O Pipeline Status, bit 2. Standard I/O port with internal pull-up.

P1[24]/

TRACECLK 32 O Trace Clock. Standard I/O port with internal pull-up.

P1[25]/EXTIN0 28 I External Trigger Input. Standard I/O with internal pull-up.

P1[26]/RTCK 24 I/O Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger

synchronization when processor frequency varies. Bidirectional pin with internal

pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1[31:26] to operate as

Debug port after reset.

P1[27]/TDO 64 O Test Data out for JTAG interface.

P1[28]/TDI 60 I Test Dat a in for JTAG interface.

P1[29]/TCK 56 I Test Clock for JTAG interface. This clock must be slower than 1⁄6 of the CPU clock

(CCLK) for the JTAG interface to operate.

P1[30]/TMS 52 I Test Mode Select for JTAG interface.

P1[31]/TRST 20 I Test Reset for JTAG interface.

TD1 10 O CAN1 transmitter output.

RESET 57 I external reset input; a LOW on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor execution to begin at

address 0. TTL with hysteresis, 5 V tolerant.

XTAL1 62 I input to the oscillator circuit and internal clock generator circuits.

XTAL2 61 O output from the oscillator amplifier.

VSS 6, 18, 25,

42, 50 I ground: 0 V reference.

Table 2. Pin de scription …continued

Symbol Pin Type Description

Product data sheet Rev. 6 — 14 June 2011 8 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

[1] SSP interface available on LPC2194/01 only.

VSSA 59 I analog ground; 0 V reference. This should nominally be the same voltage as VSS,

but should be isolated to minimize noise and error.

VSSA(PLL) 58 I PLL analog ground; 0 V reference. This should nominal ly be the same voltage as

VSS, but should be isolated to minimize noise and error.

VDD(1V8) 1 7, 49 I 1.8 V core power supply; this is the power supply voltage for internal circuitry.

VDDA(1V8) 63 I analog 1.8 V core power supply; this is the power supply voltage for internal

circuitry. This shoul d be nominally the same voltage as VDD(1V8) but should be

isolated to minimize noise and error.

VDD(3V3) 23, 43, 51 I 3.3 V pad power supply; this is the power supply voltage for the I/O ports.

VDDA(3V3) 7 I analog 3.3 V pad power supply; this should be nominally the same voltage as

VDD(3V3) but should be isolated to minimize noise and error.

Table 2. Pin de scription …continued

Symbol Pin Type Description

Product data sheet Rev. 6 — 14 June 2011 9 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

6. Functional description

Details of the LPC2194 systems and peripheral functions are described in the following

sections.

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, a nd the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex

Instruction Set Computers. This simplicity results in a high instruction throughput and

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all p arts o f the processing and m emory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

•The standard 32-bit ARM set.

•A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memor y system.

6.2 On-chip flash program memory

The LPC2194 incorporates a 25 6 kB flash memory system. This memory may be used for

both code and data storage. Programming of the flash memory may be accom plished in

several ways. It may be programmed In System via the serial port. The application

program may also erase and/or program the flash while the application is running,

allowing a great degree of flexibility for dat a storage field firmware upgrades, etc. When

on-chip bootloader is used, 248 kB of flash memory is available for user code.

The LPC2194 flash memory provides a minimum of 100000 erase/write cycles and 20

years of data retention.

On-chip bootloader (as of revision 1.60) provides Code Read Protection (CRP) for the

LPC2194 on-chip flash memory. When the CRP is enabled, the JTAG debug port and ISP

commands accessing either the on-chip RAM or flash memor y are disabled. However, the

Product data sheet Rev. 6 — 14 June 2011 10 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

ISP flash erase command can be executed at any time (no matter whether the CRP is on

or off). Removal of CRP is achieved by erasure of full on-chip user flash. With the CRP off,

full access to the chip via the JTAG and/or ISP is restored.

6.3 On-chip SRAM

On-chip SRAM may be used for code and/or data storage. The SRAM may be acce ssed

as 8 bit, 16 bit, and 32 bit. The LPC2194 provides 16 kB of SRAM.

6.4 Memory map

The LPC2194 memory maps incorporate several distinct regions, as shown in Figure 3.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either

flash memory (the default) or on-chip SRAM. This is described in Section 6.18 “System

control”.

Product data sheet Rev. 6 — 14 June 2011 11 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

6.5 Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inp uts and

categorizes them as F ast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and

non-vectored IRQ as defined by programmable settings. The programmable assignment

scheme means that priorities of interrupt s from the various peripherals can be dynamically

assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC

combines the requests to produce the FIQ signal to the ARM processor. The fastest

possible FIQ latency is achieved when only one request is classified as FIQ, because th en

the FIQ service routine can simply start dealing with that device. But if more than one

request is assigned to the FIQ class, the FIQ service routine can re ad a word from the VIC

that identifies which F IQ so ur ce (s) is (are ) requ e s ting an inte rr up t.

Fig 3. LPC2194 memory map

AHB PERIPHERALS

APB PERIPHERALS

RESERVED ADDRESS SPACE

BOOT BLOCK (RE-MAPPED FROM

ON-CHIP FLASH MEMORY)

RESERVED ADDRESS SPACE

16 kB ON-CHIP STATIC RAM

RESERVED ADDRESS SPACE

256 kB ON-CHIP FLASH MEMORY

0xFFFF FFFF

0xF000 0000

0xEFFF FFFF

0xE000 0000

0xC000 0000

0xDFFF FFFF

0x8000 0000

0x7FFF FFFF

0x7FFF E000

0x7FFF DFFF

0x4000 4000

0x4000 3FFF

0x4000 0000

0x3FFF FFFF

0x0004 0000

0x0003 FFFF

4.0 GB

3.75 GB

3.5 GB

3.0 GB

2.0 GB

1.0 GB

0.0 GB 0x0000 0000

002aad180

Product data sheet Rev. 6 — 14 June 2011 12 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned

to this category. Any of the interrupt requests can be assigned to any of the 16 vectored

IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a

VIC provides the address of the highest-priority requesting IRQs service routine,

otherwise it provides the address of a default routine that is shared by all the non-vectored

IRQs. The default routine can read another VIC register to see what IRQs are active .

6.5.1 Interrupt sources

Table 3 lists th e interrupt sources for ea ch peripheral fun ction. Each peripher al device has

one interrupt line connected to the Vectored Interrupt Controller, but may have several

internal interrupt flags. Individual interrupt flags may also represent more than one

interrupt source.

Table 3. Interrupt sources

Block Flag(s) VIC channel #

WDT Watchdog Interrupt (W DINT) 0

- Reserved for software interrupts only 1

ARM Core EmbeddedICE, DbgCommRx 2

ARM Core EmbeddedICE, DbgCommTx 3

Timer 0 Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3) 4

Timer 1 Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3) 5

UART0 Rx Line Status (RLS)

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

UART1 Rx Line Status (RLS)

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)

Character Time-out Indicator (CTI)

Modem Status Interrupt (MSI)

PWM0 Match 0 to 3 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) 8

I2C-bus SI (state change) 9

SPI0 SPIF, MODF 10

SPI1 and SSP[1] SPIF, MODF and TXRIS, RXRIS, RTRIS, RORRIS 11

PLL PLL Lock (PLOCK) 12

RTC RTCCIF (Counter Increment), RTCALF (Alarm) 13

Product data sheet Rev. 6 — 14 June 2011 13 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

[1] SSP interface available on LPC2194/01 only.

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to an y rela ted inter rupt(s) bein g enab led. Activity of a ny

enabled peripheral function that is not mapped to a related pin should be considered

undefined.

6.7 General purpose parallel I/O (GPIO) and Fast I/O

Device pins that are not connected to a specific peripheral function are controlled by the

parallel I/O registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any nu mber of outp uts simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

6.7.1 Features

•Bit-level set and clear r egisters allow a single instruction set or clear of any num ber of

bits in one port.

•Direction control of individual bits.

•Separate control of output set and clear.

•All I/O default to inputs after reset.

6.7.2 Features added with the Fast GPIO set of registers available on LPC2194/01

only

•Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O

timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.

•Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

•All GPIO registers are byte addressable.

•Entire port value can be written in one instruction.

System Control External Interrupt 0 (EINT0) 14

External Interrupt 1 (EINT1) 15

External Interrupt 2 (EINT2) 16

External Interrupt 3 (EINT3) 17

ADC A/D Converter 18

CAN 1 OR e d CAN Acceptance Filter 19

CAN1 (Tx int, Rx int) 20,21

CAN2 (Tx int, Rx int) 22,23

CAN3 (Tx int, Rx int) 24,25

CAN4 (Tx int, Rx int) 26,27

Table 3. Interrupt sources …continued

Block Flag(s) VIC channel #

Product data sheet Rev. 6 — 14 June 2011 14 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

•Ports are accessible via eithe r th e leg ac y group of registers (GPIOs) or the group of

registers providing accelerated port access (Fast GPIOs).

6.8 10-bit ADC

The LPC2194 each contain a single 10-bit successive approximation ADC with four

multiplexed channels.

6.8.1 Features

•Measurement range of 0 V to 3 V.

•Capable of performing more than 400000 10-bit samp les per second.

•Burst conversion mode for single or multiple inputs.

•Optional conversion on transition on input pin or Timer Match signal.

6.8.2 ADC features available in LPC2194/01 only

•Every analog input ha s a de dic at ed res ult re gis te r to re du ce interr up t overhead.

•Every analog input can generate an interrupt once the conversion is completed.

•The ADC pads are 5 V tolerant when configured for digital I/O function(s).

6.9 CAN controllers and acceptance filter

The LPC2194 contains four CAN controllers. The CAN is a serial communications

protocol which efficiently supp orts distributed real-time control with a very high level of

security. Its domain of application ranges from high-speed networks to low-cost multiplex

wiring.

6.9.1 Features

•Data rates up to 1 Mbit/s on each bus.

•32-bit register and RAM access.

•Compatible with CAN specification 2.0B, ISO 11898-1.

•Global Acceptan ce Filter reco gnizes 11-bit and 29-bit Rx identifiers for all CAN buses.

•Acceptance Filter can provide FullC AN- style automatic reception for selected

Standard identifiers.

6.10 UARTs

The LPC2194 each contain two UARTs. In addition to standard transmit and receive data

lines, the UART1 also provides a full modem control handshake interface.

6.10.1 Features

•16 B Receive and Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B

•Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

Product data sheet Rev. 6 — 14 June 2011 15 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

•Transmission FIFO control enables implementation of software (XON/XOFF) flow

control on both UARTs.

•UART1 is equipped with standard modem interface sign als. This module also

provides full support for hardware flow control (auto-CTS/RTS).

6.10.2 UART features available in LPC2194/01 only

Compared to previous LPC2000 microcontrollers, UARTs in LPC2194/01 introduce a

fractional baud rate generator for bo th UAR Ts, enabling these microcontro llers to achieve

standard baud rates such as 1152 00 Bd with any crystal frequency above 2 MHz. In

addition, auto-CTS/RTS flow-control functions are fully implemented in hardware.

•Fractional baud rate generator enables st andard b aud rates such as 115200 Bd to be

achieved with any crystal frequency above 2 MHz.

•Auto-bauding.

•Auto-CTS/RTS flow-control fully implemented in hardware.

6.11 I2C-bus serial I/O controller

The I2C-bus is a bidirectional bus for inter-IC control using only two wires: a serial clock

line (SCL), and a serial data line (SDA). Each device is recognized by a unique address

and can opera te as ei ther a re ceiver-on l y device (e .g ., an LCD driver or a tr ansm itter with

the capability to both receive and send information (such as memory). T ransmitters and/or

receivers can oper ate in eithe r master or sl ave mo de, dependin g on wheth er the chip has

to initiate a dat a transfer or is only ad dressed. The I2C-bus is a multi-master bu s; it can be

controlled by more than one bus master connected to it.

The I2C-bus implemented in LPC2194 supports a bit rate up to 400 kbit/s (Fast I2C-bus).

6.11.1 Features

•Standard I2C-bus compliant interface.

•Easy to configure as Master, Slave, or Master/Slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake mech anism to suspend and

resume serial transfer.

•The I2C-bus may be used for test and diagnostic purpose s.

Product data sheet Rev. 6 — 14 June 2011 16 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

6.12 SPI serial I/O controller

The LPC2194 ea ch cont ain two SPIs. The SPI is a fu ll duplex serial interface, designed to

be able to handle multiple masters and slaves connected to a given bus . O n ly a sing l e

master and a single slave can communicate on the interface during a given data transfer.

During a data transfer the master always sends a byte of data to the slave, and the slave

always sends a byte of data to the master.

6.12.1 Features

•Compliant with Serial Peripheral Interface (SPI) specification.

•Synchronous, Serial, Full Duplex communication.

•Combined SPI master and slave.

•Maximum data bit rate of 1⁄8 of the input clock rate.

6.12.2 Features available in LPC2194/01 only

•Eight to 16 bits per frame.

•When the SPI interface is used in Master mode, the SSELn pin is not needed (can be

used for a different function).

6.13 SSP controller (LPC2194/01 only)

The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single mas te r an d a sing le

slave can communicate on the bus during a given data transfer. Data transfers are in

principle full duplex, with frames of four to 16 bits of data flowing from the master to the

slave and from the slave to the master.

While the SSP and SPI1 peripherals share the same physical pins, it is not possible to

have both of these two peripher als active at the same time. The application can switch on

the fly from SPI1 to SSP and back.

6.13.1 Features

•Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National

Semiconductor’s Microwire buses.

•Synchronous serial communication.

•Master or slave operation.

•8-frame FIFOs for both transmit and receive.

•Four to 16 bits per frame.

6.14 General purpose timers

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock and optionally generate interrupts or perform other actions at

specified timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

Product data sheet Rev. 6 — 14 June 2011 17 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

6.14.1 Features

•A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

•Timer or external event counter operation

•Four 32-bit capture channels per timer that can take a snapshot of the timer value

when an input signal transitions. A capture event may also optionally generate an

interrupt.

•Four 32-bit matc h re gist er s tha t allo w:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Four external outputs per timer corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

6.14.2 Features available in LPC2194/01 only

The LPC2194/01 can count external events on one of the capture inputs if the external

pulse lasts at least one half of the period of the PCLK. In this configuration, unused

capture lines can be selected as regular timer capture inputs, or used as external

interrupts.

•T imer can count cycles of either the perip heral clock (PCLK) or an externally sup plied

clock.

•When counting cycles of an externally supplied clock, only one of the timer’s capture

inputs can be selected as the timer’s clock. The rate of such a clock is limited to

PCLK / 4. Duration of HIGH/LOW levels on the selected CAP input cannot be shorter

than 1 / (2PCLK).

6.15 Watchdog timer

The purpose of the watchdog is to reset the mi crocontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a pr edetermined

amount of time.

6.15.1 Features

•Internally resets chip if not periodically reloaded.

•Debug mode.

•Enabled by soft ware but requires a har dware reset or a watchdog reset/interrupt to be

disabled.

•Incorrect/incomplete feed sequence causes reset/interrupt if enabled.

Product data sheet Rev. 6 — 14 June 2011 18 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

•Flag to indicate watchdog reset.

•Programmable 32-bit timer with internal pre-scaler.

•Selectable time period from (T cy(PCLK) 256 4) to (Tcy(PCLK) 232 4) in multiples of

Tcy(PCLK) 4.

6.16 Real-time clock

The RTC is designed to provide a set of counters to measure time when normal or idle

operating mode is selected. The RTC has been designed to use little power, making it

suitable for battery powered systems where the CPU is not running continuously (Idle

mode).

6.16.1 Features

•Measures the passage of time to maintain a calendar and clock.

•Ultra low power design to support battery powered systems.

•Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and

Day of Year.

•Programmable refer ence clock divider allows adjustme nt of the R TC to match variou s

crystal frequencies.

6.17 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2194. The Timer is designed to count

cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other

actions when specified timer values occur, based on seven match registers. The PWM

function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires

three non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (MR0) controls the PWM cycle rate, by resetting the count upon match.

The other match register controls the PWM edge position. Additional single edge

controlled PWM ou tp u ts require only on e m atc h register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM output s will all have a

rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edge s co ntr o lled .

Again, the MR0 match register controls the PWM cycle rate. The other match registers

control the two PWM edge positions. Additional double edge controlled PWM outputs

require only two match registers each, since the repetition rate is the same for all PWM

outputs.

Product data sheet Rev. 6 — 14 June 2011 19 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

With double edge controlled PWM outputs, specific match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

6.17.1 Features

•Seven match registers allow up to six single edge controlled or three double edge

controlled PWM outputs, or a mix of both types.

•The match registers also allow:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the

output is a constant LOW . Do uble edge controlled PWM outp uts can have eithe r edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

•Pulse period and width can be any number of timer counts. This allows complete

flexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

•Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

•Match register updates are synchronized with pulse outputs to prevent ge ne ra tion of

erroneous pulses. Sof tware must ‘release’ new ma tch values before they ca n become

effective.

•May be used as a standard timer if the PWM mode is not enabled.

•A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

6.18 System control

6.18.1 Crystal oscillator

The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output

frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for

purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is

running and connected. Refer to Section 6.18.2 “PLL” for additional information.

6.18.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled

Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the

multiplier value cannot be higher than 6 o n this family of micro controllers due to the upper

frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so

there is an additional divider in the loop to keep the CCO within its frequency range while

the PLL is providing the desir ed output freq ue ncy. The output divider may be set to di vide

Product data sheet Rev. 6 — 14 June 2011 20 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

by 2, 4, 8, or 16 to produce the outpu t clock. Since the minimum output divider value is 2,

it is insured that the PLL output has a 50 % duty cycle. The PLL is t urned off and

bypassed following a chip Reset and may be enabled by software. The program must

configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a

clock source. The PLL settling time is 100 s.

6.18.3 Reset and wake-up timer

Reset has two sources on the LPC2194: the RESET pin and Watchdog Reset. The

RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip

Reset by any source starts the Wake-up Timer (see Wake-up Timer description below),

causing the internal chip reset to remain asserted until the external Reset is de-asserted,

the oscillator is running, a fixed number of clocks have passed, and the on-chip flash

controller has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is the Reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

The Wake-up Timer ensures that the oscillator and other analog functions required for

chip operation are fully functional before the processor is allowed to execute instructions.

This is import ant at power on, all types of Reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mod e, any wa ke-u p of th e pr ocessor from Pow er -d o wn mo d e

makes use of the Wake-up Timer.

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufficient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of VDD ramp (in the case of power on), the typ e of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing

ambient cond itio ns .

6.18.4 Code security (Code Read Protection - CRP)

This feature of the LPC2194/01 allows the user to enable dif ferent le vels of secu rity in th e

system so that access to the on-chip flash and use of the JTAG and ISP can be restricted.

When needed, CRP is invo ke d by pr ogr am m ing a specific pattern into a dedicated flash

location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and flash field updates are needed but all sectors can not be erased.

CRP2 disables ac ce ss to chip via th e JTAG and only allows full fla sh er as e an d upd at e

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too.

It is up to the user’s application to provide (if needed) flash update mechanism using IAP

calls or call reinvoke ISP command to enable flash update via UART0.

Product data sheet Rev. 6 — 14 June 2011 21 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

Remark: Devices without the /00 or /01 suffixes have only a security level eq uiv ale n t to

CRP2 available.

6.18.5 External interrupt inputs

The LPC2194 include up to nine edge or level sensitive External Interrupt Inputs as

selectable pin functions. When the pins are combined, external events can be processed

as four indep endent interru pt signals. The External Interrupt Input s can optionally be used

to wake-up the processor from Power-down mode.

6.18.6 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

flash memory, or to the on-chip SRAM. This allows code running in different memory

spaces to have control of the interrupts.

6.18.7 Power control

The LPC2194 support two reduced power modes: Idle mode and Power-down mode. In

Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may gener ate interrupts to

cause the processor to resume execution. Idle mode eliminates power used by the

processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM value s ar e

preserved throughout Power-down mode and the logic levels of chip output pins remain

static. The Po wer-down mode can be termin ated and normal operatio n resumed by eith er

a Reset or certain specific interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumptio n to ne a rly zero .

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings.

6.18.8 APB

The APB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first

is to provide peripherals with the desired PCLK via APB so that they can operate at the

speed chosen for the ARM processor. In order to achieve this, the APB may be slowed

down to 1⁄2 to 1⁄4 of the processor clock rate. Because the APB must work properly at

power-up (and it s timing cannot be alte red if it does not work since the APB divider control

registers reside on the APB), the default condition at reset is for the APB to run at 1⁄4 of the

processor clock rate. The second purpose of the APB divider is to allow power savings

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Product data sheet Rev. 6 — 14 June 2011 22 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

when an application does not require any peripherals to run at the full processor rate.

Because the APB divider is connected to the PLL output, the PLL remains active (if it was

running) during Idle mode.

6.19 Emulation and debugging

The LPC2194 support emulation and debugging via a JT AG serial port. A trace port allows

tracing program execution. Debugging and trace functions are multiplexed only with

GPIOs on Port 1. This means that all communication, timer and interface peripherals

residing on Port 0 ar e available during th e development and deb ugging phase as they a re

when the application is run in the embedded system itself.

6.19.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE proto col convertor. EmbeddedICE protocol convertor convert s the Remote

Debug Protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a Debug Communication Channel function built-in. The debug

communication channel allows a program running on the target to communicate with the

host debugger or another separate host without stopping the program flow or even

entering the debug state. The debug communication channel is accessed as a

co-processor 14 by the program running on the ARM7TDMI-S core. The debug

communication channel allows the JTAG port to be used for sending and receiving data

without affecting the normal program flow. The debug communication channel data and

control registers are mapped in to addresses in the EmbeddedICE logic.

The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG

interface to operate.

6.19.2 Embedded trace macrocell

Since the LPC2194 have significant amounts of on-chip memory, it is not possible to

determine how the processor core is operating simply by observing the external pins. The

Embedded Trace Macroc ell (ETM) prov ides real-time trace capability for deeply

embedded processor cores. It outputs information about processor exe cution to the trace

port.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It

compresses the trace information and exports it through a narrow trace port. An external

trace port analyzer must capture the trace information under software debugger control.

Instruction trace (or PC trace) shows the flow of execu tion of the processor and provides a

list of all the instructions that were executed. Instruction trace is significantly compressed

by only broadcasting branch addresses as well as a set of status signals that indicate the

pipeline status on a cycle by cycle basis. Trace information generation can be controlled

by selecting the trigger resource. Trigger resources include address compa rators,

counters and sequencers. Since trace information is compressed the software debugger

requires a static image of the code being executed. Self-modifying code can not be trace d

because of this restriction.

Product data sheet Rev. 6 — 14 June 2011 23 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

6.19.3 RealMonitor

RealMonitor is a configurable software module, developed by ARM Inc., which enables

real-time debug. It is a lightweight debug monitor that runs in the background while users

debug their foreground application. It communicates with the host using the DCC (Debug

Communications Channel), which is present in the EmbeddedICE logic. The LPC2194

contain a specific configuration of RealMonitor software programmed into the on-chip

flash memory.

Product data sheet Rev. 6 — 14 June 2011 24 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

7. Limiting values

[1] The following applies to Table 4:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Internal rail.

[3] External rail.

[4] Including voltage on outputs in 3-state mode.

[5] Only valid when the VDD(3V3) supply voltage is present.

[6] Not to exceed 4.6 V.

[7] Per supply pin.

[8] The peak current is limited to 25 times the corresponding maximum current.

[9] Per ground pin.

[10] Dependent on package type.

[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD(1V8) supply voltage (1.8 V) [2] 0.5 +2.5 V

VDD(3V3) supply voltage (3.3 V) [3] 0.5 +3.6 V

VDDA(3V3) analog supply voltage (3.3 V) 0.5 +4.6 V

VIA analog input voltage 0.5 +5.1 V

VIinput voltage 5 V tolerant I/O pins [4][5] 0.5 +6.0 V

other I/O pins [4][6] 0.5 VDD(3V3) + 0.5 V

IDD supply current [7][8] - 100 mA

ISS ground current [8][9] - 100 mA

Tjjunction temperature - 150 C

Tstg storage temperature [10] 65 +150 C

Ptot(pack) total power dissipation (per

package) based on package heat

transfer, not device

power consumption

-1.5 W

VESD electrostatic discharge voltage human body model [11]

all pins 2000 +2000 V

Product data sheet Rev. 6 — 14 June 2011 25 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

8. Static characteristics

Table 5. Static characteristics

Tamb =





C to +125



C for industrial applications, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD(1V8) supply voltage (1.8 V) [2] 1.65 1.8 1.95 V

VDD(3V3) supply voltage (3.3 V) [3] 3.0 3.3 3.6 V

VDDA(3V3) analog supply voltage

(3.3 V) 2.5 3.3 3.6 V

Standard port pins, RESET, RTCK

IIL LOW-level input current VI= 0 V; no pull-up - - 3 A

IIH HIGH-level input current VI=V

DD(3V3); no pull-down - - 3 A

IOZ OFF-stat e output current VO=0V; V

O=V

DD(3V3);

no pull-up/down --3A

Ilatch I/O latch-up current (0.5VDD(3V3)) < VI <

(1.5VDD(3V3)); Tj < 125 C100 - - mA

VIinput voltage [4][5][6] 0-5.5V

VOoutput voltage output active 0 - VDD(3V3) V

VIH HIGH-level input voltage 2.0 - - V

VIL LOW-level input voltage - - 0.8 V

Vhys hysteres is vo ltage 0.4 - - V

VOH HIGH-level output voltage IOH =4 mA [7] VDD(3V3)  0.4 - - V

VOL LOW-level output voltage IOL =4 mA [7] --0.4V

IOH HIGH-level output current VOH =V

DD(3V3) 0.4 V [7] 4- -mA

IOL LOW- l e vel ou tp u t c urrent VOL =0.4V [7] 4--mA

IOHS HIGH-level short-circuit

output curren t VOH =0V [8] --45 mA

IOLS LOW-level short-circuit

output curren t VOL =V

DD(3V3) [8] --50mA

Ipd pull-down current VI=5V [9] 10 50 150 A

Ipu pull-up current VI=0V [10] 15 50 85 A

VDD(3V3) < VI < 5 V [9] 000A

Product data sheet Rev. 6 — 14 June 2011 26 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

Power consumption LPC2194

IDD(act) active mode supply

current VDD(1V8) =1.8V;

CCLK = 60 MHz;

Tamb =25C; code

while(1){}

executed from flash; all

peripherals enabled vi a

PCONP[11] register but not

configured to run

-60-mA

IDD(pd) Power-down mode supply

current VDD(1V8) =1.8V;

Tamb =25C-10-A

VDD(1V8) =1.8V;

Tamb =85C- 110 500 A

VDD(1V8) =1.8V;

Tamb =125C- 300 1000 A

Power consumption LPC2194/01

IDD(act) active mode supply

current VDD(1V8) =1.8V;

CCLK = 60 MHz;

Tamb =25C; code

while(1){}

executed from flash; all

peripherals enabled vi a

PCONP[11] register but not

configured to run

- 43.5 - mA

IDD(idle) Idle mode supply current VDD(1V8) =1.8V;

CCLK = 60 MHz;

Tamb =25C;

executed from flash; all

peripherals enabled vi a

PCONP[11] register but not

configured to run

-11.5-mA

IDD(pd) Power-down mode supply

current VDD(1V8) =1.8V;

Tamb =25C-10-A

VDD(1V8) =1.8V;

Tamb =85C- 110 500 A

VDD(1V8) =1.8V;

Tamb =125C- 300 1000 A

I2C-bus pins

VIH HIGH-level input voltage 0.7VDD(3V3) --V

VIL LOW-level input voltage - - 0.3VDD(3V3) V

Vhys hysteresis voltage - 0.05VDD(3V3) -V

VOL LOW-level output voltage IOLS =3 mA [7] --0.4V

ILI input leakage current VI=V

DD(3V3) [12] -24A

VI= 5 V - 10 22 A

Table 5. Static characteristics …continued

Tamb =





C to +125



C for industrial applications, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 6 — 14 June 2011 27 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[2] Internal rail.

[3] External rail.

[4] Including voltage on outputs in 3-state mode.

[5] VDD(3V3) supply voltages must be present.

[6] 3-state outputs go into 3-state mode when VDD(3V3) is grounded.

[7] Accounts for 100 mV voltage drop in all supply lines.

[8] Only allowed for a short time period.

[9] Minimum condition for VI= 4.5 V, maximum condition for VI=5.5V.

[10] Applies to P1[25:16].

[11] See LPC2119/2129/2194/2292/2294 User Manual.

[12] To VSS.

Oscillator pins

Vi(XTAL1) input voltage on pin

XTAL1 0-1.8V

Vo(XTAL2) output voltage on pin

XTAL2 0-1.8V

Table 5. Static characteristics …continued

Tamb =





C to +125



C for industrial applications, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 6 — 14 June 2011 28 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

[1] Conditions: VSSA =0V, V

DDA =3.3V.

[2] The ADC is monotonic, there are no missing codes.

[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 4.

[4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 4.

[5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 4.

[6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 4.

[7] The absolute voltage error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the

non-calibrated ADC and the ideal transfer curve. See Figure 4.

Table 6. ADC static characteristics

VDDA = 2.5 V to 3.6 V; Tamb =





C to +125



C unless otherwise specified; ADC frequency 4.5 MHz.

Symbol Parameter Conditions Min Typ Max Unit

VIA analog input voltage 0 - VDDA V

Cia analog input

capacitance --1pF

EDdifferential linearity

error [1][2][3] --1LSB

EL(adj) integral non-linearity [1][4] --2LSB

EOoffset error [1][5] --3LSB

EGgain er ror [1][6] --0.5 %

ETabsolute error [1][7] --4LSB

Product data sheet Rev. 6 — 14 June 2011 29 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 4. ADC characteristics

002aaa668

1023

1022

1021

1020

1019

(2)

(1)

10241018 1019 1020 1021 1022 1023

7123456

1018

(5)

(4)

(3)

1 LSB

(ideal)

code

out

VDDA − VSSA

1024

offset

error

gain

error

offset

error

VIA (LSBideal)

1 LSB =

Product data sheet Rev. 6 — 14 June 2011 30 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

8.1 Power consumption measurements for LPC2194/01

The power consumption measurements represent typical values for the given conditions.

The peripherals were enabled through the PCONP registe r, but for these measurements,

the peripherals were no t configured to run. Peri pherals were disabled throu gh the PCONP

PCONP register.

Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4;

Tamb =25C; core voltage 1.8 V.

Fig 5. Typical LPC2194/01 IDD(act) measured at different frequencies

002aad118

12 20 28 36 44 52 60

frequency (M H z)

IDD(act)

(mA)

all peripherals disabled

all peripherals enabled

Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4;

Tamb = 25 C; core voltage 1.8 V; all peripherals enabled.

Fig 6. Typical LPC2194/01 IDD(act) measure d at different voltages

002aad119

1.65 1.80 1.95

12 MHz

48 MHz

60 MHz

voltage (V)

IDD(act)

(mA)

Product data sheet Rev. 6 — 14 June 2011 31 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

Test conditions: Active mode entered executing code from on-chip flash; PCLK = CCLK⁄4;

Temp = 25 C; core voltage 1.8 V; all peripherals disabled.

Fig 7. Typical LPC2194/01 IDD(act) measure d at different voltages

002aad120

1.65 1.80 1.95

12 MHz

48 MHz

60 MHz

voltage (V)

IDD(act)

(mA)

Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;

Tamb = 25 C; core voltage 1.8 V.

Fig 8. Typical LPC2194/01 IDD(idle) meas ured at different freq uencies

002aad121

0.0

5.0

10.0

15.0

12 20 28 36 44 52 60

frequency (M H z)

IDD(idle)

(mA)

all peripherals disabled

all peripherals enabled

Product data sheet Rev. 6 — 14 June 2011 32 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;

Tamb =25C; core voltage 1.8 V; all peripherals enabled.

Fig 9. Typical LPC2194/01 IDD(idle) measured at different voltages

002aad122

0.0

5.0

10.0

15.0

1.65 1.80 1.95

voltage (V)

IDD(idle)

(mA)

12 MHz

48 MHz

60 MHz

Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;

Temp = 25 C; core voltage 1.8 V; all peripherals disabled.

Fig 10. Typical LPC2194/01 IDD(idle) measured at different voltages

002aad123

0.0

2.0

4.0

6.0

8.0

1.65 1.80 1.95

voltage (V)

12 MHz

48 MHz

60 MHz

IDD(idle)

(mA)

Product data sheet Rev. 6 — 14 June 2011 33 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

Test conditions: Power-down mode entered executing code from on-chip flash.

Fig 11. Typical LPC2194/01 core power-down current IDD(pd) measur ed at different temperatures

100

200

300

400

500

1. 65 V

1. 8 V

1. 95 V

002aad124

-40 -25 -10 5 20 35 50 65 80 95 110 125

temperature (°C)

DD(pd)

(μA)

Test conditions: code executed from on-chip flash; PCLK = CCLK⁄4;

core voltage 1.8 V; all peripherals disabled.

Fig 12. Typical LPC2194/01 IDD(act) measured at different temperatur es

002aad125

-40 -25 -10 5 20 35 50 65 80 95 110 125

12 MHz

48 MHz

60 MHz

temperature (°C)

DD(act)

(mA)

Product data sheet Rev. 6 — 14 June 2011 34 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

Test conditions: Idle mode entered executing code from on-chip flash; PCLK = CCLK⁄4;

core voltage 1.8 V; all peripherals disabled.

Fig 13. Typical LPC2194/01 IDD(idle) measured at different temperatu res

002aad126

-40 -25 -10 5 20 35 50 65 80 95 110 125

12 MHz

48 MHz

60 MHz

1.0

2.0

3.0

4.0

5.0

6.0

7.0

temperature (°C)

DD(idle)

(mA)

Table 7. Typical LPC2194/01 peripheral power consumption in active mo de

Core voltage 1.8 V; Tamb =25



C; all measurements in



A; PCLK = CCLK⁄4.

Peripheral CCLK = 12 MHz CCLK = 48 MHz CCLK = 60 MHz

Timer0 43 141 184

Timer1 46 150 180

UART0 98 320 398

UART1 103 351 421

PWM0 103 341 407

I2C-bus 9 37 53

SPI0/1 6 27 29

RTC165578

ADC 33 128 167

CAN1/2/3/4 230 769 912

Product data sheet Rev. 6 — 14 June 2011 35 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

9. Dynamic characteristics

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Bus capacitance Cb in pF, from 10 pF to 400 pF.

9.1 Timing

Table 8. Dynamic characteristics

Tamb =





C to +125



C for industrial applications; V DD(1V8), VDD(3V3) over specified ranges.[1]

Symbol Parameter Conditions Min Typ Max Unit

External clock

fosc oscillator frequency supplied by an external

oscillator (signal generator) 1-50MHz

external clock frequency

supplied by an external

crystal oscillator

1-30MHz

external clock frequency if

on-chip PLL is used 10 - 25 MHz

external clock frequency if

on-chip bootloader is used

for initial code download

10 - 25 MHz

Tcy(clk) clock cycle time 20 - 1000 ns

tCHCX clock HIGH time Tcy(clk) 0.4--ns

tCLCX clock LOW time Tcy(clk) 0.4--ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Port pins (except P0[2] and P0[3])

trrise time - 10 - ns

tffall time - 10 - ns

I2C-bus pins (P0[2] and P0[3])

tffall time VIH to VIL [2] 20 + 0.1  Cb--ns

Fig 14. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)

tCHCL tCLCX tCHCX

Tcy(clk)

tCLCH

002aaa907

Product data sheet Rev. 6 — 14 June 2011 36 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

10. Package outline

Fig 15. Package outline SOT314-2 (LQFP64)

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05 1.45

1.35 0.25 0.27

0.17 0.18

0.12 10.1

9.9 0.5 12.15

11.85 1.45

1.05 7

0.12 0.11 0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT314-2 MS-026136E10 00-01-19

03-02-25

D(1) (1)(1)

10.1

9.9

12.15

11.85

1.45

1.05

EA1

detail X

(A )

HA2

vMB

vMA

48 33

pin 1 index

0 2.5 5 mm

scale

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2

Product data sheet Rev. 6 — 14 June 2011 37 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

11. Abbreviations

Table 9. Abbreviations

Acronym Description

ADC Analog-to-Digital Converter

AMBA Advanced Microcontroller Bus Architecture

APB Advanced Peripheral Bus

CAN Controller Area Network

CPU Central Processing Unit

DCC Debug Communications Channel

FIFO First In, First Out

GPIO General Purpose Input/Output

I/O Input/Output

JTAG Joint Test Action Group

PLL Phase-Locked Loop

PWM Pulse Width Modulator

RAM Random Access Memory

SPI Serial Peripheral Interface

SRAM Static Random Access Memory

SSI Synchronous Serial Interface

SSP Synchronous Serial Port

TTL Transistor-Transistor Logic

UART Universal Asynchronous Receiver/Transmitter

Product data sheet Rev. 6 — 14 June 2011 38 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

12. Revision history

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC2194 v.6 20110614 Product data sheet 201004 021F LPC2194 v.5

Modifications: •Table 5 “Static characteristics”; Changed /01 Power-down mode supply current (IDD(pd))

from 180 A to 500 A for industrial temperature range, and 430 A to 1000 A for

extended temperature range.

•Table 5 “Static characteristics”; Moved Vhys voltage from typical to minimum.

•Table 5 “Static characteristics”; Changed I2C pad hysteresis from 0.5VDD(3V3) to

0.05VDD(3V3).

LPC2194 v.5 20071210 Product data sheet - LPC2194 v.4

Modifications: •Type number LPC2194HBD64/01 has been added.

•Details introduced with /01 devices on new peripherals/features (Fast I/O Ports, SSP, CRP)

and enhancements to existing ones (UART0/1, Timers, ADC, and SPI) added.

•Power consumption measurements for LPC2194/01 added.

•Description of JTAG pin TCK has been updated.

LPC2194 v.4 20061016 Product data sheet - LPC2194 v.3

LPC2194 v.3 20060714 Product data sheet - LPC2194 v.2

LPC2194 v.2 20041222 Product data - LPC2194 v.1

LPC2194 v.1 20040206 Preliminary data - -

Product data sheet Rev. 6 — 14 June 2011 39 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

13. Legal information

13.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

13.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

13.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconduct ors’ aggregate and cumulat ive liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with t heir

applications and products.

NXP Semiconductors does not accept any liabil ity related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will ca use permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document cont ains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 6 — 14 June 2011 40 of 41

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

13.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

14. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors LPC2194

Single-chip 16/32-bit microcontroller

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 14 June 2011

Document identifier: LPC2194

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

15. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

2.1 Key features brought by LPC2194 /01 devices . 1

2.2 Key features common for all devices . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6 Functional description . . . . . . . . . . . . . . . . . . . 9

6.1 Architectural overview . . . . . . . . . . . . . . . . . . . 9

6.2 On-chip flash program memory . . . . . . . . . . . . 9

6.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 10

6.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 11

6.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 12

6.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 13

6.7 General purpose parallel I/O (GPIO) and

Fast I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.7.2 Features added with the Fast GPIO set of

registers available on LPC2194/01 only. . . . . 13

6.8 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.8.2 ADC features available in LPC2194/01 only. . 14

6.9 CAN controllers and acceptance filter . . . . . . 14

6.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.10 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.10.2 UART features available in LPC2194/01 only 15

6.11 I2C-bus serial I/O controller . . . . . . . . . . . . . . 15

6.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.12 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 16

6.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.12.2 Features available in LPC2194/01 only . . . . . 16

6.13 SSP controller (LPC2194/01 only) . . . . . . . . . 16

6.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.14 General purpose timers . . . . . . . . . . . . . . . . . 16

6.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.14.2 Features available in LPC2194/01 only . . . . . 17

6.15 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 17

6.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.16 Real-time clock. . . . . . . . . . . . . . . . . . . . . . . . 18

6.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.17 Pulse width modulator . . . . . . . . . . . . . . . . . . 18

6.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.18 System control . . . . . . . . . . . . . . . . . . . . . . . . 19

6.18.1 Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 19

6.18.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.18.3 Reset and wake-up timer. . . . . . . . . . . . . . . . 20

6.18.4 Code security (Code Read Protecti on - CRP) 20

6.18.5 External interrupt inputs. . . . . . . . . . . . . . . . . 21

6.18.6 Memory mapping control . . . . . . . . . . . . . . . . 21

6.18.7 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 21

6.18.8 APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.19 Emulation and debugging . . . . . . . . . . . . . . . 22

6.19.1 EmbeddedIC E . . . . . . . . . . . . . . . . . . . . . . . . 22

6.19.2 Embedded trace macrocell . . . . . . . . . . . . . . 22

6.19.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 24

8 Static characteristics . . . . . . . . . . . . . . . . . . . 25

8.1 Power consumption measurements for

LPC2194/01. . . . . . . . . . . . . . . . . . . . . . . . . . 30

9 Dynamic characteristics. . . . . . . . . . . . . . . . . 35

9.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

10 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 36

11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 37

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . 38

13 Legal information . . . . . . . . . . . . . . . . . . . . . . 39

13.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 39

13.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 39

13.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40

14 Contact information . . . . . . . . . . . . . . . . . . . . 40

15 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41