100351
Low Power Hex D Flip-Flop
General Description
The 100351 contains six D-type edge-triggered, master/
slave flip-flops with true and complement outputs, a pair of
common Clock inputs (CP
a
and CP
b
) and common Master
Reset (MR) input. Data enters a master when both CP
a
and
CP
b
are LOW and transfers to the slave when CP
a
and CP
b
(or both) go HIGH. The MR input overrides all other inputs
and makes the Q outputs LOW. All inputs have 50 kΩ
pull-down resistors.
Features
n40%power reduction of the 100151
n2000V ESD protection
nPin/function compatible with 100151
nVoltage compensated operating range:
−4.2V to −5.7V
nStandard Microcircuit Drawing
(SMD) 5962-9457901
Logic Symbol Pin Names Description
D
0
–D
5
Data Inputs
CP
a
,CP
b
Common Clock Inputs
MR Asynchronous Master Reset Input
Q
0
–Q
5
Data Outputs
Q
0
–Q
5
Complementary Data Outputs
DS100318-11
August 1998
100351 Low Power Hex D Flip-Flop
© 1998 National Semiconductor Corporation DS100318 www.national.com
Connection Diagrams
Logic Diagram
Truth Tables (Each Flip-flop)
Synchronous Operation
Inputs Outputs
D
n
CP
a
CP
b
MR Q
n
(t+1)
LNLL L
H
NLL H
LLNLL
HLNLH
XHNLQ
n
(t)
XNHL Q
n
(t)
XL LL Q
n
(t)
Asynchronous Operation
Inputs Outputs
D
n
CP
a
CP
b
MR Q
n
(t+1)
XX XH L
H
=
HIGH Voltage Level
L=LOW Voltage Level
X=Don’t Care
t=Time before CP positive transition
t+1 =Time after CP positive transition
N=LOW-to-HIGH transition
24-Pin DIP
DS100318-1
24-Pin Quad Cerpak
DS100318-2
DS100318-4
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Above which the useful life may be impaired
Storage Temperature (T
STG
) −65˚C to +150˚C
Maximum Junction Temperature (T
J
)
Ceramic +175˚C
V
EE
Pin Potential to Ground Pin −7.0V to +0.5V
Input Voltage (DC) V
EE
to +0.5V
Output Current (DC Output HIGH) −50 mA
ESD (Note 2) ≥2000V
Recommended Operating
Conditions
Case Temperature (T
C
)
Military −55˚C to +125˚C
Supply Voltage (V
EE
) −5.7V to −4.2V
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
V
EE
=−4.2V to −5.7V, V
CC
=V
CCA
=GND, T
C
=−55˚C to +125˚C
Symbol Parameter Min Max Units T
C
Conditions Notes
V
OH
Output HIGH Voltage −1025 −870 mV 0˚C to V
IN
=V
IH
(Max)
or V
IL
(Min) Loading with
50Ωto −2.0V (Notes 3, 4, 5)
+125˚C
−1085 −870 mV −55˚C
V
OL
Output LOW Voltage −1830 −1620 mV 0˚C to
+125˚C
−1830 −1555 mV −55˚C
V
OHC
Output HIGH Voltage −1035 mV 0˚C to V
IN
=V
IH
(Min)
or V
IL
(Max) Loading with
50Ωto −2.0V (Notes 3, 4, 5)
+125˚C
−1085 mV −55˚C
V
OLC
Output LOW Voltage −1610 mV 0˚C to
+125˚C
−1555 mV −55˚C
V
IH
Input HIGH Voltage −1165 −870 mV −55˚C to Guaranteed HIGH Signal (Notes 3, 4, 5, 6)
+125˚C for All Inputs
V
IL
Input LOW Voltage −1830 −1475 mV −55˚C to Guaranteed LOW Signal (Notes 3, 4, 5, 6)
+125˚C for All Inputs
I
IL
Input LOW Current 0.50 µA −55˚C to V
EE
=−4.2V (Notes 3, 4, 5)
+125˚C V
IN
=V
IL
(Min)
I
IH
Input HIGH Current V
EE
=−5.7V
V
IN
=V
IH
(Max) (Notes 3, 4, 5)
CP, MR 350 µA 0˚C to
D
0
–D
5
240 +125˚C
CP, MR 500 µA −55˚C
D
0
–D
5
340
I
EE
Power Supply Current −135 −50 mA −55˚C to Inputs Open (Notes 3, 4, 5)
+125˚C
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 4: Screen tested 100%on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8.
Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8.
Note 6: Guaranteed by applying specified input condition and testing VOH/VOL.
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AC Electrical Characteristics
V
EE
=−4.2V to −5.7V, V
CC
=V
CCA
=GND
Symbol Parameter T
C
=−55˚C T
C
=+25˚C T
C
=+125˚C Units Conditions Notes
Min Max Min Max Min Max
f
max
Toggle Frequency 375 375 375 MHz
Figures 2, 3
(Note 10)
t
PLH
Propagation Delay 0.40 2.40 0.50 2.20 0.50 2.60 ns
Figures 1, 3
t
PHL
CP
a
,CP
b
to Output (Notes 7, 8, 9)
t
PLH
Propagation Delay 0.60 2.70 0.70 2.60 0.80 2.90 ns
Figures 1, 4
t
PHL
MR to Output
t
TLH
Transition Time 0.20 1.60 0.20 1.60 0.20 1.60 ns
Figures 1, 3
(Note 10)
t
THL
20%to 80%,80
%to 20%
t
s
Setup Time
D
0
–D
5
0.90 0.80 0.90 ns
Figure 5
MR (Release Time) 1.60 1.80 2.60
Figure 4
t
h
Hold Time 1.50 1.40 1.60 ns
Figure 5
D
0
–D
5
t
pw
(H) Pulse Width HIGH 2.00 2.00 2.00 ns
Figures 3, 4
CP
a
,CP
b
,MR
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 8: Screen tested 100%on each device at +25˚C, Temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each Mfg. lot at +25˚C, Subgroup A9, and at +125˚C, and −55˚C Temperature, Subgroups A10 and A11.
Note 10: Not tested at +25˚C, +125˚C and −55˚C Temperature (design characterization data).
Test Circuitry
DS100318-5
Notes:
VCC,V
CCA =+2V, VEE =−2.5V
L1 and L2 =equal length 50Ωimpedance lines
RT=50Ωterminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 50Ωto GND
CL=Fixture and stray capacitance ≤3pF
FIGURE 1. AC Test Circuit
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Test Circuitry (Continued)
Switching Waveforms
DS100318-6
Notes:
VCC,V
CCA =+2V, VEE =−2.5V
L1 and L2 =equal length 50Ωimpedance lines
RT=50Ωterminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 50Ωto GND
CL=Jig and stray capacitance ≤3pF
FIGURE 2. Toggle Frequency Test Circuit
DS100318-7
FIGURE 3. Propagation Delay (Clock) and Transition Times
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Switching Waveforms (Continued)
DS100318-8
FIGURE 4. Propagation Delay (Reset)
DS100318-9
Notes:
tsis the minimum time before the transition of the clock that information must be present at the data input.
this the minimum time after the transition of the clock that information must remain unchanged at the data input.
FIGURE 5. Setup and Hold Time
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D)
NS Package Number J24E
24-Lead Quad Cerpak (F)
NS Package Number W24B
7 www.national.com
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with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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sonably expected to cause the failure of the life support
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100351 Low Power Hex D Flip-Flop
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
