32-Bit Microcontroller TC1782 / TC1182 32-Bit Single-Chip Microcontroller Data Sheet V 1.1 2011-06 Microcontrollers Edition 2011-06 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2011 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 32-Bit Microcontroller TC1782 / TC1182 32-Bit Single-Chip Microcontroller Data Sheet V 1.1 2011-06 Microcontrollers TC1782 / TC1182 Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 2.1 System Overview of the TC1782 / TC1182 . . . . . . . . . . . . . . . . . . . . . . 2-1 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 3 3.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 TC1782 / TC1182 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 4 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.6.1 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.8.1 5.3.8.2 5.3.8.3 5.3.8.4 5.4 5.4.1 5.4.2 5.4.3 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . 5-33 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . . 5-42 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44 Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . . 5-51 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52 DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54 Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56 Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . 5-56 Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . 5-58 SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60 ERAY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65 Data Sheet I-1 V 1.1, 2011-06 TC1782 / TC1182 5.4.4 6 Data Sheet Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 I-2 V 1.1, 2011-06 TC1782 / TC1182 Data Sheet 3 V 1.1, 2011-06 TC1782 / TC1182 Data Sheet 4 V 1.1, 2011-06 TC1782 / TC1182 Summary of Features 1 Summary of Features The SAK-TC1782F-320F180HR / SAK-TC1782F-320F180HL features: * * * * * * * has the following High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline - Superior real-time performance - Strong bit handling - Fully integrated DSP capabilities - Single precision Floating Point Unit (FPU) - 180 MHz operation at full temperature range 32-bit Peripheral Control Processor with single cycle instruction (PCP2) - 16 Kbyte Parameter Memory (PRAM) - 32 Kbyte Code Memory (CMEM) - 180 MHz operation at full temperature range Multiple on-chip memories - 2.5 Mbyte Program Flash Memory (PFLASH) with ECC - 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation - 128 Kbyte Data Memory (LDRAM) - Instruction Cache: up to 16 Kbyte (ICACHE, configurable) - 40 Kbyte Code Scratchpad Memory (SPRAM) - Data Cache: up to 4 Kbyte (DCACHE, configurable) - 8 Kbyte Overlay Memory (OVRAM) - 16 Kbyte BootROM (BROM) 16-Channel DMA Controller Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on-chip bus structure - 64-bit Local Memory Buses between CPU, Flash and Data Memory - 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units - One bus bridge (LFI Bridge) Versatile On-chip Peripheral Units - Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection - Three High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction - One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices - One High-Speed Micro Link interface (MLI) for serial inter-processor communication - One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality) - One FlexRayTM module with 2 channels (E-Ray). Data Sheet 1 V 1.1, 2011-06 TC1782 / TC1182 Summary of Features * * * * * * * * - One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management 32 analog input lines for ADC - 2 independent kernels (ADC0 and ADC1) - Analog supply voltage range from 3.3 V to 5 V (single supply) 4 different FADC input channels - channels with impedance control and overlaid with ADC1 inputs - Extreme fast conversion, 21 cycles of fFADC clock - 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) 86 digital general purpose I/O lines (GPIO), 4 input lines Digital I/O ports with 3.3 V capability On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus) Dedicated Emulation Device chip available (TC1782 / TC1182ED) - multi-core debugging, real time tracing, and calibration - four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface Power Management System Clock Generation Unit with PLL Data Sheet 2 V 1.1, 2011-06 TC1782 / TC1182 Summary of Features The SAK-TC1782F-256F133HR / SAK-TC1782F-256F133HL features: * * * * * * * has the following High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline - Superior real-time performance - Strong bit handling - Fully integrated DSP capabilities - Single precision Floating Point Unit (FPU) - 133 MHz operation at full temperature range 32-bit Peripheral Control Processor with single cycle instruction (PCP2) - 16 Kbyte Parameter Memory (PRAM) - 32 Kbyte Code Memory (CMEM) - 133 MHz operation at full temperature range Multiple on-chip memories - 2 Mbyte Program Flash Memory (PFLASH) with ECC - 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation - 128 Kbyte Data Memory (LDRAM) - Instruction Cache: up to 16 Kbyte (ICACHE, configurable) - 40 Kbyte Code Scratchpad Memory (SPRAM) - Data Cache: up to 4 Kbyte (DCACHE, configurable) - 8 Kbyte Overlay Memory (OVRAM) - 16 Kbyte BootROM (BROM) 16-Channel DMA Controller Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on-chip bus structure - 64-bit Local Memory Buses between CPU, Flash and Data Memory - 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units - One bus bridge (LFI Bridge) Versatile On-chip Peripheral Units - Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection - Three High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction - One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices - One High-Speed Micro Link interface (MLI) for serial inter-processor communication - One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality) Data Sheet 3 V 1.1, 2011-06 TC1782 / TC1182 Summary of Features * * * * * * * * - One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management 32 analog input lines for ADC - 2 independent kernels (ADC0 and ADC1) - Analog supply voltage range from 3.3 V to 5 V (single supply) 4 different FADC input channels - channels with impedance control and overlaid with ADC1 inputs - Extreme fast conversion, 21 cycles of fFADC clock - 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) 86 digital general purpose I/O lines (GPIO), 4 input lines Digital I/O ports with 3.3 V capability On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus) Dedicated Emulation Device chip available (TC1782 / TC1182ED) - multi-core debugging, real time tracing, and calibration - four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface Power Management System Clock Generation Unit with PLL The SAK-TC1782N-320F180HR / SAK-TC1782N-320F180HL / SAK-TC1182N320F180HR / SAK-TC1182N-320F180HL has the following features: * * * * High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline - Superior real-time performance - Strong bit handling - Fully integrated DSP capabilities - Single precision Floating Point Unit (FPU) - 180 MHz operation at full temperature range 32-bit Peripheral Control Processor with single cycle instruction (PCP2) - 16 Kbyte Parameter Memory (PRAM) - 32 Kbyte Code Memory (CMEM) - 180 MHz operation at full temperature range Multiple on-chip memories - 2.5 Mbyte Program Flash Memory (PFLASH) with ECC - 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation - 128 Kbyte Data Memory (LDRAM) - Instruction Cache: up to 16 Kbyte (ICACHE, configurable) - 40 Kbyte Code Scratchpad Memory (SPRAM) - Data Cache: up to 4 Kbyte (DCACHE, configurable) - 8 Kbyte Overlay Memory (OVRAM) - 16 Kbyte BootROM (BROM) 16-Channel DMA Controller Data Sheet 4 V 1.1, 2011-06 TC1782 / TC1182 Summary of Features * * * * * * * * * * * Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on-chip bus structure - 64-bit Local Memory Buses between CPU, Flash and Data Memory - 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units - One bus bridge (LFI Bridge) Versatile On-chip Peripheral Units - Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection - Three High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction - One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices - One High-Speed Micro Link interface (MLI) for serial inter-processor communication - One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality) - One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management 32 analog input lines for ADC - 2 independent kernels (ADC0 and ADC1) - Analog supply voltage range from 3.3 V to 5 V (single supply) 4 different FADC input channels - channels with impedance control and overlaid with ADC1 inputs - Extreme fast conversion, 21 cycles of fFADC clock - 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) 86 digital general purpose I/O lines (GPIO), 4 input lines Digital I/O ports with 3.3 V capability On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus) Dedicated Emulation Device chip available (TC1782 / TC1182ED) - multi-core debugging, real time tracing, and calibration - four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface Power Management System Clock Generation Unit with PLL Data Sheet 5 V 1.1, 2011-06 TC1782 / TC1182 Summary of Features The SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL / SAK-TC1182N256F133HR / SAK-TC1182N-256F133HL has the following features: * * * * * * * High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline - Superior real-time performance - Strong bit handling - Fully integrated DSP capabilities - Single precision Floating Point Unit (FPU) - 133 MHz operation at full temperature range 32-bit Peripheral Control Processor with single cycle instruction (PCP2) - 16 Kbyte Parameter Memory (PRAM) - 32 Kbyte Code Memory (CMEM) - 133 MHz operation at full temperature range Multiple on-chip memories - 2 Mbyte Program Flash Memory (PFLASH) with ECC - 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation - 128 Kbyte Data Memory (LDRAM) - Instruction Cache: up to 16 Kbyte (ICACHE, configurable) - 40 Kbyte Code Scratchpad Memory (SPRAM) - Data Cache: up to 4 Kbyte (DCACHE, configurable) - 8 Kbyte Overlay Memory (OVRAM) - 16 Kbyte BootROM (BROM) 16-Channel DMA Controller Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on-chip bus structure - 64-bit Local Memory Buses between CPU, Flash and Data Memory - 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units - One bus bridge (LFI Bridge) Versatile On-chip Peripheral Units - Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection - Three High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction - One serial Micro Second Bus interface (MSC) for serial port expansion to external power devices - One High-Speed Micro Link interface (MLI) for serial inter-processor communication - One MultiCAN Module with 3 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality) Data Sheet 6 V 1.1, 2011-06 TC1782 / TC1182 Summary of Features * * * * * * * * - One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management 32 analog input lines for ADC - 2 independent kernels (ADC0 and ADC1) - Analog supply voltage range from 3.3 V to 5 V (single supply) 4 different FADC input channels - channels with impedance control and overlaid with ADC1 inputs - Extreme fast conversion, 21 cycles of fFADC clock - 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) 86 digital general purpose I/O lines (GPIO), 4 input lines Digital I/O ports with 3.3 V capability On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus) Dedicated Emulation Device chip available (TC1782 / TC1182ED) - multi-core debugging, real time tracing, and calibration - four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface Power Management System Clock Generation Unit with PLL Data Sheet 7 V 1.1, 2011-06 TC1782 / TC1182 Summary of Features Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: * * The derivative itself, i.e. its function set, the temperature range, and the supply voltage The package and the type of delivery. For the available ordering codes for the TC1782 / TC1182 please refer to the "Product Catalog Microcontrollers", which summarizes all available microcontroller variants. This document describes the derivatives of the device.The Table 1 enumerates these derivatives and summarizes the differences. Table 1 TC1782 / TC1182 Derivative Synopsis Derivative Ambient Temperature Range SAK-TC1782F-320F180HR TA = -40oC to +125oC SAK-TC1782F-320F180HL TA = -40oC to +125oC SAK-TC1782N-320F180HR TA = -40oC to +125oC SAK-TC1782N-320F180HL TA = -40oC to +125oC SAK-TC1182N-320F180HR TA = -40oC to +125oC SAK-TC1182N-320F180HL TA = -40oC to +125oC SAK-TC1782F-256F133HR TA = -40oC to +125oC SAK-TC1782F-256F133HL TA = -40oC to +125oC SAK-TC1782N-256F133HR TA = -40oC to +125oC SAK-TC1782N-256F133HL TA = -40oC to +125oC SAK-TC1182N-256F133HR TA = -40oC to +125oC SAK-TC1182N-256F133HL TA = -40oC to +125oC Data Sheet 8 V 1.1, 2011-06 TC1782 / TC1182 System Overview of the TC1782 / TC1182 2 System Overview of the TC1782 / TC1182 The TC1782 / TC1182 combines three powerful technologies within one silicon die, achieving new levels of power, speed, and economy for embedded applications: * * * Reduced Instruction Set Computing (RISC) processor architecture Digital Signal Processing (DSP) operations and addressing modes On-chip memories and peripherals DSP operations and addressing modes provide the computational power necessary to efficiently analyze complex real-world signals. The RISC load/store architecture provides high computational bandwidth with low system cost. On-chip memory and peripherals are designed to support even the most demanding high-bandwidth real-time embedded control-systems tasks. Additional high-level features of the TC1782 / TC1182 include: * * * * * * * * * Efficient memory organization: instruction and data scratch memories, caches Serial communication interfaces - flexible synchronous and asynchronous modes Peripheral Control Processor - standalone data operations and interrupt servicing DMA Controller - DMA operations and interrupt servicing General-purpose timers High-performance on-chip buses On-chip debugging and emulation facilities Flexible interconnections to external components Flexible power-management The TC1782 / TC1182 is a high-performance microcontroller with TriCore CPU, program and data memories, buses, bus arbitration, an interrupt controller, a peripheral control processor and a DMA controller and several on-chip peripherals. The TC1782 / TC1182 is designed to meet the needs of the most demanding embedded control systems applications where the competing issues of price/performance, real-time responsiveness, computational power, data bandwidth, and power consumption are key design elements. The TC1782 / TC1182 offers several versatile on-chip peripheral units such as serial controllers, timer units, and Analog-to-Digital converters. Within the TC1782 / TC1182, all these peripheral units are connected to the TriCore CPU/system via the Flexible Peripheral Interconnect (FPI) Bus and the Local Memory Bus (LMB). Several I/O lines on the TC1782 / TC1182 ports are reserved for these peripheral units to communicate with the external world. Data Sheet 1 V 1.1, 2011-06 TC1782 / TC1182 System Overview of the TC1782 / TC1182Block Diagrams 2.1 Block Diagrams Figure 1 shows the block diagram of the SAK-TC1782-320F180HR / SAK-TC1782320F180HL. FPU PMI DMI TriCore CPU 24 KB SPRAM 16 KB ICACHE (Configurable) Abbreviations: ICACHE: Instruction Cache DCACHE Data Cache SPRAM: Scratch-Pad RAM LDRAM: Local Data RAM OVRAM: Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash PRAM: Parameter RAM in PCP PCODE: Code RAM in PCP 124 KB LDRAM LDRAM 4 KB DCACHE (Configurable) DCACHE CPS Local Memory Bus BCU (LMB) PMU DMA Bridge 16 channels SMIF M 2,5 MB PFlash 128 KB DFlash 8 KB OVRAM 16 KB BROM OCDS L 1 Debug Interface/ JTAG M/S MLI0 System Peripheral Bus (SPB) MemCheck 16 KB PRAM E-Ray GPTA0 System Peripheral Bus Interrupts ASC1 (2 Channels) Interrupt System FPI-Bus Interface ASC0 PCP2 Core STM 5V (3.3V supported as well) Ext. ADC Supply 32 KB CMEM SCU ADC0 28 (5V max) SBCU PLL E-RAY PLL Ports fE -Ray ADC1 4 fCPU SSC0 FADC (3.3V max) LTCA2 4 SSC1 Ext. Request Unit Figure 1 Multi CAN (3 Nodes, 128 MO) MSC0 3.3V Ext. FADC Supply SSC2 (LVDS) BlockDiagram SAK-TC1782-320F180HR SAK-TC1782-320F180HR / SAK-TC1782-320F180HL Block Diagram Figure 2 shows the block diagram of the SAK-TC1782N-320F180HR / SAK-TC1782N320F180HL / SAK-TC1182N-320F180HR / SAK-TC1182N-320F180HL. Data Sheet 2 V 1.1, 2011-06 TC1782 / TC1182 System Overview of the TC1782 / TC1182Block Diagrams FPU PMI DMI TriCore CPU 24 KB SPRAM 16 KB ICACHE (Configurable) Abbreviations: ICACHE: Instruction Cache DCACHE Data Cache SPRAM: Scratch-Pad RAM LDRAM: Local Data RAM OVRAM: Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash PRAM: Parameter RAM in PCP PCODE: Code RAM in PCP 124 KB LDRAM LDRAM 4 KB DCACHE (Configurable) DCACHE CPS Local Memory Bus BCU (LMB) PMU DMA Bridge 16 channels SMIF M 2,5 MB PFlash 128 KB DFlash 8 KB OVRAM 16 KB BROM OCDS L 1 Debug Interface/JTAG M/S MLI0 System Peripheral Bus (SPB) MemCheck 16 KB PRAM System Peripheral Bus ASC1 Interrupts FPI-Bus Interface ASC0 GPTA0 Interrupt System PCP2 Core STM 5V (3.3V supported as well) Ext. ADC Supply 32 KB CMEM SCU ADC0 28 (5V max) SBCU PLL E-RAY PLL Ports fE -Ray ADC1 4 fC PU SSC0 FADC (3.3V max) LTCA2 4 SSC1 Ext. Request Unit Figure 2 Multi CAN (3 Nodes, 128 MO) MSC0 3.3V Ext. FADC Supply SSC2 (LVDS) BlockDiagram SAK-TC1782N-320F180HR SAK-TC1782N-320F180HR / SAK-TC1782N-320F180HL / SAK-TC1182N-320F180HR / SAK-TC1182N-320F180HL / Block Diagram Figure 3 shows the block diagram of the SAK-TC1782F-256F133HR / SAK-TC1782F256F133HL / SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL / SAKTC1182N-256F133HR / SAK-TC1182N-256F133HL. Data Sheet 3 V 1.1, 2011-06 TC1782 / TC1182 System Overview of the TC1782 / TC1182Block Diagrams FPU PMI TriCore CPU 24 KB SPRAM 16 KB ICACHE (Configurable) Abbreviations: ICACHE: Instruction Cache DCACHE Data Cache SPRAM: Scratch-Pad RAM LDRAM: Local Data RAM OVRAM: Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash PRAM: Parameter RAM in PCP PCODE: Code RAM in PCP DMI 124 KB LDRAM LDRAM 4 KB DCACHE (Configurable) DCACHE CPS Local Memory Bus BCU (LMB) PMU DMA Bridge 16 channels SMIF M 2 MB PFlash 64 KB DFlash 8 KB OVRAM 16 KB BROM OCDS L 1 Debug Interface/ JTAG M/S MLI0 System Peripheral Bus (SPB) MemCheck 16 KB PRAM System Peripheral Bus ASC1 Interrupts FPI-Bus Interface ASC0 GPTA0 Interrupt System PCP2 Core STM 5V (3.3V supported as well) Ext. ADC Supply 32 KB CMEM SCU ADC0 28 (5V max) SBCU PLL E-RAY PLL Ports fE -Ray ADC1 4 fCPU SSC0 FADC (3.3V max) LTCA2 4 SSC1 Ext. Request Unit Figure 3 Data Sheet Multi CAN (3 Nodes, 128 MO) MSC0 3.3V Ext. FADC Supply SSC2 (LVDS) BlockDiagram SAK-TC1782-256F133HR SAK-TC1782F-256F133HR / SAK-TC1782F-256F133HL / SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL / SAK-TC1182N-256F133HR / SAK-TC1182N-256F133HL Block Diagram 4 V 1.1, 2011-06 TC1782 / TC1182 Pinning 3 Pinning Figure 4 is showing the TC1782 / TC1182 Logic Symbol. General Control Alternate Functions PORST TESTMODE ESR0 ESR1 16 TRST 14 16 TCK / DAP0 OCDS / JTAG Control Analog Inputs Analog Power Supply 16 TDI / BRKIN TDO / DAP2 / BRKOUT TMS / DAP1 4 16 AN[35:0] VD D M VSSM V D D MF V SSMF V D D AF VAR EF0 VAGN D 0 VFAR EF V FAGN D TC1782 / TC1182 VD D FL3 Digital Circuitry Power Supply VD D VD D P VSS 9 10 4 Port 0 Port 1 Port 2 Port 3 GPTA, SCU, E-RAY,1) MSC0 GPTA, SSC1, ADC0, OCDS GPTA, SSC0/1, MLI 0, MSC0 GPTA, ASC0/1, SSC0/1, SCU, CAN, MSC0 Port 4 GPTA, SCU, CAN Port 5 GPTA, MLI0, E-RAY, SSC2 Port 6 GPTA, MSC0 XTAL1 XTAL2 V D D OSC V D D OSC3 V SSOSC Oscillator 1) 11 1) Only available for SAK -TC1782 F-320 F180 HR and SAK -TC1782F-320F180 HL TC 1782_LQFP-176-10 Figure 4 Data Sheet TC1782 / TC1182 Logic Symbol 1 V 1.1, 2011-06 A N19 A N18 A N17 A N16 A N15 A N14 V AGND0 V AREF0 VSSM V DDM A N13 A N12 A N11 A N10 A N9 A N8 A N6 A N5 A N4 A N3 A N2 A N1 A N0 VDD V DDP V SS A D0E M UX 2/O UT1 8/IN1 8/P 1 .14 A D0E M UX 1/O UT1 7/IN1 7/P 1 .13 A D0E M UX 0/OU T1 6/IN1 6/P 1 .12 T CLK 0/ OUT 28/ OUT 32/I N32 /P 2.0 S LS O 13/ SL S O03 /OUT 33 /TRE A DY 0A /I N33/ P 2.1 T V A LID0 A/ OUT 29/ OUT 34/I N34/ P2 .2 T DA TA 0/ OUT 30/ OUT 35/I N35/ P2 .3 OUT 31 /OUT 36/ RCLK 0A /I N36/ P2 .4 RRE A DY 0A /O UT3 7/OU T1 10/I N37/ P2 .5 O UT3 8/O UT1 11/ RV AL ID0A /I N38/ P 2.6 OUT 39/ RDA TA 0A /I N39/ P 2.7 V SS V DDP VDD V SS OUT 52 /OUT 28 /IN52 /IN2 8/RX DCA N2/ P 4.0 O UT5 3/O UT2 9/IN5 3/I N29/ TX DCA N2/ P 4.1 E X T CLK 1/O UT5 4/O UT3 0/IN 54/I N30/ P 4.2 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 P 0.1 5/IN 15/R EQ 5/O UT1 5/S OP 0 C P 0.1 4/IN 14/R EQ 4/O UT1 4/F CLP 0C P 0.7 /IN7 /HW CF G7/RE Q 3/O UT7 /OUT 63 P 0.6 /IN6 /HW CF G6/RE Q 2/O UT6 /OUT 62 V SS V DDP V DD(SB) P 0.1 3/IN 13/O UT1 3/T X E NB P 0.1 2/IN 12/O UT1 2/T X E NA P 0.5 /IN5 /HW CF G5/O UT5 /OUT 61 P 0.4 /IN4 /HW CF G4/O UT4 /OUT 60 P 2.1 3/IN 13/O UT3 /S LS I1 1/S DI0 P 2.8 /S LS O0 4/S LS O 14/ EN0 0 P 2.1 2/IN 12/O UT2 /M TS R1A / SO P 0B P 2.1 1/IN 11/O UT1 /S CLK 1 A/ FCL P0 B P 2.1 0/IN 10/O UT0 /M RST 1A P 2.9 /S LS O0 5/S LS O 15/ EN0 1 P 6.3 /IN2 5/OUT 7/ OUT 83/ SO P 0A P 6.2 /IN2 4/OUT 6/ OUT 82/ SO N0 P 6.1 /IN1 5/OUT 5/ OUT 81/ FCL P0 A P 6.0 /IN1 4/OUT 4/ OUT 80/ FCL N0 V SS V DDP V DD P 0.1 1/IN 11/O UT1 1/T X DB 0 P 0.1 0/IN 10/O UT1 0/T X DA 0 P 0.9 /IN9 /RX DB 0/OU T9/ OUT 65 P 0.8 /IN8 /RX DA 0/OU T8/ OUT 64 P 0.3 /IN3 /HW CF G3/O UT3 /OUT 59 P 0.2 /IN2 /HW CF G2/O UT2 /OUT 58 P 0.1 /IN1 /HW CF G1/O UT1 /OUT 57 /S DI1 P 0.0 /IN0 /HW CF G0/O UT0 /OUT 56 P 3.1 1/O UT9 3/RE Q1 P 3.1 2/O UT9 4/RX DCA N0 /RX D0B P 3.1 3/O UT9 5/T X DCA N0/T X D0 V DDFL 3 V SS V DDP P 3.9 /OUT 91 /RX D1A P 3.1 0/O UT9 2/RE Q0 P 3.0 /OUT 84 /RX D0A P 3.1 /OUT 85 //T XD 0 P 3.1 4/O UT9 6/RX DCA N1 /RX D1B /S DI2 P 3.1 5/O UT9 7/T X DCA N1/T X D1 3.1 SLSCO 20 /OUT 40/ OUT 8/IN40 /IN 26/ P5 .0 SLSCO 21 /OUT 41 /OUT 9/IN 41/IN 27/ P5.1 SLSCO22 /OUT 42 /OUT 10 /IN 42/IN 28/ P5 .2 SLSCO 23/ OUT 43/OUT 11 /IN 43/ P5 .3 SLSCO24 /OUT 44 /OUT 12 /SLSI2AIN 44/IN 29/ P5 .4 M RST2A/OUT 45 /OUT 13 /IN 45/IN 30 /P5.5 M T SR2A/OUT 46 /OUT 14 /IN 46/IN 31/ P5 .6 SCLK2/ OUT 47/ OUT 15/IN 47/ P5.7 RXDB1/T CLK0/ OUT 95/P5 .15 VDD V DDP V SS T XDA1/RDAT A0B/OUT 89 /P5. 8 T XDB1 /RVALID0 B/OUT 90/ P5.9 T XENA/RREADY0B/OUT 91 /P5 .10 T XENB/ RCLK0B/OUT 92 /P5 .11 T DAT A0 /SLSO07 /OUT 93 /P5 .12 T VALID0B/SLSO16 /P5 .13 RXDA1/ T READY0B/OUT 94 /P5 .14 V DDP V DD(SB) V SS V DDAF VDDMF V SSMF VFAREF V FAGND AN35 AN34 AN33 AN32 AN31 AN30 AN29 AN28 AN7 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20 Figure 5 Data Sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 17 6 17 5 17 4 17 3 17 2 17 1 17 0 16 9 16 8 1 67 16 6 16 5 16 4 16 3 162 161 160 159 158 1 57 156 155 154 153 15 2 15 1 15 0 14 9 14 8 147 14 6 14 5 14 4 14 3 14 2 14 1 14 0 13 9 13 8 137 13 6 13 5 13 4 13 3 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration TC1782 / TC1182 Pin Configuration This chapter shows the pin configuration of the TC1782 / TC1182 package PG-LQFP176-10. TC1782 2 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 P3.4/ OUT 88/ M T SR0 P3.7/ SLSI01 /OUT 89 /SLSO02 /SLSO12 P3.3/ OUT 87/ M RST0 P3.2/ OUT 86/ SCLK0 P3.8/ SLSO06 /OUT 90 /T XD1 P3.6/ SLSO01 /SLSO11 /SLSO 01&SLSO 11 P3.5/ SLSO00 /SLSO10 /SLSO 00&SLSO 10 V SS V DDP V DD ESR0 PORST ESR1 P1 .1/IN 17/ OUT 17/ OUT 73 T EST M ODE P1 .15 /BRKIN/BRKOUT P1 .0/IN 16/ OUT 16/ OUT 72/BRKIN/ BRKOUT T CK/DAP0 T RST T DO/DAP2/BRKIN/BRKOUT T M S/DAP1 T DI/BRKIN/BRKOUT P1.7/ IN23 /OUT 23 /OUT 79 P1.6/ IN22 /OUT 22 /OUT 78 P1.5/ IN21 /OUT 21 /OUT 77 P1.4/ IN20 /EM GST OP/OUT 20 /OUT 76 V DDOSC3 V DDOSC V SSOSC XT AL2 XT AL1 V SS V DDP V DD P1.3 /IN19 /OUT 19 /OUT 75 P1.11 /IN27 /IN 51/SCLK 1B/OUT 27 /OUT 51 P1.10 /IN26 /IN 50/OUT 26 /OUT 50 /SLSO 17 P1.9/ IN25 /IN49 /M RST1 B/ OUT 25/OUT 49 P1.8/ IN24 /IN48 /M T SR1 B/ OUT 24/OUT 48 P1.2/ IN18 /OUT 18 /OUT 74 V SS V DD P4.3/ IN31 /IN55 /OUT 31 /OUT 55 /EXT CLK0 V DDP SAK_TC1782-320F180HR SAK-TC1782-320F180HR / SAK-TC1782-320F180HL Pinning V 1.1, 2011-06 A N19 A N18 A N17 A N16 A N15 A N14 V AGND0 V AREF 0 VSSM V DDM A N13 A N12 A N11 A N10 A N9 A N8 A N6 A N5 A N4 A N3 A N2 A N1 A N0 VDD V DDP V SS A D0E M UX 2/O UT1 8/IN1 8/P 1 .14 A D0E M UX 1/O UT1 7/IN1 7/P 1 .13 A D0E M UX 0/OU T1 6/IN1 6/P 1 .12 T CLK 0/ OUT 28/ OUT 32/I N32 /P 2.0 S LS O 13/ SL S O03 /OUT 33 /TRE A DY 0A /I N33/ P 2.1 T V A LID0 A/ OUT 29/ OUT 34/I N34/ P2 .2 T DA TA 0/ OUT 30/ OUT 35/I N35/ P2 .3 OUT 31 /OUT 36/ RCLK 0A /I N36/ P2 .4 RRE A DY 0A /O UT3 7/OU T1 10/I N37/ P2 .5 O UT3 8/O UT1 11/ RV AL ID0A /I N38/ P 2.6 OUT 39/ RDA TA 0A /I N39/ P 2.7 V SS V DDP VDD V SS OUT 52 /OUT 28 /IN52 /IN2 8/RX DCA N2/ P 4.0 O UT5 3/O UT2 9/IN5 3/I N29/ TX DCA N2/ P 4.1 E X T CLK 1/O UT5 4/O UT3 0/IN 54/I N30/ P 4.2 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 SLSCO 20 /OUT 40 /OUT 8/IN 40/ IN26 /P5.0 SLSCO21 /OUT 41 /OUT 9/IN 41/ IN27 /P5.1 SLSCO 22/ OUT 42/OUT 10 /IN 42/ IN28 /P5.2 SLSCO 23 /OUT 43/ OUT 11/ IN43 /P5.3 SLSCO24 /OUT 44 /OUT 12 /SLSI2A/IN 44/ IN29 /P5.4 M RST2 A/ OUT 45/ OUT 13/IN 45/ IN30 /P5.5 M T SR2 A/ OUT 46/OUT 14 /IN 46/ IN31 /P5.6 SCLK2 /OUT 47 /OUT 15/ IN47 /P5.7 T CLK0 /OUT 95/ P5 .15 V DD V DDP V SS RDAT A0B/OUT 89 /P5 .8 RVALID0 B/OUT 90 /P5.9 RREADY0B/ OUT 91/P5 .10 RCLK0B/ OUT 92/P5 .11 T DAT A0/SLSO 07/ OUT 93/P5 .12 T VALID0B/SLSO 16/P5 .13 T READY0B/ OUT 94/P5 .14 V DDP V DD(SB) V SS V DDAF V DDMF V SSMF V FAREF V FAGND AN35 AN34 AN33 AN32 AN31 AN30 AN29 AN28 AN7 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20 Figure 6 Data Sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 17 6 17 5 17 4 17 3 17 2 17 1 17 0 16 9 16 8 1 67 16 6 16 5 16 4 16 3 162 161 160 159 158 1 57 156 155 154 153 15 2 15 1 15 0 14 9 14 8 147 14 6 14 5 14 4 14 3 14 2 14 1 14 0 13 9 13 8 137 13 6 13 5 13 4 13 3 P 0.1 5/IN 15/R EQ 5/O UT1 5/S OP 0 C P 0.1 4/IN 14/R EQ 4/O UT1 4/F CLP 0C P 0.7 /IN7 /HW CF G7/RE Q 3/O UT7 /OUT 63 P 0.6 /IN6 /HW CF G6/RE Q 2/O UT6 /OUT 62 V SS V DDP V DD(SB) P 0.1 3/IN 13/O UT1 3 P 0.1 2/IN 12/O UT1 2 P 0.5 /IN5 /HW CF G5/O UT5 /OUT 61 P 0.4 /IN4 /HW CF G4/O UT4 /OUT 60 P 2.1 3/IN 13/O UT3 /S LS I1 1/S DI0 P 2.8 /S LS O0 4/S LS O 14/ EN0 0 P 2.1 2/IN 12/O UT2 /M TS R1A / SO P 0B P 2.1 1/IN 11/O UT1 /S CLK 1 A/ FCL P0 B P 2.1 0/IN 10/O UT0 /M RST 1A P 2.9 /S LS O0 5/S LS O 15/ EN0 1 P 6.3 /IN2 5/OUT 7/ OUT 83/ SO P 0A P 6.2 /IN2 4/OUT 6/ OUT 82/ SO N0 P 6.1 /IN1 5/OUT 5/ OUT 81/ FCL P0 A P 6.0 /IN1 4/OUT 4/ OUT 80/ FCL N0 V SS V DDP V DD P 0.1 1/IN 11/O UT1 1 P 0.1 0/IN 10/O UT1 0 P 0.9 /IN9 /OUT 9/O UT6 5 P 0.8 /IN8 /OUT 8/O UT6 4 P 0.3 /IN3 /HW CF G3/O UT3 /OUT 59 P 0.2 /IN2 /HW CF G2/O UT2 /OUT 58 P 0.1 /IN1 /HW CF G1/O UT1 /OUT 57 /S DI1 P 0.0 /IN0 /HW CF G0/O UT0 /OUT 56 P 3.1 1/O UT9 3/RE Q1 P 3.1 2/O UT9 4/RX DCA N0 /RX D0B P 3.1 3/O UT9 5/T X DCA N0/T X D0 V DDFL 3 V SS V DDP P 3.9 /OUT 91 /RX D1A P 3.1 0/O UT9 2/RE Q0 P 3.0 /OUT 84 /RX D0A P 3.1 /OUT 85 /TX D0 P 3.1 4/O UT9 6/RX DCA N1 /RX D1B /S DI2 P 3.1 5/O UT9 7/T X DCA N1/T X D1 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration TC1782 / TC1182 3 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 P3.4 /OUT 88 /M T SR0 P3.7 /SLSI01 /OUT 89 /SLSO02 /SLSO 12 P3.3 /OUT 87 /M RST0 P3.2 /OUT 86 /SCLK0 P3.8 /SLSO06 /OUT 90 /T XD1 P3.6 /SLSO01 /SLSO 11/SLSO 01 &SLSO 11 P3.5 /SLSO00 /SLSO 10/SLSO 00 &SLSO 10 V SS V DDP V DD ESR0 PORST ESR1 P1.1/ IN17 /OUT 17 /OUT 73 T EST M ODE P1 .15 /BRKIN/BRKOUT P1 .0/ IN16 /OUT 16/ OUT 72/ BRKIN/BRKOUT T CK/ DAP0 T RST T DO/DAP2/BRKIN/ BRKOUT T M S/DAP1 T DI/BRKIN/BRKOUT P1.7 /IN23 /OUT 23 /OUT 79 P1.6 /IN22 /OUT 22 /OUT 78 P1.5 /IN21 /OUT 21 /OUT 77 P1.4 /IN20 /EM GST OP/ OUT 20/OUT 76 V DDOSC3 V DDOSC V SSOSC XT AL2 XT AL1 V SS V DDP V DD P1.3 /IN19 /OUT 19 /OUT 75 P1.11 /IN27 /IN 51/ SCLK1B/OUT 27 /OUT 51 P1.10 /IN26 /IN 50/ OUT 26/ OUT 50/SLSO 17 P1.9 /IN25 /IN49 /M RST1 B/OUT 25/ OUT 49 P1.8 /IN24 /IN48 /M T SR1 B/OUT 24/ OUT 48 P1.2 /IN18 /OUT 18 /OUT 74 V SS V DD P4.3 /IN31 /IN55 /OUT 31 /OUT 55 /EXT CLK0 V DDP SAK_TC 1782-256F133HR SAK-TC1782N-320F180HR / SAK-TC1782N-320F180HL / SAK-TC1182N-320F180HR / SAK-TC1182N-320F180HL / SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL / SAK-TC1182N-256F133HR / SAK-TC1182N-256F133HL / SAK-TC1782F-256F133HR / SAK-TC1782F-256F133HL Pinning V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Pin Definitions and Functions (PG-LQFP-176-10 Package) Symbol Ctrl. Type Function A1/ PU Port 0 145 146 147 148 P0.0 I/O0 IN0 I Port 0 General Purpose I/O Line 0 IN0 I LTCA2 Input 0 HWCFG0 I Hardware Configuration Input 0 OUT0 O1 GPTA0 Output 0 OUT56 O2 GPTA0 Output 56 GPTA0 Input 0 OUT0 O3 P0.1 I/O0 LTCA2 Output 0 IN1 I IN1 I LTCA2 Input 1 SDI1 I MSC0 Serial Data Input 1 HWCFG1 I Hardware Configuration Input 1 OUT1 O1 GPTA0 Output 1 OUT57 O2 GPTA0 Output 57 A1/ PU Port 0 General Purpose I/O Line 1 GPTA0 Input 1 OUT1 O3 P0.2 I/O0 LTCA2 Output 1 IN2 I IN2 I LTCA2 Input 2 HWCFG2 I Hardware Configuration Input 2 OUT2 O1 GPTA0 Output 2 OUT58 O2 GPTA0 Output 58 OUT2 O3 LTCA2 Output 2 A1/ PU GPTA0 Input 2 P0.3 I/O0 IN3 I IN3 I LTCA2 Input 3 HWCFG3 I Hardware Configuration Input 3 OUT3 O1 GPTA0 Output 3 OUT59 O2 GPTA0 Output 59 OUT3 O3 LTCA2 Output 3 Data Sheet A1+/ PU Port 0 General Purpose I/O Line 2 Port 0 General Purpose I/O Line 3 GPTA0 Input 3 4 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 166 P0.4 I/O0 IN4 I A1/ PU IN4 I LTCA2 Input 4 HWCFG4 I Hardware Configuration Input 4 OUT4 O1 GPTA0 Output 4 OUT60 O2 GPTA0 Output 60 OUT4 O3 LTCA2 Output 4 167 173 174 GPTA0 Input 4 P0.5 I/O0 IN5 I IN5 I LTCA2 Input 5 HWCFG5 I Hardware Configuration Input 5 OUT5 O1 GPTA0 Output 5 OUT61 O2 GPTA0 Output 61 OUT5 O3 LTCA2 Output 5 P0.6 I/O0 IN6 I IN6 I LTCA2 Input 6 HWCFG6 I Hardware Configuration Input 6 REQ2 I External Request Input 2 OUT6 O1 GPTA0 Output 6 OUT62 O2 GPTA0 Output 62 OUT6 O3 LTCA2 Output 6 P0.7 I/O0 IN7 I IN7 I LTCA2 Input 7 HWCFG7 I Hardware Configuration Input 7 REQ3 I External Request Input 3 OUT7 O1 GPTA0 Output 7 OUT63 O2 GPTA0 Output 63 OUT7 O3 LTCA2 Output 7 Data Sheet A1/ PU Port 0 General Purpose I/O Line 4 A1/ PU A1/ PU Port 0 General Purpose I/O Line 5 GPTA0 Input 5 Port 0 General Purpose I/O Line 6 GPTA0 Input 6 Port 0 General Purpose I/O Line 7 GPTA0 Input 7 5 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 149 P0.8 I/O0 IN8 I A1/ PU IN8 I LTCA2 Input 8 RXDA0 I E-Ray Channel A Receive Data Input 0 1) OUT8 O1 GPTA0 Output 8 OUT64 O2 GPTA0 Output 64 OUT8 O3 LTCA2 Output 8 P0.9 I/O0 IN9 I 150 151 152 168 A1/ PU Port 0 General Purpose I/O Line 8 GPTA0 Input 8 Port 0 General Purpose I/O Line 9 GPTA0 Input 9 IN9 I LTCA2 Input 9 RXDB0 I E-Ray Channel B Receive Data Input 0 1) OUT9 O1 GPTA0 Output 9 OUT65 O2 GPTA0 Output 65 OUT9 O3 LTCA2 Output 9 P0.10 I/O0 IN10 I OUT10 O1 GPTA0 Output 10 TXDA0 O2 E-Ray Channel A transmit Data Output 1) OUT10 O3 LTCA2 Output 10 P0.11 I/O0 IN11 I OUT11 O1 GPTA0 Output 11 TXDB0 O2 E-Ray Channel B transmit Data Output 1) OUT11 O3 P0.12 I/O0 IN12 I OUT12 O1 GPTA0 Output 12 TXENA O2 E-Ray Channel A transmit Data Output enable A2/ PU A2/ PU Port 0 General Purpose I/O Line 10 GPTA0 Input 10 Port 0 General Purpose I/O Line 11 GPTA0 Input 11 LTCA2 Output 11 A2/ PU Port 0 General Purpose I/O Line 12 GPTA0 Input 12 1) OUT12 Data Sheet O3 LTCA2 Output 12 6 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 169 P0.13 I/O0 IN13 I A2/ PU OUT13 O1 GPTA0 Output 13 TXENB O2 E-Ray Channel B transmit Data Output enable Port 0 General Purpose I/O Line 13 GPTA0 Input 13 1) 175 176 OUT13 O3 LTCA2 Output 13 P0.14 I/O0 IN14 I REQ4 I External Request Input 4 OUT14 O1 GPTA0 Output 14 FCLP0C O2 MSC0 Clock Output Positive C OUT14 O3 LTCA2 Output 14 A1+/ PU A1+/ PU Port 0 General Purpose I/O Line 14 GPTA0 Input 14 P0.15 I/O0 IN15 I Port 0 General Purpose I/O Line 15 REQ5 I External Request Input 5 OUT15 O1 GPTA0 Output 15 SOP0C O2 MSC0 Serial Data Output Positive C OUT15 O3 LTCA2 Output 15 P1.0 I/O0 IN16 I BRKIN I Break Input OUT16 O1 GPTA0 Output 16 OUT72 O2 GPTA0 Output 72 OUT16 O3 LTCA2 Output 16 BRKOUT O Break Output (controlled by OCDS module) GPTA0 Input 15 Port 1 116 119 A2/ PU GPTA0 Input 16 P1.1 I/O0 IN17 I OUT17 O1 GPTA0 Output 17 OUT73 O2 GPTA0 Output 73 OUT17 O3 LTCA2 Output 17 Data Sheet A1/ PU Port 1 General Purpose I/O Line 0 Port 1 General Purpose I/O Line 1 GPTA0 Input 17 7 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 93 P1.2 I/O0 IN18 I A1/ PU OUT18 O1 GPTA0 Output 18 OUT74 O2 GPTA0 Output 74 98 107 108 109 Port 1 General Purpose I/O Line 2 GPTA0 Input 18 OUT18 O3 P1.3 I/O0 LTCA2 Output 18 IN19 I IN19 I LTCA2 Input 19 OUT19 O1 GPTA0 Output 19 OUT75 O2 GPTA0 Output 75 OUT19 O3 LTCA2 Output 19 P1.4 I/O0 IN20 I IN20 I LTCA2 Input 20 EMGSTOP I Emergency Stop Input OUT20 O1 GPTA0 Output 20 OUT76 O2 GPTA0 Output 76 A1/ PU A1/ PU Port 1 General Purpose I/O Line 3 GPTA0 Input 19 Port 1 General Purpose I/O Line 4 GPTA0 Input 20 OUT20 O3 P1.5 I/O0 LTCA2 Output 20 IN21 I IN21 I LTCA2 Input 21 OUT21 O1 GPTA0 Output 21 OUT77 O2 GPTA0 Output 77 A1/ PU Port 1 General Purpose I/O Line 35 GPTA0 Input 21 OUT21 O3 P1.6 I/O0 IN22 I IN22 I LTCA2 Input 22 OUT22 O1 GPTA0 Output 22 OUT78 O2 GPTA0 Output 78 OUT22 O3 LTCA2 Output 22 Data Sheet LTCA2 Output 21 A1/ PU Port 1 General Purpose I/O Line 6 GPTA0 Input 22 8 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 110 P1.7 I/O0 IN23 I A1/ PU IN23 I LTCA2 Input 23 OUT23 O1 GPTA0 Output 23 OUT79 O2 GPTA0 Output 79 OUT23 O3 LTCA2 Output 23 P1.8 I/O0 IN24 I IN48 I GPTA0 Input 48 MTSR1B I SSC1 Slave Receive Input B (Slave Mode) OUT24 O1 GPTA0 Output 24 OUT48 O2 GPTA0 Output 48 MTSR1B O3 P1.9 I/O0 IN25 I 94 95 96 A1+/ PU Port 1 General Purpose I/O Line 7 GPTA0 Input 23 Port 1 General Purpose I/O Line 8 GPTA0 Input 24 SSC1 Master Transmit Output B (Master Mode) A1+/ PU Port 1 General Purpose I/O Line 9 GPTA0 Input 25 IN49 I GPTA0 Input 49 MRST1B I SSC1 Master Receive Input B (Master Mode) OUT25 O1 GPTA0 Output 25 OUT49 O2 GPTA0 Output 49 MRST1B O3 SSC1 Slave Transmit Output B (Slave Mode) P1.10 I/O0 IN26 I IN50 I GPTA0 Input 50 OUT26 O1 GPTA0 Output 26 OUT50 O2 GPTA0 Output 50 SLSO17 O3 SSC1 Slave Select Output 7 Data Sheet A1+/ PU Port 1 General Purpose I/O Line 10 GPTA0 Input 26 9 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 97 P1.11 I/O0 IN27 I A1+/ PU IN51 I GPTA0 Input 51 SCLK1B I SSC1 Clock Input B OUT27 O1 GPTA0 Output 27 OUT51 O2 GPTA0 Output 51 SCLK1B O3 SSC1 Clock Output B 73 72 71 117 A1/ PU Port 1 General Purpose I/O Line 11 GPTA0 Input 27 P1.12 I/O0 IN16 I AD0EMUX0 O1 ADC0 External Multiplexer Control Output 0 AD0EMUX0 O2 ADC0 External Multiplexer Control Output 0 OUT16 O3 LTCA2 Output 16 A1/ PU Port 1 General Purpose I/O Line 12 LTCA2 Input 16 P1.13 I/O0 IN17 I AD0EMUX1 O1 ADC0 External Multiplexer Control Output 1 AD0EMUX1 O2 ADC0 External Multiplexer Control Output 1 OUT17 O3 LTCA2 Output 17 A1/ PU Port 1 General Purpose I/O Line 13 LTCA2 Input 17 P1.14 I/O0 IN18 I AD0EMUX2 O1 ADC0 External Multiplexer Control Output 2 AD0EMUX2 O2 ADC0 External Multiplexer Control Output 2 OUT18 O3 LTCA2 Output 18 P1.15 I/O0 BRKIN I Reserved O1 - Reserved O2 - Reserved O3 - BRKOUT O Break Output (controlled by OCDS module) A2/ PU Port 1 General Purpose I/O Line 14 LTCA2 Input 18 Port 1 General Purpose I/O Line 15 Break Input Port 2 Data Sheet 10 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 74 P2.0 I/O0 IN32 I A2/ PU OUT32 O1 GPTA0 Output 32 TCLK0 O2 MLI0 Transmitter Clock Output 0 75 76 77 78 Port 2 General Purpose I/O Line 0 GPTA0 Input 32 OUT28 O3 P2.1 I/O0 LTCA2 Output 28 IN33 I TREADY0A I MLI0 Transmitter Ready Input A OUT33 O1 GPTA0 Output 33 SLSO03 O2 SSC0 Slave Select Output Line 3 SLSO13 O3 SSC1 Slave Select Output Line 3 P2.2 I/O0 IN34 I OUT34 O1 GPTA0 Output 34 TVALID0 O2 MLI0 Transmitter Valid Output A2/ PU A2/ PU Port 2 General Purpose I/O Line 1 GPTA0 Input 33 Port 2 General Purpose I/O Line 2 GPTA0 Input 34 OUT29 O3 P2.3 I/O0 LTCA2 Output 29 IN35 I OUT35 O1 GPTA0 Output 35 TDATA0 O2 MLI0 Transmitter Data Output A2/ PU Port 2 General Purpose I/O Line 3 GPTA0 Input 35 OUT30 O3 P2.4 I/O0 IN36 I RCLK0A I MLI Receiver Clock Input A OUT36 O1 GPTA0 Output 36 OUT36 O2 GPTA0 Output 36 OUT31 O3 LTCA2 Output 31 Data Sheet LTCA2 Output 30 A2/ PU Port 2 General Purpose I/O Line 4 GPTA0 Input 36 11 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 79 P2.5 I/O0 IN37 I A2/ PU OUT37 O1 GPTA0 Output 37 RREADY0A O2 MLI0 Receiver Ready Output A OUT110 O3 P2.6 I/O0 IN38 I 80 81 164 160 Port 2 General Purpose I/O Line 5 GPTA0 Input 37 LTCA2 Output 110 A2/ PU Port 2 General Purpose I/O Line 6 GPTA0 Input 38 RVALID0A I MLI Receiver Valid Input A OUT38 O1 GPTA0 Output 38 OUT38 O2 GPTA0 Output 38 OUT111 O3 LTCA2 Output 111 P2.7 I/O0 IN39 I RDATA0A I MLI Receiver Data Input A OUT39 O1 GPTA0 Output 39 OUT39 O2 GPTA0 Output 39 Reserved O3 - A2/ PU GPTA0 Input 39 P2.8 I/O0 SLSO04 O1 SLSO14 O2 EN00 O3 P2.9 I/O0 SLSO05 O1 SLSO15 O2 SSC1 Slave Select Output 5 EN01 O3 MSC0 Enable Output 1 Data Sheet A2/ PU Port 2 General Purpose I/O Line 7 Port 2 General Purpose I/O Line 8 SSC0 Slave Select Output 4 SSC1 Slave Select Output 4 MSC0 Enable Output 0 A2/ PU Port 2 General Purpose I/O Line 9 SSC0 Slave Select Output 5 12 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 161 P2.10 I/O0 MRST1A I A1+/ PU IN10 I LTCA2 Input 10 MRST1A O1 SSC1 Slave Transmit Output OUT0 O2 LTCA2 Output 0 Reserved O3 - P2.11 I/O0 SCLK1A I IN11 I LTCA2 Input 11 SCLK1A O1 SSC1 Clock Output A OUT1 O2 LTCA2 Output 1 FCLP0B O3 MSC0 Clock Output Positive B 162 163 165 A1+/ PU A1+/ PU Port 2 General Purpose I/O Line 10 SSC1 Master Receive Input A Port 2 General Purpose I/O Line 11 SSC1 Clock Input A P2.12 I/O0 MTSR1A I Port 2 General Purpose I/O Line 12 IN12 I LTCA2 Input 12 MTSR1A O1 SSC1 Master Transmit Output A OUT2 O2 LTCA2 Output 2 SOP0B O3 P2.13 I/O0 SLSI11 I SSC1 Slave Receive Input A MSC0 Serial Data Output Positive B A1/ PU Port 2 General Purpose I/O Line 13 SSC1 Slave Select Input 1 SDI0 I MSC0 Serial Data Input 0 IN13 I LTCA2 Input 13 OUT3 O1 LTCA2 Output 3 Reserved O2 - Reserved O3 - Port 3 Data Sheet 13 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 136 P3.0 I/O0 RXD0A I A1+/ PU RXD0A O1 ASC0 Output (Sync. Mode) RXD0A O2 ASC0 Output (Sync. Mode) 135 129 130 132 126 Port 3 General Purpose I/O Line 0 ASC0 Receiver Input A (Async. & Sync. Mode) OUT84 O3 P3.1 I/O0 GPTA0 Output 84 TXD0 O1 TXD0 O2 ASC0 Output OUT85 O3 GPTA0 Output 85 A1+/ PU ASC0 Output P3.2 I/O0 SCLK0 I SCLK0 O1 SSC0 Clock Output (Master Mode) SCLK0 O2 SSC0 Clock Output (Master Mode) OUT86 O3 GPTA0 Output 86 P3.3 I/O0 MRST0 I MRST0 O1 SSC0 Slave Transmit Output (Slave Mode) MRST0 O2 SSC0 Slave Transmit Output (Slave Mode) OUT87 O3 GPTA0 Output 87 P3.4 I/O0 MTSR0 I MTSR0 O1 SSC0 Master Transmit Output (Master Mode) MTSR0 O2 SSC0 Master Transmit Output (Master Mode) OUT88 O3 P3.5 I/O0 SLSO00 O1 SLSO10 O2 SLSOANDO0 O3 Data Sheet A1+/ PU Port 3 General Purpose I/O Line 1 A1+/ PU A2/ PU Port 3 General Purpose I/O Line 2 SSC0 Clock Input (Slave Mode) Port 3 General Purpose I/O Line 3 SSC0 Master Receive Input (Master Mode) Port 3 General Purpose I/O Line 4 SSC0 Slave Receive Input (Slave Mode) GPTA0 Output 88 A1+/ PU Port 3 General Purpose I/O Line 5 SSC0 Slave Select Output 0 SSC1 Slave Select Output 0 SSC0 AND SSC1 Slave Select Output 0 14 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 127 P3.6 I/O0 SLSO01 O1 A1+/ PU SLSO11 O2 128 138 137 144 SSC0 Slave Select Output 1 SSC1 Slave Select Output 1 SLSOANDO1 O3 131 Port 3 General Purpose I/O Line 6 SSC0 AND SSC1 Slave Select Output 1 P3.7 I/O0 SLSI01 I SLSO02 O1 SSC0 Slave Select Output 2 SLSO12 O2 SSC1 Slave Select Output 2 OUT89 O3 GPTA0 Output 89 P3.8 I/O0 SLSO06 O1 TXD1 O2 A2/ PU A2/ PU Port 3 General Purpose I/O Line 7 SSC0 Slave Select Input 1 Port 3 General Purpose I/O Line 8 SSC0 Slave Select Output 6 ASC1 Transmit Output OUT90 O3 P3.9 I/O0 GPTA0 Output 90 RXD1A I RXD1A O1 ASC1 Receiver Output A (Synchronous Mode) RXD1A O2 ASC1 Receiver Output A (Synchronous Mode) OUT91 O3 P3.10 I/O0 REQ0 I Reserved O1 - Reserved O2 - OUT92 O3 GPTA0 Output 92 A1/ PU Port 3 General Purpose I/O Line 9 ASC1 Receiver Input A GPTA0 Output 91 A1/ PU External Request Input 0 P3.11 I/O0 REQ1 I Reserved O1 - Reserved O2 - OUT93 O3 GPTA0 Output 93 Data Sheet A1/ PU Port 3 General Purpose I/O Line 10 Port 3 General Purpose I/O Line 11 External Request Input 1 15 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 143 P3.12 I/O0 RXDCAN0 I A1/ PU RXD0B I ASC0 Receiver Input B RXD0B O1 ASC0 Receiver Output B (Synchronous Mode) RXD0B O2 ASC0 Receiver Output B (Synchronous Mode) OUT94 O3 GPTA0 Output 94 P3.13 I/O0 TXDCAN0 O1 TXD0 O2 OUT95 O3 P3.14 I/O0 RXDCAN1 I RXD1B I ASC1 Receiver Input B SDI2 I MSC0 Serial Data Input 2 RXD1B O1 ASC1 Receiver Output B (Synchronous Mode) RXD1B O2 ASC1 Receiver Output B (Synchronous Mode) OUT96 O3 GPTA0 Output 96 142 134 133 A2/ PU Port 3 General Purpose I/O Line 12 CAN Node 0 Receiver Input Port 3 General Purpose I/O Line 13 CAN Node 0 Transmitter Output ASC0 Transmit Output GPTA0 Output 95 A1/ PU A2/ PU Port 3 General Purpose I/O Line 14 CAN Node 1 Receiver Input P3.15 I/O0 TXDCAN1 O1 Port 3 General Purpose I/O Line 15 TXD1 O2 ASC1 Transmit Output OUT97 O3 GPTA0 Output 97 P4.0 I/O0 IN28 I IN52 I GPTA0 Input 52 RXDCAN2 I CAN Node 2 Receiver Input OUT28 O1 GPTA0 Output 28 OUT52 O2 GPTA0 Output 52 Reserved O3 - CAN Node 1 Transmitter Output Port 4 86 Data Sheet A1+/ PU Port 4 General Purpose I/O Line 0 GPTA0 Input 28 16 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 87 P4.1 I/O0 IN29 I A1+/ PU IN53 I GPTA0 Input 53 OUT29 O1 GPTA0 Output 29 OUT53 O2 GPTA0 Output 53 TXDCAN2 O3 CAN Node 2 Transmitter Output P4.2 I/O0 IN30 I IN54 I GPTA0 Input 54 OUT30 O1 GPTA0 Output 30 OUT54 O2 GPTA0 Output 54 EXTCLK1 O3 External Clock 1 Output 88 90 A2/ PU A2/ PU Port 4 General Purpose I/O Line 1 GPTA0 Input 29 Port 4 General Purpose I/O Line 2 GPTA0 Input 30 P4.3 I/O0 IN31 I Port 4 General Purpose I/O Line 3 IN55 I GPTA0 Input 55 OUT31 O1 GPTA0 Output 31 OUT55 O2 GPTA0 Output 55 EXTCLK0 O3 External Clock 0 Output P5.0 I/O0 IN40 I IN26 I LTCA2 Input 26 OUT40 O1 GPTA0 Output 40 OUT8 O2 LTCA2 Output 8 SLSO20 O3 SSC2 Slave Select Output 0 GPTA0 Input 31 Port 5 1 Data Sheet A1+/ PU Port 5 General Purpose I/O Line 0 GPTA0 Input 40 17 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 2 P5.1 I/O0 IN41 I A1+/ PU IN27 I LTCA2 Input 27 OUT41 O1 GPTA0 Output 41 OUT9 O2 LTCA2 Output 9 SLSO21 O3 SSC2 Slave Select Output 1 P5.2 I/O0 IN42 I IN28 I LTCA2 Input 28 OUT42 O1 GPTA0 Output 42 OUT10 O2 LTCA2 Output 10 SLSO22 O3 SSC2 Slave Select Output 2 P5.3 I/O0 IN43 I OUT43 O1 GPTA0 Output 43 OUT11 O2 LTCA2 Output 11 SLSO23 O3 SSC2 Slave Select Output 3 P5.4 I/O0 IN44 I IN29 I LTCA2 Input 29 SLSI2A I SSC2 Slave Select Input A OUT44 O1 GPTA0 Output 44 OUT12 O2 LTCA2 Output 12 SLSO24 O3 SSC2 Slave Select Output 4 3 4 5 Data Sheet A1+/ PU A1+/ PU A1+/ PU Port 5 General Purpose I/O Line 1 GPTA0 Input 41 Port 5 General Purpose I/O Line 2 GPTA0 Input 42 Port 5 General Purpose I/O Line 3 GPTA0 Input 43 Port 5 General Purpose I/O Line 4 GPTA0 Input 44 18 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 6 P5.5 I/O0 IN45 I A1+/ PU IN30 I LTCA2 Input 30 MRST2A I SSC2 Master Receive Input (Master Mode) OUT45 O1 GPTA0 Output 45 OUT13 O2 LTCA2 Output 13 MRST2 O3 SSC2 Master Transmit Input (Slave Mode) P5.6 I/O0 IN46 I 7 8 13 14 A1+/ PU Port 5 General Purpose I/O Line 5 GPTA0 Input 45 Port 5 General Purpose I/O Line 6 GPTA0 Input 46 IN31 I LTCA2 Input 31 MTSR2A I SSC2 Slave Receive Input (Slave Mode) OUT46 O1 GPTA0 Output 46 OUT14 O2 LTCA2 Output 14 MTSR2 O3 SSC2 Master Transmit Output (Master Mode) P5.7 I/O0 A1+/ PU Port 5 General Purpose I/O Line 7 IN47 I SCLK2A I SSC2 Clock Input (Slave Mode) OUT47 O1 GPTA0 Output 47 OUT15 O2 LTCA2 Output 15 SCLK2 O3 SSC2 Clock Output (Master Mode) A2/ PU GPTA0 Input 47 P5.8 I/O0 RDATA0B I Reserved O1 - TXDA1 O2 E-Ray Channel A transmit Data Output 1) OUT89 O3 LTCA2 Output 89 MLI0 Receiver Data Input B P5.9 I/O0 RVALID0B I Reserved O1 - TXDB1 O2 E-Ray Channel B transmit Data Output 1) OUT90 O3 LTCA2 Output 90 Data Sheet A2/ PU Port 5 General Purpose I/O Line 8 Port 5 General Purpose I/O Line 9 MLI0 Receiver Data Valid Input B 19 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 15 P5.10 I/O0 RREADY0B O1 A2/ PU TXENA O2 Port 5 General Purpose I/O Line 10 MLI0 Receiver Ready Input B E-Ray Channel A transmit Data Output enable 1) 16 OUT91 O3 P5.11 I/O0 RCLK0B I LTCA2 Output 91 A2/ PU Port 5 General Purpose I/O Line 11 MLI0 Receiver Clock Input B Reserved O1 - TXENB O2 E-Ray Channel B transmit Data Output enable 1) 17 18 19 9 OUT92 O3 P5.12 I/O0 LTCA2 Output 92 TDATA0 O1 SLSO07 O2 SSC0 Slave Select Output 7 OUT93 O3 LTCA2 Output 93 A1+/ PU A1+/ PU Port 5 General Purpose I/O Line 12 MLI0 Transmitter Data Output P5.13 I/O0 TVALID0B O1 Port 5 General Purpose I/O Line 13 SLSO16 O2 Reserved O3 P5.14 I/O0 TREADY0B I RXDA1 I E-Ray Channel A Receive Data Input 1 1) Reserved O1 - Reserved O2 - OUT94 O3 LTCA2 Output 94 P5.15 I/O0 RXDB1 I TCLK0 O1 MLI0 Transmitter Clock Output Reserved O2 - OUT95 O3 LTCA2 Output 95 MLI0 Transmitter Valid Input B SSC1 Slave Select Output 6 - A1+/ PU A1+/ PU Port 5 General Purpose I/O Line 14 MLI0 Transmitter Ready Input B Port 5 General Purpose I/O Line 15 E-Ray Channel B Receive Data Input 1 1) Port 6 Data Sheet 20 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 156 P6.0 I/O0 IN14 I FCLN0 O1 A1/ F/ PU OUT80 O2 157 158 159 OUT4 O3 P6.1 I/O0 IN15 I FCLP0A O1 OUT81 O2 Port 6 General Purpose I/O Line 0 LTCA2 Input 14 MSC0 Clock Output Negative GPTA0 Output 80 LTCA2 Output 4 A1/ F/ PU Port 6 General Purpose I/O Line 1 LTCA2 Input 15 MSC0 Clock Output Positive A GPTA0 Output 81 OUT5 O3 P6.2 I/O0 IN24 I SON0 O1 OUT82 O2 GPTA0 Output 82 OUT6 O3 LTCA2 Output 6 P6.3 I/O0 IN25 I LTCA2 Output 5 A1/ F/ PU A1/ F/ PU Port 6 General Purpose I/O Line 2 LTCA2 Input 24 MSC0 Serial Data Output Negative Port 6 General Purpose I/O Line 3 LTCA2 Input 25 SOP0A O1 OUT83 O2 MSC0 Serial Data Output Positive A GPTA0 Output 83 OUT7 O3 LTCA2 Output 7 Analog Input Port 67 AN0 I D ADC0 Analog Input Channel 0 66 AN1 I D ADC0 Analog Input Channel 1 65 AN2 I D ADC0 Analog Input Channel 2 64 AN3 I D ADC0 Analog Input Channel 3 63 AN4 I D ADC0 Analog Input Channel 4 62 AN5 I D ADC0 Analog Input Channel 5 61 AN6 I D ADC0 Analog Input Channel 6 36 AN7 I D ADC0 Analog Input Channel 7 60 AN8 I D ADC0 Analog Input Channel 8 Data Sheet 21 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 59 AN9 I D ADC0 Analog Input Channel 9 58 AN10 I D ADC0 Analog Input Channel 10 57 AN11 I D ADC0 Analog Input Channel 11 56 AN12 I D ADC0 Analog Input Channel 12 55 AN13 I D ADC0 Analog Input Channel 13 50 AN14 I D ADC0 Analog Input Channel 14 49 AN15 I D ADC0 Analog Input Channel 15 48 AN16 I D ADC1 Analog Input Channel 16 47 AN17 I D ADC1 Analog Input Channel 17 46 AN18 I D ADC1 Analog Input Channel 18 45 AN19 I D ADC1 Analog Input Channel 19 44 AN20 I D ADC1 Analog Input Channel 20 43 AN21 I D ADC1 Analog Input Channel 21 42 AN22 I D ADC1 Analog Input Channel 22 41 AN23 I D ADC1 Analog Input Channel 23 40 AN24 I D ADC1 Analog Input Channel 24 39 AN25 I D ADC1 Analog Input Channel 25 38 AN26 I D ADC1 Analog Input Channel 26 37 AN27 I D ADC1 Analog Input Channel 27 35 AN28 I D ADC1 / FADC Analog Input Channel 28 34 AN29 I D ADC1 / FADC Analog Input Channel 29 33 AN30 I D ADC1 / FADC Analog Input Channel 30 32 AN31 I D ADC1 / FADC Analog Input Channel 31 31 AN32 I D FADC Analog Input P Channel 0 30 AN33 I D FADC Analog Input N Channel 0 29 AN34 I D FADC Analog Input P Channel 1 28 AN35 I D FADC Analog Input N Channel 1 54 VDDM VSSM VAREF0 - - ADC Analog Part Power Supply (3.3V - 5V) - - ADC Analog Part Ground - - ADC0 and ADC1 Reference Voltage 53 52 Data Sheet 22 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 51 VAGND0 VDDMF VDDAF VSSMF VSSAF VFAREF VFAGND VDD - - ADC Reference Ground - - FADC Analog Part Power Supply (3.3V) - - FADC Analog Part Logic Power Supply (1.3V) - - FADC Analog Part Ground - - FADC Analog Part Ground - - FADC Reference Voltage - - FADC Reference Ground - - Digital Core Power Supply (1.3V) VDDP - - Port Power Supply (3.3V) 24 23 25 26 27 10, 212), 68, 84, 91, 99, 123, 153, 170 2) 11, 20, 69, 83, 89, 100, 124, 139, 154, 171 Data Sheet 23 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 12, 22, 70, 82, 85, 92, 101, 125, 140, 155, 172 VSS - - Digital Ground 105 - - Main Oscillator and PLL Power Supply (1.3V) - - Main Oscillator Power Supply (3.3V) - - Main Oscillator and PLL Ground 141 VDDOSC VDDOSC3 VSSOSC VDDFL3 - - Power Supply for Flash (3.3V) 102 XTAL1 I Main Oscillator Input 103 XTAL2 O Main Oscillator Output 111 TDI I 106 104 A2/ PU JTAG Serial Data Input BRKIN I BRKOUT O TMS I DAP1 I/O TDO I/O DAP2 I/O BRKIN I OCDS Break Input Line BRKOUT O OCDS Break Output Line 114 TRST I I/ PD JTAG Reset Input 115 TCK I JTAG Clock Input DAP0 I A1/ PD 118 TESTMODE I I/ PU Test Mode Select Input 120 ESR1 I/O A2/ PD External System Request Reset Input 1 112 113 Data Sheet OCDS Break Input Line OCDS Break Output Line A2/ PD JTAG State Machine Control Input A2/ PU JTAG Serial Data Output Device Access Port Line 1 Device Access Port Line 2 Device Access Port Line 0 24 V 1.1, 2011-06 TC1782 / TC1182 PinningTC1782 / TC1182 Pin Configuration Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont'd) Pin Symbol Ctrl. Type Function 121 PORST I I/ PD Power On Reset Input 122 ESR0 I/O A2 External System Request Reset Input 0 Default configuration during and after reset is open-drain driver. The driver drives low during power-on reset. 1) Only available for SAK-TC1782F-320F180HR and SAK-TC1782F-320F180HL. 2) For the emulation device (ED), this pin is bonded to VDDSB (ED Stand By RAM supply). In the production devide device, this pin is bonded to a VDD pad. Legend for Table 2 Column "Ctrl.": I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXXB) O = Output O0 = Output with IOCR bit field selection PCx = 1X00B O1 = Output with IOCR bit field selection PCx = 1X01B (ALT1) O2 = Output with IOCR bit field selection PCx = 1X10B(ALT2) O3 = Output with IOCR bit field selection PCx = 1X11(ALT3) Column "Type": A1 = Pad class A1 (LVTTL) A1+ = Pad class A1+ (LVTTL) A2 = Pad class A2 (LVTTL) F = Pad class F (LVDS/CMOS) D = Pad class D (ADC) I = Pad class I (LVTTL) PU = with pull-up device connected during reset (PORST = 0) PD = with pull-down device connected during reset (PORST = 0) TR = tri-state during reset (PORST = 0) Data Sheet 25 V 1.1, 2011-06 TC1782 / TC1182 Identification Registers 4 Identification Registers The Identification Registers uniquely identify the whole device. Table 3 SAK-TC1782F-320F180HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H BA CBS_JTAGID 1018 E083H F000 0464H BA SCU_CHIPID 8500 9310H F000 0640H BA SCU_MANID 0000 1820H F000 0644H BA SCU_RTID 0000 0000H F000 0648H BA Table 4 SAK-TC1782F-320F180HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H BA CBS_JTAGID 1018 E083H F000 0464H BA SCU_CHIPID 0500 9310H F000 0640H BA SCU_MANID 0000 1820H F000 0644H BA SCU_RTID 0000 0000H F000 0648H BA Table 5 SAK-TC1782F-256F133HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H BA CBS_JTAGID 1018 E083H F000 0464H BA SCU_CHIPID 9400 9310H F000 0640H BA SCU_MANID 0000 1820H F000 0644H BA SCU_RTID 0000 0000H F000 0648H BA Table 6 SAK-TC1782F-256F133HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H BA CBS_JTAGID 1018 E083H F000 0464H BA SCU_CHIPID 1400 9310H F000 0640H BA Data Sheet 1 V 1.1, 2011-06 TC1782 / TC1182 Identification Registers Table 6 SAK-TC1782F-256F133HL Identification Registers (cont'd) Short Name Value Address Stepping SCU_MANID 0000 1820H F000 0644H BA SCU_RTID 0000 0000H F000 0648H BA Table 7 SAK-TC1782N-320F180HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H BA CBS_JTAGID 1018 E083H F000 0464H BA SCU_CHIPID 8500 9410H F000 0640H BA SCU_MANID 0000 1820H F000 0644H BA SCU_RTID 0000 0000H F000 0648H BA Table 8 SAK-TC1782N-320F180HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H BA CBS_JTAGID 1018 E083H F000 0464H BA SCU_CHIPID 0500 9410H F000 0640H BA SCU_MANID 0000 1820H F000 0644H BA SCU_RTID 0000 0000H F000 0648H BA Table 9 SAK-TC1782N-256F133HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H BA CBS_JTAGID 1018 E083H F000 0464H BA SCU_CHIPID 9400 9410H F000 0640H BA SCU_MANID 0000 1820H F000 0644H BA SCU_RTID 0000 0000H F000 0648H BA Data Sheet 2 V 1.1, 2011-06 TC1782 / TC1182 Identification Registers Table 10 SAK-TC1782N-256F133HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H BA CBS_JTAGID 1018 E083H F000 0464H BA SCU_CHIPID 1400 9410H F000 0640H BA SCU_MANID 0000 1820H F000 0644H BA SCU_RTID 0000 0000H F000 0648H BA Table 11 SAK-TC1182N-320F180HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H BA CBS_JTAGID 1018 E083H F000 0464H BA SCU_CHIPID 8500 B210H F000 0640H BA SCU_MANID 0000 1820H F000 0644H BA SCU_RTID 0000 0000H F000 0648H BA Table 12 SAK-TC1182N-320F180HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H BA CBS_JTAGID 1018 E083H F000 0464H BA SCU_CHIPID 0500 B210H F000 0640H BA SCU_MANID 0000 1820H F000 0644H BA SCU_RTID 0000 0000H F000 0648H BA Table 13 SAK-TC1182N-256F133HR Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H BA CBS_JTAGID 1018 E083H F000 0464H BA SCU_CHIPID 9400 B210H F000 0640H BA SCU_MANID 0000 1820H F000 0644H BA SCU_RTID 0000 0000H F000 0648H BA Data Sheet 3 V 1.1, 2011-06 TC1782 / TC1182 Identification Registers Table 14 SAK-TC1182N-256F133HL Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350H F000 0408H BA CBS_JTAGID 1018 E083H F000 0464H BA SCU_CHIPID 1400 B210H F000 0640H BA SCU_MANID 0000 1820H F000 0644H BA SCU_RTID 0000 0000H F000 0648H BA Data Sheet 4 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersGeneral Parameters 5 Electrical Parameters This specification provides all electrical parameters of the TC1782 / TC1182. 5.1 General Parameters 5.1.1 Parameter Interpretation The parameters listed in this section partly represent the characteristics of the TC1782 / TC1182 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column "Symbol": * * CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC1782 / TC1182 and must be regarded for a system design. SR Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC1782 / TC1182 designed in. Data Sheet 1 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersGeneral Parameters 5.1.2 Pad Driver and Pad Classes Summary This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1. Table 15 Pad Driver and Pad Classes Overview Sub Class Speed Load Grade A A1 (e.g. GPIO) 6 MHz 100 pF 500 nA A1+ (e.g. serial I/Os) 25 MHz 50 pF 1 A Series termination recommended A2 (e.g. serial I/Os) 40 MHz 50 pF 3 A Series termination recommended LVDS - 50 MHz - - Parallel termination, 100 10% 1) CMOS - 6 MHz 50 pF - F 3.3 V 3.3 V LVTTL I/O, LVTTL outputs Leakage 150oC Termination Class Power Type Supply DE 5V ADC - - - - I 3.3 V LVTTL (input only) - - - - No 1) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or properly terminated with the differential parallel termination of 100 10%. Data Sheet 2 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersGeneral Parameters 5.1.3 Absolute Maximum Ratings Stresses above the values listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 16 Absolute Maximum Rating Parameters Parameter Symbol Values Min. Typ. Max. Unit Note / Test Con dition SR -65 - 150 C - SR - - 2.0 V - - - 4.3 V - SR - - 7.0 V - VDDP + 0.5 or max. 4.3 V Whatever is lower -0.5 - 7.0 V - Voltage on any shared Class VAINF -0.5 - D analog input pin with SR respect to VSSAF, if the FADC is switched through to the pin. 7.0 V - TST Voltage at 1.3 V power supply VDD pins with respect to VSS Voltage at 3.3 V power supply VDDP pins with respect to VSS SR Voltage at 5 V power supply VDDM pins with respect to VSS Voltage on any Class A input VIN Storage temperature SR -0.5 - pin and dedicated input pins with respect to VSS Voltage on any Class D analog input pin with respect to VAGND0 VAIN VAREF0 SR IIN -10 - +10 mA Absolute maximum sum of all IIN input circuit currents for one port group during overload condition1) -25 - +25 mA Absolute maximum sum of all IIN input circuit currents during overload condition - - |200| mA Input current on any pin during overload condition 1) The port groups are defined in Table 21. Data Sheet 3 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersGeneral Parameters 5.1.4 Pin Reliability in Overload When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification. Table 17 defines overload conditions that will not cause any negative reliability impact if all the following conditions are met: * * full operation life-time (24000 h) is not exceeded Operating Conditions are met for - pad supply levels - temperature If a pin current is out of the Operating Conditions but within the overload parameters, then the parameters functionality of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters. Note: An overload condition on one or more pins does not require a reset. Table 17 Overload Parameters Parameter Symbol Input current on any digital pin IIN during overload condition except LVDS pins Input current on LVDS pins Absolute sum of all input circuit currents for one port group during overload condition1) Input current on analog pins Absolute sum of all analog input currents for analog inputs of a single ADC during overload condition Absolute sum of all input circuit currents during overload condition Min. Typ. Max. Values Unit Note / Test Con dition -5 mA - +5 IINLVDS IING -3 - +3 mA -20 - +20 mA IINANA IINSAS -3 - +3 mA -15 - +15 mA IINS -100 - 100 mA 1) The port groups are defined in Table 21. Note: FADC input pins count as analog pin as they are overlayed with an ADC pins. Data Sheet 4 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersGeneral Parameters Table 18 PN-Junction Characterisitics for positive Overload Pad Type IIN = 3 mA IIN = 5 mA A1 / A1+ / F UIN = VDDP + 0.6 V UIN = VDDP + 0.5 V UIN = VDDP + 0.7 V UIN = VDDP + 0.6 V UIN = VDDP + 0.7 V UIN = VDDP + 0.6 V A2 LVDS D Table 19 - PN-Junction Characterisitics for negative Overload Pad Type IIN = -3 mA IIN = -5 mA A1 / A1+ / F UIN = VSS - 0.6 V UIN = VSS - 0.5 V UIN = VSS - 0.7 V UIN = VSS - 0.6 V UIN = VSS - 0.7 V UIN = VSS - 0.6 V A2 LVDS D Data Sheet - 5 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersGeneral Parameters 5.1.5 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the TC1782 / TC1182. Digital supply voltages applied to the TC1782 / TC1182 must be static regulated voltages which allow a typical voltage swing of 5 %. All parameters specified in the following tables refer to these operating conditions (Table 20), unless otherwise noticed in the Note / Test Condition column. The Extended Range Operating Conditions did not increase area of validity of the parameters defined in table 8 and later. Table 20 Parameter Operating Conditions Parameters Symbol Overload coupling factor KOVAN for analog inputs, negative CC Values Unit Min. Typ. Max. - - 0.0001 Note / Test Condition IOV 0 mA; IOV -1 mA; analog pad= 5.0 V Overload coupling factor KOVAP for analog inputs, positive CC - - 0.0000 1 IOV 3 mA; IOV 0 mA; analog pad= 5.0 V Data Sheet 6 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersGeneral Parameters Table 20 Operating Conditions Parameters (cont'd) Parameter Symbol Values Min. CPU Frequency FPI bus frequency Data Sheet Unit Note / Test Condition Typ. Max. fCPU SR - - 133 MHz SAK-TC1782F256F133HR / S AK-TC1782F256F133HL / S AK-TC1782N256F133HR / S AK-TC1782N256F133HL / S AK-TC1182N256F133HR / S AK-TC1182N256F133HL - - 180 MHz SAK-TC1782F320F180HR / S AK-TC1782F320F180HL / S AK-TC1782N320F180HR / S AK-TC1782N320F180HL / S AK-TC1182N320F180HR / S AK-TC1182N320F180HL - - 90 MHz fFPI SR 7 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersGeneral Parameters Table 20 Operating Conditions Parameters (cont'd) Parameter Symbol Values Min. LMB frequency Data Sheet Unit Note / Test Condition Typ. Max. fLMB CC - - 133 MHz SAK-TC1782F256F133HR / S AK-TC1782F256F133HL / S AK-TC1782N256F133HR / S AK-TC1782N256F133HL / S AK-TC1182N256F133HR / S AK-TC1182N256F133HL - - 180 MHz SAK-TC1782F320F180HR / S AK-TC1782F320F180HL / S AK-TC1782N320F180HR / S AK-TC1782N320F180HL / S AK-TC1182N320F180HR / S AK-TC1182N320F180HL 8 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersGeneral Parameters Table 20 Operating Conditions Parameters (cont'd) Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. fPCP SR - - 133 MHz SAK-TC1782F256F133HR / S AK-TC1782F256F133HL / S AK-TC1782N256F133HR / S AK-TC1782N256F133HL / S AK-TC1182N256F133HR / S AK-TC1182N256F133HL - - 180 MHz SAK-TC1782F320F180HR / S AK-TC1782F320F180HL / S AK-TC1782N320F180HR / S AK-TC1782N320F180HL / S AK-TC1182N320F180HR / S AK-TC1182N320F180HL Inactive device pin current IID SR -1 - 1 mA Short circuit current of digital outputs1) ISC SR -5 - 5 mA Absolute sum of short circuit currents of the device ISC_D CC - - 100 mA Absolute sum of short circuit currents per pin group ISC_PG CC - - 20 mA Ambient Temperature TA SR -40 - 125 C PCP Frequency Data Sheet 9 All power supply voltagesVDDx = 0 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersGeneral Parameters Table 20 Operating Conditions Parameters (cont'd) Parameter Symbol Values Min. Unit Typ. Max. Junction temperature - 150 Core Supply Voltage 1.3 1.3652) V 3.3 3.474) V 3.13 3.3 5.53) V 1.235 1.3 1.3652) V 3.3 3.474) TJ SR -40 VDD SR 1.235 3.13 Flash supply voltage 3.3V VDDFL3 Note / Test Condition C SR ADC analog supply voltage VDDM Oscillator core supply voltage VDDOSC Oscillator 3.3V supply voltage SR SR VDDOSC3 3.05 V SR Digital supply voltage for IO pads VDDP SR 3.13 3.3 3.47 4) V VDDP voltage to ensure defined pad states5) VDDPPA - - V - - V 0 0.1 V 1.3 1.3652) V 3.13 3.3 3.474) V -0.1 0 0.1 V 0.65 CC VSS SR 0 Analog ground voltage for VSSM SR -0.1 VDDM Analog core supply VDDAF 1.235 Digital ground voltage SR FADC / ADC analog supply voltage VDDMF SR Analog ground voltage for VSSAF SR VDDMF 1) Applicable for digital outputs. 2) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 3) Voltage overshoot to 6.5V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 4) Voltage overshoot to 4.0V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 5) This parameter is valid under the assumption the PORST signal is constantly at low level during the powerup/power-down of VDDP. Extended Range Operating Conditions The following extended operating conditions are defined: Data Sheet 10 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersGeneral Parameters * * * 1.3V + 5% < VDD / VDDOSC / VDDAF < 1.3V + 7.5% (overvoltage condition): - limited to 10000 hour duration cumulative in lifetime, due to the reliability reduction of the chip caused by the overvoltage stress. 1.3V + 7.5% < VDD / VDDOSC / VDDAF < 1.3V + 10% (overvoltage condition): - limited to 1 hour duration cumulative in lifetime, due to the reliability reduction of the chip caused by the overvoltage stress. VDDP / VDDOSC3 / VDDFL3 / VDDMF< 3.3 V 10% - 3.3V + 5% < VDDP / VDDOSC3 / VDDFL3 / VDDMF< 3.3V + 10% (overvoltage condition): limited to 1 hour duration cumulative in lifetime, due to the reliability reduction of the chip caused by the overvoltage stress. - 3.3V - 10% < VDDP / VDDOSC3 / VDDFL3 / VDDMF< 3.3 V - 5% (undervoltage condition): -reduces GPIO pads performance Table 21 Pin Groups for Overload / Short-Circuit Current Sum Parameter Group Pins 1 P5.[7:2], P5.15 2 P5.[9:8] 3 P5.[11:10] 4 P5.[14:12] 5 P1.[14:12], P2.0 6 P2.[4:1] 7 P2.[7:5] 8 P4.[2:0] 9 P4.3 10 P1.2, P1.8 11 P1.[10:9] 12 P1.3, P1.11 13 P1.[7:4] 14 P1.[1:0], P1.15 15 P3.[8:5], P3.[3:2] 16 P3.[1:0], P3.4, P3.[10:9], P3.[15:14] Data Sheet 11 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersGeneral Parameters Table 21 Pin Groups for Overload / Short-Circuit Current Sum Parameter Group Pins 17 P0.[1:0], P3.[13:11] 18 P0.[3:2], P0.[9:8] 19 P0.[11:10] 20 P6.[3:0] 21 P2.[13:8] 22 P0.[5:4], P0.[13:12] 23 P0.[7:6], P0.[15:14], P5.[1:0] Data Sheet 12 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters 5.2 DC Parameters 5.2.1 Input/Output Pins Table 22 Standard_Pads Parameters Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition TA= 25 C; f= 1 MHz Vi 0.6 x VDDP V Vi 0.36 x VDDP V Vi 0.6 x VDDP V Vi 0.36 x VDDP V Pin capacitance (digital inputs/outputs) CIO CC - - 10 pF Pull-down current |IPDL| CC - - 150 A 10 - - A |IPUH| CC 10 - - A - - 100 A - - 10 ns only PORST pin 100 - - ns only PORST pin Unit Note / Test Condition Pull-Up current Spike filter always blocked tSF1 CC pulse duration Spike filter pass-through pulse duration Table 23 tSF2 CC Standard_Pads Class_A1 Parameter Input Hysteresis for A1 pads 1) Input Leakage Current Class A1 Ratio Vil/Vih, A1 pads Symbol Values Min. Typ. Max. HYSA1 0.1 x - - V CC VDDP IOZA1 -500 - 500 nA 0.6 - - - 450 600 Ohm IOH< -0.5 mA; P_MOS - 210 340 Ohm IOL< 0.5 mA; N_MOS CC VILA1 / VIHA1 Vi 0 V; Vi VDDP V CC On-Resistance of the RDSONW class A1 pad, weak driver CC Data Sheet 13 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 23 Standard_Pads Class_A1 (cont'd) Parameter Symbol RDSONM On-Resistance of the class A1 pad, medium driver CC Fall time, pad type A1 tFA1 CC Values Unit Note / Test Condition Min. Typ. Max. - - 155 Ohm IOH< -2 mA; P_MOS - - 110 Ohm IOL< 2 mA; N_MOS - - 150 ns CL= 20 pF; pin out driver= weak - - 50 ns CL= 50 pF; pin out driver= medium - - 140 ns CL= 150 pF; pin out driver= medium - - 550 ns CL= 150 pF; pin out driver= weak - - 18000 ns CL= 20000 pF; pin out driver= medium - - 65000 ns CL= 20000 pF; pin out driver= weak Data Sheet 14 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 23 Standard_Pads Class_A1 (cont'd) Parameter Symbol Values Min. Rise time, pad type A1 tRA1 CC - Typ. Max. - 150 Unit Note / Test Condition ns CL= 20 pF; pin out driver= weak - - 50 ns CL= 50 pF; pin out driver= medium - - 140 ns CL= 150 pF; pin out driver= medium - - 550 ns CL= 150 pF; pin out driver= weak - - 18000 ns CL= 20000 pF; pin out driver= medium - - 65000 ns CL= 20000 pF; pin out driver= weak Input high voltage class A1 pads VIHA1 0.6 x SR VDDP - min(V V DDP+ 0.3,3.6 ) - Input low voltage class A1 VILA1 SR -0.3 pads Data Sheet 0.36 x V VDDP 15 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 23 Standard_Pads Class_A1 (cont'd) Parameter Symbol Values Min. Output voltage high class A1 pads Typ. VOHA1 VDDP - - CC 0.4 Unit Note / Test Condition V IOH -1.4 mA; Max. - pin out driver= medium - 2.4 - V IOH -2 mA; pin out driver= medium VDDP - - - V IOH -400 A; pin out driver= weak 0.4 Output voltage low class A1 pads VOLA1 2.4 - - V IOH -500 A; pin out driver= weak - - 0.4 V IOL 2 mA; pin CC out driver= medium - - 0.4 V IOL 500 A; pin out driver= weak 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cant be guaranteed that it suppresses switching due to external system noise. Table 24 Standard_Pads Class_A1+ Parameter Symbol Input Hysteresis for A1+ pads 1) HYSA1 + CC IOZA1+ Input Leakage Current Class A1+ On-Resistance of the class A1+ pad, weak driver Data Sheet Values Unit Note / Test Condition Min. Typ. Max. 0.1 x - - V -1000 - 1000 nA - 450 600 Ohm IOH< -0.5 mA; P_MOS - 210 340 Ohm IOL< 0.5 mA; N_MOS VDDP CC RDSONW CC 16 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 24 Standard_Pads Class_A1+ (cont'd) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - - 155 Ohm IOH< -2 mA; P_MOS - - 110 Ohm IOL< 2 mA; N_MOS On-Resistance of the class A1+ pad, strong driver RDSON1+ - - 100 Ohm IOH< -2 mA; P_MOS - - 80 Ohm IOL< 2 mA; N_MOS Fall time, pad type A1+ tFA1+ CC - - 150 ns On-Resistance of the class A1+ pad, medium driver RDSONM CC CC CL= 20 pF; pin out driver= weak - - 28 ns CL= 50 pF; edge= slow ; pin out driver= strong - - 16 ns CL= 50 pF; edge= soft ; pin out driver= strong - - 50 ns CL= 50 pF; pin out driver= medium - - 140 ns CL= 150 pF; pin out driver= medium - - 550 ns CL= 150 pF; pin out driver= weak - - 18000 ns CL= 20000 pF; pin out driver= medium - - 65000 ns CL= 20000 pF; pin out driver= weak Data Sheet 17 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 24 Standard_Pads Class_A1+ (cont'd) Parameter Symbol Values Min. Rise time, pad type A1+ tRA1+ CC - Typ. Max. - 150 Unit Note / Test Condition ns CL= 20 pF; pin out driver= weak - - 28 ns CL= 50 pF; edge= slow ; pin out driver= strong - - 16 ns CL= 50 pF; edge= soft ; pin out driver= strong - - 50 ns CL= 50 pF; pin out driver= medium - - 140 ns CL= 150 pF; pin out driver= medium - - 550 ns CL= 150 pF; pin out driver= weak - - 18000 ns CL= 20000 pF; pin out driver= medium - - 65000 ns CL= 20000 pF; pin out driver= weak Input high voltage, Class A1+ pads VIHA1+ 0.6 x SR VDDP - min(V V DDP+ 0.3,3.6 ) Input low voltage Class A1+ pads Ratio Vil/Vih, A1+ pads VILA1+ - -0.3 VILA1+ / VIHA1+ 0.36 x V VDDP SR - 0.6 - CC Data Sheet 18 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 24 Standard_Pads Class_A1+ (cont'd) Parameter Symbol Values Min. Output voltage high class A1+ pads Typ. VOHA1+ VDDP - - CC 0.4 Unit Note / Test Condition V IOH -1.4 mA; Max. - pin out driver= medium VDDP - - - V 0.4 IOH -1.4 mA; pin out driver= strong - 2.4 - V IOH -2 mA; pin out driver= medium - 2.4 - V IOH -2 mA; pin out driver= strong VDDP - - - V IOH -400 A; pin out driver= weak 0.4 Output voltage low class A1+ pads VOLA1+ 2.4 - - V IOH -500 A; pin out driver= weak - - 0.4 V IOL 2 mA; pin CC out driver= medium - - 0.4 V IOL 2 mA; pin out driver= strong - - 0.4 V IOL 500 A; pin out driver= weak 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cant be guaranteed that it suppresses switching due to external system noise. Data Sheet 19 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 25 Standard_Pads Class_A2 Parameter Input Hysteresis for A2 pads 1) Input Leakage current Class A2 Symbol Values Unit Note / Test Condition Min. Typ. Max. HYSA2 0.1 x - - V CC VDDP IOZA2 -6000 - 6000 nA -3000 - 3000 nA 0.6 - - - 450 600 Ohm IOH< -0.5 mA; P_MOS - 210 340 Ohm IOL< 0.5 mA; N_MOS - - 155 Ohm IOH< -2 mA; P_MOS - - 110 Ohm IOL< 2 mA; N_MOS - - 28 Ohm IOH< -2 mA; P_MOS - - 22 Ohm IOL< 2 mA; N_MOS CC Vi< VDDP / 2 1 V; Vi> VDDP / 2 + 1 V; Vi 0 V; Vi VDDP V Vi> VDDP / 2 1 V; Vi< VDDP / 2 +1V Ratio Vil/Vih, A2 pads VILA2 / VIHA2 CC On-Resistance of the RDSONW class A2 pad, weak driver CC On-Resistance of the class A2 pad, medium driver RDSONM CC On-Resistance of the RDSON2 class A2 pad, strong driver CC Data Sheet 20 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 25 Standard_Pads Class_A2 (cont'd) Parameter Fall time, pad type A2 Symbol tFA2 CC Values Min. Typ. Max. - - 150 Unit Note / Test Condition ns CL= 20 pF; pin out driver= weak - - 7 ns CL= 50 pF; edge= medium ; pin out driver= strong - - 10 ns CL= 50 pF; edge= mediumminus ; pin out driver= strong - - 3.7 ns CL= 50 pF; edge= sharp ; pin out driver= strong - - 5 ns CL= 50 pF; edge= sharpminus ; pin out driver= strong - - 16 ns CL= 50 pF; edge= soft ; pin out driver= strong - - 50 ns CL= 50 pF; pin out driver= medium - - 7.5 ns CL= 100 pF; edge= sharp ; pin out driver= strong - - 140 ns CL= 150 pF; pin out driver= medium Data Sheet 21 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 25 Parameter Standard_Pads Class_A2 (cont'd) Symbol Values Min. Typ. Max. - - 550 Unit Note / Test Condition ns CL= 150 pF; pin out driver= weak - - 18000 ns CL= 20000 pF; pin out driver= medium - - 65000 ns CL= 20000 pF; pin out driver= weak Data Sheet 22 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 25 Standard_Pads Class_A2 (cont'd) Parameter Symbol Values Min. Rise time, pad type A2 tRA2 CC - Typ. Max. - 150 Unit Note / Test Condition ns CL= 20 pF; pin out driver= weak - - 7.0 ns CL= 50 pF; edge= medium ; pin out driver= strong - - 10 ns CL= 50 pF; edge= mediumminus ; pin out driver= strong - - 3.7 ns CL= 50 pF; edge= sharp ; pin out driver= strong - - 5 ns CL= 50 pF; edge= sharpminus ; pin out driver= strong - - 16 ns CL= 50 pF; edge= soft ; pin out driver= strong - - 50 ns CL= 50 pF; pin out driver= medium - - 7.5 ns CL= 100 pF; edge= sharp ; pin out driver= strong - - 140 ns CL= 150 pF; pin out driver= medium Data Sheet 23 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 25 Standard_Pads Class_A2 (cont'd) Parameter Symbol Values Min. Typ. Max. - - 550 Unit Note / Test Condition ns CL= 150 pF; pin out driver= weak - - 18000 ns CL= 20000 pF; pin out driver= medium - - 65000 ns CL= 20000 pF; pin out driver= weak Input high voltage, class A2 pads VIHA2 0.6 x SR VDDP - min(V V DDP + 0.3, 3.6) - Input low voltage Class A2 VILA2 SR -0.3 pads Output voltage high class A2 pads 0.36 x V VDDP VOHA2 VDDP - - CC 0.4 - V IOH -1.4 mA; pin out driver= medium VDDP - - - V 0.4 IOH -1.4 mA; pin out driver= strong - 2.4 - V IOH -2 mA; pin out driver= medium - 2.4 - V IOH -2 mA; pin out driver= strong VDDP - - - V IOH -400 A; pin out driver= weak - V IOH -500 A; pin out driver= weak 0.4 - 2.4 Data Sheet 24 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 25 Standard_Pads Class_A2 (cont'd) Parameter Symbol Output voltage low class A2 pads VOLA2 Values Min. Typ. Max. - - 0.4 Unit Note / Test Condition V IOL 2 mA; pin CC out driver= medium - - 0.4 V IOL 2 mA; pin out driver= strong - - 0.4 V IOL 500 A; pin out driver= weak 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cant be guaranteed that it suppresses switching due to external system noise. Table 26 Standard_Pads Class_F Parameter Input Hysteresis F1) Input Leakage Current Class F Symbol Values Unit Note / Test Condition Min. Typ. Max. HYSF 0.05 x - - V CC VDDP IOZF CC -6000 - 6000 nA -3000 - 3000 nA - - 450 600 Ohm IOH< -0.5 mA; P_MOS - 210 340 Ohm IOL< 0.5 mA; N_MOS - - 155 Ohm IOH< -2 mA; P_MOS - - 110 Ohm IOL< 2 mA; N_MOS Vi< VDDP / 2 1 V; Vi> VDDP / 2 + 1 V; Vi 0 V; Vi VDDP V Vi> VDDP / 2 1 V; Vi< VDDP / 2 +1V Ratio Vil/ Vih, F pads On-Resistance of the class F pad, weak driver On-Resistance of the class F pad, medium driver Data Sheet VILF / 0.6 VIHF CC RDSONW - CC RDSONM CC 25 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 26 Standard_Pads Class_F (cont'd) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Fall time, pad type F, CMOS mode tFF CC - - 60 ns CL= 50 pF Rise time, pad type F, CMOS mode tRF CC - - 60 ns CL= 50 pF Input high voltage, pad class F, CMOS mode VIHF SR 0.6 x VDDP - min(V V DDP+ 0.3, 3.6) Input low voltage, Class F VILF SR pads, CMOS mode Output high voltage, class VOHF F pads, CMOS mode CC - -0.3 V VDDP VDDP- - - V IOH -1.4 mA - - V - 0.4 V IOH -2 mA IOL 2 mA 0.4 2.4 Output low voltage, class F pads, CMOS mode 0.36 x VOLF CC - 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cant be guaranteed that it suppresses switching due to external system noise. Table 27 Standard_Pads Class_I Parameter Input Hysteresis Class I1) Input Leakage Current Ratio between low and high input threshold Input high voltage, class I pins Symbol Values Unit Min. Typ. Max. HYSI 0.1 x - - V CC VDDP - 1000 nA - - - min(V V DDP+ IOZI CC -1000 VILI / VIHI 0.6 Note / Test Condition CC VIHI SR 0.6 x VDDP 0.3, 3.6) Input low voltage, Class I pads Data Sheet VILI SR - -0.3 0.36 x V VDDP 26 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cant be guaranteed that it suppresses switching due to external system noise. Table 28 LVDS_Pads Parameters Parameter Symbol Values Unit Min. Typ. Max. Note / Test Condition Output impedance, pad class F, LVDS mode RO CC 40 - 140 Ohm Fall time, pad type LVDS tFL CC - - 2 ns termination 100 1 % Rise time, pad type LVDS tRL CC - - 2 ns termination 100 1 % tSET_LVD - - 13 s termination 100 1 % - 400 mV termination 100 1 % Pad set-up time S CC Output Differential Voltage VOD CC 150 Output voltage high, pad class F, LVDS mode VOH CC - - 1525 mV termination 100 1 % Output voltage low, pad class F, LVDS mode VOL CC - - mV termination 100 1 % Output Offset Voltage VOS CC 1075 - 1325 mV termination 100 1 % Data Sheet 875 27 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters 5.2.2 Analog to Digital Converters (ADCx) ADC parameter are valid for VDD / DDAF = 1.235 V to 1.365 V; VDDM = 4.75 V to 5.25 V. Table 29 ADC Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. CAINSW Switched capacitance at the analog voltage inputs1) CC - 9 20 pF CAINTOT - 20 30 pF Switched capacitance at the positive reference voltage input2)3) CAREFSW - 15 30 pF Total capacitance of the voltage reference inputs2) CAREFTO - 20 40 pF -3 - 3 LSB ADC resolution= 12bit 8) 9) -3.5 - 3.5 LSB ADC resolution= 12bit 8) 9) -3 - 3 LSB ADC resolution= 12bit 8) 9) -4 - 4 LSB ADC resolution= 12bit 8) 9) fADC SC 4 fADCI CC 1 QCONV 70 - 90 MHz fADC= fFPI 18 MHz 100 pC Total capacitance of an analog input Differential Non-Linearity Error4)5)6)7) Gain Error4)6)5)7) CC CC T CC EADNL CC EAGAIN CC Integral NonLinearity4)6)5)7) Offset Error4)6)5)7) EAINL CC EAOFF CC Converter clock Internal ADC clock Charge consumption per conversion - 10) 85 CC charge needs to be provided via VAREF0 Data Sheet 28 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 29 ADC Parameters (cont'd) Parameter Symbol Values Min. Input leakage at analog inputs11) IOZ1 CC -100 Typ. Max. - 500 Unit Note / Test Condition nA Vi VDDM V; Vi 0.97 x VDDM V; overlayed= No - -100 600 nA Vi 0.97 x VDDM V; Vi VDDM V; overlayed= Yes -500 - 100 nA Vi 0.03 x VDDM V; Vi 0 V; -600 - 100 nA Vi 0.03 x VDDM V; Vi 0 V; -100 - 200 nA Vi> 0.03 x VDDM V; Vi< 0.97 x VDDM V; overlayed= No overlayed= Yes overlayed= No - -100 300 nA Vi< 0.97 x VDDM V; Vi> 0.03 x VDDM V; overlayed= Yes Input leakage current at Varef0 IOZ2 CC -2 - 2 A VAREF0 VDDM V Input leakage current at Vagnd0 IOZ3 CC -2 - 2 A VAGND0 VDDM V ON resistance of the transmission gates in the analog voltage path RAIN CC - 900 1500 Ohm 550 900 Ohm ON resistance for the ADC RAIN7T test (pull down for AIN7) CC Data Sheet 180 29 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 29 ADC Parameters (cont'd) Parameter Symbol RAREF Resistance of the reference voltage input path Values Typ. Max. - 500 1000 Ohm - 257 TADCI - 4352 cycle s - 413) LSB Note / Test Condition CC tS CC 2 Calibration time after reset tCAL CC - Sample time TUE CC -4 Total Unadjusted Error6)5)12) Analog reference ground2) VAGND0 SR Analog input voltage Analog reference voltage Unit Min. 2) VSSM - - VAREF0 V 0.05 -1 VAIN SR VAGND0 - VAREF0 VAGND0 - SR +1 ADC resolution= 12bit VAREF0 V VDDM + V 0.0514) 15) Analog reference voltage range6)5)2) VAREF0 - VDDM/2 - VAGND0 VDDM + V 0.05 SR 1) The sampling capacity of the conversion C-network is pre-charged to VAREF0/2 before the sampling moment. Because of the parasitic elements the voltage measured at AINx can deviate from VAREF0/2. 2) Applies to AINx, when used as auxiliary reference input. 3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead smaller capacitances are successively switched to the reference voltage. 4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error. 5) If a reduced analog reference voltage between 1V and VDDM / 2 is used, then there are additional decrease in the ADC speed and accuracy. 6) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1), TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k. 7) If the analog reference voltage is > VDDM, then the ADC converter errors increase. 8) For 10-bit conversions the error value must be multiplied with a factor 0.25. 9) For 8-bit conversions the error value must be multiplied with a factor 0.0625. 10) For a conversion time of 1 s a rms value of 85A result for IAREF0. 11) The leakage current definition is a continuos function, as shown in figure ADCx Analoge Input Leakage. The numerical values defined determine the characteristic points of the given continuous linear approximation they do not define step function. 12) Measured without noise. Data Sheet 30 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters 13) For 10-bit conversion the TUE is 2LSB; for 8-bit conversion the TUE is 1LSB 14) A running conversion may become inexact in case of violating the normal conditions (voltage overshoot). 15) If the reference voltage VAREF0 increase or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V), then the accuracy of the ADC decrease by 4LSB12. Table 30 Conversion Time (Operating Conditions apply) Parameter Symbol Conversion tC time with post-calibration Values Unit Note CC 2 x TADC + (4 + STC + n) x TADCI s 2 x TADC + (2 + STC + n) x TADCI Conversion time without post-calibration n = 8, 10, 12 for n - bit conversion TADC = 1 / fFPI TADCI = 1 / fADCI The power-up calibration of the ADC requires a maximum number of 4352 fADCI cycles. REXT VAIN = Analog Input Circuitry RAIN, On ANx CEXT CAINSW CAINTOT - CAINSW VAGNDx RAIN7T Reference Voltage Input Circuitry RAREF, On VAREFx VAREF CAREFTOT - CAREFSW CAREFSW VAGNDx Analog_InpRefDiag Figure 7 Data Sheet ADCx Input Circuits 31 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Ioz1 Single ADC Input 500nA 200nA 100nA -100nA VIN[VDDM%] 3% 97% 100% -500nA Ioz1 Overlayed ADC/FADC Input 600nA 300nA 100nA -100nA VIN[VDDM%] 3% 97% 100% -600nA Figure 8 Data Sheet ADCx Analog Inputs Leakage 32 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters 5.2.3 Table 31 Fast Analog to Digital Converter (FADC) FADC Parameters Parameter Input current at VFAREF Symbol IFAREF Values Unit Min. Typ. Max. - - 120 A -500 - 500 nA -500 - 500 nA -1 - 1 LSB Note / Test Condition CC IFOZ2 Input leakage current at VFAREF1) CC Input leakage current at VFAGND CC DNL error IFOZ3 EFDNL CC VFAREF VDDMF V; VFAREF 0 V VIN mode= differential -1 - 1 LSB VIN mode= EFGRAD -5 - 5 % VIN mode= single ended GRADient error CC differential ; Gain 4 - -5 5 % VIN mode= single ended ; Gain 4 - -6 6 % VIN mode= differential ; Gain= 8 - -6 6 % VIN mode= single ended ; Gain= 8 INL error EFINL -4 - 4 LSB VIN mode= -4 - 4 LSB VIN mode= CC differential single ended Data Sheet 33 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 31 FADC Parameters (cont'd) Parameter Offset error Symbol EFOFF Values Min. Typ. Max. -90 - 90 Unit Note / Test Condition mV VIN mode= CC differential ; Calibration= No - -90 90 mV VIN mode= single ended ; Calibration= No - -20 20 mV VIN mode= differential ; Calibration= Ye s 2)3) - -20 20 mV VIN mode= single ended ; Calibration= Ye s 2)3) Error of commen mode voltage VFAREF/2 EFREF -60 - 60 mV 2 - - MHz 1 - 90 MHz fFADC= fFPI - - 21 1/ CC Channel amplifier cutoff frequency fCOFF Converter clock fFADC CC SC Conversion time tC CC For 10-bit fFADC conversion - 200 kOh m - 5 s VDDMF V VSSAF - - VSSAF V 0.05 + 0.05 Input resistance of the analog voltage path (Rn, Rp) RFAIN Settling time of a channel amplifier after changing ENN or ENP tSET CC - Analog input voltage range VAINF Analog reference ground VFAGND SR VFAREF 3.0 Analog reference voltage 100 CC VFAGND - SR - V 5) SR Data Sheet 3.634) 34 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters 1) This value applies in power-down mode. 2) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed minimium once per week. 3) The offser error voltage drifts over the whole temperature range maximum +-3LSB. 4) Voltage overshoot to 4V is permissible, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 5) A running conversion may become inexact in case of violating the nomal operating conditions (voltage overshoots). The calibration procedure should run after each power-up, when all power supply voltages and the reference voltage have stabilized. FADC Analog Input Stage RN FAINxN VFAREF /2 = VFAGND + + RP FAINxP - FADC Reference Voltage Input Circuitry VFAREF IFAREF VFAREF VFAGND FADC_InpRefDiag Figure 9 Data Sheet FADC Input Circuits 35 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters 5.2.4 Table 32 Oscillator Pins OSC_XTAL Parameters Parameter Symbol Values Unit Note / Test Condition VIN0 V Min. Typ. Max. -25 - 25 A Input current at XTAL1 IIX1 CC Input frequency fOSC SR 4 - 40 MHz Direct Input Mode selected 8 - 25 MHz External Crystal Mode selected - - 10 ms VDDOS V Oscillator start-up time1) tOSCS CC Input high voltage at XTAL12) VIHX SR 0.7 x VDDOS Input low voltage at XTAL1 VILX SR -0.5 Input Hysteresis for XTAL1 pad 3) HYSAX - + 0.5 C3 C3 - 0.3 x V VDDOS C3 - - 200 mV CC 1) tOSCS is defined from the moment when VDDOSC3 = 3.13V until the oscillations reach an amplitude at XTAL1 of 0.3 * VDDOSC3. The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystral suppliers. 2) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.4 * VDDOSC3 is necessary. 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cant be guaranteed that it suppresses switching due to external system noise. Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal or ceramic resonator supplier. Data Sheet 36 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters 5.2.5 Table 33 Temperature Sensor DTS Parameters Parameter Measurement time Temperature sensor range Symbol tM CC TSR SR Values Unit Min. Typ. Max. - - 100 s -40 - 150 C Sensor Accuracy (calibrated) TTSA CC -6 - 6 C Start-up time after resets inactive tTSST SR - - 20 s Note / Test Condition The following formula calculates the temperature measured by the DTS in [oC] from the RESULT bit field of the DTSSTAT register. (1) DTSSTAT RESULT - 596 Tj = ------------------------------------------------------------------2, 03 Data Sheet 37 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters 5.2.6 Power Supply Current The total power supply current defined below consists of leakage and switching component. Application relevant values are typically lower than those given in the following two tables and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations). The operating conditions for the parameters in the following table are: VDD=1.365 V, VDDP=3.47 V, VDDM=5.1 V, fLMB=180 / 133 MHz, TJ=150 oC The realisic power pattern defines the following conditions: * * * * * * TJ=150 oC fLMB = fPCP = fCPU = 180 / 133 MHz fFPI = 90 / 66.5 MHz VDD = VDDOSC = VDDAF = 1.326 V VDDP = VDDOSC3 = VDDFL3 = VDDMF = 3.366 V VDDM = 5.1 V The max power pattern defines the following conditions: * * * * * * TJ=150 oC fLMB = fPCP = fCPU = 180 / 133 MHz fFPI = 90 / 66.5 MHz VDD = VDDOSC = VDDAF = 1.365 V VDDP = VDDOSC3 = VDDFL3 = VDDMF = 3.47 V VDDM = 5.5 V Data Sheet 38 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 34 Power Supply Parameters Parameter Unit Note / Test Condition 4863) mA power pattern= max ; SAK-TC1782F-256F133HR SAK-TC1782F-256F133HL SAK-TC1782N-256F133HR SAK-TC1782N-256F133HL SAK-TC1182N-256F133HR SAK-TC1182N-256F 133HL - 5503) mA power pattern= max ; SAK-TC1782F320F180HR SAK-TC1782F320F180HL SAK-TC1782N-320F180HR SAK-TC1782N-320F180HL SAK-TC1182N-320F180HR SAK-TC1182N-320F180HL - - 3704) mA power pattern= realistic ; SAK-TC1782F-256F133HR SAK-TC1782F-256F133HL SAK-TC1782N-256F133HR SAK-TC1782N-256F133HL SAK-TC1182N-256F133HR SAK-TC1182N-256F 133HL; VDD=1.326 V - - 3984) mA power pattern= realistic ; SAK-TC1782F320F180HR SAK-TC1782F320F180HL SAK-TC1782N-320F180HR SAK-TC1782N-320F180HL SAK-TC1182N-320F180HR SAK-TC1182N320F180HL; VDD=1.326 V IDD current at PORST Low IDD_PORS - - 300 mA CC - - 291 mA Analog core supply current IDDAF - - 23 mA - - 4 mA Core active mode supply current1)2) Oscillator core supply current Data Sheet Symbol IDD CC T Values Min. Typ. Max. - - - VDD=1.326 V CC IDDOSC CC 39 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 34 Power Supply Parameters (cont'd) Parameter Symbol Values Min. IDDP current at IDDP_POR - PORST Low ST Unit Typ. Max. - 2.5 - IDDP_P mA CC IDDP current no IDDP CC - pad activity, LVDS off ORST mA including flash read current mA including flash programming current 5) mA including flash erase verify current 5) + 12 - - IDDP_P ORST + 27 - - IDDP_P ORST + 20 6) Flash memory current during reading the Flash memory - - 56 mA - - 15 mA - - 15 mA - - 24 mA IDDM CC - - 2 mA IDDFL3 CC Oscillator power supply current, 3.3V IDDOSC3 FADC analog supply current, 3.3V IDDMF CC CC Current ILVDS Consumption of CC LVDS Pad Pairs ADC 5V power supply current Data Sheet Note / Test Condition 40 for all LVDS pads in total V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters Table 34 Parameter Maximum power dissipation Power Supply Parameters (cont'd) Symbol PD CC Values Unit Note / Test Condition 1143 mW power pattern= max ; SAK-TC1782F-256F133HR SAK-TC1782F-256F133HL SAK-TC1782N-256F133HR SAK-TC1782N-256F133HL SAK-TC1182N-256F133HR SAK-TC1182N-256F 133HL - 1231 mW power pattern= max ; SAK-TC1782F320F180HR SAK-TC1782F320F180HL SAK-TC1782N-320F180HR SAK-TC1782N-320F180HL SAK-TC1182N-320F180HR SAK-TC1182N-320F180HL - - 957 mW power pattern= realistic ; SAK-TC1782F-256F133HR SAK-TC1782F-256F133HL SAK-TC1782N-256F133HR SAK-TC1782N-256F133HL SAK-TC1182N-256F133HR SAK-TC1182N-256F 133HL; VDD=1.326 V - - 994 mW power pattern= realistic ; SAK-TC1782F320F180HR SAK-TC1782F320F180HL SAK-TC1782N-320F180HR SAK-TC1782N-320F180HL SAK-TC1182N-320F180HR SAK-TC1182N320F180HL; VDD=1.326 V Min. Typ. Max. - - - 1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each customer application will most probably be lower than this value, but must be evaluated seperately. 2) This current includes the E-Ray module power consumption, including the PCP operation component. 3) The IDD decreases typically by 68mA if the fCPU decreases by 50MHz, at constant TJ 4) The IDD decreases typically by 30mA if the fCPU decreases by 50MHz, at constant TJ 5) Relevant for the power supply dimensioning, not for thermal considerations. 6) In case of erase of Program Flash PF, internal flash array loading effects may generate transient current spikes of up to 15 mA for maximum 5 ms per flash module. Data Sheet 41 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersDC Parameters 5.2.6.1 Calculating the 1.3 V Current Consumption The current consumption of the 1.3 V rail compose out of two parts: * * Static current consumption Dynamic current consumption The static current consumption is related to the device temperature TJ and the dynamic current consumption depends of the configured clocking frequencies and the software application executed. These two parts needs to be added in order to get the rail current consumption. (2) I 0 mA = 2, 20897 --------- x e 0, 02696 x T J [ C ] C (3) mA I 0 = 10, 68 --------- x e 0, 02203 x T J [ C ] C Function 2 defines the typical static current consumption and Function 3 defines the maximum static current consumption. Both functions are valid for VDD = 1.326 V. For the dynamic current consumption using the application pattern and fLMB = 2 * fFPI the function 4 applies: (4) mA I D y m = 0, 6 ------------- x f CPU [ MHz ] MHz and this finally results in (5) I DD = I 0 + I DYM Data Sheet 42 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters 5.3 AC Parameters All AC parameters are defined with the temperature compensation disabled. That means, keeping the pads constantly at maximum strength. 5.3.1 Testing Waveforms VD D P 90% 90% 10% 10% VSS tR tF rise_fall Figure 10 Rise/Fall Time Parameters VD D P VD D E / 2 Test Points VD D E / 2 VSS mct04881_a.vsd Figure 11 Testing Waveform, Output Delay VLoad+ 0.1 V VLoad- 0.1 V Timing Reference Points VOH - 0.1 V VOL - 0.1 V MCT04880_new Figure 12 Data Sheet Testing Waveform, Output High Impedance 43 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters 5.3.2 Power Sequencing V 5.25V 5V 4.75V VAREF 3.47V 3.3V 3.0V -12% 1.365V 1.3V 1.235V 0.5V -12% 0.5V 0.5V t VDDP PORST power down power fail t Power-Up 10.vsd Figure 13 5 V / 3.3 V / 1.3 V Power-Up/Down Sequence The following list of rules applies to the power-up/down sequence: * * * All ground pins VSS must be externally connected to one single star point in the system. Regarding the DC current component, all ground pins are internally directly connected. At any moment in time to avoid increased latch-up risk, each power supply must be higher then any lower_power_supply - 0.5 V, or: VDD5 > VDD3.3 - 0.5 V; VDD5 > VDD1.3 - 0.5 V;VDD3.3 > VDD1.3 - 0.5 V, see Figure 13. - The latch-up risk is minimized if the I/O currents are limited to: - 20 mA for one pin group - AND 100 mA for the completed device I/Os - AND additionally before power-up / after power-down: 1 mA for one pin in inactive mode (0 V on all power supplies) During power-up and power-down, the voltage difference between the power supply pins of the same voltage (3.3 V, 1.3 V, and 5 V) with different names (for example VDDP, VDDFL3 ...), that are internally connected via diodes, must be lower than 100 mV. On the other hand, all power supply pins with the same name (for example all VDDP), Data Sheet 44 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters 1. 2. 3. 4. 5. 6. are internally directly connected. It is recommended that the power pins of the same voltage are driven by a single power supply. The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.3, and VAREF powersupplies and the oscillator have reached stable operation, within the normal operating conditions. At normal power down the PORST signal should be activated within the normal operating range, and then the power supplies may be switched off. Care must be taken that all Flash write or delete sequences have been completed. At power fail the PORST signal must be activated at latest when any 3.3 V or 1.3 V power supply voltage falls 12% below the nominal level. If, under these conditions, the PORST is activated during a Flash write, only the memory row that was the target of the write at the moment of the power loss will contain unreliable content. In order to ensure clean power-down behavior, the PORST signal should be activated as close as possible to the normal operating voltage range. In case of a power-loss at any power-supply, all power supplies must be powereddown, conforming at the same time to the rules number 2 and 4. Although not necessary, it is additionally recommended that all power supplies are powered-up/down together in a controlled way, as tight to each other as possible. Additionally, regarding the ADC reference voltage VAREF: - VAREF must power-up at the same time or later then VDDM, and - VAREF must power-down either earlier or at latest to satisfy the condition VAREF < VDDM + 0.5 V. This is required in order to prevent discharge of VAREF filter capacitance through the ESD diodes through the VDDM power supply. In case of discharging the reference capacitance through the ESD diodes, the current must be lower than 5 mA. Data Sheet 45 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters 5.3.3 Table 35 Power, Pad and Reset Timing Reset Timings Parameters Parameter Application Reset Boot Time1)2) Power on Reset Boot Time3)4) Symbol tB CC tBP CC Values Unit Note / Test Condition 810 s SAK-TC1782F256F133HR SAK-TC1782F256F133HL SAK-TC1782N256F133HR SAK-TC1782N256F133HL SAK-TC1182N256F133HR SAK-TC1182N256F 133HL - 665 s SAKTC1782F320F1 80HR SAKTC1782F320F1 80HL SAK-TC1782N320F180HR SAK-TC1782N320F180HL SAK-TC1182N320F180HR SAK-TC1182N320F180HL - 2.5 ms - - ns - - ns Min. Typ. Max. 150 - 150 - tHDH SR 16 / fFPI HWCFG pins setup time to tHDS CC 0 HWCFG pins hold time from ESR0 rising edge ESR0 rising edge Data Sheet 46 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters Table 35 Reset Timings Parameters (cont'd) Parameter Symbol Values Unit Min. Typ. Max. Ports inactive after ESR0 reset active tPI CC - - 8 / fFPI ns Ports inactive after PORST reset active5) tPIP CC - - 150 ns Minimum PORST active time after power supplies are stable at operating levels tPOA CC 10 - - ms TESTMODE / TRST hold time from PORST rising edge tPOH SR 100 - - ns PORST rise time tPOR SR - tPOS SR 0 - 50 ms - - ns TESTMODE / TRST setup time to PORST rising edge Note / Test Condition 1) The duration of the boot time is defined between the rising edge of the internal application reset and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts. 2) The given time includes the time of the internal reset extension for a configured value of SCU_RSTCNTCON.RELSA = 0x05BE. 3) The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts. 4) The given time includes the internal reset extension time for the System and Application Reset which is visible through ESR0. 5) This parameter includes the delay of the analog spike filter in the PORST pad. Data Sheet 47 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters VDD P -12% VD D PPA V D DPPA VDDP VDD VD D -12% tPOA tPOA PORST tPOH TRST TESTMODE tPOH t hd t hd ESR0 tHDH tHDH tHDH HWCFG t PIP tPI t PIP tPI Pads tPI tPI t PIP tPI Pad-state undefined Tri-state or pull device active reset_beh2 As programmed Figure 14 Data Sheet Power, Pad and Reset Timing 48 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters 5.3.4 Table 36 Phase Locked Loop (PLL) PLL_SysClk Parameters Parameter Symbol Values Min. Typ. Max. Note / Test Condition - 7 ns 200 320 MHz fREF CC 8 fVCO CC 400 tL CC 50 - 16 MHz - 720 MHz - 200 s N > 32 100 - 400 s N 32 DP CC -7 fPLLBASE 50 Accumulated Jitter PLL base frequency Unit CC VCO input frequency VCO frequency range PLL lock-in time Phase Locked Loop Operation When PLL operation is enabled and configured, the PLL clock fVCO (and with it the LMBBus clock fLMB) is constantly adjusted to the selected frequency. The PLL is constantly adjusting its output frequency to correspond to the input frequency (from crystal or clock source), resulting in an accumulated jitter that is limited. This means that the relative deviation for periods of more than one clock cycle is lower than for a single clock cycle. This is especially important for bus cycles using wait states and for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in [ns] dependent on the K2 - factor, the LMB clock frequency fLMB in [MHz], and the number m of consecutive fLMB clock periods. for ( K2 100 ) ( m ( f LMB [ MHz ] ) 2 ) and 740 ( 1 - 0, 01 x K2 ) x ( m - 1 -) + 0, 01 x K2 D m [ ns ] = -------------------------------------------- + 5 x -------------------------------------------------------------- K2 x f LMB [ MHz ] 0, 5 x f LMB [ MHz ] - 1 else 740 D m [ ns ] = --------------------------------------------+5 K2 x f LMB [ MHz ] (6) (7) With rising number m of clock cycles the maximum jitter increases linearly up to a value of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum Data Sheet 49 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock frequency fLMB results in a higher absolute maximum jitter value. Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the maximum driver and sharp edge. Note: The maximum peak-to-peak noise on the pad supply voltage, measured between VDDOSC3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. The maximum peak-to peak noise on the pad supply voltage, measured between VDDOSC and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Oscillator Watchdog (OSC_WDT) The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The OSC_WDT checks for too low frequencies and for too high frequencies. The frequency that is monitored is fOSCREF which is derived for fOSC. (8) f O S C R EF fO S C = ---------------------------------OSCVAL + 1 The divider value SCU_OSCCON.OSCVAL has to be selected in a way that fOSCREF is 2.5 MHz. Note: fOSCREF has to be within the range of 2 MHz to 3 MHz and should be as close as possible to 2.5 MHz. The monitored frequency is too low if it is below 1.25 MHz and too high if it is above 7.5 MHz. This leads to the following two conditions: * * Too low: fOSC < 1.25 MHz x (SCU_OSCCON.OSCVAL+1) Too high: fOSC > 7.5 MHz x (SCU_OSCCON.OSCVAL+1) Note: The accuracy is 30% for these boundaries. Data Sheet 50 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters 5.3.5 Table 37 ERAY Phase Locked Loop (ERAY_PLL) PLL_ERAY Parameters Parameter Symbol Values Min. Unit Typ. Max. Accumulated jitter at SYSCLK pin DPP CC -0.8 - 0.8 ns Accumulated_Jitter DP CC -0.5 fPLLBASE_ 50 - 0.5 ns 250 360 MHz PLL Base Frequency of the ERAY PLL ERAY Note / Test Condition CC VCO input frequency of the ERAY PLL fREF CC 20 - 40 MHz VCO frequency range of the ERAY PLL fVCO_ERA 450 - 500 MHz Y CC PLL lock-in time tL CC - 200 s 50 Note: The specified PLL jitter values are valid if the capacitive load per pin does not exceed CL = 20 pF with the maximum driver and sharp edge. Note: The maximum peak-to-peak noise on the pad supply voltage, measured between VDDOSC3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise frequencies below 300 KHz and VPP = 40 mV for noise frequencies above 300 KHz. These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Data Sheet 51 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters 5.3.6 JTAG Interface Timing The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 38 JTAG Interface Timing Parameters (Operating Conditions apply) Parameter Min. Typ. Max. Unit Note / Test Condition t1 SR t2 SR t3 SR t4 SR t5 SR t6 SR 25 - - ns - 10 - - ns - 10 - - ns - - - 4 ns - - - 4 ns - 6 - - ns - t7 SR 6 - - ns - TDO valid after TCK falling t8 CC edge1) (propagation delay) t CC 8 - - 13 ns CL = 50 pF 3 - - ns CL = 20 pF TDO hold after TCK falling t18 CC edge1) 2 - - ns TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time TDI/TMS setup to TCK rising edge TDI/TMS hold after TCK rising edge Symbol Values TDO high imped. to valid from TCK falling edge1)2) t9 CC - - 14 ns CL = 50 pF TDO valid to high imped. from TCK falling edge1) t10 CC - - 13.5 ns CL = 50 pF 1) The falling edge on TCK is used to generate the TDO timing. 2) The setup time for TDO is given implicitly by the TCK cycle time. Data Sheet 52 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters t1 0.9 VD D P 0.5 VD D P t5 t2 0.1 VD D P t4 t3 MC_ JTAG_ TCK Figure 15 Test Clock Timing (TCK) TCK t6 t7 t6 t7 TMS TDI t9 t8 t1 0 TDO t18 MC_JTAG Figure 16 Data Sheet JTAG Timing 53 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters 5.3.7 DAP Interface Timing The following parameters are applicable for communication through the DAP debug interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 39 DAP Parameters Parameter Symbol DAP0 clock period1) tTCK SR t12 SR t13 SR t14 SR t15 SR t16 SR DAP0 high time 1) DAP0 low time DAP0 clock rise time DAP0 clock fall time DAP1 setup to DAP0 rising edge Values Unit Min. Typ. Max. 12.5 - - ns 4 - - ns 4 - - ns - - 2 ns - - 2 ns 6.0 - - ns DAP1 hold after DAP0 rising edge t17 SR 6.0 - - ns DAP1 valid per DAP0 clock period2) t19 CC 8 - - ns 10 - - ns Note / Test Condition CL= 20 pF; f= 80 MHz CL= 50 pF; f= 40 MHz 1) See the DAP chapter for clock rate restrictions in the Active:IDLE protocol state. 2) The Host has to find a suitable sampling point by analyzing the sync telegram response. t11 0.9 VD D P 0.5 VD D P t1 5 t1 2 t14 0.1 VD D P t1 3 MC_DAP0 Figure 17 Data Sheet Test Clock Timing (DAP0) 54 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters DAP0 t1 6 t1 7 DAP1 MC_ DAP1_RX Figure 18 DAP Timing Host to Device t1 1 DAP1 t1 9 MC_ DAP1_TX Figure 19 Data Sheet DAP Timing Device to Host 55 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters 5.3.8 Peripheral Timings Note: Peripheral timing parameters are not subject to production test. They are verified by design/characterization. 5.3.8.1 Micro Link Interface (MLI) Timing MLI Transmitter Timing t13 t14 t10 t12 TCLKx t11 t15 t15 TDATAx TVALIDx t16 t17 TREADYx MLI Receiver Timing t23 t24 t20 t22 RCLKx t21 t25 t26 RDATAx RVALIDx t27 t27 RREADYx MLI_Tmg_2.vsd Figure 20 MLI Interface Timing Note: The generation of RREADYx is in the input clock domain of the receiver. The reception of TREADYx is asynchronous to TCLKx. Data Sheet 56 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters The MLI parameters are vaild for CL = 50 pF (typical). Table 40 MLI Receiver Parameter Symbol RCLK clock period RCLK high time1)2) t20 SR t21 SR Values Unit Min. Typ. Max. 1 / fFPI - - ns - 0.5 x - ns - ns 4 ns Note / Test Condition t20 RCLK low time1)2) t22 SR - 0.5 x t20 RCLK rise time3) RCLK fall time 3) RDATA/RVALID setup time before RCLK falling edge t23 SR t24 SR t25 SR RDATA/RVALID hold time t26 CC after RCLK falling edge RREADY output delay time t27 CC - - - - 4 ns 4.2 - - ns 2.2 - - ns 0 - 16 ns 1) The following formula is valid: t21 + t22 = t20. 2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver timing parameters. 3) The RCLK max. input rise/fall times are best case parameters for fSYS = 90 MHz. For reduction of EMI, slower input signal rise/fall times can be used for longer RCLK clock periods. Table 41 MLI Transmitter Parameter TCLK clock period Symbol t10 CC Values Unit Min. Typ. Max. 2x1/ - - ns 0.45 x 0.5 x 0.55 x ns t10 t10 t10 0.45 x 0.5 x 0.55 x t10 t10 t10 - - 0.3 x Note / Test Condition fFPI TCLK high time1)2) TCLK low time1)2) TCLK rise time Data Sheet t11 CC t12 CC t13 CC ns ns t103) 57 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters Table 41 MLI Transmitter (cont'd) Parameter Symbol Values Unit Min. Typ. Max. t14 CC - - 0.3 x TDATA/TVALID output delay time t15 CC -3 - 4.4 ns TREADY setup time before TCLK rising edge t16 SR 18 - - ns TREADY hold time after TCLK rising edge t17 SR -4 - - ns TCLK fall time Note / Test Condition ns t103) 1) The following formula is valid: t11 + t12 = t10. 2) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be regarded additionally to t11 / t12. 3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended for TCLK. 5.3.8.2 Micro Second Channel (MSC) Interface Timing The MSC parameters are vaild for CL = 50 pF (typical). Table 42 MSC Parameters Parameter Symbol FCLP clock period1)2) t40 CC SOP4)/ENx outputs delay from FCLP4) rising edge Data Sheet t45 CC Values Unit Note / Test Condition Min. Typ. Max. 2x - - ns -2 - 5 ns ENx with strong driver and sharp (minus ) edge -2 - 10 ns ENx with strong driver and medium (minus) edge 0 - 21 ns ENx with strong driver and soft edge TMSC3) 58 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters Table 42 MSC Parameters (cont'd) Parameter Symbol t46 CC SDI bit time Values Unit Min. Typ. Max. 8x - - ns - - 100 ns - - 100 ns Note / Test Condition TMSC t48 SR t49 SR SDI rise time SDI fall time 1) FCLP signal rise/fall times are only defined by the pad rise/fall times. 2) FCLP signal high and low can be minimum 1xTMSC 3) TMSC = TSYS = 1 / fSYS. 4) SOP / FCLP either propagated by LVDS or by CMOS strong driver and non soft edge. t40 0.9 VDDP 0.1 VDDP FCLP t45 t45 SOP EN t48 t49 0.9 VDDP 0.1 VDDP SDI t46 t46 MSC_Tmg_1.vsd Figure 21 MSC Interface Timing Note: The data at SOP should be sampled with the falling edge of FCLP in the target device. Data Sheet 59 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters 5.3.8.3 SSC Master/Slave Mode Timing The SSC parameters are vaild for CL = 50 pF (typical). Table 43 SSC Parameters Parameter SCLK clock period1)2)3) Symbol t50 CC Values Unit Min. Typ. Max. 2x1/ - - ns Note / Test Condition fFPI MTSR/SLSOx delay form SCLK rising edge t51 CC 0 - 8 ns MRST setup to SCLK falling edge3) t52 SR 16.5 - - ns MRST hold from SCLK falling edge3) t53 SR 0 - - ns SCLK input clock period1)3) t54 SR 4x1/ - - ns SCLK input clock duty cycle t55_t54 45 - 55 % MTSR setup to SCLK latching edge3)4) t56 CC 1 / fFPI - - ns MTSR hold from SCLK latching edge t57 CC 1 / fFPI +5 - - ns SLSI setup to first SCLK latching edge t58 CC 1 / fFPI +5 - - ns SLSI hold from last SCLK t59 CC latching edge 7 - - ns MRST delay from SCLK shift edge t60 CC 0 - 16.5 ns SLSI to valid data on MRST t61 CC - - 16.5 ns fFPI SR 1) SCLK signal rise/fall times are the same as the rise/fall times of the pad. 2) SCLK signal high and low times can be minimum 1xTSSC. 3) TSSCmin = TSYS = 1/fSYS. 4) Fractional divider switched off, SSC internal baud rate generation used. Data Sheet 60 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters t50 SCLK1)2) t51 t51 MTSR1) t52 t53 Data valid 1) MRST t51 2) SLSOn 1) This timing is based on the following setup: CON.PH = CON.PO = 0. 2) The transition at SLSOn is based on the following setup: SSOTC.TRAIL = 0 and the first SCLK high pulse is in the first one of a transmission. SSC_TmgMM Figure 22 SSC Master Mode Timing t54 First latching SCLK edge First shift SCLK edge SCLK1) t55 t56 Last latching SCLK edge t55 t56 t57 Data valid 1) MTSR t57 Data valid t60 t60 1) MRST t61 SLSI t59 t58 1) This timing is based on the following setup: CON.PH = CON.PO = 0. SSC_TmgSM Figure 23 Data Sheet SSC Slave Mode Timing 61 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters 5.3.8.4 ERAY Interface Timing The timings of this section are valid for the strong driver and either sharp edge or medium edge settings of the output drivers with CL = 25 pF. The ERAY interface is only available for the SAK-TC1782F-320F180HR / SAKTC1782F-320F180HL. Table 44 ERAY Parameters Parameter Symbol Values Min. Typ. Unit Max. Note / Test Condition Time span from last BSS to FES without the influence of quartz tolerancies (d10Bit_TX)1) t60 CC 997.75 - 1002.2 ns 5 TxD data valid from fsample flip flop txd_reg TxDA, TxDB (dTxAsym)2)3) t61-t62 - - 1.5 Time span between last BSS and FES without influence of quartz tolerancies (d10Bit_RX)1)4)5) t63 SR 966 - 1046.1 ns RxD capture by fsample (RxDA/RxDB sampling flip-flop) (dRxAsym)5) t64-t65 - - 3.0 ns Asymmetrical delay of rising and falling edge (RxDA, RxDB) TxD data delay from sampling flip-flop dTxdly - - 10.0 ns Px_PDR.PDy = 000B - - 15.0 ns Px_PDR.PDy = 001B - - 10.0 ns RxD capture delay by sampling flip-flop ns CC CC CC dRxdly Asymmetrical delay of rising and falling edge (TxDA, TxDB) CC 1) This includes the PLL_ERAY accumulated jitter. 2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers. Quarz tolerance and PLL_ERAY accumulated jitter are not included. 3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |tFA2 - tRA2| 1 ns. 4) Limits of 966ns and 1046.1ns correspond to (30%, 70%) * VDDP FlexRay standard input thresholds. For input thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied. Data Sheet 62 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersAC Parameters 5) Valid for output slopes of the bus driver of dRxSlope 5ns, 20% * VDDP to 80% * VDDP, according to the FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming signal have to satisfy the following inequality: -1.6ns tFA2 - tRA2 1.3ns. Last CRC Byte BSS (Byte Start Sequence) FES (Frame End Sequence) 0.7 VDD 0.3 VDD TXD t60 tsample TXD 0.9 VDD 0.1 VDD t61 t62 Last CRC Byte BSS (Byte Start Sequence) FES (Frame End Sequence) 0.7 VDD 0.3 VDD RXD t63 tsample RXD 0.7 VDD 0.3 VDD t64 t65 ERAY_TIMING Figure 24 Data Sheet ERAY Timing 63 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersPackage and Reliability 5.4 Package and Reliability 5.4.1 Package Parameters Table 45 Thermal Characteristics of the Package Device Package RJCT1) RJCB1) RJLead Unit Note TC1782 / TC1182 PG-LQFP-17610 8,1 0,3 30,9 K/W with soldered exposed pad 2) TC1782 / TC1182 PG-LQFP-17610 8,1 12,6 30,9 K/W with not soldered exposed pad 1) The top and bottom thermal resistances between the case and the ambient (RTCAT, RTCAB) are to be combined with the thermal resistances between the junction and the case given above (RTJCT, RTJCB), in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ = TA + RTJA x PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances. Thermal resistances as measured by the 'cold plate method' (MIL SPEC-883 Method 1012.1). 2) It is recommended by Infineon Technologies AG to connect the exposed pad. Data Sheet 64 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersPackage and Reliability 5.4.2 Package Outline Exposed DIPAD Figure 25 Package Outlines PG-LQFP-176-10 Table 46 Exposed pad Dimensions Ex 7.8 mm Ey 7.8 mm You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products. 5.4.3 Flash Memory Parameters The data retention time of the TC1782 / TC1182's Flash memory depends on the number of times the Flash memory has been erased and programmed. Data Sheet 65 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersPackage and Reliability Table 47 FLASH32 Parameters Parameter Symbol Values Min. Unit Typ. Max. Note / Test Condition Data Flash Erase Time per Sector tERD CC - - 3 s Program Flash Erase Time per 256 KByte Sector tERP CC - - 5 s Program time data flash per page1) tPRD CC - - 5.3 ms without reprogramming - - 15.9 ms with two reprogramming cycles tPRP CC - - 5.3 ms without reprogramming - - 10.6 ms with one reprogramming cycle - cycle Max. data s retention time 5 years - 15 ms - - s Program time program flash per page2) Data Flash Endurance Erase suspend delay NE CC 60000 - 3) tFL_ErSusp - CC Wait time after margin change tFL_Margin 10 Del CC Program Flash Retention Time, Physical Sector4)5) tRET CC 20 - - year s Max. 1000 erase/program cycles Program Flash Retention Time, Logical Sector4)5) tRETL CC 20 - - year s Max. 100 erase/program cycles UCB Retention Time4)5) tRTU CC 20 - - year s Max. 4 erase/program cycles per UCB Wake-Up time tWU CC - 270 s Data Sheet - 66 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersPackage and Reliability Table 47 FLASH32 Parameters (cont'd) Parameter Symbol Values Min. DFlash wait state configuration WSDF PFlash wait state configuration WSPF Typ. 50 ns x - fFSI 26 ns x - fFSI CC CC Unit Max. Note / Test Condition - - 1) In case the Program Verify feature detects weak bits, these bits will be programmed up to twice more. Each reprogramming takes additional 5 ms. 2) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The reprogramming takes additional 5 ms. 3) Only valid when a robust EEPROM emulation algorithm is used. For more details see the Users Manual. 4) Storage and inactive time included. 5) At average weighted junction temperature Tj = 100C, or the retention time at average weighted temperature of Tj = 110C is minimum 10 years, or the retention time at average weighted temperature of Tj = 150C is minimum 0.7 years. 5.4.4 Table 48 Quality Declarations Quality Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. - - 24000 hours -2) ESD susceptibility VHBM according to Human Body Model (HBM) - - 2000 V Conforming to JESD22-A114-B ESD susceptibility VHBM1 of the LVDS pins - - 500 V - ESD susceptibility VCDM according to Charged Device Model (CDM) - - 500 V Conforming to JESD22-C101-C Moisture Sensitivity Level - - 3 - Conforming to Jedec J-STD-020C for 240C Operation Lifetime1) tOP MSL 1) This lifetime refers only to the time when the device is powered on. Data Sheet 67 V 1.1, 2011-06 TC1782 / TC1182 Electrical ParametersPackage and Reliability 2) For worst-case temperature profile equivalent to: 1200 hours at Tj = 125...150oC 3600 hours at Tj = 110...125oC 7200 hours at Tj = 100...110oC 11000 hours at Tj = 25...100oC 1000 hours at Tj = -40...25oC Data Sheet 68 V 1.1, 2011-06 TC1782 / TC1182 History 6 History The following changes where done between Version 0.7 and 0.8 of this document: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Change product name from SAK-TC1782-320F180HL to SAK-TC1782-320F180HR Change product name from SAK-TC1782-256F133HL to SAK-TC1782-256F133HR Change DFLASH size from 64Kbyte to 128Kbyte in chapter 1 Add ADC module abbreviation to table 1 Analog Input Port Function description Change SCU_RTID and SCU_CHIPID values to match the step Extend VDDOSC3 to -7.5 % Add parameter HYSA1+ Add parameter HYSA2 Add parameter VILF / VIHF Add parameter RDSONF Changed typical value of CAINSW from 7 to 9 pF Changed typical value of CAINTOT from 25 to 20 pF Remove 3.3 V values from ADC section Add parameter fADC Changed max. value of fADCI from 20 to 18 MHz Remove parameter IAIN7T (covered by RAIN7T ) Replace parameter IAREF by QCONV Changed typical value of RAIN from 700 to 900 Ohm Add parameter tS Add footnote to max value of TUE Add parameter fFADC Add parameter tC Add formula for DTS temperature calculation Adapt current values to reduced limits of BA step Add clarification to parameter ILVDS Remove parameter RTHJA (not required) Add clarification to parameter tPOH description Add clarification to parameter tPOS description Add min. value to parameters tL Changed typical value of fPLLBASE_ERAY from 200 to 250 MHz Add MSC t45 behavior for CMOS / LVDS usage Add RTHs for non soldered exposed pad Add table 33 Change DTS accuracy to 6C of the complete temperature range Remove limitations of the DFLASH and PFLASH operating in extended Range operating conditions Change package version von PG-LQFP-176-6 to PG-LQFP-176-12 The following changes where done between Version 0.8 and 1.0 of this document: * Change package version von PG-LQFP-176-12 to PG-LQFP-176-10 Data Sheet 1 V 1.1, 2011-06 TC1782 / TC1182 History * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * improve description in table 2 for analog channels add class A1+ to type list of table 2 add clarification that table 7 defines the conditions for all other parameters add note the spike filter is only available for the PORST pin add Vil to Vih ratio for A1+ pad remove irritating Note / Test Conditions adapt maximum power dissipation values add conditions for MLI, MSC, SSC, parameters changed definition for t13 and t14 of the MLI timing changed definition for t45 of the MSC timing add parameters dTxdly and dRxdly to ERAY parameters correct ERAY parameters t60 and t63 values correct footnotes for ERAY parameters split flash parameters tPRD and tPRP in two conditions add conditions to LVDS pad parameters Changed VAREFx to VAREF0 and VAGNDx to VAGND0 remove Pin Reliability in Overload section add parameters IIN and Sum IIN to absolute ratings adjust thresholds in figure 28 (ERAY) add parameter HYSX to PSC_XTAL added RDSON values for all driver settings (weak, medium, and strong) removed footnote 2 of table 6 change conditions for RDSON weak parameters change load for timing of SSC, MSC, and MLI from CL = 25 pF to CL = 50 pF (typical) add type I to legend of table 2 add SAK-TC1782-320F180HL and SAK-TC1782-256F133HL changed timing checkpoints in figure 23 add section 5.2.6.1 add to parameters tRF and tFF condition CL = 50 pF add new footnote 7) to ADC parameter table add min and max value for QCONV and adapt typ value add load conditions for tFF1 and tRF1 add conditions to PLL parameter tL change DAP parameter t19 from SR to CC classification remove footnote 2 for the FADC increase current for IDDP_POR from 2 to 2.5mA add footnote 3 to table 9 change SAK-TC1782-320F180HR / SAK-TC1782-320F180HL to SAK-TC1782F320F180HR / SAK-TC1782F-320F180HL change SAK-TC1782-256F133HR / SAK-TC1782-256F133HL to SAK-TC1782F256F133HR / SAK-TC1782F-256F133HL add information for the following products: - SAK-TC1782N-320F180HR Data Sheet 2 V 1.1, 2011-06 TC1782 / TC1182 History - - - - - - - SAK-TC1782N-320F180HL SAK-TC1182N-320F180HR SAK-TC1182N-320F180HL SAK-TC1782N-256F133HR SAK-TC1782N-256F133HL SAK-TC1182N-256F133HR SAK-TC1182N-156F133HL The following changes where done between Version 1.0 and 1.1 of this document: * * * * * * * * * add section Pin Reliability in Overload remove sentence `Exposure to conditions within the maximum ratings will not affect device reliability. To replace this sentence section Pin Reliability in Overload was added. increase values for absolute maximum parameters IIN and SumIIN remove capacitance conditions for LVDS pad parameters as loads are defined by interface (MSC) timings remove term typical from load of Peripheral Timings add definition of driver strength settings for ERAY Interface Timing change footnote 4 wording for ERAY timing back to TC1797 wording increase flash parameters tPRD and tPRP values rework the 3.3 V current part of the Power Supply Parameters for better description and usage - Parameters IDDP_FP, IDDFL3E and IDDFL3R are removed and replaced in the following way - IDDP_FP is replaced by IDDP with the condition including flash programming current - IDDFL3E is replaced by IDDP with the condition including flash erase verify current - IDDFL3R is replaced by IDDP with the condition including flash read current - parameter IDDFL3R was renamed to IDDFL3 The rework of the 3.3 V current part of the Power Supply Parameters was done for simplification and clarification. Former given values could still be used if liked, the new definition results in the same resulting values or slightly better values. The flash module is supplied via IDDFL3 and IDDP. For the different flash operating modes in worst case different allocations for the two domains resulting. The application typical case `flash read' has max IDDP of 12 mA and max IDDFL3 of 56 mA resulting is a sum of 68 mA. The case `flash programming' has max IDDP of 27 mA and max IDDFL3 of 21 mA resulting is a sum of 48 mA. The case `flash erase verify' has max IDDP of 20 mA and max IDDFL3 of 56 mA resulting is a sum of 76 mA. for the old parameter IDDP with 15 mA, the new version reads as IDDP = 12+IDDP_PORST = 14.5 mA for the same application relevant case. So Data Sheet 3 V 1.1, 2011-06 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG