Data Sheet
V 1.1 2011-06
Microcontrollers
32-Bit
Microcontroller
TC1782 / TC1182
32-Bit Single-Chip Microcontroller
Edition 2011-06
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein , any typical values stated herein and/or any
information regard ing the application of t he device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limit ation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements , compone nts may contain dangerous substances. For information on the types in
question, please cont act the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
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of that life-suppo rt device or system or to affect the safety or effectiveness of t hat device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human lif e. If they fa il, it is reasona ble to assume that th e healt h of the user or other per so ns may
be endangered.
Data Sheet
V 1.1 2011-06
Microcontrollers
32-Bit
Microcontroller
TC1782 / TC1182
32-Bit Single-Chip Microcontroller
Data Sheet I-1 V 1.1, 2011-06
TC1782 / TC1182
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2 System Overview of the TC1782 / TC1182 . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 TC1782 / TC1182 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
4 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
5 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.2 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.1.4 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.1.5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.2.2 Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5.2.3 Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . 5-33
5.2.4 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
5.2.5 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
5.2.6 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
5.2.6.1 Calculating the 1.3 V Current Consumption . . . . . . . . . . . . . . . . . 5-42
5.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
5.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43
5.3.2 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
5.3.3 Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46
5.3.4 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49
5.3.5 ERAY Phase Locked Loop (ERAY_PLL) . . . . . . . . . . . . . . . . . . . . . . 5-51
5.3.6 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52
5.3.7 DAP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54
5.3.8 Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56
5.3.8.1 Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . 5-56
5.3.8.2 Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . 5-58
5.3.8.3 SSC Master/Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60
5.3.8.4 ERAY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62
5.4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64
5.4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64
5.4.2 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
5.4.3 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
Table of Contents
Data Sheet I-2 V 1.1, 2011-06
TC1782 / TC1182
5.4.4 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67
6History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
TC1782 / TC1182
Data Sheet 3 V 1.1, 2011-06
TC1782 / TC1182
Data Sheet 4 V 1.1, 2011-06
TC1782 / TC1182
Summary of Features
Data Sheet 1 V 1.1, 2011-06
1 Summary of Features
The SAK-TC1782F-320F180HR /SAK-TC1782F-320F180HL has the following
features:
High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipelin e
Superior real-time performance
Strong bit handling
Fully integrated DSP capabilities
Single precision Floati ng Point Unit (FPU)
180 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
16 Kbyte Parameter Memory (PRAM)
32 Kbyte Code Memory (CMEM)
180 MHz operation at full temperature range
Multiple on-chip memories
2.5 Mbyte Program Flash Memory (PFLASH) with ECC
128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
128 Kbyte Data Memory (LDRAM)
Instruction Cache: up to 16 Kbyte (ICACHE, configurable)
40 Kbyte Code Scratchpad Memory (SPRAM)
Data Cache: up to 4 Kbyte (DCACHE, configurable)
8 Kbyte Overlay Memory (OVRAM)
16 Kbyte BootROM (BROM)
16-Channel DMA Controller
Sophisticated interrupt system with 2 ×255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus stru cture
64-bit Local Memory Buses betwe en CPU, Flash and Data Memory
32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
One bus bridge (LFI Bridge)
Versatile On-chip Peripheral Units
Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
Three High-Speed Syn chronous Serial Channels (SSC) with programma ble data
length and shift dire ction
One serial Micro Second Bus interface (MSC) for serial port expansion to external
power devices
One High-Speed Micro Link interface (MLI) for serial inter-processor
communication
One MultiCAN Module with 3 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
One FlexRayTM module with 2 channels (E-Ray).
TC1782 / TC1182
Summary of Features
Data Sheet 2 V 1.1, 2011-06
One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell
Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
32 analog input lines for ADC
2 independent kernels (ADC0 and ADC1)
Analog supply voltage range from 3.3 V to 5 V (single supp ly)
4 different FADC input channels
channels with impedance control and overlai d with ADC1 inputs
Extreme fast conversion, 21 cycles of fFADC clock
10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
86 digital general purpose I/O lines (GPIO), 4 input lines
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
Dedicated Emulation Device chip available (TC1782 / TC1182ED)
multi-core debugging, real time tracing, and calibration
four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL
TC1782 / TC1182
Summary of Features
Data Sheet 3 V 1.1, 2011-06
The SAK-TC1782F-256F133HR / SAK-TC1782F-256F133HL has the following
features:
High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipelin e
Superior real-time performance
Strong bit handling
Fully integrated DSP capabilities
Single precision Floati ng Point Unit (FPU)
133 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
16 Kbyte Parameter Memory (PRAM)
32 Kbyte Code Memory (CMEM)
133 MHz operation at full temperature range
Multiple on-chip memories
2 Mbyte Program Flash Memory (PFLASH) with ECC
128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
128 Kbyte Data Memory (LDRAM)
Instruction Cache: up to 16 Kbyte (ICACHE, configurable)
40 Kbyte Code Scratchpad Memory (SPRAM)
Data Cache: up to 4 Kbyte (DCACHE, configurable)
8 Kbyte Overlay Memory (OVRAM)
16 Kbyte BootROM (BROM)
16-Channel DMA Controller
Sophisticated interrupt system with 2 ×255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus stru cture
64-bit Local Memory Buses betwe en CPU, Flash and Data Memory
32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
One bus bridge (LFI Bridge)
Versatile On-chip Peripheral Units
Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
Three High-Speed Syn chronous Serial Channels (SSC) with programma ble data
length and shift dire ction
One serial Micro Second Bus interface (MSC) for serial port expansion to external
power devices
One High-Speed Micro Link interface (MLI) for serial inter-processor
communication
One MultiCAN Module with 3 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
TC1782 / TC1182
Summary of Features
Data Sheet 4 V 1.1, 2011-06
One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell
Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
32 analog input lines for ADC
2 independent kernels (ADC0 and ADC1)
Analog supply voltage range from 3.3 V to 5 V (single supp ly)
4 different FADC input channels
channels with impedance control and overlai d with ADC1 inputs
Extreme fast conversion, 21 cycles of fFADC clock
10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
86 digital general purpose I/O lines (GPIO), 4 input lines
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
Dedicated Emulation Device chip available (TC1782 / TC1182ED)
multi-core debugging, real time tracing, and calibration
four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL
The SAK-TC1782N-320F180HR / SAK-TC1782N-320F180HL /SAK-TC1182N-
320F180HR / SAK-TC1182N-320F180HL has the following features:
High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipelin e
Superior real-time performance
Strong bit handling
Fully integrated DSP capabilities
Single precision Floati ng Point Unit (FPU)
180 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
16 Kbyte Parameter Memory (PRAM)
32 Kbyte Code Memory (CMEM)
180 MHz operation at full temperature range
Multiple on-chip memories
2.5 Mbyte Program Flash Memory (PFLASH) with ECC
128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
128 Kbyte Data Memory (LDRAM)
Instruction Cache: up to 16 Kbyte (ICACHE, configurable)
40 Kbyte Code Scratchpad Memory (SPRAM)
Data Cache: up to 4 Kbyte (DCACHE, configurable)
8 Kbyte Overlay Memory (OVRAM)
16 Kbyte BootROM (BROM)
16-Channel DMA Controller
TC1782 / TC1182
Summary of Features
Data Sheet 5 V 1.1, 2011-06
Sophisticated interrupt system with 2 ×255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus stru cture
64-bit Local Memory Buses betwe en CPU, Flash and Data Memory
32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
One bus bridge (LFI Bridge)
Versatile On-chip Peripheral Units
Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
Three High-Speed Syn chronous Serial Channels (SSC) with programma ble data
length and shift dire ction
One serial Micro Second Bus interface (MSC) for serial port expansion to external
power devices
One High-Speed Micro Link interface (MLI) for serial inter-processor
communication
One MultiCAN Module with 3 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell
Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
32 analog input lines for ADC
2 independent kernels (ADC0 and ADC1)
Analog supply voltage range from 3.3 V to 5 V (single supp ly)
4 different FADC input channels
channels with impedance control and overlai d with ADC1 inputs
Extreme fast conversion, 21 cycles of fFADC clock
10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
86 digital general purpose I/O lines (GPIO), 4 input lines
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
Dedicated Emulation Device chip available (TC1782 / TC1182ED)
multi-core debugging, real time tracing, and calibration
four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL
TC1782 / TC1182
Summary of Features
Data Sheet 6 V 1.1, 2011-06
The SAK-TC1782N-256F133HR /SAK-TC1782N-256F133HL / SAK-TC1182N-
256F133HR /SAK-TC1182N-256F133HL has the following features:
High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipelin e
Superior real-time performance
Strong bit handling
Fully integrated DSP capabilities
Single precision Floati ng Point Unit (FPU)
133 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
16 Kbyte Parameter Memory (PRAM)
32 Kbyte Code Memory (CMEM)
133 MHz operation at full temperature range
Multiple on-chip memories
2 Mbyte Program Flash Memory (PFLASH) with ECC
128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
128 Kbyte Data Memory (LDRAM)
Instruction Cache: up to 16 Kbyte (ICACHE, configurable)
40 Kbyte Code Scratchpad Memory (SPRAM)
Data Cache: up to 4 Kbyte (DCACHE, configurable)
8 Kbyte Overlay Memory (OVRAM)
16 Kbyte BootROM (BROM)
16-Channel DMA Controller
Sophisticated interrupt system with 2 ×255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus stru cture
64-bit Local Memory Buses betwe en CPU, Flash and Data Memory
32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
One bus bridge (LFI Bridge)
Versatile On-chip Peripheral Units
Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
Three High-Speed Syn chronous Serial Channels (SSC) with programma ble data
length and shift dire ction
One serial Micro Second Bus interface (MSC) for serial port expansion to external
power devices
One High-Speed Micro Link interface (MLI) for serial inter-processor
communication
One MultiCAN Module with 3 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
TC1782 / TC1182
Summary of Features
Data Sheet 7 V 1.1, 2011-06
One General Purpose Timer Array Module (GPTA) with additional Local Timer Cell
Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
32 analog input lines for ADC
2 independent kernels (ADC0 and ADC1)
Analog supply voltage range from 3.3 V to 5 V (single supp ly)
4 different FADC input channels
channels with impedance control and overlai d with ADC1 inputs
Extreme fast conversion, 21 cycles of fFADC clock
10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
86 digital general purpose I/O lines (GPIO), 4 input lines
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
Dedicated Emulation Device chip available (TC1782 / TC1182ED)
multi-core debugging, real time tracing, and calibration
four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
Power Management System
Clock Generation Unit with PLL
TC1782 / TC1182
Summary of Features
Data Sheet 8 V 1.1, 2011-06
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
The package and the type of delivery.
For the available ordering codes for the TC1782 / TC1182 please refer to the “Product
Catalog Microcontrollers”, which summarizes all available microcontroller variants.
This document describes the derivatives of the device.The Table 1 enumerates these
derivatives and summarizes the differences.
Table 1 TC1782 / TC1182 Derivative Synopsis
Derivative Ambient Temperature Range
SAK-TC1782F-320F180HR TA = -40oC to +125oC
SAK-TC1782F-320F180HL TA = -40oC to +125oC
SAK-TC1782N-320F180HR TA = -40oC to +125oC
SAK-TC1782N-320F180HL TA = -40oC to +125oC
SAK-TC1182N-320F180HR TA = -40oC to +125oC
SAK-TC1182N-320F180HL TA = -40oC to +125oC
SAK-TC1782F-256F133HR TA = -40oC to +125oC
SAK-TC1782F-256F133HL TA = -40oC to +125oC
SAK-TC1782N-256F133HR TA = -40oC to +125oC
SAK-TC1782N-256F133HL TA = -40oC to +125oC
SAK-TC1182N-256F133HR TA = -40oC to +125oC
SAK-TC1182N-256F133HL TA = -40oC to +125oC
TC1782 / TC1182
System Overview of the TC1782 / TC1182
Data Sheet 1 V 1.1, 2011-06
2 System Overview of the TC1782 / TC1182
The TC1782 / TC1182 combines three powerful technologies within one silicon die,
achieving new levels of power, speed, and economy for embedded applications:
Reduced Instruction Set Computi ng (RISC) processor architecture
Digital Signal Processing (DSP) operations and addressing modes
On-chip memories and peripherals
DSP operations and addressin g modes provide the computational power necessary to
efficiently analyze complex real-world signals. The RISC load/store architecture
provides high computational bandwidth with low system cost. On-chip memory and
peripherals are designed to support even the most demanding high-bandwidth real-time
embedded control-systems tasks.
Additional high-level features of the TC1782 / TC1182 include:
Efficient memory organization: instruction and data scratch memories, caches
Serial communication interfaces – flexible synchron ous and asynchronous modes
Periphera l Co nt rol Processor – standalone data operations and interrupt servicing
DMA Controller – DMA operations and interrupt servicing
General-purpose timers
High-performance on-chip buses
On-chip debugging and emulation facilities
Flexible interconnections to external components
Flexible power-management
The TC1782 / TC1182 is a high-performance microcontroller with TriCore CPU, program
and data memories, buses, bus arbitration, an interrupt controller, a peripheral control
processor and a DMA controller and several on-chip peripherals. The TC1782 / TC1182
is designed to meet the needs of the most demanding embedded control systems
applications where the competing issues of price/performance, real-time
responsiveness, computational power, data bandwidth, and power consumption are key
design elements.
The TC1782 / TC1182 offers several versatile on-chip peripheral units such as serial
controllers, timer units, and Analog-to-Dig ital converters. Within the T C1782 / TC1182,
all these peripheral units are connected to the TriCore CPU/system via the Flexible
Peripheral Interconnect (FPI) Bus and the Local Memory Bus (LMB). Several I/O lines
on the TC1782 / TC1182 ports are reserve d for these peripheral units to communicate
with the external world.
TC1782 / TC1182
System Overview of the TC1782 / TC1182Block Diagrams
Data Sheet 2 V 1.1, 2011-06
2.1 Block Diagrams
Figure 1 shows the block diagram of the SAK-TC1782-320F180HR / SAK-TC1782-
320F180HL.
Figure 1 SAK-TC1782-320F180HR / SAK-TC17 82-320F180HL Block Diagram
Figure 2 shows the block diagram of the SAK-TC1782N-320F180HR / SAK-TC1782N-
320F180HL / SAK-TC1182N-320F180HR / SAK-TC1182N-320F180HL.
E-Ray
(2 Channels)
OCDS
L1 D eb ug
Interface/ JTAG
MLI0
MemCheck
FADC
TriCore
CPU
PMI
Interrupt
System
FPI-Bu s Interface
16 KB PRAM
PCP2
Core
32 KB CMEM
Interrupts
Sy stem Peripheral Bus
System Peripheral Bus
(SPB)
SSC0
SBCU
Bridge
SMIF
DMI
LDRAM
DCACHE
CPS
BCU
PMU
GPTA0
Multi
CAN
(3 N o d es,
128 MO)
ASC0
ASC1
MSC0
(LVDS )
SSC1
STM
SCU
Ports
Ext.
Request
Unit
LTCA2
2,5 MB PFlash
128 KB DFlash
8 KB OVRAM
16 KB BROM
ADC0
ADC1
BlockDiagram
SAK-TC1782-320F180HR
M
M/S
3.3V
Ext. FADC Supply
24 KB SPRAM
16 KB ICACHE
(Configurable)
124 KB LDRAM
4 K B DCACHE
(Configurable)
FPU
PLL
E-RAY
PLL
f
E-Ray
f
CPU
Abbreviations:
ICACHE: Instruction Cache
DCACHE Da ta Cache
SPRAM: Scratch-Pad RAM
LDRAM: Local Data RAM
OVRAM: Overlay RAM
BROM: Boot ROM
PFlash: Program Flash
DFlash: Data Flash
PRAM: Parameter RAM in PCP
PCODE: Code RAM in PCP
DMA
16 chan n els
28
(3.3V max)
(5V max)
4
4
SSC2
5V (3.3V supported as well)
Ext. ADC Supply
Local Memory B u s (LMB)
TC1782 / TC1182
System Overview of the TC1782 / TC1182Block Diagrams
Data Sheet 3 V 1.1, 2011-06
Figure 2 SAK-TC1782N-320F180HR / SAK-TC1782N-320F180HL /
SAK-TC1182N-320F180HR / SAK-TC1182N-320F180HL /
Block Diagram
Figure 3 shows the block diagram of the SAK-TC1782F-256F133HR / SAK-TC1782F-
256F133HL / SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL / SAK-
TC1182N-256F133HR / SAK-TC1182N-256F133HL.
OCDS
L1 D eb ug
Interface/JTAG
MLI0
MemCheck
FADC
TriCore
CPU
PMI
Interrupt
System
FPI-B u s Interface
16 KB PRAM
PCP2
Core
32 KB CMEM
Interrupts
Sy ste m Peripheral Bus
Sy stem Peripheral Bus
(SPB)
SSC0
SBCU
Bridge
SMIF
DMI
LDRAM
DCACHE
CPS
BCU
PMU
GPTA0
Multi
CAN
(3 Nod es,
128 MO)
ASC0
ASC1
MSC0
(LVDS )
SSC1
STM
SCU
Ports
Ext.
Request
Unit
LTCA2
2,5 MB PFlas h
128 KB DFlash
8 KB OVRAM
16 KB BROM
ADC0
ADC1
BlockDiagram
SAK-TC1782N-320F180HR
M
M/S
3.3V
Ext. FADC Supply
24 KB SPRAM
16 KB ICACHE
(Configurable)
124 KB LDRAM
4 KB DCA CHE
(Configurable)
FPU
PLL
E-RAY
PLL
f
E-Ray
f
CPU
Abbreviations:
ICACHE: Instruction Cache
DCACHE Da ta Cache
SPRAM: Scratch-Pad RAM
L DRAM: L oc al Dat a RAM
OVRAM: Overlay RAM
BROM: Boot ROM
PFlash: Program Flash
DFlash: Data Flash
PRAM: Parameter RAM in PCP
PCODE: Code RAM in PCP
DMA
16 chan nels
28
(3.3V max)
(5V max)
4
4
SSC2
5V (3.3V supported as well)
Ext. ADC Supply
Local Memory Bus (LMB)
TC1782 / TC1182
System Overview of the TC1782 / TC1182Block Diagrams
Data Sheet 4 V 1.1, 2011-06
Figure 3 SAK-TC1782F-256F133HR / SAK-TC1782F-256F133HL /
SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL /
SAK-TC1182N-256F133HR / SAK-TC1182N-256F133HL
Block Diagram
OCDS
L1 Debug
Interface/JTAG
MLI0
MemCheck
FADC
TriCore
CPU
PMI
Interrupt
System
FP I-B u s Inter face
16 KB PRAM
PCP2
Core
32 KB CMEM
Interrupts
System Peripheral Bus
System Peripheral Bus
(SPB)
SSC0
SBCU
Bridge
SMIF
DMI
LDRAM
DCACHE
CPS
BCU
PMU
GPTA0
Multi
CAN
(3 Node s,
128 MO)
ASC0
ASC1
MSC0
(LVDS )
SSC1
STM
SCU
Ports
Ext.
Request
Unit
LTCA2
2 MB PFlash
64 KB DFlash
8 KB OVRAM
16 KB BROM
ADC0
ADC1
BlockDiagram
SAK-TC1782-256F133HR
M
M/S
3.3V
Ext. FADC Supply
24 KB SPRAM
16 KB ICACHE
(Configurable)
124 KB LDRAM
4 KB DCACHE
(Configurable)
FPU
PLL
E-RAY
PLL
f
E-Ray
f
CPU
Abbreviations:
ICACHE: Instruction Cache
DCACHE Da ta Cac he
SPRAM: Scratch-Pad RAM
L DRAM: Local Data RAM
OVRAM: Overlay RAM
BROM: Boot ROM
PFlash: Program Flash
DFlash: Data Flash
PRAM: Parameter RAM in PCP
PCODE: Code RAM in PCP
DMA
16 ch an nel s
28
(3.3V max)
(5V max)
4
4
SSC2
5V (3.3V supported as well)
Ext. ADC Supply
Local Memory Bus (LMB)
TC1782 / TC1182
Pinning
Data Sheet 1 V 1.1, 2011-06
3 Pinning
Figure 4 is showing the TC178 2 / TC1182 Logic Symbol.
Figure 4 TC1782 / TC1182 Logic Symbol
TESTMODE
ESR0
PORST
D i gi tal C ir cuitry
Power Suppl y
Gener al C ontrol
AN[35:0]Analog Inputs V
DDM
V
SSM
V
DDMF
V
SSMF
V
DDAF
V
AREF0
V
AGND0
V
FAREF
V
FAGND
V
DDFL3
Analog Pow er
Supply
TC1782_LQFP-176-10
V
DDOSC3
Alternate Funct ions
Oscillator
GPTA, SCU, E-RAY,
MSC0
GPTA, SSC0/1,
MLI0, MSC0
GPTA, ASC0/1, SSC 0/1,
SCU, CAN, MSC0
GPTA , SCU , CAN
V
DDOSC
GPTA, MLI0, E -RAY,
SSC2
V
SSOSC
TC1782
/
TC1182
Port 0
16
Port 1
16
Port 2
14
Port 3
16
Port 4
4
Port 5
16
Port 6
4GPTA, MS C0
XTAL2
XTAL1
V
SS
11
V
DDP
10
V
DD
9
ESR1
TRST
TCK / DAP 0
TDI / B RKIN
TDO / DA P2 /
BRKOUT
TMS / DAP 1
OCDS /
JTAG Control
GPT A , SSC 1 ,
ADC0, OCDS
1)
1)
1) Only available for SAK -TC1782 F-320 F180 HR
and SAK -TC1782F-320F180 HL
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 2 V 1.1, 2011-06
3.1 TC1782 / TC1182 Pin Configuration
This chapter shows the pin configuration of the TC1782 / T C1182 package PG-LQFP-
176-10.
Figure 5 SAK-TC1782-320F180HR / SAK-TC1782-320F180HL Pinning
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
39
40
41
42
43
44
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
30
31
32
33
34
35
36
37
38
45
46
47
48
49
50
51
52
53
97
96
95
94
93
92
91
90
89
100
99
98
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
13 3
13 4
13 5
13 6
137
13 8
13 9
14 0
14 1
14 2
14 3
14 4
14 5
14 6
147
14 8
14 9
15 0
15 1
15 2
153
154
155
156
157
158
159
160
161
162
16 3
16 4
16 5
16 6
167
16 8
16 9
17 0
17 1
17 2
17 3
17 4
17 5
17 6
P0.0 /IN0 /HW CF G0/O UT0 /OUT56
P0.1 /IN1 /HWCF G1/O UT1 /OUT 57 /SDI1
P0.2 /IN2 /HW CF G2/O UT2 /OUT58
P0.3 /IN3 /HW CF G3/O UT3 /OUT59
P0.4 /IN4 /HW CF G4/O UT4 /OUT60
P0.5 /IN5 /HW CF G5/O UT5 /OUT61
P0.6 /IN6 /HW CF G6/RE Q 2/O U T6 /OUT 62
P0.7 /IN7 /HW CF G7/RE Q 3/O U T7 /OUT 63
P0.8 /IN8/RXDA0/OU T8/OUT64
P0.9 /IN9/RXDB0/OU T9/OUT65
P0.1 0/IN 10/OUT1 0/TXDA0
P0.1 1/IN 11/OUT1 1/TXDB0
P0.1 2/IN 12/OUT1 2/TXENA
P0.1 3/IN 13/OUT1 3/TXENB
P 0.1 4/IN 14/R EQ 4/O U T1 4/F CLP 0C
P0.1 5/IN 15/R EQ 5/O UT1 5/SOP 0 C
P1.0/IN16/OUT16/OUT72/BRKIN/BRKOUT
P1.15/BRKIN/BRKOUT
P1.2/IN18/OUT18/OUT74
P1.3 /IN19 /OUT 19 /OUT 75
P1.4/ IN20 /EM GST OP/OUT 20 /OUT 76
P1.5/IN21/OUT21/OUT77
P1.6/IN22/OUT22/OUT78
P1.7/IN23/OUT23/OUT79
P1.8/ IN24 /IN48 /M T SR1 B/ OUT 24/OUT 48
P1.9/ IN25 /IN49 /M RS T1 B/ OUT 25/OUT 49
P1.10 /IN26 /IN 50/OUT 26 /OUT 50 /SLSO 17
P1.11 /IN27 /IN 51/SCLK 1B/OUT 27 /OUT 51
AD0EM UX0/OU T1 6/IN1 6/P 1 .12
AD0EM UX1/O UT1 7/IN1 7/P 1 .13
AD0EM UX2/O UT1 8/IN1 8/P 1 .14
T CLK0/ OUT 28/ OUT 32/I N32 /P2.0
SLSO13/SLSO03/OUT33/TREADY0A/IN33/P2.1
T VALID0 A/ OUT 29/ OUT 34/I N34/ P2 .2
T DATA0/ OUT 30/ OUT 35/I N35/ P2 .3
OUT31 /OUT 36/ RCLK0A/I N36/ P2 .4
RREADY 0A/O UT3 7/OU T1 10/I N37/ P2 .5
O UT3 8/O UT1 11/ RV AL ID0A /I N38/ P 2.6
OUT39/RDATA0A/IN39/P2.7
P2.8 /SLS O0 4/SLSO 14/ EN0 0
P2.9 /SLS O0 5/SLSO 15/ EN0 1
P2.1 0/IN 10/O UT0 /M RST 1A
P2.1 1/IN 11/O UT1 /SCLK 1 A/ FCL P0 B
P2.1 2/IN 12/O UT2 /M TSR1A /SO P 0B
P2.1 3/IN 13/OUT3 /SLSI1 1/SDI0
P3.0 /OUT 84 /RX D0A
P3.1 /OUT 85 //TXD 0
P3.2/OUT86/ SCLK0
P3.3/OUT87/ MRST0
P3.4/OUT88/MTSR0
P3.5/SLSO00/SLSO10/SLSO00&SLSO10
P3.6/SLSO01/SLSO11/SLSO01&SLSO11
P3.7/SLSI01/OUT89/SLSO02/SLSO12
P3.8/ SLSO06 /OUT 90 /TXD1
P3.9 /OUT 91 /RX D1A
P3.1 0/O UT9 2/REQ0
P3.1 1/O UT9 3/REQ1
P3.1 2/O UT9 4/RXDCAN0 /RX D0B
P3.1 3/O UT9 5/T XDCA N0/T XD0
P3.1 4/O UT9 6/RXDCAN1 /RXD1B/SDI2
P3.1 5/O UT9 7/T XDCA N1/T XD1
OUT52 /OUT28/IN52/IN2 8/RXDCAN2/P4.0
O UT5 3/O UT2 9/IN5 3/I N29/ TXDCA N2/ P 4.1
EXT CLK 1/O UT5 4/O UT3 0/IN 54/I N30/ P 4.2
P4.3/ IN31 /IN55 /OUT 31 /OUT 55 /EX TCLK0
SLSCO20/OUT40/OUT8/IN40/IN26/P5.0
SLSCO21/OUT41/OUT9/IN41/IN27/P5.1
SLSCO22 /OUT 42 /OUT 10 /IN 42/IN 28/ P5 .2
SLSCO24/OUT44/OUT12/SLSI2AIN 44/IN29/P5.4
SLSCO23/OUT43/OUT11/IN43/P5.3
M RS T2A /OUT 45 /OUT 13 /IN 45/IN 30 /P5.5
M TS R2A /OUT 46 /OUT 14 /IN 46/IN 31/ P5 .6
SCLK2/ OUT 47/ OUT 15/IN 47/ P5.7
RXDB1/TCLK0/OUT95/P5.15
TXDB1/RVALID0B/OUT90/P5.9
TXENA/RREADY0B/OUT91/P5.10
TXENB/RCLK0B/OUT92/P5.11
T DAT A0 /SLSO07 /OUT 93 /P5 .12
TVALID0B/SLSO16/P5.13
RXDA1/TREADY0B/OUT94/P5.14
T XDA 1/RDATA 0B/OUT 89 /P5. 8
P6.1/IN15/OUT5/ OUT81/FCLP0A
P6.0/IN14/OUT4/ OUT80/FCLN0
P6.3/IN25/OUT7/ OUT83/SO P0A
P6.2/IN24/OUT6/ OUT82/SO N0
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN8
AN7
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
TRST
P1 .1/IN 17/ OUT 17/ OUT 73
TDI/BRKIN/BRKOUT
TDO/DAP2/BRKIN/BRKOUT
TMS/DAP1
TCK/DAP0
ESR1
PORST
V
SS
TESTMODE
XTAL1
XTAL2
V
DD
V
DDP
V
SS
V
DD
V
DD(SB)
TC1782
V
DD
V
DDP
V
SS
V
DDMF
V
SSMF
V
DDAF
V
SS
V
FAREF
V
FAGND
V
DDM
V
SSM
V
AREF0
V
AGND0
V
DD
V
DDP
V
SS
V
DD
V
DDP
V
SS
V
SS
V
DD
V
DDP
V
SS
V
DDOSC
V
DDOSC3
V
SSOSC
V
DDFL3
V
DDP
V
SS
V
DD
V
DDP
V
SS
V
DD(SB)
V
DDP
V
SS
SAK_TC1782-320F180HR
V
DDP
V
DDP
ESR0
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 3 V 1.1, 2011-06
Figure 6 SAK-TC1782N-320F180HR / SAK-TC1782N-320F180HL /
SAK-TC1182N-320F180HR / SAK-TC1182N-320F180HL /
SAK-TC1782N-256F133HR / SAK-TC1782N-256F133HL /
SAK-TC1182N-256F133HR / SAK-TC1182N-256F133HL /
SAK-TC1782F-256F133HR / SAK-TC1782F-256F133HL Pinning
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
39
40
41
42
43
44
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
30
31
32
33
34
35
36
37
38
45
46
47
48
49
50
51
52
53
97
96
95
94
93
92
91
90
89
100
99
98
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
13 3
13 4
13 5
13 6
137
13 8
13 9
14 0
14 1
14 2
14 3
14 4
14 5
14 6
147
14 8
14 9
15 0
15 1
15 2
153
154
155
156
157
158
159
160
161
162
16 3
16 4
16 5
16 6
167
16 8
16 9
17 0
17 1
17 2
17 3
17 4
17 5
17 6
P0.0 /IN0 /HWCF G0/O UT0 /OUT 56
P0.1 /IN1 /HWCF G1/O UT1 /OUT 57 /SDI1
P0.2 /IN2 /HWCF G2/O UT2 /OUT 58
P0.3 /IN3 /HWCF G3/O UT3 /OUT 59
P0.4 /IN4 /HWCF G4/O UT4 /OUT 60
P0.5 /IN5 /HWCF G5/O UT5 /OUT 61
P0.6 /IN6 /HWCF G6/REQ 2/O UT6 /OUT 62
P0.7 /IN7 /HWCF G7/REQ 3/O UT7 /OUT 63
P0.8 /IN8 /OUT 8/O UT6 4
P0.9 /IN9 /OUT 9/O UT6 5
P0.1 0/IN 10/O UT1 0
P0.1 1/IN 11/O UT1 1
P0.1 2/IN 12/O UT1 2
P0.1 3/IN 13/O UT1 3
P0.1 4/IN 14/R EQ 4/O UT1 4/FCLP 0C
P0.1 5/IN 15/R EQ 5/O UT1 5/SOP0 C
P1 .0/ IN16 /OUT 16/ OUT 72/ BRKIN/BRKOUT
P1.15/BRKIN/BRKOUT
P1.2/IN18/OUT18/OUT74
P1.3/IN19/OUT19/OUT75
P1.4 /IN20 /EM GST OP/ OUT 20/OUT 76
P1.5/IN21/OUT21/OUT77
P1.6/IN22/OUT22/OUT78
P1.7/IN23/OUT23/OUT79
P1.8 /IN24 /IN48 /M T SR1 B/OUT 24/ OUT 48
P1.9 /IN25 /IN49 /M RST1 B/OUT 25/ OUT 49
P1.10 /IN26 /IN 50/ OUT 26/ OUT 50/SLS O 17
P1.11 /IN27 /IN 51/ S CLK1B /OUT 27 /OUT 51
AD0EM UX0/OU T1 6/IN1 6/P1 .12
AD0EM UX1/O UT1 7/IN1 7/P1 .13
AD0EM UX2/O UT1 8/IN1 8/P1 .14
T CLK 0/ OUT 28/ OU T 32/I N32 /P 2.0
SLS O 13/ SL S O03 /OUT 33 /TREADY 0A/I N33/ P2.1
T VALID0 A/ OUT 29/ OUT 34/I N34/ P2 .2
T DATA0/ OUT 30/ OUT 35/I N35/ P2 .3
OUT 31 /OUT 36/ RCLK0A/I N36/ P2 .4
RREADY 0A/O UT3 7/OU T1 10/I N37/ P2 .5
O UT3 8/O UT1 11/ RVAL ID0A/I N38/ P2.6
OUT 39/ RDATA0A /I N39/ P 2.7
P2.8/SLSO04/SLSO14/EN00
P2.9/SLSO05/SLSO15/EN01
P2.1 0/IN 10/O UT0 /M RST1A
P2.1 1/IN 11/O UT1 /SCLK1 A/ FCL P0 B
P2.12/IN 12/OUT2/MTSR1A/SOP0B
P2.1 3/IN 13/O UT3 /SLS I1 1/SDI0
P3.0 /OUT 84 /RXD0A
P3.1 /OUT 85 /TXD0
P3.2 /OUT 86 /SCLK 0
P3.3 /OUT 87 /M RST0
P3.4 /OUT 88 /M TSR0
P3.5/SLSO00/SLSO10/SLSO00&SLSO10
P3.6/SLSO01/SLSO11/SLSO01&SLSO11
P3.7/SLSI01/OUT89/SLSO02/SLSO12
P3.8 /S LSO06 /OUT 90 /T XD1
P3.9 /OUT 91 /RXD1A
P3.10/OUT92/REQ0
P3.11/OUT93/REQ1
P3.1 2/O UT9 4/RXDCAN0 /RXD0B
P3.1 3/O UT9 5/T XDCA N0/T XD0
P3.14/OUT96/RXDCAN1/RXD1B/SDI2
P3.1 5/O UT9 7/T XDCA N1/T XD1
OUT52/OUT28/IN52/IN2 8/RXDCAN2/ P4.0
O UT5 3/O UT2 9/IN5 3/I N29/ TXDCA N2/ P4.1
EX TCLK1/O UT5 4/O UT3 0/IN 54/I N30/ P 4.2
P4.3 /IN31 /IN55 /OUT 31 /OUT 55 /EX TCLK0
SLSCO20/OUT40/OUT8/IN 40/IN26/P5.0
SLSCO21/OUT41/OUT9/IN 41/IN27/P5.1
SLSCO22/ OUT42/OUT10/IN42/IN28/P5.2
SLSCO24/OUT44/OUT12/SLSI2A/IN44/IN29/P5.4
SLSCO 23 /OUT 43/ OUT 11/ IN43 /P5.3
M RST2 A/ OUT 45/ OUT 13/IN 45/ IN30 /P5.5
M TS R2 A/ OUT 46/OUT14 /IN 46/ IN31 /P5.6
SCLK2 /OUT 47 /OUT 15/ IN47 /P5.7
TCLK0/OUT95/P5.15
RV ALID0 B /OUT 90 /P5.9
RREADY0B/OUT91/P5.10
RCLK0B/OUT92/P5.11
TDATA0/SLSO07/OUT93/P5.12
TVALID0B/SLSO16/P5.13
TREADY0B/OUT94/P5.14
RDATA0B/OUT89/P5 .8
P6.1 /IN1 5/OUT 5/ OUT 81/ FCL P0 A
P6.0 /IN1 4/OUT 4/ OUT 80/ FCL N0
P6.3 /IN2 5/OUT 7/ OUT 83/ SO P0A
P6.2 /IN2 4/OUT 6/ OUT 82/ SO N0
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN8
AN7
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
TRST
P1.1/IN17/OUT17/OUT73
TDI/BRKIN/BRKOUT
TDO/DAP2/BRKIN/BRKOUT
TMS/DAP1
T C K/ D A P0
ESR1
PORST
V
SS
TESTMODE
XTAL1
XTAL2
V
DD
V
DDP
V
SS
V
DD
V
DD(SB)
TC1782
/
TC1182
V
DD
V
DDP
V
SS
V
DDMF
V
SSMF
V
DDAF
V
SS
V
FAREF
V
FAGND
V
DDM
V
SSM
V
AREF0
V
AGND0
V
DD
V
DDP
V
SS
V
DD
V
DDP
V
SS
V
SS
V
DD
V
DDP
V
SS
V
DDOSC
V
DDOSC3
V
SSOSC
V
DDFL3
V
DDP
V
SS
V
DD
V
DDP
V
SS
V
DD(SB)
V
DDP
V
SS
SAK_TC1782-256F133HR
V
DDP
V
DDP
ESR0
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 4 V 1.1, 2011-06
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package)
Pin Symbol Ctrl. Type Function
Port 0
145 P0.0 I/O0 A1/
PU Port 0 General Purpose I/O Line 0
IN0 I GPTA0 Input 0
IN0 I LTCA2 Input 0
HWCFG0 I Hardware Configuration Input 0
OUT0 O1 GPTA0 Output 0
OUT56 O2 GPTA0 Output 56
OUT0 O3 LTCA2 Output 0
146 P0.1 I/O0 A1/
PU Port 0 General Purpose I/O Line 1
IN1 I GPTA0 Input 1
IN1 I LTCA2 Input 1
SDI1 I MSC0 Serial Data Input 1
HWCFG1 I Hardware Configuration Input 1
OUT1 O1 GPTA0 Output 1
OUT57 O2 GPTA0 Output 57
OUT1 O3 LTCA2 Output 1
147 P0.2 I/O0 A1/
PU Port 0 General Purpose I/O Line 2
IN2 I GPTA0 Input 2
IN2 I LTCA2 Input 2
HWCFG2 I Hardware Configuration Input 2
OUT2 O1 GPTA0 Output 2
OUT58 O2 GPTA0 Output 58
OUT2 O3 LTCA2 Output 2
148 P0.3 I/O0 A1+/
PU Port 0 General Purpose I/O Line 3
IN3 I GPTA0 Input 3
IN3 I LTCA2 Input 3
HWCFG3 I Hardware Configuration Input 3
OUT3 O1 GPTA0 Output 3
OUT59 O2 GPTA0 Output 59
OUT3 O3 LTCA2 Output 3
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 5 V 1.1, 2011-06
166 P0.4 I/O0 A1/
PU Port 0 General Purpose I/O Line 4
IN4 I GPTA0 Input 4
IN4 I LTCA2 Input 4
HWCFG4 I Hardware Configuration Input 4
OUT4 O1 GPTA0 Output 4
OUT60 O2 GPTA0 Output 60
OUT4 O3 LTCA2 Output 4
167 P0.5 I/O0 A1/
PU Port 0 General Purpose I/O Line 5
IN5 I GPTA0 Input 5
IN5 I LTCA2 Input 5
HWCFG5 I Hardware Configuration Input 5
OUT5 O1 GPTA0 Output 5
OUT61 O2 GPTA0 Output 61
OUT5 O3 LTCA2 Output 5
173 P0.6 I/O0 A1/
PU Port 0 General Purpose I/O Line 6
IN6 I GPTA0 Input 6
IN6 I LTCA2 Input 6
HWCFG6 I Hardware Configuration Input 6
REQ2 I External Request Input 2
OUT6 O1 GPTA0 Output 6
OUT62 O2 GPTA0 Output 62
OUT6 O3 LTCA2 Output 6
174 P0.7 I/O0 A1/
PU Port 0 General Purpose I/O Line 7
IN7 I GPTA0 Input 7
IN7 I LTCA2 Input 7
HWCFG7 I Hardware Configuration Input 7
REQ3 I External Request Input 3
OUT7 O1 GPTA0 Output 7
OUT63 O2 GPTA0 Output 63
OUT7 O3 LTCA2 Output 7
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 6 V 1.1, 2011-06
149 P0.8 I/O0 A1/
PU Port 0 General Purpose I/O Line 8
IN8 I GPTA0 Input 8
IN8 I LTCA2 Input 8
RXDA0 I E-Ray Channel A Receive Data Input 0 1)
OUT8 O1 GPTA0 Output 8
OUT64 O2 GPTA0 Output 64
OUT8 O3 LTCA2 Output 8
150 P0.9 I/O0 A1/
PU Port 0 General Purpose I/O Line 9
IN9 I GPTA0 Input 9
IN9 I LTCA2 Input 9
RXDB0 I E-Ray Channel B Receive Data Input 0 1)
OUT9 O1 GPTA0 Output 9
OUT65 O2 GPTA0 Output 65
OUT9 O3 LTCA2 Output 9
151 P0.10 I/O0 A2/
PU Port 0 General Purpose I/O Line 10
IN10 I GPTA0 Input 10
OUT10 O1 GPTA0 Output 10
TXDA0 O2 E-Ray Channel A transmit Data Output 1)
OUT10 O3 LTCA2 Output 10
152 P0.11 I/O0 A2/
PU Port 0 General Purpose I/O Line 11
IN11 I GPTA0 Input 11
OUT11 O1 GPTA0 Output 11
TXDB0 O2 E-Ray Channel B transmit Data Output 1)
OUT11 O3 LTCA2 Output 11
168 P0.12 I/O0 A2/
PU Port 0 General Purpose I/O Line 12
IN12 I GPTA0 Input 12
OUT12 O1 GPTA0 Output 12
TXENA O2 E-Ray Channel A transmit Data Output enable
1)
OUT12 O3 LTCA2 Output 12
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 7 V 1.1, 2011-06
169 P0.13 I/O0 A2/
PU Port 0 General Purpose I/O Line 13
IN13 I GPTA0 Input 13
OUT13 O1 GPTA0 Output 13
TXENB O2 E-Ray Channel B transmit Data Output enable
1)
OUT13 O3 LTCA2 Output 13
175 P0.14 I/O0 A1+/
PU Port 0 General Purpose I/O Line 14
IN14 I GPTA0 Input 14
REQ4 I External Request Input 4
OUT14 O1 GPTA0 Output 14
FCLP0C O2 MSC0 Clock Output Positive C
OUT14 O3 LTCA2 Output 14
176 P0.15 I/O0 A1+/
PU Port 0 General Purpose I/O Line 15
IN15 I GPTA0 Input 15
REQ5 I External Request Input 5
OUT15 O1 GPTA0 Output 15
SOP0C O2 MSC0 Serial Data Output Positive C
OUT15 O3 LTCA2 Output 15
Port 1
116 P1.0 I/O0 A2/
PU Port 1 General Purpose I/O Line 0
IN16 I GPTA0 Input 16
BRKIN IBreak Input
OUT16 O1 GPTA0 Output 16
OUT72 O2 GPTA0 Output 72
OUT16 O3 LTCA2 Output 16
BRKOUT OBreak Output (controlled by OCDS module)
119 P1.1 I/O0 A1/
PU Port 1 General Purpose I/O Line 1
IN17 I GPTA0 Input 17
OUT17 O1 GPTA0 Output 17
OUT73 O2 GPTA0 Output 73
OUT17 O3 LTCA2 Output 17
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 8 V 1.1, 2011-06
93 P1.2 I/O0 A1/
PU Port 1 General Purpose I/O Line 2
IN18 I GPTA0 Input 18
OUT18 O1 GPTA0 Output 18
OUT74 O2 GPTA0 Output 74
OUT18 O3 LTCA2 Output 18
98 P1.3 I/O0 A1/
PU Port 1 General Purpose I/O Line 3
IN19 I GPTA0 Input 19
IN19 I LTCA2 Input 19
OUT19 O1 GPTA0 Output 19
OUT75 O2 GPTA0 Output 75
OUT19 O3 LTCA2 Output 19
107 P1.4 I/O0 A1/
PU Port 1 General Purpose I/O Line 4
IN20 I GPTA0 Input 20
IN20 I LTCA2 Input 20
EMGSTOP I Emergen cy Stop Input
OUT20 O1 GPTA0 Output 20
OUT76 O2 GPTA0 Output 76
OUT20 O3 LTCA2 Output 20
108 P1.5 I/O0 A1/
PU Port 1 General Purpose I/O Line 35
IN21 I GPTA0 Input 21
IN21 I LTCA2 Input 21
OUT21 O1 GPTA0 Output 21
OUT77 O2 GPTA0 Output 77
OUT21 O3 LTCA2 Output 21
109 P1.6 I/O0 A1/
PU Port 1 General Purpose I/O Line 6
IN22 I GPTA0 Input 22
IN22 I LTCA2 Input 22
OUT22 O1 GPTA0 Output 22
OUT78 O2 GPTA0 Output 78
OUT22 O3 LTCA2 Output 22
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 9 V 1.1, 2011-06
110 P1.7 I/O0 A1/
PU Port 1 General Purpose I/O Line 7
IN23 I GPTA0 Input 23
IN23 I LTCA2 Input 23
OUT23 O1 GPTA0 Output 23
OUT79 O2 GPTA0 Output 79
OUT23 O3 LTCA2 Output 23
94 P1.8 I/O0 A1+/
PU Port 1 General Purpose I/O Line 8
IN24 I GPTA0 Input 24
IN48 I GPTA0 Input 48
MTSR1B I SSC1 Slave Receive Input B (Slave Mode)
OUT24 O1 GPTA0 Output 24
OUT48 O2 GPTA0 Output 48
MTSR1B O3 SSC1 Master Transmit Output B (Master Mode)
95 P1.9 I/O0 A1+/
PU Port 1 General Purpose I/O Line 9
IN25 I GPTA0 Input 25
IN49 I GPTA0 Input 49
MRST1B I SSC1 Master Receive Input B (Master Mode)
OUT25 O1 GPTA0 Output 25
OUT49 O2 GPTA0 Output 49
MRST1B O3 SSC1 Slave Transmit Output B (Slave Mode)
96 P1.10 I/O0 A1+/
PU Port 1 General Purpose I/O Line 10
IN26 I GPTA0 Input 26
IN50 I GPTA0 Input 50
OUT26 O1 GPTA0 Output 26
OUT50 O2 GPTA0 Output 50
SLSO17 O3 SSC1 Slave Select Ou tput 7
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 10 V 1.1, 2011-06
97 P1.11 I/O0 A1+/
PU Port 1 General Purpose I/O Line 11
IN27 I GPTA0 Input 27
IN51 I GPTA0 Input 51
SCLK1B I SSC1 Clock Input B
OUT27 O1 GPTA0 Output 27
OUT51 O2 GPTA0 Output 51
SCLK1B O3 SSC1 Clock Output B
73 P1.12 I/O0 A1/
PU Port 1 General Purpose I/O Line 12
IN16 I LTCA2 Input 16
AD0EMUX0 O1 ADC0 External Multiplexer Control Output 0
AD0EMUX0 O2 ADC0 External Multiplexer Control Output 0
OUT16 O3 LTCA2 Output 16
72 P1.13 I/O0 A1/
PU Port 1 General Purpose I/O Line 13
IN17 I LTCA2 Input 17
AD0EMUX1 O1 ADC0 External Multiplexer Control Output 1
AD0EMUX1 O2 ADC0 External Multiplexer Control Output 1
OUT17 O3 LTCA2 Output 17
71 P1.14 I/O0 A1/
PU Port 1 General Purpose I/O Line 14
IN18 I LTCA2 Input 18
AD0EMUX2 O1 ADC0 External Multiplexer Control Output 2
AD0EMUX2 O2 ADC0 External Multiplexer Control Output 2
OUT18 O3 LTCA2 Output 18
117 P1.15 I/O0 A2/
PU Port 1 General Purpose I/O Line 15
BRKIN IBreak Input
Reserved O1 -
Reserved O2 -
Reserved O3 -
BRKOUT OBreak Output (controlled by OCDS module)
Port 2
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 11 V 1.1, 2011-06
74 P2.0 I/O0 A2/
PU Port 2 General Purpose I/O Line 0
IN32 I GPTA0 Input 32
OUT32 O1 GPTA0 Output 32
TCLK0 O2 MLI0 Transmitter Clock Output 0
OUT28 O3 LTCA2 Output 28
75 P2.1 I/O0 A2/
PU Port 2 General Purpose I/O Line 1
IN33 I GPTA0 Input 33
TREADY0A I MLI0 Transmitter Ready Inp ut A
OUT33 O1 GPTA0 Output 33
SLSO03 O2 SSC0 Slave Select Ou tput Line 3
SLSO13 O3 SSC1 Slave Select Ou tput Line 3
76 P2.2 I/O0 A2/
PU Port 2 General Purpose I/O Line 2
IN34 I GPTA0 Input 34
OUT34 O1 GPTA0 Output 34
TVALID0 O2 MLI0 Transmitter Valid Output
OUT29 O3 LTCA2 Output 29
77 P2.3 I/O0 A2/
PU Port 2 General Purpose I/O Line 3
IN35 I GPTA0 Input 35
OUT35 O1 GPTA0 Output 35
TDATA0 O2 MLI0 Transmitter Data Output
OUT30 O3 LTCA2 Output 30
78 P2.4 I/O0 A2/
PU Port 2 General Purpose I/O Line 4
IN36 I GPTA0 Input 36
RCLK0A I MLI Receiver Clock Input A
OUT36 O1 GPTA0 Output 36
OUT36 O2 GPTA0 Output 36
OUT31 O3 LTCA2 Output 31
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 12 V 1.1, 2011-06
79 P2.5 I/O0 A2/
PU Port 2 General Purpose I/O Line 5
IN37 I GPTA0 Input 37
OUT37 O1 GPTA0 Output 37
RREADY0A O2 MLI0 Receiver Ready Output A
OUT110 O3 LTCA2 Output 110
80 P2.6 I/O0 A2/
PU Port 2 General Purpose I/O Line 6
IN38 I GPTA0 Input 38
RVALID0A I MLI Receiver Valid Input A
OUT38 O1 GPTA0 Output 38
OUT38 O2 GPTA0 Output 38
OUT111 O3 LTCA2 Output 111
81 P2.7 I/O0 A2/
PU Port 2 General Purpose I/O Line 7
IN39 I GPTA0 Input 39
RDATA0A I MLI Receiver Data Input A
OUT39 O1 GPTA0 Output 39
OUT39 O2 GPTA0 Output 39
Reserved O3 -
164 P2.8 I/O0 A2/
PU Port 2 General Purpose I/O Line 8
SLSO04 O1 SSC0 Slave Select Ou tput 4
SLSO14 O2 SSC1 Slave Select Ou tput 4
EN00 O3 MSC0 Enable Output 0
160 P2.9 I/O0 A2/
PU Port 2 General Purpose I/O Line 9
SLSO05 O1 SSC0 Slave Select Ou tput 5
SLSO15 O2 SSC1 Slave Select Ou tput 5
EN01 O3 MSC0 Enable Output 1
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 13 V 1.1, 2011-06
161 P2.10 I/O0 A1+/
PU Port 2 General Purpose I/O Line 10
MRST1A I SSC1 Master Receive Input A
IN10 I LTCA2 Input 10
MRST1A O1 SSC1 Slave Transmit Output
OUT0 O2 LTCA2 Output 0
Reserved O3 -
162 P2.11 I/O0 A1+/
PU Port 2 General Purpose I/O Line 11
SCLK1A I SSC1 Clock Input A
IN11 I LTCA2 Input 11
SCLK1A O1 SSC1 Clock Output A
OUT1 O2 LTCA2 Output 1
FCLP0B O3 MSC0 Clock Output Positive B
163 P2.12 I/O0 A1+/
PU Port 2 General Purpose I/O Line 12
MTSR1A I SSC1 Slave Receive Input A
IN12 I LTCA2 Input 12
MTSR1A O1 SSC1 Master Transmit Output A
OUT2 O2 LTCA2 Output 2
SOP0B O3 MSC0 Serial Data Output Positive B
165 P2.13 I/O0 A1/
PU Port 2 General Purpose I/O Line 13
SLSI11 I SSC1 Slave Select Input 1
SDI0 I MSC0 Serial Data Input 0
IN13 I LTCA2 Input 13
OUT3 O1 LTCA2 Output 3
Reserved O2 -
Reserved O3 -
Port 3
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 14 V 1.1, 2011-06
136 P3.0 I/O0 A1+/
PU Port 3 General Purpose I/O Line 0
RXD0A I ASC0 Receiver Input A (Async. & Sync. Mode)
RXD0A O1 ASC0 Output (Sync. Mode)
RXD0A O2 ASC0 Output (Sync. Mode)
OUT84 O3 GPTA0 Output 84
135 P3.1 I/O0 A1+/
PU Port 3 General Purpose I/O Line 1
TXD0 O1 ASC0 Output
TXD0 O2 ASC0 Output
OUT85 O3 GPTA0 Output 85
129 P3.2 I/O0 A1+/
PU Port 3 General Purpose I/O Line 2
SCLK0 I SSC0 Clock Input (Slave Mode)
SCLK0 O1 SSC0 Clock Output (Master Mode)
SCLK0 O2 SSC0 Clock Output (Master Mode)
OUT86 O3 GPTA0 Output 86
130 P3.3 I/O0 A1+/
PU Port 3 General Purpose I/O Line 3
MRST0 I SSC0 Master Receive Input (Master Mode)
MRST0 O1 SSC0 Slave Transmit Outpu t (Slave Mode)
MRST0 O2 SSC0 Slave Transmit Outpu t (Slave Mode)
OUT87 O3 GPTA0 Output 87
132 P3.4 I/O0 A2/
PU Port 3 General Purpose I/O Line 4
MTSR0 I SSC0 Slave Receive Inpu t (Slave Mode)
MTSR0 O1 SSC0 Master Transmit Output (Master Mode)
MTSR0 O2 SSC0 Master Transmit Output (Master Mode)
OUT88 O3 GPTA0 Output 88
126 P3.5 I/O0 A1+/
PU Port 3 General Purpose I/O Line 5
SLSO00 O1 SSC0 Slave Select Ou tput 0
SLSO10 O2 SSC1 Slave Select Ou tput 0
SLSOANDO0 O3 SSC0 AND SSC1 Slave Select Output 0
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 15 V 1.1, 2011-06
127 P3.6 I/O0 A1+/
PU Port 3 General Purpose I/O Line 6
SLSO01 O1 SSC0 Slave Select Ou tput 1
SLSO11 O2 SSC1 Slave Select Ou tput 1
SLSOANDO1 O3 SSC0 AND SSC1 Slave Select Output 1
131 P3.7 I/O0 A2/
PU Port 3 General Purpose I/O Line 7
SLSI01 I SSC0 Slave Select Input 1
SLSO02 O1 SSC0 Slave Select Ou tput 2
SLSO12 O2 SSC1 Slave Select Ou tput 2
OUT89 O3 GPTA0 Output 89
128 P3.8 I/O0 A2/
PU Port 3 General Purpose I/O Line 8
SLSO06 O1 SSC0 Slave Select Ou tput 6
TXD1 O2 ASC1 Transmit Output
OUT90 O3 GPTA0 Output 90
138 P3.9 I/O0 A1/
PU Port 3 General Purpose I/O Line 9
RXD1A I ASC1 Receiver Input A
RXD1A O1 ASC1 Receiver Output A (Synchronous Mode)
RXD1A O2 ASC1 Receiver Output A (Synchronous Mode)
OUT91 O3 GPTA0 Output 91
137 P3.10 I/O0 A1/
PU Port 3 General Purpose I/O Line 10
REQ0 I External Request Input 0
Reserved O1 -
Reserved O2 -
OUT92 O3 GPTA0 Output 92
144 P3.11 I/O0 A1/
PU Port 3 General Purpose I/O Line 11
REQ1 I External Request Input 1
Reserved O1 -
Reserved O2 -
OUT93 O3 GPTA0 Output 93
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 16 V 1.1, 2011-06
143 P3.12 I/O0 A1/
PU Port 3 General Purpose I/O Line 12
RXDCAN0 I CAN Node 0 Receiver Input
RXD0B I ASC0 Receiver Input B
RXD0B O1 ASC0 Receiver Output B (Synchronous Mode)
RXD0B O2 ASC0 Receiver Output B (Synchronous Mode)
OUT94 O3 GPTA0 Output 94
142 P3.13 I/O0 A2/
PU Port 3 General Purpose I/O Line 13
TXDCAN0 O1 CAN Node 0 Transmitte r Output
TXD0 O2 ASC0 Transmit Output
OUT95 O3 GPTA0 Output 95
134 P3.14 I/O0 A1/
PU Port 3 General Purpose I/O Line 14
RXDCAN1 I CAN Node 1 Receiver Input
RXD1B I ASC1 Receiver Input B
SDI2 I MSC0 Serial Data Input 2
RXD1B O1 ASC1 Receiver Output B (Synchronous Mode)
RXD1B O2 ASC1 Receiver Output B (Synchronous Mode)
OUT96 O3 GPTA0 Output 96
133 P3.15 I/O0 A2/
PU Port 3 General Purpose I/O Line 15
TXDCAN1 O1 CAN Node 1 Transmitte r Output
TXD1 O2 ASC1 Transmit Output
OUT97 O3 GPTA0 Output 97
Port 4
86 P4.0 I/O0 A1+/
PU Port 4 General Purpose I/O Line 0
IN28 I GPTA0 Input 28
IN52 I GPTA0 Input 52
RXDCAN2 I CAN Node 2 Receiver Input
OUT28 O1 GPTA0 Output 28
OUT52 O2 GPTA0 Output 52
Reserved O3 -
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 17 V 1.1, 2011-06
87 P4.1 I/O0 A1+/
PU Port 4 General Purpose I/O Line 1
IN29 I GPTA0 Input 29
IN53 I GPTA0 Input 53
OUT29 O1 GPTA0 Output 29
OUT53 O2 GPTA0 Output 53
TXDCAN2 O3 CAN Node 2 Transmitte r Output
88 P4.2 I/O0 A2/
PU Port 4 General Purpose I/O Line 2
IN30 I GPTA0 Input 30
IN54 I GPTA0 Input 54
OUT30 O1 GPTA0 Output 30
OUT54 O2 GPTA0 Output 54
EXTCLK1 O3 External Clock 1 Outpu t
90 P4.3 I/O0 A2/
PU Port 4 General Purpose I/O Line 3
IN31 I GPTA0 Input 31
IN55 I GPTA0 Input 55
OUT31 O1 GPTA0 Output 31
OUT55 O2 GPTA0 Output 55
EXTCLK0 O3 External Clock 0 Outpu t
Port 5
1 P5.0 I/O0 A1+/
PU Port 5 General Purpose I/O Line 0
IN40 I GPTA0 Input 40
IN26 I LTCA2 Input 26
OUT40 O1 GPTA0 Output 40
OUT8 O2 LTCA2 Output 8
SLSO20 O3 SSC2 Slave Select Ou tput 0
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 18 V 1.1, 2011-06
2 P5.1 I/O0 A1+/
PU Port 5 General Purpose I/O Line 1
IN41 I GPTA0 Input 41
IN27 I LTCA2 Input 27
OUT41 O1 GPTA0 Output 41
OUT9 O2 LTCA2 Output 9
SLSO21 O3 SSC2 Slave Select Ou tput 1
3 P5.2 I/O0 A1+/
PU Port 5 General Purpose I/O Line 2
IN42 I GPTA0 Input 42
IN28 I LTCA2 Input 28
OUT42 O1 GPTA0 Output 42
OUT10 O2 LTCA2 Output 10
SLSO22 O3 SSC2 Slave Select Ou tput 2
4 P5.3 I/O0 A1+/
PU Port 5 General Purpose I/O Line 3
IN43 I GPTA0 Input 43
OUT43 O1 GPTA0 Output 43
OUT11 O2 LTCA2 Output 11
SLSO23 O3 SSC2 Slave Select Ou tput 3
5 P5.4 I/O0 A1+/
PU Port 5 General Purpose I/O Line 4
IN44 I GPTA0 Input 44
IN29 I LTCA2 Input 29
SLSI2A I SSC2 Slave Select Input A
OUT44 O1 GPTA0 Output 44
OUT12 O2 LTCA2 Output 12
SLSO24 O3 SSC2 Slave Select Ou tput 4
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 19 V 1.1, 2011-06
6 P5.5 I/O0 A1+/
PU Port 5 General Purpose I/O Line 5
IN45 I GPTA0 Input 45
IN30 I LTCA2 Input 30
MRST2A I SSC2 Master Receive Input (Master Mode)
OUT45 O1 GPTA0 Output 45
OUT13 O2 LTCA2 Output 13
MRST2 O3 SSC2 Master Transmit Input (Slave Mode)
7 P5.6 I/O0 A1+/
PU Port 5 General Purpose I/O Line 6
IN46 I GPTA0 Input 46
IN31 I LTCA2 Input 31
MTSR2A I SSC2 Slave Receive Input (Slave Mode)
OUT46 O1 GPTA0 Output 46
OUT14 O2 LTCA2 Output 14
MTSR2 O3 SSC2 Master Transmit Output (Master Mode)
8 P5.7 I/O0 A1+/
PU Port 5 General Purpose I/O Line 7
IN47 I GPTA0 Input 47
SCLK2A I SSC2 Clock Input (Slave Mode)
OUT47 O1 GPTA0 Output 47
OUT15 O2 LTCA2 Output 15
SCLK2 O3 SSC2 Clock Output (Master Mode)
13 P5.8 I/O0 A2/
PU Port 5 General Purpose I/O Line 8
RDATA0B I MLI0 Receiver Data Input B
Reserved O1 -
TXDA1 O2 E-Ray Channel A transmit Data Output 1)
OUT89 O3 LTCA2 Output 89
14 P5.9 I/O0 A2/
PU Port 5 General Purpose I/O Line 9
RVALID0B I MLI0 Receiver Data Valid Input B
Reserved O1 -
TXDB1 O2 E-Ray Channel B transmit Data Output 1)
OUT90 O3 LTCA2 Output 90
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 20 V 1.1, 2011-06
15 P5.10 I/O0 A2/
PU Port 5 General Purpose I/O Line 10
RREADY0B O1 MLI0 Receiver Ready Input B
TXENA O2 E-Ray Channel A transmit Data Output enable
1)
OUT91 O3 LTCA2 Output 91
16 P5.11 I/O0 A2/
PU Port 5 General Purpose I/O Line 11
RCLK0B I MLI0 Receiver Clock Input B
Reserved O1 -
TXENB O2 E-Ray Channel B transmit Data Output enable
1)
OUT92 O3 LTCA2 Output 92
17 P5.12 I/O0 A1+/
PU Port 5 General Purpose I/O Line 12
TDATA0 O1 MLI0 Transmitter Data Output
SLSO07 O2 SSC0 Slave Select Ou tput 7
OUT93 O3 LTCA2 Output 93
18 P5.13 I/O0 A1+/
PU Port 5 General Purpose I/O Line 13
TVALID0B O1 MLI0 Transmitter Valid Input B
SLSO16 O2 SSC1 Slave Select Ou tput 6
Reserved O3 -
19 P5.14 I/O0 A1+/
PU Port 5 General Purpose I/O Line 14
TREADY0B I MLI0 Transmitter Ready Inp ut B
RXDA1 I E-Ray Channel A Receive Data Input 1 1)
Reserved O1 -
Reserved O2 -
OUT94 O3 LTCA2 Output 94
9 P5.15 I/O0 A1+/
PU Port 5 General Purpose I/O Line 15
RXDB1 I E-Ray Channel B Receive Data Input 1 1)
TCLK0 O1 MLI0 Transmitter Clock Output
Reserved O2 -
OUT95 O3 LTCA2 Output 95
Port 6
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 21 V 1.1, 2011-06
156 P6.0 I/O0 A1/
F/
PU
Port 6 General Purpose I/O Line 0
IN14 I LTCA2 Input 14
FCLN0 O1 MSC0 Clock Output Negative
OUT80 O2 GPTA0 Output 80
OUT4 O3 LTCA2 Output 4
157 P6.1 I/O0 A1/
F/
PU
Port 6 General Purpose I/O Line 1
IN15 I LTCA2 Input 15
FCLP0A O1 MSC0 Clock Output Positive A
OUT81 O2 GPTA0 Output 81
OUT5 O3 LTCA2 Output 5
158 P6.2 I/O0 A1/
F/
PU
Port 6 General Purpose I/O Line 2
IN24 I LTCA2 Input 24
SON0 O1 MSC0 Serial Data Output Negative
OUT82 O2 GPTA0 Output 82
OUT6 O3 LTCA2 Output 6
159 P6.3 I/O0 A1/
F/
PU
Port 6 General Purpose I/O Line 3
IN25 I LTCA2 Input 25
SOP0A O1 MSC0 Serial Data Output Positive A
OUT83 O2 GPTA0 Output 83
OUT7 O3 LTCA2 Output 7
Analog Input Port
67 AN0 I D ADC0 Analog Input Channel 0
66 AN1 I D ADC0 Analog Input Channel 1
65 AN2 I D ADC0 Analog Input Channel 2
64 AN3 I D ADC0 Analog Input Channel 3
63 AN4 I D ADC0 Analog Input Channel 4
62 AN5 I D ADC0 Analog Input Channel 5
61 AN6 I D ADC0 Analog Input Channel 6
36 AN7 I D ADC0 Analog Input Channel 7
60 AN8 I D ADC0 Analog Input Channel 8
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 22 V 1.1, 2011-06
59 AN9 I D ADC0 Analog Input Channel 9
58 AN10 I D ADC0 Analog Input Channel 10
57 AN11 I D ADC0 Analog Input Channel 11
56 AN12 I D ADC0 Analog Input Channel 12
55 AN13 I D ADC0 Analog Input Channel 13
50 AN14 I D ADC0 Analog Input Channel 14
49 AN15 I D ADC0 Analog Input Channel 15
48 AN16 I D ADC1 Analog Input Channel 16
47 AN17 I D ADC1 Analog Input Channel 17
46 AN18 I D ADC1 Analog Input Channel 18
45 AN19 I D ADC1 Analog Input Channel 19
44 AN20 I D ADC1 Analog Input Channel 20
43 AN21 I D ADC1 Analog Input Channel 21
42 AN22 I D ADC1 Analog Input Channel 22
41 AN23 I D ADC1 Analog Input Channel 23
40 AN24 I D ADC1 Analog Input Channel 24
39 AN25 I D ADC1 Analog Input Channel 25
38 AN26 I D ADC1 Analog Input Channel 26
37 AN27 I D ADC1 Analog Input Channel 27
35 AN28 I D ADC1 / FADC Analog Input Channel 28
34 AN29 I D ADC1 / FADC Analog Input Channel 29
33 AN30 I D ADC1 / FADC Analog Input Channel 30
32 AN31 I D ADC1 / FADC Analog Input Channel 31
31 AN32 I D FADC Analog Input P Channel 0
30 AN33 I D FADC Analog Input N Channel 0
29 AN34 I D FADC Analog Input P Channel 1
28 AN35 I D FADC Analog Input N Channel 1
54 VDDM --ADC Analog Part Power Supply (3.3V - 5V)
53 VSSM --ADC Analog Part Ground
52 VAREF0 --ADC0 and ADC1 Reference Voltage
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 23 V 1.1, 2011-06
51 VAGND0 --ADC Reference Ground
24 VDDMF --FADC Analog Part Power Supply (3.3V)
23 VDDAF --FADC Analog Part Logic Power Supply (1.3V)
25 VSSMF --FADC Analog Part Gro und
VSSAF --FADC Analog Part Gro und
26 VFAREF --FADC Reference Voltage
27 VFAGND --FADC Reference Ground
10,
212),
68,
84,
91,
99,
123,
153,
170
2)
VDD --Digital Core Power Supply (1.3V)
11,
20,
69,
83,
89,
100,
124,
139,
154,
171
VDDP --Port Power Supply (3.3V)
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 24 V 1.1, 2011-06
12,
22,
70,
82,
85,
92,
101,
125,
140,
155,
172
VSS --Digital Ground
105 VDDOSC --Main Oscillator and PLL Power Supply (1.3V)
106 VDDOSC3 --Main Oscillator Power Supply (3.3V)
104 VSSOSC --Main Oscillator and PLL Ground
141 VDDFL3 --Power Supply for Flash (3.3V)
102 XTAL1 I Main Oscillator Input
103 XTAL2 O Main Oscillator Output
111 TDI I A2/
PU JTAG Serial Data Input
BRKIN I OCDS Break Input Line
BRKOUT O OCDS Break Output Line
112 TMS I A2/
PD JTAG State Machine Control Input
DAP1 I/O Device Access Port Line 1
113 TDO I/O A2/
PU JTAG Serial Data Output
DAP2 I/O Device Access Port Line 2
BRKIN I OCDS Break Input Line
BRKOUT O OCDS Break Output Line
114 TRST I I /
PD JTAG Reset Input
115 TCK I A1/
PD JTAG Clock Input
DAP0 I Device Access Port Line 0
118 TESTMODE I I /
PU Test Mode Select Input
120 ESR1 I/O A2/
PD External System Request Reset Input 1
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
PinningTC1782 / TC1182 Pin Configuration
Data Sheet 25 V 1.1, 2011-06
Legend for Table 2
Column “Ctrl.”:
I = Input (for GPIO port lines with IOCR bit field selection PCx = 0XXXB)
O = Output
O0 = Output with IOCR bi t field selection PCx = 1X00B
O1 = Output with IOCR bi t field selection PCx = 1X01B (ALT1)
O2 = Output with IOCR bi t field selection PCx = 1X10B(ALT2)
O3 = Output with IOCR bi t field selection PCx = 1X11(ALT3)
Column “Type”:
A1 = Pad class A1 (LVTTL)
A1+ = Pad class A1+ (LVTTL)
A2 = Pad class A2 (LVTTL)
F = Pad class F (LVDS/CMOS)
D = Pad class D (ADC)
I = Pad class I (LVTTL)
PU = with pull-up device connected during reset (PORST = 0)
PD = with pull-down device connected during reset (PORST = 0)
TR = tri-state during reset (PORST = 0)
121 PORST I I /
PD Power On Reset Input
122 ESR0 I/O A2 External System Request Reset Input 0
Default configuration during and after reset is
open-drain driver. The driver drives low during
power-on reset.
1) Only available for SAK-TC1782F-320F180HR and SAK-TC1782F-320F180HL.
2) For the emulation device (ED), this pin is bonded to VDDSB (ED Stand By RAM supply). In the production
devide device, this pin is bonded to a VDD pad.
Table 2 Pin Definitions and Functions (PG-LQFP-176-10 Package) (cont’d)
Pin Symbol Ctrl. Type Function
TC1782 / TC1182
Identification Registers
Data Sheet 1 V 1.1, 2011-06
4 Identification Registers
The Identification Registers uniquely identify the whole device.
Table 3 SAK-TC1782F-320F180HR Identification Registers
Short Name Value Address Stepping
CBS_JDPID 0000 6350HF000 0408HBA
CBS_JTAGID 1018 E083HF000 0464HBA
SCU_CHIPID 8500 9310HF000 0640HBA
SCU_MANID 0000 1820HF000 0644HBA
SCU_RTID 0000 0000HF000 0648HBA
Table 4 SAK-TC1782F-320F180H L Identification Registers
Short Name Value Address Stepping
CBS_JDPID 0000 6350HF000 0408HBA
CBS_JTAGID 1018 E083HF000 0464HBA
SCU_CHIPID 0500 9310HF000 0640HBA
SCU_MANID 0000 1820HF000 0644HBA
SCU_RTID 0000 0000HF000 0648HBA
Table 5 SAK-TC1782F-256F133HR Identification Registers
Short Name Value Address Stepping
CBS_JDPID 0000 6350HF000 0408HBA
CBS_JTAGID 1018 E083HF000 0464HBA
SCU_CHIPID 9400 9310HF000 0640HBA
SCU_MANID 0000 1820HF000 0644HBA
SCU_RTID 0000 0000HF000 0648HBA
Table 6 SAK-TC1782F-256F133H L Identification Registers
Short Name Value Address Stepping
CBS_JDPID 0000 6350HF000 0408HBA
CBS_JTAGID 1018 E083HF000 0464HBA
SCU_CHIPID 1400 9310HF000 0640HBA
TC1782 / TC1182
Identification Registers
Data Sheet 2 V 1.1, 2011-06
SCU_MANID 0000 1820HF000 0644HBA
SCU_RTID 0000 0000HF000 0648HBA
Table 7 SAK-TC1782N-320F180HR Identification Registers
Short Name Value Address Stepping
CBS_JDPID 0000 6350HF000 0408HBA
CBS_JTAGID 1018 E083HF000 0464HBA
SCU_CHIPID 8500 9410HF000 0640HBA
SCU_MANID 0000 1820HF000 0644HBA
SCU_RTID 0000 0000HF000 0648HBA
Table 8 SAK-TC1782N-320F180HL Identification Registers
Short Name Value Address Stepping
CBS_JDPID 0000 6350HF000 0408HBA
CBS_JTAGID 1018 E083HF000 0464HBA
SCU_CHIPID 0500 9410HF000 0640HBA
SCU_MANID 0000 1820HF000 0644HBA
SCU_RTID 0000 0000HF000 0648HBA
Table 9 SAK-TC1782N-256F133HR Identification Registers
Short Name Value Address Stepping
CBS_JDPID 0000 6350HF000 0408HBA
CBS_JTAGID 1018 E083HF000 0464HBA
SCU_CHIPID 9400 9410HF000 0640HBA
SCU_MANID 0000 1820HF000 0644HBA
SCU_RTID 0000 0000HF000 0648HBA
Table 6 SAK-TC1782F-256F133H L Identification Registers (cont’d)
Short Name Value Address Stepping
TC1782 / TC1182
Identification Registers
Data Sheet 3 V 1.1, 2011-06
Table 10 SAK-TC1782N-256F133HL Identification Registers
Short Name Value Address Stepping
CBS_JDPID 0000 6350HF000 0408HBA
CBS_JTAGID 1018 E083HF000 0464HBA
SCU_CHIPID 1400 9410HF000 0640HBA
SCU_MANID 0000 1820HF000 0644HBA
SCU_RTID 0000 0000HF000 0648HBA
Table 11 SAK-TC1182N-320F180HR Iden tification Registers
Short Name Value Address Stepping
CBS_JDPID 0000 6350HF000 0408HBA
CBS_JTAGID 1018 E083HF000 0464HBA
SCU_CHIPID 8500 B210HF000 0640HBA
SCU_MANID 0000 1820HF000 0644HBA
SCU_RTID 0000 0000HF000 0648HBA
Table 12 SAK-TC1182N-320F180HL Identification Registers
Short Name Value Address Stepping
CBS_JDPID 0000 6350HF000 0408HBA
CBS_JTAGID 1018 E083HF000 0464HBA
SCU_CHIPID 0500 B210HF000 0640HBA
SCU_MANID 0000 1820HF000 0644HBA
SCU_RTID 0000 0000HF000 0648HBA
Table 13 SAK-TC1182N-256F133HR Iden tification Registers
Short Name Value Address Stepping
CBS_JDPID 0000 6350HF000 0408HBA
CBS_JTAGID 1018 E083HF000 0464HBA
SCU_CHIPID 9400 B210HF000 0640HBA
SCU_MANID 0000 1820HF000 0644HBA
SCU_RTID 0000 0000HF000 0648HBA
TC1782 / TC1182
Identification Registers
Data Sheet 4 V 1.1, 2011-06
Table 14 SAK-TC1182N-256F133HL Identification Registers
Short Name Value Address Stepping
CBS_JDPID 0000 6350HF000 0408HBA
CBS_JTAGID 1018 E083HF000 0464HBA
SCU_CHIPID 1400 B210HF000 0640HBA
SCU_MANID 0000 1820HF000 0644HBA
SCU_RTID 0000 0000HF000 0648HBA
TC1782 / TC1182
Electrical ParametersGeneral Parameters
Data Sheet 1 V 1.1, 2011-06
5 Electrical Parameters
This specification provides all electrical parameters of the TC1782 / TC1182.
5.1 General Parameters
5.1.1 Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the TC1782 /
TC1182 and partly its requirements on the system. To aid interpreting the parameters
easily when evaluating them for a design, they are marked with an two-letter
abbreviation in column “Symbol”:
CC
Such parameters indicate Controller Characteristics which are a distinctive feature of
the TC1782 / TC1182 and must be regarded for a system design.
SR
Such parameters indicate System Requirements which must provided by the
microcontroller system in which the TC1782 / TC1182 designed in.
TC1782 / TC1182
Electrical ParametersGeneral Parameters
Data Sheet 2 V 1.1, 2011-06
5.1.2 Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in the Section 5.2.1.
Table 15 Pad Driver and Pad Classes Overv ie w
Class Power
Supply Type Sub Class Speed
Grade Load Leakage
150oCTermination
A3.3 V LVTTL
I/O,
LVTTL
outputs
A1
(e.g. GPIO) 6 MHz 100 pF 500 nA No
A1+
(e.g. serial
I/Os)
25
MHz 50 pF 1 μASeries
termination
recommended
A2
(e.g. serial
I/Os)
40
MHz 50 pF 3 μASeries
termination
recommended
F3.3 V LVDS 50
MHz –– Parallel
termination,
100 Ω± 10% 1)
1) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or
properly terminated with the differential parallel termination of 100 Ω±10%.
CMOS 6 MHz 50 pF
DE5V ADC
I3.3 V LVTTL
(input
only)
––
TC1782 / TC1182
Electrical ParametersGeneral Parameters
Data Sheet 3 V 1.1, 2011-06
5.1.3 Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 16 Absolute Maximum Rating Parameters
Parameter Symbol Values Unit Note /
Test Con
dition
Min. Typ. Max.
Storage temperature TST SR -65 150 °C–
Voltage at 1.3 V power supply
pins with respect to VSS
VDD SR 2.0 V
Voltage at 3.3 V power supply
pins with respect to VSS
VDDP
SR ––4.3 V
Voltage at 5 V power supply
pins with respect to VSS
VDDM SR 7.0 V
Voltage on any Class A input
pin and dedicated input pins
with respect to VSS
VIN SR -0.5 VDDP + 0.5
or max. 4.3 V Whatever
is lower
Voltage on any Class D
analog input pin with respect
to VAGND0
VAIN
VAREF0 SR
-0.5 7.0 V
Voltage on any shared Class
D analog input pin with
respect to VSSAF, if the FADC
is switched through to the pin.
VAINF SR -0.5 7.0 V
Input current on any pin
during overload condition IIN -10 +10 mA
Absolute maximum sum of all
input circuit currents for one
port group during overload
condition1)
1) The port groups are defined in Table 21.
IIN -25 +25 mA
Absolute maximum sum of all
input circuit currents during
overload condition
ΣIIN ––|200| mA
TC1782 / TC1182
Electrical ParametersGeneral Parameters
Data Sheet 4 V 1.1, 2011-06
5.1.4 Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 17 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
full operation life-time (24000 h) is not exceeded
Operating Co nditions are met for
pad supply levels
temperature
If a pin current is out of the Operating Conditions but within th e overload paramete rs,
then the parameters functionality of this pin as stated in the Operating Conditions can no
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.
Note: FADC input pins count as analog pin as they are overlayed with an ADC pins.
Table 17 Overload Parameters
Parameter Symbol Values Unit Note /
Test Con
dition
Min. Typ. Max.
Input current on any digital pin
during overload condition
except LVDS pins
IIN -5 +5 mA
Input current on LVDS pins IINLVDS -3 +3 mA
Absolute sum of all input
circuit currents for one port
group during overload
condition1)
1) The port groups are defined in Table 21.
IING -20 +20 mA
Input current on analog pins IINANA -3 +3 mA
Absolute sum of all analog
input currents for analog
inputs of a single ADC during
overload condition
IINSAS -15 +15 mA
Absolute sum of all input
circuit currents during
overload condition
ΣIINS -100 100 mA
TC1782 / TC1182
Electrical ParametersGeneral Parameters
Data Sheet 5 V 1.1, 2011-06
Table 18 PN-Junction Cha racterisitics for positive Overload
Pad Type IIN =3mA I
IN =5mA
A1 / A1+ / F UIN =VDDP +0.6V UIN =VDDP +0.7V
A2 UIN =VDDP +0.5V UIN =VDDP +0.6V
LVDS UIN =VDDP +0.7V -
DUIN =VDDP +0.6V -
Table 19 PN-Junction Characterisitics for negative Ov erload
Pad Type IIN =-3mA I
IN =-5mA
A1 / A1+ / F UIN =VSS -0.6V UIN =VSS -0.7V
A2 UIN =VSS -0.5V UIN =VSS -0.6V
LVDS UIN =VSS -0.7V -
DUIN =VSS -0.6V -
TC1782 / TC1182
Electrical ParametersGeneral Parameters
Data Sheet 6 V 1.1, 2011-06
5.1.5 Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the TC1782 / TC1182.
Digital supply voltages applied to the TC1782 / TC1182 must be static regulated voltages
which allow a typical voltage swing of ± 5 %.
All parameters specified in the following tables refer to these operating conditions
(Table 20), unless otherwise noticed in the Note / Test Condition column.
The Extended Range Operating Conditions did not increase area of validity of the
paramete rs defined in table 8 and later.
Table 20 Operating Cond itions Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Overload coupling factor
for analog inputs, negative KOVAN
CC −−0.0001 IOV0mA;
IOV-1 mA;
analog
pad= 5.0 V
Overload coupling factor
for analog inputs, positive KOVAP
CC −−0.0000
1IOV3mA;
IOV0mA;
analog
pad= 5.0 V
TC1782 / TC1182
Electrical ParametersGeneral Parameters
Data Sheet 7 V 1.1, 2011-06
CPU Frequency fCPU SR −−133 MHz SAK-TC1782F-
256F133HR / S
AK-TC1782F-
256F133HL / S
AK-TC1782N-
256F133HR / S
AK-TC1782N-
256F133HL / S
AK-TC1182N-
256F133HR / S
AK-TC1182N-
256F133HL
−−180 MHz SAK-TC1782F-
320F180HR / S
AK-TC1782F-
320F180HL / S
AK-TC1782N-
320F180HR / S
AK-TC1782N-
320F180HL / S
AK-TC1182N-
320F180HR / S
AK-TC1182N-
320F180HL
FPI bus frequency fFPI SR −−90 MHz
Table 20 Operating Cond itions Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersGeneral Parameters
Data Sheet 8 V 1.1, 2011-06
LMB frequency fLMB CC −−133 MHz SAK-TC1782F-
256F133HR / S
AK-TC1782F-
256F133HL / S
AK-TC1782N-
256F133HR / S
AK-TC1782N-
256F133HL / S
AK-TC1182N-
256F133HR / S
AK-TC1182N-
256F133HL
−−180 MHz SAK-TC1782F-
320F180HR / S
AK-TC1782F-
320F180HL / S
AK-TC1782N-
320F180HR / S
AK-TC1782N-
320F180HL / S
AK-TC1182N-
320F180HR / S
AK-TC1182N-
320F180HL
Table 20 Operating Cond itions Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersGeneral Parameters
Data Sheet 9 V 1.1, 2011-06
PCP Frequency fPCP SR −−133 MHz SAK-TC1782F-
256F133HR / S
AK-TC1782F-
256F133HL / S
AK-TC1782N-
256F133HR / S
AK-TC1782N-
256F133HL / S
AK-TC1182N-
256F133HR / S
AK-TC1182N-
256F133HL
−−180 MHz SAK-TC1782F-
320F180HR / S
AK-TC1782F-
320F180HL / S
AK-TC1782N-
320F180HR / S
AK-TC1782N-
320F180HL / S
AK-TC1182N-
320F180HR / S
AK-TC1182N-
320F180HL
Inactive device pin current IID SR -1 1 mA All power
supply
voltagesVDDx =
0
Short circuit current of
digital outputs1) ISC SR -5 5mA
Absolute sum of short
circuit currents of the
device
ΣISC_D
CC −−100 mA
Absolute sum of short
circuit currents per pin
group
ΣISC_PG
CC −−20 mA
Ambient Temperature TA SR -40 125 °C
Table 20 Operating Cond itions Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersGeneral Parameters
Data Sheet 10 V 1.1, 2011-06
Extended Range Op era t in g Conditions
The following extended operating conditions are defined:
Junction temperature TJ SR -40 150 °C
Core Supply Voltage VDD SR 1.235 1.3 1.3652) V
Flash supply voltage 3.3V VDDFL3
SR 3.13 3.3 3.474) V
ADC analog supply
voltage VDDM
SR 3.13 3.3 5.53) V
Oscillator core supply
voltage VDDOSC
SR 1.235 1.3 1.3652) V
Oscillator 3.3V supply
voltage VDDOSC3
SR 3.05 3.3 3.474) V
Digital supply voltage for
IO pads VDDP SR 3.13 3.3 3.47 4) V
VDDP voltage to ensure
defined pad states5) VDDPPA
CC 0.65 −−V
Digital ground voltage VSS SR 0 −−V
Analog ground voltage for
VDDM
VSSM SR -0.1 0 0.1 V
Analog core supply VDDAF
SR 1.235 1.3 1.3652) V
FADC / ADC analog
supply voltage VDDMF
SR 3.13 3.3 3.474) V
Analog ground voltage for
VDDMF
VSSAF
SR -0.1 0 0.1 V
1) Applicable for digital outputs.
2) Voltage overshoot to 1.7V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
3) Voltage overshoot to 6.5V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
4) Voltage overshoot to 4.0V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h.
5) This parameter is valid under the assumption the PORST signal is constantly at low level during the power-
up/power-down of VDDP.
Table 20 Operating Cond itions Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersGeneral Parameters
Data Sheet 11 V 1.1, 2011-06
•1.3V+5%<VDD /VDDOSC /VDDAF <1.3V+7.5% (overvoltage condition):
limited to 10000 hour duration cumulative in lifetime, due to the reliability reduction
of the chip caused by the overvoltage stress.
1.3V + 7.5% < VDD /VDDOSC /VDDAF <1.3V+10% (overvoltage condition):
limited to 1 hour duration cumulative in lif etime, due to the reliability reduction of
the chip caused by the overvoltage stress.
VDDP /VDDOSC3 /VDDFL3 /VDDMF<3.3V±10%
–3.3V+5%<VDDP /VDDOSC3 /VDDFL3 /VDDMF<3.3V+10%
(overvoltage condition):
limited to 1 hour duration cumulative in lifet ime, due to the reliability reduction of
the chip caused by the overvoltage stress.
3.3V - 10% < VDDP /VDDOSC3 /VDDFL3 /VDDMF<3.3V5%
(undervoltage condition):
-reduces GPIO pads performance
Table 21 Pin Groups for Overload / Short-Circuit Current Sum Parameter
Group Pins
1 P5.[7 :2], P5.15
2 P5.[9:8]
3 P5.[11:10]
4 P5.[14:12]
5 P1.[14:12], P2.0
6 P2.[4:1]
7 P2.[7:5]
8 P4.[2:0]
9P4.3
10 P1.2, P1.8
11 P1.[10:9]
12 P1.3, P1.11
13 P1.[7:4]
14 P1.[1:0], P1.15
15 P3.[8:5], P3.[3:2]
16 P3.[1:0], P3.4, P3.[10:9], P3.[15:14]
TC1782 / TC1182
Electrical ParametersGeneral Parameters
Data Sheet 12 V 1.1, 2011-06
17 P0.[1:0], P3.[13:11]
18 P0.[3:2], P0.[9:8]
19 P0.[11:10]
20 P6.[3:0]
21 P2.[13:8]
22 P0.[5:4], P0.[13:12]
23 P0.[7:6], P0.[15:14], P5.[1 :0]
Table 21 Pin Groups for Overload / Short-Circuit Current Sum Parameter
Group Pins
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 13 V 1.1, 2011-06
5.2 DC Parameters
5.2.1 Input/Output Pins
Table 22 Standard_Pads Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Pin capacitance (digital
inputs/outputs) CIO CC −−10 pF TA=2C;
f=1MHz
Pull-down current |IPDL|
CC −−150 μAVi0.6 x VDDP V
10 −−μAVi0.36 x
VDDP V
Pull-Up current |IPUH|
CC 10 −−μAVi0.6 x VDDP V
−−100 μAVi0.36 x
VDDP V
Spike filter always blocked
pulse duration tSF1 CC −−10 ns only PORST pin
Spike filter pass-through
pulse duration tSF2 CC 100 −−ns only PORST pin
Table 23 Standard_Pa ds Class_A1
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input Hysteresis for A1
pads 1) HYSA1
CC 0.1 x
VDDP
−−V
Input Leakage Current
Class A1 IOZA1
CC -500 500 nA Vi0V;
ViVDDP V
Ratio Vil/Vih, A1 pads VILA1 /
VIHA1
CC
0.6 −−
On-Resistance of the
class A1 pad, weak driver RDSONW
CC 450 600 Ohm IOH<-0.5mA;
P_MOS
210 340 Ohm IOL<0.5mA;
N_MOS
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 14 V 1.1, 2011-06
On-Resistance of the
class A1 pad, medium
driver
RDSONM
CC −−155 Ohm IOH<-2mA;
P_MOS
−−110 Ohm IOL<2mA;
N_MOS
Fall time, pad type A1 tFA1 CC −−150 ns CL= 20 pF; pin
out
driver= weak
−−50 ns CL= 50 pF; pin
out
driver= medium
−−140 ns CL= 150 pF; pin
out
driver= medium
−−550 ns CL= 150 pF; pin
out
driver= weak
−−18000 ns CL= 20000 pF;
pin out
driver= medium
−−65000 ns CL= 20000 pF;
pin out
driver= weak
Table 23 Standard_Pa ds Class_A1 (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 15 V 1.1, 2011-06
Rise time, pad type A1 tRA1 CC −−150 ns CL= 20 pF; pin
out
driver= weak
−−50 ns CL= 50 pF; pin
out
driver= medium
−−140 ns CL= 150 pF; pin
out
driver= medium
−−550 ns CL= 150 pF; pin
out
driver= weak
−−18000 ns CL= 20000 pF;
pin out
driver= medium
−−65000 ns CL= 20000 pF;
pin out
driver= weak
Input high voltage class
A1 pads VIHA1
SR 0.6 x
VDDP
min(V
DDP+
0.3,3.6
)
V
Input low voltage class A1
pads VILA1 SR -0.3 0.36 x
VDDP
V
Table 23 Standard_Pa ds Class_A1 (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 16 V 1.1, 2011-06
Output voltage high class
A1 pads VOHA1
CC VDDP -
0.4 −−VIOH-1.4 mA;
pin out
driver= medium
2.4 −−VIOH-2 mA; pin
out
driver= medium
VDDP -
0.4 −−VIOH-400 μA;
pin out
driver= weak
2.4 −−VIOH-500 μA;
pin out
driver= weak
Output voltage low class
A1 pads VOLA1
CC −−0.4 V IOL2 mA; pin
out
driver= medium
−−0.4 V IOL500 μA;
pin out
driver= weak
1) Hysteresis is implemente d to avoid metastab le states a nd switching due to in ternal ground bou nce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Table 24 Standard_Pa ds Class_A1+
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input Hysteresis for A1+
pads 1) HYSA1
+ CC 0.1 x
VDDP
−−V
Input Leakage Current
Class A1+ IOZA1+
CC -1000 1000 nA
On-Resistance of the
class A1+ pad, weak
driver
RDSONW
CC 450 600 Ohm IOH<-0.5mA;
P_MOS
210 340 Ohm IOL<0.5mA;
N_MOS
Table 23 Standard_Pa ds Class_A1 (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 17 V 1.1, 2011-06
On-Resistance of the
class A1+ pad, medium
driver
RDSONM
CC −−155 Ohm IOH<-2mA;
P_MOS
−−110 Ohm IOL<2mA;
N_MOS
On-Resistance of the
class A1+ pad, strong
driver
RDSON1+
CC −−100 Ohm IOH<-2mA;
P_MOS
−−80 Ohm IOL<2mA;
N_MOS
Fall time, pad type A1+ tFA1+ CC −−150 ns CL= 20 pF; pin
out
driver= weak
−−28 ns CL=50pF;
edge= slow ;
pin out
driver= strong
−−16 ns CL=50pF;
edge= soft ; pin
out
driver= strong
−−50 ns CL= 50 pF; pin
out
driver= medium
−−140 ns CL= 150 pF; pin
out
driver= medium
−−550 ns CL= 150 pF; pin
out
driver= weak
−−18000 ns CL= 20000 pF;
pin out
driver= medium
−−65000 ns CL= 20000 pF;
pin out
driver= weak
Table 24 Standard_Pa ds Class_A1+ (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 18 V 1.1, 2011-06
Rise time, pad type A1+ tRA1+ CC −−150 ns CL= 20 pF; pin
out
driver= weak
−−28 ns CL=50pF;
edge= slow ;
pin out
driver= strong
−−16 ns CL=50pF;
edge= soft ; pin
out
driver= strong
−−50 ns CL= 50 pF; pin
out
driver= medium
−−140 ns CL= 150 pF; pin
out
driver= medium
−−550 ns CL= 150 pF; pin
out
driver= weak
−−18000 ns CL= 20000 pF;
pin out
driver= medium
−−65000 ns CL= 20000 pF;
pin out
driver= weak
Input high voltage, Class
A1+ pads VIHA1+
SR 0.6 x
VDDP
min(V
DDP+
0.3,3.6
)
V
Input low voltage Class
A1+ pads VILA1+
SR -0.3 0.36 x
VDDP
V
Ratio Vil/Vih, A1+ pads VILA1+ /
VIHA1+
CC
0.6 −−
Table 24 Standard_Pa ds Class_A1+ (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 19 V 1.1, 2011-06
Output voltage high class
A1+ pads VOHA1+
CC VDDP -
0.4 −−VIOH-1.4 mA;
pin out
driver= medium
VDDP -
0.4 −−VIOH-1.4 mA;
pin out
driver= strong
2.4 −−VIOH-2 mA; pin
out
driver= medium
2.4 −−VIOH-2 mA; pin
out
driver= strong
VDDP -
0.4 −−VIOH-400 μA;
pin out
driver= weak
2.4 −−VIOH-500 μA;
pin out
driver= weak
Output voltage low class
A1+ pads VOLA1+
CC −−0.4 V IOL2 mA; pin
out
driver= medium
−−0.4 V IOL2 mA; pin
out
driver= strong
−−0.4 V IOL500 μA;
pin out
driver= weak
1) Hysteresis is implemente d to avoid metastab le states a nd switching due to in ternal ground bou nce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Table 24 Standard_Pa ds Class_A1+ (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 20 V 1.1, 2011-06
Table 25 Standard_Pa ds Class_A2
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input Hysteresis for A2
pads 1) HYSA2
CC 0.1 x
VDDP
−−V
Input Leakage current
Class A2 IOZA2
CC -6000 6000 nA Vi<VDDP / 2 -
1V;
Vi>VDDP / 2
+ 1 V; Vi0V;
ViVDDP V
-3000 3000 nA Vi>VDDP / 2 -
1V; Vi<VDDP / 2
+ 1 V
Ratio Vil/Vih, A2 pads VILA2 /
VIHA2
CC
0.6 −−
On-Resistance of the
class A2 pad, weak driver RDSONW
CC 450 600 Ohm IOH<-0.5mA;
P_MOS
210 340 Ohm IOL<0.5mA;
N_MOS
On-Resistance of the
class A2 pad, medium
driver
RDSONM
CC −−155 Ohm IOH<-2mA;
P_MOS
−−110 Ohm IOL<2mA;
N_MOS
On-Resistance of the
class A2 pad, strong driver RDSON2
CC −−28 Ohm IOH<-2mA;
P_MOS
−−22 Ohm IOL<2mA;
N_MOS
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 21 V 1.1, 2011-06
Fall time, pad type A2 tFA2 CC −−150 ns CL= 20 pF; pin
out
driver= weak
−−7ns
CL=50pF;
edge= medium
; pin out
driver= strong
−−10 ns CL=50pF;
edge= medium-
minus ; pin out
driver= strong
−−3.7 ns CL=50pF;
edge= sharp ;
pin out
driver= strong
−−5ns
CL=50pF;
edge= sharp-
minus ; pin out
driver= strong
−−16 ns CL=50pF;
edge= soft ; pin
out
driver= strong
−−50 ns CL= 50 pF; pin
out
driver= medium
−−7.5 ns CL=100pF;
edge= sharp ;
pin out
driver= strong
−−140 ns CL= 150 pF; pin
out
driver= medium
Table 25 Standard_Pa ds Class_A2 (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 22 V 1.1, 2011-06
−−550 ns CL= 150 pF; pin
out
driver= weak
−−18000 ns CL= 20000 pF;
pin out
driver= medium
−−65000 ns CL= 20000 pF;
pin out
driver= weak
Table 25 Standard_Pa ds Class_A2 (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 23 V 1.1, 2011-06
Rise time, pad type A2 tRA2 CC −−150 ns CL= 20 pF; pin
out
driver= weak
−−7.0 ns CL=50pF;
edge= medium
; pin out
driver= strong
−−10 ns CL=50pF;
edge= medium-
minus ; pin out
driver= strong
−−3.7 ns CL=50pF;
edge= sharp ;
pin out
driver= strong
−−5ns
CL=50pF;
edge= sharp-
minus ; pin out
driver= strong
−−16 ns CL=50pF;
edge= soft ; pin
out
driver= strong
−−50 ns CL= 50 pF; pin
out
driver= medium
−−7.5 ns CL=100pF;
edge= sharp ;
pin out
driver= strong
−−140 ns CL= 150 pF; pin
out
driver= medium
Table 25 Standard_Pa ds Class_A2 (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 24 V 1.1, 2011-06
−−550 ns CL= 150 pF; pin
out
driver= weak
−−18000 ns CL= 20000 pF;
pin out
driver= medium
−−65000 ns CL= 20000 pF;
pin out
driver= weak
Input high voltage, class
A2 pads VIHA2
SR 0.6 x
VDDP
min(V
DDP +
0.3,
3.6)
V
Input low voltage Class A2
pads VILA2 SR -0.3 0.36 x
VDDP
V
Output voltage high class
A2 pads VOHA2
CC VDDP -
0.4 −−VIOH-1.4 mA;
pin out
driver= medium
VDDP -
0.4 −−VIOH-1.4 mA;
pin out
driver= strong
2.4 −−VIOH-2 mA; pin
out
driver= medium
2.4 −−VIOH-2 mA; pin
out
driver= strong
VDDP -
0.4 −−VIOH-400 μA;
pin out
driver= weak
2.4 −−VIOH-500 μA;
pin out
driver= weak
Table 25 Standard_Pa ds Class_A2 (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 25 V 1.1, 2011-06
Output voltage low class
A2 pads VOLA2
CC −−0.4 V IOL2 mA; pin
out
driver= medium
−−0.4 V IOL2 mA; pin
out
driver= strong
−−0.4 V IOL500 μA;
pin out
driver= weak
1) Hysteresis is implemente d to avoid metastab le states a nd switching due to in ternal ground bou nce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Table 26 Standard_Pa ds Class_F
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input Hysteresis F1) HYSF
CC 0.05 x
VDDP
−−V
Input Leakage Current
Class F IOZF CC -6000 6000 nA Vi<VDDP / 2 -
1V; Vi>VDDP / 2
+ 1 V; Vi0V;
ViVDDP V
-3000 3000 nA Vi>VDDP / 2 -
1V; Vi<VDDP / 2
+ 1 V
Ratio Vil/ Vih, F pads VILF /
VIHF CC 0.6 −−
On-Resistance of the
class F pad, weak driver RDSONW
CC 450 600 Ohm IOH<-0.5mA;
P_MOS
210 340 Ohm IOL<0.5mA;
N_MOS
On-Resistance of the
class F pad, medium
driver
RDSONM
CC −−155 Ohm IOH<-2mA;
P_MOS
−−110 Ohm IOL<2mA;
N_MOS
Table 25 Standard_Pa ds Class_A2 (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 26 V 1.1, 2011-06
Fall time, pad type F,
CMOS mode tFF CC −−60 ns CL=50pF
Rise time, pad type F,
CMOS mode tRF CC −−60 ns CL=50pF
Input high voltage, pad
class F, CMOS mode VIHF SR 0.6 x
VDDP
min(V
DDP+
0.3,
3.6)
V
Input low voltage, Class F
pads, CMOS mode VILF SR -0.3 0.36 x
VDDP
V
Output high voltage, class
F pads, CMOS mode VOHF
CC VDDP-
0.4
−−VIOH-1.4 mA
2.4 −−VIOH-2 mA
Output low voltage , class
F pads, CMOS mode VOLF CC −−0.4 V IOL2mA
1) Hysteresis is implemente d to avoid metastab le states a nd switching due to in ternal ground bou nce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Table 27 Standard_Pa ds Class_I
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input Hysteresis Class I1) HYSI
CC 0.1 x
VDDP
−−V
Input Leakage Current IOZI CC -1000 1000 nA
Ratio between low and
high input threshold VILI / VIHI
CC 0.6 −−
Input high voltage, class I
pins VIHI SR 0.6 x
VDDP
min(V
DDP+
0.3,
3.6)
V
Input low voltage, Class I
pads VILI SR -0.3 0.36 x
VDDP
V
Table 26 Standard_Pa ds Class_F (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 27 V 1.1, 2011-06
1) Hysteresis is implemente d to avoid metastab le states a nd switching due to in ternal ground bou nce. It can´t be
guaranteed that it suppresses switching due to external system noise.
Table 28 LVDS_Pads Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Output impedance, pad
class F, LVDS mode RO CC 40 140 Ohm
Fall time, pad type LVDS tFL CC −−2 ns termination
100 ±1%
Rise time, pad type LVDS tRL CC −−2 ns termination
100 ±1%
Pad set-up time tSET_LVD
S CC −−13 μs termination
100 ±1%
Output Differential Voltage VOD CC 150 400 mV termination
100 ±1%
Output voltage high, pad
class F, LVDS mode VOH CC −−1525 mV termination
100 ±1%
Output voltage low, pad
class F, LVDS mode VOL CC 875 −−mV termination
100 ±1%
Output Offset Voltage VOS CC 1075 1325 mV termination
100 ±1%
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 28 V 1.1, 2011-06
5.2.2 Analog to Digital Converters (ADCx)
ADC parameter are valid for VDD / DDAF = 1.235 V to 1.365 V; VDDM = 4.75 V to 5.25 V.
Table 29 ADC Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Switched capacitance at
the analog voltage inputs1) CAINSW
CC 920pF
Total capacitance of an
analog input CAINTOT
CC 20 30 pF
Switched capacitance at
the positive reference
voltage input2)3)
CAREFSW
CC 15 30 pF
Total capacitance of the
voltage reference inputs 2) CAREFTO
T CC 20 40 pF
Differential Non-Linearity
Error4)5)6)7) EADNL
CC -3 3 LSB ADC
resolution= 12-
bit 8) 9)
Gain Error4)6)5)7) EAGAIN
CC -3.5 3.5 LSB ADC
resolution= 12-
bit 8) 9)
Integral Non-
Linearity4)6)5)7) EAINL
CC -3 3 LSB ADC
resolution= 12-
bit 8) 9)
Offset Error4)6)5)7) EAOFF
CC -4 4 LSB ADC
resolution= 12-
bit 8) 9)
Converter clock fADC SC 4 90 MHz fADC=fFPI
Internal ADC clock fADCI CC 1 18 MHz
Charge consumption per
conversion QCONV
CC 70 8510) 100 pC charge needs to
be provided via
VAREF0
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 29 V 1.1, 2011-06
Input leakage at analog
inputs11) IOZ1 CC -100 500 nA ViVDDM V;
Vi0.97 x
VDDM V;
overlayed= No
-100 600 nA Vi0.97 x
VDDM V;
ViVDDM V;
overlayed= Yes
-500 100 nA Vi0.03 x
VDDM V;
Vi0V;
overlayed= No
-600 100 nA Vi0.03 x
VDDM V;
Vi0V;
overlayed= Yes
-100 200 nA Vi> 0.03 x
VDDM V;
Vi< 0.97 x
VDDM V;
overlayed= No
-100 300 nA Vi< 0.97 x
VDDM V;
Vi> 0.03 x
VDDM V;
overlayed= Yes
Input leakage current at
Varef0 IOZ2 CC -2 2μAVAREF0VDDM V
Input leakage current at
Vagnd0 IOZ3 CC -2 2μAVAGND0VDDM V
ON resistance of the
transmission gates in the
analog voltage path
RAIN CC 900 1500 Ohm
ON resistance for the ADC
test (pull down for AIN7) RAIN7T
CC 180 550 900 Ohm
Table 29 ADC Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 30 V 1.1, 2011-06
Resistance of the
reference vol t age input
path
RAREF
CC 500 1000 Ohm
Sample time tS CC 2 257 TADCI
Calibration time after reset tCAL CC −−4352 cycle
s
Total Unadjusted
Error6)5)12) TUE CC -4 413) LSB ADC
resolution= 12-
bit
Analog reference ground2) VAGND0
SR VSSM -
0.05 VAREF0
- 1 V
Analog input voltage VAIN SR VAGND0 VAREF0 V
Analog reference voltage2) VAREF0
SR VAGND0
+ 1 VDDM +
0.0514)
15)
V
Analog reference voltage
range6)5)2) VAREF0 -
VAGND0
SR
VDDM/2 VDDM +
0.05 V
1) The sampling capacity of the conversion C-network is pre-charged to VAREF0/2 before the sampling moment.
Because of the parasitic elemen ts the voltage measured at AINx can deviate from VAREF0/2.
2) Applies to AINx, when used as auxiliary reference input.
3) This represents an equivalent switched capacit ance. This capacitance is not switched to the reference voltage
at once. Instead smaller capacitances are successively switched to the refere nce voltage.
4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
5) If a reduced analog reference voltage be tween 1V and VDDM / 2 is used, then there are addition al decrease in
the ADC speed and accuracy.
6) If the analog referen ce voltage range is below VDDM but still in t he defi ned rang e of VDDM / 2 a nd VDDM is used,
then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1),
TUE,DNL,INL,Gain, and Offs et errors increase also by the factor 1/k.
7) If the analog reference voltage is > VDDM, then the ADC converter errors increase.
8) For 10-bit conversions the error value must be multiplied with a factor 0.25.
9) For 8-bit conversions the error value must be multiplied with a factor 0.0625.
10)For a conversion time of 1 µs a rms value of 85µA result for IAREF0.
11)The leakage current definition is a continuos function, as shown in figure ADCx Analoge Input Leakage. The
numerical values defined determine the characteristic points of the given continuous linear approximation -
they do not define step function.
12)Measured without noise.
Table 29 ADC Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 31 V 1.1, 2011-06
The power-up calibration of the ADC requires a maximum number of 4352 fADCI cycles.
Figure 7 ADCx Input Circuits
13)For 10-bit conversion the TUE is ±2LSB; for 8-bit conversion the TUE is ±1LSB
14)A running conversion may become inexact in case of violating the normal conditions (voltage overshoot).
15)If the reference voltage VAREF0 in crease or the VDDM decrease, so that VAREF = (VDDM + 0.05V to VDDM + 0.07V),
then the accuracy of the ADC decrease by 4LSB12.
Table 30 Conversi on Time (Operating Conditions apply)
Parameter Symbol Values Unit Note
Conversion
time with
post-calibration
tCCC 2 ×TADC +(4+STC+n)× TADCI μs n = 8, 10, 12 for
n - bit conversion
TADC =1/fFPI
TADCI =1/fADCI
Conversion
time without
post-calibration
2×TADC +(2+STC+n)× TADCI
Reference Voltage Input Circuitry
Analog Input Circuitry
Analog_InpRefDiag
REXT
=
VAIN CEXT
RAIN, On
CAINTOT - CAINSW
CAINSW
ANx
VAREF
RAREF, On
CAREFTOT - CAREFSW CAREFSW
VAGNDx
VAREFx
RAIN7T
VAGNDx
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 32 V 1.1, 2011-06
Figure 8 ADCx Analog Inputs Leakage
VIN[VDDM%]
200nA
500nA
3% 100%97%
Ioz1
100nA
-500nA
-100nA
VIN[VDDM%]
300nA
600nA
3% 100%97%
Ioz1
100nA
-600nA
-100nA
Single ADC Input
Overlayed ADC/FADC Input
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 33 V 1.1, 2011-06
5.2.3 Fas t An al og to Digi ta l Co nv e rter (F ADC )
Table 31 FADC Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input current at VFAREF IFAREF
CC −−120 μA
Input leakage current at
VFAREF1) IFOZ2
CC -500 500 nA VFAREFVDDMF
V; VFAREF0V
Input leakage current at
VFAGND IFOZ3
CC -500 500 nA
DNL error EFDNL
CC -1 1LSBVIN mode=
differential
-1 1LSB
VIN mode=
single ended
GRADient error EFGRAD
CC -5 5%VIN mode=
differential ;
Gain4
-5 5%
VIN mode=
single ended ;
Gain4
-6 6%VIN mode=
differential ;
Gain= 8
-6 6%
VIN mode=
single ended ;
Gain= 8
INL error EFINL
CC -4 4LSBVIN mode=
differential
-4 4LSB
VIN mode=
single ended
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 34 V 1.1, 2011-06
Offset error EFOFF
CC -90 90 mV VIN mode=
differential ;
Calibration= No
-90 90 mV VIN mode=
single ended ;
Calibration= No
-20 20 mV VIN mode=
differential ;
Calibration= Ye
s2)3)
-20 20 mV VIN mode=
single ended ;
Calibration= Ye
s2)3)
Error of commen mode
voltage VFAREF/2 EFREF
CC -60 60 mV
Channel amplifier cutoff
frequency fCOFF
CC 2−−MHz
Converter clock fFADC
SC 190 MHz fFADC=fFPI
Conversion time tC CC −−21 1 /
fFADC
For 10-bit
conversion
Input resistance of the
analog voltage path (Rn,
Rp)
RFAIN
CC 100 200 kOh
m
Settling time of a channel
amplifier after changing
ENN or ENP
tSET CC −−5μs
Analog input voltage
range VAINF
SR VFAGND VDDMF V
Analog reference ground VFAGND
SR VSSAF -
0.05 VSSAF
+ 0.05 V
Analog reference voltage VFAREF
SR 3.0 3.634)
5) V
Table 31 FADC Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 35 V 1.1, 2011-06
The calibration procedure should run after each power-up, when all power supply
voltages and the reference voltage have stabilized.
Figure 9 FADC Input Circuits
1) This value applies in power-down mode.
2) Calibration should be preformed at each power-up. In case of a continous operation, it should be performed
minimium once per week.
3) The offser error voltage drifts over the whole temperature range maximum +-3LSB.
4) Voltage overshoot to 4V is pe rmissible, provided the pulse dur ation is less than 100 μs and the cumulated su m
of the pulses does not exceed 1 h.
5) A running conversion may become inexact in case of violating the nomal operating conditions (voltage
overshoots).
FADC_InpRefDiag
=
+
-
+
-
RN
FAINxN
FAINxP
VFAGND
FADC Analog Input Stage
RP
VFAREF/2
VFAREF
FADC Reference Voltage
Input Circuitry
VFAGND
VFAREF
IFAREF
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 36 V 1.1, 2011-06
5.2.4 Oscillator Pins
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal or
ceramic resonator supplier.
Table 32 OSC_XTAL Pa rameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input current at XTAL1 IIX1 CC -25 25 μAVIN<VDDOSC3 ;
VIN>0 V
Input frequency fOSC SR 4 40 MHz Direct Input
Mode selected
825 MHz External Crystal
Mode selected
Oscillator start-up time1)
1) tOSCS is defined from the momen t wh en VDDOSC3 = 3. 13V u ntil t he oscillatio ns rea ch an a mplitude at XTAL1 of
0.3 * VDDOSC3. The external oscillator circuitry must be optimized by the customer and checked for negative
resistance as recommended and specified by crystral suppliers.
tOSCS
CC −−10 ms
Input high voltage at
XTAL12)
2) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.4 * VDDOSC3 is
necessary.
VIHX SR 0.7 x
VDDOS
C3
VDDOS
C3 +
0.5
V
Input low voltage at
XTAL1 VILX SR -0.5 0.3 x
VDDOS
C3
V
Input Hysteresis for
XTAL1 pad 3)
3) Hysteresis is implemente d to avoid metastab le states a nd switching due to in ternal ground bou nce. It can´t be
guaranteed that it suppresses switching due to external system noise.
HYSAX
CC −−200 mV
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 37 V 1.1, 2011-06
5.2.5 Temperature Sensor
The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bit field of the DTSSTAT register.
(1)
Table 33 DTS Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Measurement time tM CC −−100 μs
Temperature sensor
range TSR SR -40 150 °C
Sensor Accuracy
(calibrated) TTSA CC -6 C
Start-up time after resets
inactive tTSST SR −−20 μs
Tj DTSSTATRESULT 596
203,
-------------------------------------------------------------------=
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 38 V 1.1, 2011-06
5.2.6 Power Supply Current
The total power supply current defined below consists of leakage and switching
component.
Application relevant values are typically lower than those given in the following
two tables and depend on the customer's system operating conditions (e.g.
thermal connection or used application config urations).
The operating conditions for the parameters in the following table are:
VDD=1.365 V, VDDP=3.47 V, VDDM=5.1 V, fLMB=180 / 133 MHz, TJ=150 oC
The realisic power pattern defines the following condi tions:
TJ=150 oC
fLMB =fPCP =fCPU = 180 / 133 MHz
fFPI = 90 / 66.5 MHz
VDD =VDDOSC =VDDAF =1.326V
VDDP =VDDOSC3 =VDDFL3 =VDDMF =3.366V
VDDM =5.1V
The max power pattern defines the following conditions:
TJ=150 oC
fLMB =fPCP =fCPU = 180 / 133 MHz
fFPI = 90 / 66.5 MHz
VDD =VDDOSC =VDDAF =1.365V
VDDP =VDDOSC3 =VDDFL3 =VDDMF =3.47V
VDDM =5.5V
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 39 V 1.1, 2011-06
Table 34 Power Supply Par ameters
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Core active
mode supply
current1)2)
IDD CC −−4863) mA power pattern= max ;
SAK-TC1782F-256F133HR
SAK-TC1782F-256F133HL
SAK-TC1782N-256F133HR
SAK-TC1782N-256F133HL
SAK-TC1182N-256F133HR
SAK-TC1182N-256F 133HL
−−5503) mA power pattern= max ;
SAK-TC1782F320F180HR
SAK-TC1782F320F180HL
SAK-TC1782N-320F180HR
SAK-TC1782N-320F180HL
SAK-TC1182N-320F180HR
SAK-TC1182N-320F180HL
−−3704) mA power pattern= realistic ;
SAK-TC1782F-256F133HR
SAK-TC1782F-256F133HL
SAK-TC1782N-256F133HR
SAK-TC1782N-256F133HL
SAK-TC1182N-256F133HR
SAK-TC1182N-256F
133HL; VDD=1.326 V
−−3984) mA power pattern= realistic ;
SAK-TC1782F320F180HR
SAK-TC1782F320F180HL
SAK-TC1782N-320F180HR
SAK-TC1782N-320F180HL
SAK-TC1182N-320F180HR
SAK-TC1182N-
320F180HL; VDD=1.326 V
IDD current at
PORST Low IDD_PORS
T CC −−300 mA
−−291 mA VDD=1.326 V
Analog core
supply current IDDAF
CC −−23 mA
Oscillator core
supply current IDDOSC
CC −−4mA
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 40 V 1.1, 2011-06
IDDP current at
PORST Low IDDP_POR
ST CC −−2.5 mA
IDDP current no
pad activity,
LVDS off
IDDP CC −−IDDP_P
ORST +
12
mA including flash read current
−−IDDP_P
ORST +
27
mA including flash programming
current 5)
−−IDDP_P
ORST +
20 6)
mA including flash erase verify
current 5)
Flash memory
current during
reading the
Flash memory
IDDFL3
CC −−56 mA
Oscillator
power supply
current, 3.3V
IDDOSC3
CC −−15 mA
FADC analog
supply current,
3.3V
IDDMF
CC −−15 mA
Current
Consumption of
LVDS Pad
Pairs
ILVDS
CC −−24 mA for all LVDS pads in total
ADC 5V power
supply current IDDM CC −−2mA
Table 34 Power Supply Par ameters (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 41 V 1.1, 2011-06
Maximum
power
dissipation
PD CC −−1143 mW power pattern= max ;
SAK-TC1782F-256F133HR
SAK-TC1782F-256F133HL
SAK-TC1782N-256F133HR
SAK-TC1782N-256F133HL
SAK-TC1182N-256F133HR
SAK-TC1182N-256F 133HL
−−1231 mW p ower pattern= max ;
SAK-TC1782F320F180HR
SAK-TC1782F320F180HL
SAK-TC1782N-320F180HR
SAK-TC1782N-320F180HL
SAK-TC1182N-320F180HR
SAK-TC1182N-320F180HL
−−957 mW power pattern= realistic ;
SAK-TC1782F-256F133HR
SAK-TC1782F-256F133HL
SAK-TC1782N-256F133HR
SAK-TC1782N-256F133HL
SAK-TC1182N-256F133HR
SAK-TC1182N-256F
133HL; VDD=1.326 V
−−994 mW power pattern= realistic ;
SAK-TC1782F320F180HR
SAK-TC1782F320F180HL
SAK-TC1782N-320F180HR
SAK-TC1782N-320F180HL
SAK-TC1182N-320F180HR
SAK-TC1182N-
320F180HL; VDD=1.326 V
1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each customer
application will most probably be lower tha n this value, but must be evaluated seperately.
2) This current includes the E-Ray module power consumption, including the PCP operation component.
3) The IDD decreases typically by 68mA if the fCPU decreases by 50MHz, at constant TJ
4) The IDD decreases typically by 30mA if the fCPU decreases by 50MHz, at constant TJ
5) Relevant for the power supply dimensioning, not fo r thermal considerations.
6) In case of erase of Program Flash PF, internal fl ash array lo ading effects may genera te transient current spikes
of up to 15 mA for maximum 5 ms per flash module.
Table 34 Power Supply Par ameters (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersDC Parameters
Data Sheet 42 V 1.1, 2011-06
5.2.6.1 Calculating the 1.3 V Current Consumption
The current consumption of the 1.3 V rail compose out of two parts:
Static current consumption
Dynamic current consumption
The static current consumption is relate d to the device temperature TJ and the dynamic
current consumption depends of the configured clocking frequencies and the softw are
application executed. These two parts needs to be added in order to get the rail current
consumption.
(2)
(3)
Function 2 defines the typical static current consumption and Function 3 defines the
maximum static current consumption. Both functions are valid for VDD =1.326V.
For the dynamic current consumption using the application pattern and fLMB =2*fFPI the
function 4 applies:
(4)
and this finally results in
(5)
I02 20897 mA
C
---------
,e0 02696,TJ
×
×C[]=
I010 68 mA
C
---------
,e0 02203,TJ
×
×C[]=
IDym06 mA
MHz
-------------
,fCPU MHz[]×=
IDD I0IDYM
+=
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 43 V 1.1, 2011-06
5.3 AC Parameters
All AC parameters are defined with the temperature compensation disabled. That
means, keeping the pads constantl y at maximum strength.
5.3.1 Testing Waveforms
Figure 10 Rise/Fa ll Time Parameters
Figure 11 Testing Waveform, Output Delay
Figure 12 Testing Waveform, Output High Impedance
10%
90%
10%
90%
V
SS
V
DDP
t
R
rise_fall
t
F
mct04881_a.vsd
V
DDE
/ 2 Test Points V
DDE
/ 2
V
SS
V
DDP
MCT04880_new
V
Load
+ 0.1 V V
OH
- 0.1 V
Timing
Reference
Points
V
Load
- 0.1 V V
OL
- 0.1 V
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 44 V 1.1, 2011-06
5.3.2 Power Sequencing
Figure 13 5 V / 3.3 V / 1.3 V Power-Up/Down Sequence
The following list of rules applies to the power-up/down sequence:
All ground pins VSS must be externally connected to one single star point in the
system. Regarding the DC current compon ent, all ground p ins are intern ally directly
connected.
At any moment in time to avoid increased latch-up risk,
each power supply must be higher then any lower_power_supply - 0.5 V, or:
VDD5 > VDD3.3 - 0.5 V; VDD5 > VDD1.3 - 0.5 V;VDD3.3 > VDD1.3 - 0.5 V, see Figure 13.
The latch-up risk is minimized if the I/O currents are limited to:
20 mA for one pin group
AND 100 mA for the completed device I/Os
AND additionally before power-up / after power-down:
1 mA for one pin in inactive mode (0 V on all power supplies)
During power-up and power-down, the voltage difference between the power supply
pins of the same voltage (3.3 V, 1.3 V, and 5 V) with different names (for example
VDDP, VDDFL3 ...), that are internally connected via diodes, must be lower than 100 mV.
On the other hand, all power supply pins with the same name (for example all VDDP),
Power-Up 10.vsd
1.3V
3.3V
5V
t
V
t
-12%
-12%
PORST
0.5V0.5V 0.5V
VDDP
VAREF
power
down power
fail
3.47V
3.0V
1.235V
1.365V
4.75V
5.25V
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 45 V 1.1, 2011-06
are internally directly connected. It is recommended that the power pins of the same
voltage are driven by a single power supply.
1. The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.3, and VAREF power-
supplies and the oscillator have reached stable operation, within the normal
operating conditions.
2. At normal power down the PORST signal should be activated within the normal
operating range, and then the power supplies may be switched off. Care must be
taken that all Flash write or delete sequences have been completed.
3. At power fail th e PORST signal must be activa ted at latest when any 3 .3 V or 1.3 V
power supply voltage fal ls 12% below the nomina l level. If, under these conditions,
the PORST is activated during a Flash write, only the memory row that was the target
of the write at the moment of the power loss will contain u nreliable content. In o rder
to ensure clean power-down behavior, the PORST signal should be activated as
close as possible to the normal operating voltage ra nge.
4. In case of a power-loss at any power-supply, all power supplies must be powe red-
down, conforming at the same time to the rules number 2 and 4.
5. Although not n ecessary, it is additionally recommended that all power supplie s are
powered-up/down together in a controlled way, as tight to each other as possible.
6. Additionally, regarding the ADC reference voltage VAREF:
VAREF must power-up at the same time or later then VDDM, and
VAREF must power-down either earlier or at latest to satisfy the condition
VAREF <VDDM + 0.5 V. This is requi red in order to prevent d ischarge of VAREF filter
capacitance through the ESD diodes through the VDDM power supply. In case of
discharging the reference capacitance throug h the ESD diodes, the current must
be lower than 5 mA.
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 46 V 1.1, 2011-06
5.3.3 Power, Pad and Reset Timing
Table 35 Reset Timings Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Application Reset Boot
Time1)2) tB CC 150 810 μs SAK-TC1782F-
256F133HR
SAK-TC1782F-
256F133HL
SAK-TC1782N-
256F133HR
SAK-TC1782N-
256F133HL
SAK-TC1182N-
256F133HR
SAK-TC1182N-
256F 133HL
150 665 μs SAK-
TC1782F320F1
80HR
SAK-
TC1782F320F1
80HL
SAK-TC1782N-
320F180HR
SAK-TC1782N-
320F180HL
SAK-TC1182N-
320F180HR
SAK-TC1182N-
320F180HL
Power on Reset Boot
Time3)4) tBP CC −−2.5 ms
HWCFG pins hold time
from ESR0 rising edge tHDH SR 16 /
fFPI
−−ns
HWCFG pins setup time to
ESR0 rising edge tHDS CC 0 −−ns
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 47 V 1.1, 2011-06
Ports inactive after ESR0
reset active tPI CC −−8 / fFPI ns
Ports inactive after
PORST reset active5) tPIP CC −−150 ns
Minimum P ORST active
time after power supplies
are stable at operating
levels
tPOA CC 10 −−ms
TESTMODE /TRST hold
time from PORST rising
edge
tPOH SR 100 −−ns
PORST rise time tPOR SR −−50 ms
TESTMODE /TRST
setup time to PORST
rising edge
tPOS SR 0 −−ns
1) The duration of the boot ti me is def ined bet ween the r ising edge of the internal application reset and t he clock
cycle when the first user instruction has entered the CPU pipeline and its processing starts.
2) The given time includes the time of the internal reset extension for a configured value of
SCU_RSTCNTCON.RELSA = 0x05BE.
3) The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the
first user instruction has entered the CPU pipeline and its processing starts.
4) The given time includes the internal reset extension t ime for the System and Application Rese t which is visible
through ESR0.
5) This parameter includes the delay of the ana log spike filter in the PORST pad.
Table 35 Reset Timings Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 48 V 1.1, 2011-06
Figure 14 Power, Pad and Reset Timing
reset_beh2
As progr am med
VDDP
Pads
Pad-stat e undefi ned
VDD
V
DDPPA
V
DDPPA
t
hd
t
POA
t
POA
TRST
TESTMODE
ESR0
PORST t
POH
HWCFG
t
HDH
t
PIP
t
PI
T ri-stat e or pul l devi ce active
t
hd
t
POH
t
HDH
t
PIP
t
PI
t
PIP
t
PI
t
PI
t
HDH
t
PI
V
DDP
-12%
V
DD
-12%
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 49 V 1.1, 2011-06
5.3.4 Phase Locked Loop (PLL)
Phase Locked Loo p Operation
When PLL operation is enabled and configured, the PLL clock fVCO (and with it the LMB-
Bus clock fLMB) is constantly adjusted to the selected frequency. The PLL is constantly
adjusting its output frequency to correspond to the input frequency (from crystal or clock
source), resulting in an accumulated jitter that is limited. This means that the relative
deviation for periods of more than one clock cycle is lower than for a single clock cycle.
This is especially important for bus cycles using wait states and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
Two formulas are defined for the (absolu te) approximate ma ximum value o f jitter Dm in
[ns] dependent on the K2 - factor, the LMB clock frequency fLMB in [MHz], and the
number m of consecutive fLMB clock periods.
(6)
(7)
With rising number m of clock cycles the maximum jitter increases linearly up to a value
of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum
Table 36 PLL_SysClk Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Accumulated Jitter DP CC -7 7ns
PLL base frequency fPLLBASE
CC 50 200 320 MHz
VCO input frequency fREF CC 8 16 MHz
VCO frequency range fVCO CC 4 00 720 MHz
PLL lock-in time tL CC 50 200 μsN>32
100 400 μsN32
for K2 100()and m fLMB MHz[]()2()
Dmns[] 740
K2 fLMB MHz[]×
---------------------------------------------5+
⎝⎠
⎛⎞
1001,K2×()m1()×
05,fLMB MHz[]1×
---------------------------------------------------------------- 0 01,K2×+
⎝⎠
⎛⎞
×=
else Dmns[] 740
K2 fLMB MHz[]×
---------------------------------------------5+=
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 50 V 1.1, 2011-06
accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock
frequency fLMB results in a higher abso lute maximum jitter value.
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL= 20 pF with the maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
VDDOSC3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
The maximum peak-to peak noise on the pad supply voltage, measured between
VDDOSC and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Oscillator Watchdog (OSC_WDT)
The expected input frequency is selected via the bit field SCU_OSCCON.OSCVAL. The
OSC_WDT checks for too low frequencies and for too high frequencies.
The frequency that is monitored is fOSCREF which is derived for fOSC.
(8)
The divider value SCU_OSCCON.OSCVAL has to be selected in a way that fOSCREF is
2.5 MHz.
Note: fOSCREF has to be within the ra nge of 2 MHz to 3 MHz and shou ld be as close as
possible to 2.5 MHz.
The monitored frequency is too low if it is below 1.25 MHz and too high if it is above
7.5 MHz. This leads to the following two conditions:
•Too low: fOSC <1.25MHz×(SCU_OSCCON.OSCVAL+1)
Too high: fOSC >7.5MHz×(SCU_OSCCON.OSCVAL+1)
Note: The accuracy is 30% for these boundaries.
fOSCREF
fOSC
OSCVAL 1+
-----------------------------------=
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 51 V 1.1, 2011-06
5.3.5 ERAY Phase Locked Loop (ERAY_PLL)
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL= 20 pF with the maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
VDDOSC3 and VSSOSC, is limited to a peak-to-peak voltage of VPP = 100 mV for noise
frequencies below 300 KHz and VPP = 40 mV for noise frequencies above
300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Table 37 PLL_ERAY Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Accumulated jitter at
SYSCLK pin DPP CC -0.8 0.8 ns
Accumulated_Jitter DP CC -0.5 0.5 ns
PLL Base Frequency of
the ERAY PLL fPLLBASE_
ERAY CC 50 250 360 MHz
VCO input frequency of
the ERAY PLL fREF CC 20 40 MHz
VCO frequency range of
the ERAY PLL fVCO_ERA
Y CC 450 500 MHz
PLL lock-in time tL CC 50 200 μs
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 52 V 1.1, 2011-06
5.3.6 JTAG Interface Timing
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters ar e n ot subj ect to production test but verified by design and/or
characterization.
Table 38 JTAG Interface Timing Parameters
(Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TCK clock period t1 SR 25 ns
TCK high time t2 SR 10 ns
TCK low time t3 SR 10 ns
TCK clock rise time t4 SR––4ns
TCK clock fall time t5 SR––4ns
TDI/TMS setup
to TCK rising edge t6 SR6––ns
TDI/TMS hold
after TCK rising edge t7 SR6––ns
TDO valid after TCK falling
edge1) (propagation delay)
1) The falling edge on TCK is used to generate the TDO timing.
t8 CC––13nsC
L=50pF
t8 CC3––nsC
L=20pF
TDO hold after TCK falling
edge1) t18 CC2––ns
TDO high imped. to valid
from TCK falling edge1)2)
2) The setup time for TDO is given implicitly by the TCK cycle time.
t9 CC––14nsC
L=50pF
TDO valid to high imped.
from TCK falling edge1) t10 CC 13.5 ns CL=50pF
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 53 V 1.1, 2011-06
Figure 15 Test Clock Timing (TCK)
Figure 16 JTAG Timing
MC_JTAG_TCK
0.9
VDDP
0.5
VDDP
t1
t2t3
0.1
VDDP
t5t4
t
6
t
7
t
6
t
7
t
9
t
8
t
10
TCK
TMS
TDI
TDO
MC_JTAG
t
18
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 54 V 1.1, 2011-06
5.3.7 DAP Interface Timing
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters ar e n ot subj ect to production test but verified by design and/or
characterization.
Figure 17 Test Clock Timing (DAP0)
Table 39 DAP Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
DAP0 clock period1)
1) See the DAP chapter for clock rate restrictions in the Active:IDLE protocol state.
tTCK SR 12.5 −−ns
DAP0 high time t12 SR 4 −−ns
DAP0 low time1) t13 SR 4 −−ns
DAP0 clock rise time t14 SR −−2ns
DAP0 clock fall time t15 SR −−2ns
DAP1 setup to DAP0
rising edge t16 SR 6.0 −−ns
DAP1 hold after DAP0
rising edge t17 SR 6.0 −−ns
DAP1 valid per DAP0
clock period2)
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t19 CC 8 −−ns CL=20pF;
f=80MHz
10 −−ns CL=50pF;
f=40MHz
MC_DAP0
0.9
VDDP
0.5
VDDP
t11
t12 t13
0.1
VDDP
t15 t14
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 55 V 1.1, 2011-06
Figure 18 DAP Timing Host to Device
Figure 19 DAP Timing Device to Host
t16 t17
DAP0
DAP1
MC_DAP1_RX
DAP1
MC_DAP1_TX
t
11
t
19
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 56 V 1.1, 2011-06
5.3.8 Peripheral Timings
Note: Peripheral timing parameters are not subject to production test. They are verified
by design/characterization.
5.3.8.1 Micro Link Interface (MLI) Timing
Figure 20 MLI Interface Timing
Note: The generation of RREADYx is in the input clock domain of the receiver. The
reception of TREADYx is asynchronous to TCLKx.
t27
t25 t26
t16 t17
t15
t15
MLI_Tmg_2.vsd
TDATAx
TVALIDx
TCLKx
RDATAx
RVALIDx
RCLKx
TREADYx
RREADYx
t10
t13
t11
t12
t14
t20
t27
MLI Transmitter Timing
MLI Receiver Timing
t23
t21
t22
t24
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 57 V 1.1, 2011-06
The MLI parameters are vaild for CL= 50 pF (typical).
Table 40 MLI Receiver
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
RCLK clock period t20 SR 1 / fFPI −−ns
RCLK high time1)2)
1) The following formula is valid: t21 + t22 = t20.
2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver
timing parameters.
t21 SR 0.5 x
t20
ns
RCLK low time1)2) t22 SR 0.5 x
t20
ns
RCLK rise time3)
3) The RCLK max. input rise/fall times ar e best case parameters fo r fSYS = 90 MHz. For reduction of E MI, slower
input signal rise/fall times can be used for longer RCLK clock periods.
t23 SR −−4ns
RCLK fall time3) t24 SR −−4ns
RDATA/RVALID setup
time before RCLK falling
edge
t25 SR 4.2 −−ns
RDATA/RVALID hold time
after RCLK falling edge t26 CC 2.2 −−ns
RREADY output delay
time t27 CC 0 16 ns
Table 41 MLI Transmitter
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TCLK clock period t10 CC 2 x 1 /
fFPI
−−ns
TCLK high time1)2) t11 CC 0.45 x
t10
0.5 x
t10
0.55 x
t10
ns
TCLK low time1)2) t12 CC 0.45 x
t10
0.5 x
t10
0.55 x
t10
ns
TCLK rise time t13 CC −−0.3 x
t103) ns
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 58 V 1.1, 2011-06
5.3.8.2 Micro Second Channel (MSC) Interface Timing
The MSC parameters are vaild for CL= 50 pF (typical).
TCLK fall time t14 CC −−0.3 x
t103) ns
TDATA/TVALID output
delay time t15 CC -3 4.4 ns
TREADY setup time
before TCLK rising edge t16 SR 18 −−ns
TREADY hold time after
TCLK rising edge t17 SR -4 −−ns
1) The following formula is valid: t11 + t12 = t10.
2) The min./max. TCLK low/high times t11/t12 include the PLL jitter of fSYS. Fractional divider settings must be
regarded additionally to t11 / t12.
3) For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended
for TCLK.
Table 42 MSC Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
FCLP clock period1)2) t40 CC 2 x
TMSC3) −−ns
SOP4)/ENx outputs delay
from FCLP4) rising edge t45 CC -2 5 ns ENx with strong
driver and
sharp (minus )
edge
-2 10 ns ENx with strong
driver and
medium
(minus) edge
021 ns ENx with strong
driver and soft
edge
Table 41 MLI Transmitter (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 59 V 1.1, 2011-06
Figure 21 MSC Interface Timing
Note: The data at SOP should be sampled with the falling edge of FCLP in the target
device.
SDI bit time t46 CC 8 x
TMSC
−−ns
SDI rise time t48 SR −−100 ns
SDI fall time t49 SR −−100 ns
1) FCLP signal rise/fall times are only defined by the pad rise/fall times.
2) FCLP signal high and low can be minimum 1xTMSC
3) TMSC = TSYS = 1 / fSYS.
4) SOP / FCLP either propagated by LVDS or by CMOS strong driver and non soft edge.
Table 42 MSC Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
MSC_Tmg_1.vsd
t45 t45
t40
0.1 VDDP
0.9 VDDP
t46
t48
0.1 VDDP
0.9 VDDP
t49
t46
SOP
EN
FCLP
SDI
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 60 V 1.1, 2011-06
5.3.8.3 SSC Master/Slave Mode Timing
The SSC parameters are vaild for CL= 50 pF (typical).
Table 43 SSC Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
SCLK clock period1)2)3)
1) SCLK signal rise/fall times are the same as the rise/fall times of the pad.
2) SCLK signal high and low times can be minimum 1xTSSC.
3) TSSCmin = TSYS = 1/fSYS.
t50 CC 2 x 1 /
fFPI
−−ns
MTSR/SLSOx delay form
SCLK rising edge t51 CC 0 8ns
MRST setup to SCLK
falling edge3) t52 SR 16.5 −−ns
MRST hold from SCLK
falling edge3) t53 SR 0 −−ns
SCLK input clock
period1)3) t54 SR 4 x 1 /
fFPI
−−ns
SCLK input clock duty
cycle t55_t54
SR 45 55 %
MTSR setup to SCLK
latching edge3)4)
4) Fractional divider switched off, SSC internal baud rate generation used.
t56 CC 1 / fFPI −−ns
MTSR hold from SCLK
latching edge t57 CC 1 / fFPI
+ 5 −−ns
SLSI setup to first SCLK
latching edge t58 CC 1 / fFPI
+ 5 −−ns
SLSI hold from last SCLK
latching edge t59 CC 7 −−ns
MRST delay from SCLK
shift edge t60 CC 0 16.5 ns
SLSI to valid data on
MRST t61 CC −−16.5 ns
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 61 V 1.1, 2011-06
Figure 22 SSC Master Mode Timing
Figure 23 SSC Slave Mode Timing
SSC_TmgMM
SCLK1)2)
MTSR1)
t51 t51
MRST1)
t53
Data
valid
t52
SLSOn2)
t51
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
2) The transition at SLSOn is based on the following setup: SSOTC.TRAIL = 0
and the first SCLK high pulse is in the first one of a transmission.
t50
SSC_TmgSM
SCLK1)
t55
MTSR1)
t57
Data
valid
t56
SLSI t58
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
t54
t55
t59
Last latching
SCLK edge
First latching
SCLK edge
t57
Data
valid
t56
MRST1)
t60
First shift
SCLK edge
t60
t61
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 62 V 1.1, 2011-06
5.3.8.4 ERAY Interface Timing
The timings of this section are valid for the strong driver and either sharp edge or medium
edge settings of the output driver s with CL = 25 pF.
The ERAY interface is only available for the SAK-TC1782F-320F180HR / SAK-
TC1782F-320F180HL.
Table 44 ERAY Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Time span from last BSS
to FES without the
influence of quartz
tolerancies (d10Bit_TX)1)
1) This includes the PLL_ERAY accumulated ji tter.
t60 CC 997.75 1002.2
5ns
TxD data valid from
fsample flip flop txd_reg
TxDA, TxDB
(dTxAsym)2)3)
2) Refers to delays caused by the asymmetries of the output drivers of the digital logi c and the GPIO pad drivers.
Quarz tolerance and PLL_ERAY accumulat ed jitter are not included.
3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of | tFA2 - tRA2| 1 ns.
t61-t62
CC −−1.5 ns Asymmetrical
delay of rising
and falling edge
(TxDA, TxDB)
Time span between last
BSS and FES without
influence of quartz
tolerancies
(d10Bit_RX)1)4)5)
4) Limits of 966ns and 1046.1 ns correspond t o (30%, 7 0%) * VDDP FlexRay stand ard input thresholds. For input
thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied.
t63 SR 966 1046.1 ns
RxD capture by fsample
(RxDA/RxDB sampling
flip-flop) (dRxAsym)5)
t64-t65
CC −−3.0 ns Asymmetrical
delay of rising
and falling edge
(RxDA, RxDB)
TxD data del a y from
sampling flip-flop dTxdly
CC −−10.0 ns Px_PDR.PDy =
000B
−−15.0 ns Px_PDR.PDy =
001B
RxD capture delay by
sampling flip-flop dRxdly
CC −−10.0 ns
TC1782 / TC1182
Electrical ParametersAC Parameters
Data Sheet 63 V 1.1, 2011-06
Figure 24 ERAY Timing
5) Valid for output slopes of the bus driver of dRxSlope 5ns, 20% * VDDP to 80% * VDDP, according to the
FlexRay Electrical Physical Layer Specification V2.1B. For A2 pads, the rise and fall times of the incoming
signal have to satisfy the following inequality: -1.6ns tFA2 - tRA2 1.3ns.
TXD
t60
0.7 VDD
0.3 VDD
BSS
(Byte Start Sequence) Last CRC Byte FES
(Frame End Sequence)
ERAY_TIMING
RXD
t63
0.7 VDD
0.3 VDD
BSS
(Byte Start Sequence) Last CRC Byte FES
(Frame End Sequence)
0.9 VDD
0.1 VDD
TXD
t61 t62
tsample
0.7 VDD
0.3 VDD
RXD
t64 t65
tsample
TC1782 / TC1182
Electrical ParametersPackage and Reliability
Data Sheet 64 V 1.1, 2011-06
5.4 Package and Reliability
5.4.1 Package Parameters
Table 45 Thermal Characteristics of the Package
Device Package RΘJCT1)
1) The top and bottom t hermal resist ances between the case a nd the ambie nt ( RTCAT, RTCAB) are to be combined
with the thermal resistances be tween the junction and the ca se given above (RTJCT, RTJCB), in order to calculate
the total thermal resistance bet ween the junction and the ambient (RTJA). The th ermal resistances between the
case and the ambient (RTCAT, RTCAB) depend on the external system (PCB, case) characteristics, and are
under user responsibility.
The junction temperature can be calculated using the following equation: TJ=TA+RTJA ×PD, where the RTJA
is the total thermal resistance between the junction and the ambient. This total junction ambient resistance
RTJA can be obtained from the upper four partial thermal resistances.
Thermal resistances as measured by the ’cold plate method’ (MIL SPEC-883 Method 1012.1).
RΘJCB1) RΘJLead Unit Note
TC1782 /
TC1182 PG-LQFP-176-
10 8,1 0,3 30,9 K/W with soldered
exposed pad 2)
2) It is recommended by Infineon Technologies AG to connect the exposed pad.
TC1782 /
TC1182 PG-LQFP-176-
10 8,1 12,6 30,9 K/W with not solde red
exposed pad
TC1782 / TC1182
Electrical ParametersPackage and Reliability
Data Sheet 65 V 1.1, 2011-06
5.4.2 Package Outline
Figure 25 Package Outlines PG-LQFP-176-10
You can find all of our packages, sorts of packing and others in our Infineon Internet
Page “Products”: http://www.infineon.com/products.
5.4.3 Flash Memory Parameters
The data retention time of the TC1782 / TC1182’s Flash memory depends on the
number of times the Flash memory has been erased and programmed.
Table 46 Exposed pad Dimensions
Ex 7.8 mm
Ey 7.8 mm
Exposed
DIPAD
TC1782 / TC1182
Electrical ParametersPackage and Reliability
Data Sheet 66 V 1.1, 2011-06
Table 47 FLASH32 Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Data Flash Erase Time
per Sector tERD CC −−3s
Program Flash Erase
Time per 256 KByte
Sector
tERP CC −−5s
Program time data flash
per page1) tPRD CC −−5.3 ms without
reprogramming
−−15.9 ms with two
reprogramming
cycles
Program time program
flash per page2) tPRP CC −−5.3 ms without
reprogramming
−−10.6 ms with one
reprogramming
cycle
Data Flash Endurance NE CC 60000
3) −−cycle
sMax. data
retention time 5
years
Erase suspend delay tFL_ErSusp
CC −−15 ms
Wait time after margin
change tFL_Margin
Del CC 10 −−μs
Program Flash Retention
Time, Physical Sector4)5) tRET CC 20 −−year
sMax. 1000
erase/program
cycles
Program Flash Retention
Time, Logical Sector4)5) tRETL CC 20 −−year
sMax. 100
erase/program
cycles
UCB Retention Time4)5) tRTU CC 20 −−year
sMax. 4
erase/program
cycles per UCB
Wake-Up time tWU CC −−270 μs
TC1782 / TC1182
Electrical ParametersPackage and Reliability
Data Sheet 67 V 1.1, 2011-06
5.4.4 Quality Declarations
DFlash wait state
configuration WSDF
CC 50 ns x
fFSI
−−
PFlash wait state
configuration WSPF
CC 26 ns x
fFSI
−−
1) In case the Program Verify feature detects weak bits, these bits will be programmed up to twice more. Each
reprogramming takes additional 5 ms.
2) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes additional 5 ms.
3) Only valid when a robust EEPROM emulation algorithm is used. For more details see the User´s Manual.
4) Storage and inactive time included.
5) At average weighted junction temperature Tj = 100°C, or the retention time at average weighted temperat ure
of Tj = 110°C is minimum 10 years, or the retention time at average weighted temperature of Tj = 150°C is
minimum 0.7 years.
Table 48 Quality Parameters
Parameter Symbol Values Unit Note / T est Condition
Min. Typ. Max.
Operation
Lifetime1)
1) This lifetime refers only to the t i me when the device is powered on.
tOP 24000 hours 2)
ESD susceptibility
according to
Human Body
Model (HBM)
VHBM 2000 V Conforming to
JESD22-A114-B
ESD susceptibility
of the LVDS pins VHBM1 ––500V
ESD susceptibility
according to
Charged Device
Model (CDM)
VCDM 500 V Conforming to
JESD22-C101-C
Moisture
Sensitivity Level MSL 3 Conforming to Jedec
J-STD-020C for 240°C
Table 47 FLASH32 Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TC1782 / TC1182
Electrical ParametersPackage and Reliability
Data Sheet 68 V 1.1, 2011-06
2) For worst-case temperature profile equivalent to:
1200 hours at Tj = 125...150oC
3600 hours at Tj = 110...125oC
7200 hours at Tj = 100...110oC
11000 hours at Tj = 25...100oC
1000 hours at Tj = -40...25oC
TC1782 / TC1182
History
Data Sheet 1 V 1.1, 2011-06
6History
The following changes where done between Version 0.7 and 0.8 of this document:
Change product name from SAK-TC1782-320F180HL to SAK-TC1782-320F180HR
Change product name from SAK-TC1782-256F133HL to SAK-TC1782-256F133HR
Change DFLASH size from 64Kbyte to 128Kbyte in chapter 1
Add ADC module abbreviation to table 1 Analog Input Port Function description
Change SCU_RTID and SCU_CHIPID values to match the step
Extend VDDOSC3 to -7.5 %
Add parameter HYSA1+
Add parameter HYSA2
Add parameter VILF /VIHF
Add parameter RDSONF
Changed typical value of CAINSW from 7 to 9 pF
Changed typical value of CAINTOT from 25 to 20 pF
Remove 3.3 V values from ADC section
Add parameter fADC
Changed max. value of fADCI from 20 to 18 MHz
Remove parameter IAIN7T (covered by RAIN7T )
Replace parameter IAREF by QCONV
Changed typical value of RAIN from 700 to 900 Ohm
Add parameter tS
Add footnote to max value of TUE
Add parameter fFADC
Add parameter tC
Add formula for DTS temperature calculation
Adapt current values to reduced limits of BA step
Add clarification to parameter ILVDS
Remove parameter RTHJA (not required)
Add clarification to parameter tPOH description
Add clarification to parameter tPOS description
Add min. value to parameters tL
Changed typical value of fPLLBASE_ERAY from 200 to 250 MHz
Add MSC t45 behavior for CMOS / LVDS usage
Add RTHs for non soldered exposed pad
Add table 33
Change DTS accuracy to 6°C of the complete temperature range
Remove limitations of the DFLASH and PFLASH operating in extended Range
operating conditions
Change package version von PG-LQFP-176-6 to PG-LQFP-176-12
The following changes where done between Version 0.8 and 1.0 of this document:
Change package version von PG-LQFP-176-12 to PG-LQFP-176-10
TC1782 / TC1182
History
Data Sheet 2 V 1.1, 2011-06
improve description in table 2 for analog channels
add class A1+ to type list of table 2
add clarification that table 7 defines the conditions for all other parame te rs
add note the spike filter is only available for the PORST pin
add Vil to Vih ratio for A1+ pad
remove irritating Note / Test Condi tions
adapt maximum power dissipation values
add conditions for MLI, MSC, SSC, parameters
changed definition for t13 and t14 of the MLI timing
changed definition for t45 of the MSC timing
add parameters dTxdly and dRxdly to ERAY parameters
correct ERAY parameters t60 and t63 values
correct footnotes for ERAY parameters
split flash parameters tPRD and tPRP in two conditions
add conditions to LVDS pad parameters
Changed VAREFx to VAREF0 and VAGNDx to VAGND0
remove Pin Reliability in Overload section
add parameters IIN and Sum IIN to absolute ratings
adjust thresholds in figure 28 (ERAY)
add parameter HYSX to PSC_XTAL
added RDSON values for all driver settings (weak, medium, and strong)
removed footnote 2 of table 6
change conditions for RDSON weak parameters
change load for timing of SSC, MSC, and MLI from CL=25pF to C
L= 50 pF (typical)
add type I to legend of table 2
add SAK-TC1782-320F180HL and SAK-TC1782-256F133HL
changed timing checkpoints in figure 23
add section 5.2.6.1
add to parameters tRF and tFF condition CL=50pF
add new footnote 7) to ADC parameter table
add min and max value for QCONV and adapt typ value
add load conditions for tFF1 and tRF1
add conditions to PLL parameter tL
change DAP parameter t19 from SR to CC classification
remove footnote 2 for the FADC
increase current for IDDP_POR from 2 to 2.5mA
add footnote 3 to table 9
change SAK-TC1782-320F180HR /SAK-TC1782-320F180HL to SAK-TC1782F-
320F180HR /SAK-TC1782F-320F180HL
change SAK-TC1782-256F133HR / SAK-TC1782-256F133HL to SAK-TC1782F-
256F133HR / SAK-TC1782F-256F133HL
add information for the following products:
SAK-TC1782N-320F180HR
TC1782 / TC1182
History
Data Sheet 3 V 1.1, 2011-06
SAK-TC1782N-320F180HL
SAK-TC1182N-320F180HR
SAK-TC1182N-320F180HL
SAK-TC1782N-256F133HR
SAK-TC1782N-256F133HL
SAK-TC1182N-256F133HR
SAK-TC1182N-156F133HL
The following changes where done between Version 1.0 and 1.1 of this document:
add section Pin Reliability in Overload
remove sentence ‘Exposure to conditions withi n the maximum rati ngs will not affect
device reliability. To replace this sentence section Pin Reliability in Overload was
added.
increase values for absolute maximum parameters IIN and SumIIN
remove capacitance conditions for LVDS pad parameters as loads are defined by
interface (MSC) timings
remove term typical from load of Peripheral Timings
add definition of driver strength settings for ERAY Interface Timing
change footnote 4 wording fo r ERAY timing back to TC1797 wording
increase flash parameters tPRD and tPRP values
rework the 3.3 V current part of the Power Supply Parameters for better description
and usag e
Parameters IDDP_FP, IDDFL3E and IDDFL3R are removed and replaced in the following
way
IDDP_FP is replaced by IDDP with the condition including flash programming current
IDDFL3E is replaced by IDDP with the condition including flash erase verify current
IDDFL3R is replaced by IDDP with the condition including flash read current
parameter IDDFL3R was renamed to IDDFL3
The rework of the 3.3 V current part of the Power Supply Parameters was done for
simplification and clarification. Former given value s could still be used if liked, the new
definition results in the same resulting values or slightly better values. The flash module
is supplied via IDDFL3 and IDDP. For the different flash operating modes in worst case
different allocations for the two domains resultin g.
The application typical case ‘flash read’ has max IDDP of 12 mA and max IDDFL3 of 56 mA
resulting is a sum of 68 mA.
The case ‘flash programming’ has max IDDP of 27 mA and max IDDFL3 of 21 mA resulting
is a sum of 48 mA.
The case ‘flash erase verify’ has max IDDP of 20 mA and max IDDFL3 of 56 mA resulting
is a sum of 76 mA.
So for the old parameter IDDP with 15 mA, the new version reads as
IDDP = 12+IDDP_PORST = 14.5 mA for the same application relevant case.
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