X28C010
1
5 Volt, Byte Alterable E2PROM
© Xicor, Inc. 1991, 1995, 1996 Patents Pending Characteristics subject to change without notice
3858-3.1 4/3/97 T1/C0/D0 SH
FEATURES
•Access Time: 120ns
•Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
•Low Power CMOS:
—Active: 50mA
—Standby: 500µA
•Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
•High Speed Page Write Capability
•Highly Reliable Direct Write™ Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
•Early End of Write Detection
—DATA Polling
—Toggle Bit Polling
DESCRIPTION
The Xicor X28C010 is a 128K x 8 E2PROM, fabricated
with Xicor's proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C010 is a 5V only device. The
X28C010 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard
EPROMs.
The X28C010 supports a 256-byte page write operation,
effectively providing a 19µs/byte write cycle and en-
abling the entire memory to be typically written in less
than 2.5 seconds. The X28C010 also features DATA
Polling and Toggle Bit Polling, system software support
schemes used to indicate the early completion of a write
cycle. In addition, the X28C010 supports Software Data
Protection option.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Data retention is
specified to be greater than 100 years.
1M X28C010 128K x 8 Bit
PIN CONFIGURATIONS
3858 FHD F02.1
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
X28C010
CERDIP
FLAT PACK
SOIC (R)
X28C010
(TOP VIEW)
A6
A5
A4
A3
A2
A1
A0
I/O0
A13
A8
A9
A11
A10
I/O7
A14
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
A12
A15
A16
NC
VCC
WE
NC
232
61
5
43
8
7
9
10
11
12
13 15 1716 18 19 20
22
23
24
25
26
27
28
29
31
OE
CE
A7
14 21
30
X28C010
(TOP VIEW)
A6
A5
A4
A3
A2
A1
A0
I/O0
A13
A8
A9
A11
A10
I/O7
A14
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
A12
A15
A16
NC
VCC
WE
NC
232
6
1
5
43
8
7
9
10
11
12
13
15 1716 18 19 20
22
23
24
25
26
27
28
29
31
OE
CE
A7
14
21
30
3858 FHD F03.1
PLCC
LCC
EXTENDED LCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
X28C010
3858 ILL F21
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
NC
NC
VSS
NC
NC
I/O2
I/O1
I/O0
A0
A1
A2
A3
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
A16
A15
A12
A7
A6
A5
A4
TSOP
X28C010
(BOTTOM VIEW)
14
A016
I/O118
VSS
11A3
9A5
7A7
15
I/O017
I/O219
I/O3
5A15 2NC 36
VCC
20
I/O4
21
I/O5
34
NC
23
I/O7
25
A10
27
A11
29
A8
22
I/O6
32
NC
24
CE
26
OE
28
A9
30
A13
13
A1
12
A2
10
A4
8A6
4A16 3NC 1NC 35
WE 33
NC
31
A14
6A12
PGA
3858 FHD F20
2
X28C010
PIN DESCRIPTIONS
Addresses (A0–A16)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28C010 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C010.
PIN NAMES
Symbol Description
A0–A16 Address Inputs
I/O0–I/O7Data Input/Output
WE Write Enable
CE Chip Enable
OE Output Enable
VCC +5V
VSS Ground
NC No Connect 3858 PGM T01
3858 FHD F01
FUNCTIONAL DIAGRAM
X BUFFERS
LA TCHES AND
DECODER
I/O BUFFERS
AND LATCHES
Y BUFFERS
LA TCHES AND
DECODER
CONTROL
LOGIC AND
TIMING
1M-BIT
E2PROM
ARRAY
I/O0–I/O7
DATA INPUTS/OUTPUTS
CE
OE
VCC
VSS
A8–A16
WE
A0–A7
X28C010
3
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C010 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE, which-
ever occurs last. Similarly, the data is latched internally by
the rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X28C010 allows the entire
memory to be written in 5 seconds. Page write allows
two to two hundred fifty-six bytes of data to be consecu-
tively written to the X28C010 prior to the commence-
ment of the internal programming cycle. The host can
fetch data from another device within the system during
a page write operation (change the source address), but
the page address (A8 through A16) for each subsequent
valid write cycle to the part during this operation must be
the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty six bytes
in the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to
LOW transition, must begin within 100µs of the falling
edge of the preceding WE. If a subsequent WE HIGH to
LOW transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
Write Operation Status Bits
The X28C010 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
DATA Polling (I/O7)
The X28C010 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X28C010,
eliminating additional interrupt inputs or external hard-
ware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the
complement of that data on I/O7 (i.e., write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O7 will reflect true data. Note: If the
X28C010 is in the protected state and an illegal write
operation is attempted DATA Polling will not operate.
Toggle Bit (I/O6)
The X28C010 also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle, I/O6 will toggle from
HIGH to LOW and LOW to HIGH on subsequent at-
tempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
Figure 1. Status Bit Assignment
5TBDP 43210I/O
RESERVED
TOGGLE BIT
DATA POLLING
3858 FHD F11
4
X28C010
DATA Polling I/O7
Figure 2. DATA Polling Bus Sequence
Figure 3. DATA Polling Software Flow
3858 FHD F12
DATA Polling can effectively halve the time for writing to
the X28C010. The timing diagram in Figure 2 illustrates
the sequence of events on the bus. The software flow
diagram in Figure 3 illustrates one method of implement-
ing the routine.
3858 FHD F13
WRITE DATA
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
I/O7
COMPARE?
X28C010
READY
NO
YES
WRITES
COMPLETE? NO
YES
CE
OE
WE
I/O7X28C010
READY
LAST
WRITE
HIGH Z VOL
VIH
A0–A14 An An An An An An
VOH
An
X28C010
5
The Toggle Bit I/O6
Figure 4. Toggle Bit Bus Sequence
Figure 5. Toggle Bit Software Flow
3858 FHD F14
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28C010 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on
the bus. The software flow diagram in Figure 5 illustrates
a method for polling the Toggle Bit.
3858 FHD F15
CE
OE
WE
I/O6X28C010
READY
VOH
VOL
LAST
WRITE
HIGH Z
* Beginning and ending state of I/O6 will vary.
**
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
X28C010
READY
COMPARE
OK?
NO
YES
LAST WRITE
6
X28C010
HARDWARE DATA PROTECTION
The X28C010 provides three hardware features that
protect nonvolatile data from inadvertent writes.
•Noise Protection—A WE pulse less than 10ns will not
initiate a write cycle.
•Default VCC Sense—All functions are inhibited when
VCC is ≤3.5V.
•Write inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle
during power-up and power-down, maintaining data
integrity.
SOFTWARE DATA PROTECTION
The X28C010 offers a software controlled data protec-
tion feature. The X28C010 is shipped from Xicor with the
software data protection NOT ENABLED: that is the
device will be in the standard operating mode. In this
mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the
device once VCC was stable.
The X28C010 can be automatically protected during
power-up and power-down without the need for external
circuits by employing the software data protection fea-
ture. The internal software data protection circuit is
enabled after the first write operation utilizing the soft-
ware algorithm. This circuit is nonvolatile and will remain
set for the life of the device unless the reset command
is issued.
Once the software protection is enabled, the X28C010
is also protected from inadvertent and accidental writes
in the powered-up state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific ad-
dresses. Refer to Figures 6 and 7 for the sequence. The
three byte sequence opens the page write window
enabling the host to write from one to two hundred fifty-
six bytes of data. Once the page load cycle has been
completed, the device will automatically be returned to
the data protected state.
X28C010
7
Software Data Protection
Figure 6. Timing Sequence—Byte or Page Write
Figure 7. Write Sequence for
Software Data Protection Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the X28C010
will automatically disable further writes unless another
command is issued to cancel it. If no further commands
are issued the X28C010 will be write protected during
power-down and after any subsequent power-up. The
state of A15 and A16 while executing the algorithm is
don’t care.
Note: Once initiated, the sequence of write operations
should not be interrupted.
3858 FHD F16
3858 FHD F17
CE
WE
(VCC)
WRITE
PROTECTED
VCC
0V
DATA
ADDR AA
5555 55
2AAA A0
5555
≤tBLC MAX
WRITES
OK
BYTE
OR
PAGE
tWC
WRITE LAST
BYTE TO
LAST ADDRESS
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA A0
TO ADDRESS
5555
WRITE DATA XX
TO ANY
ADDRESS
AFTER tWC
RE-ENTERS DATA
PROTECTED STATE
WRITE DATA AA
TO ADDRESS
5555
OPTIONAL
BYTE/PAGE
LOAD OPERATION
8
X28C010
Resetting Software Data Protection
Figure 8. Reset Software Data Protection Timing Sequence
CE
WE
STANDARD
OPERATING
MODE
VCC
DATA
ADDR AA
5555 55
2AAA 80
5555 ≥tWC
AA
5555 55
2AAA 20
5555
3858 FHD F18
Figure 9. Software Sequence to Deactivate
Software Data Protection In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E2PROM programmer, the following six step algo-
rithm will reset the internal protection circuit. After tWC,
the X28C010 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
3858 FHD F19
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 80
TO ADDRESS
5555
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 20
TO ADDRESS
5555
WRITE DATA AA
TO ADDRESS
5555
X28C010
9
SYSTEM CONSIDERATIONS
Because the X28C010 is frequently used in large memory
arrays it is provided with a two line control architecture
for both read and write operations. Proper usage can
provide the lowest possible power dissipation and elimi-
nate the possibility of contention where multiple I/O pins
share the same bus.
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
Because the X28C010 has two power modes, standby
and active, proper decoupling of the memory array is of
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the I/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high fre-
quency ceramic capacitor be used between VCC and
VSS at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for each
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
Active Supply Current vs. Ambient Temperature ICC (RD) by Temperature over Frequency
Standby Supply Current vs. Ambient Temperature
–55 –10 +125
0.15
0.2
0.25
0.3
AMBIENT TEMPERATURE (°C)
I
SB
(mA)
3858 ILL F25
0.05 +35 +80
V
CC
= 5V
0.1
–55 –10 +125
12
14
16
18
AMBIENT TEMPERATURE (°C)
I
CC
WR (mA)
3858 ILL F24
10 +35 +80
V
CC
= 5V
0315
30
40
50
5.0 V
CC
FREQUENCY (MHz)
I
CC
RD (mA)
3858 ILL F26
10 69
–55°C
+25°C
+125°C
12
20
60
10
X28C010
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias
X28C010...................................... –10°C to +85°C
X28C010I................................... –65°C to +135°C
X28C010M................................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS .......................................–1V to +7V
D.C. Output Current .............................................5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
RECOMMEND OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Military –55°C +125°C
3858 PGM T02
Supply Voltage Limits
X28C010 5V ±10%
3858 PGM T03
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol Parameter Min. Max. Units Test Conditions
ICC VCC Current (Active) 50 mA CE = OE = VIL, WE = VIH,
(TTL Inputs) All I/O’s = Open, Address Inputs =
.4V/2.4V Levels @ f = 5MHz
ISB1 VCC Current (Standby) 3 mA CE = VIH, OE = VIL
(TTL Inputs) All I/O’s = Open, Other Inputs = VIH
ISB2 VCC Current (Standby) 500 µACE = VCC – 0.3V, OE = VIL
(CMOS Inputs) All I/O’s = Open, Other Inputs = VCC
ILI Input Leakage Current 10 µAV
IN = VSS to VCC
ILO Output Leakage Current 10 µAV
OUT = VSS to VCC, CE = VIH
VlL(1) Input LOW Voltage –1 0.8 V
VIH(1) Input HIGH Voltage 2 VCC + 1 V
VOL Output LOW Voltage 0.4 V IOL = 2.1mA
VOH Output HIGH Voltage 2.4 V IOH = –400µA3858 PGM T04.2
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
X28C010
11
ENDURANCE AND DATA RETENTION
Parameter Min. Max. Units
Endurance 10,000 Cycles Per Byte
Endurance 100,000 Cycles Per Page
Data Retention 100 Years
3858 PGM T07.1
POWER-UP TIMING
Symbol Parameter Max. Units
tPUR(2) Power-up to Read Operation 100 µs
tPUW(2) Power-up to Write Operation 5 ms 3858 PGM T05
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol Parameter Max. Units Test Conditions
CI/O(2) Input/Output Capacitance 10 pF VI/O = 0V
CIN(2) Input Capacitance 10 pF VIN = 0V
3858 PGM T06
A.C. CONDITIONS OF TEST
Input Pulse Levels 0V to 3V
Input Rise and
Fall Times 10ns
Input and Output
Timing Levels 1.5V
3858 PGM T05.1
MODE SELECTION
CE OE WE Mode I/O Power
L L H Read DOUT Active
L H L Write DIN Active
H X X Standby and High Z Standby
Write Inhibit
X L X Write Inhibit — —
X X H Write Inhibit — —
3858 PGM T08
EQUIVALENT A.C. LOAD CIRCUIT
Note: (2) This parameter is periodically sampled and not 100%
tested.
WAVEFORM INPUTS OUTPUTS
Must be
steady Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
SYMBOL TABLE
3858 FHD F04.3
5V
1.92KΩ
100pF
OUTPUT
1.37KΩ
12
X28C010
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
X28C010-12 X28C010-15 X28C010-20 X28C010-25
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Units
tRC Read Cycle Time 120 150 200 250 ns
tCE Chip Enable Access Time 120 150 200 250 ns
tAA Address Access Time 120 150 200 250 ns
tOE Output Enable Access Time 50 50 50 50 ns
tLZ(3) CE LOW to Active Output 0 0 0 0 ns
tOLZ(3) OE LOW to Active Output 0 0 0 0 ns
tHZ(3) CE HIGH to High Z Output 50 50 50 50 ns
tOHZ(3) OE HIGH to High Z Output 50 50 50 50 ns
tOH Output Hold from 0 0 0 0 ns
Address Change 3858 PGM T09.1
Read Cycle
Note: (3) tLZ min.,tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL =
5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
3858 FHD F05
tCE
tRC
ADDRESS
CE
OE
WE
DATA VALID DATA VALID
tOE
tLZ
tOLZ
tOH
tAA
tHZ
tOHZ
DATA I/O
VIH
HIGH Z
3858 FHD F05
X28C010
13
Write Cycle Limits
Symbol Parameter Min. Max. Units
tWC(4) Write Cycle Time 10 ms
tAS Address Setup Time 0 ns
tAH Address Hold Time 50 ns
tCS Write Setup Time 0 ns
tCH Write Hold Time 0 ns
tCW CE Pulse Width 100 ns
tOES OE HIGH Setup Time 10 ns
tOEH OE HIGH Hold Time 10 ns
tWP WE Pulse Width 100 ns
tWPH WE HIGH Recovery 100 ns
tDV Data Valid 1 µs
tDS Data Setup 50 ns
tDH Data Hold 0 ns
tDW Delay to Next Write 10 µs
tBLC Byte Load Cycle 0.2 100 µs
3858 PGM T10.1
WE Controlled Write Cycle
Notes: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to complete internal write operation.
3858 FHD F06
ADDRESS
tAS
tWC
tAH
tOES
tDV
tDS tDH
tOEH
CE
WE
OE
DATA IN
DATA OUT HIGH Z
DATA VALID
tCS tCH
tWP
tWPH
3858 FHD F06
14
X28C010
CE Controlled Write Cycle
Page Write Cycle
Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively
performing a polling operation.
(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must
conform to either the CE or WE controlled write cycle timing.
3858 FHD F07
ADDRESS
tAS
tOEH
tWC
tAH
tOES tWPH
tCS
tDV
tDS tDH
tCH
CE
WE
OE
DATA IN
DATA OUT HIGH Z
tCW
DATA VALID
3858 FHD F07
3858 FHD F08
WE
OE (5)
LAST BYTE
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2
tWP
tWPH
tBLC
tWC
CE
ADDRESS * (6)
I/O
*For each successive write within the page write operation, A8–A16 should be the same or
writes to an unknown address could occur.
X28C010
15
DATA Polling Timing Diagram(7)
3858 FHD F09
Toggle Bit Timing Diagram
CE
OE
WE
I/O6
tOES
tDW
tWC
tOEH
HIGH Z *
*
* I/O6 beginning and ending state will vary.
3858 FHD F10
Note: (7) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
ADDRESS AN
3858 FHD F09
DIN=X DOUT=X DOUT=X
tWC
tOEH tOES
ANAN
CE
WE
OE
I/O7
tDW
16
X28C010
NOTES
X28C010
17
PACKAGING INFORMATION
0.620 (15.75)
0.590 (14.99)
TYP. 0.614 (15.60)
0.110 (2.79)
0.090 (2.29)
TYP. 0.018 (0.46)
1.690 (42.95)
MAX.
0.023 (0.58)
0.014 (0.36)
TYP. 0.018 (0.46)
0.232 (5.90) MAX.
0.060 (1.52)
0.015 (0.38)
3926 FHD F09
PIN 1
SEATING
PLANE
0.200 (5.08)
0.150 (3.18) 0.065 (1.65)
0.033 (0.84)
TYP. 0.055 (1.40)
0.610 (15.49)
0.500 (12.70)
0.100 (2.54) MAX.
0°
15°
32-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.005 (0.13) MIN.
0.150 (3.8)
MIN.
0.015 (0.33)
0.008 (0.20)
18
X28C010
PACKAGING INFORMATION
0.150 (3.81) BSC
0.300 (7.62)
BSC
0.458 (11.63)
––
0.458 (11.63)
0.442 (11.22)
PIN 1
0.400 (10.16)
BSC
0.560 (14.22)
0.540 (13.71)
3926 FHD F14
0.020 (0.51) x 45° REF.
0.095 (2.41)
0.075 (1.91)
0.022 (0.56)
0.006 (0.15)
0.055 (1.39)
0.045 (1.14)
TYP. (4) PLCS.
0.040 (1.02) x 45° REF.
TYP. (3) PLCS.
0.050 (1.27) BSC
0.028 (0.71)
0.022 (0.56)
(32) PLCS.
0.200 (5.08)
BSC
0.558 (14.17)
––
0.088 (2.24)
0.050 (1.27)
0.120 (3.05)
0.060 (1.52)
PIN 1 INDEX CORDER
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
X28C010
19
PACKAGING INFORMATION
3926 FHD F20
32-LEAD CERAMIC FLAT PACK
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.019 (0.48)
0.015 (0.38)
0.045 (1.14) MAX.
PIN 1 INDEX
132
0.130 (3.30)
0.090 (2.29)
0.047 (1.19)
0.026 (0.66)
0.0065 (0.17)
0.004 (0.10)
0.370 (9.40)
0.300 (7.62)
0.828 (21.04)
0.812 (20.64) 0.055 (1.40)
0.045 (1.14)
0.440 (11.18)
0.430 (10.93)
0.347 (8.82)
0.333 (8.46)
0.005 (0.13) MIN.
20
X28C010
PACKAGING INFORMATION
0.021 (0.53)
0.013 (0.33)
0.420 (10.67)
0.050 (1.27) TYP.
TYP. 0.017 (0.43)0.045 (1.14) x 45°
0.300 (7.62)
REF.
0.453 (11.51)
0.447 (11.35)
TYP. 0.450 (11.43)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
PIN 1
0.400
(10.16)REF.
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
3° TYP.
0.048 (1.22)
0.042 (1.07)
0.140 (3.56)
0.100 (2.45)
TYP. 0.136 (3.45)
0.095 (2.41)
0.060 (1.52)
—
0.015 (0.38)
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
3926 FHD F13
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
0.510"
TYPICAL
0.050"
TYPICAL
0.050"
TYPICAL
0.300"
REF
FOOTPRINT
0.400"
0.410"
0.030" TYPICAL
32 PLACES
X28C010
21
PACKAGING INFORMATION
3926 FHD F21
36-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K
15 17 19 21 22
14 16 18 20 23
10 9 27 28
8 7 29 30
5 2 36 34 32
4 3 1 35 33
TYP. 0.100 (2.54)
ALL LEADS
PIN 1 INDEX
0.050 (1.27)
0.008 (0.20)
NOTE: LEADS 5, 14, 23, & 32
12 11 25 26
13
6 31
24
A
A
TYP. 0.180 (.010)
(4.57 ± .25)
4 CORNERS
0.770 (19.56)
0.750 (19.05)
SQ
A
A
0.185 (4.70)
0.175 (4.45)
0.020 (0.51)
0.016 (0.41)
0.072 (1.83)
0.062 (1.57)
0.120 (3.05)
0.100 (2.54)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
TYP. 0.180 (.010)
(4.57 ± .25)
4 CORNERS
22
X28C010
PACKAGING INFORMATION
32-LEAD CERAMIC SMALL OUTLINE GULL WING PACKAGE TYPE R
3926 FHD F27
NOTES:
1. ALL DIMENSIONS IN INCHES
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
0.340
±0.007
SEE DETAIL “A”
FOR LEAD
INFORMATION
0.440 MAX.
0.560 NOM.
0.0192
0.0138
0.050
0.750
±0.005
0.840
MAX.
0.060 NOM.
0.020 MIN.
0.015 R TYP.
0.035 MIN.
0.015 R
TYP.
0.035 TYP.
0.165 TYP.
DETAIL “A”
0.560"
TYPICAL
0.050"
TYPICAL
0.050"
TYPICAL
FOOTPRINT 0.030" TYPICAL
32 PLACES
X28C010
23
PACKAGING INFORMATION
0.300 BSC
0.458 MAX.
0.450 ± 0.008
PIN 1
3926 FHD F35
0.035 x 45° REF.
0.085 ± 0.010
0.020 (1.02) x 45° REF.
TYP. (3) PLCS.
0.050 BSC
0.400 BSC
0.708 MAX.
0.060/0.120
PIN #1 INDEX CORNER
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
0.700 ± 0.010
0.005/0.015
0.025 ± 0.003
0.050 ± 0.005
0.006/0.022
DET AIL A
DETAIL A
32-PAD STRETCHED CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE N
24
X28C010
PACKAGING INFORMATION
3926 ILL F39.2
NOTE:
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
0.50 ± 0.04
(0.0197 ± 0.0016)
0.30 ± 0.05
(0.012 ± 0.002)
14.80 ± 0.05
(0.583 ± 0.002)
1.30 ± 0.05
(0.051 ± 0.002)
0.17 (0.007)
0.03 (0.001)
TYPICAL
40 PLACES 15 EQ. SPC. @ 0.50 ± 0.04
0.0197 ± 0.016 = 9.50 ± 0.06
(0.374 ± 0.0024) OVERALL
TOL. NON-CUMULATIVE
SOLDER PADS
FOOTPRINT
10.058 (0.396)
9.957 (0.392)
12.522 (0.493)
12.268 (0.483)
PIN #1 IDENT.
O 1.016 (0.040)
O 0.762 (0.030)
1
0.965
(0.038)
1.143 (0.045)
0.889 (0.035) 0.127 (0.005) DP.
0.076 (0.003) DP.
X
0.065 (0.0025)
14.148 (0.557)
13.894 (0.547)
SEATING
PLANE
A
0.178 (0.007)
1.016 (0.040)
SEATING
PLANE
15° TYP.
0.500 (0.0197)
1.219 (0.048)
0.254 (0.010)
0.152 (0.006)
0.432 (0.017)
0.813 (0.032) TYP.
0.432 (0.017)
0.508 (0.020) TYP.
0.152 (0.006)
TYP.
4° TYP.
DETAIL A
40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T
X28C010
25
ORDERING INFORMATION
Device Access Time
–12 = 120ns
–15 = 150ns
–20 = 200ns
–25 = 250ns
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883
Package
D = 32-Lead Cerdip
E = 32-Pad LCC
F = 32-Lead Flat Pack
J = 32-Lead PLCC
K = 36-Lead Pin Grid Array
R = 32-Lead Hermetic SOIC (Gull Wing)
N = 32-Lead Extended LCC
T = 40-Lead TSOP
X28C010 X X -X
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
