EiceDRIVERTM 2EDi product family Fast, robust, dual-channel, functional and rein forced isolated MOSFET gate-driver wi th accurate and stable ti ming Description The EiceDRIVERTM 2EDi is a family of fast dual-channel isolated MOSFET gate-driver ICs providing functional (2EDFx) or reinforced (2EDSx) input-to-output isolation by means of coreless transformer (CT) technology. Due to high driving current, excellent common-mode rejection and fast signal propagation, 2EDi is particularly well suited for driving medium- to high-voltage MOSFETs (CoolMOSTM, OptiMOSTM, CoolSICTM) in fast-switching power systems. Features * * * * * * * * * * 4 A / 8 A or 1 A / 2 A source / sink output current Up to 10 MHz PWM switching frequency PWM signal propagation delay typ. 37 ns with - 3 ns channel-to-channel mismatch - +7/-6 ns propagation delay variance Resistor-programmable Dead Time Control (DTC) ranging from 15 ns to 250 ns Common Mode Transient Immunity CMTI >150 V/ns Fast safety turn-off in case of input side Undervoltage Lockout (UVLO) Output supply voltage from 4.5 V to 20 V with 4 V or 8 V UVLO threshold Wide temperature operating range TJ = -40C to +150C RoHS compliant wide /narrow-body (WB/NB) DSO16 and 5 mm x 5 mm LGA packages Fully qualified according to JEDEC for Industrial Applications Isolation and safety certificates * * 2EDSx with reinforced isolation: - DIN V VDE V 0884-10 (2006-12) compliant with VIOTM = 8 kVpk and VIOSM = 6.25 kVpk (tested at 10kVpk) - certified according to UL1577 (Ed. 5) opto-coupler component isolation standard with VISO = 5700 VRMS - certified according to DIN EN 62368-1 and DIN EN 60950-1 and corresponding CQC certificates - certified according to EN 61010-1 (reinforced isolation, 300 Vrms mains voltage, overvoltage category III) 2EDFx with functional isolation: Production test with 1.5 kVDC for 10 ms VDD > 3.5V RVDDI VDD 8 CVDDI VBus VDDA VDDI (3.3V) SLDON Controller UVLO UVLO SLDO RX TX Rg1 OUTA Logic M1 Control Logic PWM2 INB 8 CVDDA GNDA Vsw Isolation 8 Input-to-Output INA PWM1 Channel-to-Channel Isolation Dboot VDDB Aux Power (12V) UVLO DISABLE GPIOx TX 8 RDTC DTC GND 3 GNDI RX OUTB Rg2 Logic M2 Dead Time Control GNDB CVDDB PGND Final datasheet www.infineon.com Please read the Important Notice and Warnings at the end of this document Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Potential Applications * Server, telecom and industrial SMPS * Synchronous rectification, brick converters, UPS and battery storage * EV charging industry automation, motor drives and power tools Final datasheet 2 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 1.1 1.2 1.3 1.4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EiceDRIVERTM 2EDi product family device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input-to-output isolation testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel-to-channel isolation testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application overview and system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 5 5 5 2 2.1 2.2 Pin configurations by device type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin configuration for dual-channel input mode with (with DISABLE, SLDON) . . . . . . . . . . . . . . . . . . . . . . 6 Pin configuration for dual-channel input mode (with DISABLE, SLDOP, DTC) . . . . . . . . . . . . . . . . . . . . . . 8 3 3.1 3.2 3.2.1 3.3 3.3.1 3.3.2 3.4 3.5 3.6 3.6.1 3.6.2 3.7 3.8 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input-to-output isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical applications by isolation type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input-side power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output-side power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input-side UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output-side UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data transmission input-side to output-side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dead Time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 11 11 11 11 12 12 13 13 13 13 13 4 4.1 4.2 4.3 4.4 4.5 4.5.1 4.5.1.1 4.5.1.2 4.5.2 4.5.3 Device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional and reinforced isolation specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional isolation specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional isolation of devices in PG-TFLGA-13-1 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional isolation of devices in NB PG-DSO-16-11 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reinforced isolation of devices in WB PG-DSO-16-30 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Safety-limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 15 16 16 20 20 20 21 22 24 5 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 7.1 7.2 7.3 7.4 Package outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device numbers and markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package PG-DSO-16-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package PG-DSO-16-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package PG-TFLGA-13-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 31 31 33 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Final datasheet 3 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Description 1 Description The gate drivers of the EiceDRIVERTM 2EDi product family are designed for fast-switching, medium to high power systems with MOSFET switches. They are optimized for high timing accuracy over temperature and production spread. The reliable accurate timing simplifies system design and provides better power conversion efficiency. The 2EDSx, 2EDFx dual-channel reinforced (safe) and functional isolated product variants are available with different drive strengths: 4 A/8 A for low-ohmic power MOSFETs, 1 A/2 A for higher Ron MOSFETs or slower switching transients (EMI). The 1 A/2 A reinforced isolation driver can also be used as a PWM Data Coupler in combination with a non-isolated boost gate driver such as 1EDNx 4 A/8 A placed in closest proximity to the Superjunction power switches. Two independent and galvanically isolated gate driver channels ensure that all 2EDi versions can be used in any possible configuration of low- and high-side switches. Improved system robustness is supported by min. 150 V/ns Common Mode Transient Immunity (CMTI), PWM inputs with 18 ns noise filter, UVLO on output side including a safety self-lock-down of driver outputs in case of input UVLO (VDDI < 3 V), PWM outputs with up to 5 A peak reverse current capability and an intrinsically robust gate driver design. 1.1 EiceDRIVERTM 2EDi product family device overview Table 1 EiceDRIVERTM 2EDi product family device overview Input-to-output isolation Part number1) Package 2EDF7275F 2EDF9275F 2EDF7175F 2EDF7275K 2EDF7235K 2EDS8265H 2EDS9265H 2EDS8165H NB-DSO16 10mm x 6mm LGA13 5mm x 5mm WB-DSO16 10.3mm x 10.3mm Source/ UVLO Isolation sink class current 4 A/8 A 1 A/ 2 A 4 A/8 A Rating DTC Safety 2) Surge testing certification 4V no 13 V no 4V Functional VIO = 1.5 kVDC n.a no n.a 4V no yes 4 A/8 A 1 A/2 A VIOTM = 8 kVpk (VDE0884-10 3)) VIOSM = 10 kVpk 8V (IEC60065) 13 V Reinforced VISO = 5.7 kVrms 8V (UL1577) VDE0884-10 3) UL1577 EN 60950-1, EN 62368-1, EN 61010-1 no no no 1) for device ordering information and device marking see Chapter 7.1, Table 31 2) CSA Component Acceptance Notice 5A IEC60950 planned and CQC per GB4943.1-2011 pending. For 2EDS9265H, all certifications are planned. 3) tested according to VDE0884-10 specifications with certification no longer available due to standard expiration The 2EDi product table is provided as a first quick device selection guide; more detailed specifications are provided in the product features, package dimension and testing chapters of this datasheet. Find current information on configurations and application notes under www.infineon.com/2EDi Final datasheet 4 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Description 1.2 * Input-to-output isolation testing 2EDSx Reinforced isolation (2EDSx in WB PG-DSO-16-30 package), for details see Table 26 to Table 29. - 8 kVpk transient isolation voltage applied according to DIN V VDE V 0884-10 (2006-12) - 10 kVpk surge isolation tested with 25 positive and 25 negative pulses according to VDE-0884-10 * Functional isolation (2EDFx in NB PG-DSO-16-11 and PG-TFLGA-13-1 packages), for details see Table 21 to Table 23 - Production test with 1.5 kVDC for 10 ms 1.3 * Channel-to-channel isolation testing The functional isolation between the two channels are verified by the following tests - sample test with 1.5 kVDC for 10 ms (NB PG-DSO-16-11, WB PG-DSO-16-30) - sample test with 0.65 kVDC for 10 ms (PG-TFLGA-13-1) 1.4 Application overview and system block diagram 2EDi gate drivers are perfectly suited to substitute bulky pulse transformers and drive power MOSFETs in halfbridge configuration as depicted in Figure 1. The input side is usually powered by the same power supply as the PWM controllers (VDDI = 3.3 V or VDDI > 3.5 V if SLDO is activated). The output-side gate driver voltages VDDA, VDDB are generated by separate isolated auxiliary supplies. In some topologies like LLC, the high side driver supply VDDA can be generated via a bootstrapping circuitry. For further application implementation guidance please refer to dedicated application notes. VDD > 3.5V RVDDI VDD 8 CVDDI VBus VDDA VDDI (3.3V) SLDON Controller UVLO UVLO SLDO RX TX Rg1 OUTA Logic M1 Control Logic PWM2 INB 8 CVDDA GNDA Vsw Isolation 8 Input-to-Output INA PWM1 Channel-to-Channel Isolation Dboot VDDB Aux Power (12V) UVLO DISABLE GPIOx TX 8 RDTC DTC GND 3 RX OUTB Rg2 Logic M2 Dead Time Control GNDB GNDI CVDDB PGND Figure 1 Typical application with 5 V controller and bootstrapped high-side VDDA Final datasheet 5 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Pin configurations by device type 2 Pin configurations by device type Functional behavior and electrical characteristics are independent of package configuration 2.1 Pin configuration for dual-channel input mode with (with DISABLE, SLDON) The pin configurations for the different package variants 2EDFxx75F, 2EDF7x75K and 2EDSxx65H are outlined in Figure 2. DSO-16 INA 1 16 VDDA INB 2 15 OUTA 14 GNDA 13 N.C. 12 N.C. 11 VDDB narrow-body 2EDF7275F 2EDF9275F 2EDF7175F VDDI 3 GNDI 4 DISABLE 5 N.C. 6 N.C. 7 10 OUTB SLDON 8 9 GNDB wide-body 2EDS8265H 2EDS9265H 2EDS8165H LGA-13 (5 x 5 mm) Figure 2 GNDI 1 13 VDDA INA 2 12 OUTA INB 3 11 GNDA SLDON 4 DISABLE 5 10 VDDB N.C. 6 9 OUTB VDDI 7 8 GNDB 2EDF7275K Pin configuration DSO-16 and LGA-13 packages (2EDF7x75F, 2EDF7x75K and 2EDF8x65H) (Top view, figure is not to scale) Final datasheet 6 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Pin configurations by device type For package drawing details see Chapter 7 Package outline dimensions. Table 2 Pin description for dual-channel input mode (with DISABLE, SLDON) Pin# Pin# Symbol DSO LGA Description 1 2 INA Digital CMOS / TTL logic signal input for channel A with internal pull-down resistor to GNDI If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4) 2 3 INB Digital CMOS / TTL logic signal input for channel B with internal pull-down resistor to GNDI If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4) 3 7 VDDI Supply voltage (input side) 3.3 V (Internal SLDO available) It is recommended to place a bypass capacitor from VDDI to GNDI (see Chapter 3.3.1) 4 1 GNDI Ground input side (all signals on input side are referenced to this pin) (see Chapter 3.3.1) 5 5 DISABLE Digital CMOS / TTL logic input for both channels A and B; logic input high disables both output channels Internal pull-down resistor (see Chapter 3.4) 6 6 N.C. Not connected; keep pin floating 7 - N.C. Not connected; keep pin floating 8 4 SLDON Default 3.3 V supply selected, if N.C. or connected to VDDI If SLDON pin is connected to GNDI, SLDO is activated and a supply voltage higher than 3.5 V can be used (see Chapter 3.3.1) Internal pull-up resistor to VDDI; hard-wired PCB connection recommended 9 8 GNDB Ground for output channel B 10 9 OUTB Output gate driver for channel B 11 10 VDDB Supply voltage for output channel B It is recommended to place a bypass capacitor from VDDB to GNDB (see Chapter 3.3.2) 12 N.P. N.C. 13 - 14 Not present; not connected; for channel-to-channel isolation N.C. Not connected; for channel-to-channel isolation 11 GNDA Ground for output channel A 15 12 OUTA Output gate driver for channel A 16 13 VDDA Supply voltage for output channel A It is recommended to place a bypass capacitor from VDDA to GNDA (see Chapter 3.3.2) Final datasheet 7 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Pin configurations by device type 2.2 Pin configuration for dual-channel input mode (with DISABLE, SLDOP, DTC) The pin configuration for the LGA-version with Dead Time Control (2EDF7235K) is outlined in Figure 3 LGA-13 (5 x 5 mm) Figure 3 GNDI 1 13 VDDA INA 2 12 OUTA INB 3 11 GNDA SLDOP 4 DISABLE 5 10 VDDB DTC 6 9 OUTB VDDI 7 8 GNDB 2EDF7235K Pin configuration dual-channel input mode (with DISABLE, SLDOP, DTC) for 2EDF7235K (Top view, Figure is not to scale) Final datasheet 8 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Pin configurations by device type For package drawing details see Chapter 7 Package outline dimensions. Table 3 Pin description for dual-channel input mode (with DISABLE, SLDOP, DTC) Pin# Symbol LGA Description 2 INA Digital CMOS / TTL logic signal input for channel A with internal pull-down resistor to GNDI If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4) 3 INB Digital CMOS / TTL logic signal input for channel B with internal pull-down resistor to GNDI If channel is not used it is recommended to connect pin to GNDI (see Chapter 3.4) 7 VDDI Supply voltage (input side) 3.3 V (Internal SLDO available) It is recommended to place a bypass capacitor from VDDI to GNDI (see Chapter 3.3.1) 1 GNDI Ground input side (all signals on input side are referenced to this pin) (see Chapter 3.3.1) 5 DISABLE Digital CMOS / TTL logic input for both channels A and B Logic input high disables both output channels Internal pull-down resistor (see Chapter 3.4) 6 DTC Dead time control Programmable from 15 ns to 350 ns via resistor to GNDI see Chapter 3.8 Dead Time Control Internal pull-up resistor; no connection or connection to VDDI disables DTC functionality 4 SLDOP Default mode: supply voltage > 3.5V (with external shunt resistor), if pin N.C. or connected to VDDI If SLDOP pin is connected to GNDI SLDO Operation is deactivated, for use with 3.3 V supply on VDDI(see Chapter 3.3.1) Internal pull-up resistor to VDDI; hard-wired PCB connection recommended 8 GNDB Ground for output channel B 9 OUTB Output gate driver for channel B 10 VDDB Supply voltage for output channel B It is recommended to place a bypass capacitor from VDDB to GNDB (see Chapter 3.3.2) N.P. Not present; for channel-to-channel isolation creepage requirements 11 GNDA Ground for output channel A 12 OUTA Output gate driver for channel A 13 VDDA Supply voltage for output channel A It is recommended to place a bypass capacitor from VDDA to GNDA (see Chapter 3.3.2) - Final datasheet 9 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Functional description 3 Functional description 3.1 Block diagram A simplified functional block diagram for the the EiceDRIVERTM 2EDi gate-driver family is given in Figure 4. UVLO VDDI SLDO Tx Logic INA Control Logic INB DISABLE ENABLE Tx NC DTC VDDA Rx Input-to-Output Isolation SLDON SLDOP UVLO OUTA GNDA Channel-to-Channel Isolation UVLO VDDB Rx Logic Dead Time Control GNDI OUTB GNDB Figure 4 EiceDRIVERTM 2EDi product family block diagram 3.2 Input-to-output isolation All EiceDRIVERTM 2EDi dual-channel isolated products are tested in accordance with their respective isolation class. * * 2EDFx for functional isolation, typically used as primary-side controlled galvanically isolated driver. Device part numbers: 2EDFxxxxK (2EDF7275K, 2EDF7235K) and 2EDFxxxxF (2EDF7275F, 2EDF9275F, 2EDF7175F) 2EDSx for reinforced safe isolation, typically used as secondary-side controlled isolated gate driver. Device part numbers: 2EDSxxxxH (2EDS8165H, 2EDS9265H, 2EDS8265H) In combination with the different package dimensions and material characteristics, e.g. WB DSO-16 wide-body (PG-DSO-16-30), NB DSO-16 narrow-body (PG-DSO-16-11) or LGA - 13 at 5mm x 5mm (PG-TFLGA-13-1) the maximum input-to-output and channel-to-channel creepage and clearance distances and the possible working voltages of the IC as a semiconductor component are defined (see Table 18 to Table 29) Note: The achievable system isolation depends on PCB design, materials, manufacturing- and working environment. It is the customer's obligation to verify that the outlined semiconductor component isolation of the 2EDSx, 2EDFx device fits to application, manufacturing, working environment and end system saftey requirement standards. Final datasheet 10 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Functional description 3.2.1 Typical applications by isolation type Isolated gate drivers are typically deployed in the following applications. Table 4 Isolation type Potential applications * Functional Reinforced 3.3 * * High-power hard-switching high-voltage PFC, Vienna Rectifier, Totem Pole PFC or Synchronous Rectification Driving switches with Kelvin source connection (4-pin package) Secondary-side control in low voltage isolated DC/DC topologies and brick converters * * * Secondary-side control of high voltage SJ-MOSFETs in LLC or PS-ZVS Primary-side controlled synchronous rectification 1 A / 2 A PWM data- / signal-coupler for local boost gate drivers Supply voltages Three different power domains with independent internal power management are utilized to supply the input chip and the two output drivers. An undervoltage lockout functionality (UVLO) in each domain enables a defined startup and ensures a robust operation under all conditions. 3.3.1 Input-side power supply The input side is powered via VDDI with nominal 3.3 V. For using the device with a supply voltage > 3.5 V the onchip switched low-dropout regulator (SLDO) must be activated and an external shunt resistor RVDDI has to be connected to VDDI. It is recommended to use a ceramic bypass capacitor (10 nF - 22 nF) between VDDI and GNDI. The SLDO is activated, if the pin SLDON is connected to GNDI. In devices with the inverted pin SLDOP (e.g. 2EDF7235K) the SLDO is active by default and will be deactivated if connected to GNDI. A hard-wired connection is recommended. The SLDO regulates the current through an external resistor RVDDI connected between the external supply voltage VDD and pin VDDI as depicted in Figure 1 to generate the required voltage drop. For proper operation it has to be ensured that the current through RVDDI always exceeds the maximum supply current IVDD of the input chip (see Figure 8). Thus, RVDDI has to fulfill: RVDDI < (VDD - 3.3) / IVDD, max A typical choice for VDD = 12 V is RVDDI = 3 k, resulting in sufficient margin between resistor current and VDDI operating current. Dynamic current peaks are eliminated by a blocking cap (10 to 22 nF) between VDDI and GNDI. The total power consumption of 2EDi is dominated by the output side and depends on switching frequency, gate resistor and gate charge, while for typical switching frequencies the input supply current stays relatively constant (see Figure 7 to Figure 8) 3.3.2 Output-side power supply Each gate driver channel has to be powered separately. It is recommended to use a ceramic bypass capacitor (minimum value 20 x Ciss of MOSFET) from VDDA to GNDA and from VDDB to GNDB in close proximity to the device. The operating supply voltage can range from 4.5 V to 20 V for each gate drive channel. The minimum gate driver turn-on voltage is set by the device Undervoltage Lockout (UVLO) to protect the power MOSFETs from operating in the saturation region. Devices with 4 V, 8 V and 13 V UVLO thresholds for the output supply are currently available (see Chapter 1.1.) Final datasheet 11 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Functional description 3.4 Input configurations The inputs INA and INB control two independent PWM channels. The input signal is transferred non-inverted to the corresponding gate driver outputs OUTA and OUTB. All inputs are compatible with LV-TTL threshold levels and provide a hysteresis of typ. 0.8 V. The hysteresis is independent of the supply voltage VDDI. The PWM inputs are internally pulled down to a logic low voltage level (GNDI). In case the PWM-controller signals have an undefined state during the power-up sequence, the gate driver outputs are forced to the "off"-state (low). If the DISABLE input is "high", this unconditionally drives both channel outputs to "low" regardless of the state of INA or INB. Table 5 Logic table Inputs DISABLE INA INB UVLO input side1) x x x active x x x L x L Gate Drive Output UVLO output side1) OUTA OUTB x L L x ch A/B active L L L inactive ch A activ, ch B inactive L L x H inactive ch A active, ch B inactive L H L L x inactive ch A inactive, ch B active L L L H x inactive ch A inactive, ch B active H L H x x inactive ch A/B inactive L L L L L inactive ch A/B inactive L L L L H inactive ch A/B inactive L H L H H inactive ch A/B inactive H H 1) "inactive" means that VDD is above UVLO threshold voltage (normal operation) "active" means that UVLO disables the gate driver output stages 3.5 Driver outputs The two rail-to-rail output stages, realized with complementary PMOS, NMOS transistors, are able to provide the necessary sourcing and sinking current and shoot-through protection and active current limitation have been implemented with a very low on-resistance (see Table 15). The use of a p-channel sourcing transistor PMOS is crucial for achieving true rail-to-rail behavior without any source follower voltage drop. Gate Drive Outputs OUTA, OUTB are held actively low in case of floating inputs or during startup or power down as long as the UVLO thresholds are not exceeded. Final datasheet 12 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Functional description 3.6 Undervoltage Lockout 3.6.1 Input-side UVLO During startup (rise of the input-side supply), as long as VDDI is below UVLO, no data is transferred to the output side. All gate driver outputs are held low (Safety Lock-down at startup). When VDDI exceeds the UVLO level, the PWM input signal is transferred to the output side. If the output side is ready (not in UVLO condition), the output reacts according to the logic input. At any time, if the VDDI voltage drops below the UVLO threshold, an immediate "switch-to-low" command is sent to all output channels. The gate driver outputs are held low (Safety Lock-down is active at missing VDDI supply). 3.6.2 Output-side UVLO The Undervoltage Lockout function (UVLO) ensures that the output can be switched to its high level only if the gate driver supply voltage exceeds the UVLO threshold voltage. Thus it can be guaranteed, that the power switch transistors always stay within their Safe Operating Area (SOA). Otherwise a too low driving voltage could cause the power MOSFET to enter its saturation (ohmic) region with potentially destructive power dissipation. The UVLO of each channel VDDA/VDDB is controlled independently. There is no feedback to the input side. 3.7 Data transmission input-side to output-side Coreless Transformer (CT) based communication modules situated on the input die are used for signal transfer between input and output devices. A proven high-resolution pulse repetition scheme in the transmitter combined with a watchdog time-out at the receiver side enables recovery from communication fails and ensures safe system shutdown in failure cases. 3.8 Dead Time Control Dead Time Control function (DTC) increases the propagation delay of the rising output voltage by a time tDT. This feature is used in half-bridge applications to prevent the switches from a shoot-through current due to overlapping or jitter on the PWM signals. If the DTC feature is available, it can be enabled by connecting a resistor from DTC to GND. If this pin is not connected or set to VDDI, DTC is disabled. Recommended DTC resistor (RDTC) values are between 4.7 k and 150 k . RDTC is related to tDT by the formula: RDTC [k] = (tDT[ns] - 3) / 1.8 The resistor values and dead time delays are shown in Table 17 and Figure 15. Final datasheet 13 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Device characteristics 4 Device characteristics The absolute maximum ratings are listed in Table 6. Stresses beyond these values may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4.1 Absolute maximum ratings Table 6 Absolute maximum ratings Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Input supply voltage VDDI -0.3 - 4.0 V SLDO inactive (N.C. or connected to VDDI) Output supply voltage VDDO -0.3 - 22 V - Voltage at pins PWM and DISABLE VIN -0.3 - 17 V - -5 - - V < 50 ns for transient 1) Voltage at pins DTC and TEST/SLDO VDTC / VTEST/SLDO -0.3 - VDDI + 0.3 V - VOUTA/B -0.3 - VDDO + 0.3 V - -2 - VDDO+ 1.5 V < 200 ns 1) ISRC_rev -5 - - Apk < 500 ns 1) ISNK_rev - - 5 Apk CMTI 400 - - Junction temperature TJ -40 - 150 C - Storage temperature TSTG -65 - 150 C - Soldering temperature TSOL - - 260 C reflow / wave soldering 2) ESD capability VESD_CDM - - 0.5 kV Charged Device Model (CDM) 3) ESD capability VESD_HBM - - 2 kV Human Body Model (HBM) 4) Voltage at pins OUTA, OUTB Reverse current peak at pins OUTA, OUTB Non-destructive Common Mode Transient Immunity 1) 2) 3) 4) V/ns input to each output channel parameter verified by design, not tested in production according to JESD22A111 according to JESD22-002 according to JESD22-A114-B (discharging 100 pF capacitor through 1.5 k resistor) Final datasheet 14 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Device characteristics 4.2 Thermal characteristics Table 7 Thermal characteristics at Tamb= 25C Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition PG-TFLGA-13-1 Thermal resistance junctionambient 1) RthJA25 - 112 - K/W - Thermal resistance junction-case (top) 2) RthJC25 - 44 - K/W - Thermal resistance junction-board 3) RthJB25 - 66 - K/W - Characterization parameter junction-top 4) thJT25 - 7.7 - K/W - Characterization parameter junction-board 4) thJB25 - 5.6 - K/W - Thermal resistance junctionambient 1) RthJA25 - 51 - K/W - Thermal resistance junction-case (top) 2) RthJC25 - 25 - K/W - Thermal resistance junction-board 3) RthJB25 - 36 - K/W - Characterization parameter junction-top 4) thJT25 - 4.4 - K/W - Characterization parameter junction-board 4) thJB25 - 5.4 - K/W - Thermal resistance junctionambient 1) RthJA25 - 59 - K/W - Thermal resistance junction-case (top) 2) RthJC25 - 32 - K/W - Thermal resistance junction-board 3) RthJB25 - 33 - K/W - Characterization parameter junction-top 4) thJT25 - 8.9 - K/W - Characterization parameter junction-board 4) thJB25 - 7.7 - K/W - PG-DSO-16-11 PG-DSO-16-30 1) obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 2) obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 3) obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. 4) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7). Final datasheet 15 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Device characteristics 4.3 Operating range Table 8 Operating range Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. VDDI 3.0 - 3.5 V Min. defined by UVLO VDDA / VDDB 4.5 - 20 V Min. defined by UVLO Logic input voltage at pins INA, INB, DISABLE VIN 0 - 15 V - Voltage at pins DTC and SLDO VDTC / 0 - 3.5 V - Junction temperature TJ -40 - 150 C 1) Ambient temperature Tamb -40 - 125 C - Input supply voltage Output supply voltage VTEST/SLDO 1) continuous operation above 125C may reduce lifetime. 4.4 Electrical characteristics Unless otherwise noted, min./max. values of characteristics are the lower and upper limits, respectively. They are valid within the full operating range. The supply voltage is VDDA, VDDB= 12 V and VDDI= 3.3 V. Typical values are given at TJ = 25C. Table 9 Power supply (see Figure 7, Figure 8 and Figure 9) Parameter Symbol IVDDI quiescent current IVDDA , IVDDB quiescent current Table 10 Values Unit Note or Test Condition Min. Typ. Max. IVDDIqu1 - 1.4 - mA no switching IVDDAqu2 / IVDDBqu2 - 0.6 - mA Outx = low, no switching (4 V, 8 V UVLO options) - 0.7 - mA Outx = low, no switching, VDDA/B= 15 V > UVLO_ CMon (13 V UVLO options) Undervoltage Lockout VDDI (See Figure 11) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Undervoltage Lockout (UVLO) turn-on threshold VDDI UVLOon 2.75 2.85 2.95 V - Undervoltage Lockout (UVLO) turn-off threshold VVDDI UVLOoff - 2.70 - V - UVLO threshold hysteresis VDDI UVLOhys 0.1 0.15 0.2 V - Final datasheet 16 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Device characteristics Table 11 Undervoltage Lockout VDDA, VDDB 13 V-versions for SiC MOSFETs (see Figure 13) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Undervoltage Lockout (UVLO) turn-on threshold VDDA, VDDB UVLO_ CMon 13.0 13.7 14.2 V - Undervoltage Lockout (UVLO) turn-off threshold VDDA , VDDB UVLO_ CMoff - 12.9 - V - UVLO threshold hysteresis VDDA, VDDB UVLO_ CMhys 0.4 0.8 1.2 V - Table 12 Undervoltage Lockout VDDA, VDDB 8 V-versions for standard MOSFETs (see Figure 12) Parameter Symbol Values Unit Min. Typ. Max. Note or Test Condition Undervoltage Lockout (UVLO) turn-on threshold VDDA, VDDB UVLO_ CMon 7.6 8.0 8.4 V - Undervoltage Lockout (UVLO) turn-off threshold VDDA , VDDB UVLO_ CMoff - 7.0 - V - UVLO threshold hysteresis VDDA, VDDB UVLO_ CMhys 0.7 1 1.3 V - Table 13 Undervoltage Lockout VDDA, VDDB 4 V-versions for logic-level MOSFETs (see Figure 12) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Undervoltage Lockout (UVLO) turn on threshold VDDA , VDDB UVLO_ CMon 4.0 4.2 4.4 V - Undervoltage Lockout (UVLO) turn off threshold VDDA, VDDB UVLO_ CMoff - 3.9 - V - UVLO threshold hysteresis VDDA , VDDB UVLO_ CMhys 0.2 0.3 0.4 V - Table 14 Logic inputs INA, INB and DISABLE (see Figure 11) Parameter Symbol Values Unit Min. Typ. Max. Note or Test Condition Input voltage threshold for transition LH VINH 1.7 2.0 2.3 V - Input voltage threshold for transition HL VINL - 1.2 - V - VIN_hys 0.4 0.8 1.2 V - RIN - 150 - k - Input voltage threshold hysteresis Input pull-down resistor Final datasheet 17 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Device characteristics Table 15 Static output characteristics 4 A/8 A devices (see Figure 10) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition High-level (Sourcing) Output Resistance Ron_SRC 0.42 0.85 1.6 ISNK = 50 mA Peak Sourcing Output Current ISRC_pk - 4 1) A - Low-level (Sinking) Output Resistance Ron_SNK 0.18 0.35 0.75 ISRC = 50 mA ISNK_pk 2) -8 - A - Peak Sinking Output Current 1) actively limited by design at approx. 5.2 Apk, parameter is not subject to production test - verified by design / characterization 2) actively limited by design at approx. -10.2 Apk, parameter is not subject to production test - verified by design / characterization Table 16 Static output characteristics 1 A / 2 A devices (see Figure 10) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. High-level (Sourcing) Output Resistance Ron_SRC 1.4 3.1 5.8 ISNK = 50 mA Peak Sourcing Output Current ISRC_pk - 1 1) A - Low-level (Sinking) Output Resistance Ron_SNK 0.6 1.2 2.5 ISRC = 50 mA Peak Sinking Output Current ISNK_pk 2) -2 - A - 1) actively limited by design at approx. 1.3 Apk, parameter is not subject to production test - verified by design / characterization 2) actively limited by design at approx. -2.6 Apk, parameter is not subject to production test - verified by design / characterization Table 17 Dynamic characteristics (see Figure 5 and Figure 14) TJ,max = 125C, CLOAD = 1.8 nF for 4 A / 8 A version, CLOAD = 0.47 nF for 1 A / 2 A version Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. INA- /INB-to-output turn-on / turn-off propagation delay tPDon, tPDoff 31 37 44 ns 4 A/8 A version INA- /INB-to-output turn-on propagation delay tPDon 31 37 44 ns 1 A/2 A version INA- /INB-to-output turn-off propagation delay tPDoff 29 35 44 ns 1 A/2 A version DISABLE-to-output turn-on/ -off propagation delay tPDDISoff, tPDDISoff - - 100 ns - Output turn-on propagation delay mismatch between channels tPDon - - 3 ns INA, INB shorted trise - 6.5 121) ns - Rise time Final datasheet 18 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Device characteristics Table 17 Dynamic characteristics (see Figure 5 and Figure 14) (cont'd) TJ,max = 125C, CLOAD = 1.8 nF for 4 A / 8 A version, CLOAD = 0.47 nF for 1 A / 2 A version Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Fall time tfall - 4.5 81) ns - Minimum input pulse width that changes output state tPW - 18 - ns - Programmable dead time tDT - 115 - ns with RDTC = 62 k 1) parameter verified by design, not tested in production Final datasheet 19 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Device characteristics 4.5 Functional and reinforced isolation specifications Each individual part number and package variant has its own safety isolation characteristic due to package dimension and respective isolation test voltages and methods applied. The table heading references each unique part number. For reinforced safety, the regulatory tests described in the component and system standards are applied by Infineon. For functional isolation, the outlined in-house test methods have been applied. As soon as the regulatory certificates are available, the reference and or documents will become available for public download on the Infineon website www.infineon.com/2EDi Note: Final creepage and clearance of component, must be verified in conjunction with PCB design layout and manufacturing choice like PCB material (CTI), stubs, graves, lacquer which might increase or reduce safety distances. Meeting the isolation requirements on system level is therefore the responsibility of the application owner. 4.5.1 Functional isolation specifications 4.5.1.1 Functional isolation of devices in PG-TFLGA-13-1 package The PG-TFLGA-13-1 package is available for 2EDF7275K and 2EDF7235K. The isolation related parameters are shown in Table 18, Table 19 and Table 20; for a component with basic or reinforced safety approval, choose a different part number (e.g. Chapter 4.5.2: 2EDS8265H, 2EDS9265H and 2EDS8165H) Table 18 Functional isolation input-to-output (PG-TFLGA-13-1) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. VIO 1500 - - VDC Impulse test >10 ms, production tested Maximum isolation working voltage VIOWM 460 - - VRMS according to IEC 60664-1 (PD 2; MG II) Package clearance CLR - 3.4 - mm Shortest distance over air, from any input pin to any output pin Package creepage CPG - 3.4 - mm Shortest distance over surface, from any input pin to any output pin Common Mode Transient Immunity CMTI 150 - - V/ns according to DIN V VDE V0884-10, static and dynamic test Capacitance input-to-output CIO - 2 - pF 1) Resistance input-to-output RIO - >1000 - M 1) Functional isolation test voltage 1) parameter verified by design, not tested in production Final datasheet 20 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Device characteristics Table 19 Package characteristics (PG-TFLGA-13-1) Parameter Symbol Comparative Tracking Index of package mold Material group Table 20 Unit Note or Test Condition Min. Typ. Max. CTI 400 - 600 V according to DIN EN 60112 (VDE 0303-11) - - II - - according to IEC 60112 Functional isolation channel-to-channel (PG-TFLGA-13-1) Parameter Symbol Functional isolation test voltage Package creepage 4.5.1.2 Values Values VCh2Ch-DC- Unit Note or Test Condition Min. Typ. Max. 650 - - VDC Impulse Test > 10 ms; sample tested - 1.0 - mm Shortest distance over surface, from output pin Ch1-GND to output pin Ch2-VDD Test CPG Functional isolation of devices in NB PG-DSO-16-11 package The PG-DSO-16-11 package is available for 2EDF7175F, 2EDF9275Fand 2EDF7275F. The isolation related parameters are shown in Table 21, Table 22 and Table 23 Table 21 Input-to-output isolation specification (NB PG-DSO-16-11) Parameter Symbol Values Min. Functional isolation test voltage Unit Note or Test Condition Typ. Max. VIO 1500 - - VDC Impulse test > 10 ms, sample tested Maximum isolation working voltage VIOWM 510 - - VRMS according to IEC 60664-1 (PD2; MG II) Package clearance CLR - - mm Shortest distance over air, from any input pin to any output pin Package creepage CPG mm Shortest distance over surface, from any input pin to any output pin Common Mode Transient Immunity CMTI 150 - - V/ns according to DIN V VDE V0884-10, static and dynamic test Capacitance input-to-output CIO - 2 - pF 1) Resistance input-to-output RIO - >1000 - M 1) 4.0 - 4.0 - 1) parameter verified by design, not tested in production Final datasheet 21 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Device characteristics Table 22 Package characteristics (NB PG-DSO-16-11) Parameter Symbol Comparative Tracking Index of package mold Material group Table 23 Unit Note or Test Condition Min. Typ. Max. CTI 400 - 600 V according to DIN EN 60112 (VDE 0303-11) - - II - - according to IEC 60112 Channel-to-channel isolation (NB PG-DSO-16-11) Parameter Symbol Functional isolation test voltage Package Creepage 4.5.2 Values VCh2Ch-DC- Values Unit Note or Test Condition Min. Typ. Max. 1500 - - VDC Impulse Test >10 ms; sample tested - 2.5 - mm Shortest distance over surface, from Output pin Ch1-GND to output pin Ch2-VDD Test CPG Reinforced isolation of devices in WB PG-DSO-16-30 package The PG-DSO-16-30 package is available for 2EDS8265H, 2EDS9265H and 2EDS8165H. The safety related certifications are listed in Table 24, Table 25 and the isolation related parameters are shown in Table 26 to Table 30 Table 24 Component safety-related certificates for WB PG-DSO-16-301) Certification Issuing certification body Certification status 2) DIN V VDE V 0884-10 VDE Certified UL 1577 UL Certified Certification number 40043864 E311313 1) certifications planned for 2EDS9265H 2) certification no longer available due to standard expiration Table 25 Sistem safety-related certifications for WB PG-DSO-16-30 1) Certification Issuing certification body Certification status Certification number DIN EN 62368-1 (VDE 0868-1), DIN 60950-1 (VDE 0805-1) VDE Certified 40050289 EN 61010-1 VDE Certified 40051533 EN 60601-1 VDE Certification pending - GB 4943.1-2011 CQC Certification pending - CSA C22.2 No. 62368-1 CSA Certification planned - 1) certifications planned for 2EDS9265H Final datasheet 22 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Device characteristics Table 26 Input-to-output isolation specification according to DIN V, VDE0884-10 (2016-06)1) in WB PG-DSO-16-30 Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Maximum transient isolation voltage VIOTM 8000 - - Vpk qualification for t = 60 s; production test with VIOTM > 10 kVpk for t =1 s Maximum repetitive peak isolation voltage VIORM 1420 - - Vpk Time Dependent Dielectric Breakdown test method Maximum isolation working voltage VIOWM 1420 - - VDC 1000 - - VRMS Partial discharge voltage VPD 4500 - - Vpk Test sequence: 10.2 kVpk for t = 1 s followed by partial discharge 4.5 kVpk > 1.875 x VIOWM , QPD < 5 pC; production test Maximum surge isolation voltage VIOSM 6250 - - Vpk VIOSM_test = 1.6 x VIOSM >10 kVpk; sample tested 2) Package clearance CLR - 8.0 - mm from any input pin to any output pin Package creepage CPG - 8.0 - mm from any input pin to any output pin - I - IV Rated mains voltage 150 VRMS I - III 300 VRMS I - II 600 VRMS Overvoltage category per IEC 60664-1 table F.1 Capacitance input-to-output CIO - 2 - pF - Resistance input-to-output RIO - >1000 - M - CMTI 150 - - V/ns input to each output channel; static & dynamic; sample test Common Mode Transient Immunity 1) VDE encompasses former VDE0884-10, IEC60747-5-5 (opto-coupler standard) 2) Surge pulse tests applied according to IEC60065-10.1 (Ed 8.0 2014), 61000-4-5, 60060-1; waveforms (1.2 s slope, 50 s decay) Table 27 Reinforced isolation package characteristics (in WB PG-DSO-16-30) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. CTI 400 - 600 V according to DIN EN 60112 (VDE 0303-11) Material group - - II - - according to IEC 60112 Pollution degree - - 2 - - - Climatic category - - 40/125/ 21 - - - Comparative Tracking Index of package mold Final datasheet 23 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Device characteristics Table 28 Reinforced input-to-output isolation according to UL1577 Ed 5 (in WB PG-DSO-16-30) Parameter Symbol Withstand isolation voltage VISO Values Unit Note or Test Condition Min. Typ. Max. 5700 - - VRMS VISO= 5700 VRMS for t = 60 s (qualification); VISO > 1.2 x VRMS = 6840 V for t=1s Table 29 Functional isolation channel-to-channel (in WB PG-DSO-16-30) Parameter Symbol Functional isolation test voltage VCh2Ch-DC- Values Unit Note or Test Condition Min. Typ. Max. 1500 - - VDC Impulse Test >10 ms; sample tested 2.4 2.5 2.7 mm Shortest distance over surface, from Output pin Ch1-GND to output pin Ch2-VDD test Package creepage CPG 4.5.3 Safety-limiting values Table 30 Reinforced isolation safety-limiting values as outlined in VDE-0884-10 (WB PG-DSO-16-30) Parameter Safety supply power Safety supply currents Safety temperature Side Values Unit Note or Test Condition Min. Typ. Max. Input chip - - 20.0 mW Output A - - 1050 mW Output B - - 1050 mW Total - - 2120 mW Output A - - 87.5 mA Output B - - 87.5 mA Output A - - 53.5 mA Output B - - 53.5 mA RthJA = 59 K/W, VDDA/VDDB = 20 V, Tamb = 25C, TJ = 150C Ts - - 150 C Ts = TJ,max RthJA = 59 K/W1), Tamb = 25C, TJ = 150C RthJA = 59 K/W1), VDDA/VDDB = 12 V, Tamb = 25C, TJ = 150C 1) calculated with the Rth of WB PG-DSO-16-30 package (see Table 7) According to VDE0884-10 and UL1577, safety-limiting values define the operating conditions under which the isolation barrier can be guaranteed to stay unaffected. This corresponds with the maximum allowed junction temperature, as temperature-induced failures might cause significant overheating and eventually damage the isolation barrier. Final datasheet 24 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Timing diagrams 5 Timing diagrams Figure 5 depicts rise, fall and delay times for 2EDi 4 A/8 A. Besides, the effect of an activated dead time control (resistor connected to pin DTC) is indicated. VINH VINL INA/B 90% 90% OUTA/B tPDon Figure 5 10% 10% tPDoff tdt trise tfall Propagation delays, rise, fall and dead time Figure 6 illustrates the Undervoltage Lockout function for the output supplies. UVLOon UVLOoff VDDA/B - GNDA/B OUTA/B - GNDA/B Figure 6 Output UVLO behavior (output state high) Final datasheet 25 Timing_diag.fm Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Typical characteristics 6 Typical characteristics VDDA = VDDB = 12 V, VDDI = 3.3 V, Tamb = 25C, 2EDF7235K (PG-TFLGA-13-1) and no load unless otherwise noted. 6.0 1.6 100kHz 1MHz 5.0 3MHz 4.0 IVDDI [mA] IVDDI [mA] 1.4 3.0 2.0 1.2 1.0 0 1.0 -50 0 50 TJ[C] 100 -50 150 Typical VDDI quiescent current vs. temperature Figure 7 50 TJ[C] 100 150 Typical VDDI current vs. temperature and frequency Supply current VDDI 1.0 1.0 OUT High OUT Low OUT High OUT Low 0.9 0.8 IVDDA/B [mA] IVDDA/B [mA] 0 0.8 0.7 0.6 0.6 0.5 0.4 0.4 -50 0 50 TJ[C] 100 0 150 Typical VDDA/B quiescent currents vs. temperature Figure 8 5 10 15 20 VDDA/B [V] Typical VDDA/B quiescent currents vs. supply voltage 25 Supply current VDDA, VDDB Final datasheet 26 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Typical characteristics 14 50 50kHz Duty Cycle 50% CLoad = 1.8nF 1MHz 12 VDD 4.5V VDD 12V VDD 20V 40 3MHz IVDDA/B [mA] IVDDA/B [mA] 10 8 6 30 20 4 10 2 0 0 -50 Figure 9 0 50 100 0 150 400 600 800 1000 TJ[C] frequency [kHz] Typical VDDA/B current vs. temperature and frequency, no load Typical VDDA/B current consumption with capacitive load vs frequency Supply current VDDA, VDDB (with / without load) 6 2.0 Ron_src Ron_snk 1.8 1.6 Ron_src Ron_snk 5 1.4 4 1.2 Ron [] Ron [] 200 1.0 3 0.8 2 0.6 0.4 1 0.2 0 0 -50 0 50 100 -50 150 TJ[C] Typical output resistance vs. temperature (4A/8A version) Figure 10 0 50 100 150 TJ[C] Typical output resistance vs. temperature (1A/2A version) Output resistance Final datasheet 27 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Typical characteristics 2.5 UVLO on UVLO off ON threshold OFF threshold 2.9 VDD [V] VVIN [V] 2.0 1.5 2.7 1.0 2.5 0.5 -50 0 50 TJ[C] 100 -50 150 50 100 150 TJ[C] Typical input voltage thresholds vs. temperature Figure 11 0 Typical Undervoltage Lockout threshold VDDI vs. temperature Logic input thresholds and VDDI UVLO 4.5 8.8 UVLO on UVLO off UVLO on UVLO off 8.4 4.3 VDD [V] VDD [V] 8.0 4.1 7.6 7.2 3.9 6.8 6.4 3.7 -50 Figure 12 -50 0 50 100 150 TJ[C] Typical Undervoltage Lockout threshold VDDA/B vs. temperature (4V-versions) 0 50 100 150 TJ[C] Typical Undervoltage Lockout threshold VDDA/B vs. temperature (8V-versions) VDDA/B UVLO (4 V and 8 V) Final datasheet 28 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Typical characteristics 14.0 UVLO on UVLO off VDD [V] 13.6 13.2 12.8 12.4 -50 0 50 Tj [C] 100 150 Typical Under Voltage Lockout threshold VDDA/B vs. temperature (13V-version) Figure 13 VDDA/B UVLO (13 V) 8 45 turn-on turn-off 40 trise/fall [ns] tPDon,off [ns] 7 6 5 35 4 VDD=12V Cload=1.8n 3 30 -50 -50 0 50 100 50 100 150 TJ[C] TJ[C] Typical rise and fall time vs. temperature Typical propagation delay vs. temperature Figure 14 0 150 Propagation delay and rise / fall time Final datasheet 29 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Typical characteristics 300 250 tDTC [ns] 200 150 100 50 0 0 Figure 15 50 100 RDTC [k] 200 Dead time control: rising edge delay vs RDTC 2500 Safety limiting power per channel [mW] 100 Safety limiting current per output [mA] 150 I_VDDA, VDDB for VDD=12 V I_VDDA, VDDB for VDD=20 V 75 50 25 VDDI = 3.3 V (Current in each channel with both channels running simultaneously) 2000 1500 1000 500 VDDI = 3.3 V (Current in each channel with both channels running simultaneously) 0 0 -50 0 50 100 -50 150 Tamb [C] 50 100 150 Tamb [C] Thermal derating for safetyrelated limiting current Figure 16 0 Thermal derating for safetyrelated limiting power Thermal derating curves Final datasheet 30 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Package outline dimensions 7 Package outline dimensions The following package versions are available. * an NB PG-DSO-16-11 package with typ. 4 mm creepage input to output * an area optimized 5 x 5 mm2 PG-TFLGA-13-1 * a WB PG-DSO-16-30 package with typ. 8 mm creepage input to output Note: For further information on package types, recommendation for board assembly, please go to: www.infineon.com/2EDi 7.1 Device numbers and markings Table 31 Device numbers and markings Orderable part number (OPN) Device marking 2EDF7275F 2EDF7275FXUMA2 2F7275B 2EDF9275F 2EDF9275FXUMA1 2F9275B 2EDF7175F 2EDF7175FXUMA2 2F7175B 2EDF7275K 2EDF7275KXUMA2 2F7275B 2EDF7235K 2EDF7235KXUMA1 2F7235A 2EDS8265H 2EDS8265HXUMA2 2S8265B 2EDS9265H 2EDS9265HXUMA1 2S9265B 2EDS8165H 2EDS8165HXUMA2 2S8165B 0.25 GAUGE PLANE +0.17 8 M AX. 0.33-0.08 x 45 +0.05 D 1) 0.0 4-0.2 0.2-0.01 1) 0.0 10-0.2 1.75 MAX. Package PG-DSO-16-11 0.1 MIN. STAND OFF 7.2 Part number 0.64 0.25 0.1 C 16x C SEATING COPLANARITY PLANE 60.2 +0.08 0.41-0.06 0.25 D C 16x 16 9 1 8 INDEX MARKING BOTTOM VIEW 9 16 8 1 1.27 1) DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF 0.25 MAX. PER SIDE ALL DIMENSIONS ARE IN UNITS MM THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [ ] Figure 17 PG-DSO-16-11 outline Final datasheet 31 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Package outline dimensions Figure 18 PG-DSO-16-11 footprint 3,1 ,1'(; 0$5.,1* $// ',0(16,216 $5( ,1 81,76 00 7+( '5$:,1* ,6 ,1 &203/,$1&( :,7+ ,62 352-(&7,21 0(7+2' > Figure 19 @ PG-DSO-16-11 packaging Final datasheet 32 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Package outline dimensions 0$; [ r ' [ r r $% & [ *$8*( 3/$1( Package PG-DSO-16-30 s 67$1' 2)) 7.3 s & & [ 6($7,1* &23/$1$5,7< 3/$1( 723 9,(: s & $% ' [ %27720 9,(: $ ' & [ (-(&725 0$5. )/$7 6+$3( ,1'(;0$5.,1* %$// 6+$3( % '2(6 127 ,1&/8'( 3/$67,& 25 0(7$/ 3527586,21 2) 0$; 3(5 6,'( '2(6 127 ,1&/8'( '$0%$5 3527586,21 2) 0$; $// ',0(16,216 $5( ,1 81,76 00 7+( '5$:,1* ,6 ,1 &203/,$1&( :,7+ ,62 352-(&7,21 0(7+2' > @ Figure 20 PG-DSO-16-30 outline Figure 21 PG-DSO-16-30 footprint Final datasheet 33 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Package outline dimensions 16 0.3 10.8 24 4 11 PIN 1 INDEX MARKING 2.7 3.2 All dimensions are in units mm The drawing is in compliance with ISO 128-30, Projection Method 1 [ Figure 22 PG-DSO-16-30 packaging 7.4 Package PG-TFLGA-13-1 Figure 23 PG-TFLGA-13-1 outline Final datasheet 34 ] Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Package outline dimensions Figure 24 PG-TFLGA-13-1 footprint Figure 25 PG-TFLGA-13-1 packaging Final datasheet 35 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Revision history Page or Item Subjects (major changes since previous revision) Rev. 2.5 Datasheet, 2020-03-17 Page 1 "certified according to DIN V VDE V0884-10" changed in "DIN V VDE V0884-10 compliant" due to standard expiration on 2019.12.31 Whole document added references to 2EDF9275F and 2EDS9265H (13 V UVLO options for SiC MOSFETs driving) Page 1, Table 1 added reference to EN 61010-1 certification Page 1 update of term DIN EN 62368-1 and DIN EN 60950-1 Table 1 CQC removed from Table 1 due to presence of footnote 2) Table 1 added footnote 3) due to expiration of VDE0884-10 certification Table 1, Table 31 added 2EDF9275F and 2EDS9265H products Table 1 removed OPN for better readability; OPN shown in Table 31 Table 13 VIN max. value 6.5 V 15 V Table 9 added IVDDA, IVDDBquiescient current for 2EDF9275F and 2EDS9265H Table 11 added VDDA, VDDB Undervoltage Lockout table for 2EDF9275F and 2EDS9265H Table 13 added "UVLO threshold vs temperature" for the 13 V UVLO options (2EDF9275F, 2EDS9265H) Table 24, Table 25 added tables for overview on safety-related certifications of PG-DSO-16-30 Table 26 "see VDE certificate" footnote removed due to certification expiration Table 28 fixed typo in the test condition: 5700 kVRMS 5700 VRMS Table 31 new OPN and "B" marking: improved secondary-side clamping performance Rev 2.4 Datasheet, 2019-02-08 Table 6 max. VDDI: 3.7 V 4.0 V Rev. 2.3 Datasheet, 2019-01-31 Whole document removed "certification pending" because certification has been issued (see Table 1) Chapter 7 latest footprints, outlines and packaging for PG-DSO-16-11 and PG-DSO-16-30 Figure 7 adjusted values Page 1 propagation delay variance in "Features" updated Table 1 and Table 31 OPN inserted for 2EDF7235K Table 6 reference to max. value VDDO for voltage at pins OUTA and OUTB Table 6 removed footnote 1 from parameter "Non-destructive Common Mode Transient Immunity" Table 8 Tamb max. value 85C 125C Table 17 CLOAD in "Note or test condition" moved to table description Table 18, Table 21 and Table 26 Non-destructive Common Mode Transient Immunity transferred to Table 6, Absolute maximum ratings Table 18 Final datasheet added footnote to "Capacitance" and "Resistance" parameters 36 Rev. 2.5 2020-03-17 EiceDRIVERTM 2EDi product family 2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers Page or Item Subjects (major changes since previous revision) Table 21 footnotes assignation patched Rev. 2.2 Datasheet, 2018-11-07 Chapter 3.2 Update device part numbers Chapter 4 Update of term "DIN V, VDE V0884-10" Page 1 Update product validation in "Features" Table 1, Table 31 Update of OPN Table 6 Removed typos Rev. 2.1 Datasheet, 2018-10-24 Table 1, Table 6, Table 31 Updates Rev. 2.0 Datasheet, 2018-06-04 Initial data sheet available Final datasheet 37 Rev. 2.5 2020-03-17 Please read the Important Notice and Warnings at the end of this document Trademarks of Infineon Technologies AG All referenced product or service names and trademarks are the property of their respective owners. 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