LM8327 LM8327 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface Literature Number: SNLS329 LM8327 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface 1.0 General Description The LM8327 GenI/O-Expander and Keypad Controller is a dedicated device to unburden a host processor from scanning a matrix-addressed keypad and to provide flexible and general purpose, host-programmable input/output functions. Three independent PWM timer outputs are provided for dynamic LED brightness modulation. It communicates with a host processor through an I2C-compatible ACCESS.bus serial interface. It can communicate in Standard (100 kHz) and Fast-Mode (400 kHz) in slave Mode only. All available input/output pins can alternately be used as a direct key input connection, an input or an output in a keypad matrix, or as a host-programmable general purpose input or output. Any pin programmed as an input can also sense hardware interrupts. The interrupt polarity ("high-to-low" or "low-to-high" transition) is thereby programmable. The LM8327 follows a predefined register based set of commands. Upon startup (power on) a configuration file must be sent from the host to setup the hardware of the device. 2.0 Applications: Cordless Phones Smart Handheld Devices Keyboard Applications 3.0 LM8327 Function Blocks 30124201 (c) 2011 National Semiconductor Corporation 301242 www.national.com LM8327 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface September 14, 2011 LM8327 4.0 Features * 4.1 KEY FEATURES * Internal RC oscillator, no external clock required * Internal PWM clock generation, no external clock required * Programmable I2C-compatible ACCESS.bus address (Default 0x8A) * Support for Keypad matrices of up to of 8 x 12 keys, plus 8 special function (SF) keys, for a full 104 key support * Support for up to 26 direct connect keys * I2C-compatible ACCESS.bus slave interface at 100 kHz (Standard-Mode) and 400 kHz (Fast-Mode) * Three host-programmable PWM outputs for smooth LED brightness modulation * Supports general-purpose I/O expansion on pins not otherwise used for keypad or PWM output * 15-byte Key event buffer * Multiple Key event storage * Key events, errors, and dedicated hardware interrupts request host service by asserting an IRQ output * Automatic HALT Mode for low power operation * Wake-up from HALT mode on any interface (rising edge, falling edge or pulse) * www.national.com Three PWM outputs with dedicated script buffer for up to 32 commands Register-based command interpreter with auto-increment address 4.2 HOST-CONTROLLED FEATURES * PWM scripting for three PWM outputs * Period of inactivity that triggers entry into HALT mode * Debounce time for reliable key event polling * Configuration of general purpose I/O ports * Various initialization options (keypad size, etc.) 4.3 KEY DEVICE FEATURES * 1.8V 10% single-supply operation * On-chip power-on reset (POR) * ESD glitch filter on RESETN pin * Watchdog timer * Dedicated slow clock input for 32 kHz up to 8MHz * -40C to +85C temperature range * 36-pin MICRO ARRAY package 2 LM8327 5.0 Pin Assignments 30124202 FIGURE 1. LM8327 Pinout - Top View 3 www.national.com LM8327 Table of Contents 1.0 General Description ......................................................................................................................... 1 2.0 Applications: ................................................................................................................................... 1 3.0 LM8327 Function Blocks .................................................................................................................. 1 4.0 Features ........................................................................................................................................ 2 4.1 KEY FEATURES ...................................................................................................................... 2 4.2 HOST-CONTROLLED FEATURES ............................................................................................. 2 4.3 KEY DEVICE FEATURES ......................................................................................................... 2 5.0 Pin Assignments ............................................................................................................................. 3 6.0 Ordering Information ........................................................................................................................ 7 7.0 Signal Descriptions .......................................................................................................................... 7 7.1 DEVICE PIN FUNCTIONS ........................................................................................................ 7 7.2 PIN CONFIGURATION AFTER RESET ...................................................................................... 9 8.0 Typical Application Setup ............................................................................................................... 10 8.1 FEATURES ........................................................................................................................... 10 8.1.1 Hardware .................................................................................................................... 10 8.1.2 Communication Layer ................................................................................................... 10 9.0 Halt Mode .................................................................................................................................... 11 9.1 HALT MODE DESCRIPTION ................................................................................................... 11 9.2 ACCESS.BUS ACTIVITY ........................................................................................................ 11 10.0 LM8327 Programming Interface ..................................................................................................... 12 10.1 ACCESS.BUS COMMUNICATION ......................................................................................... 12 10.1.1 Starting a Communication Cycle ................................................................................... 12 10.1.2 Communication Initialized from Host (Restart from Sleep Mode) ....................................... 13 10.1.3 ACCESS.Bus Communication Flow .............................................................................. 13 10.1.4 Auto Increment ........................................................................................................... 13 10.1.5 Reserved Registers and Bits ........................................................................................ 13 10.1.6 Global Call Reset ........................................................................................................ 13 11.0 Keyscan Operation ...................................................................................................................... 15 11.1 KEYSCAN INITIALIZATION ................................................................................................... 15 11.2 KEYSCAN INITIALIZATION EXAMPLE ................................................................................... 16 11.3 KEYSCAN PROCESS ........................................................................................................... 17 11.4 READING KEYSCAN STATUS BY THE HOST ........................................................................ 18 11.5 MULTIPLE KEY PRESSES ................................................................................................... 19 12.0 Direct Key Operation .................................................................................................................... 20 12.1 DIRECT KEY INITIALIZATION ............................................................................................... 20 12.2 DIRECT KEY INITIALIZATION EXAMPLE ............................................................................... 21 13.0 PWM Timer ................................................................................................................................ 22 13.1 OVERVIEW OF PWM FEATURES ......................................................................................... 22 13.2 OVERVIEW ON PWM SCRIPT COMMANDS ........................................................................... 22 13.2.1 RAMP COMMAND ..................................................................................................... 22 13.2.2 SET_PWM COMMAND ............................................................................................... 22 13.2.3 GO_TO_START COMMAND ....................................................................................... 23 13.2.4 BRANCH COMMAND ................................................................................................. 23 13.2.5 TRIGGER COMMAND ................................................................................................ 23 13.2.6 END COMMAND ........................................................................................................ 23 14.0 LM8327 Register Set ................................................................................................................... 25 14.1 KEYBOARD REGISTERS AND KEYBOARD CONTROL ........................................................... 25 14.1.1 KBDSETTLE - Keypad Settle Time Register ................................................................... 25 14.1.2 KBDBOUNCE - Debounce Time Register ...................................................................... 25 14.1.3 KBDSIZE - Set Keypad Size Register ............................................................................ 25 14.1.4 KBDDEDCFG - Dedicated Key Register ........................................................................ 26 14.1.5 KBDRIS - Keyboard Raw Interrupt Status Register .......................................................... 26 14.1.6 KBDMIS - Keypad Masked Interrupt Status Register ....................................................... 27 14.1.7 KBDIC - Keypad Interrupt Clear Register ....................................................................... 27 14.1.8 KBDMSK - Keypad Interrupt Mask Register .................................................................... 28 14.1.9 KBDCODE0 - Keyboard Code Register 0 ....................................................................... 28 14.1.10 KBDCODE1 - Keyboard Code Register 1 ..................................................................... 28 14.1.11 KBDCODE2 - Keyboard Code Register 2 ..................................................................... 29 14.1.12 KBDCODE3 - Keyboard Code Register 3 ..................................................................... 29 14.1.13 EVTCODE - Key Event Code Register ......................................................................... 29 14.2 PWM TIMER CONTROL REGISTERS .................................................................................... 29 14.2.1 TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers .............................................. 29 14.2.2 PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers ................................. 30 14.2.3 TIMSCALx - PWM Timer 0, 1 and 2 Prescale Registers ................................................... 30 www.national.com 4 5 31 31 32 33 33 34 35 35 35 35 35 35 36 36 37 37 37 38 38 39 39 39 40 40 41 42 42 43 43 43 44 44 44 45 46 47 47 47 48 48 48 48 48 49 49 49 49 50 50 50 50 51 51 51 52 51 52 52 52 53 53 53 53 53 54 54 www.national.com LM8327 14.2.4 TIMSWRES - PWM Timer Software Reset Registers ....................................................... 14.2.5 TIMRIS - PWM Timer Interrupt Status Register ............................................................... 14.2.6 TIMMIS - PWM Timer Masked Interrupt Status Register .................................................. 14.2.7 TIMIC - PWM Timer Interrupt Clear Register .................................................................. 14.2.8 PWMWP - PWM Timer Pattern Pointer Register ............................................................. 14.2.9 PWMCFG - PWM Script Register (Two Byte) ................................................................. 14.3 INTERFACE CONTROL REGISTERS ..................................................................................... 14.3.1 I2CSA - I2C-Compatible ACCESS.bus Slave Address Register ......................................... 14.3.2 MFGCODE - Manufacturer Code Register ..................................................................... 14.3.3 SWREV - Software Revision Register ............................................................................ 14.3.4 SWRESET - Software Reset ........................................................................................ 14.3.5 RSTCTRL - System Reset Register .............................................................................. 14.3.6 RSTINTCLR - Clear NO Init/Power-On Interrupt Register ................................................. 14.3.7 CLKMODE - Clock Mode Register ................................................................................ 14.3.8 CLKCFG - Clock Configuration Register ........................................................................ 14.3.9 CLKEN - Clock Enable Register ................................................................................... 14.3.10 AUTOSLP - Autosleep Enable Register ....................................................................... 14.3.11 AUTOSLPTI - Auto Sleep Time Register ...................................................................... 14.3.12 IRQST - Global Interrupt Status Register ...................................................................... 14.4 GPIO FEATURE CONFIGURATION ....................................................................................... 14.4.1 GPIO Feature Mapping ............................................................................................... 14.4.2 IOCGF - Input/Output Pin Mapping Configuration Register ............................................... 14.4.3 IOPC0 - Pull Resistor Configuration Register 0 ............................................................... 14.4.4 IOPC1 - Pull Resistor Configuration Register 1 ............................................................... 14.4.5 IOPC2 - Pull Resistor Configuration Register 2 ............................................................... 14.4.6 GPIOOME0 - GPIO Open Drain Mode Enable Register 0 ................................................. 14.4.7 GPIOOMS0 - GPIO Open Drain Mode Select Register 0 .................................................. 14.4.8 GPIOOME1 - GPIO Open Drain Mode Enable Register 1 ................................................. 14.4.9 GPIOOMS1 - GPIO Open Drain Mode Select Register 1 .................................................. 14.4.10 GPIOOME2 - GPIO Open Drain Mode Enable Register 2 ............................................... 14.4.11 GPIOOMS2 - GPIO Open Drain Mode Select Register 2 ................................................ 14.5 GPIO DATA INPUT/OUTPUT ................................................................................................. 14.5.1 GPIOPDATA0 - GPIO Data Register 0 .......................................................................... 14.5.2 GPIOPDATA1 - GPIO Data Register 1 .......................................................................... 14.5.3 GPIOPDATA2 - GPIO Data Register 2 .......................................................................... 14.5.4 GPIOPDIR0 - GPIO Port Direction Register 0 ................................................................. 14.5.5 GPIOPDIR1 - GPIO Port Direction Register 1 ................................................................. 14.5.6 GPIOPDIR2 - GPIO Port Direction Register 2 ................................................................. 14.6 GPIO INTERRUPT CONTROL ............................................................................................... 14.6.1 GPIOIS0 - Interrupt Sense Configuration Register 0 ........................................................ 14.6.2 GPIOIS1 - Interrupt Sense Configuration Register 1 ........................................................ 14.6.3 GPIOIS2 - Interrupt Sense Configuration Register 2 ........................................................ 14.6.4 GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0 ............................................... 14.6.5 GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1 ............................................... 14.6.6 GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2 ............................................... 14.6.7 GPIOIEV0 - GPIO Interrupt Edge Select Register 0 ......................................................... 14.6.8 GPIOIEV1 - GPIO Interrupt Edge Select Register 1 ......................................................... 14.6.9 GPIOIEV2 - GPIO Interrupt Edge Select Register 2 ......................................................... 14.6.10 GPIOIE0 - GPIO Interrupt Enable Register 0 ................................................................ 14.6.11 GPIOIE1 - GPIO Interrupt Enable Register 1 ................................................................ 14.6.12 GPIOIE2 - GPIO Interrupt Enable Register 2 ................................................................ 14.6.13 GPIOIC0 - GPIO Clear Interrupt Register 0 .................................................................. 14.6.14 GPIOIC1 - GPIO Clear Interrupt Register 1 .................................................................. 14.6.15 GPIOIC2 - GPIO Clear Interrupt Register 2 .................................................................. 14.7 GPIO INTERRUPT STATUS .................................................................................................. 14.7.1 GPIORIS0 - Raw Interrupt Status Register 0 .................................................................. 14.7.2 GPIORIS1 - Raw Interrupt Status Register 1 .................................................................. 14.7.3 GPIORIS2 - Raw Interrupt Status Register 2 .................................................................. 14.7.4 GPIOMIS0 - Masked Interrupt Status Register 0 ............................................................. 14.7.5 GPIOMIS1 - Masked Interrupt Status Register 1 ............................................................. 14.7.6 GPIOMIS2 - Masked Interrupt Status Register 2 ............................................................. 14.8 GPIO WAKE-UP CONTROL .................................................................................................. 14.8.1 GPIOWAKE0 - GPIO Wake-Up Register 0 ..................................................................... 14.8.2 GPIOWAKE1 - GPIO Wake-Up Register 1 ..................................................................... 14.8.3 GPIOWAKE2 - GPIO Wake-Up Register 2 ..................................................................... 14.9 DIRECT KEY REGISTERS AND DIRECT KEY CONTROL ........................................................ LM8327 14.9.1 DEVTCODE - Direct Key Event Code Register ............................................................... 14.9.2 DBOUNCE - Direct Key Debounce Time Register ........................................................... 14.9.3 DIRECT0 - Direct Key Register 0 .................................................................................. 14.9.4 DIRECT1 - Direct Key Register 1 .................................................................................. 14.9.5 DIRECT2 - Direct Key Register 2 .................................................................................. 14.9.6 DIRECT3 - Direct Key Register 3 .................................................................................. 14.9.7 DKBDRIS - Direct Key Raw Interrupt Status Register ...................................................... 14.9.8 DKBDMIS - Direct Key Masked Interrupt Status Register ................................................. 14.9.9 DKBDIC - Direct Key Interrupt Clear Register ................................................................. 14.9.10 DKBDMSK - Direct Key Interrupt Mask Register ............................................................ 15.0 Absolute Maximum Ratings ........................................................................................................... 16.0 Electrical Characteristics ............................................................................................................... 17.0 Registers .................................................................................................................................... 17.1 REGISTER MAPPING .......................................................................................................... 17.1.1 Keyboard Registers .................................................................................................... 17.1.2 Direct Key Registers ................................................................................................... 17.1.3 PWM Timer Registers ................................................................................................. 17.1.4 System Registers ....................................................................................................... 17.1.5 Global Interrupt Registers ............................................................................................ 17.1.6 GPIO Registers .......................................................................................................... 18.0 Physical Dimensions .................................................................................................................... www.national.com 6 54 55 55 55 55 56 56 56 57 57 58 58 61 61 61 61 62 63 63 63 69 LM8327 6.0 Ordering Information NSID Spec Package Type Package Method LM8327JGR8 NOPB MICRO ARRAY 1000 pieces tape & reel LM8327JGR8X NOPB MICRO ARRAY 3500 pieces tape & reel 7.0 Signal Descriptions 7.1 DEVICE PIN FUNCTIONS TABLE 1. KEY AND ALTERNATE FUNCTIONS OF ALL DEVICE PINS Ball Function 0 Function 1 D2 Direct Keypad24 Clock In D1 Direct Keypad25 F3 Interrupt A4 F4 Function 3 Pin Count Ball Name Genio 1 DIRECT24 CLKIN Genio 1 DIRECT25 1 IRQN Supply Voltage 2 VCC C1 ResetN 1 RESETN E1 I2 C 1 SCL 1 SDA Main Function 2 - Clk E2 Main I2C - Data A6 Direct Keypad0 Keypad - I/O X0 Genio 1 DIRECT0 KPX0 A5 Direct Keypad1 Keypad - I/O X1 Genio 1 DIRECT1 KPX1 F1 Direct Keypad2 Keypad - I/O X2 Genio 1 DIRECT2 KPX2 F2 Direct Keypad3 Keypad - I/O X3 Genio 1 DIRECT3 KPX3 A2 Direct Keypad4 Keypad - I/O X4 Genio 1 DIRECT4 KPX4 B3 Direct Keypad5 Keypad - I/O X5 Genio 1 DIRECT5 KPX5 A3 Direct Keypad6 Keypad - I/O X6 Genio 1 DIRECT6 KPX6 B4 Direct Keypad7 Keypad - I/O X7 Genio 1 DIRECT7 KPX7 C6 Direct Keypad8 Keypad - I/O Y0 Genio 1 DIRECT8 KPY0 C5 Direct Keypad9 Keypad - I/O Y1 Genio 1 DIRECT9 KPY1 B6 Direct Keypad10 Keypad - I/O Y2 Genio 1 DIRECT10 KPY2 B5 Direct Keypad11 Keypad - I/O Y3 Genio 1 DIRECT11 KPY3 B2 Direct Keypad12 Keypad - I/O Y4 Genio 1 DIRECT12 KPY4 A1 Direct Keypad13 Keypad - I/O Y5 Genio 1 DIRECT13 KPY5 B1 Direct Keypad14 Keypad - I/O Y6 Genio 1 DIRECT14 KPY6 C2 Direct Keypad15 Keypad - I/O Y7 Genio 1 DIRECT15 KPY7 7 www.national.com LM8327 Ball Function 0 Function 1 E3 Direct Keypad16 D5 Function 3 Pin Count Ball Name Keypad - I/O Y8 Genio 1 DIRECT16 KPY8 Direct Keypad17 Keypad - I/O Y9 Genio 1 DIRECT17 KPY9 E6 Direct Keypad18 Keypad - I/O Y10 Genio 1 DIRECT18 KPY10 F6 Direct Keypad19 Keypad - I/O Y11 Genio 1 DIRECT19 KPY11 E4 Direct Keypad20 PWM output 0 Genio 1 DIRECT20 PWM0 F5 Direct Keypad21 PWM output 1 Genio 1 DIRECT21 PWM1 E5 Direct Keypad22 PWM output 2 Genio 1 DIRECT22 PWM2 D6 Direct Keypad23 Genio 1 DIRECT23 GENIO1 C3 C4 D3 D4 Ground 4 GND TOTAL 36 www.national.com Function 2 Clockout 8 LM8327 7.2 PIN CONFIGURATION AFTER RESET Upon power-up or RESET the LM8327 will have defined states on all pins. Table 2 provides a comprehensive overview on the states of all functional pins. TABLE 2. Pin Configuration after Reset Pins DIRECT KEYPAD 0 DIRECT KEYPAD 1 DIRECT KEYPAD 2 DIRECT KEYPAD 3 DIRECT KEYPAD 4 DIRECT KEYPAD 5 DIRECT KEYPAD 6 DIRECT KEYPAD 7 DIRECT KEYPAD 8 DIRECT KEYPAD 9 DIRECT KEYPAD 10 DIRECT KEYPAD 11 DIRECT KEYPAD 12 DIRECT KEYPAD 13 DIRECT KEYPAD 14 DIRECT KEYPAD 15 DIRECT KEYPAD 16 DIRECT KEYPAD 17 DIRECT KEYPAD 18 DIRECT KEYPAD 19 DIRECT KEYPAD 20 DIRECT KEYPAD 21 DIRECT KEYPAD 22 DIRECT KEYPAD 23 DIRECT KEYPAD 24 DIRECT KEYPAD 25 IRQN SCL SDA Pin States Full Buffer mode input with an on-chip pull-up resistor enabled. Open Drain mode with no pull resistor enabled, driven low. NOTE: The IRQN is driven low after Power-On Reset due to PORIRQ signal. The value 0x01 must be written to the RSTINTCLR register (0x84) to release the IRQN pin. Open Drain mode with no pull resistor enabled. 9 www.national.com LM8327 8.0 Typical Application Setup 30124203 FIGURE 2. LM8327 in a Typical Setup with Standard Handset Keypad 8.1 FEATURES The following features are supported with the application example shown above: * * 8.1.1 Hardware * Hardware * 4 x 8 keys and 8 Special Function (SF) keys for 40 keys. * ACCESS.bus interface for communication with a host device. - communication speeds supported are: 100 kHz standard mode and 400 kHz fast mode of operation. * Interrupt signal (IRQN) to indicate any keypad or hardware interrupt events to the host. * Sophisticated PWM function block with 3 independent channels to control color LED. 8.1.2 Communication Layer * Versatile register-based command integration supported from on-chip command interpreter. * Keypad event storage. * Individual PWM script file storage and execution control for 3 PWM channels. www.national.com 10 External clock input for accurate PWM clock (not used). Four host-programmable dedicated general-purpose output pins (GPIOs:KPY4:7) supporting I/O-expansion capabilities for host device. Six host-programmable dedicated direct key connection input pins (DIRECT 16:19, 23, 25) with wake-up supporting I/O-expansion capabilities for host device. 9.1 HALT MODE DESCRIPTION The fully static architecture of the LM8327 allows stopping the internal RC clock in Halt mode, which reduces power consumption to the minimum level. Figure 3 shows an estimate of the current in Halt mode at the maximum VCC (1.98V) from 25C to +85C. 9.2 ACCESS.BUS ACTIVITY When the LM8327 is in Halt mode, only activity on the ACCESS.bus interface that matches the LM8327 Slave Address will cause the LM8327 to exit from Halt mode. However, the LM8327 will not be able to acknowledge the first bus cycle immediately following wake-up from Halt mode. It will respond with a negative acknowledgement, and the host should then repeat the cycle. A peripheral that is continuously active can share the bus since this activity will not prevent the LM8327 from entering Halt mode. 30124204 FIGURE 3. Halt Current vs. Temperature at 1.98V 11 www.national.com LM8327 Halt mode is entered when no key-press event, key-release event, or is detected for a certain period of time (by default, 1020 milliseconds). The mechanism for entering Halt mode is always enabled in hardware, but the host can program the period of inactivity which triggers entry into Halt mode using the autosleep function. (See Table 52.) 9.0 Halt Mode LM8327 mission protocol. All functions can be controlled by configuring one or multiple registers. Please refer to Section 14.0 LM8327 Register Set for the complete register set. 10.0 LM8327 Programming Interface The LM8327 operation is controlled from a host device by a complete register set, accessed via the I2C-compatible ACCESS.bus interface. The ACCESS.bus communication is based on a READ/WRITE structure, following the I2C trans- 10.1 ACCESS.BUS COMMUNICATION Figure 4 shows a typical read cycle initiated by the host. 30124205 FIGURE 4. Master/Slave Serial Communication (Host to LM8327) TABLE 3. Definition of Terms used in Serial Command Example Term Bits S ADDRESS Description START Condition (always generated from the master device) 7 Slave address of LM8327 sent from the host R/W 1 This bit determines if the following data transfer is from master to slave (data write) or from slave to master (data read). 0: Write 1: Read ACK 1 An acknowledge bit is mandatory and must be appended on each byte transfer. The Acknowledge status is actually provided from the slave and indicates to the master that the byte transfer was successful. REG 8 The first byte after sending the slave address is the REGISTER byte which contains the physical address the host wants to read from or write to. RS Repeated START condition DATA 8 The DATA field contains information to be stored into a register or information read from a register. NACK 1 Not Acknowledge Bit. The Not Acknowledge status is assigned from the Master receiving data from a slave. The NACK status will actually be assigned from the master in order to signal the end of a communication cycle transfer P STOP condition (always generated from the master device). 2. All actions associated with the non-shaded boxes in Figure 4 are controlled from the master (host) device. All actions associated with the shaded boxes in Figure 4 are controlled from the slave (LM8327) device. The master device can send subsequent REGISTER addresses separated by Repeated START conditions. A STOP condition must be set from the master at the very end of a communication cycle. It is recommended to use Repeated START conditions in multi-Master systems when sending subsequent REGISTER addresses. This technique will make sure that the master device communicating with the LM8327 will not loose bus arbitration. 10.1.1 Starting a Communication Cycle There are two reasons for the host device to start communication to the LM8327: 1. The LM8327 device has set the IRQN line low in order to signal a key - event or any other condition which initializes a hardware interrupt from LM8327 to the host. www.national.com 12 The host device wants to set a GENIO port, read from a GENIO port, configure a GENIO port, and read the status from a register or initialize any other function which is supported from the LM8327. In case a GENIO shall be read it will be most likely, that the LM8327 device will be residing in "sleep mode". In this mode the system clock will be off to establish the lowest possible current consumption. If the host device starts the communication under this condition the LM8327 device will not be able to acknowledge the first attempt of sending the slave address. The LM8327 will wake up because of the START condition but it can't establish the internal timing to scan the first byte received. The master device must therefore apply a second attempt to start the communication with the LM8327 device. LM8327 10.1.2 Communication Initialized from Host (Restart from Sleep Mode) 30124206 FIGURE 5. Host Starts Communication While LM8327 is in Sleep Mode * * * * * In the timing diagram shown in Figure 5 the LM8327 resides in sleep mode. Since the LM8327 device can't acknowledge the slave address the host must generate a STOP condition followed by a second START condition. On the second attempt the slave address is being acknowledged from the LM8327 device because it is in active mode now. The host can send different WRITE and/or READ commands subsequently after each other. The host must finally free the bus by generating a STOP condition. Normally the LM8327 will clock stretch after the acknowledge bit is transmitted; however, there are some conditions where the LM8327 will clock stretch between the SDA Start bit and the first rising edge of SCL. 10.1.4 Auto Increment In order to improve multi-byte register access, the LM8327 supports the auto increment of the address pointer. A typical protocol access sequence to the LM8327 starts with the I2C-compatible ACCESS.bus address, followed by REG, the register to access (see Figure 4). After a REPEATED START condition the host reads/writes a data byte from/to this address location. If more than one byte is transmitted, the LM8327 automatically increments the address pointer for each data byte by 1. The address pointer keeps the status until the STOP condition is received. The LM8327 always uses auto increments unless otherwise noted. Please refer to Table 4 and Table 5 for the typical ACCESS.bus flow of reading and writing multiple data bytes. 10.1.3 ACCESS.Bus Communication Flow The LM8327 will only be driven in slave mode. The maximum communication speed supported is Fast Mode (FS) which is 400 kHz. The device can be heavily loaded as it is processing different kind of events caused from the human interface and the host device. In such cases the LM8327 may temporarily be unable to accept new commands and data sent from the host device. Please Note: "It is a legitimate measure of the slave device to hold SCL line low in such cases in order to force the master device into a waiting state!. It is therefore the obligation of the host device to detect such cases. Typically there is a control bit set in the master device indicating the Busy status of the bus. As soon as the SCL line is released the host can continue sending commands and data." Further Remarks: * In systems with multiple masters it is recommended to separate commands with Repeat START conditions rather than sending a STOP - and another START condition to communicate with the LM8327 device. * Delays enforced by the LM8327 during very busy phases of operation should typically not exceed a duration of 100 sec. 10.1.5 Reserved Registers and Bits The LM8327 includes reserved registers for future implementation options. Please use value 0 on a write to all reserved register bits. 10.1.6 Global Call Reset The LM8327 supports the Global Call Reset as defined in the I2C Specification, which can be used by the host to reset all devices connected to interface. The Global call reset is a single byte ACCESS.bus/I2C write of data byte 0x06 to slave address 0x00. The Global Call Reset changes the I2C-compatible ACCESS.bus Slave address of the LM8327 back to its default value of 0x8A. 13 www.national.com LM8327 TABLE 4. Multi-Byte Write with Auto Increment I2C Com. Step Master/Slave Value 1 M S 2 M ADDR. 0x8A 3 M R/W 0 Address Pointer Comment START condition 4 S ACK 5 M REG 6 S ACK 7 M DATA 8 S ACK 9 M 10 11 I2C-compatible ACCESS.bus Address Write Acknowledge 0xAA 0xAA Register Address, used as Address Pointer 0xAA Acknowledge 0x01 0xAA Write Data to Address in Pointer 0 0xAB Acknowledge, Address pointer incremented DATA 0x05 0xAB Write Data to address 0xAB S ACK 0 0xAC Acknowledge, Address pointer incremented M P STOP condition TABLE 5. Multi-Byte Read with Auto Increment Step Master/Slave I2C Com. 1 M S 2 M ADDR. 0x8A 3 M R/W 0 4 S ACK 5 M REG 6 S 7 M 8 M ADDR. 0x8A 9 M R/W 1 10 S ACK 0 0xAA Acknowledge 11 S DATA 0x01 0xAA Read Data from Address in Pointer 12 M ACK 0 0xAB Acknowledge, Address Pointer incremented 13 S DATA 0x05 0xAB Read Data from Address in Pointer 14 M NACK 0 0xAC No Acknowledge, stops transmission 15 M P Value Address Pointer I2C-compatible ACCESS.bus Address Write Acknowledge 0xAA 0xAA Register Address, used as Address pointer ACK 0xAA Acknowledge RS 0xAA Repeated Start 0xAA I2C-compatible ACCESS.bus Address Read STOP condition All non-bolded actions rows in Tables 4 and 5 are controlled from the master (host) device. All highlighted rows in Tables 4 and 5 are controlled from the slave (LM8327) device. www.national.com Comment START condition 14 LM8327 11.0 Keyscan Operation 11.1 KEYSCAN INITIALIZATION 30124207 FIGURE 6. Keyscan Initialization 15 www.national.com LM8327 * 11.2 KEYSCAN INITIALIZATION EXAMPLE Table 6 shows all the LM8327 register configurations to initialize keyscan: Keypad matrix configuration is 8 rows x 12 columns. TABLE 6. Keyscan Initialization Example Register name Adress Access Type Value CLKEN 0x8A byte 0x01 enable keyscan clock Comment KBDSETTLE 0x01 byte 0x80 set the keyscan settle time to 12 msec KBDBOUNCE 0x02 byte 0x80 set the keyscan debounce time to 12 msec KBDSIZE 0x03 byte 0x8C set the keyscan matrix size to 8 rows x 12 columns KBDDEDCFG 0x04 word 0xFFFF IOCFG 0xA7 byte 0x00 IOPC0 0xAA word 0xAAAA configure pull-up resistors for KPX[7:0] IOPC1 0xAC word 0x5555 configure pull-down resistors for KPY[7:0] IOPC2 0xAE word 0x0055 configure pull-down resistors for KPY[11:8] KBDIC 0x08 byte 0x03 clear any pending interrupts KBDMSK 0x09 byte 0x03 enable keyboard interrupts www.national.com configure KPX[7:2] and KPY[11:2] pins as keyboard matrix write default value to enable all pins as keyboard matrix 16 30124208 FIGURE 7. Example Keyscan Operation for 1 Key Press and Release 17 www.national.com LM8327 the device sets the RAW keyboard event interrupt REVTINT. The RSINT interrupt is set anytime the keyboard status has changed. Depending on the interrupt masking for the keyboard events (KBDMSK) and the masked interrupt handling (KBDMIS), the pin IRQN will follow the IRQST.KBDIRQ status, which is set as soon as one interrupt in KBDRIS is set. Figure 7 shows the basic flow of a scanning process and which registers are affected. 11.3 KEYSCAN PROCESS The LM8327 keyscan functionality is based on a specific scanning procedure performed in a 4ms interval. On each scan all assigned key matrix pins are evaluated for state changes. In case a key event has been identified, the event is stored in the key event FIFO, accessible via the EVTCODE register. A key event can either be a key press or a key release. In addition, key presses are also stored in the KBDCODE[3:0] registers. As soon as the EVTCODE FIFO includes a event, LM8327 host first reads the KBDCODE to get possible key press events and afterwards reads the complete event list by reading the EVTCODE register until all events are captured (0x7F indicates end of buffer). Reading KBDCODE clears the RSINT interrupt bit if all keyboards events are emptied. In the same way, REVTINT is cleared in case the EVTCODE FIFO reaches its empty state on read. The event buffer content and the REVTINT and RELINT (lost event) interrupt bits are also cleared if the KBDIC.EVTIC bit is set. Interrupt bits in the masked interrupt register KBDMIS follow the masked KBDRIS status. In order to support efficient Multi-byte reads from EVTCODE, the autoincrement feature is turned off for this register. Therefore the host can continuously read the complete EVTCODE buffer by sending one command. 11.4 READING KEYSCAN STATUS BY THE HOST In order to keep track of the keyscan status, the host either needs to regularly poll the EVTCODE register or needs to react on the Interrupt signaled by the IRQN pin. Figure 8 gives an example on which registers to read to get the keyboard events from the LM8327 and how they influence the interrupt event registers. The example is based on the assumption that the LM8327 has indicated the keyboard event by the IRQN pin. Since the interrupt pin has various sources, the host first checks the IRQST register for the interrupt source. If KBDIRQ is set, the host can check the KBDMIS register to define the exact interrupt source. KBDMIS contains the masked status of KBDRIS and reflects the source for raising the interrupt pin. The interrupt mask is defined by KBDMSK. The complete status of all pending keyboard interrupts is available in the raw interrupt register KBDRIS. After evaluating the interrupt source the host starts reading the EVTCODE or KBDCODE register. In this example the 30124209 FIGURE 8. Example Host Reacting to Interrupt for Keypad Event www.national.com 18 30124210 FIGURE 9. Example Keyscan Operation for 2 Key Press Events and 1 Key Release Event 19 www.national.com LM8327 KBDCODE3 accordingly. The four registers signal the last multi-key press events. All events are stored in parallel in the EVTCODE register for the complete set of events. All KBDCODE[3:0] registers are cleared on read. 11.5 MULTIPLE KEY PRESSES The LM8327 supports up to four simultaneous key presses. Any time a single key is pressed KBDCODE0 is set with the appropriate key code. If a second key is pressed, the key is stored in KBDCODE1 and the MULTIKEY flag of KBDCODE0 is set. Additional key presses are stored in KBDCODE2 and LM8327 12.0 Direct Key Operation 12.1 DIRECT KEY INITIALIZATION 30124213 FIGURE 10. Direct Key Initialization www.national.com 20 LM8327 12.2 DIRECT KEY INITIALIZATION EXAMPLE Table 7 shows all the LM8327 register configurations to initialize direct keys. * Direct key configuration is for 26 direct keys. TABLE 7. Direct Key Initialization Example Register Name Address Access Type Value Comment CLKEN 0x8A byte 0x02 Enable direct key clock DBOUNCE 0xE7 byte 0x04 Set the keyscan debounce time to 12 msec. GPIOIBE0 0xCC byte 0x00 Configure single key event detection for DK[7:0] GPIOIBE1 0xCD byte 0x00 Configure single key event detection for DK[15:8] GPIOIBE2 0xCE byte 0x00 Configure single key event detection for DK[23:16] GPIOIEV0 0xCF byte 0x00 Configure press key event detection DK[7:0] GPIOIEV1 0xD0 byte 0x00 Configure press key event detection DK[15:8] GPIOIEV2 0xD1 byte 0x00 Configure press key event detection DK[23:16] GPIOIE0 0xD2 byte 0x00 Disable GPI interrupts for DK[7:0] GPIOIE1 0xD3 byte 0x00 Disable GPI interrupts for DK[15:8] GPIOIE2 0xD4 byte 0x00 Disable GPI interrupts for DK[23:16] IOCFG 0xA7 byte 0x00 Write default value to enable all pins as direct keys IOPC0 0xAA word 0xAAAA Configure pull-up resistors for DK[7:0] IOPC1 0xAC word 0xAAAA Configure pull-up resistors for DK[15:8] IOPC2 0xAE word 0xAAAA Configure pull-up resistors for DK[23:16] DKBDIC 0xF2 byte 0x01 Clear any pending interrupts DKBDMSK 0xF3 byte 0x00 Enable direct key and lost direct key interrupts DIRECT0 0xEC byte 0xFF Enable pins as DK[7:0] DIRECT1 0xED byte 0xFF Enable pins as DK[15:8] DIRECT2 0xEE byte 0xFF Enable pins as DK[23:16] DIRECT3 0xEF byte 0x03 Enable pins as DK[25:24] 21 www.national.com LM8327 * 13.0 PWM Timer The LM8327 supports a timer module dedicated to smooth LED control techniques (lighting controls). The PWM timer module consists of three independent timer units of which each can generate a PWM output with a fixed period and automatically incrementing or decrementing variable duty cycle. The timer units are all clocked with a slow (32.768 kHz) clock whereas the interface operates with the main system clock. * * The execution of any pre-programmed task is selfsustaining and does not require further interaction from the host. 64-byte script buffer for each PWM for up to 32 consecutive instructions. Direct addressing within script buffer to support multiple PWM tasks in one buffer. 13.2 OVERVIEW ON PWM SCRIPT COMMANDS The commands listed in Table 8 are dedicated to the slow PWM timers. Please note: The PWM Script commands are not part of the command set supported by the LM8327 command interpreter. These commands must be transferred from the host with help of the register-based command set. 13.1 OVERVIEW OF PWM FEATURES * Each PWM can establish fixed - or variable - duty-cycle signal sequences on its output. * Each PWM can trigger execution of any pre-programmed task on another PWM channel. TABLE 8. PWM Script Commands Command 15 14 RAMP 0 PRESCALE 13 12 STEPTIME 11 10 SET_PWM 0 1 0 9 8 7 6 5 SIGN 4 3 2 1 0 INCREMENT PWMVALUE GO_TO_ START 0 BRANCH 1 0 1 END 1 1 0 TRIGGER 1 1 1 LOOPCOUNT 1 ADDR STEPNUMBER INT X WAITTRIGGER SENDTRIGGER 0 the direction of a RAMP (up or down). The STEPTIME field and the PRESCALE bit determine the duration of one step. Based on a 32.768 kHz clock, the minimum time resulting from these options would be 0.49 milliseconds and the maximum time for one step would be 1 second. 13.2.1 RAMP COMMAND A RAMP command will vary the duty cycle of a PWM output in either direction (up or down). The INCREMENT field specifies the amount of steps for the RAMP. The maximum amount of steps which can be executed with one RAMP Command is 126 which is equivalent to 50%. The SIGN bit field determines TABLE 9. RAMP Command Bit Fields 15 14 0 PRESCALE 13 12 11 10 9 8 7 STEPTIME 6 5 4 SIGN 3 2 1 0 INCREMENT TABLE 10. Description of Command Bit Fields of the RAMP Command Bit or Field Value PRESCALE STEPTIME Divide the 32.768 kHz clock by 16 1 Divide the 32.768 kHz clock by 512 1 - 63 SIGN INCREMENT Description 0 Number of prescaled clock cycles per step 0 Increment RAMP counter 1 Decrement RAMP counter 0 - 126 Number of steps executed by this instruction; a value of 0 functions as a WAIT determined by STEPTIME. FULL SCALE (0% or 100%). A RAMP command following the SET_PWM command will finally establish the desired duty cycle on the PWM output. 13.2.2 SET_PWM COMMAND The SET_PWM command does not allow generation of a PWM output with a fixed duty cycle between 0% and 100%. This command will set the starting duty cycle MIN SCALE or TABLE 11. SET_PWM Command Bit Fields 15 14 13 12 11 10 9 8 0 1 0 0 0 0 0 0 www.national.com 7 6 5 4 3 DUTYCYCLE 22 2 1 0 LM8327 TABLE 12. Description of Bit Fields of the SET_PWM Command Bit or Field Value 0 DUTYCYCLE Description Duty cycle is 0%. 255 Duty cycle is 100%. 13.2.3 GO_TO_START COMMAND The GO_TO_START command jumps to the first command in the script command file. TABLE 13. GO_TO_START Command Bit Fields 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 gives the option of looping for a specified number of repetitions. Please note: Nested loops are not allowed. 13.2.4 BRANCH COMMAND The BRANCH command jumps to the specified command in the script command file. The BRANCH is executed with either absolute or relative addressing. In addition, the command TABLE 14. BRANCH Command Bit Fields 15 14 13 1 0 1 12 11 10 9 8 7 6 LOOPCOUNT 5 4 ADDR 3 2 1 0 STEPNUMBER TABLE 15. Description of Command Bit Fields of the BRANCH Command Bit or Field Value 0 LOOPCOUNT 1 - 63 ADDR STEPNUMBER Description Loop until a STOP PWM SCRIPT command is issued by the host. Number of loops to perform. 0 Absolute addressing 1 Relative addressing 0 - 63 Depending on ADDR: ADDR=0: Addr to jump to ADDR=1: Number of backward steps On trigger it will clear the trigger(s) and continue to the next command. When a trigger is sent, it is stored by the receiving channel and can only be cleared when the receiving channel executes a TRIGGER command that waits for the trigger. 13.2.5 TRIGGER COMMAND Triggers are used to synchronize operations between PWM channels. A TRIGGER command that sends a trigger takes sixteen 32.768 kHz clock cycles, and a command that waits for a trigger takes at least sixteen 32.768 kHz clock cycles. A TRIGGER command that waits for a trigger (or triggers) will stall script execution until the trigger conditions are satisfied. TABLE 16. TRIGGER Command Bit Fields 15 14 13 1 1 1 12 11 10 9 8 7 6 WAITTRIGGER 5 4 3 SENDTRIGGER 2 1 0 0 TABLE 17. Description of Command Bit Fields Field WAITTRIGGER SENDTRIGGER Value Description 000xx1 Wait for trigger from channel 0 000x1x Wait for trigger from channel 1 0001xx Wait for trigger from channel 2 000xx1 Send trigger to channel 0 000x1x Send trigger to channel 1 0001xx Send trigger to channel 2 When the END command is executed, the PWM output will be set to the level defined by PWMCFG.PWMPOL for this channel. Also, the script counter is reset back to the beginning of the script command buffer. 13.2.6 END COMMAND The END command terminates script execution. It will only assert an interrupt to the host if the INT bit is set to "1". 23 www.national.com LM8327 Please note: If a PWM channel is waiting for the trigger (last executed command was "TRIGGER") and the script execution is halted then the "END" command can't be executed because the previous command is still pending. This is an exception - in this case the IRQ signal will not be asserted. TABLE 18. END Command Bit Fields 15 14 13 12 11 1 1 0 1 INT 10 9 8 7 6 5 4 3 2 1 0 0 TABLE 19. Description of Command Bit Fields of the END Command Field INT www.national.com Value Description 0 No interrupt will be sent. 1 Set TIMRIS.CDIRQ for this PWM channel to notify that program has ended. 24 LM8327 14.0 LM8327 Register Set 14.1 KEYBOARD REGISTERS AND KEYBOARD CONTROL Keyboard selection and control registers are mapped in the address range from 0x01 to 0x10. This paragraph describes the functions of the associated registers down to the bit level. 14.1.1 KBDSETTLE - Keypad Settle Time Register TABLE 20. KBDSETTLE - Keypad Settle Time Register Register - Name Address Type Register Function KBDSETTLE 0x01 R/W Initial time for keys to settle, before the key-scan process is started. Bit - Name Bit Default WAIT[7:0] 7:0 0x80 Bit Function The default value 0x80 : 0xBF sets a time target of 12 msec Further time targets are as follows: 0xC0 - 0xFF: 16 msec 0x80 - 0xBF: 12 msec 0x40 - 0x7F: 8 msec 0x01 - 0x3F: 4 msec 0x00 : no settle time 14.1.2 KBDBOUNCE - Debounce Time Register TABLE 21. KBDBOUNCE - Debounce Time Register Register - Name Address Type KBDBOUNCE 0x02 R/W Bit - Name Bit Default WAIT[7:0] 7:0 0x80 Register Function Time between first detection of key and final sampling of key. Bit Function The default value 0x80 : 0xBF sets a time target of 12 msec. Further time targets are as follows: 0xC0 - 0xFF: 16 msec 0x80 - 0xBF: 12 msec 0x40 - 0x7F: 8 msec 0x01 - 0x3F: 4 msec 0x00: no debouncing time 14.1.3 KBDSIZE - Set Keypad Size Register TABLE 22. KBDSIZE - Set Keypad Size Register Register - Name Address Type KBDSIZE 0x03 R/W Bit - Name Bit Default Bit Function 0x2 Number of rows in the keyboard matrix: 0x0: free all rows to become GPIO, KPX[1:0] used as dedicated key inputs if scanning is enabled by CLKEN.KBEN. 0x1: (illegal value) 0x2 - 0x8: Number of rows in the matrix 0x2 Number of columns in the keyboard matrix: 0x0: free all rows to become GPIO, KPY[1:0] used as dedicated key inputs if scanning is enabled by CLKEN.KBEN 0x1: (illegal value) 0x2 - 0xC: Number of columns in the matrix ROWSIZE[3:0] COLSIZE[3:0] 7:4 3:0 Register Function Defines the physical keyboard matrix size. 25 www.national.com LM8327 14.1.4 KBDDEDCFG - Dedicated Key Register TABLE 23. KBDDEDCFG - Dedicated Key Register Register - Name Address Type Register Function KBDDEDCFG 0x04 R/W Defines if a key is used as a standard keyboard/GPIO pin or whether it is used as dedicated key input. Bit - Name Bit Default Bit Function 0x3F Each bit in ROW [7:2] corresponds to ball KPX7 : KPX2. Bit=0: the dedicated key function applies. Bit=1: no dedicated key function is selected. The standard GPIO functionality applies according to register IOCFG or defined keyboard matrix. 0x03 Each bit in COL [11:10] corresponds to ball KPY11 : KPY10. Bit=0: the dedicated key function applies. Bit=1: no dedicated key function is selected. The standard GPIO functionality applies according to register IOCFG or defined keyboard matrix. 0xFF Each bit in COL [9:2] corresponds to ball KPY9 : KPY2 and can be configured individually. Bit=0: the dedicated key function applies. Bit=1: no dedicated key function is selected. The standard GPIO functionality applies according to register IOCFG or defined keyboard matrix. ROW[7:2] COL[11:10] COL[9:2] 15:10 9:8 7:0 14.1.5 KBDRIS - Keyboard Raw Interrupt Status Register TABLE 24. KBDRIS - Keyboard Raw Interrupt Status Register Register - Name Address Type KBDRIS 0x06 R Bit - Name Bit Default (reserved) 7:4 RELINT REVTINT 3 2 Register Function Returns the status of stored keyboard interrupts. Bit Function (reserved) 0x0 Raw event lost interrupt. More than 8 keyboard events have been detected and caused the event buffer to overflow. This bit is cleared by setting bit EVTIC of the KBDIC register. 0x0 Raw keyboard event interrupt. At least one key press or key release is in the keyboard event buffer. Reading from EVTCODE until the buffer is empty will clear this interrupt. RKLINT 1 0x0 Raw key lost interrupt indicates a lost key-code. This interrupt is asserted when RSINT has not been cleared upon detection of a new key press or key release, or when more than 4 keys are pressed simultaneously. RSINT 0 0x0 Raw scan interrupt. Interrupt generated after keyboard scan, if the keyboard status has changed. www.national.com 26 LM8327 14.1.6 KBDMIS - Keypad Masked Interrupt Status Register TABLE 25. KBDMIS - Keypad Masked Interrupt Status Register Register - Name Address Type Register Function KBDMIS 0x07 R Returns the status on masked keyboard interrupts after masking with the KBDMSK register. Bit - Name Bit Default (reserved) 7:4 MELINT MEVTINT Bit Functions (reserved) 3 2 0x0 Masked event lost interrupt. More than 8 keyboard events have been detected and caused the event buffer to overflow. This bit is cleared by setting bit EVTIC of the KBDIC register. 0x0 Masked keyboard event interrupt. At least one key press or key release is in the keyboard event buffer. Reading from EVTCODE until the buffer is empty will clear this interrupt. MKLINT 1 0x0 Masked key lost interrupt. Indicates a lost key-code. This interrupt is asserted when RSINT has not been cleared upon detection of a new key press or key release, or when more than 4 keys are pressed simultaneously. MSINT 0 0x0 Masked scan interrupt. Interrupt generated after keyboard scan, if the keyboard status has changed, after masking process. 14.1.7 KBDIC - Keypad Interrupt Clear Register TABLE 26. KBDIC - Keypad Interrupt Clear Register Register - Name Address Default KBDIC 0x08 W Bit - Name Bit Default Register Function Setting these bits clears Keypad active Interrupts. Bit Function Switches off scanning of special function (SF) keys, when keyboard has no special function layout. 0: keyboard layout and SF keys are scanned 1: only keyboard layout is scanned, SF keys are not scanned SFOFF 7 (reserved) 6:2 EVTIC 1 Clear event buffer and corresponding interrupts REVTINT and RELINT by writing a 1 to this bit position. KBDIC 0 Clear RSINT and RKLINT interrupt bits by writing a 1 to this bit position. (reserved) 27 www.national.com LM8327 14.1.8 KBDMSK - Keypad Interrupt Mask Register TABLE 27. KBDMSK - Keypad Interrupt Mask Register Register - Name Type Register Function 0x09 R/W Configures masking of keyboard interrupts. Masked interrupts do not trigger an event on the Interrupt output. In case the interrupt processes registers KBDCODE[3:0], MSKELINT and MSKEINT should be set to 1. When the Event FIFO is processed, MSKLINT and MSKSINT should be set. For keyboard polling operations, all bits should be set and the polling operation consists of reading out the EVTCODE. Bit - Name Bit Default (reserved) 7:4 MSKELINT 3 0x1 0: keyboard event lost interrupt RELINT triggers IRQ line 1: keyboard event lost interrupt RELINT is masked MSKEINT 2 0x1 0: keyboard event interrupt REVINT triggers IRQ line 1: keyboard event interrupt REVINT is masked MSKLINT 1 0x0 0: keyboard lost interrupt RKLINT triggers IRQ line 1: keyboard lost interrupt RKLINT is masked MSKSINT 0 0x0 0: keyboard status interrupt RSINT triggers IRQ line 1: keyboard status interrupt RSINT is masked KBDMSK Address Bit Function (reserved) Please note: Reading out all key code registers (KBDCODE0 to KBDCODE3) will automatically reset the keyboard scan interrupt RSINT the same way as an active write access into bit KBDIC of the interrupt clear register does. Reading 0x7F from the KBDCODE0 register means that no key was pressed. 14.1.9 KBDCODE0 - Keyboard Code Register 0 The key code detected by the keyboard scan can be read from the registers KBDCODE0: KBDCODE3. Up to 4 keys can be detected simultaneously. Each KBDCODE register includes a bit (MULTIKEY) indicating if another key has been detected. TABLE 28. KBDCODE0 - Keyboard Code Register 0 Register - Name Address Default KBDCODE0 0x0B R Bit - Name Bit Default Register Function Holds the row and column information of the first detected key. Bit Function MULTIKEY 7 0x0 If this bit is 1 another key is available in KBDCODE1 register. KEYROW[2:0] 6:4 0x7 ROW index of detected key (0 to 7) KEYCOL[3:0] 3:0 0xF Column index of detected (0 to 11, 12 for special function key). 14.1.10 KBDCODE1 - Keyboard Code Register 1 TABLE 29. KBDCODE1 - Keyboard Code Register 1 Register - Name Address Default KBDCODE1 0x0C R Bit - Name Bit Default Register Function Holds the row and column information of the second detected key. Bit Function MULTIKEY 7 0x0 If this bit is 1 another key is available in KBDCODE2 register. KEYROW[2:0] 6:4 0x7 ROW index of detected key (0 to 7) KEYCOL[3:0] 3:0 0xF Column index of detected key (0 to 11, 12 for special function key). www.national.com 28 LM8327 14.1.11 KBDCODE2 - Keyboard Code Register 2 TABLE 30. KBDCODE2 - Keyboard Code Register 2 Register - Name Address Default KBDCODE2 0x0D R Register Function Holds the row and column information of the third detected key. Bit - Name Bit Default MULTIKEY 7 0x0 If this bit is 1 another key is available in KBDCODE3 register. Bit Function KEYROW[2:0] 6:4 0x7 ROW index of detected key (0 to 7) KEYCOL[3:0] 3:0 0xF Column index of detected key (0 to 11, 12 for special function key). 14.1.12 KBDCODE3 - Keyboard Code Register 3 TABLE 31. KBDCODE3 - Keyboard Code Register 3 Register - Name Address Default KBDCODE3 0x0E R Bit - Name Bit Default Register Function Holds the row and column information of the forth detected key. Bit Function 0x0 If this bit is set to "1" then more than 4 keys are pressed simultaneously. 6:4 0x7 ROW index of detected key (0 to 7) 3:0 0xF Column index of detected key (0 to 11, 12 for special function key). MULTIKEY 7 KEYROW[2:0] KEYCOL[3:0] 14.1.13 EVTCODE - Key Event Code Register TABLE 32. EVTCODE - Key Event Code Register Register - Name Address Default Bit Function EVTCODE 0x10 R With this register a FIFO buffer is addressed storing up to 15 consecutive events. Reading the value 0x7F from this address means that the FIFO buffer is empty. See further details below. NOTE: Auto increment is disabled on this register. Multi-byte read will always read from the same address. Bit - Name Bit Default Bit Function RELEASE 7 0x0 This bit indicates, whether the keyboard event was a key press or a key release event. 0: key was pressed 1: key was released KEYROW[2:0] 6:4 0x7 Row index of key that is pressed or released. KEYCOL[3:0] 3:0 0xF Column index of key that is pressed (0...11, 12 for special function key) or released. timer control registers are mapped in the range from 0x60 to 0x7F. This paragraph describes the functions of the associated registers down to the bit level. 14.2 PWM TIMER CONTROL REGISTERS The LM8327 provides three host-programmable PWM outputs useful for smooth LED brightness modulation. All PWM 14.2.1 TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers TABLE 33. TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers Register - Name Address Type TIMCFG0 TIMCFG1 TIMCFG2 0x60 0x68 0x70 R/W Bit - Name (x = 0, 1 or 2) Bit Default Register Function This register configures interrupt masking and handles PWM start/ stop control of the associated PWM channel. Bit Function 29 www.national.com LM8327 Register - Name Address Type Register Function CYCIRQxMSK 4 0x0 Interrupt mask for PWM CYCIRQx (see Table 37): 0: interrupt enabled 1: interrupt masked (reserved) 3:0 0x0 (reserved) 14.2.2 PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers TABLE 34. PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers Register - Name Address Type Register Function R/W This register defines interrupt masking and the output behavior for the associated PWM channel. PGEx is used to start and stop the PWM script execution. PWMENx sets the PWM output to either reflect the generated pattern or the value configured in PWMPOLx. Bit Function PWMCFG0 0x61 PWMCFG1 0x69 PWMCFG2 0x71 Bit - Name (x = 0, 1 or 2) Bit Default CDIRQxMSK 3 0x0 Mask for CDIRQ: 0: CDIRQ enabled 1: CDIRQ disabled/masked PGEx 2 0x0 Pattern Generator Enable. Start/Stop PWM command processing for this channel. Script execution is started always from beginning. 0: Pattern Generator disabled 1: Pattern Generator enabled PWMENx 1 0x0 0: PWM disabled. PWM timer output assumes value programmed in PWMPOL. 1: PWM enabled PWMPOLx 0 0x0 Off-state of PWM output, when PWMEN=0. 0: PWM off-state is low 1: PWM off-state is high 14.2.3 TIMSCALx - PWM Timer 0, 1 and 2 Prescale Registers TABLE 35. TIMSCALx - PWM Timer 0, 1 and 2 Prescale Registers Register - Name Type Register Function 0x62 0x6A 0x72 R/W The registers determine the divider of the CLKIN external clock. The resulting clock is only used for PWM generation. The value should only be changed while PWM is stopped. Since all 3 PWM channels use the same slow clock, TIMSCAL0 affects all 3 PWM channels. TIMSCAL1 and TIMSCAL2 are directly linked to TIMSCAL0. Bit - Name Bit Default SCAL[7:0] 7:0 0x0 TIMSCAL0 TIMSCAL1 TIMSCAL2 www.national.com Address Bit Function CLKIN is divided by (SCAL+1). 30 LM8327 14.2.4 TIMSWRES - PWM Timer Software Reset Registers TABLE 36. TIMSWRES - PWM Timer Software Reset Registers Register - Name Type Register Function 0x78 W Reset control on all PWM timers. A reset forces the pattern generator to fetch the first pattern and stops it. Each reset stops all state-machines and timer. Patterns stored in the pattern configuration register remain unaffected. Interrupts on each timer are not cleared, they need to be cleared writing into register TIMIC. Bit - Name Bit Default (reserved) 7:3 SWRES2 2 Software reset of timer 2. 0: no action 1: Software reset on timer 2, needs not to be written back to 0. SWRES1 1 Software reset of timer 1. 0: no action 1: Software reset on timer 1, needs not to be written back to 0. SWRES0 0 Software reset of timer 0. 0: no action 1: software reset on timer 0, needs not to be written back to 0. TIMSWRES Address Bit Function (reserved) 14.2.5 TIMRIS - PWM Timer Interrupt Status Register TABLE 37. TIMRIS - PWM Timer Interrupt Status Register Register - Name Type Register Function 0x7A R This register returns the raw interrupt status from the PMW timers 0, 1 and 2. CYCIRQx - Interrupt from the timers when PWM cycle is complete (applies to the current PWM command residing in the active command register of a PWM block). CDIRQx - Interrupt from the pattern generator when PWM pattern code is complete (applies to a completed task residing in the script buffer of a PWM block). Bit - Name Bit Default (reserved) 7:6 TIMRIS Address Bit Functions (reserved) CDIRQ2 5 0x0 Raw interrupt status for CDIRQ timer2: 0: no interrupt pending 1: unmasked interrupt generated CDIRQ1 4 0x0 Raw interrupt status for CDIRQ timer1: 0: no interrupt pending 1: unmasked interrupt generated CDIRQ0 3 0x0 Raw interrupt status for CDIRQ timer0: 0: no interrupt pending 1: unmasked interrupt generated CYCIRQ2 2 0x0 Raw interrupt status for CYCIRQ timer2: 0: no interrupt pending 1: unmasked interrupt generated CYCIRQ1 1 0x0 Raw interrupt status for CYCIRQ timer1: 0: no interrupt pending 1: unmasked interrupt generated 31 www.national.com LM8327 Register - Name Address Type CYCIRQ0 0 0x0 Register Function Raw interrupt status for CYCIRQ timer0: 0: no interrupt pending 1: unmasked interrupt generated 14.2.6 TIMMIS - PWM Timer Masked Interrupt Status Register TABLE 38. TIMMIS - PWM Timer Masked Interrupt Status Register Register - Name Type Register Function 0x7B R This register returns the masked interrupt status from the PMW timers 0,1 and 2. The raw interrupt status (TIMRIS) is masked with the associated TIMCFGx.CYCIRQxMSK and PWMCFGx.CDIRQxMSK bits to get the masked interrupt status of this register. CYCIRQ - Interrupt from the timers when PWM cycle is complete (applies to the current PWM command residing in the active command register of a PWM block). CDIRQ - Interrupt from the pattern generator when PWM pattern code is complete (applies to a completed task residing in the script buffer of a PWM block). Bit - Name Bit Default (reserved) 7:6 TIMMIS CDIRQ2 CDIRQ1 CDIRQ0 CYCIRQ2 CYCIRQ1 CYCIRQ0 www.national.com Address 5 4 3 2 1 0 Bit Function (reserved) 0x0 Interrupt after masking, indicates active contribution to the interrupt ball, when set. Status for CDIRQ timer2: 0: no interrupt pending 1: interrupt generated 0x0 Interrupt after masking, indicates active contribution to the interrupt ball, when set. Status for CDIRQ timer1: 0: no interrupt pending 1: interrupt generated 0x0 Interrupt after masking, indicates active contribution to the interrupt ball, when set. Status for CDIRQ timer0: 0: no interrupt pending 1: interrupt generated 0x0 Interrupt after masking, indicates active contribution to the interrupt ball, when set. Status for CYCIRQ timer2: 0: no interrupt pending 1: interrupt generated 0x0 Interrupt after masking, indicates active contribution to the interrupt ball, when set. Status for CYCIRQ timer1: 0: no interrupt pending 1: interrupt generated 0x0 Interrupt after masking, indicates active contribution to the interrupt ball, when set. Status for CYCIRQ timer0: 0: no interrupt pending 1: interrupt generated 32 LM8327 14.2.7 TIMIC - PWM Timer Interrupt Clear Register TABLE 39. TIMIC - PWM Timer Interrupt Clear Register Register - Name Type Register Function 0x7C W This register clears timer and pattern interrupts. CYCIRQ - Interrupt from the timers when PWM cycle is complete (applies to the current PWM command residing in the active command register of a PWM block). CDIRQ - Interrupt from the pattern generator when PWM pattern code is complete (applies to a completed task residing in the script buffer of a PWM block). Bit - Name Bit Default (reserved) 7:6 TIMIC Address Bit Function (reserved) CDIRQ2 5 Clears interrupt CDIRQ timer2: 0: no effect 1: interrupt is cleared. Does not need to be written back to 0 CDIRQ1 4 Clears interrupt CDIRQ timer1: 0: no effect 1: interrupt is cleared. Does not need to be written back to 0 CDIRQ0 3 Clears interrupt CDIRQ timer0: 0: no effect 1: interrupt is cleared. Does not need to be written back to 0 CYCIRQ2 2 Clears interrupt CYCIRQ timer2: 0: no effect 1: interrupt is cleared. Does not need to be written back to 0 CYCIRQ1 1 Clears interrupt CYCIRQ timer1: 0: no effect 1: interrupt is cleared. Does not need to be written back to 0 CYCIRQ0 0 Clears interrupt CYCIRQ timer0: 0: no effect 1: interrupt is cleared. Does not need to be written back to 0 14.2.8 PWMWP - PWM Timer Pattern Pointer Register TABLE 40. PWMWP - PWM Timer Pattern Pointer Register Register - Name Address Type Register Function Pointer to the pattern position inside the configuration register, which will be overwritten by the next write access to be PWMCFG register. NOTE: 1 pattern consist of 2 bytes and not the byte position (low or high). It is incremented by 1 every time a full PWMCFG register access (word) is performed. PWMWP 0x7D R/W Bit - Name Bit Default (reserved) 7 0x0 Bit Function (reserved) 0 POINTER < 32 : timer0 patterns 0 to 31 POINTER[6:0] 6:0 0x0 32 POINTER < 64 : timer1 patterns 0 to 31 64 POINTER < 96 : timer2 patterns 0 to 31 96 POINTER < 128: not valid 33 www.national.com LM8327 14.2.9 PWMCFG - PWM Script Register (Two Byte) TABLE 41. PWMCFG - PWM Script Register Register - Name Type Register Function 0x7E W Two byte pattern storage register for a PWM script command indexed by PWMWP. PWMWP is automatically incremented. To be applied by two consecutive parameter bytes in one I2C Write Transaction. NOTE: Autoincrement is disabled on this register. Address will stay at 0x7E for each word access. Bit - Name Bit Default CMD[15:8] 15:8 High byte portion of a PWM script command. CMD[7:0] 7:0 Low byte portion of a PWM script command. PWMCFG www.national.com Address Bit Function 34 14.3.1 I2CSA - I2C-Compatible ACCESS.bus Slave Address Register TABLE 42. I2CSA - I2C-Compatible ACCESS.bus Slave Address Register Register - Name I2CSA Address Type 0x80 W Register Function I2C-compatible ACCESS.bus Slave Address. The address is internally applied after the next I2C STOP. Bit - Name Bit Default Bit Function SLAVEADDR[7:1] 7:1 0x45 7-bit address field for the I2C-compatible ACCESS.bus slave address. (reserved) 0 (reserved) 14.3.2 MFGCODE - Manufacturer Code Register TABLE 43. MFGCODE - Manufacturer Code Register Register - Name Address Type MFGCODE 0x80 R Bit - Name Bit Default MFGBIT 7:0 0x00 Register Function Manufacturer code of the LM8327. Bit Function 8-bit field containing the manufacturer code. 14.3.3 SWREV - Software Revision Register TABLE 44. SWREV - Software Revision Register Register - Name Type Register Function 0x81 R Software revision code of the LM8327. NOTE: Writing the SW revision with the inverted value triggers a reset (see SWRESET). Bit - Name Bit Default SWBIT 7:0 0xC4 SWREV Address Bit Function 8-bit field containing the SW Revision number. 14.3.4 SWRESET - Software Reset TABLE 45. SWRESET - Software Reset Register Register - Name Address Type SWRESET 0x81 W Bit - Name Bit Default SWBIT 7:0 Register Function Software reset. NOTE: the reset is only applied if the supplied parameter has the inverted value as SWBIT. Reading this register provides the software revision (see Table 44). Bit Function Reapply inverted value for software reset. set). This will reset the slave address back to 0x8A. During an active reset of a module, the LM8327 blocks the access to the module registers. A read will return 0, write commands are ignored. 14.3.5 RSTCTRL - System Reset Register This register allows to reset specific blocks of the LM8327. For global reset of the I/OExpander the I2C command 'General Call reset' is used (see Section 10.1.6 Global Call Re- 35 www.national.com LM8327 NOTE: I2CSA and MFGCODE use the same address. They just differentiate in the access type: * Write - I2CSA * Read - MFGCODE 14.3 INTERFACE CONTROL REGISTERS The following section describes the functions of special control registers provided for the main controller. The manufacturer code MFGCODE and the software revision number SWREV tell the main device which configuration file has to be used for this device. LM8327 TABLE 46. RSTCTRL - System Reset Register Register - Name Address Type RSTCTRL 0x82 R/W Bit - Name Bit Default (reserved) 7:5 Register Function Software reset of specific parts of the LM8327. Bit Function (reserved) IRQRST 4 0x0 Interrupt controller reset. Does not change status on IRQN ball. Only controls IRQ module register. Interrupt status read out is not possible when this bit is set. 0: interrupt controller not reset 1: interrupt controller reset TIMRST 3 0x0 Timer reset for Timers 0, 1, 2: 0: timer not reset 1: timer is reset (reserved) 2 0x0 (reserved) KBDRST 1 0x0 Keyboard interface reset: 0: keyboard is not reset 1: keyboard is reset 0x0 GENIO reset: 0: GENIO not reset 1: GENIO is reset. GPIRST 0 14.3.6 RSTINTCLR - Clear NO Init/Power-On Interrupt Register TABLE 47. RSTINTCLR - Clear NO Init/Power-On Interrupt Register Register - Name Type Register Function 0x84 W This register allows to de-assert the POR/No Init Interrupt set every time the device returns from RESET (either POR, HW or SW Reset), the IRQN line is assigned active (low) and the IRQST.PORIRQ bit is set. Bit - Name Bit Default reserved 7:1 IRQCLR 0 RSTINTCLR Address Bit Function (reserved) 1: Clears the PORIRQ Interrupt signalled in IRQST register. 0: is ignored 14.3.7 CLKMODE - Clock Mode Register TABLE 48. CLKMODE - Clock Mode Register Register - Name Address Type Register Function This register controls the current operating mode of the LM8327 device. CLKMODE 0x88 R/W Bit - Name Bit Default (reserved) 7:2 (reserved) 1:0 Writing to 00 forces the device to immediately enter sleep mode, regardless of any autosleep configuration. Reading this bit returns the current operating mode, which should always be 01. 00: SLEEP Mode 01: Operation Mode 1x: Future modes MODCTL[1:0] www.national.com 0x01 Bit Function 36 LM8327 14.3.8 CLKCFG - Clock Configuration Register TABLE 49. CLKCFG - Clock Configuration Register Register - Name Address Type CLKCFG 0x89 R/W Bit - Name Bit Default (reserved) 7 0x0 (reserved) 6:5 0x2 00: (reserved) 01: use externally generated clock from CLKIN pin as PWM slow clock 1x: use internally generated PWM slow clock 4:0 0x0 (reserved) CLKSRCSEL[1:0] (reserved) Register Function Configures clock sources and power options of the device. NOTE: Don't change while a PWM script is in progress. Bit Function 14.3.9 CLKEN - Clock Enable Register TABLE 50. CLKEN - Clock Enable Register Register - Name Address Type CLKEN 0x8A R/W Bit - Name Bit Default 0x0 Register Function Controls the clock to different functional units. It shall be used to enable the functional blocks globally and independently. Bit Function CLKOUT clock output enable: 00: CLKOUT clock disabled. Fixed to low level. 01: CLKOUT frequency = PWM slow clock frequency. 10: reserved 11: reserved CLKOUTEN 7:6 (reserved) 5:3 TIMEN 2 0x0 PWM Timer 0, 1, 2 clock enable: 0: Timer 0, 1, 2 clock disabled 1: Timer 0, 1, 2 clock enabled. DKBDEN* 1 0x0 Direct Key clock enable (starts/stops direct key scan): 0: Direct Key clock disabled 1: Direct Key clock enabled KBDEN* 0 0x0 Keyboard clock enable (starts/stops key scan): 0: Keyboard clock disabled 1: Keyboard clock enabled (reserved) *Note: Only one of KBDEN or DKBDEN of CLKEN register can be set at a time, since Direct Key functions cannot be used at the same time as Keypad (Matrix). Setting both bits to 1 at the same time will enable only Direct Key. 14.3.10 AUTOSLP - Autosleep Enable Register TABLE 51. AUTOSLP - Autosleep Enable Register Register - Name Address Type Register Function AUTOSLP 0x8B R/W This register controls the Auto Sleep function of the LM8327 device. Bit - Name Bit Default Bit Function (reserved) 7:1 ENABLE 0 (reserved) 0x00 Enables automatic sleep mode after a defined activity time stored in the AUTOSLPTI register: 1: Enable entering auto sleep mode 0: Disable entering auto sleep mode 37 www.national.com LM8327 14.3.11 AUTOSLPTI - Auto Sleep Time Register TABLE 52. AUTOSLPTI - Auto Sleep Time Register Register - Name Address Type Register Function AUTOSLPTIL AUTOSLPTIH 0x8C 0x8D R/W This register defines the activity time. If this time passes without any processing events then the device enters into sleep-mode, but only if AUTOSLP.ENABLE bit is set to 1. Bit - Name Bit Default Bit Function (reserved) 15:11 (reserved) 10:8 7:0 Values of UPTIME[10:0] match to multiples of 4ms: 0x00: no autosleep, regardless if AUTOSLP.ENABLE is set 0x01: 4ms 0x02: 8ms 0x7A: 500 ms 0xFF: 1020 ms (default after reset) 0x100: 1024 ms 0x7FF: 8188 ms UPTIME[10:8] UPTIME[7:0] 0x00 0xFF 14.3.12 IRQST - Global Interrupt Status Register TABLE 53. IRQST - Global Interrupt Status Register Register - Name Address Type Register Function Returns the interrupt status from various on-chip function blocks. If any of the bits is set and an IRQN line is configured, the IRQN line is asserted active IRQST 0x91 R Bit - Name Bit Default Bit Function PORIRQ 7 0x1 Supply failure on VCC. Also power-on is considered as an initial supply failure. Therefore, after power-on, the bit is set. 0: no failure recorded 1: Failure, device was completely reset and requires re-programming. KBDIRQ 6 0x0 Keyboard interrupt (further key selection in keyboard module): 0: inactive 1: active DKBDIRQ 5 0x0 Direct key interrupt (further key selection in direct key module): 0: inactive 1: active (reserved) 4 TIM2IRQ 3 (reserved) 0x0 Timer2 expiry (CDIRQ or CYCIRQ): 0: inactive 1: active TIM1IRQ 2 0x0 Timer1 expiry (CDIRQ or CYCIRQ): 0: inactive 1: active TIM0IRQ 1 0x0 Timer0 expiry (CDIRQ or CYCIRQ): 0: inactive 1: active GPIOIRQ 0 0x0 GPIO interrupt (further selection in GPIO module): 0: inactive 1: active www.national.com 38 14.4.1 GPIO Feature Mapping The LM8327 has a flexible I/O structure which allows user to dynamically assign different functionality to each ball. The functionality of each ball is determined by the complete configuration of the balls. In general the following priority is given: * Direct Key * Keypad * GPIO * PWM With this, each ball will be available as keypad, GPIO, or PWM unless it is specified to be a direct key. The configuration for TABLE 54. Ball Configuration Options BALL Module connectivity GPIOSEL BALLCFG 0x0 0x1 0x2 0x3 0x4 0x5 0x6 KPX[7:0] not used GPIO[7:0] - - - - - - KPY[7:0] not used GPIO[15:8] - - - - - - KPY8 not used GPIO16 - - - - - - KPY9 not used GPIO17 - - - - - - KPY10 not used GPIO18 - - - - - - KPY11 not used GPIO19 - - - - - - PWM0 GPIO20 PWM0 - - - - - - PWM1 GPIO21 PWM1 - - - - - - PWM2 GPIO22 PWM2 - - - - - - EXTIO GPIO23 - - - - - - - 14.4.2 IOCGF - Input/Output Pin Mapping Configuration Register TABLE 55. IOCGF - Input/Output Pin Mapping Configuration Register Register - Name Address Type IOCFG 0xA7 W Bit - Name Bit Default GPIOSEL 7:4 (reserved) 3 BALLCFG 2:0 Register Function Configures usage of PWM[2:0] and EXTIO if not used as primary function. Bit Function TBD (reserved) Select column to configure, see Table 54 39 www.national.com LM8327 direct key, keypad, GPIO or PWM usage is defined by the following registers: * DIRECTn -- This register defines a ball as a direct key. * KBDSIZE and KBDDEDCFG -- Both registers define a ball as either part of the keypad matrix or as dedicated key input. These settings have highest priority and will overwrite settings made in other registers. * IOCFG -- This register is used to define the usage of PWM[2:0] and EXTIO if not configured to be part of the keymatrix, to be used as GPIO. 14.4 GPIO FEATURE CONFIGURATION LM8327 14.4.3 IOPC0 - Pull Resistor Configuration Register 0 TABLE 56. IOPC0 - Pull Resistor Configuration Register 0 Register - Name Address Type IOPC0* OxAA R/W Bit - Name Bit Default KPX7PR[1:0] KPX6PR[1:0] KPX5PR[1:0] KPX4PR[1:0] KPX3PR[1:0] KPX2PR[1:0] KPX1PR[1:0] KPX0PR[1:0] 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Register Function Defines the pull resistor configuration for balls KPX[7:0]. Bit Function 0x3 Resistor enable for KPX7 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPX6 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPX5 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPX4 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPX3 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPX2 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPX1 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPX0 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed * Written values of 0x2 and 0x3 will always be read back as 0x3. 14.4.4 IOPC1 - Pull Resistor Configuration Register 1 TABLE 57. IOPC1 - Pull Resistor Configuration Register 1 Register - Name Address Type IOPC1** 0xAC R/W Bit - Name Bit Default KPY7PR[1:0] www.national.com 15:14 0x3 Register Function Defines the pull resistor configuration for balls KPY[7:0]. Bit Function Resistor enable for KPY7 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 40 KPY6PR[1:0] KPY5PR[1:0] KPY4PR[1:0] KPY3PR[1:0] KPY2PR[1:0] KPY1PR[1:0] KPY0PR[1:0] Address 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Type LM8327 Register - Name Register Function 0x3 Resistor enable for KPY6 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPY5 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPY4 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPY3 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPY2 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPY1 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPY0 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed ** Written values of 0x2 and 0x3 will always be read back as 0x3. 14.4.5 IOPC2 - Pull Resistor Configuration Register 2 TABLE 58. IOPC2 - Pull Resistor Configuration Register 2 Register - Name Address Type Register Function IOPC2*** 0xAE R/W Defines the pull resistor configuration for balls KPY[11:8], PWM[2:0], EXTIO. Bit - Name Bit Default EXTIO[1:0] PWM2[1:0] PWM1[1:0] 15:14 13:12 11:10 Bit Function 0x3 Resistor enable for EXTIO ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for PWM2 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for PWM1 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 41 www.national.com LM8327 Register - Name PWM0[1:0] KPY11PR[1:0] KPY10PR[1:0] KPY9PR[1:0] KPY8PR[1:0] Address 9:8 7:6 5:4 3:2 1:0 Type Register Function 0x3 Resistor enable for PWM0 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPY11 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPY10 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPY9 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed 0x3 Resistor enable for KPY8 ball: 00: no pull resistor at ball 01: pull down resistor programmed 1x: pull up resistor programmed *** Written values of 0x2 and 0x3 will always be read back as 0x3. 14.4.6 GPIOOME0 - GPIO Open Drain Mode Enable Register 0 TABLE 59. GPIOOME0 - GPIO Open Drain Mode Enable Register 0 Register - Name Address Type Register Function GPIOOME0 0xE0 R/W Configures KPX[7:0] for Open Drain or standard output functionality. The Open Drain drive source is configured by GPIOOMS0. Bit - Name Bit Default KPX[7:0]ODE 7:0 0x0 Bit Function Open Drain Enable on KPX[7:0]: 0: full buffer 1: open drain functionality 14.4.7 GPIOOMS0 - GPIO Open Drain Mode Select Register 0 TABLE 60. GPIOOMS0 - GPIO Open Drain Mode Select Register 0 Register - Name Address Type Register Function Configures the Open Drain drive source on KPX[7:0] if selected by GPIOOME0. GPIOOMS0 0xE1 R/W Bit - Name Bit Default Bit Function 0x0 0: Only NMOS transistor is active in output driver stage. Output can be driven to gnd or Hi-Z. 1: Only PMOS transistor is active in output driver stage. Output can be driven to VCC or Hi-Z. KPX[7:0]ODM www.national.com 7:0 42 LM8327 14.4.8 GPIOOME1 - GPIO Open Drain Mode Enable Register 1 TABLE 61. GPIOOME1 - GPIO Open Drain Mode Enable Register 1 Register - Name Address Type Register Function GPIOOME1 0xE2 R/W Configures KPY[7:0] for Open Drain or standard output functionality. The Open Drain drive source is configured by GPIOOMS1. Bit - Name Bit Default KPY[7:0]ODE 7:0 0x0 Bit Function Open Drain Enable on KPY[7:0]: 0: full buffer 1: open drain functionality 14.4.9 GPIOOMS1 - GPIO Open Drain Mode Select Register 1 TABLE 62. GPIOOMS1 - GPIO Open Drain Mode Select Register 1 Register - Name Address Type Register Function Configures the Open Drain drive source on KPY[7:0] if selected by GPIOOME1. GPIOOMS1 0xE3 R/W Bit - Name Bit Default Bit Function 0x0 0: Only NMOS transistor is active in output driver stage. Output can be driven to GND or Hi-Z. 1: Only PMOS transistor is active in output driver stage. Output can be driven to VCC or Hi-Z. KPY[7:0]ODM 7:0 14.4.10 GPIOOME2 - GPIO Open Drain Mode Enable Register 2 TABLE 63. GPIOOME2 - GPIO Open Drain Mode Enable Register 2 Register - Name Address Type Register Function GPIOOME2 0xE4 R/W Configures KPY[11:8], PWM[2:0], EXTIO for Open Drain or standard output functionality. The Open Drain drive source is configured by GPIOOMS2. Bit - Name Bit Default Bit Function EXTIOODM 7 0x0 Open Drain Enable on EXTIO: 0: full buffer 1: open drain functionality PWM[2:0]ODM 6:4 0x0 Open Drain Enable on PWM[2:0]: 0: full buffer 1: open drain functionality 0x0 Open Drain Enable on KPY[11:8]: 0: full buffer 1: open drain functionality KPY[11:8]ODE 3:0 43 www.national.com LM8327 14.4.11 GPIOOMS2 - GPIO Open Drain Mode Select Register 2 TABLE 64. GPIOOMS2 - GPIO Open Drain Mode Select Register 2 Register - Name Address Type Register Function GPIOOMS2 0xE5 R/W Bit - Name Bit Default Bit Function Configures the Open Drain drive source on KPY[11:8], PWM[2:], EXTIO if selected by GPIOOME2. EXTIOODM 7 0x0 0: only NMOS transistor is active in output driver stage. Output can be driven to GND or Hi-Z. 1: only PMOS transistor is active in output driver stage. Output can be driven to GND or Hi-Z. PWM[2:0]ODM 6:4 0x0 same as above KPY[11:8]ODM 3:0 0x0 same as above 14.5 GPIO DATA INPUT/OUTPUT 30124211 14.5.1 GPIOPDATA0 - GPIO Data Register 0 TABLE 65. GPIOPDATA0 - GPIO Data Register 0 Register - Name Address Type Register Function GPIODATA0 0xC0 R/W This register is used for data input/output of KPX[7:0]. Every data I/O is masked with the associated MASK register. If one of the I/Os is defined as output (see Table 68) values written to this register are masked with MASK and then applied to the associated pin. If one of the I/Os is defined as input (see Table 68) values read from this register hold the masked input value of the associated pin. Bit - Name Bit Default Bit Function MASK7 15 0x0 Mask Status for KPX7 when enabled as GPIO: 1: KPX7 enabled 0: KPX7 disabled MASK6 14 0x0 Mask Status for KPX6 when enabled as GPIO: 1: KPX6 enabled 0: KPX6 disabled MASK5 13 0x0 Mask Status for KPX5 when enabled as GPIO: 1: KPX5 enabled 0: KPX5 disabled MASK4 12 0x0 Mask Status for KPX4 when enabled as GPIO: 1: KPX4 enabled 0: KPX4 disabled MASK3 11 0x0 Mask Status for KPX3 when enabled as GPIO: 1: KPX3 enabled 0: KPX3 disabled www.national.com 44 Address Type MASK2 10 0x0 Mask Status for KPX2 when enabled as GPIO: 1: KPX2 enabled 0: KPX2 disabled MASK1 9 0x0 Mask Status for KPX1 when enabled as GPIO: 1: KPX1 enabled 0: KPX1 disabled MASK0 8 0x0 Mask Status for KPX0 when enabled as GPIO: 1: KPX0 enabled 0: KPX0 disabled DATA7 7 0x0 Pin Status for KPX7 when enabled as GPIO. DATA6 6 0x0 Pin Status for KPX6 when enabled as GPIO. DATA5 5 0x0 Pin Status for KPX5 when enabled as GPIO. DATA4 4 0x0 Pin Status for KPX4 when enabled as GPIO. DATA3 3 0x0 Pin Status for KPX3 when enabled as GPIO. DATA2 2 0x0 Pin Status for KPX2 when enabled as GPIO. DATA1 1 0x0 Pin Status for KPX1 when enabled as GPIO. DATA0 0 0x0 Pin Status for KPX0 when enabled as GPIO. LM8327 Register - Name Register Function 14.5.2 GPIOPDATA1 - GPIO Data Register 1 TABLE 66. GPIOPDATA1 - GPIO Data Register 1 Register - Name Address Type Register Function This register is used for data input/output of KPY[7:0]. Every data I/O is masked with the associated MASK register. If one of the I/Os is defined as output (see Table 69) values written to this register are masked with MASK and then applied to the associated pin. If one of the I/Os is defined as input (see Table 69) values read from this register hold the masked input value of the associated pin. GPIODATA1 0xC2 R/W Bit - Name Bit Default Bit Function MASK15 15 0x0 Mask Status for KPY7 when enabled as GPIO: 1: KPY7 enabled 0: KPY7 disabled MASK14 14 0x0 Mask Status for KPY6 when enabled as GPIO: 1: KPY6 enabled 0: KPY6 disabled MASK13 13 0x0 Mask Status for KPY5 when enabled as GPIO: 1: KPY5 enabled 0: KPY5 disabled MASK12 12 0x0 Mask Status for KPY4 when enabled as GPIO: 1: KPY4 enabled 0: KPY4 disabled MASK11 11 0x0 Mask Status for KPY3 when enabled as GPIO: 1: KPY3 enabled 0: KPY3 disabled MASK10 10 0x0 Mask Status for KPY2 when enabled as GPIO: 1: KPY2 enabled 0: KPY2 disabled MASK9 9 0x0 Mask Status for KPY1 when enabled as GPIO: 1: KPY1 enabled 0: KPY1 disabled 45 www.national.com LM8327 Register - Name Address Type Register Function MASK8 8 0x0 Mask Status for KPY0 when enabled as GPIO: 1: KPY0 enabled 0: KPY0 disabled DATA15 7 0x0 Pin Status for KPY7 when enabled as GPIO. DATA14 6 0x0 Pin Status for KPY6 when enabled as GPIO. DATA13 5 0x0 Pin Status for KPY5 when enabled as GPIO. DATA12 4 0x0 Pin Status for KPY4 when enabled as GPIO. DATA11 3 0x0 Pin Status for KPY3 when enabled as GPIO. DATA10 2 0x0 Pin Status for KPY2 when enabled as GPIO. DATA9 1 0x0 Pin Status for KPY1 when enabled as GPIO. DATA8 0 0x0 Pin Status for KPY0 when enabled as GPIO. 14.5.3 GPIOPDATA2 - GPIO Data Register 2 TABLE 67. GPIOPDATA2 - GPIO Data Register 2 Register - Name Address Type Register Function This register is used for data input/output of KPY[11:8], PWM[2:0], EXTIO. Every data I/O is masked with the associated MASK register. If one of the I/Os is defined as output (see Table 70) values written to this register are masked with MASK and then applied to the associated pin. If one of the I/Os is defined as input (see Table 70) values read from this register hold the masked input value of the associated pin. GPIODATA2 0xC4 R/W Bit - Name Bit Default Bit Function MASK23 15 0x0 Mask Status for EXTIO when enabled as GPIO: 1: EXTIO enabled 0: EXTIO disabled MASK22 14 0x0 Mask Status for PWM2 when enabled as GPIO: 1: PWM2 enabled 0: PWM2 disabled MASK21 13 0x0 Mask Status for PWM1 when enabled as GPIO: 1: PWM1 enabled 0: PWM1 disabled MASK20 12 0x0 Mask Status for PWM0 when enabled as GPIO: 1: PWM0 enabled 0: PWM0 disabled MASK19 11 0x0 Mask Status for KPY11 when enabled as GPIO: 1: KPY11 enabled 0: KPY11 disabled MASK18 10 0x0 Mask Status for KPY10 when enabled as GPIO: 1: KPY10 enabled 0: KPY10 disabled MASK17 9 0x0 Mask Status for KPY9 when enabled as GPIO: 1: KPY9 enabled 0: KPY9 disabled MASK16 8 0x0 Mask Status for KPY8 when enabled as GPIO: 1: KPY8 enabled 0: KPY8 disabled DATA23 7 0x0 Pin Status for EXTIO when enabled as GPIO. DATA22 6 0x0 Pin Status for PWM2 when enabled as GPIO. DATA21 5 0x0 Pin Status for PWM1 when enabled as GPIO. DATA20 4 0x0 Pin Status for PWM0 when enabled as GPIO. www.national.com 46 Address Type DATA19 3 0x0 Pin Status for KPY11 when enabled as GPIO DATA18 2 0x0 Pin Status for KPY10 when enabled as GPIO. DATA17 1 0x0 Pin Status for KPY9 when enabled as GPIO. DATA16 0 0x0 Pin Status for KPY8 when enabled as GPIO. LM8327 Register - Name Register Function 14.5.4 GPIOPDIR0 - GPIO Port Direction Register 0 TABLE 68. GPIOPDIR0 - GPIO Port Direction Register 0 Register - Name Address Type GPIODIR0 0xC6 R/W Bit - Name Bit Default KPX[7:0]DIR 7:0 0x00 Register Function Port direction for KPX[7:0]. Bit Function Direction bits for KPX[7:0]: 0: input mode 1: output mode 14.5.5 GPIOPDIR1 - GPIO Port Direction Register 1 TABLE 69. GPIOPDIR1 - GPIO Port Direction Register 1 Register - Name Address Type Register Function GPIODIR1 0xC7 R/W Port direction for KPY[7:0]. Bit - Name Bit Default KPY[7:0]DIR 7:0 0x00 Bit Function Direction bits for KPY[7:0]: 0: input mode 1: output mode 14.5.6 GPIOPDIR2 - GPIO Port Direction Register 2 TABLE 70. GPIOPDIR2 - GPIO Port Direction Register 2 Register - Name Address Type GPIODIR2 0xC8 R/W Bit - Name Bit Default Register Function Port direction for KPY[11:8], PWM[2:0], EXTIO. Bit Function EXTIODIR 7 0x0 Direction bits for EXTIO: 0: input mode 1: output mode PWM[2:0]DIR 6:4 0x0 Direction bits for PWM[2:0:]: 0: input mode 1: output mode KPY[11:8]DIR 3:0 0x00 Direction bits for KPY[11:8]: 0: input mode 1: output mode 47 www.national.com LM8327 14.6 GPIO INTERRUPT CONTROL 14.6.1 GPIOIS0 - Interrupt Sense Configuration Register 0 TABLE 71. GPIOIS0 - Interrupt Sense Configuration Register 0 Register - Name Address Type GPIOIS0 0xC9 R/W Bit - Name Bit Default KPX[7:0]IS 7:0 0x0 Register Function Interrupt type on KPX[7:0]. Bit Function Interrupt type bits for KPX[7:0]: 0: edge sensitive interrupt 1: level sensitive interrupt 14.6.2 GPIOIS1 - Interrupt Sense Configuration Register 1 TABLE 72. GPIOIS1 - Interrupt Sense Configuration Register 1 Register - Name Address Type GPIOIS1 0xCA R/W Bit - Name Bit Default KPY[7:0]IS 7:0 0x0 Register Function Interrupt type on KPY[7:0]. Bit Function Interrupt type bits for KPY[7:0]: 0: edge sensitive interrupt 1: level sensitive interrupt 14.6.3 GPIOIS2 - Interrupt Sense Configuration Register 2 TABLE 73. GPIOIS2 - Interrupt Sense Configuration Register 2 Register - Name Address Type Register Function GPIOIS2 0xCB R/W Bit - Name Bit Default EXTIOIS 7 0x0 Interrupt type bits for EXTIO: 0: edge sensitive interrupt 1: level sensitive interrupt PWM[2:0]IS 6:4 0x0 Interrupt type bits for PWM[2:0:]: 0: edge sensitive interrupt 1: level sensitive interrupt KPY[11:8]IS 3:0 0x0 Interrupt type bits for KPY[11:8]: 0: edge sensitive interrupt 1: level sensitive interrupt Interrupt type on KPY[11:8], PWM[2:0], EXTIO. Bit Function 14.6.4 GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0 TABLE 74. GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0 Register - Name Address Type Register Function GPIOIBE0 0xCC R/W Defines whether an interrupt on KPX[7:0] is triggered on both edges or on a single edge. See Table 77 for the edge configuration. Bit - Name Bit Default KPX[7:0]IBE www.national.com 7:0 0x0 Bit Function Interrupt both edges bits for KPX[7:0]: 0: interrupt generated at the active edge 1: interrupt generated after both edges 48 LM8327 14.6.5 GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1 TABLE 75. GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1 Register - Name Address Type Register Function GPIOIBE1 0xCD R/W Defines whether an interrupt on KPY[7:0] is triggered on both edges or on a single edge. See Table 78 for the edge configuration. Bit - Name Bit Default KPY[7:0]IBE 7:0 0x0 Bit Function Interrupt both edges bits for KPY[7:0]: 0: interrupt generated at the configured edge 1: interrupt generated after both edges 14.6.6 GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2 TABLE 76. GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2 Register - Name Address Type Register Function Defines whether an interrupt on KPY[11:8], PWM[2:0], EXTIO is triggered on both edges or on a single edge. See Table 79 for the edge configuration. GPIOIBE2 0xCE R/W Bit - Name Bit Default Bit Function EXTIOIBE 7 0x0 Interrupt both edges bits for EXTIO: 0: interrupt generated at the active edge 1: interrupt generated after both edges PWM[2:0]IBE 6:4 0x0 Interrupt both edges bits for PWM[2:0:]: 0: interrupt generated at the active edge 1: interrupt generated after both edges KPY[11:8]IBE 3:0 0x0 Interrupt both edges bits for KPY[11:8]: 0: interrupt generated at the active edge 1: interrupt generated after both edges 14.6.7 GPIOIEV0 - GPIO Interrupt Edge Select Register 0 TABLE 77. GPIOIEV0 - GPIO Interrupt Edge Select Register 0 Register - Name Address Type Register Function GPIOIEV0 0xCF R/W Select Interrupt edge for KPX[7:0]. Bit - Name Bit Default KPX[7:0]EV 7:0 0x0 Bit Function Interrupt edge select from KPX[7:0]: 0: interrupt at low level or falling edge 1: interrupt at high level or rising edge 14.6.8 GPIOIEV1 - GPIO Interrupt Edge Select Register 1 TABLE 78. GPIOIEV1 - GPIO Interrupt Edge Select Register 1 Register - Name Address Type Register Function GPIOIEV1 0xD0 R/W Select Interrupt edge for KPY[7:0]. Bit - Name Bit Default KPY[7:0]EV 7:0 0x0 Bit Function Interrupt edge select from KPY[7:0]: 0: interrupt at low level or falling edge 1: interrupt at high level or rising edge 49 www.national.com LM8327 14.6.9 GPIOIEV2 - GPIO Interrupt Edge Select Register 2 TABLE 79. GPIOIEV2 - GPIO Interrupt Edge Select Register 2 Register - Name Address Type Register Function GPIOIEV2 0xD1 R/W Select Interrupt edge for KPY[11:8], PWM[2:0], EXTIO. Bit - Name Bit Default Bit Function EXTIOEV 7 0x0 Interrupt edge select from EXTIO: 0: interrupt at low level or failig edge 1: interrupt at high level or rising edge PWM[2:0]EV 6:4 0x0 Interrupt edge select from PWM[2:0:]: 0: interrupt at low level or failig edge 1: interrupt at high level or rising edge KPY[11:8]EV 3:0 0x0 Interrupt edge select from KPY[11:8]: 0: interrupt at low level or falling edge 1: interrupt at high level or rising edge 14.6.10 GPIOIE0 - GPIO Interrupt Enable Register 0 TABLE 80. GPIOIE0 - GPIO Interrupt Enable Register 0 Register - Name Address Type GPIOIE0 0xD2 R/W Bit - Name Bit Default KPX[7:0]IE 7:0 0x0 Register Function Enable/disable interrupts on KPX[7:0]. Bit Function Interrupt enable on KPX[7:0]: 0: disable interrupt 1: enable interrupt 14.6.11 GPIOIE1 - GPIO Interrupt Enable Register 1 TABLE 81. GPIOIE1 - GPIO Interrupt Enable Register 1 Register - Name Address Type GPIOIE1 0xD3 R/W Bit - Name Bit Default KPY[7:0]IE 7:0 0x0 Register Function Enable/disable interrupts on KPY[7:0] Bit Function Interrupt enable on KPY[7:0]: 0: disable interrupt 1: enable interrupt 14.6.12 GPIOIE2 - GPIO Interrupt Enable Register 2 TABLE 82. GPIOIE2 - GPIO Interrupt Enable Register 2 Register - Name Address Type GPIOIE2 0xD4 R/W Bit - Name Bit Default Register Function Enable/disable interrupts on KPY[11:8], PWM[2:0], EXTIO. Bit Function EXTIOIE 7 0x0 Interrupt enable on EXTIO: 0: disable interrupt 1: enable interrupt PWM[2:0]IE 6:4 0x0 Interrupt enable on PWM[2:0:]: 0: disable interrupt 1: enable interrupt www.national.com 50 Address Type KPY[11:8]IE 3:0 0x0 LM8327 Register - Name Register Function Interrupt enable on KPY[11:8]: 0: disable interrupt 1: enable interrupt 14.6.13 GPIOIC0 - GPIO Clear Interrupt Register 0 TABLE 83. GPIOIC0 - GPIO Clear Interrupt Register 0 Register - Name Address Type GPIOIC0 0xDC W Bit - Name Bit Default KPX[7:0]IC 7:0 Register Function Clears the interrupt on KPX[7:0]. Bit Function Clear Interrupt on KPX[7:0]. 0: no effect 1: Clear corresponding interrupt 14.6.14 GPIOIC1 - GPIO Clear Interrupt Register 1 TABLE 84. GPIOIC1 - GPIO Clear Interrupt Register 1 Register - Name Address Type GPIOIC1 0xDD W Bit - Name Bit Default KPY[7:0]IC 7:0 Register Function Clears the interrupt on KPY[7:0]. Bit Function Clear Interrupt on KPY[7:0]. 0: no effect 1: Clear corresponding interrupt 14.6.15 GPIOIC2 - GPIO Clear Interrupt Register 2 TABLE 85. GPIOIC2 - GPIO Clear Interrupt Register 2 Register - Name Address Type GPIOIC2 0xDE W Bit - Name Bit Default Register Function Clears the interrupt on KPY[11:8], PWM[2:0], EXTIO. Bit Function EXTIOIC 7 Clear interrupt on EXTIO: 0: no effect 1: Clear corresponding interrupt PWM[2:0]IC 6:4 Clear interrupt on PWM[2:0]: 0: no effect 1: Clear corresponding interrupt KPY[11:8]IC 3:0 Clear Interrupt on KPY[11:8]: 0: no effect 1: Clear corresponding interrupt 51 www.national.com LM8327 14.7 GPIO INTERRUPT STATUS 14.7.1 GPIORIS0 - Raw Interrupt Status Register 0 TABLE 86. GPIORIS0 - Raw Interrupt Status Register 0 Register - Name Address Type GPIORIS0 0xD6 R Bit - Name Bit Default KPX[7:0]RIS 7:0 0x0 Register Function Raw interrupt status on KPX[7:0]. Bit Function Raw Interrupt status data on KPX[7:0]: 0: no interrupt condition at GPIO 1: interrupt condition at GPIO 14.7.2 GPIORIS1 - Raw Interrupt Status Register 1 TABLE 87. GPIORIS1 - Raw Interrupt Status Register 1 Register - Name Address Type GPIORIS1 0xD7 R Bit - Name Bit Default KPY[7:0]RIS 7:0 0x0 Register Function Raw interrupt status on KPY[7:0]. Bit Function Raw Interrupt status data on KPY[7:0]: 0: no interrupt condition at GPIO 1: interrupt condition at GPIO 14.7.3 GPIORIS2 - Raw Interrupt Status Register 2 TABLE 88. GPIORIS2 - Raw Interrupt Status Register 2 Register - Name Address Type Register Function GPIORIS2 0xD8 R Bit - Name Bit Default EXTIORIS 7 0x0 Raw Interrupt status data on EXTIO: 0: no interrupt condition at GPIO 1: interrupt at GPIO is active PWM[2:0]RIS 6:4 0x0 Raw Interrupt status data on PWM[2:0]: 0: no interrupt condition at GPIO 1: interrupt at GPIO is active KPY[11:8]RIS 3:0 0x0 Raw Interrupt status data on KPY[11:8]: 0: no interrupt condition at GPIO 1: interrupt condition at GPIO Raw interrupt status on KPY[11:8], PWM[2:0], EXTIO. Bit Function 14.7.4 GPIOMIS0 - Masked Interrupt Status Register 0 TABLE 89. GPIOMIS0 - Masked Interrupt Status Register 0 Register - Name Address Type GPIOMIS0 0xD9 R Bit - Name Bit Default KPX[7:0]MIS 7:0 0x0 www.national.com Register Function Masked interrupt status on KPX[7:0]. Bit Function Masked Interrupt status data on KPX[7:0]: 0: no interrupt contribution from GPIO 1: interrupt GPIO is active 52 LM8327 14.7.5 GPIOMIS1 - Masked Interrupt Status Register 1 TABLE 90. GPIOMIS1 - Masked Interrupt Status Register 1 Register - Name Address Type GPIOMIS1 0xDA R Bit - Name Bit Default KPY[7:0]MIS 7:0 0x0 Register Function Masked interrupt status on KPY[7:0]. Bit Function Masked Interrupt status data on KPY[7:0]: 0: no interrupt contribution from GPIO 1: interrupt GPIO is active 14.7.6 GPIOMIS2 - Masked Interrupt Status Register 2 TABLE 91. GPIOMIS2 - Masked Interrupt Status Register 2 Register - Name Address Type GPIOMIS2 0xDB R Bit - Name Bit Default Register Function Masked interrupt status on KPY[11:8], PWM[2:0], EXTIO. Bit Function EXTIOMIS 7 0x0 Masked Interrupt status data on EXTIO: 0: no interrupt condition from GPIO 1: interrupt at GPIO is active PWM[2:0]MIS 6:4 0x0 Masked Interrupt status data on PWM[2:0]: 0: no interrupt condition from GPIO 1: interrupt at GPIO is active 0x0 Masked Interrupt status data on KPY[11:8]: 0: no interrupt contribution from GPIO 1: interrupt GPIO is active KPY[11:8]MIS 3:0 14.8 GPIO WAKE-UP CONTROL 14.8.1 GPIOWAKE0 - GPIO Wake-Up Register 0 TABLE 92. GPIOWAKE0 - GPIO Wake-Up Register 0 Register - Name Address Type GPIOWAKE0 0xE9 R/W Bit - Name Bit Default KPX[7:0]WAKE 7:0 0x0 Register Function Configures wake-up conditions for KPX[7:0]. Each bit corresponds to a ball. When bit set, the corresponding ball contributes to wakeup from auto sleep mode. Bit Function Wakeup enable on KPX[7:0]: 0: disable wakeup 1: enable wakeup 14.8.2 GPIOWAKE1 - GPIO Wake-Up Register 1 TABLE 93. GPIOWAKE1 - GPIO Wake-Up Register 1 Register - Name Address Type GPIOWAKE1 0xEA R/W Bit - Name Bit Default KPY[7:0]WAKE 7:00 0x0 Register Function Configures wake-up conditions for KPY[7:0]. Each bit corresponds to a ball. When bit set, the corresponding ball contributes to wakeup from auto sleep mode. Bit Function Wakeup enable on KPX[7:0]: 0: disable wakeup 1: enable wakeup 53 www.national.com LM8327 14.8.3 GPIOWAKE2 - GPIO Wake-Up Register 2 TABLE 94. GPIOWAKE2 - GPIO Wake-Up Register 2 Register - Name Address Type GPIOWAKE2 0xEB R/W Bit - Name Bit Default Register Function Configures wake-up conditions for KPY[11:8], PWM[2:0}, EXTIO. Each bit corresponds to a ball. When bit set, the corresponding ball contributes to wakeup from auto sleep mode. Bit Function EXTIOWAKE 7 0x0 Wakeup enable on EXTIO: 0: disable wakeup 1: enable wakeup PWM[2:0]WAKE 6:4 0x0 Wakeup enable on PWM[2:0]: 0: disable wakeup 1: enable wakeup KPY[11:8]WAKE 3:0 0x0 Wakeup enable on KPY[11:8]: 0: disable wakeup 1: enable wakeup 14.9 DIRECT KEY REGISTERS AND DIRECT KEY CONTROL Direct Key selection and control registers are mapped in the address range from 0xE6 to 0xF3. This paragraph describes the functions of the associated registers down to the bit level. 14.9.1 DEVTCODE - Direct Key Event Code Register TABLE 95. DEVTCODE - Direct Key Event Code Register Register - Name Type Register Function 0xE6 R With this register a FIFO buffer is addressed storing up to 15 consecutive events. Reading the value 0x3F from this address means that the FIFO buffer is empty and a key is not pressed. Reading the value 0x1F form this address means that the FIFO buffer is empty and a key is still pressed. DKBDRIS.DREVTINT bit is cleared as soon as this FIFO reaches its empty state. See further details below. NOTE: Auto increment is disabled on this register. Multi-byte read will always read from the same address. Bit - Name Bit Default (reserved) 7:6 DEVTCODE Address DKEYSTAT 5 0x0 DKEYCODE 4:0 0x1F www.national.com Bit Function (reserved) This bit indicates whether the direct key event was a key press or a key release event. 0: direct key was pressed 1: direct key was released. Column index of key is pressed (0...24, 25 for Direct keys). 54 LM8327 14.9.2 DBOUNCE - Direct Key Debounce Time Register TABLE 96. DBOUNCE - Direct Key Debounce Time Register Register - Name Address Type DBOUNCE 0xE7 R/W Bit - Name Bit Default (reserved) 7:5 (reserved) 4:0 De-bounce time for direct keys. Values of DEBOUNCE[4:0] match to multiples of 3ms: 0x00: 0ms 0x01: 3ms 0x02: 6ms 0x03: 9ms 0x1F: 93 ms DEBOUNCE 0x03 Register Function Time between first detection of key and final sampling of key. Bit Function bits take priority over anything else. Direct key bits must be cleared before IOCFG is accessed to set other functions for the pins. 14.9.3 DIRECT0 - Direct Key Register 0 The direct key settings. If not enabled as a direct key, then that pin follows the IOCFG and keypad registers. Direct Key TABLE 97. DIRECT0 - Direct Key Register 0 Register - Name Address Type DIRECT0 0xEC R/W Bit - Name Bit Default DK[7:0] 7:0 0xFF Register Function Enable Direct Key connections for DK[7:0]. Bit Function 1: Direct Key connection 0: Direct Key follows IOCFG and keypad registers. 14.9.4 DIRECT1 - Direct Key Register 1 TABLE 98. DIRECT1 - Direct Key Register 1 Register - Name Address Type Register Function DIRECT1 0xED R/W Enable Direct Key connections for DK[15:8]. Bit - Name Bit Default DK[15:8] 7:0 0xFF Bit Function 1: Direct Key connection 0: Direct Key follows IOCFG and keypad registers. 14.9.5 DIRECT2 - Direct Key Register 2 TABLE 99. DIRECT2 - Direct Key Register 2 Register - Name Address Type DIRECT2 0xEE R/W Bit - Name Bit Default DK[23:16] 7:0 0xFF Register Function Enable Direct Key connections for DK[23:16]. Bit Function 1: Direct Key connection 0: Direct Key follows IOCFG and keypad registers. 55 www.national.com LM8327 14.9.6 DIRECT3 - Direct Key Register 3 TABLE 100. DIRECT3 - Direct Key Register 3 Register - Name Address Type DIRECT3 0xEF R/W Bit - Name Bit Default (reserved) 7:2 DK[25:24] 1:0 Register Function Enable Direct Key connections for DK[25:24]. Bit Function (reserved) 0x03 1: Direct Key connection 0: Direct Key follows IOCFG and keypad registers. 14.9.7 DKBDRIS - Direct Key Raw Interrupt Status Register TABLE 101. DKBDRIS - Direct Key Raw Interrupt Status Register Register - Name Address Type DKBDRIS 0xF0 R Bit - Name Bit Default (reserved) 7:2 DRELINT DREVTINT 1 0 Register Function Returns the status of stored direct key interrupts. Bit Function (reserved) 0x0 Raw event lost interrupt. More than 8 direct key events have been detected and caused the event buffer to overflow. This bit is cleared by setting bit DEVTIC of the DKBDIC register. 0x0 Raw direct key event interrupt. At least one direct key press or direct key release is in the direct key event buffer. Reading from DEVTCODE until the buffer is empty will automatically clear this interrupt. 14.9.8 DKBDMIS - Direct Key Masked Interrupt Status Register TABLE 102. DKBDMIS - Direct Key Masked Interrupt Status Register Register - Name Type Register Function 0xF1 R Returns the status of masked direct key interrupts after masking with the DKBDMSK register. Bit - Name Bit Default (reserved) 7:2 DKBDMIS DMELINT DMEVTINT www.national.com Address 1 0 Bit Function (reserved) 0x0 Masked event lost interrupt. More than 8 direct key events have been detected and caused the event buffer to overflow. This bit is cleared by setting bit DEVTIC of the DKBDIC register. 0x0 Masked direct key event interrupt. At least one direct key press or direct key release is in the direct key event buffer. Reading from DEVTCODE until the buffer is empty will automatically clear this interrupt. 56 LM8327 14.9.9 DKBDIC - Direct Key Interrupt Clear Register TABLE 103. DKBDIC - Direct Key Interrupt Clear Register Register - Name Address Type DKBDIC 0xF2 W Bit - Name Bit Default (reserved) 7:1 DEVTIC 0 Register Function Setting these bits clears direct key active interrupts. Bit Function (reserved) Clear event buffer and corresponding interrupts DREVTINT and DRELINT by writing a '1' to this bit position. 14.9.10 DKBDMSK - Direct Key Interrupt Mask Register TABLE 104. DKBDMSK - Direct Key Interrupt Mask Register Register - Name Type Register Function 0xF3 R/W Configures masking of direct key interrupts. Masked interrupts do not trigger an event of the interrupt output. Bit - Name Bit Default (reserved) 7:2 MSKELINT 1 0x1 0: direct key event lost interrupt DRELINT triggers IRQ line 1: direct key event lost interrupt DRELINT is masked. MSKEINT 0 0x1 0: direct key event interrupt DREVTINT triggers IRQ line 1: direct key event interrupt DREVTINT is masked. DKBDMSK Address Bit Function (reserved) 57 www.national.com LM8327 Maximum Input Current Without Latchup ESD Protection Level (Human Body Model) (Machine Model) (Charge Device Model) Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) Storage Temperature Range 15.0 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Generic IOs Voltage at Backdrive/Overvoltage IOs -0.3V to 2.2V -0.2V to VCC +0.2V 100 mA 2kV 200V 750V 100 mA 100 mA -65C to +140C -0.3V to +4.25V 16.0 Electrical Characteristics TABLE 105. DC ELECTRICAL CHARACTERISTICS Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. (Temperature: -40C TA +85C, unless otherwise specified) Parameter Conditions Operating Voltage (VCC) Min Max Units 1.98 V 3.60 V 1.2 2.0 mA VCC = 1.8V, TA = 25C Internal Clock = OFF, no internal functional blocks running <9 40 A Internal Clock = ON, no internal functional blocks running 1 Core Supply Voltage Typ 1.62 Maximum Input voltage for Backdrive/Overvoltage IOs Internal Clock = ON, all internal functional blocks running, No loads on pins, VCC = 1.8V, TC = 1s Supply Current (IDD) (Note 2, Note 3) TA = 25C Sleep Mode HALT Current (IHALT) (Note 4) IDLE Current mA TABLE 106. AC ELECTRICAL CHARACTERISTICS (Temperature: -40C TA +85C) Data sheet specification limits are guaranteed by design, test, or statistical analysis. Parameter Conditions System Clock Frequency System Clock Period (mclk) Internal RC Internal RC Oscillator (tC) Min Max Units 1.62V VCC 1.98V MHz ns 1.62V VCC 1.98V 0.95 s Internal RC Oscillator Frequency Variation 7 ACCESS.bus Input Signals Bus Free Time Between Stop and Start Condition (tBUFi) (Note 5) % 16 SCL Setup Time (tCSTOsi) (Note 5) Before Stop Condition 8 SCL Hold Time (tCSTRhi) (Note 5) After Start Condition 8 SCL Setup Time (tCSTRsi) (Note 5) Before Start Condition 8 Data High Setup Time (tDHCsi) (Note 5) (Note 6) Data Low Setup Time (tDLCsi) (Note 5) (Note 6) SCL Low Time (tSCLlowi) (Note 5) Before SCL Rising Edge (RE) 2 Before SCL RE 2 After SCL Falling Edge (FE) 12 SCL High Time (tSCLhighi) (Note 5) (Note 6) SDA Hold Time (tSDAhi) (Note 5) After SCL FE 12 After SCL FE 0 SDA Setup Time (tSDAsi) (Note 5) (Note 6) Before SCL RE 2 www.national.com Typ 10.5 95 58 mclk ACCESS.bus Output Signals SDA Hold Time (tSDAho) (Note 5) Conditions After SCL Falling Edge Min Typ Max 2 Units mclk TABLE 107. GENERAL GPIO CHARACTERISTICS Characteristics for all pins except CLKIN, IRQN/KPY11/PWM2, SDA, and SCL in GPIO mode. Parameter Conditions VIH (Min. Input High Voltage) Min Typ Max 0.7xVCC Units V VIL (Max. Input Low Voltage) 0.3xVCC V -16 mA ISource VCC = 1.62 VOH = 0.7xVCC ISink VCC = 1.62 VOL = 0.3xVCC 16 IPU (Weak Pull-UP Current) (Note 8) VOUT = 0V -30 -160 IPD (Weak Pull-Down Current) (Note 8) VOUT = VCC 30 160 IOZ (Input Leakage Current) GPIO output disabled Vpin = 0 to VCC 2 tRise/Fall (Max. Rise and Fall times) (Note 5) CLOAD = 50 pF 15 ns Max Units mA Allowable Sink current per pin (Note 7) 16 mA A TABLE 108. BACKDRIVE/OVERVOLTAGE I/O DC CHARACTERISTICS Characteristics for pins CLKIN, IRQN/KPY11/PWM2, SDA and SCL Parameter Conditions VIH (Min. Input High Voltage) Min Typ 0.7xVCC VIL (Max. Input Low Voltage) 0.3xVCC V ISource VCC = 1.62V VOH = 1.15V ISink1 (as GPIO) VCC = 1.62V VOL = 0.4V 12 mA ISink2 (as ACCESS.bus) VCC = 1.62V VOL = 0.4V 3 mA ISink3 (as ACCESS.bus) VCC = 1.62V VOL = 0.6V 4 mA -6 Allowable Sink current per pin (Note 7) 12 IPU (Weak Pull-UP Current) (Note 8) VOUT = 0V -7 -40 IPD (Weak Pull-Down Current) (Note 8) VOUT = VCC 7 40 IOZ1 (Input Leakage Current) (Note 9) IOZ2 (Input Backdrive Leakage Current) GPIO output disabled VCC = 1.62V to 1.98V mA mA A Vpin = 0 to VCC 2 Vpin = VCC to 3.6V 10 0 VCC 0.5V Vpin = 0 to 3.6V 10 A Max Units TABLE 109. BACKDRIVE/OVERVOLTAGE I/O AC CHARACTERISTICS Characteristics for pins CLKIN, IRQN/KPY11/PWM2, SDA and SCL Parameter Conditions tRise/Fall (Max. Rise and Fall time) (Note 5) CLOAD=50 pF @ 1MHz tFall (Max. Fall time) as ACCESS.bus (SDA, SCL only) (Note 5) CLOAD=10 pF to 100 pF VIHmin to VILmax 59 Min Typ 70 ns 10 120 www.national.com LM8327 Parameter LM8327 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. Note 2: Supply and IDLE current is measured with inputs connected to VCC and outputs driven low but not connected to a load. Note 3: Values are estimates. Values will be updated after characterization is completed. Note 4: In sleep mode, the internal clock is switched off. Supply current in sleep mode is measured with inputs connected to VCC and outputs driven low but not connected to a load. Note 5: Guaranteed by design, not tested. Note 6: The ACCESS.bus interface implements and meets the timings necessary for interface to the I2C and SMBus protocols at logic levels. The bus drivers have open-drain outputs for bidirectional operation. Due to Internal RC Oscillator Frequency Variation, this specification may not meet the AC timing and current/ voltage drive requirements of the full-bus specifications. Note 7: The sum of all I/O sink/source current must not exceed the maximum total current into VCC and out of GND as specified in the absolute maximum ratings. Note 8: This is the internal weak pull-up (pull-down) current when driver output is disabled. If enabled, during receiving mode, this is the current required to switch the input from one state to another. Note 9: IOZ1 for CLKIN is max 60 A if VPIN > VCC because the weak pull-down is enabled. www.national.com 60 LM8327 17.0 Registers 17.1 REGISTER MAPPING 17.1.1 Keyboard Registers Table 110 shows the register map for keyboard functionality. In addition to Global Call Reset (see Section 10.1.6 Global Call Reset) or Software Reset using SWRESET (see Table 45), these registers are reset to 0x00 values by a module reset using RSTCTRL.KBDRST and should be rewritten for desired settings (see RSTCTRL - Section 14.3.5 RSTCTRL - System Reset Register). TABLE 110. Register Map for Keyboard Functionality Register Name Description Register File Address Register Type ACCESS Size Default value Next RF Address KBDSETTLE Keypad Settle Time 0x01 R/W byte 0x80 0x02 KBDBOUNCE Keypad Debounce Time 0x02 R/W byte 0x80 0x03 KBDSIZE Keypad Size Configuration 0x03 R/W byte 0x22 0x04 KBDDEDCFG0 Keypad Dedicated Key 0 0x04 R/W byte 0xFF 0x05 KBDDEDCFG1 Keypad Dedicated Key 1 0x05 R/W byte 0xFF 0x06 KBDRIS Keypad Raw Interrupt Status 0x06 R byte 0x00 0x07 KBDMIS Keypad Masked Interrupt Status 0x07 R byte 0x00 0x08 KBDIC Keypad Interrupt Clear 0x08 W byte KBDMSK Keypad Interrupt Mask 0x09 R byte 0x0C 0x0A KBDCODE0 Keypad Code 0 0x0B R byte 0x7F 0x0C KBDCODE1 Keypad Code 1 0x0C R byte 0x7F 0x0D KBDCODE2 Keypad Code 2 0x0D R byte 0x7F 0x0E KBDCODE3 Keypad Code 3 0x0E R byte 0x7F 0x0F EVTCODE Key Event Code 0x10 R byte 0x7F 0x10 0x09 set), these registers are reset to 0x00 values by a module reset using RSTCTRL.KBDRST and should be rewritten for desired settings (see RSTCTRL, Section 14.3.5 RSTCTRL System Reset Register). 17.1.2 Direct Key Registers Table 111 shows the register map for keyboard functionality when using direct keys. In addition to Global Call Reset (see Section 10.1.6 Global Call Reset) or Software Reset using SWRESET (see Section 14.3.4 SWRESET - Software Re- TABLE 111. Register Map for Direct Key Registers Description Register File Address Register Type ACCESS Size Default value Next RF Address DEVTCODE Direct Key Event Code 0xE6 R byte 0x3F 0xE6 DBOUNCE Direct Key Debounce Time 0xE7 R/W byte 0x03 0xE8 DIRECT0 Direct Key Config 0 0xEC R/W byte 0xFF 0xED DIRECT1 Direct Key Config 1 0xED R/W byte 0xFF 0xEE DIRECT2 Direct Key Config 2 0xEE R/W byte 0xFF 0xEF DIRECT3 Direct Key Config 3 0xEF R/W byte 0x03 0xF0 DKBDRIS Direct Key Raw Interrupt Status 0xF0 R byte 0x00 0xF1 DKBDMIS Direct Key Masked Int. Status 0xF1 R byte 0x00 0xF2 DKBDIC Direct Key Interrupt Clear 0xF2 W byte DKBDMSK Direct Key Interrupt Mask 0xF3 R/W byte Register Name 61 0xF3 0x03 0xF4 www.national.com LM8327 17.1.3 PWM Timer Registers Table 112 shows the register map for PWM Timer functionality. In addition to Global Call Reset (see Section 10.1.6 Global Call Reset) or Software Reset using SWRESET (see Table 45), these registers are reset to default values by a module reset using RSTCTRL.TIMRST (see Section 14.3.5 RSTCTRL - System Reset Register). TABLE 112. Register Map for PWM Timer Functionality Description Register File Address Register Type ACCESS Size Default value Next RF Address PWM Timer Configuration 0 0x60 R/W byte 0x00 0x61 PWMCFG0 PWM Configuration 0 0x61 R/W byte 0x00 0x62 TIMSCAL0 PWM Timer Prescaler 0 0x62 R/W byte 0x00 0x63 TIMCFG1 PWM Timer Configuration 1 0x68 R/W byte 0x00 0x69 PWMCFG1 PWM Configuration 1 0x69 R/W byte 0x00 0x6A TIMSCAL1 PWM Timer Prescaler 1 0x6A R/W byte 0x00 0x6B TIMCFG2 PWM Timer Configuration 2 0x70 R/W byte 0x00 0x71 PWMCFG2 PWM Configuration 2 0x71 R/W byte 0x00 0x72 TIMSCAL2 PWM Timer Prescaler 2 0x72 R/W byte 0x00 0x73 TIMSWRES PWM Timer SW Reset 0x78 W byte TIMRIS PWM Timer Interrupt Status 0x7A R byte 0x00 0x7B TIMMIS PWM Timer Masked Int. Status 0x7B R byte 0x00 0x7C Timer Interrupt Clear 0x7C W byte PWMWP PWM Command Write Pointer 0x7D R/W byte PWMCFG PWM Command Script 0x7E W word Register Name TIMCFG0 TIMIC www.national.com 62 0x79 0x7D 0x00 0x7E 0x7F TABLE 113. Register Map for System Control Functionality Register Name Description Register File Address Register Type ACCESS Size Default value Next RF Address I2CSA I2C Slave Address 0x80 W byte 0x8A 0x81 MFGCODE Manufacturer Code 0x80 R byte 0x00 0x81 0xC4 0x82 SWREV SW Revision 0x81 R byte SWRESET SW Reset 0x81 W byte RSTCTRL System Reset 0x82 R/W byte Clear No Init/Power On Interrupt 0x84 W byte RSTINTCLR CLKMODE CLKCFG CLKEN AUTOSLP 0x82 0x00 0x83 0x85 Clock Mode 0x88 R/W byte 0x01 0x89 Clock Configuration 0x89 R/W byte 0x40 0x8A Clock Enable 0x8A R/W byte 0x00 0x8B Auto Sleep Enable 0x8B R/W byte 0x00 0x8C AUTOSLPTI Auto Sleep Time 0x8C R/W word 0x00FF 0x8D MMASTER Multi-Master Mode 0xF4 R/W byte 0x00 0xF5 Table 45), these registers are reset to default values by a module reset using RSTCTRL.IRQRST (see Section 14.3.5 RSTCTRL - System Reset Register). 17.1.5 Global Interrupt Registers Table 114 shows the register map for global interrupt functionality. In addition to Global Call Reset (see Section 10.1.6 Global Call Reset) or Software Reset using SWRESET (see TABLE 114. Register Map for Global Interrupt Functionality Register Name IRQST Description Register File Address Register Type ACCESS Size Default value Next RF Address Global Interrupt Status 0x91 R byte 0x80 0x92 these registers are reset to 0x00 values by a module reset using RSTCTRL.GPIRST and should be rewritten for desired settings (see Section 14.3.5 RSTCTRL - System Reset Register). 17.1.6 GPIO Registers Table 115 shows the register map for GPIO functionality. In addition to Global Call Reset (see Section 10.1.6 Global Call Reset) or Software Reset using SWRESET (see Table 45), TABLE 115. Register Map for GPIO Functionality Register Name Description Register File Address Register Type ACCESS Size Default value Next RF Address IOCFG I/O Pin Mapping Configuration 0xA7 W byte IOPC0 Pull Resistor Configuration 0 0xAA R/W word 0xFFFF 0xAB IOPC1 Pull Resistor Configuration 1 0xAC R/W word 0xFFFF 0xAD IOPC2 Pull Resistor Configuration 2 0xAE R/W word 0xFFFF 0xAF GPIODATA0 GPIO I/O Data 0 0xC0 R/W byte 0x00 0xC1 GPIOMASK0 GPIO I/O Mask 0 0xC1 W byte GPIODATA1 GPIO I/O Data 1 0xC2 R/W byte GPIOMASK1 GPIO I/O Mask 1 0xC3 W byte GPIODATA2 GPIO I/O Data 2 0xC4 R/W byte GPIOMASK2 GPIO I/O Mask 2 0xC5 W byte GPIODIR0 GPIO I/O Direction 0 0xC6 R/W byte 0x00 0xC7 GPIODIR1 GPIO I/O Direction 1 0xC7 R/W byte 0x00 0xC8 63 0xA8 0xC2 0x00 0xC3 0xC4 0x00 0xC5 0xC6 www.national.com LM8327 TRL - System Reset Register). These registers can only be reset to default values by a Global Call Reset (see Section 10.1.6 Global Call Reset) or by a complete Software Reset using SWRESET (seeTable 45). 17.1.4 System Registers Table 113 shows the register map for general system registers. These registers are not affected by any of the module resets addressed by RSTCTRL (see Section 14.3.5 RSTC- LM8327 Register Name GPIODIR2 Description Register File Address Register Type ACCESS Size Default value Next RF Address GPIO I/O Direction 2 0xC8 R/W byte 0x00 0xC9 GPIOIS0 GPIO Int Sense Config 0 0xC9 R/W byte 0x00 0xCA GPIOIS1 GPIO Int Sense Config 1 0xCA R/W byte 0x00 0xCB GPIOIS2 GPIO Int Sense Config 2 0xCB R/W byte 0x00 0xCC GPIOIBE0 GPIO Int Both Edges Config 0 0xCC R/W byte 0x00 0xCD GPIOIBE1 GPIO Int Both Edges Config 1 0xCD R/W byte 0x00 0xCE GPIOIBE2 GPIO Int Both Edges Config 2 0xCE R/W byte 0x00 0xCF GPIOIEV0 GPIO Int Edge Select 0 0xCF R/W byte 0x00 0xD0 GPIOIEV1 GPIO Int Edge Select 1 0xD0 R/W byte 0x00 0xD1 GPIOIEV2 GPIO Int Edge Select 2 0xD1 R/W byte 0x00 0xD2 GPIOIE0 GPIO Interrupt Enable 0 0xD2 R/W byte 0x00 0xD3 GPIOIE1 GPIO Interrupt Enable 1 0xD3 R/W byte 0x00 0xD4 GPIOIE2 GPIO Interrupt Enable 2 0xD4 R/W byte 0x00 0xD5 GPIORIS0 GPIO Raw Int Status 0 0xD6 R byte 0x00 0xD7 GPIORIS1 GPIO Raw Int Status 1 0xD7 R byte 0x00 0xD8 GPIORIS2 GPIO Raw Int Status 2 0xD8 R byte 0x00 0xD9 GPIOMIS0 GPIO Masked Int Status 0 0xD9 R byte 0x00 0xDA GPIOMIS1 GPIO Masked Int Status 1 0xDA R byte 0x00 0xDB GPIOMIS2 GPIO Masked Int Status 2 0xDB R byte 0x00 0xDC GPIOIC0 GPIO Interrupt Clear 0 0xDC W byte 0xDD GPIOIC1 GPIO Interrupt Clear 1 0xDD W byte 0xDE GPIOIC2 GPIO Interrupt Clear 2 0xDE W byte 0xDF GPIOOME0 GPIO Open Drain Mode Enable 0 0xE0 R/W byte 0x00 0xE1 GPIOOMS0 GPIO Open Drain Mode Select 0 0xE1 R/W byte 0x00 0xE2 GPIOOME1 GPIO Open Drain Mode Enable 1 0xE2 R/W byte 0x00 0xE3 GPIOOMS1 GPIO Open Drain Mode Select 1 0xE3 R/W byte 0x00 0xE4 GPIOOME2 GPIO Open Drain Mode Enable 2 0xE4 R/W byte 0x08 0xE5 GPIOOMS2 GPIO Open Drain Mode Select 2 0xE5 R/W byte 0x00 0xE6 GPIOWAKE0 GPIO Wakeup Enable 0 0xE9 R/W byte 0x00 0xEA GPIOWAKE1 GPIO Wakeup Enable 1 0xEA R/W byte 0x00 0xEB GPIOWAKE2 GPIO Wakeup Enable 2 0xEB R/W byte 0x00 0xEC www.national.com 64 0x7D 0x7E 0x7F 0x80 0x80 0x81 0x81 PWMWP PWMCFG(Low) PWMCFG(High) I2CSA MFGCODE SWREV SWRESET 0x7A TIMRIS 0x7B 0x78 TIMSWRES 0x7C 0x72 TIMSCAL2 TIMIC 0x71 TIMMIS 0x70 PWMCFG2 0x68 TIMCFG1 TIMCFG2 0x62 TIMSCAL0 0x69 0x61 PWMCFG0 0x6A 0x60 TIMCFG0 TIMSCAL1 0x10 PWMCFG1 0x0E EVTCODE 0x09 KBDMSK KBDCODE3 0x08 KBDIC 0x0D 0x07 KBDMIS KBDCODE2 0x06 KBDRIS 0x0B 0x05 KBDDEDCFG1 0x0C 0x04 KBDDEDCFG0 KBDCODE1 0x03 KBDSIZE KBDCODE0 0x02 KBDBOUNCE Addr. 0x01 Register KBDSETTLE 0 RELEASE MULTIKEY MULTIKEY MULTIKEY MULTIKEY SFOFF ROW7 COL9 ROWSIZE3 BIT 7 KEYROW2 KEYROW2 KEYROW2 KEYROW2 KEYROW2 ROW6 COL8 ROWSIZE2 BIT 6 CDIRQ2 CDIRQ2 CDIRQ2 KEYROW1 KEYROW1 KEYROW1 KEYROW1 KEYROW1 ROW5 COL7 ROWSIZE1 BIT 5 CDIRQ2MSK CMD[7:0] PWMWP[6:0] CDIRQ0 CDIRQ0 CDIRQ0 CMD[15:8] SWBIT[7:0] SWBIT[7:0] MFGBIT[7:0] SLAVEADDR[7:1] CDIRQ1 CDIRQ1 CDIRQ1MSK SCAL[7:0] CYCIRQ2MSK CDIRQ1 CDIRQ0MSK KEYCOL3 KEYCOL3 KEYCOL3 KEYCOL3 KEYCOL3 MSKELINT SCAL[7:0] CYCIRQ1MSK RELINT ROW3 COL5 MELINT SCAL[7:0] CYCIRQ0MSK KEYROW0 KEYROW0 KEYROW0 KEYROW0 KEYROW0 ROW4 COL6 BIT 3 COLSIZE3 Wait[7:0] Wait[7:0] ROWSIZE0 BIT 4 TABLE 116. REGISTER LAYOUT - Control Bits in LM8327 Registers CYCIRQ2 CYCIRQ2 CYCIRQ2 SWRES2 PGE PGE PGE KEYCOL2 KEYCOL2 KEYCOL2 KEYCOL2 KEYCOL2 MSKEINT MEVTINT REVTINT ROW2 COL4 COLSIZE2 BIT 2 CYCIRQ1 CYCIRQ1 CYCIRQ1 SWRES1 PWMEN PWMEN PWMEN KEYCOL1 KEYCOL1 KEYCOL1 KEYCOL1 KEYCOL1 MSKLINT EVTIC MKLINT RKLINT COL11 COL3 COLSIZE1 BIT 1 0 CYCIRQ0 CYCIRQ0 CYCIRQ0 SWRES0 PWMPOL START PWMPOL START PWMPOL START KEYCOL0 KEYCOL0 KEYCOL0 KEYCOL0 KEYCOL0 MSKSINT KBDIC MSINT RSINT COL10 COL2 COLSIZE0 BIT 0 LM8327 65 www.national.com www.national.com 66 0x82 0x84 0x88 0X89 0x8A 0x8B 0x8C 0x8D 0x91 0xA7 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 RSTINTCLR CLKMODE CLKCFG CLKEN AUTOSLP AUTOSLPTI (Low) AUTOSLPTI (High) IRQST IOCFG IOPC0 (Low) IOPC0 (High) IOPC1 (Low) IOPC1 (High) IOPC2 (Low) IOPC2 (High) GPIODATA0 GPIOMASK0 GPIODATA1 GPIOMASK1 GPIODATA2 GPIOMASK2 GPIODIR0 GPIODIR1 GPIODIR2 GPIOIS0 GPIOIS1 GPIOIS2 GPIOIBE0 GPIOIBE1 GPIOIBE2 GPIOIEV0 GPIOIEV1 GPIOIEV2 GPIOIE0 Addr. RSTCTRL Register KBD1RQ KPX7IE EXTIOIEV KPY7EV KPX7EV EXTIOIBE KPY7IBE KPX7IBE EXTIOIS KPY7IS KPX7IS EXTIODIR KPY7DIR KPX7DIR MASK23 DATA23 MASK15 DATA15 MASK7 DATA7 KPX6IE PWM2IEV KPY6EV KPX6EV PWM2IBE KPY6IBE KPX6IBE PWM2IS KPY6IS KPX6IS PWM2DIR KPY6DIR KPX6DIR MASK22 DATA22 MASK14 DATA14 MASK6 DATA6 EXTIOPR[1:0] KPY11PR[1:0] KPY7PR[1:0] KPY3PR[1:0] KPX7PR[1:0] KPX3PR[1:0] PORIRQ BIT 5 KPX5IE PWM1IEV KPY5EV KPX5EV PWM1IBE KPY5IBE KPX5IBE PWM1IS KPY5IS KPX5IS PWM1DIR KPY5DIR KPX5DIR MASK21 DATA21 MASK13 DATA13 MASK5 DATA5 KPX4IE PWM0IEV KPY4EV KPX4EV PWM0IBE KPY4IBE KPX4IBE PWM0IS KPY4IS KPX4IS PWM0DIR KPY4DIR KPX4DIR MASK20 DATA20 MASK12 DATA12 MASK4 TIM1IRQ TIMEN BIT 2 KPX3IE KPY11IEV KPY3EV KPX3EV KPY11IBE KPY3IBE KPX3IBE KPY11IS KPY3IS KPX3IS KP11DIR KPY3DIR KPX3DIR MASK19 DATA19 MASK11 DATA11 MASK3 DATA3 KPX2IE KPY10IEV KPY2EV KPX2EV KPY10IBE KPY2IBE KPX2IBE KPY10IS KPY2IS KPX2IS KPY10DIR KPY2DIR KPX2DIR MASK18 DATA18 DATA10 DATA10 MASK2 DATA2 PWM1PR{1:0] KPY9PR[1:0] KPY5PR[1:0] KPY1PR[1:0] KPX5PR[1:0] KPX1PR[1:0] TIM2IRQ IOCFGPM [7:0] DATA4 PWM2PR[1:0] KPY10PR[1:0] KPY6PR[1:0] KPY2PR[1:0] KPX6PR[1:0] TIMRST BIT 3 UP-TIME [7:0] IRQRST BIT 4 KPX2PR[1:0] DKBDIRQ CLKSRCSEL[1:0] BIT 6 CLKOUTEN[1:0] BIT 7 IRQCLR GPIRST BIT 0 KBDEN GPIIRQ ENABLE KPX1IE KPY9IEV KPY1EV KPX1EV KPY9IBE KPY1IBE KPX1IBE KPY9IS KPY1IS KPX1IS KPY9DIR KPY1DIR KPX1DIR MASK17 DATA17 DATA9 DATA9 MASK1 DATA1 KPX0IE KPY8IEV KPY0EV KPX0EV KPY8IBE KPY0IBE KPX0IBE KPY8IS KPY0IS KPX0IS KPY8DIR KPY0DIR KPX0DIR MASK16 DATA16 DATA8 DATA8 MASK0 DATA0 PWM0PR[1:0] KPY8PR[1:0] KPY4PR[1:0] KPY0PR[1:0] KPX4PR[1:0] KPX0PR[1:0] TIM01RQ UP-TIME [10:8] DKBDEN MODCTL[1:0] KBDRST BIT 1 LM8327 0xD9 0xDB 0xDC 0xDD 0xDE 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 GPIOMIS2 GPIOIC0 GPIOIC1 GPIOIC2 GPIOOME0 GPIOOMS0 GPIOOME1 GPIOOMS1 GPIOOME2 GPIOOMS2 DEVTCODE DBOUNCE GPIOWAKE0 GPIOWAKE1 GPIOWAKE2 DIRECT0 DIRECT1 DIRECT2 DIRECT3 DKBDRIS DKBDMIS DKBDIC DKBDMSK MMASTER 0xD8 GPIORIS2 0xDA 0xD7 GPIORIS1 GPIOMIS1 0xD6 GPIORIS0 GPIOMIS0 0xD4 GPIOIE2 Addr. 0xD3 Register GPIOIE1 BIT 7 DK23 DK15 DK07 EXTIOWAKE KPY7WAKE KPX7WAKE EXTIO-ODM EXTIO-ODE KPY7ODM KPY7ODE KPX7ODM KPX7ODE EXTIOIC KPY7IC KPX7IC EXTIOMIS KPY7MIS KPX7MIS EXTIORIS KPY7RIS KPX7RIS EXTIOIE KPY7IE BIT 6 DK22 DK14 DK06 PWM2WAKE KPY6WAKE KPX6WAKE PWM2-ODM PWM2-ODE KPY6ODM KPY6ODE KPX6ODM KPX6ODE PWM2IC KPY6IC KPX6IC PWM2MIS KPY6MIS KPX6MIS PWM2RIS KPY6RIS KPX6RIS PWM2IE KPY6IE BIT 5 DK21 DK13 DK05 PWM1WAKE KPY5WAKE KPX5WAKE PWM1-ODM PWM1-ODE KPY5ODM KPY5ODE KPX5ODM KPX5ODE PWM1IC KPY5IC KPX5IC PWM1MIS KPY5MIS KPX5MIS PWM1RIS KPY5RIS KPX5RIS PWM1IE KPY5IE BIT 4 MSTADR[7:1] DK20 DK12 DK04 PWM0WAKE KPY4WAKE KPX4WAKE PWM0-ODM PWM0-ODE KPY4ODM KPY4ODE KPX4ODM KPX4ODE PWM0IC KPY4IC KPX4IC PWM0MIS KPY4MIS KPX4MIS PWM0RIS KPY4RIS KPX4RIS PWM0IE KPY4IE BIT 3 DK19 DK11 KPY10ODM KPY10ODE KPY2ODM KPY2ODE KPX2ODM KPX2ODE KPY10IC KPY2IC KPX2IC KPY10MIS KPY2MIS KPX2MIS KPY10RIS KPY2RIS KPX2RIS KPY10IE DK18 DK10 DK02 KPY10WAKE KPY2WAKE KPX2WAKE DBOUNCE[4:0] KPY11WAKE KPY3WAKE KPX3WAKE DK03 BIT 2 KPY2IE DKEYCODE[4:0] KPY11ODM KPY11ODE KPY3ODM KPY3ODE KPX3ODM KPX3ODE KPY11IC KPY3IC KPX3IC KPY11MIS KPY3MIS KPX3MIS KPY11RIS KPY3RIS KPX3RIS KPY11IE KPY3IE BIT 1 DMSKELINT DMELINT DRELINT DK25 DK17 DK09 DK01 KPY9WAKE KPY1WAKE KPX1WAKE KPY9 ODM KPY9 ODE KPY1ODM KPY1ODE KPX1ODM KPX1ODE KPY9IC KPY1IC KPX1IC KPY9MIS KPY1MIS KPX1MIS KPY9RIS KPY1RIS KPX1RIS KPY9IE KPY1IE BIT 0 MMSTEN DMSKEINT DEVTIC DMEVTINT DREVTINT DK24 DK16 DK08 DK00 KPY8WAKE KPY0WAKE KPX0WAKE KPY8 ODM KPY8 ODE KPY0ODM KPY0ODE KPX0ODM KPX0ODE KPY8IC KPY0IC KPX0IC KPY8MIS KPY0MIS KPX0MIS KPY8RIS KPY0RIS KPX0RIS KPY8IE KPY0IE LM8327 67 www.national.com LM8327 www.national.com 68 LM8327 18.0 Physical Dimensions inches (millimeters) unless otherwise noted MICRO ARRAY Package Order Number LM8327JGR8 NOPB or LM8327JGR8X NOPB NS Package Number GRA36A 69 www.national.com LM8327 Mobile I/O Companion Supporting Keyscan, I/O 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