NX2138
1
Rev. 1.6
12/09/09
TYPICAL APPLICATION
DESCRIPTION
The NX2138 controller IC is a compact Buck controller
IC with 16 lead MLPQ package designed for step down
DC to DC converter in portable applications. It can be
selected to operate in synchronous mode or non-syn-
chronous mode to improve the efficiency at light
load.Constant on time control provides fast response,
good line regulation and nearly constant frequency un-
der wide voltage input range. The NX2138 controller is
optimized to convert single supply up to 24V bus volt-
age to as low as 0.75V output voltage. Over current
protection and FB UVLO followed by latch feature. Other
features includes: internal boost schottky diode, 5V gate
drive capability, power good indicator, over current pro-
tection, over voltage protection and adaptive dead band
control.
n Internal boost schottky diode
n Ultrasonic mode operation available
nBus voltage operation from 4.5V to 24V
n Less than 1uA shutdown current with Enable low
nExcellent dynamic response with constant on time
control
n Selectable between synchronous CCM mode and
diode emulation mode to improve efficiency at
light load
n Programmable switching frequency
nCurrent limit and FB UVLO with latch off
nOver voltage protection with latch off
nPower good indicator available
n Pb-free and RoHS compliant
ORDERING INFORMATION
FEATURES
SINGLE CHANNEL MOBILE PWM CONTROLLER
APPLICATIONS
nNotebook PCs and Desknotes
nTablet PCs/Slates
nOn board DC to DC such as
12V to 3.3V, 2.5V or 1.8V
nHand-held portable instruments
PRODUCTION DATA SHEET
Figure1 - Typical application of NX2138
Device Temperature Package Pb-Free
NX2138CMTR -10oC to 100oC4X4 MLPQ-16L Yes
Pb Free Product
VIN 7V~22V
TON
HDRV
BST
SW
LDRV
OCSET
FB
VOUT
ENSW
/MODE
5V
10 VCC
PVCC
PGOOD
Vout 1.8V/7A
AGND
PGOOD 1MEG
4
9
2
15
6
3
1
10
8
11
13
12
16
100k
1u 1u
7.5k
10.5k
2R5TPE330MC
5k
1u
2x10uF
1n
IRF7807
AO4714
1.5uH
N X 2 1 3 8
330uF
PGND
7
NC
2
NC
14
2.2
NX2138
2
Rev. 1.6
12/09/09
9
10
11
12
4
3
2
1
VCC
TON
FB
PGOOD PVCC
OCSET
SW
HDRV
8
7
6
5
PGND
LDRV
NC
AGND
16 15 14 13
NC
VO
ENSW/MODE
BST
PAD
17
ABSOLUTE MAXIMUM RATINGS
VCC,PVCC to GND & BST to SW voltage ............ -0.3V to 6.5V
TON to GND ......................................................... -0.3V to 28V
HDRV to SW Voltage .......................................... -0.3V to 6.5V
SW to GND ......................................................... -2V to 30V
All other pins ........................................................ VCC+0.3V
Storage Temperature Range ..................................-65oC to 150oC
Operating Junction Temperature Range .................-40oC to 150oC
ESD Susceptibility ............................................... 2kV
CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent
damage to the device. This is a stress only rating and operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
4x4 16-LEAD PLASTIC MLPQ
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =5V, VIN=15V and TA =25oC, unless otherwise
specified.
o
JA
CW
θ≈46/
PARAMETER SYM Test Condition Min TYP MAX Units
VIN
recommended voltage range 4.5 24 V
Shut down current ENSW=GND 1 uA
VCC,PVCC Supply
Input voltage range Vin 4.5 5.5 V
Operating quiescent current No switching, ENSW=5V 1.6 mA
Shut down current ENSW=GND 1 uA
NX2138
3
Rev. 1.6
12/09/09
N
PARAMETER SYM Test Condition Min TYP MAX Units
VCC UVLO
Under-voltage Lockout
threshold VCC_UVLO 3.9 4.1 4.5 V
Falling VCC threshold 3.7 3.9 4.3 V
ON and OFF time
TON operating current VIN=15V, Rton=1Mohm 15 uA
ON -time VIN=9V,VOUT=0.75V,Rton=
1Mohm 312 390 468 ns
Minimum off time 380 590 800 ns
FB voltage
Internal FB voltage Vref 0.739 0.75 0.761 V
Input bias current 100 nA
Line regulation VCC from 4.5 to 5.5 -1 1%
OUTPUT voltage
Output range 0.75 3.3 V
VOUT shut down discharge
resistance ENSW/MODE=GND 30 ohm
Soft start time 1.5 ms
PGOOD
Power good high rising
threshold 90 % Vref
PGOOD propagation delay
filter NOTE1 2us
Power good hysteresis NOTE1 5%
Pgood output switch
impedance 13 ohm
Pgood leakage current 1 uA
SW zero cross comparator
Offset voltage 5 mV
High Side Driver
(CL=3300pF)
Output Impedance , Sourcing
Current Rsource(Hdrv) I=200mA 1.5 ohm
Output Impedance , Sinking
Current Rsink(Hdrv) I=200mA 1.5 ohm
Rise Time THdrv(Rise) 10% to 90% 50 ns
Fall Time THdrv(Fall) 90% to 10% 50 ns
Deadband Time Tdead(L to
H)
Ldrv going Low to Hdrv going
High, 10% to 10% 30 ns
Low Side Driver
(CL=3300pF)
Output Impedance, Sourcing
Current Rsource(Ldrv) I=200mA 1.5 ohm
Output Impedance, Sinking
Current Rsink(Ldrv) I=200mA 0.5 ohm
Rise Time TLdrv(Rise) 10% to 90% 50 ns
Fall Time TLdrv(Fall) 90% to 10% 50 ns
10 nsDeadband Time Tdead(H to
L) SW going Low to Ldrv going
High, 10% to 10%
NX2138
4
Rev. 1.6
12/09/09
PARAMETER SYM Test Condition Min TYP MAX Units
ENSW/MODE threshold and
bias current
PFM/Non Synchronous Mode
80%
VCC
VCC+0
.3V V
Ultrasonic Mode
60%
VCC
80%
VCC V
Synchronous Mode
Leave it open or use limits in
spec 2
60%
VCC V
Shutdown mode 00.8 V
ENSW/MODE=VCC 5 uA
ENSW/MODE=GND -5 uA
Current Limit
Ocset setting current 20 24 28 uA
Over temperature
Threshold 155 oC
Hysteresis 15 oC
Under voltage
FB threshold
70
%Vref
Over voltage
Over voltage tripp point
125
%Vref
Internal Schottky Diode
Forward voltage drop forward current=50mA 500 mV
Input bias current
NX2138
5
Rev. 1.6
12/09/09
PIN DESCRIPTIONS
PIN NUMBER PIN SYMBOL PIN DESCRIPTION
This pin is directly connected to the output of the switching regulator and
senses the VOUT voltage. An internal MOSFET discharges the output during
turn off.
This pin supplies the internal 5V bias circuit. A 1uF X7R ceramic capacitor is
placed as close as possible to this pin and ground pin.
This pin is the error amplifiers inverting input. This pin is connected via
resistor divider to the output of the switching regulator to set the output DC
voltage from 0.75V to 3.3V.
PGOOD indicator for switching regulator. It requires a pull up resistor to Vcc
or lower voltage. When FB pin reaches 90% of the reference voltage
PGOOD transitions from LO to HI state.
Not used.
Analog ground.
Power ground.
Low side gate driver output.
Provide the voltage supply to the lower MOSFET drivers. Place a high
frequency decoupling capacitor 1uF X5R to this pin.
This pin is connected to the drain of the external low side MOSFET and is
the input of over current protection(OCP) comparator. An internal current
source is flown to the external resistor which sets the OCP voltage across
the Rdson of the low side MOSFET.
This pin is connected to source of high side FETs and provide return path for
the high side driver. It is also the input of zero current sensing comparator.
High side gate driver output.
This pin supplies voltage to high side FET driver. A high freq 1uF X7R
ceramic capacitor and 2.2ohm resistor in series are recommended to be
placed as close as possible to and connected to this pin and SW pin.
Not used.
Switching converter enable input. Connect to VCC for PFM/Non synchronous
mode, connected to an external resistor divider equals to 70%VCC for ultra-
sonic, connected to GND for shutdown mode, floating or connected to 2V for
the synchronous mode.
VIN sensing input. A resistor connects from this pin to VIN will set the fre-
quency. A 1nF capacitor from this pin to GND is recommended to ensure the
proper operation.
Used as thermal pad. Connect this pad to ground plane through multiple vias.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
VOUT
VCC
FB
PGOOD
NC
AGND
PGND
LDRV
PVCC
OCSET
SW
HDRV
BST
NC
ENSW/
MODE
TON
PAD
NX2138
6
Rev. 1.6
12/09/09
BLOCK DIAGRAM
Figure 2 - Simplified block diagram of the NX2138
VIN
BST(13)
HDRV(12)
LDRV(8)
SW(11)
PVCC(9)
5V
FET Driver
start ODB
HD_IN
start
VOUT(1)
0.9*Vref
SS_finished
PGOOD(4)
OCSET(10)
ENSW
/MODE(15)
start POR
FB(3)
TON(16)
HD
VREF=0.75V
FBUVLO_latch
R
SQ
Mini offtime
400ns
OCP_COMP
HD
Diode
emulation
OCP_COMP
0.7*Vref
FB
1.25*Vref/0.7VREF
FB
OVP
FBUVLO_latch VOUT
Sync
PFM_nonultrasonic
4.3/4.1
VCC(2) Bias POR
Disable
Disable_B
VOUT
VIN
1.8V
Thermal
shutdown
soft start
ON time
pulse
genearation
VOUT
MODE
SELECTION
VCC1M
1M
AGND(6)
PGND(7)
NX2138
7
Rev. 1.6
12/09/09
Figure 3 - Demo board schematic
2.2
1.5n
VIN 7V~22V
TON
HDRV
BST
SW
LDRV
OCSET
FB
VOUT
ENSW
/MODE
5V
10 VCC
PVCC
PGOOD
Vout 1.8V/7A
AGND
PGOOD 1MEG
4
9
2
15
6
3
1
10
8
11
13
12
16
100k
1u 1u
2R5TPE330MC
5k
1u
1n
IRF7807
AO4714
1.5uH
N X 2 1 3 8
330uF
PGND
7
NC
2
NC
14
R1
R2
C1 C2
C3
R4
R5
M1
M2
Lo
CI1
2x10uF
CO1
R3
C5
7.5k
10.5k
R6
R7
C4
2.2R8
TYPICAL APPLICATION
(VIN=7V to 22V, VOUT=1.8V/7A)
NX2138
8
Rev. 1.6
12/09/09
Bill of Materials
Item Quantity Reference Value Manufacture
1 2 CI1 10uF/X5R/25V
2 1 CO1 2R5TPE330MC SANYO
3 2 C1,C2,C4 1uF
4 2 C3 1nF
5 1 C5 1.5nF
6 1 Lo DO5010H-152 COILCRAFT
7 1 M1 IRF7807 IR
8 1 M2 AO4714 IR
9 1 R1 100k
10 1R2 10
11 2R3,R8 2.2
12 1R4 1M
13 1R5 5k
14 1R6 10.5k
15 1R7 7.5k
16 1U1 NX2138 NEXSEM INC.
NX2138
9
Rev. 1.6
12/09/09
Demoboard waveforms
Fig.4 Startup (CH2 1.8V OUTPUT, CH3 PGOOD) Fig.5 Turn off (CH2 1.8V OUTPUT, CH3 PGOOD)
Fig. 9 Output ripple at full load (CH1 SW, CH2 1.8V
OUTPUT AC, CH4 OUTPUT CURRENT)
Fig.7 Output transient in PFM mode (CH1 SW, CH2
1.8V OUTPUT AC, CH4 OUTPUT CURRENT) Fig.8 Start into short (CH3 VOUT, CH4 OUTPUT
CURRENT)
Fig. 10 Output ripple at light load in PFM mode(CH1
SW, CH2 1.8V OUTPUT AC)
NX2138
10
Rev. 1.6
12/09/09
Fig. 11 Output ripple at no load in synchronous mode
(CH1 SW, CH2 1.8V OUTPUT AC, CH4 OUTPUT
CURRENT)
Demoboard waveforms(Cont')
Fig. 12 Dynamic response in synchronous mode
(CH2 1.8V OUTPUT AC, CH4 OUTPUT CURRENT)
Fig. 13 Dynamic response in synchronous mode
(CH2 1.8V OUTPUT AC, CH4 OUTPUT CURRENT) Fig. 14 Dynamic response in PFM mode
(CH2 1.8V OUTPUT AC, CH4 OUTPUT CURRENT)
Fig. 15 Dynamic response in PFM mode
(CH2 1.8V OUTPUT AC, CH4 OUTPUT CURRENT)
VIN=12V, VOUT=1.8V
50.00%
55.00%
60.00%
65.00%
70.00%
75.00%
80.00%
85.00%
90.00%
95.00%
10 100 1000 10000
OUTPUT CURRENT(mA)
OUTPUT EFFICIENCY(%)
Fig. 16 Output efficiency
NX2138
11
Rev. 1.6
12/09/09
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN - Input voltage
VOUT - Output voltage
IOUT - Output current
DVRIPPLE - Output voltage ripple
FS - Working frequency
DIRIPPLE - Inductor current ripple
Design Example
The following is typical application for NX2138,
the schematic is figure 1.
VIN = 7 to 22V
VOUT=1.8V
FS=220kHz
IOUT=7A
DVRIPPLE <=60mV
DVDROOP<=60mV @ 3A step
On_Time and Frequency Calculation
The constant on time control technique used in
NX2138 delivers high efficiency, excellent transient dy-
namic response, make it a good candidate for step down
notebook applications.
An internal one shot timer turns on the high side
driver with an on time which is proportional to the input
supply VIN as well inversely proportional to the output
voltage VOUT. During this time, the output inductor
charges the output cap increasing the output voltage
by the amount equal to the output ripple. Once the
timer turns off, the Hdrv turns off and cause the output
voltage to decrease until reaching the internal FB volt-
age of 0.75V on the PFM comparator. At this point the
comparator trips causing the cycle to repeat itself. A
minimum off time of 400nS is internally set.
The equation setting the On Time is as follows:
12
TONOUT
IN
4.4510RV
TON V0.5V
−
×××
=− ...(1)
OUT
SIN
V
F
VTON
=× ...(2)
In this application example, the RTON is chosen
to be 1Mohm, when VIN=22V, the TON is 372nS and
FS is around 220kHz.
Output Inductor Selection
The value of inductor is decided by inductor ripple
current and working frequency. Larger inductor value
normally means smaller ripple current. However if the
inductance is chosen too large, it brings slow response
and lower efficiency. The ripple current is a design free-
dom which can be decided by design engineer accord-
ing to various application requirements. The inductor
value can be calculated by using the following equa-
tions:
(
)
INOUT ON
OUT RIPPLE
RIPPLEOUTPUT
V-VT
L= I
I=kI
×
× ...(3)
where k is percentage of output current.
In this example, inductor from COILCRAFT
DO5010H-152 with L=1.5uH is chosen.
Current Ripple is recalculated as below:
INOUT ON
RIPPLE OUT
(V-V)T
I= L
(22V-1.8V)372nS
= 1.5uH
=5A
×
× ...(4)
Output Capacitor Selection
Output capacitor is basically decided by the
amount of the output voltage ripple allowed during
steady state(DC) load condition as well as specifica-
tion for the load transient. The optimum design may
require a couple of iterations to satisfy both conditions.
Based on DC Load Condition
The amount of voltage ripple during the DC load
condition is determined by equation(5).
∆
∆=×∆+
××
RIPPLE
RIPPLERIPPLE
SOUT
I
VESRI 8FC ...(5)
Where ESR is the output capacitors' equivalent
series resistance,COUT is the value of output capaci-
tors. Typically POSCAP is recommended to use in
NX2139's applications. The amount of the output volt-
age ripple is dominated by the first term in equation(5)
NX2138
12
Rev. 1.6
12/09/09
and the second term can be neglected.
For this example, one POSCAP 2R5TPE330MC
is chosen as output capacitor, the ESR and inductor
current typically determines the output voltage ripple.
When VIN reach maximum voltage, the output volt-
age ripple is in the worst case.
RIPPLE
desire RIPPLE
V60mV
ESR=12m
I5A
∆
==Ω
∆ ...(6)
If low ESR is required, for most applications, mul-
tiple capacitors in parallel are needed. The number of
output capacitor can be calculate as the following:
ERIPPLE
RIPPLE
ESRI
NV×∆
=∆ ...(7)
12m5A
N60mV
Ω×
=
N =1
The number of capacitor has to be round up to a
integer. Choose N =1.
Based On Transient Requirement
Typically, the output voltage droop during tran-
sient is specified as
∆Vdroop ∆V
tran
< @step load DISTEP
During the transient, the voltage droop during the
transient is composed of two sections. One section is
dependent on the ESR of capacitor, the other section
is a function of the inductor, output capacitance as well
as input, output voltage. For example, for the over-
shoot when load from high load to light load with a
DISTEP transient load, if assuming the bandwidth of sys-
tem is high enough, the overshoot can be estimated
as the following equation.
2
OUT
overshootstep OUT
V
VESRI 2LC
∆=×∆+×τ
×× ...(8)
where
Ï„
is the a function of capacitor,etc.
crit
step
OUTcrit
OUT
0ifLL
LI
ESRCifLL
V
≤

×∆
τ=−×≥

 ...(9
where
OUTOUTEEOUT
crit stepstep
ESRCVESRCV
LII
××××
==
∆∆
...(10)
where ESRE and CE represents ESR and capaci-
tance of each capacitor if multiple capacitors are used
in parallel.
The above equation shows that if the selected
output inductor is smaller than the critical inductance,
the voltage droop or overshoot is only dependent on
the ESR of output capacitor. For low frequency ca-
pacitor such as electrolytic capacitor, the product of
ESR and capacitance is high and
crit
LL
≤ is true. In
that case, the transient spec is mostly like to depen-
dent on the ESR of capacitor.
Most case, the output capacitor is multiple ca-
pacitor in parallel. The number of capacitor can be cal-
culated by the following
Estep
2
OUT
tranEtran
ESRI V
NV2LCV
×∆
=+×τ
∆×××∆ ...(11)
where
crit
step
EEcrit
OUT
0ifLL
LI
ESRCifLL
V
≤

×∆
τ=−×≥

 ...(12)
For example, assume voltage droop during tran-
sient is 60mV for 3A load step.
If one POSCAP 2R5TPE330MC(330uF, 12mohm
ESR) is used, the crticial inductance is given as
EEOUT
crit step
ESRCV
LI
12m3300F1.8V
23.76H
3A
××
==
∆
Ω×µ×
=µ
The selected inductor is 1.5uH which is smaller
than critical inductance. In that case, the output volt-
age transient mainly dependent on the ESR.
number of capacitor is
Estep
tran
ESRI
NV
12m3A
60mV
0.6
×∆
=∆
Ω×
=
=
Choose N=1.
NX2138
13
Rev. 1.6
12/09/09
Based On Stability Requirement
ESR of the output capacitor can not be chosen
too low which will cause system unstable. The zero
caused by output capacitor's ESR must satisfy the re-
quirement as below:
SW
ESR OUT
F
1
F
2ESRC4
=≤
×π×× ...(13)
Besides that, ESR has to be bigger enough so
that the output voltage ripple can provide enough volt-
age ramp to error amplifier through FB pin. If ESR is
too small, the error amplifier can not correctly dectect
the ramp, high side MOSFET will be only turned off for
minimum time 400nS. Double pulsing and bigger out-
put ripple will be observed. In summary, the ESR of
output capacitor has to be big enough to make the sys-
tem stable, but also has to be small enough to satify
the transient and DC ripple requirements.
Input Capacitor Selection
Input capacitors are usually a mix of high fre-
quency ceramic capacitors and bulk capacitors. Ce-
ramic capacitors bypass the high frequency noise, and
bulk capacitors supply switching current to the
MOSFETs. Usually 1uF ceramic capacitor is chosen
to decouple the high frequency noise.The bulk input
capacitors are decided by voltage rating and RMS cur-
rent rating. The RMS current in the input capacitors
can be calculated as:
RMSOUT
ONS
IID1-D
DTF
=××
=× ...(14)
When VIN = 22V, VOUT=1.8V, IOUT=7A, the result of
input RMS current is 1.9A.
For higher efficiency, low ESR capacitors are
recommended. One 10uF/X5R/25V and two 4.7uF/
X5R/25V ceramic capacitors are chosen as input
capacitors.
Power MOSFETs Selection
The NX2138 requires at least two N-Channel
power MOSFETs. The selection of MOSFETs is based
on maximum drain source voltage, gate source volt-
age, maximum current rating, MOSFET on resistance
and power dissipation. The main consideration is the
power loss contribution of MOSFETs to the overall con-
verter efficiency. In this application, one IRF7807 for
high side and one AO4714 with integrated schottky di-
ode for low side are used.
There are two factors causing the MOSFET
power loss:conduction loss, switching loss.
Conduction loss is simply defined as:
×××
×−××
+
2
HCONOUTDS(ON)
2
LCONOUTDS(ON)
TOTALHCONLCON
P=IDRK
P=I(1D)RK
P=PP ...(15)
where the RDS(ON) will increases as MOSFET junc-
tion temperature increases, K is RDS(ON) temperature
dependency. As a result, RDS(ON) should be selected
for the worst case. Conduction loss should not exceed
package rating or overall system thermal budget.
Switching loss is mainly caused by crossover
conduction at the switching transition. The total
switching loss can be approximated.
SWINOUTSWS
1
PVITF
2
=××××
...(16)
where IOUT is output current, TSW is the sum of TR
and TF which can be found in mosfet datasheet, and
FS is switching frequency. Swithing loss PSW is fre-
quency dependent.
Also MOSFET gate driver loss should be consid-
ered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by dis-
charging the gate capacitor and is dissipated in driver
circuits.It is proportional to frequency and is defined
as:
gateHGATEHGSLGATELGSS
P(QVQV)F
=×+××
...(17)
where QHGATE is the high side MOSFETs gate
charge,QLGATE is the low side MOSFETs gate
charge,VHGS is the high side gate source voltage, and
VLGS is the low side gate source voltage.
This power dissipation should not exceed maxi-
mum power dissipation of the driver device.
Output Voltage Calculation
Output voltage is set by reference voltage and
external voltage divider. The reference voltage is fixed
NX2138
14
Rev. 1.6
12/09/09
Mode Selection
NX2138 can be operated in PFM mode, ultrasonic
PFM mode, CCM mode and shutdown mode by apply-
ing different voltage on ENSW/MODE pin.
When VCC applied to ENSW/MODE pin, NX2138
is In PFM mode. The low side MOSFET emulates the
function of diode when discontinuous continuous mode
happens, often in light load condition. During that time,
the inductor current crosses the zero ampere border
and becomes negative current. When the inductor cur-
rent reaches negative territory, the low side MOSFET
is turned off and it takes longer time for the output volt-
age to drop, the high side MOSFET waits longer to be
turned on. At the same time, no matter light load and
heavy load, the on time of high side MOSFET keeps
the same. Therefore the lightier load, the lower the
switching frequency will be. In ultrosonic PFM mode,
the lowest frequency is set to be 25kHz to avoid audio
frequency modulation. This kind of reduction of fre-
quency keeps the system running at light light with high
efficiency.
In CCM mode, inductor current zero-crossing
sensing is disabled, low side MOSFET keeps on even
when inductor current becomes negative. In this way
the efficiency is lower compared with PFM mode at
light load, but frequency will be kept constant.
Over Current Protection
Over current protection for NX2138 is achieved
by sensing current through the low side MOSFET. An
typical internal current source of 24uA flows through
an external resistor connected from OCSET pin to SW
node sets the over current protection threshold. When
synchronous FET is on, the voltage at node SW is given
as
SWLDSON
V=-IR×
The voltage at pin OCSET is given as
OCPOCPSW
IR+V
×
When the voltage is below zero, the over current
occurs as shown in figure below.
OCP
comparator
OCP
24uA
OCP
I
OCP
RSW
vbus
Figure 18 - Over Voltage Protection
The over current limit can be set by the following
equation.=×
SETOCPOCPDSON
IIR/R
If the low side MOSFET RDSON=10mΩ at the OCP
occuring moment, and the current limit is set at 12A,
then
SETDSON
OCP OCP
IR 12A10m
R5k
I24uA
××Ω
===Ω
Choose ROCP=5kΩ
Power Good Output
Power good output is open drain output, a pull
up resistor is needed. Typically when softstart is
at 0.75V. The divider consists of two ratioed resistors
so that the output voltage applied at the Fb pin is 0.75V
when the output voltage is at the desired value.
The following equation applies to figure 11, which
shows the relationship between
OUT
V,
REF
Vand volt-
age divider.
Vout
Vref
Fb
R2
R1
Figure 17 - Voltage Divider
2REF
1
OUT REF
RV
R=V-V
× ...(18)
where R2 is part of the compensator, and the value
of R1 value can be set by voltage divider.
NX2138
15
Rev. 1.6
12/09/09
finised and FB pin voltage is over 90% of VREF, the
PGOOD pin is pulled to high after a 1.6ms delay.
Smart Over Output Voltage Protection
Active loads in some applications can leak cur-
rent from a higher voltage than VOUT, cause output volt-
age to rise. When the FB pin voltage is sensed over
112% of VREF, the high side MOSFET will be turned off
and low side MOSFET will be turned on to discharge
the VOUT. NX2138 resumes its switching operation after
FB pin voltage drops to VREF.
If FB pin voltage keeps rising and is sensed over
125% of VREF, the low side MOSFET will be latched to
be on to discharge the output voltage and over voltage
protection is triggered. To resume the switching opera-
tion, resetting voltage on pin VCC or pin EN is neces-
sary.
Under Output Voltage Protection
Typically when the FB pin voltage is under 70%
of VREF, the high side and low side MOSFET will be
turned off. To resume the switching operation, VCC or
ENSW has to be reset.
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
There are two sets of components considered in
the layout which are power components and small sig-
nal components. Power components usually consist of
input capacitors, high-side MOSFET, low-side
MOSFET, inductor and output capacitors. A noisy en-
vironment is generated by the power components due
to the switching power. Small signal components are
connected to sensitive pins or nodes. A multilayer lay-
out which includes power plane, ground plane and sig-
nal plane is recommended .
Layout guidelines:
1. First put all the power components in the top
layer connected by wide, copper filled areas. The input
capacitor, inductor, output capacitor and the MOSFETs
should be close to each other as possible. This helps
to reduce the EMI radiated by the power loop due to
the high switching currents through them.
2. Low ESR capacitor which can handle input
RMS ripple current and a high frequency decoupling
ceramic cap which usually is 1uF need to be practi-
cally touching the drain pin of the upper MOSFET, a
plane connection is a must.
3. The output capacitors should be placed as close
as to the load as possible and plane connection is re-
quired.
4. Drain of the low-side MOSFET and source of
the high-side MOSFET need to be connected thru a
plane and as close as possible. A snubber needs to be
placed as close to this junction as possible.
5. Source of the lower MOSFET needs to be con-
nected to the GND plane with multiple vias. One is not
enough. This is very important. The same applies to
the output capacitors and input capacitors.
6. Hdrv and Ldrv pins should be as close to
MOSFET gate as possible. The gate traces should be
wide and short. A place for gate drv resistors is needed
to fine tune noise if needed.
7. Vcc capacitor, BST capacitor or any other by-
passing capacitor needs to be placed first around the
IC and as close as possible. The capacitor on comp to
GND or comp back to FB needs to be place as close to
the pin as well as resistor divider.
8. The output sense line which is sensing output
back to the resistor divider should not go through high
frequency signals, should be kept away from the in-
ductor and other noise sources. The resistor divider
must be located as close as possible to the FB pin of
the device.
9. All GNDs need to go directly thru via to GND
plane.
10. In multilayer PCB, separate power ground
and analog ground. These two grounds must be con-
nected together on the PC board layout at a single point.
The goal is to localize the high current path to a sepa-
rate loop that does not interfere with the more sensi-
tive analog control function.
NX2138
16
Rev. 1.6
12/09/09
4x4 16 PIN MLPQ OUTLINE DIMENSIONS
NOTE: ALL DIMENSIONS ARE DISPLAYED IN MILLIMETERS.
