C2
22uF
3.3V / 0.5A
C1
10uF
2.2µH
VIN
TPS62170-Q1
R1
470k
R2
150k
VIN
EN
AGND
PGND
SW
VOS
PG
FB
100k
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62170-Q1
,
TPS62171-Q1
,
TPS62172-Q1
SLVSCK7D –DECEMBER 2014–REVISED FEBRUARY 2017
TPS6217x-Q1 3-V to17-V 0.5-A Step-Down Converters with DCS-Control™
1
1 Features
1• DCS-Control™ Topology
• Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade: –40°C to 125°C
Operating Junction Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
• Input Voltage Range: 3 V to 17 V
• Up to 500-mA Output Current
• Adjustable Output Voltage from 0.9 V to 6 V
• Fixed Output Voltage Versions
• Seamless Power Save Mode Transition
• Typically 17-µA Quiescent Current
• Power Good Output
• 100% Duty Cycle Mode
• Short Circuit Protection
• Over Temperature Protection
• Pin to Pin Compatible With TPS62160-Q1
• Available in a 2 × 2 mm, WSON-8 Package
• Create a Custom Design Using the TPS62170-Q1
With the WEBENCH®Power Designer
2 Applications
• Automotive 12-V Rail Supplies
• Power Over Coax POL Supply
• Camera, Video Modules
• LDO Alternative
3 Description
The TPS6217x-Q1 family is an easy to use
synchronous step down DC-DC converter optimized
for applications with high power density. A high
switching frequency of typically 2.25 MHz allows the
use of small inductors and provides fast transient
response as well as high output voltage accuracy by
utilization of the DCS-Control™ topology.
With their wide operating input voltage range of 3 V
to 17 V, the devices are ideally suited for systems
powered from either a Li-Ion or other battery as well
as from 12-V intermediate power rails. It supports up
to 0.5-A continuous output current at output voltages
between 0.9 V and 6 V (with 100% duty cycle mode).
Power sequencing is also possible by configuring the
Enable and open-drain Power Good pins.
In Power Save Mode, the devices draw quiescent
current of about 17 μA from VIN. Power Save Mode,
entered automatically and seamlessly if load is small,
maintains high efficiency over the entire load range.
In Shutdown Mode, the device is turned off and
shutdown current consumption is less than 2 μA.
The device, available in adjustable and fixed output
voltage versions, is packaged in an 8-pin WSON
package measuring 2 × 2 mm (DSG).
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS62170-Q1 WSON (8) 2.00 mm × 2.00 mm
TPS62171-Q1 WSON (8) 2.00 mm × 2.00 mm
TPS62172-Q1 WSON (8) 2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic Efficiency vs Output Current
space
spacespace
2
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,
TPS62171-Q1
,
TPS62172-Q1
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 6
8 Detailed Description.............................................. 7
8.1 Overview................................................................... 7
8.2 Functional Block Diagram......................................... 7
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
9 Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical TPS62170-Q1 Application ......................... 11
9.3 System Examples ................................................... 20
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
11.3 Thermal Considerations........................................ 24
12 Device and Documentation Support................. 25
12.1 Device Support .................................................... 25
12.2 Documentation Support ....................................... 25
12.3 Related Links ........................................................ 26
12.4 Trademarks........................................................... 26
12.5 Electrostatic Discharge Caution............................ 26
12.6 Receiving Notification of Documentation Updates 26
12.7 Community Resources.......................................... 26
12.8 Glossary................................................................ 26
13 Mechanical, Packaging, and Orderable
Information........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2016) to Revision D Page
• Added WEBENCH®information ............................................................................................................................................. 1
• Changed TJspec MAX value From 125°C To 150°C in the Absolute Maximum Ratings table............................................. 4
Changes from Revision B (October 2016) to Revision C Page
• Added Pin to Pin compatible feature ..................................................................................................................................... 1
• Changed Thermal Information table....................................................................................................................................... 4
• Added C1, C2, R1, R2, descriptors to Figure 5.................................................................................................................... 11
• Added C1, C2 to Table 1 ..................................................................................................................................................... 11
Changes from Revision A (September 2016) to Revision B Page
• Added the Device Comparison Table..................................................................................................................................... 3
Changes from Original (December 2014) to Revision A Page
• Changed "POE Over Coax POL Supply " To: "Power Over Coax POL Supply " in the Application list................................ 1
• Added TPS62171-Q1 device to data sheet............................................................................................................................ 1
• Changed Unit from mA to V for Pin voltage at FB, PG, and VOS in the Absolute Maximum Ratings table. ........................ 4
• Changed Unit from °C to mA in the Absolute Maximum Ratings table for Power Good sink current. .................................. 4
• Changed Unit from kV to °C in the Absolute Maximum Ratings table for the Operating junction temperature, TJ.............. 4
• Added legal NOTE at Application and Implementation ....................................................................................................... 11
• Added cross references to Third-Party Products disclaimer in Table 1............................................................................... 11
8PG
SW
VOS
FB
Exposed
Thermal
Pad
PGND
VIN
EN
AGND
7
6
5
2
3
1
4
3
TPS62170-Q1
,
TPS62171-Q1
,
TPS62172-Q1
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SLVSCK7D –DECEMBER 2014–REVISED FEBRUARY 2017
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5 Device Comparison Table
(1) For detailed ordering information please check the Mechanical, Packaging, and Orderable Information
section at the end of this datasheet.
PART NUMBER(1) OUTPUT VOLTAGE
TPS62170-Q1 adjustable
TPS62171-Q1 1.8 V
TPS62172-Q1 3.3 V
(1) For more information about connecting pins, see Detailed Description and Application and Implementation sections.
6 Pin Configuration and Functions
8-Pin WSON
DSG Package
(Top View)
space
Pin Functions
PIN(1) I/O DESCRIPTION
NAME NUMBER
PGND 1 Power ground
VIN 2 I Supply voltage
EN 3 I Enable input (High = enabled, Low = disabled)
AGND 4 Analog ground
FB 5 I Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. It is recommended
to connect FB to AGND on fixed output voltage versions for improved thermal performance.
VOS 6 I Output voltage sense pin and connection for the control loop circuitry.
SW 7 O Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and
output capacitor.
PG 8 O Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires
pull-up resistor; goes high impedance, when device is switched off)
Exposed
Thermal Pad Must be connected to AGND. Must be soldered to achieve appropriate power dissipation and
mechanical reliability.
4
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,
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,
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Pin voltage(2)
VIN –0.3 20 V
EN –0.3 VIN+0.3
SW -0.3 VIN+0.3 V
FB, PG, VOS –0.3 7 V
Power Good sink current PG 10 mA
Operating junction temperature range, TJ–40 150 °C
Storage temperature range, Tstg –65 150 °C
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V
Charged device model (CDM), per AEC Q100-011 ±500
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted) MIN TYP MAX UNIT
VIN Supply voltage 3 17 V
VOUT Output voltage range 0.9 6 V
TJOperating junction temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, .
7.4 Thermal Information
THERMAL METRIC(1) TPS6217x-Q1 UNIT
DSG (8 PINS)
RθJA Junction-to-ambient thermal resistance 65.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 66.4 °C/W
RθJB Junction-to-board thermal resistance 35.5 °C/W
ψJT Junction-to-top characterization parameter 1.7 °C/W
ψJB Junction-to-board characterization parameter 35.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.4 °C/W
5
TPS62170-Q1
,
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,
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(1) The device is still functional down to Under Voltage Lockout (see parameter VUVLO).
(2) Current into VIN pin.
(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit and Short
Circuit Protection).
(4) For fixed voltage versions, the (internal) resistive feedback divider is included.
(5) The accuracy in Power Save Mode can be improved by increasing the COUT value, reducing the output voltage ripple.
(6) Line and load regulation are depending on external component selection and layout (see Figure 14 and Figure 15).
7.5 Electrical Characteristics
over junction temperature range (TJ= –40°C to +125°C), typical values at VIN = 12 V and TJ= 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range(1) 3 17 V
IQOperating quiescent current EN = High, IOUT = 0 mA, Device not switching 17 30 µA
ISD Shutdown current(2) EN = Low 1.8 25 µA
VUVLO Undervoltage lockout threshold Falling input voltage 2.6 2.7 2.82 V
Hysteresis 180 mV
TSD Thermal shutdown temperature 160 °C
Thermal shutdown hysteresis 20
CONTROL (EN, PG)
VEN_H High-level input threshold voltage (EN) 0.9 V
VEN_L Low-level input threshold voltage (EN) 0.3 V
ILKG_EN Input leakage current (EN) EN = VIN or GND 0.01 1 µA
VTH_PG Power Good threshold voltage Rising (%VOUT) 92% 95% 98%
Falling (%VOUT) 87% 90% 93%
VOL_PG Power Good output low IPG = –2 mA 0.07 0.3 V
ILKG_PG Input leakage current (PG) VPG = 1.8 V 1 400 nA
POWER SWITCH
RDS(ON)
High-side MOSFET ON-resistance VIN ≥6 V 300 600 mΩ
VIN = 3 V 430
Low-side MOSFET ON-resistance VIN ≥6 V 120 200 mΩ
VIN = 3 V 165
ILIMF High-side MOSFET forward current limit(3) VIN = 12 V, TA= 25°C 0.85 1.05 1.35 A
OUTPUT
VREF Internal reference voltage 0.8 V
ILKG_FB Pin leakage current (FB) TPS62170-Q1, VFB = 1.2 V 5 400 nA
VOUT
Output voltage range TPS62170-Q1, VIN ≥VOUT 0.9 6.0 V
Feedback voltage accuracy(4) PWM Mode operation, VIN ≥VOUT + 1 V –3% 3%
Power Save Mode operation, COUT = 22 µF(5) –3.5% 4%
DC output voltage load regulation(6) VIN = 12 V, VOUT = 3.3 V, PWM Mode operation 0.05 % / A
DC output voltage line regulation (6) 3 V ≤VIN ≤17 V, VOUT = 3.3 V, IOUT = 0.5 A,
PWM Mode operation 0.02 % / V
6
TPS62170-Q1
,
TPS62171-Q1
,
TPS62172-Q1
SLVSCK7D –DECEMBER 2014–REVISED FEBRUARY 2017
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7.6 Typical Characteristics
At VIN = 12 V, VOUT = 3.3 V and TJ= 25°C (unless otherwise noted)
Figure 1. Quiescent Current Figure 2. Shutdown Current
Figure 3. High-Side Static Drain-Source-Resistance (RDSon) Figure 4. Low-Side Static Drain-Source-Resistance (RDSon)
control logic
Soft
start
Thermal
Shtdwn UVLO PG control
power
control
error
amplifier
gate
drive
HS lim
LS lim
VINPG
PGND
AGND
comp
comp
+
_
timer tON
DCS - ControlTM
direct control
&
compensation
comparator
ramp
SW
EN*
VOS
FB
Copyright © 2016, Texas Instruments Incorporated
7
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,
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,
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8 Detailed Description
8.1 Overview
The TPS6217x-Q1 synchronous switched mode power converters are based on DCS-Control™ (Direct Control
with Seamless transition into power save mode), an advanced regulation topology, that combines the advantages
of hysteretic, voltage mode and current mode control including an AC loop directly associated to the output
voltage. This control loop takes information about output voltage changes and feeds it directly to a fast
comparator stage. It sets the switching frequency, which is constant for steady state operating conditions, and
provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback
loop is used. The internally compensated regulation network achieves fast and stable operation with small
external components and low ESR capacitors.
The DCS-ControlTM topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.25 MHz with a controlled frequency variation
depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain
high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the
load current. Since DCS-ControlTM supports both operation modes within one single building block, the transition
from PWM to Power Save Mode is seamless without effects on the output voltage.
8.2 Functional Block Diagram
* This pin is connected to a pull down resistor internally (see Feature Description section).
8
TPS62170-Q1
,
TPS62171-Q1
,
TPS62172-Q1
SLVSCK7D –DECEMBER 2014–REVISED FEBRUARY 2017
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8.3 Feature Description
8.3.1 Enable / Shutdown (EN)
When Enable (EN) is set High, the device starts operation.
Shutdown is forced if EN is pulled Low with a shutdown current of typically 1.8 µA. During shutdown, the internal
power MOSFETs as well as the entire control circuitry are turned off. The internal resistive divider pulls down the
output voltage smoothly. If the EN pin goes Low, an internal pull-down resistor of about 400 kΩis connected and
keeps it Low in case of floating pin. To avoid ON/OFF oscillations, a minimum slew rate of about 50 mV/s is
recommended for the EN signal.
Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple
power rails.
8.3.2 Softstart
The internal soft start circuitry controls the output voltage slope during startup. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high-
impedance power sources or batteries. When EN is set to start device operation, the device starts switching after
a delay of about 50 µs and VOUT rises with a slope of about 25 mV/µs. See Figure 26 and Figure 27 for typical
startup operation.
The TPS6217x-Q1 can start into a pre-biased output. During monotonic pre-biased startup, the low-side
MOSFET is not allowed to turn on until the device's internal ramp sets an output voltage above the pre-bias
voltage.
8.3.3 Power Good (PG)
The TPS6217x-Q1 has a built in power good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an
open-drain output that requires a pull-up resistor (to any voltage below 7 V). It can sink 2 mA of current and
maintain its specified logic low level. It is high impedance when the device is turned off due to EN, UVLO, or
thermal shutdown.
8.3.4 Under Voltage Lockout (UVLO)
If the input voltage drops, the under voltage lockout prevents misoperation of the device by switching off both the
power FETs. The under voltage lockout threshold is set typically to 2.7 V. The device is fully operational for
voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 180 mV.
8.3.5 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJexceeds 160°C
(typ), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and PG
goes high impedance. When TJdecreases below the hysteresis amount, the converter resumes normal
operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented
on the thermal shut down temperature.
8.4 Device Functional Modes
8.4.1 Pulse Width Modulation (PWM) Operation
The TPS62170-Q1 operates with pulse width modulation in continuous conduction mode (CCM) with a nominal
switching frequency of about 2.25 MHz. The frequency variation in PWM is controlled and depends on VIN, VOUT
and the inductance. The device operates in PWM mode as long the output current is higher than half the
inductor's ripple current. To maintain high efficiency at light loads, the device enters Power Save Mode at the
boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than
half the inductor's ripple current.
( )
L)on(DSOUT(min)OUT(min)IN RRIVV ++=
ns
V
V
t
IN
OUT
ON 420×=
9
TPS62170-Q1
,
TPS62171-Q1
,
TPS62172-Q1
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Device Functional Modes (continued)
8.4.2 Power Save Mode Operation
The TPS6217x-Q1's built in Power Save Mode will be entered seamlessly, if the load current decreases. This
secures a high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor
current is discontinuous.
In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in
both directions.
The TPS6217x-Q1 includes a fixed on-time circuitry. This on-time, in steady-state operation, can be estimated
as:
space
(1)
space
For very small output voltages, the on-time increases beyond the result of Equation 1, to stay above an absolute
minimum on-time, tON(min), which is around 80 ns to limit switching losses. The peak inductor current in PSM can
be approximated by:
space
(2)
space
When VIN decreases to typically 15% above VOUT, the TPS62170-Q1 does not enter Power Save Mode,
regardless of the load current. The device maintains output regulation in PWM mode.
8.4.3 100% Duty-Cycle Operation
The duty cycle of the buck converter is given by D = Vout/Vin and increases as the input voltage comes close to
the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal
setpoint. This allows the conversion of small input to output voltage differences, e.g. for longest operation time of
battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
space
(3)
where
IOUT is the output current,
RDS(on) is the RDS(on) of the high-side FET and
RLis the DC resistance of the inductor used.
space
8.4.4 Current Limit and Short Circuit Protection
The TPS6217x-Q1 devices are protected against heavy load and short circuit events. At heavy loads, the current
limit determines the maximum output current. If the current limit is reached, the high-side FET will be turned off.
Avoiding shoot through current, the low-side FET is then switched on to allow the inductor current to decrease.
The high-side FET will turn on again, only if the current in the low-side FET has decreased below the low side
current limit threshold.
( ) ns
L
VV
II OUTIN
HSLIMFtyppeak 30×
-
+= _)(
PD
L
LIMFtyppeak t
L
V
II ×+=
)(
10
TPS62170-Q1
,
TPS62171-Q1
,
TPS62172-Q1
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Device Functional Modes (continued)
The output current of the device is limited by the current limit (see Electrical Characteristics). Due to internal
propagation delay, the actual current can exceed the static current limit during that time. The dynamic current
limit can be calculated as follows:
space
(4)
where
ILIMF is the static current limit, specified in the electrical characteristic table,
L is the inductor value,
VLis the voltage across the inductor and
tPD is the internal propagation delay.
space
The dynamic high side switch peak current can be calculated as follows:
space
(5)
space
Care on the current limit has to be taken if the input voltage is high and very small inductances are used.
8.4.5 Operation Above TJ= 125°C
The operating junction temperature of the device is specified up to 125°C. In power supply circuits, the self
heating effect causes, that the junction temperature, TJ, is even higher than the ambient temperature TA.
Depending on TAand the load current, the maximum operating temperature TJcan be exceeded. However, the
electrical characteristics are specified up to a TJof 125°C only. The device operates as long as thermal
shutdown threshold is not triggered.
C2
22uF
3.3V / 0.5A
C1
10uF
2.2µH
VIN
TPS62170-Q1
R1
470k
R2
150k
VIN
EN
AGND
PGND
SW
VOS
PG
FB
100k
11
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,
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,
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(1) See Third-Party Products disclaimer.
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following information is intended to be a guideline through the individual power supply design process.
9.2 Typical TPS62170-Q1 Application
space
Figure 5. 3.3-V/0.5-A Power Supply
9.2.1 Design Requirements
The step-down converter design can be adapted to different output voltage and load current needs by choosing
external components appropriate. The following design procedure is adequate for whole VIN, VOUT and load
current range of TPS62170-Q1. Using Table 2, the design procedure needs minimum effort.
Table 1. List of Components
REFERENCE DESCRIPTION MANUFACTURER(1)
IC 17-V, 0.5-A step-down converter, WSON TPS62170QDSG, Texas Instruments
L1 2.2-µH, 1.4-A, 3 x 2.8 x 1.2 mm VLF3012ST-2R2M1R4, TDK
C1 10-µF, 25-V, ceramic Standard
C2 22-µF, 6.3-V, ceramic Standard
R1 Depending on Vout
R2 Depending on Vout
R3 100-kΩ, chip, 0603, 1/16-W, 1% Standard
space
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62170-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
2
(max)
(max)(max)
L
OUTL
I
II
D
+=
÷
ø
ö
ç
è
æ-= 1
0.8V
V
RR OUT
21
12
TPS62170-Q1
,
TPS62171-Q1
,
TPS62172-Q1
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(1) The values in the table are nominal values. Variations of typically ±20% due to tolerance, saturation and DC bias are assumed.
(2) This LC combination is the standard value and recommended for most applications.
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Programming the Output Voltage
While the output voltage of the TPS62170-Q1 is adjustable, the TPS62171-Q1 and TPS62172-Q1 are
programmed to a fixed output voltage. For fixed output versions, the FB pin is pulled down internally and may be
left floating. it is recommended to connect it to AGND to improve thermal resistance. The adjustable version can
be programmed for output voltages from 0.9 V to 6 V by using a resistive divider from VOUT to FB to AGND. The
voltage at the FB pin is regulated to 800 mV. The value of the output voltage is set by the selection of the
resistive divider from Equation 6. It is recommended to choose resistor values which allow a cross current of at
least 2 uA, meaning the value of R2 should not exceed 400 kΩ. Lower resistor values are recommended for
highest accuracy and most robust design. For applications requiring lowest current consumption, the use of fixed
output voltage versions is recommended.
space
(6)
space
In case the FB pin gets opened, the device clamps the output voltage at the VOS pin to about 7.4 V.
9.2.2.3 External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the devices
control loop. The TPS62170-Q1 is optimized to work within a range of external components. The LC output filters
inductance and capacitance have to be considered together, creating a double pole, responsible for the corner
frequency of the converter (see Output Filter and Loop Stability section). Table 2 can be used to simplify the
output filter component selection.
space
Table 2. Recommended LC Output Filter Combinations(1)
4.7µF 10µF 22µF 47µF 100µF 200µF 400µF
1µH
2.2µH √ √(2) √√√
3.3µH √√√√
4.7µH
More detailed information on further LC combinations can be found in SLVA463.
9.2.2.3.1 Inductor Selection
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-
PSM transition point and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under
static load conditions.
space
(7)
LPSMload II D=
2
1
)(
÷
÷
÷
÷
÷
ø
ö
ç
ç
ç
ç
ç
è
æ
×
-
×=D
SW
IN
OUT
OUTL fL
V
V
VI
(min)
(max)
(max)
1
13
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,
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,
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(1) IRMS at 40°C rise or ISAT at 30% drop.
(2) See Third-Party Products disclaimer.
(8)
where
IL(max) is the maximum inductor current,
ΔILis the Peak to Peak Inductor Ripple Current,
L(min) is the minimum effective inductor value and
fSW is the actual PWM Switching Frequency.
space
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS62170-Q1 and are recommended for use:
Table 3. List of Inductors
TYPE INDUCTANCE [µH] CURRENT [A](1) DIMENSIONS [L x B x H] mm MANUFACTURER(2)
VLF3012ST-2R2M1R4 2.2 µH, ±20% 1.9 A 3.0 x 2.8 x 1.2 TDK
VLF302512MT-2R2M 2.2 µH, ±20% 1.9 A 3.0 x 2.5 x 1.2 TDK
VLS252012-2R2 2.2 µH, ±20% 1.3 A 2.5 x 2.0 x 1.2 TDK
XFL3012-222MEC 2.2 µH, ±20% 1.9 A 3.0 x 3.0 x 1.2 Coilcraft
XFL3012-332MEC 3.3 µH, ±20% 1.6 A 3.0 x 3.0 x 1.2 Coilcraft
XPL2010-222MLC 2.2 µH, ±20% 1.3 A 1.9 x 2.0 x 1.0 Coilcraft
XPL2010-332MLC 3.3 µH, ±20% 1.1 A 1.9 x 2.0 x 1.0 Coilcraft
LPS3015-332ML 3.3 µH, ±20% 1.4 A 3.0 x 3.0 x 1.4 Coilcraft
PFL2512-222ME 2.2 µH, ±20% 1.0 A 2.8 x 2.3 x 1.2 Coilcraft
PFL2512-333ME 3.3 µH, ±20% 0.78 A 2.8 x 2.3 x 1.2 Coilcraft
744028003 3.3 µH, ±30% 1.0 A 2.8 x 2.8 x 1.1 Wuerth
PSI25201B-2R2MS 2.2 µH, ±20% 1.3 A 2.0 x 2.5 x 1.2 Cyntec
NR3015T-2R2M 2.2 µH, ±20% 1.5 A 3.0 x 3.0 x 1.5 Taiyo Yuden
BRC2012T2R2MD 2.2 µH, ±20% 1.0 A 2.0 x 1.25 x 1.4 Taiyo Yuden
BRC2012T3R3MD 3.3 µH, ±20% 0.87 A 2.0 x 1.25 x 1.4 Taiyo Yuden
The TPS6217x-Q1 can be run with an inductor as low as 2.2 µH. However, for applications running with low
input voltages, 3.3 µH is recommended, to allow the full output current. The inductor value also determines the
load current at which Power Save Mode is entered:
space
(9)
space
Using Equation 8, this current level can be adjusted by changing the inductor value.
÷
÷
ø
ö
ç
ç
è
æ+×
×
=
21
11
252
1
RRpF
fpole p
pFR
fzero 252
1
1××
=
p
CL
fLC
×
=
p2
1
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9.2.2.3.2 Capacitor Selection
9.2.2.3.2.1 Output Capacitor
The recommended value for the output capacitor is 22 µF. The architecture of the TPS6217x-Q1 allows the use
of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low
output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, it's recommended to use X7R or X5R dielectric. Using a higher value can
have some advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save Mode (see
SLVA463).
NOTE
In Power Save Mode, the output voltage ripple depends on the output capacitance, its
ESR and the peak inductor current. Using ceramic capacitors provides small ESR and low
ripple.
9.2.2.3.2.2 Input Capacitor
For most applications, 10 µF is sufficient and is recommended, though a larger value reduces input current ripple
further. The input capacitor buffers the input voltage for transient events and also decouples the converter from
the supply. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between VIN and GND as close as possible to those pins.
NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will
have a strong influence on the final effective capacitance. Therefore the right capacitor
value has to be chosen carefully. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.
9.2.2.4 Output Filter and Loop Stability
The devices of the TPS6217x-Q1 family are internally compensated to be stable with L-C filter combinations
corresponding to a corner frequency to be calculated with Equation 10:
space
(10)
space
Proven nominal values for inductance and ceramic capacitance are given in Table 2 and are recommended for
use. Different values may work, but care has to be taken on the loop stability which might be affected. More
information including a detailed L-C stability matrix can be found in SLVA463.
The TPS6217x-Q1 devices, both fixed and adjustable versions, include an internal 25-pF feedforward capacitor,
connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and
zero in the control loop with the resistors of the feedback divider, per Equation 11 and Equation 12:
space
(11)
space
(12)
space
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,
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Though the TPS6217x-Q1 devices are stable without the pole and zero being in a particular location, adjusting
their location to the specific needs of the application can provide better performance in Power Save mode and/or
improved transient response. An external feed-forward capacitor can also be added. A more detailed discussion
on the optimization for stability vs transient response can be found in SLVA289 and SLVA466.
If using ceramic capacitors, the DC bias effect has to be considered. The DC bias effect results in a drop in
effective capacitance as the voltage across the capacitor increases (see DC Bias effect NOTE in the Input
Capacitor section).
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1
VIN=5V
VIN=12V
VIN=17V
Output Current (A)
Efficiency (%)
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
IOUT=1mA IOUT=10mA
IOUT=100mA
IOUT=500mA
Input Voltage (V)
Efficiency (%)
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1
VIN=5V
VIN=12V
VIN=17V
Output Current (A)
Efficiency (%)
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1
VIN=5V
VIN=12V
VIN=17V
Output Current (A)
Efficiency (%)
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1
VIN=6V
VIN=12V
VIN=17V
Output Current (A)
Efficiency (%)
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
7 8 9 10 11 12 13 14 15 16 17
IOUT=1mA
IOUT=10mA
IOUT=100mA
IOUT=500mA
Input Voltage (V)
Efficiency (%)
G001
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9.2.3 Application Performance Plots
At VIN = 12 V, VOUT = 3.3 V and TJ= 25°C (unless otherwise noted)
Vout = 6 V
Figure 6. Efficiency vs Output Current
Vout = 6 V
Figure 7. Efficiency vs Input Voltage
Vout = 3.3 V
Figure 8. Efficiency vs Output Current
Vout = 3.3 V
Figure 9. Efficiency vs Input Voltage
Vout = 1.8 V
Figure 10. Efficiency vs Output Current
Vout = 1.8 V
Figure 11. Efficiency vs Input Voltage
0
0.5
1
1.5
2
2.5
3
3.5
4
0 0.1 0.2 0.3 0.4 0.5
Output Current (A)
Switching Frequency (MHz)
G000
0
0.5
1
1.5
2
2.5
3
3.5
4
4 6 8 10 12 14 16 18
IOUT=0.5A
Input Voltage (V)
Switching Frequency (MHz)
G000
3.20
3.25
3.30
3.35
0.0001 0.001 0.01 0.1 1
VIN=5V VIN=12V VIN=17V
Output Current (A)
Output Voltage (V)
G001
3.20
3.25
3.30
3.35
4 7 10 13 16
IOUT=1mA IOUT=10mA
IOUT=100mA IOUT=500mA
Input Voltage (V)
Output Voltage (V)
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.0001 0.001 0.01 0.1 1
VIN=5V
VIN=12V
VIN=17V
Output Current (A)
Efficiency (%)
G001
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
IOUT=1mA
IOUT=10mA IOUT=100mA IOUT=500mA
Input Voltage (V)
Efficiency (%)
G001
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At VIN = 12 V, VOUT = 3.3 V and TJ= 25°C (unless otherwise noted)
Vout = 0.9 V
Figure 12. Efficiency vs Output Current
Vout = 0.9 V
Figure 13. Efficiency vs Input Voltage
Figure 14. Output Voltage Accuracy (Load Regulation) Figure 15. Output Voltage Accuracy (Line Regulation)
Figure 16. Switching Frequency vs Output Current Figure 17. Switching Frequency vs Input Voltage
0
0.01
0.02
0.03
0.04
0.05
0 0.1 0.2 0.3 0.4 0.5
VIN=5V
VIN=12V
VIN=17V
Output Current (A)
Output Voltage Ripple (V)
G000
0
0.2
0.5
0.8
1
1.2
1.5
4 5 6 7 8 9 10 11 12 13 14 15 16 17
−40°C 25°C
85°C
Input Voltage (V)
Output Current (A)
G000
18
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At VIN = 12 V, VOUT = 3.3 V and TJ= 25°C (unless otherwise noted)
Figure 18. Output Voltage Ripple Figure 19. Maximum Output Current
Figure 20. PWM / PSM Mode Transition Figure 21. PWM to PSM Mode Transition
200 mA to 500 mA
Figure 22. Load Transient Response in PWM Mode
100 mA to 500 mA
Figure 23. Load Transient Response from Power Save
Mode
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At VIN = 12 V, VOUT = 3.3 V and TJ= 25°C (unless otherwise noted)
200 mA to 500 mA
Figure 24. Load Transient Response in PWM Mode, Rising
Edge
200 mA to 500 mA
Figure 25. Load Transient Response in PWM Mode, Falling
Edge
Iout = 100 mA
Figure 26. Startup to VOUT = 3.3 V
Iout = 500 mA
Figure 27. Startup to VOUT = 3.3 V
Iout = 66 mA
Figure 28. Typical Operation in Power Save Mode
Iout = 500 mA
Figure 29. Typical Operation in PWM Mode
22uF10uF
2.2µH
(5 .. 17)V
TPS62170-Q1
680k
130k
VIN
EN
AGND
PGND
SW
VOS
PG
FB
100k
5V / 0.5A
22uF10uF
2.2µH
TPS62170-Q1
680k
130k
VIN
EN
GND
PGND
SW
VOS
PG
FB
100k
-5V
10uF
maxINOUTIN VVV £+
20
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9.3 System Examples
9.3.1 Inverting Power Supply
The TPS62170-Q1 can be used as inverting power supply by rearranging external circuitry as shown in
Figure 30. As the former GND node now represents a voltage level below system ground, the voltage difference
between VIN and VOUT has to be limited for operation to the maximum supply voltage of 17 V (see Equation 13).
space
(13)
space
Figure 30. –5-V Inverting Power Supply
space
The transfer function of the inverting power supply configuration differs from the buck mode transfer function,
incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output
capacitance of at least 22 µF is recommended. A detailed design example is given in SLVA469.
9.3.2 Various Output Voltages
The TPS62170-Q1 can be set for different output voltages between 0.9 V and 6 V. Some examples are shown
below.
space
space
Figure 31. 5-V/0.5-A Power Supply
space
space
22uF10uF
2.2µH
(3 .. 17)V
TPS62170-Q1
130k
150k
VIN
EN
AGND
PGND
SW
VOS
PG
FB
100k
1.5V / 0.5A
22uF
1.8V / 0.5A
10uF
2.2µH
(3 .. 17)V
TPS62170-Q1
200k
160k
VIN
EN
AGND
PGND
SW
VOS
PG
FB
100k
22uF
2.5V / 0.5A
10uF
2.2µH
(3 .. 17)V
TPS62170-Q1
390k
180k
VIN
EN
AGND
PGND
SW
VOS
PG
FB
100k
22uF
3.3V / 0.5A
10uF
2.2µH
(3.3 .. 17)V
TPS62170-Q1
470k
150k
VIN
EN
AGND
PGND
SW
VOS
PG
FB
100k
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System Examples (continued)
Figure 32. 3.3-V/0.5-A Power Supply
space
space
Figure 33. 2.5-V/0.5-A Power Supply
space
space
Figure 34. 1.8-V/0.5-A Power Supply
space
space
Figure 35. 1.5-V/0.5-A Power Supply
space
space
22uF10uF
2.2µH
(3 .. 17)V
TPS62170-Q1
51k
200k
VIN
EN
AGND
PGND
SW
VOS
PG
FB
100k
1V / 0.5A
22uF10uF
2.2µH
(3 .. 17)V
TPS62170-Q1
75k
150k
VIN
EN
AGND
PGND
SW
VOS
PG
FB
100k
1.2V / 0.5A
22
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System Examples (continued)
Figure 36. 1.2-V/0.5-A Power Supply
space
space
Figure 37. 1-V/0.5-A Power Supply
space
10 Power Supply Recommendations
The TPS6217x-Q1 are designed to operate from a 3-V to 17-V input voltage supply. The input power supply's
output current needs to be rated according to the output voltage and the output current of the power rail
application.
VIN
GND VOUT
L1
R2 R1
C2
AGND
PG
VOS
C1
AGND
EN
VIN
PGND
SW
FB
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11 Layout
11.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TPS6217x-Q1 demands careful attention to ensure operation and
to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load),
stability and accuracy weaknesses, increased EMI radiation and noise sensitivity. Considering the following
topics ensures best electrical and optimized thermal performance:
1) The input capacitor must be placed as close as possible to the VIN and PGND pin of the IC. This provides low
resistive and inductive path for the high di/dt input current.
2) The VOS pin must be connect in the shortest way to VOUT at the output capacitor - avoiding noise coupling.
3) The feedback resistors, R1 and R2 must be connected close to the FB and AGND pins - avoiding noise
coupling.
4) The output capacitor should be placed such that its ground is as close as possible to the IC's PGND pins -
avoiding additional voltage drop in traces.
5) The inductor should be placed close to the SW pin and connect directly to the output capacitor - minimizing
the loop area between the SW pin, inductor, output capacitor and PGND pin.
More detailed information can be found in the EVM Users Guide,SLVU483.
The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve
appropriate power dissipation. Although the Exposed Thermal Pad can be connected to a floating circuit board
trace, the device will have better thermal performance if it is connected to a larger ground plane. The Exposed
Thermal Pad is electrically connected to AGND.
11.2 Layout Example
space
space
Figure 38. Layout Example
24
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11.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB by soldering the Exposed Thermal Pad
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Note (SZZA017), and (SPRA953).
The TPS6217x-Q1 are designed for a maximum operating junction temperature (TJ) of 125°C. Therefore the
maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance,
given by the package and the surrounding PCB structures. Since the thermal resistance of the package is fixed,
increasing the size of the surrounding copper area and improving the thermal connection to the IC can reduce
the thermal resistance. To get an improved thermal behavior, it's recommended to use top layer metal to connect
the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for
improved thermal performance.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
25
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62170-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.1.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
Optimizing the TPS62130/40/50/60/70 Output Filter Application Report (SLVA463)
Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor
Application Report (SLVA289)
Using a Feedforward Capacitor to Improve Stability and Bandwidth of TPS62130/40/50/60/70 Application Report
(SLVA466)
Using the TPS6215x in an Inverting Buck-Boost Topology Application Report (SLVA469)
TPS62160EVM-627 and TPS62170EVM-627 Evaluation Modules User's Guide (SLVU483)
Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs Application Report
(SZZA017)
Semiconductor and IC Package Thermal Metrics Application Report (SPRA953)
26
TPS62170-Q1
,
TPS62171-Q1
,
TPS62172-Q1
SLVSCK7D –DECEMBER 2014–REVISED FEBRUARY 2017
www.ti.com
Product Folder Links: TPS62170-Q1 TPS62171-Q1 TPS62172-Q1
Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
TPS62170-Q1 Click here Click here Click here Click here Click here
TPS62171-Q1 Click here Click here Click here Click here Click here
TPS62172-Q1 Click here Click here Click here Click here Click here
12.4 Trademarks
DCS-Control, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.7 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.8 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Feb-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS62170QDSGRQ1 ACTIVE WSON DSG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QUEQ
TPS62170QDSGTQ1 ACTIVE WSON DSG 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QUEQ
TPS62171QDSGRQ1 ACTIVE WSON DSG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QUFQ
TPS62171QDSGTQ1 ACTIVE WSON DSG 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QUFQ
TPS62172QDSGRQ1 ACTIVE WSON DSG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QUGQ
TPS62172QDSGTQ1 ACTIVE WSON DSG 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QUGQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Feb-2017
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS62170-Q1, TPS62171-Q1, TPS62172-Q1 :
•Catalog: TPS62170, TPS62171, TPS62172
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS62170QDSGRQ1 WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS62170QDSGTQ1 WSON DSG 8 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS62171QDSGRQ1 WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS62171QDSGTQ1 WSON DSG 8 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS62172QDSGRQ1 WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TPS62172QDSGTQ1 WSON DSG 8 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Feb-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS62170QDSGRQ1 WSON DSG 8 3000 210.0 185.0 35.0
TPS62170QDSGTQ1 WSON DSG 8 250 210.0 185.0 35.0
TPS62171QDSGRQ1 WSON DSG 8 3000 210.0 185.0 35.0
TPS62171QDSGTQ1 WSON DSG 8 250 210.0 185.0 35.0
TPS62172QDSGRQ1 WSON DSG 8 3000 210.0 185.0 35.0
TPS62172QDSGTQ1 WSON DSG 8 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Feb-2017
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
SEE OPTIONAL
TERMINAL 8X 0.3
0.2
1.6 0.1
2X
1.5
0.9 0.1
6X 0.5
8X 0.4
0.2
0.05
0.00
0.8 MAX
A2.1
1.9 B
2.1
1.9
0.3
0.2
0.4
0.2
(0.2) TYP
WSON - 0.8 mm max heightDSG0008A
PLASTIC SMALL OUTLINE - NO LEAD
4218900/B 09/2017
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
9
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 5.500
OPTIONAL TERMINAL
TYPICAL
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
8X (0.25)
(1.6)
(1.9)
6X (0.5)
(0.9) ( 0.2) VIA
TYP
(0.55)
8X (0.5)
(R0.05) TYP
WSON - 0.8 mm max heightDSG0008A
PLASTIC SMALL OUTLINE - NO LEAD
4218900/B 09/2017
SYMM
1
45
8
LAND PATTERN EXAMPLE
SCALE:20X
SYMM 9
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
www.ti.com
EXAMPLE STENCIL DESIGN
(R0.05) TYP
8X (0.25)
8X (0.5)
(0.9)
(0.7)
(1.9)
(0.45)
6X (0.5)
WSON - 0.8 mm max heightDSG0008A
PLASTIC SMALL OUTLINE - NO LEAD
4218900/B 09/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
SYMM
1
45
8
METAL
SYMM 9
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Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
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TPS62172QDSGRQ1 TPS62172QDSGTQ1