© 2002 Fairchild Semiconductor Corporation DS005971 www.fairchildsemi.com
October 1987
Revised April 2002
CD4049UBC • CD4050BC Hex Inverting Buffer • Hex Non-Inverting Buffer
CD4049UBC • CD4050BC
Hex Inver ti n g Bu f f e r •
Hex Non-Inverting Buffer
General Description
The CD4049UBC and CD4050BC hex buffers are mono-
lithic co mp le me nta ry M OS (CMOS) inte gra t ed circ u its c o n-
structed with N- and P-channel enhancement mode
transistors. These devices feature logic level conversion
using only on e supply volta ge (VDD). The inpu t signal h igh
level (VIH) can exce ed th e VDD su pply vol tage when these
devices are used for logic level conversions. These
devices are intended for use as hex buffers, CMOS to DTL/
TTL conve rters, o r as CM OS curren t driv ers, a nd at VDD =
5.0V, they can drive directly two DTL/TTL loads over the
full operating temperature range.
Features
■Wide supply voltage rang e: 3.0V to 15V
■Direct dri ve to 2 T TL load s at 5.0V over full tem perat ure
range
■High source and sink current capability
■Special input protection permits input voltages greater
than VDD
Applications
• CMOS hex invert er /bu ffer
• CMOS to DTL/TTL hex converter
• CMOS curr en t “sin k” or “sou rc e ” driv er
• CMOS HIGH-to-LOW logic level converter
Ordering Code:
Devices also available in Tape and Reel. Spe ci fy by append ing the suffix let t er “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP
CD4049UBC
Top View
CD4050BC
Top View
Order Number Package Number Package Description
CD4049UBCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4049UBCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD4050BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4050BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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CD4049UBC • CD4050BC
Schematic D ia gr a ms
CD4049UBC
1 of 6 Identical Units
CD4050BC
1 of 6 Identical Units
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CD4049UBC • CD4050BC
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions (Note 2)
Note 1: “Absolute Maximum Ratings” are those va lues beyond which the
safety of th e device ca nnot be guaranteed; th ey are not meant to imply th at
the devices should be operated at these limits. The table of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provides
conditions for actual device operation.
Note 2: VSS = 0V unles s ot herwise s pecified .
DC Electrical Characteristics (Note 3)
Note 3: VSS = 0V unless otherwise specified.
Supply Voltage (VDD)−0.5V to +18V
Input Voltage (VIN)−0.5V to +18V
Voltage at Any Output Pin (VOUT)−0.5V to VDD + 0.5V
Stora ge Temperatu re R ang e (TS)−65°C to +150°C
Power Di ssipa ti on (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 260 °C
Supply Voltage (VDD) 3V to 15V
Input Voltage (VIN) 0V to 15V
Voltage at Any Output Pin (VOUT) 0 to VDD
Operating Temperature Range (TA)
CD4049UBC, CD4050BC −55°C to +125°C
Symbol Parameter Conditions −55°C+25°C+125°CUnits
Min Max Min Typ Max Min Max
IDD Quiescent Device Current VDD = 5V 1.0 0.01 1.0 30 µAVDD = 10V 2.0 0.01 2.0 60
VDD = 15V 4.0 0.03 4.0 120
VOL LOW Level Output Voltage VIH = VDD, VIL = 0V,
|IO| < 1 µA
VDD = 5V 0.05 0 0.05 0.05 VVDD = 10V 0.05 0 0.05 0.05
VDD = 15V 0.05 0 0.05 0.05
VOH HIGH Level Output Voltage VIH = VDD, VIL = 0V,
|IO| < 1 µA
VDD = 5V 4.95 4.95 5 4.95 VVDD = 10V 9.95 9.95 10 9.95
VDD = 15V 14.95 14.95 15 14.95
VIL LOW Level Input Voltage |IO| < 1 µA
(CD4050BC Only) VDD = 5V, VO = 0.5V 1.5 2.25 1 .5 1.5 VVDD = 10V, VO = 1V 3.0 4.5 3.0 3.0
VDD = 15V, VO = 1.5V 4.0 6.75 4.0 4.0
VIL LOW Level Input Voltage |IO| < 1 µA
(CD4049UBC Only) VDD = 5V, VO = 4.5V 1.0 1.5 1.0 1.0 VVDD = 10V, VO = 9V 2.0 2.5 2.0 2.0
VDD = 15V, VO = 13.5V 3.0 3.5 3.0 3.0
VIH HIGH Level Input Voltage |IO| < 1 µA
(CD4050BC Only) VDD = 5V, VO = 4.5V 3.5 3.5 2.75 3.5 VVDD = 10V, VO = 9V 7.0 7.0 5. 5 7.0
VDD = 15V, VO = 13.5V 11.0 1 1.0 8.25 11 .0
VIH HIGH Level Input Voltage |IO| < 1 µA
(CD4049UBC Only) VDD = 5V, VO = 0.5V 4.0 4.0 3.5 4.0 VVDD = 10V, VO = 1V 8.0 8.0 7.5 8.0
VDD = 15V, VO = 1.5V 12.0 12.0 1 1.5 12.0
IOL LOW Level Output Current VIH = VDD, VIL = 0V
(Note 4) VDD = 5V, VO = 0.4V 5.6 4.6 5 3.2 mAVDD = 10V, VO = 0.5V 12 9.8 12 6.8
VDD = 15V, VO = 1.5V 35 29 40 20
IOH HIGH Level Output Current VIH = VDD, VIL = 0V
(Note 4) VDD = 5V, VO = 4.6V −1.3 −1.1 −1.6 −0.72 mAVDD = 10V, VO = 9.5V −2.6 −2.2 −3.6 −1.5
VDD = 15V, VO = 13.5V −8.0 −7.2 −12 −5
IIN Input Current VDD = 15V, VIN = 0V −0.1 −10−5−0.1 −1.0 µA
VDD = 15V, VIN = 15V 0.1 10−50.1 1.0
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CD4049UBC • CD4050BC
DC Electrical Characteristics (Continued)
Note 4: These ar e peak outpu t current capab ilities. Continu ous output current is r ated at 12 mA m aximum. Th e output curre nt should not be allowed to
exceed this value for ext ended p eriods of tim e. IOL and IOH are tested one output at a t im e.
AC Electrical Characteristics (Note 5)
CD4049UBC
TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise specified
Note 5: AC Parameters are guara nt eed by DC c orrelat ed testing.
AC Electrical Characteristics (Note 6)
CD4050BC
TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise specified
Note 6: AC Parameters are guara nt eed by DC c orrelat ed testing.
Symbol Parameter Conditions Min Typ Max Units
tPHL Propagation Delay Time VDD = 5V 30 65 nsHIGH-to-LOW Level VDD = 10V 20 40
VDD = 15V 15 30
tPLH Propagation Delay Time VDD = 5V 45 85 nsLOW-to-HIGH Level VDD = 10V 25 45
VDD = 15V 20 35
tTHL Transition Time VDD = 5V 30 60 nsHIGH-to-LOW Level VDD = 10V 20 40
VDD = 15V 15 30
tTLH Transition Time VDD = 5V 60 120 nsLOW-to-HIGH Level VDD = 10V 30 55
VDD = 15V 25 45
CIN Input Capacitance Any Input 15 22.5 pF
Symbol Parameter Conditions Min Typ Max Units
tPHL Propagation Delay Time VDD = 5V 60 110 nsHIGH-to-LOW Level VDD = 10V 25 55
VDD = 15V 20 30
tPLH Propagation Delay Time VDD = 5V 60 120 nsLOW-to-HIGH Level VDD = 10V 30 55
VDD = 15V 25 45
tTHL Transition Time VDD = 5V 30 60 nsHIGH-to-LOW Level VDD = 10V 20 40
VDD = 15V 15 30
tTLH Transition Time VDD = 5V 60 12 0 nsLOW-to-HIGH Level VDD = 10V 30 55
VDD = 15V 25 45
CIN Input Capacitance Any Input 5 7.5 pF
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CD4049UBC • CD4050BC
Switching Time Waveforms
Typical Applications
CMOS to TLL or CMOS at a Lower VDD
VDD1 ≥ VDD2
In the case of the C D 4049UBC t he output d riv e c apability inc r eases with increas ing input v olt age.
E.g., If VDD1 = 10V the C D 4049UBC c ould driv e 4 T T L loads.
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CD4049UBC • CD4050BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
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CD4049UBC • CD4050BC Hex Inverting Buff er • Hex Non-Inverting Buffer
Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume an y responsibility for u se of any circuitry d escribed, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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sonably expected to result in a significant injury to the
user.
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