ATmega328/P
AVR® Microcontroller with picoPower® Technology
Introduction
The picoPower® ATmega328/P is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega328/P achieves
throughputs close to 1 MIPS per MHz. This empowers system designers to optimize the device for power
consumption versus processing speed.
Feature
High Performance, Low-Power AVR® 8-Bit Microcontroller Family
Advanced RISC Architecture
131 Powerful instructions
Most single clock cycle execution
32 x 8 General purpose working registers
Fully static operation
Up to 20 MIPS throughput at 20 MHz
On-chip 2-cycle multiplier
High Endurance Nonvolatile Memory Segments
32K Bytes of in-system self-programmable Flash program memory
1K Bytes EEPROM
2K Bytes internal SRAM
Write/erase cycles: 10,000 Flash/100,000 EEPROM
Data retention: 20 years at 85°C/100 years at 25°C(1)
Optional boot code section with independent lock bits
In-system programming by on-chip boot program
True read-while-write operation
Programming lock for software security
QTouch Library Support
Capacitive touch buttons, sliders and wheels
QTouch and QMatrix acquisition
Up to 64 sense channels
Peripheral Features
Two 8-bit Timer/counters with separate prescaler and Compare mode
One 16-bit Timer/counter with separate prescaler, Compare mode, and Capture mode
Real time counter with separate oscillator
Six PWM channels
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 1
8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature measurement
6-channel 10-bit ADC in PDIP package
Temperature measurement
Two master/slave SPI serial interface
One programmable serial USART
One byte-oriented 2-wire serial interface (Philips I2C compatible)
Programmable watchdog timer with separate on-chip oscillator
One on-chip analog comparator
Interrupt and wake-up on pin change
Special Microcontroller Features
Power-on Reset and programmable Brown-out Detection
Internal calibrated oscillator
External and internal interrupt sources
Six sleep modes: idle, ADC noise reduction, power-save, power-down, standby, and extended
standby
I/O and Packages
23 Programmable I/O lines
28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
Operating Voltage:
1.8 - 5.5V
Temperature Range:
-40°C to 105°C
Speed Grade:
ATmega328/P: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Power Consumption at 1 MHz, 1.8V, 25°C
Active mode: 0.2 mA
Power-Down mode: 0.1 μA
Power-Save mode: 0.75 μA (Including 32 kHz RTC)
ATmega328/P
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 2
Table of Contents
Introduction......................................................................................................................1
Feature............................................................................................................................ 1
1. Description.................................................................................................................9
2. Configuration Summary...........................................................................................10
3. Ordering Information ...............................................................................................11
3.1. ATmega328 ............................................................................................................................... 11
3.2. ATmega328P .............................................................................................................................11
4. Block Diagram......................................................................................................... 13
5. Pin Configurations................................................................................................... 14
5.1. Pinout......................................................................................................................................... 14
5.2. Pin Descriptions......................................................................................................................... 17
6. I/O Multiplexing........................................................................................................19
7. Resources............................................................................................................... 21
8. Data Retention.........................................................................................................22
9. About Code Examples.............................................................................................23
10. Capacitive Touch Sensing....................................................................................... 24
10.1. QTouch Library........................................................................................................................... 24
11. AVR CPU Core........................................................................................................ 25
11.1. Overview.................................................................................................................................... 25
11.2. Arithmetic Logic Unit (ALU)........................................................................................................ 26
11.3. Status Register...........................................................................................................................26
11.4. General Purpose Register File................................................................................................... 29
11.5. Stack Pointer..............................................................................................................................30
11.6. Instruction Execution Timing...................................................................................................... 32
11.7. Reset and Interrupt Handling..................................................................................................... 33
12. AVR Memories.........................................................................................................36
12.1. Overview.................................................................................................................................... 36
12.2. In-System Reprogrammable Flash Program Memory................................................................36
12.3. SRAM Data Memory.................................................................................................................. 37
12.4. EEPROM Data Memory............................................................................................................. 38
12.5. I/O Memory.................................................................................................................................39
12.6. Register Description................................................................................................................... 40
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 3
13. System Clock and Clock Options............................................................................ 49
13.1. Clock Systems and Their Distribution........................................................................................ 49
13.2. Clock Sources............................................................................................................................ 50
13.3. Low-Power Crystal Oscillator..................................................................................................... 52
13.4. Full Swing Crystal Oscillator.......................................................................................................54
13.5. Low-Frequency Crystal Oscillator.............................................................................................. 55
13.6. Calibrated Internal RC Oscillator................................................................................................56
13.7. 128 kHz Internal Oscillator......................................................................................................... 57
13.8. External Clock............................................................................................................................ 58
13.9. Timer/Counter Oscillator.............................................................................................................59
13.10. Clock Output Buffer....................................................................................................................59
13.11. System Clock Prescaler............................................................................................................. 59
13.12. Register Description...................................................................................................................60
14. Power Management and Sleep Modes................................................................... 64
14.1. Overview.................................................................................................................................... 64
14.2. Sleep Modes.............................................................................................................................. 64
14.3. BOD Disable...............................................................................................................................65
14.4. Idle Mode....................................................................................................................................65
14.5. ADC Noise Reduction Mode...................................................................................................... 65
14.6. Power-Down Mode.....................................................................................................................66
14.7. Power-Save Mode......................................................................................................................66
14.8. Standby Mode............................................................................................................................ 67
14.9. Extended Standby Mode............................................................................................................67
14.10. Power Reduction Register......................................................................................................... 67
14.11. Minimizing Power Consumption................................................................................................. 67
14.12. Register Description...................................................................................................................69
15. System Control and Reset.......................................................................................74
15.1. Resetting the AVR...................................................................................................................... 74
15.2. Reset Sources............................................................................................................................74
15.3. Power-on Reset..........................................................................................................................75
15.4. External Reset............................................................................................................................76
15.5. Brown-out Detection...................................................................................................................76
15.6. Watchdog System Reset............................................................................................................77
15.7. Internal Voltage Reference.........................................................................................................77
15.8. Watchdog Timer......................................................................................................................... 78
15.9. Register Description................................................................................................................... 80
16. Interrupts................................................................................................................. 84
16.1. Interrupt Vectors in ATmega328/P............................................................................................. 84
16.2. Register Description................................................................................................................... 86
17. EXTINT - External Interrupts................................................................................... 89
17.1. Pin Change Interrupt Timing.......................................................................................................89
17.2. Register Description................................................................................................................... 90
18. I/O-Ports.................................................................................................................. 99
ATmega328/P
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 4
18.1. Overview.................................................................................................................................... 99
18.2. Ports as General Digital I/O......................................................................................................100
18.3. Alternate Port Functions...........................................................................................................103
18.4. Register Description................................................................................................................. 115
19. 8-bit Timer/Counter0 (TC0) with PWM.................................................................. 127
19.1. Features................................................................................................................................... 127
19.2. Overview.................................................................................................................................. 127
19.3. Timer/Counter Clock Sources.................................................................................................. 129
19.4. Counter Unit............................................................................................................................. 129
19.5. Output Compare Unit............................................................................................................... 130
19.6. Compare Match Output Unit.....................................................................................................132
19.7. Modes of Operation..................................................................................................................134
19.8. Timer/Counter Timing Diagrams.............................................................................................. 138
19.9. Register Description................................................................................................................. 140
20. 16-bit Timer/Counter1 (TC1) with PWM................................................................ 152
20.1. Overview.................................................................................................................................. 152
20.2. Features................................................................................................................................... 152
20.3. Block Diagram.......................................................................................................................... 152
20.4. Definitions.................................................................................................................................153
20.5. Registers.................................................................................................................................. 154
20.6. Accessing 16-bit Timer/Counter Registers...............................................................................154
20.7. Timer/Counter Clock Sources.................................................................................................. 157
20.8. Counter Unit............................................................................................................................. 157
20.9. Input Capture Unit.................................................................................................................... 158
20.10. Output Compare Units............................................................................................................. 160
20.11. Compare Match Output Unit.....................................................................................................162
20.12. Modes of Operation..................................................................................................................163
20.13. Timer/Counter 0, 1 Prescalers................................................................................................. 171
20.14. Timer/Counter Timing Diagrams.............................................................................................. 171
20.15. Register Description.................................................................................................................173
21. Timer/Counter 0, 1 Prescalers...............................................................................186
21.1. Internal Clock Source............................................................................................................... 186
21.2. Prescaler Reset........................................................................................................................186
21.3. External Clock Source..............................................................................................................186
21.4. Register Description................................................................................................................. 188
22. 8-bit Timer/Counter2 (TC2) with PWM and Asynchronous Operation...................190
22.1. Features................................................................................................................................... 190
22.2. Overview.................................................................................................................................. 190
22.3. Timer/Counter Clock Sources.................................................................................................. 192
22.4. Counter Unit............................................................................................................................. 192
22.5. Output Compare Unit............................................................................................................... 193
22.6. Compare Match Output Unit.....................................................................................................195
22.7. Modes of Operation..................................................................................................................196
22.8. Timer/Counter Timing Diagrams.............................................................................................. 200
ATmega328/P
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 5
22.9. Asynchronous Operation of Timer/Counter2............................................................................201
22.10. Timer/Counter Prescaler.......................................................................................................... 203
22.11. Register Description................................................................................................................. 203
23. Serial Peripheral Interface (SPI)............................................................................218
23.1. Features................................................................................................................................... 218
23.2. Overview.................................................................................................................................. 218
23.3. SS Pin Functionality................................................................................................................. 222
23.4. Data Modes..............................................................................................................................222
23.5. Register Description................................................................................................................. 223
24. Universal Synchronous Asynchronous Receiver Transceiver (USART)............... 228
24.1. Features................................................................................................................................... 228
24.2. Overview.................................................................................................................................. 228
24.3. Block Diagram.......................................................................................................................... 228
24.4. Clock Generation......................................................................................................................229
24.5. Frame Formats.........................................................................................................................232
24.6. USART Initialization................................................................................................................. 233
24.7. Data Transmission – The USART Transmitter......................................................................... 234
24.8. Data Reception – The USART Receiver.................................................................................. 236
24.9. Asynchronous Data Reception.................................................................................................240
24.10. Multi-Processor Communication Mode.................................................................................... 243
24.11. Examples of Baud Rate Setting............................................................................................... 243
24.12. Register Description.................................................................................................................246
25. USART in SPI (USARTSPI) Mode.........................................................................256
25.1. Features................................................................................................................................... 256
25.2. Overview.................................................................................................................................. 256
25.3. Clock Generation......................................................................................................................256
25.4. SPI Data Modes and Timing.....................................................................................................257
25.5. Frame Formats.........................................................................................................................257
25.6. Data Transfer............................................................................................................................259
25.7. AVR USART MSPIM vs. AVR SPI............................................................................................260
25.8. Register Description................................................................................................................. 261
26. Two-Wire Serial Interface (TWI)............................................................................ 262
26.1. Features................................................................................................................................... 262
26.2. Two-Wire Serial Interface Bus Definition..................................................................................262
26.3. Data Transfer and Frame Format.............................................................................................263
26.4. Multi-Master Bus Systems, Arbitration, and Synchronization...................................................266
26.5. Overview of the TWI Module.................................................................................................... 268
26.6. Using the TWI...........................................................................................................................270
26.7. Transmission Modes................................................................................................................ 273
26.8. Multi-Master Systems and Arbitration...................................................................................... 291
26.9. Register Description................................................................................................................. 292
27. Analog Comparator (AC).......................................................................................300
27.1. Overview.................................................................................................................................. 300
ATmega328/P
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 6
27.2. Analog Comparator Multiplexed Input...................................................................................... 300
27.3. Register Description................................................................................................................. 301
28. Analog-to-Digital Converter (ADC)........................................................................ 305
28.1. Features................................................................................................................................... 305
28.2. Overview.................................................................................................................................. 305
28.3. Starting a Conversion...............................................................................................................307
28.4. Prescaling and Conversion Timing...........................................................................................308
28.5. Changing Channel or Reference Selection.............................................................................. 310
28.6. ADC Noise Canceler................................................................................................................ 312
28.7. ADC Conversion Result........................................................................................................... 315
28.8. Temperature Measurement...................................................................................................... 316
28.9. Register Description................................................................................................................. 316
29. debugWIRE On-chip Debug System.....................................................................325
29.1. Features................................................................................................................................... 325
29.2. Overview.................................................................................................................................. 325
29.3. Physical Interface..................................................................................................................... 325
29.4. Software Breakpoints............................................................................................................... 326
29.5. Limitations of debugWIRE........................................................................................................326
29.6. Register Description................................................................................................................. 326
30. Boot Loader Support – Read-While-Write Self-programming (BTLDR)................ 328
30.1. Features................................................................................................................................... 328
30.2. Overview.................................................................................................................................. 328
30.3. Application and Boot Loader Flash Sections............................................................................328
30.4. Read-While-Write and No Read-While-Write Flash Sections...................................................329
30.5. Boot Loader Lock Bits.............................................................................................................. 331
30.6. Entering the Boot Loader Program...........................................................................................332
30.7. Addressing the Flash During Self-Programming...................................................................... 333
30.8. Self-Programming the Flash.....................................................................................................334
30.9. Register Description................................................................................................................. 342
31. Memory Programming (MEMPROG).....................................................................345
31.1. Program And Data Memory Lock Bits...................................................................................... 345
31.2. Fuse Bits.................................................................................................................................. 346
31.3. Signature Bytes........................................................................................................................348
31.4. Calibration Byte........................................................................................................................349
31.5. Serial Number.......................................................................................................................... 349
31.6. Page Size.................................................................................................................................349
31.7. Parallel Programming Parameters, Pin Mapping, and Commands..........................................349
31.8. Parallel Programming...............................................................................................................351
31.9. Serial Downloading.................................................................................................................. 359
32. Electrical Characteristics....................................................................................... 364
32.1. Absolute Maximum Ratings......................................................................................................364
32.2. Common DC Characteristics....................................................................................................364
32.3. Speed Grades.......................................................................................................................... 367
ATmega328/P
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 7
32.4. Clock Characteristics................................................................................................................368
32.5. System and Reset Characteristics........................................................................................... 369
32.6. SPI Timing Characteristics....................................................................................................... 370
32.7. Two-Wire Serial Interface Characteristics................................................................................ 371
32.8. ADC Characteristics................................................................................................................. 373
32.9. Parallel Programming Characteristics...................................................................................... 374
33. Typical Characteristics (TA = -40°C to 85°C).........................................................377
33.1. ATmega328 Typical Characteristics......................................................................................... 377
34. Typical Characteristics (TA = -40°C to 105°C).......................................................402
34.1. ATmega328P Typical Characteristics.......................................................................................402
35. Register Summary.................................................................................................427
35.1. Note..........................................................................................................................................429
36. Instruction Set Summary....................................................................................... 431
37. Packaging Information...........................................................................................436
37.1. 32-pin 32A................................................................................................................................436
37.2. 32-pin 32M1-A..........................................................................................................................437
37.3. 28-pin 28M1............................................................................................................................. 438
37.4. 28-pin 28P3..............................................................................................................................438
38. Errata.....................................................................................................................440
38.1. Errata ATmega328/P................................................................................................................440
39. Datasheet Revision History................................................................................... 441
39.1. Rev. A – 2/2018........................................................................................................................441
39.2. Pre Microchip Revisions...........................................................................................................441
The Microchip Web Site.............................................................................................. 442
Customer Change Notification Service........................................................................442
Customer Support....................................................................................................... 442
Microchip Devices Code Protection Feature............................................................... 442
Legal Notice.................................................................................................................443
Trademarks................................................................................................................. 443
Quality Management System Certified by DNV...........................................................444
Worldwide Sales and Service......................................................................................445
ATmega328/P
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 8
1. Description
The AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to
be accessed in a single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega328/P provides the following features: 32Kbytes of in-system programmable Flash with read-
while-write capabilities, 1Kbytes EEPROM, 2Kbytes SRAM, 23 general purpose I/O lines, 32 general
purpose working registers, Real Time Counter (RTC), three flexible timer/counters with Compare modes
and PWM, 1 serial programmable USARTs , 1 byte-oriented 2-wire Serial Interface (I2C), a 6-channel 10-
bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable watchdog timer with internal
oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the
CPU while allowing the SRAM, timer/counters, SPI port, and interrupt system to continue functioning. The
Power-Down mode saves the register contents but freezes the oscillator, disabling all other chip functions
until the next interrupt or hardware Reset. In Power-Save mode, the asynchronous timer continues to run,
allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise
Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC to minimize
switching noise during ADC conversions. In Standby mode, the crystal/resonator oscillator is running
while the rest of the device is sleeping. This allows very fast start-up combined with low-power
consumption. In Extended Standby mode, both the main oscillator and the asynchronous timer continue
to run.
Microchip offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust
sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression
(AKS) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain
allows you to explore, develop and debug your own touch applications.
The device is manufactured using Microchip’s high density nonvolatile memory technology. The on-chip
ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by
a conventional nonvolatile memory programmer, or by an on-chip boot program running on the AVR core.
The boot program can use any interface to download the application program in the application Flash
memory. Software in the boot Flash section will continue to run while the application Flash section is
updated, providing true read-while-write operation. By combining an 8-bit RISC CPU with in-system self-
programmable Flash on a monolithic chip, the ATmega328/P is a powerful microcontroller that provides a
highly flexible and cost effective solution to many embedded control applications.
The ATmega328/P is supported with a full suite of program and system development tools including: C
compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
ATmega328/P
Description
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 9
2. Configuration Summary
Features ATmega328/P
Pin Count 28/32
Flash (Bytes) 32K
SRAM (Bytes) 2K
EEPROM (Bytes) 1K
General Purpose I/O Lines 23
SPI 2
TWI (I2C) 1
USART 1
ADC 10-bit 15 kSPS
ADC Channels 8
8-bit Timer/Counters 2
16-bit Timer/Counters 1
ATmega328/P
Configuration Summary
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 10
3. Ordering Information
3.1 ATmega328
Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1) Operational Range
20 1.8 - 5.5 ATmega328-AU
ATmega328-AUR(5)
ATmega328-MMH(4)
ATmega328-MMHR(4)(5)
ATmega328-MU
ATmega328-MUR(5)
ATmega328-PU
32A
32A
28M1
28M1
32M1-A
32M1-A
28P3
Industrial
(-40°C to 85°C)
Note: 
1. This device can also be supplied in wafer form. Please contact your local Microchip sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Please refer to Speed Grades for Speed vs. VCC
4. Tape & Reel.
5. NiPdAu Lead Finish.
Package Type
28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
3.2 ATmega328P
Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1) Operational Range
20 1.8 - 5.5 ATmega328P-AU
ATmega328P-AUR(5)
ATmega328P-MMH(4)
ATmega328P-MMHR(4)(5)
ATmega328P-MU
32A
32A
28M1
28M1
32M1-A
Industrial
(-40°C to 85°C)
ATmega328/P
Ordering Information
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 11
Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1) Operational Range
ATmega328P-MUR(5)
ATmega328P-PU
32M1-A
28P3
ATmega328P-AN
ATmega328P-ANR(5)
ATmega328P-MN
ATmega328P-MNR(5)
ATmega328P-PN
32A
32A
32M1-A
32M1-A
28P3
Industrial
(-40°C to 105°C)
Note: 
1. This device can also be supplied in wafer form. Please contact your local Microchip sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Please refer to Speed Grades for Speed vs. VCC
4. Tape & Reel.
5. NiPdAu Lead Finish.
Package Type
28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
ATmega328/P
Ordering Information
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 12
4. Block Diagram
Figure 4-1. Block Diagram
CPU
USART
ADC
ADC[7:0]
AREF
RxD0
TxD0
XCK0
I/O
PORTS
D
A
T
A
B
U
S
GPIOR[2:0]
SRAM
OCD
EXTINT
FLASH
NVM
programming
debugWire
I
N
/
O
U
T
D
A
T
A
B
U
S
TC 0
(8-bit)
SPI
AC
AIN0
AIN1
ADCMUX
EEPROM
EEPROMIF
TC 1
(16-bit)
OC1A/B
T1
ICP1
TC 2
(8-bit async)
TWI SDA0
SCL0
Internal
Reference
Watchdog
Timer
Power
management
and clock
control
VCC
GND
Clock generation
8MHz
Calib RC
128kHz int
osc
32.768kHz
XOSC
External
clock
Power
Supervision
POR/BOD &
RESET
XTAL2 /
TOSC2
RESET
XTAL1 /
TOSC1
16MHz LP
XOSC
PCINT[23:0]
INT[1:0]
T0
OC0A
OC0B
MISO0
MOSI0
SCK0
SS0
OC2A
OC2B
PB[7:0]
PC[6:0]
PD[7:0]
ADC6,ADC7,PC[5:0]
AREF
PD[7:0], PC[6:0], PB[7:0]
PD3, PD2
PB1, PB2
PD5
PB0
PB3
PD3
PD4
PD6
PD5
PB4
PB3
PB5
PB2
PD6
PD7
ADC6, ADC7
PC[5:0]
PD0
PD1
PD4
PC4
PC5
ATmega328/P
Block Diagram
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 13
5. Pin Configurations
5.1 Pinout
Figure 5-1. 28-pin PDIP
Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
(PCINT14/RESET) PC6
(PCINT16/RXD) PD0
(PCINT17/TXD) PD1
(PCINT18/INT0) PD2
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
PB4 (MISO/PCINT4)
PB3 (MOSI/OC2A/PCINT3)
PB2 (SS/OC1B/PCINT2)
PB1 (OC1A/PCINT1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ATmega328/P
Pin Configurations
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 14
Figure 5-2. 28-pin MLF Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
Bottom pad should be
soldered to ground
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
21
20
19
18
17
16
15
28
27
26
25
24
23
22
ATmega328/P
Pin Configurations
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 15
Figure 5-3. 32-pin TQFP Top View
1
2
3
4
32
31
30
29
28
27
26
5
6
7
8
24
23
22
21
20
19
18
17
25
9
10
11
12
13
14
15
16
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4
ATmega328/P
Pin Configurations
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 16
Figure 5-4. 32-pin MLF Top View
1
2
3
4
32
31
30
29
28
27
26
5
6
7
8
24
23
22
21
20
19
18
17
25
9
10
11
12
13
14
15
16
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
Bottom pad should be
soldered to ground
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
5.2 Pin Descriptions
5.2.1 VCC
Digital supply voltage pin.
5.2.2 GND
Ground.
5.2.3 Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port B
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
B pins are tri-stated during a Reset condition even if the clock is not running.
ATmega328/P
Pin Configurations
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 17
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting oscillator
amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting oscillator
amplifier.
If the internal calibrated RC oscillator is used as chip clock source, PB[7:6] is used as TOSC[2:1] input for
the asynchronous timer/counter2 if the AS2 bit in ASSR is set.
5.2.4 Port C (PC[5:0])
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The PC[5:0]
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
C pins are tri-stated during a Reset condition even if the clock is not running.
5.2.5 PC6/RESET
If the RSTDISBL fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of
PC6 differ from those of the other pins of Port C.
If the RSTDISBL fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer
than the minimum pulse length will generate a Reset, even if the clock is not running. Shorter pulses are
not guaranteed to generate a Reset.
The various special features of Port C are elaborated in the Alternate Functions of Port C section.
5.2.6 Port D (PD[7:0])
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port D
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
D pins are tri-stated during a Reset condition even if the clock is not running.
5.2.7 AVCC
AVCC is the supply voltage pin for the A/D Converter (ADC), PC[3:0], and PE[3:2]. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through
a low-pass filter. Note that PC[6:4] use digital supply voltage, VCC.
5.2.8 AREF
AREF is the analog reference pin for the A/D Converter.
5.2.9 ADC[7:6]
In the TQFP and VFQFN package, ADC[7:6] serve as analog inputs to the A/D converter. These pins are
powered by the analog supply and serve as 10-bit ADC channels.
ATmega328/P
Pin Configurations
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 18
6. I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions.
The following table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 6-1. PORT Function Multiplexing
(32-pin
MLF/TQFP)
Pin#
(28-pin
MLF) Pin#
(28-pin
PIPD) Pin#
PAD EXTINT PCINT ADC/AC OSC T/C #0 T/C
#1
USART 0 I2C 0 SPI 0
1 1 5 PD3 INT1 PCINT19 OC2B
2 2 6 PD4 PCINT20 T0 XCK0
4 3 7 VCC
3 4 8 GND
6 - - VCC
5 - - GND
7 5 9 PB6 PCINT6 XTAL1/
TOSC1
8 6 10 PB7 PCINT7 XTAL2/
TOSC2
9 7 11 PD5 PCINT21 OC0B T1
10 8 12 PD6 PCINT22 AIN0 OC0A
11 9 13 PD7 PCINT23 AIN1
12 10 14 PB0 PCINT0 CLKO ICP1
13 11 15 PB1 PCINT1 OC1A
14 12 16 PB2 PCINT2 OC1B SS0
15 13 17 PB3 PCINT3 OC2A MOSI0
16 14 18 PB4 PCINT4 MISO0
17 15 19 PB5 PCINT5 SCK0
18 16 20 AVCC
19 - - ADC6 ADC6
20 17 21 AREF
21 18 22 GND
22 - - ADC7 ADC7
23 19 13 PC0 PCINT8 ADC0
24 20 24 PC1 PCINT9 ADC1
25 21 25 PC2 PCINT10 ADC2
26 22 26 PC3 PCINT11 ADC3
27 23 27 PC4 PCINT12 ADC4 SDA0
28 24 28 PC5 PCINT13 ADC5 SCL0
ATmega328/P
I/O Multiplexing
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 19
(32-pin
MLF/TQFP)
Pin#
(28-pin
MLF) Pin#
(28-pin
PIPD) Pin#
PAD EXTINT PCINT ADC/AC OSC T/C #0 T/C
#1
USART 0 I2C 0 SPI 0
29 25 1 PC6/RESET PCINT14
30 26 2 PD0 PCINT16 RXD0
31 27 3 PD1 PCINT17 TXD0
32 28 4 PD2 INT0 PCINT18
ATmega328/P
I/O Multiplexing
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 20
7. Resources
A comprehensive set of development tools, application notes, and datasheets are available for download
on http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus.
ATmega328/P
Resources
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 21
8. Data Retention
Reliability qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C.
ATmega328/P
Data Retention
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 22
9. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compilation. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C
is compiler dependent. Confirm with the C compiler documentation for more details.
For I/O registers located in extended I/O map, IN, OUT, SBIS, SBIC, CBI, and SBI instructions must be
replaced with instructions that allow access to extended I/O. Typically LDS and STS combined with SBRS,
SBRC, SBR, and CBR.
ATmega328/P
About Code Examples
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 23
10. Capacitive Touch Sensing
10.1 QTouch Library
The QTouch® library provides a simple to use solution to realize touch sensitive interfaces on most AVR®
microcontrollers. The QTouch library includes support for the QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate QTouch library for the AVR
microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and
then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor
states.
The QTouch library is FREE and downloadable from QTouch Library . For implementation details and
other information, refer to the QTouch Library User Guide, also available for download from the Microchip
website.
ATmega328/P
Capacitive Touch Sensing
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 24
11. AVR CPU Core
11.1 Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must, therefore, be able to access memories, perform
calculations, control peripherals, and handle interrupts.
Figure 11-1. Block Diagram of the AVR Architecture
Register file
Flash program
memory
Program
counter
Instruction
register
Instruction
decode
Data memory
ALU
Status
register
R0R1
R2R3
R4R5
R6R7
R8R9
R10R11
R12R13
R14R15
R16R17
R18R19
R20R21
R22R23
R24R25
R26 (XL)R27 (XH)
R28 (YL)R29 (YH)
R30 (ZL)R31 (ZH)
Stack
pointer
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Reprogrammable Flash memory.
The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the register file, the operation is executed, and the result is
stored back in the register file – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space
addressing – enabling efficient address calculations. One of these address pointers can be used as an
ATmega328/P
AVR CPU Core
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 25
address pointer for lookup tables in Flash program memory. These added function registers are the 16-bit
X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic operation, the
Status register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly
address the whole address space. Most AVR instructions have a single 16-bit word format. Every
program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided into two sections, the Boot Program section and the Application
Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.
The Stack is effectively allocated in the general data SRAM, and consequently, the Stack size is only
limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the Stack
Pointer (SP) in the Reset routine (before subroutines or interrupts are executed). The SP is read/write
accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt
enable bit in the Status register. All interrupts have a separate interrupt vector in the interrupt vector table.
The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt
vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control registers, SPI, and
other I/O functions. The I/O memory can be accessed directly, or as the data space locations following
those of the register file, 0x20 - 0x5F. In addition, this device has extended I/O space from 0x60 - 0xFF in
SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
11.2 Arithmetic Logic Unit (ALU)
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working
registers. Within a single clock cycle, arithmetic operations between general purpose registers or
between a register and an immediate are executed. The ALU operations are divided into three main
categories: arithmetic, logical, and bit-functions. Some implementations of the architecture provide a
powerful multiplier supporting both signed/unsigned multiplication and fractional format. See Instruction
Set Summary section for a detailed description.
Related Links
Instruction Set Summary
11.3 Status Register
The Status register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. The Status register is updated after all ALU operations, as specified in the instruction set
reference. This will in many cases remove the need for using the dedicated compare instructions,
resulting in faster and more compact code.
ATmega328/P
AVR CPU Core
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 26
The Status register is not automatically stored when entering an interrupt routine and restored when
returning from an interrupt. This must be handled by software.
ATmega328/P
AVR CPU Core
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 27
11.3.1 Status Register
Name:  SREG
Offset:  0x5F
Reset:  0x00
Property:  When addressing as I/O Register: address offset is 0x3F
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 – I Global Interrupt Enable
The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable
control is then performed in separate control registers. If the Global Interrupt Enable register is cleared,
none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is
cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI
instructions, as described in the instruction set reference.
Bit 6 – T Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for
the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a
bit in T can be copied into a bit in a register in the register file by the BLD instruction.
Bit 5 – H Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. Half carry flag is useful in BCD
arithmetic. See the Instruction Set Description for detailed information.
Bit 4 – S Sign Flag, S = N V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag
V. See the Instruction Set Description for detailed information.
Bit 3 – V Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetic. See the Instruction Set
Description for detailed information.
Bit 2 – N Negative Flag
The negative flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
Bit 1 – Z Zero Flag
The zero flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
ATmega328/P
AVR CPU Core
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 28
Bit 0 – C Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description
for detailed information.
11.4 General Purpose Register File
The register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required
performance and flexibility, the following input/output schemes are supported by the register file:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 11-2. AVR CPU General Purpose Working Registers
7
0
Addr.
0x00
0x01
0x02
0x0D
General
0x0E
Purpose
0x0F
Working
0x10
Registers
0x11
0x1A
X-register Low Byte
0x1B
X-register High Byte
0x1C
Y-register Low Byte
0x1D
Y-register High Byte
0x1E
Z-register Low Byte
0x1F
Z-register High Byte
Most of the instructions operating on the register file have direct access to all registers, and most of them
are single cycle instructions. As shown in the figure, each register is also assigned a data memory
address, mapping them directly into the first 32 locations of the user data space. Although not being
physically implemented as SRAM locations, this memory organization provides great flexibility in access
of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.
11.4.1 The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage. These registers are
16-bit address pointers for indirect addressing of the data space. The three indirect address registers X,
Y, and Z are defined as described in the figure.
ATmega328/P
AVR CPU Core
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 29
Figure 11-3. The X-, Y-, and Z-registers
15
XH
XL
0
X-register
7
0
7
0
R27
R26
15
YH
YL
0
Y-register
7
0
7
0
R29
R28
15
ZH
ZL
0
Z-register
7
0
7
0
R31
R30
In the different addressing modes, these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
Related Links
Instruction Set Summary
11.5 Stack Pointer
The stack is mainly used for storing temporary data, local variables, and return addresses after interrupts
and subroutine calls. The stack is implemented as growing from higher to lower memory locations. The
Stack Pointer register always points to the top of the stack.
The stack pointer points to the data SRAM stack area where the subroutine and interrupt stacks are
located. A stack PUSH command will decrease the stack pointer. The stack in the data SRAM must be
defined by the program before any subroutine calls are executed or interrupts are enabled. Initial stack
pointer value equals the last address of the internal SRAM and the stack pointer must be set to point
above start of the SRAM. See the table for stack pointer details.
Table 11-1. Stack Pointer Instructions
Instruction Stack Pointer Description
PUSH Decremented by 1 Data is pushed onto the stack
CALL
ICALL
RCALL
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
interrupt
POP Incremented by 1 Data is popped from the stack
RET
RETI
Incremented by 2 Return address is popped from the stack with return from subroutine or
return from interrupt
ATmega328/P
AVR CPU Core
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 30
The AVR stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH register will not be present.
ATmega328/P
AVR CPU Core
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 31
11.5.1 Stack Pointer Register Low and High byte
Name:  SPL and SPH
Offset:  0x5D
Reset:  0x4FF
Property:  When addressing I/O registers as data space the offset address is 0x3D
The SPL and SPH register pair represents the 16-bit value, SP. The low byte [7:0] (suffix L) is accessible
at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on
reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Bit 15 14 13 12 11 10 9 8
SP11 SP10 SP9 SP8
Access R R R R RW RW RW RW
Reset 0 0 0 0 0 1 0 0
Bit 7 6 5 4 3 2 1 0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Access RW RW RW RW RW RW RW RW
Reset 1 1 1 1 1 1 1 1
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – SP Stack Pointer Register
SPL and SPH are combined into SP.
Related Links
Accessing 16-bit Timer/Counter Registers
11.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is
driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal
clock division is used. The figure below shows the parallel instruction fetches and instruction executions
enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power unit.
ATmega328/P
AVR CPU Core
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 32
Figure 11-4. The Parallel Instruction Fetches and Instruction Executions
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALU
operation using two register operands is executed and the result is stored back to the destination register.
Figure 11-5. Single Cycle ALU Operation
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU
11.7 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset vector
each have a separate program vector in the program memory space. All interrupts are assigned
individual enable bits, which must be written logic one together with the global interrupt enable bit in the
Status register in order to enable the interrupt. Depending on the program counter value, interrupts may
be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security.
The lowest addresses in the program memory space are by default defined as the Reset and interrupt
vectors. They have determined priority levels: The lower the address the higher is the priority level.
RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The interrupt vectors
can be moved to the start of the boot Flash section by setting the IVSEL bit in the MCU Control Register
(MCUCR). The Reset vector can be moved to the start of the boot Flash section by programming the
BOOTRST Fuse.
When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
interrupt the current interrupt routine. The I-bit is automatically set when a return from interrupt instruction
– RETI – is executed.
There are basically two types of interrupts:
The first type is triggered by an event that sets the interrupt flag. For these interrupts, the program
counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and
ATmega328/P
AVR CPU Core
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 33
hardware clears the corresponding interrupt flag. Interrupt flags can be cleared by writing a logic one to
the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt
enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt
enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do
not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled,
the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main
program and execute one more instruction before any pending interrupt is served.
The Status register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No
interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI
instruction. The following example shows how this can be used to avoid interrupts during the timed
EEPROM write sequence.
Assembly Code Example(1)
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example(1)
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
1. Refer to About Code Examples.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before
any pending interrupts, as shown in this example.
Assembly Code Example(1)
sei ; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
C Code Example(1)
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
1. Refer to About Code Examples.
Related Links
Memory Programming
Boot Loader Support – Read-While-Write Self-Programming
ATmega328/P
AVR CPU Core
© 2018 Microchip Technology Inc. Datasheet Complete DS40001984A-page 34