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FEATURES
APPLICATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
CON1
CON0
EXTREF
AIN+
AIN−
AGND
AVDD
REFT
REFB
OVRNG
D11
D10
D9
CLK
AVDD
OE
D0
D1
D2
D3
D4
DVDD
DGND
D5
D6
D7
D8
DW OR PW PACKAGE
(TOP VIEW)
DESCRIPTION
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
3.3-V, 12-BIT, 30 MSPS, LOW-POWER ANALOG-TO-DIGITALCONVERTER WITH POWER DOWN
•12-Bit Resolution, 30 MSPSAnalog-to-Digital Converter•Input Configurations:
– Differential (0.5x)– Differential (1x)•3.3-V Supply Operation•Internal Voltage Reference•Out-of-Range Indicator•Power-Down Mode•IF Undersampling
•Set Top Box (STB)•Camcorders
•Digital Cameras•Copiers
•Communications
•Test Instruments
•IF and Baseband Digitization
The THS1230 is a CMOS, low-power, 12-bit, 30 MSPS analog-to-digital converter (ADC) that operates with a3.3-V supply. The THS1230 gives circuit developers complete flexibility. The analog input to the THS1230 isdifferential with a gain of 0.5 for Mode 2 and 1.0 for Mode 1. The THS1230 provides a wide selection of voltagereferences to match the user's design requirements. For more design flexibility, the internal reference can bebypassed to use an external reference to suit the dc accuracy and temperature drift requirements of theapplication. The out-of-range output is used to monitor any out-of-range condition in the THS1230's input range.
The speed, resolution, and single-supply operation of the THS1230 are suited for applications in set top box(STB), video, multimedia, high-speed acquisition, and communications. The speed and resolution ideally suitcharge-couple device (CCD) input systems such as digital copiers, digital cameras, and camcorders. The wideinput voltage range between V
REFB
and V
REFT
allows the THS1230 to be designed into multiple systems.
The THS1230C is characterized for operation from 0°C to 70°C. The THS1230I is characterized for operationfrom –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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FUNCTIONAL BLOCK DIAGRAM
12-Bit ADC D[11:0]
Sample
and Hold
CLK
DGNDAGND
OVRNG
CON0
Timing Circuitry
REFT REFB
Internal
Reference
Circuit
CON1
3-State
Output
Buffers
EXTREF
Configuration
Control
Circuit
DVDD
AIN+
AIN−
AVDD
OE
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions. Failure to observe proper handling and installationprocedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precisionintegrated circuits may be more susceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.
ORDERING INFORMATION
PRODUCT PACKAGE- PACKAGE SPECIFIED PACKAGE ORDERING TRANSPORT MEDIA,LEAD DESIGNATOR
(1)
TEMPERATURE MARKING NUMBER QUANTITYRANGE
THS1230 TSSOP-28 PW 0°C to 70°C TH1230 THS1230CPW Tube, 50THS1230 TSSOP-28 PW 0°C to 70°C TH1230 THS1230CPWR Tape and reel, 2000THS1230 TSSOP-28 PW -40°C to 85°C TJ1230 THS1230IPW Tube, 50THS1230 TSSOP-28 PW -40°C to 85°C TJ1230 THS1230IPWR Tape and reel, 2000THS1230 SOP-28 DW 0°C to 70°C TH1230 THS1230CDW Tube, 20THS1230 SOP-28 DW 0°C to 70°C TH1230 THS1230CDWR Tape and reel, 1000THS1230 SOP-28 DW -40°C to 85°C TJ1230 THS1230IDW Tube, 20THS1230 SOP-28 DW -40°C to 85°C TJ1230 THS1230IDWR Tape and reel, 1000
(1) For the most current specifictions and package information refer to our Web site at www.ti.com.
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TERMINAL FUNCTIONS
ABSOLUTE MAXIMUM RATINGS
(1)
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
TERMINAL
I/O DESCRIPTIONNAME NO.
AGND 1, 7 I Analog groundAV
DD
8, 27 I Analog supplyAIN+ 5 I Positive analog inputAIN- 6 I Negative analog inputCLK 28 I ADC conversion clockCON1 2 I Configuration input 1CON0 3 I Configuration input 0DGND 19 I Digital groundDV
DD
20 I Digital supplyD11 12 O ADC data bit 11D10 13 O ADC data bit 10D9 14 O ADC data bit 9D8 15 O ADC data bit 8D7 16 O ADC data bit 7D6 17 O ADC data bit 6D5 18 O ADC data bit 5D4 21 O ADC data bit 4D3 22 O ADC data bit 3D2 23 O ADC data bit 2D1 24 O ADC data bit 1D0 25 O ADC data bit 0EXTREF 4 I Reference select input (high = external, low = internal)OVRNG 11 O Out of range indicator (high = out of range)OE 26 I Output enable (high = disable, low = enable)REFT 9 I/O Upper ADC reference voltageREFB 10 I/O Lower ADC reference voltage
over operating free-air temperature range (unless otherwise noted)
UNIT
AV
DD
to AGND, DV
DD
to DGND –0.3 V to 4 VSupply voltage range
AGND to DGND –0.3 V to 0.3 VReference voltage input range, REFT, REFB to AGND –0.3 to AV
DD
+ 0.3 VAnalog input voltage range, AIN+, AIN- to AGND –0.3 to AV
DD
+ 0.3 VClock input voltage range, CLK to AGND –0.3 to AV
DD
+ 0.3 VDigital input voltage range, digital input to DGND –0.3 to DV
DD
+ 0.3 VDigital output voltage range, digital output to DGND –0.3 to DV
DD
+ 0.3 VOperating junction temperature range, T
J
–40°C to 150°CStorage temperature range, T
STG
– 65°C to 150°CLead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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RECOMMENDED OPERATING CONDITIONS
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
over operating free-air temperature range, T
A
(unless otherwise noted)
MIN NOM MAX UNIT
POWER SUPPLY
Supply voltage AV
DD
3.0 3.3 3.6 VDV
DD
ANALOG AND REFERENCE INPUTS
Reference input voltage V
REFT
f
CLK
= 5 MHz to 30 MHz 2.0 2.15 2.5 VV
REFB
f
CLK
= 5 MHz to 30 MHz 1.05 1.15 1.3Reference voltage differential, V
REFT
– V
REFB
f
CLK
= 5 MHz to 30 MHz 0.95 1.0 1.05 VAnalog input voltage differential, (AIN+) – (AIN–)
(1)
CON1 = 0, CON0 = 1 –1.0 1.0 VCON1 = 1, CON0 = 0 –2.0 2.0Analog input capacitance, C
i
10 pFClock input
(2)
0 AV
DD
V
DIGITAL OUTPUTS
Minimum digital output load resistance, R
L
100 kΩMaximum digital output load capacitance, C
i
0 10 15 pF
DIGITAL INPUTS
High-level input voltage, V
IH
2.4 DV
DD
VLow-level input voltage, V
IL
DGND 0.8 VClock frequency, f
CLK
(3)
5 30 MHzClock pulse duration, t
w(CLKL)
, t
w(CLKH)
f
CLK
= 30 MHz 15 16.7 18.3 nsOperating free-air temperature, T
A
TH1230 0 70 °CTJ1230 –40 85
(1) Based on V
REFT
– V
REFB
= 1.0 V, varies proportional to the V
REFT
– V
REFB
value. AIN+ and AIN– inputs must always be greater than 0 Vand less than AV
DD
.(2) Clock pin is referenced to AGND and powered by AV
DD
.(3) Clock frequency can be extended to this range without degradation of performance.
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ELECTRICAL CHARACTERISTICS
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
over recommended operating conditions (AV
DD
= DV
DD
= 3.3 V, f
s
= 30 MHz/50% duty cycle, MODE = 1, 1-V input span,internal reference, T
min
to T
max
) (unless otherwise noted)
DIGITAL INPUTS AND OUTPUTS (ALL SUPPLIES = 3.3 V)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
DIGITAL INPUTS
All other inputs 0.8 ×DV
DDV
IH
High level input voltage VCLK 0.8 ×AV
DD
All other inputs 0.2 ×DV
DDV
IL
Low level input voltage VCLK 0.2 ×AV
DD
I
IH
High level input current 1 µAI
IL
Low level input current –1 µAC
i
Input capacitance 5 pF
DIGITAL OUTPUTS
V
OH
High level output voltage I
load
= 50 µA DV
DD
–0.4
VV
OL
Low level output voltage I
load
= –50 µA 0.4High impedance output current ±1 µAt
r
/t
f
Rise/fall time C
L
= 10 pF 4.5 ns
ANALOG INPUTS
C
i
Switched input capacitance 6 pFt
d(ap)
Aperture delay time 2 nsAperture uncertainty (jitter) 2 psDC leakage current (input = ±FS) 10 µA
POWER SUPPLY (CLK = 30 MHz)
XV
DD
Supply voltage (all supplies) 3 3.3 3.6 VI
DD
Supply current active - total 48 66I
(analog)
Supply current active - analog 35 mAI
(digital)
Supply current active - digital 13I
I(standby)
Standby supply current CLK = 0 MHz 10 µA1 µF Bypass
(1)
770 µst
(PU)
Power-up time for references from standby
10 µF Bypass
(1)
6.2 mst
(PUconv)
Power-up time for valid ADC conversions See Note
(2)
720 nsSee Note
(3)
168 220P
D
Power dissipation mWSee Note
(4)
188P
D(STBY)
Standby power dissipation CLK = 0 MHz 36 µWPSRR Power supply rejection ratio ±0.1 %FS
(1) Time for reference to recover to 1% of its final voltage level.(2) Time for ADC conversions to be accurate to within 0.1% of fullscale, INT ckts.(3) Clock = 30 MHz, AIN+ and AIN– at Common Mode or 1.65 V DC.(4) Clock = 30 MHz, fin = 3.58 MHz at –1 dBFS.
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ELECTRICAL CHARACTERISTICS (CONTINUED)
1.5 V
BAND
GAP
REFT
REFB
CT
CB
CTB
THS1230
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
over recommended operating conditions (AV
DD
= DV
DD
= 3.3 V, f
s
= 30 MHz/50% duty cycle, MODE = 1, 1-V input span,internal reference, T
min
to T
max
) (unless otherwise noted)
REFT, REFB REFERENCE VOLTAGES (all supplies = 3.3 V)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
INTERNAL REFERENCE
(1)
V
REFT
Upper reference voltage 2.15V
REFB
Lower reference voltage 1.15 VV
REF
Differential reference voltage, V
REFT
– V
REFB
0.95 1 1.05Differential reference voltage, V
REFT
– V
REFB
accuracy –5% 5%
EXTERNAL REFERENCE
Externally applied V
REFT
reference voltage range 2 2.5Externally applied V
REFB
reference voltage range 1.05 1.3 VExternally applied (V
REFT
– V
REFB
) reference voltage range 0.75 1.05External mode V
REFT
to V
REFB
impedance 9 kΩ
INTERNAL OR EXTERNAL REFERENCE
C
T
V
REFT
decoupling capacitor value 0.1C
B
V
REFB
decoupling capacitor value 0.1 µFC
TB
Decoupling capacitor V
REFT
to V
REFB
10
(1) The internal reference voltage is not intended for use driving off chip.
Figure 1. Reference Generation
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ELECTRICAL CHARACTERISTICS (CONTINUED)
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
over recommended operating conditions (AV
DD
= DV
DD
= 3.3 V, f
s
= 30 MHz/50% duty cycle, MODE = 1, 1-V input span,internal reference, T
min
to T
max
) (unless otherwise noted)
TESTPARAMETER MIN TYP MAX UNITCONDITIONS
DC ACCURACY (LINEARITY)
Number of missing codes All modes 0 codesDNL Differential nonlinearity All modes ±0.4 ±1 LSBINL Integral nonlinearity All modes –2.5 ±1.2 2 LSBOffset error All modes 0.7 1.2 %FSRGain error All modes 1.1 3.5 %FSR
DYNAMIC PERFORMANCE
(1)
f
i
= 3.58 MHz 10.9ENOB Effective number of bits f
i
= 10 MHz 10.4 10.6 Bitsf
i
= 15 MHz 10.4f
i
= 3.58 MHz –76THD Total harmonic distortion f
i
= 10 MHz –74 –65 dBf
i
= 15 MHz –72.5f
i
= 3.58 MHz 68SNR Signal-to-noise ratio f
i
= 10 MHz 64.5 65.6 dBf
i
= 15 MHz 64.6f
i
= 3.58 MHz 67.4SINAD Signal-to-noise + distortion f
i
= 10 MHz 64 65 dBf
i
= 15 MHz 64.5f
i
= 3.58 MHz 78.1SFDR Spurious free dynamic range f
i
= 10 MHz 67 74 dBf
i
= 15 MHz 72Analog input bandwidth 180 MHzDifferential phase, DP 0.12 degreeG
(diff)
Differential gain 0.01%
TIMING (all supplies = 3.3 V)
f
CLK
Clock frequency
(2)
5 30 MHzClock duty cycle 45% 50% 55%t
d(O)
Output delay time 7 19 nst
d(PZ)
Delay time, output disable to Hi-Z output 3.2 nst
d(EN)
Delay time, output enable to output valid 5 19 nsLatency 5 cycles
(1) Input amplitudes for all single tone dynamic tests are at –1 dBFS, all supplies = 3.3 V.(2) The clock frequency may be extended to 5 MHz without degradation in specified performance.
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PARAMETER MEASUREMENT INFORMATION
TIMING DIAGRAM
Analog
CLK
D[9:0] S1 S2 S3
S1 S2 S3
td(O)
tPIPELINE
1 2 3 4 5 6 7 8 9 10
OE
D[9:0]
td(PZ)
td(EN)
Hi−Z Hi−Z
Data Data Data
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
Figure 2. Analog Input and Data Output Timing
Figure 3. Output Enable Timing
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TYPICAL CHARACTERISTICS
170
160
150
−40 −15 10 35 60 85
Power − mW
180
190
200
TA − Temperature − °C
186.8 187.2 187.4 188 189.2 190.2
fin = 3.58 MHz @ −1dBFS
AIN− = AIN+ = 1.65 V
AVDD = DVDD = 3.3 V,
fs = 30 MSPS
Mode 1
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
POWER SIGNAL-TO-NOISE RATIOvs vsTEMPERATURE TEMPERATURE
Figure 4. Figure 5.
SPURIOUS FREE DYNAMIC RANGE TOTAL HARMONIC DISTORTIONvs vsTEMPERATURE TEMPERATURE
Figure 6. Figure 7.
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0.4
0.2
0 500 1000 1500 2000 2500 3000
DNL − Differential Nonlinearity − LSB
0.6
0.8
ADC Code
1
3500 4000
−0.4
−0.6
−0.2
0
−0.8
−1
AVDD = DVDD = 3.3 V
fs = 30 MSPS
0.5
0
0 500 1000 1500 2000 2500 3000
INL − Integral Nonlinearity − LSB
1
1.5
ADC Code
2
3500 4000
−1.5
−2
−1
−0.5
AVDD = DVDD = 3.3 V
fs = 30 MSPS
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE AND DISTORTION EFFECTIVE NUMBER OF BITSvs vsTEMPERATURE TEMPERATURE
Figure 8. Figure 9.
DIFFERENTIAL NONLINEARITY
Figure 10.
INTEGRAL NONLINEARITY
Figure 11.
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−140
−120
−100
−80
−60
−40
−20
0
0
0.88
1.76
2.64
3.53
4.41
5.29
6.17
7.05
7.93
8.81
9.69
10.6
11.5
12.3
13.2
14.1
15
Power − dBFS
f − Frequency − MHz
AVDD = DVDD = 3.3 V,
fs = 30 MSPS,
fi = 3.58 MHz, −1 dBFS,
Mode 1 Differential
−140
−120
−100
−80
−60
−40
−20
0
0
0.88
1.76
2.64
3.53
4.41
5.29
6.17
7.05
7.93
8.81
9.69
10.6
11.5
12.3
13.2
14.1
15
AVDD = DVDD = 3.3 V,
fs = 30 MSPS,
fi = 3.58 MHz, −1 dBFS,
Mode 2 Differential
Power − dBFS
f − Frequency − MHz
PRINCIPLES OF OPERATION
Analog Input
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
FAST FOURIER TRANSFORM - MODE 1
Figure 12.
FAST FOURIER TRANSFORM - MODE 2
Figure 13.
The analog input AIN is sampled in the sample and hold unit, the output of which feeds the ADC CORE, wherethe process of analog to digital conversion is performed against ADC reference voltages, V
REFT
and V
REFB
.
Connecting the EXTREF pin to one of two voltages, DGND or DV
DD
selects one of the two configurations of ADCreference generation. The ADC reference voltages come from either the internal reference buffer or completelyexternal sources. Connect EXTREF to DGND for internal reference generation or to DV
DD
for external referencegeneration.
CON0 and CON1 as described below, select the input configuration mode or place the device in powerdown.The ADC core drives out through output buffers to the data pins D0 to D11. The output buffers can be disabledby the OE pin.
A single, sample-rate clock (30 MHz maximum) is required at pin CLK. The analog input signal is sampled on therising edge of CLK, and corresponding data is output after the fifth following rising edge.
The THS1230 can operate in differential Mode 1 or differential Mode 2, controlled by the configuration pinsCON0 and CON1 as shown in Table 1 . Mode 0 places the device in power-down state or standby for reducedpower consumption.
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AIN−
0
4095
2V
MODE 2, CON[1:0] = 10
OUTPUT CODE
AIN−
0
4095
1V
MODE 1, CON[1:0] = 01
OUTPUT
CODE
AIN+ AIN+
Signal Processing Chain (Sample and Hold, ADC)
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
Table 1. Input Modes of Operation
MODE CON1 CON0 MODE OF OPERATION
0 0 0 Device powered down1 0 1 Differential mode ×12 1 0 Differential mode ×0.53 1 1 Not used
Modes 1 and 2 are shown in Figure 14 .
Figure 14. Input Mode Configurations
The gain of the sample and hold changes with the CON1 and the CON0 inputs. Table 2 shows the gain of thesample and hold and the levels applied at the AIN+ and AIN– analog inputs for Mode 1 and Mode 2. Thecommon mode level for the two analog inputs is at AVDD/2.
Table 2. Input Mode Switching
(AIN+) – (AIN–) (AIN+) – (AIN–)MODE CON1 CON0 S/H GAINMIN MAX
1 0 1 –1 V 1 V ×12 1 0 –2 V 2 V ×0.5
Table 2 assumes that the delta in ADC reference voltages V
REFT
and V
REFB
is set to 1 V, i.e., V
REFT
– V
REFB
= 1V. Note that V
REFB
and V
REFT
can be set externally, which will scale the numbers given in this table.
The user-chosen operating configuration and reference voltages determine what input signal voltage range theTHS1230 can handle.
The following sections explain both the internal signal flow of the device and how the input signal span is relatedto the ADC reference voltages, as well as the ways in which the ADC reference voltages can be bufferedinternally or externally applied.
Figure 15 shows the signal flow through the sample and hold unit and the PGA to the ADC core.
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SAMPLE
AND
HOLD
AIN−
AIN+ +1
−1
VP+
VP−
REFT
REFB
ADC
CORE
Sample and Hold
Analog-to-Digital Converter
Analog Input
THS1230
RS
VS+ VS−
RS
RSW
RSW
CI
CI
VCM VCM _
+
_
+
RS1
2fCLK CIIn(256)–RSW
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
Figure 15. Analog Input Signal Flow
The differential sample and hold processes A
IN
with respect to the voltages applied to the REFT and REFB pins,to give a differential output (VP+) – (VP–) = VP given by:•VP = (AIN+) – ( AIN–)
No matter what operating configuration is chosen, VP is digitized against ADC reference voltages V
REFT
andV
REFB
. The V
REFT
and V
REFB
voltages set the analog input span limits FS+ and FS–, respectively. Any voltages atAIN greater than REFT or less than REFB causes ADC over-range, which is signaled by OVR going high whenthe conversion result is output.
A first-order approximation for the equivalent analog input circuit of the THS1230 is shown in Figure 16 . Theequivalent input capacitance C
I
is 5 pF typical. The input must charge/discharge this capacitance within thesample period of one half of a clock cycle. When a full-scale voltage step is applied, the input source providesthe charging current through the switch resistance R
SW
(200 Ω) of S1 and quickly settles. In this case the inputimpedance is low. Alternatively, when the source voltage equals the value previously stored on C
I
, the holdcapacitor requires no input current and the equivalent input impedance is very high.
Figure 16. Simplified Equivalent Input Circuit
To maintain the frequency performance outlined in the specifications, the total source impedance should belimited to the following equation with f
CLK
= 30 MHz, C
I
= 5 pF, R
SW
= 200 Ω:
So, for applications running at a lower f
CLK
, the total source resistance can increase proportionally.
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VIN+
VIN−
R1
R2
−
+
R1
R2
−
+
C1
C1
C2
C2
THS1230
AIN+
AIN−
REFT
REFB
AVDD
2
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
The analog input of the THS1230 is a differential input that can be configured in various ways depending on thesignal source and the required level of performance. A fully differential connection (see Figure 17 ) delivers thebest performance from the converter.
Figure 17. AC-Coupled Differential Input
The analog input can be dc-coupled (see Figure 18 ) as long as the inputs are within the analog input commonmode voltage range. For example (see Figure 18 ), V+ and V– are signals centered on GND with a peak-to-peakvoltage of 2 V, and the circuit in Figure 18 is used to interface it with the THS1230. Assume AV
DD
of theconverter is 3 V. Two problems have to be solved. The first is to shift common mode level (CML) from 0 V to 1.5V (AV
DD
/2). To do that, a V bias voltage and an adequate ratio of R1 and R2 have to be selected. For instance, ifV bias = AV
DD
= 3 V, then R1 = R2. The second is that the differential voltage has to be reduced from 4 V (2 x 2V) to 1 V, and for that an attenuation of 4 to1 is needed. The attenuation is determined by the relation:(R3||2R2)/((R3||2R2) + 2R1). One possible solution is R1 = R2 = R3 = 150 Ω. In this case, moreover, the inputimpedance (2R1 + (R3||2R2)) will be 400 Ω. The values can be changed to match any other input impedance. Acapacitor, C, connected from AIN+ to AIN– helps filter any high frequency noise on the inputs, also improvingperformance. Note that the chosen value of capacitor C must take into account the highest frequency componentof the analog input signal.
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VIN+
VIN−
R1
R1
R3
THS1230
AIN+
REFT
REFB
AIN−
R2
R2
VBIAS
VBIAS
VIN
AVDD
2THS1230
AIN+
AIN−
REFT
REFB
Digital Outputs
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
Figure 18. DC-Coupled Differential Input Circuit
A single-ended source may give better overall system performance when it is converted to a differential signalbefore driving the THS1230. The configuration in Figure 19 takes a VIN of 1 V and drives the 1:1 transformerratio so that value of AIN+ and AIN– converts to fullscale value at the ADC digital output. With VIN at –1 V thevalue at AIN+ and AIN– converts to 0 at the ADC digital outputs.
Figure 19. Transformer Coupled Single-Ended Input
The output of THS1230 is in unsigned binary code. The ADC input over-range indicator is output on pin OVRNG.Capacitive loading on the output should be kept as low as possible (a maximum loading of 10 pF isrecommended) to ensure best performance. Higher output loading causes higher dynamic output currents andcan therefore increase noise coupling into the part's analog front end. To drive higher loads the use of an outputbuffer is recommended.
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THS1230
DA11
DA0
SN74ALVCH16841
12
1D9
1D0
2D7
2D2
LE
OE
1Q9
1Q0
2Q9
2Q2
12
ASIC
or
DSP
2D1
2D0
2Q1
2Q0
FIFO
D11
D0
1Q15
1Q0 16
DSP
WRTCLK
HF flag INTR
D15
D12
THS1230
DA11
DA0 12
30 MHz
Clock
CLK
Layout, Decoupling and Grounding Rules
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
When clocking output data from THS1230, it is important to observe its timing relation to CLK. The pipeline ADCdelay is 5 clock cycles to which the maximum output propagation delay needs to be added.
Figure 20. Buffered Output Connection
Figure 21. FIFO Connection
Proper grounding and layout of the PCB on which THS1230 is populated is essential to achieve the statedperformance. It is advised to use separate analog and digital ground planes that are spliced underneath the IC.THS1230 has digital and analog pins on opposite sides of the package to make this easier. Because there is noconnection internally between analog and digital grounds, they have to be joined on the PCB. It is advised to dothis at one point in close proximity to THS1230.
Because of the high sampling rate and switched-capacitor architecture, THS1230 generates transients on thesupply and reference lines. Proper decoupling of these lines is therefore essential. Decoupling is recommendedas shown in the schematic of the THS1230 evaluation module in Figure 22 .
16
www.ti.com
AGND 1
CON1
2CON0
3
EXTREF
4
AIN+
5
AIN−
6
AGND 7
AVDD
8
REFT
9
REFB
10 OVRNG 11
D11 12
D10 13
D9 14
D8 15
D7 16
D6 17
D5 18
DGND 19
DVDD
20
D4 21
D3 22
D2 23
D1 24
D0 25
OE
26
CLKVDD
27
CLK
28
U1
THS1230PW
+3.3VA +3.3VD +3.3VA
ADCCLK
OEB
CON0
CON1
EXTREF
VINP
VINM
ADCCLK
OEB
CON0
CON1
EXTREF
VINM
D4
10
D5
9
D6
8
D7
7
D8
6
D9
5
D10
4
D11
3
D12
2
D13
1
CLK
28
MODE
25
DVDD
27 DGND 26
AGND 20
AVDD
24
EXTLO 16
REFIO 17
FSADJ 18
COMP1 19
COMP2 23
IOUT1 22
IOUT2 21
SLEEP
15
D3
11 D2
12 D1
13 D0
14
U3
THS5671AIPW
LNK3
LNK2
LNK4
LNK5
R2
47K R23
47K
R1
47K
R24
47K
+3.3VD +3.3VD
+3.3VD +3.3VD
OEB EXTREF
CON1 CON0 CON0
TP1 TP2
+
C28
10uF
C27
0.1uF
C25
0.1uF C26
0.1uF
VRT VRB
VRT VRB
C62
470pF C63
0.1uF C64
470pF C65
0.1uF C66
470pF C67
0.1uF
+3.3VD
_3.3VA
ADCOVRNG
ADCD00
ADCD01
ADCD02
ADCD03
ADCD04
ADCD05
ADCD06
ADCD07
ADCD08
ADCD09
ADCD10
ADCD11
ADCD [00:11]
+3.3VA+3.3VD
ADCDB00
ADCDB01
ADCDB02
ADCDB03
ADCDB04
ADCDB05
ADCDB06
ADCDB07
ADCDB08
ADCDB09
ADCDB10
ADCDB11
ADCDB[00:11]
DACCLK DACCLK
C6
0.1uF
C15
0.1uF
+3.3VA
IOUT1
IOUT2
R10
2K
C16
0.01uF
C5
0.1uF C19
10uF
C17
0.1uF
C18
0.1uF
+3.3VD
+3.3VA
CON1
OEB EXTREF
IOUT1
IOUT2
+
VINP
DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset and Gain Error
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
Figure 22. EVM Schematic
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2LSB beyond the last code transition. The deviation is measured from the center of each particular code to thetrue straight line between these two end-points.
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.Therefore, this measure indicates how uniform the transfer function step sizes are. The ideal step size is definedhere as the step size for the device under test, i.e. (last transition level - first transition level)/(2n –2). Using thisdefinition for DNL separates the effects of gain and offset error. A minimum DNL better than –1 LSB ensures nomissing codes.
Offset error (in LSBs) is defined as the average offset for all inputs, and gain error is defined as the maximumerror (in LSBs) caused by the angular deviation from the offset corrected straight line.
17
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Analog Input Bandwidth
Output Timing
Signal-to-Noise Ratio + Distortion (SINAD)
Effective Number of Bits (ENOB)
Total Harmonic Distortion (THD)
Spurious Free Dynamic Range (SFDR)
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
The analog input bandwidth is defined as the maximum frequency of a 1-dBFS input sine wave that can beapplied to the device for which an extra 3-dB attenuation is observed in the reconstructed output signal.
Output timing t
d(O)
is measured from the 50% level of the CLK input falling edge to the 10%/90% level of thedigital output. The digital output load is not higher than 10 pF.
Output hold time t
h(O)
is measured from the 50% level of the CLK input falling edge to the10%/90% level of thedigital output. The digital output load is not less than 2 pF.
Aperture delay t
d(A)
is measured from the 50% level of the CLK input to the actual sampling instant.
The OE signal is asynchronous.
OE timing t
d(PZ)
is measured from the V
IH(min)
level of OE to the high-impedance state of the output data. Thedigital output load is not higher than 10 pF.
OE timing t
d(EN)
is measured from the V
IL(max)
level of OE to the instant when the output data reaches V
OH(min)
orV
OL(max)
output levels. The digital output load is not higher than 10 pF.
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral componentsbelow the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed indecibels.
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,•N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effectivenumber of bits for a device for sine wave inputs at a given input frequency can be calculated directly from itsmeasured SINAD.
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured inputsignal and is expressed as a percentage or in decibels.
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
18
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS1230IDW ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS1230IDWG4 ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS1230IPW ACTIVE TSSOP PW 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS1230IPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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