ICs for Communications
DMA Integrated Serial Communication Controller
MISTRAL
PEB 20542 Version 1.1
PEF 20542 Version 1.1
Preliminary Data Sheet 08.99 DS 1
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PEB 20542, PEF 20542
Revision History: Current Version: 08.99
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Edition 08.99
Published by Infineon Technologies AG i. Gr.,
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PEB 20542
PEF 20542
Preliminary Data Sheet 3 08.99
Preface
The MISTRAL is a Protocol Controller for a wide range of data communication and
telecommunication applications. This document provides complete reference
information on hardware and software related issues as well as on general operation.
Organization of this Docum ent
T his Prelimina ry Data Sheet is divided into 9 chapters . It is organized as follows:
• Chapter 1, Introduc tion
Gives a general description of the produ ct, lists t he key featu res, and pres ents som e
typical application s.
• Chapter 2, Pin Descriptio n
Lists pi n l ocat io ns wi th associated sig nals , cate gorizes signal s ac cording to fun ction,
and describes si gnal s.
• Chapters 3 Functional Description
These chapters provide detailed descriptions of all MISTRAL internal function blocks.
• Chapter 4, Detailed Protocol Descriptions
Gives a detailed description of all protocols supported by the serial communication
controllers SCCs.
• Chapter 5, Detailed Register Description
Gives a detailed descr ipti on of all MISTRAL on chip registers.
• Chapter 6, Programming
Provides program ming hel p for MISTRAL initializati on proce dure and operatio n.
• Chapter 7, Electrical Characteristics
Gives a detailed descr iption of all electrical DC and AC characteristics and provides
timing diagrams and values for all interfaces.
• Chapter 8, Test Modes
Gives a detailed description of the JTAG boundary scan unit.
• Chapter 9, Package Outli ne
PEB 20542
PEF 20542
Table of Contents Page
Preliminary Data Sheet 4 08.99
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1.2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
1.3 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
1.3 .1 Syste m Integration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
1.3 .2 Serial Configuration Examp les . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1.4 Differences between MISTRAL and the ESCC Family . . . . . . . . . . . . . . 1-24
1.4.1 Enhancement s to the ESCC Serial Core . . . . . . . . . . . . . . . . . . . . . . . 1- 24
1.4 .2 Simplifications to the ESCC Serial Core . . . . . . . . . . . . . . . . . . . . . . . 1-24
2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.1 Pin Di agr am P-TQFP-144- 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.2 Pin D efi nitions and Funct i ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 26
3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
3.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
3.2 Serial Comm unication Con troller (SCC) . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3.2.1 Pr ot ocol Modes Overvi ew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 42
3.2 .2 SCC FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3.2 .2.1 SCC Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
3.2 .2.2 SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
3.2 .2.3 SCC FIFO Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
3.2 .3 Clocking System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
3.2 .3.1 Cloc k Mode 0 (0a/0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
3.2 .3.2 Cloc k Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
3.2 .3.3 Cloc k Mode 2 (2a/2b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
3.2 .3.4 Cloc k Mode 3 (3a/3b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
3.2 .3.5 Cloc k Mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
3.2 .3.6 Cloc k Mode 5a (T ime Slot Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55
3.2 .3.7 Cloc k Mode 5b (Octet Sync Mode) . . . . . . . . . . . . . . . . . . . . . . . . . 3-62
3.2 .3.8 Cloc k Mode 6 (6a/6b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
3.2 .3.9 Cloc k Mode 7 (7a/7b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-66
3.2.4 Baud Rate Genera tor (BRG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67
3.2 .5 Clock Recovery (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67
3.2 .6 SCC Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70
3.2 .7 SCC Serial Bus Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71
3.2 .8 Serial Bus Access Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71
3.2.9 Serial Bus Collisions and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71
3.2 .10 Serial Bus Acces s Priority Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72
3.2.11 Serial Bus Configuratio n Timing Modes . . . . . . . . . . . . . . . . . . . . . . . 3-73
3.2.12 Fu nct ions Of Signal RTS in HDLC Mod e . . . . . . . . . . . . . . . . . . . . . . . 3- 73
3.2 .13 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73
PEB 20542
PEF 20542
Table of Contents Page
Preliminary Data Sheet 5 08.99
3.2 .13.1 NRZ and NRZI Enco ding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74
3.2 .13.2 FM0 and FM1 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74
3.2 .13.3 Ma nches ter Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75
3.2.14 Modem Control Signals (RTS, CTS, CD) . . . . . . . . . . . . . . . . . . . . . . 3- 76
3.2.14.1 RTS/CTS H andshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76
3.2 .14.2 Carrier Detect (CD) Receiver Control . . . . . . . . . . . . . . . . . . . . . . . 3-77
3.2.15 Local Loop Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
3.3 Microproces sor Interfa ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
3.4 Inte rnal DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79
3.4 .1 Arbitration for Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79
3.4 .2 Performing DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80
3.4 .3 Bus Preemption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81
3.4 .4 Ending DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81
3.5 Interru pt Arc hitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81
3.6 Gener al Purpose Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83
3.6.1 GPP Funct i onal Desc ription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83
3.6 .2 GPP Interrupt Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83
4 Detailed Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84
4.1 HDLC/SDLC Protocol Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85
4.1.1 HD LC Subm odes Over vie w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85
4.1 .1.1 Automod e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85
4.1 .1.2 Address Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-86
4.1 .1.3 Address Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-86
4.1 .1.4 Address Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-86
4.1 .2 HDLC Receive Data Pro cessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87
4.1 .3 Receiv e Address Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89
4.1 .4 HDLC Transmit Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89
4.1 .5 Shared Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-91
4.1 .6 One Bit Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-91
4.1 .7 Preamble Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-91
4.1.8 CRC Ge neration and Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-91
4.1.9 Receive Lengt h Check Featu re . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-92
4.2 Point-to-Point Protocol (PPP) Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-93
4.2.1 Bit Synchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-93
4.2.2 Octet Synchro nous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-93
4.2.3 Asynchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 94
4.2.4 Data Transparency in PPP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94
4.3 Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96
4.4 Asyn chro nous (ASYNC) Protocol Mode . . . . . . . . . . . . . . . . . . . . . . . . . 4-96
4.4 .1 Character Fr aming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96
4.4 .2 Data Receptio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-97
4.4 .2.1 Asynchrono us Mod e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-97
PEB 20542
PEF 20542
Table of Contents Page
Preliminary Data Sheet 6 08.99
4.4.2.2 Isochronous M ode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-97
4.4.2.3 Storage of Receiv e Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 98
4.4 .3 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-98
4.4 .4 Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-99
4.4 .4.1 Brea k Detection/Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-99
4.4.4.2 In-band Flow Control by XON/XOFF Characters . . . . . . . . . . . . . . . 4- 99
4.4.4.3 Out-of-band Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-101
4.5 BISYNC Protoco l Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-103
4.5 .1 Character Fr aming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-103
4.5 .2 Data Receptio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-104
4.5 .3 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-105
4.5 .4 Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-106
4.5 .4.1 Prea mble Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-106
4.6 Pro cedur al Support (Layer-2 Functions) . . . . . . . . . . . . . . . . . . . . . . . . 4-106
4.6.1 Full-Dup lex LAPB/LAPD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 4-106
4.6 .2 Half-Duplex SDLC-NRM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 4-112
4.6 .3 Signaling System #7 (SS7) Operatio n . . . . . . . . . . . . . . . . . . . . . . . . 4-114
5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-117
5.1 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-117
5.2 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-123
5.2.1 Gl obal Regis ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-123
5.2.2 Channel Specific SCC Regis ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-139
5.2.3 Channel Specific DMA Reg isters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 235
5.2.4 M iscel l aneous Regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-251
6 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-254
6.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-254
6.2 Inte rrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6- 254
6.2 .1 Data Transmission (Interrupt Driven) . . . . . . . . . . . . . . . . . . . . . . . . . 6-254
6.2 .2 Data Receptio n (Interrupt Driven) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-256
6.3 Inte rnal DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-259
6.3 .1 Data Transmission (DMA Controlled) . . . . . . . . . . . . . . . . . . . . . . . . 6-259
6.3 .2 Data Receptio n (DMA Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-262
6.3.3 Buffer Switched Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-266
7 Electrical Characteristics (Preliminary) . . . . . . . . . . . . . . . . . . . . . . . 7-268
7.1 Abso lute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-268
7.2 Oper ating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-268
7.3 Thermal Package Cha racteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-269
7.4 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-270
7.5 AC Cha racteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-271
7.6 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-271
7.7 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-272
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Preliminary Data Sheet 7 08.99
7.7 .1 Micro processor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-272
7.7 .1.1 Microprocessor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . 7-272
7.7 .1.2 Sie mens/Intel Bus Interface Timing (Slave Access) . . . . . . . . . . . 7-273
7.7 .1.3 Motorola Bus Interface Timing (Slave Access) . . . . . . . . . . . . . . . 7-275
7.7.1.4 Siemens/Intel Bus Interface Timing (Master Access) . . . . . . . . . . 7-277
7.7.1.5 Motorola Bus Interface Timing (M aster Access) . . . . . . . . . . . . . . 7-279
7.7 .1.6 Bus Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-281
7.7 .2 PCM Se rial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-282
7.7.2.1 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7- 282
7.7 .2.2 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-283
7.7 .2.3 Tran smit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-285
7.7.2.4 Clock Mode 1 Str obe Ti ming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-287
7.7.2.5 Clock Mode 5 Frame Synchronisati on Timin g . . . . . . . . . . . . . . . . 7-288
7.7 .2.6 Cloc k Mode 4 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . 7-289
7.7 .2.7 Cloc k Mode 4 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . 7-290
7.7 .3 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-291
7.7.4 J TAG-Bounda ry Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-292
8 Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-293
8.1 JTAG Boundar y Scan Inter face . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-293
9 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-298
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Preliminary Data Sheet 8 08.99
Fig ure 1-1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Fig ure 1-2 Syste m Integration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Fig ure 1-3 Point-to-Poin t Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Fig ure 1-4 Point-to-Multipoint Bus Configur ation . . . . . . . . . . . . . . . . . . . . . . . . 1-23
Fig ure 1-5 Multimaster Bus Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
Figure 2-1 Pin Configuration P-TQFP-144-10 Packag e . . . . . . . . . . . . . . . . . . . 2- 25
Fig ure 3-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
Fig ure 3-2 SCC Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
Fig ure 3-3 SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
Fig ure 3-4 XFIFO/RFIFO W ord Access (Intel Mode) . . . . . . . . . . . . . . . . . . . . . 3-45
Fig ure 3-5 XFIFO/RFIFO W ord Access (Motorola Mo de). . . . . . . . . . . . . . . . . . 3-45
Fig ure 3-6 Clock Supply Overvie w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
Figure 3-7 Clock Mode 0a/0b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 50
Figure 3-8 Clock Mode 1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 51
Figure 3-9 Clock Mode 2a/2b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 52
Figure 3-10 Clock Mode 3a/3b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
Figure 3-11 Clock Mode 4 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 54
Figure 3-12 Selec ting one time-slot of programm able delay and width . . . . . . . . 3- 56
Figure 3-13 Selecting one or more time-slots of 8-bit wi dth . . . . . . . . . . . . . . . . . 3-58
Figure 3-14 Clock Mode 5a Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
Figure 3-15 Clock Mode 5a "Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60
Figure 3-16 Clock Mode 5a "Non Continuous Mo de" . . . . . . . . . . . . . . . . . . . . . . 3-61
Figure 3-17 Selecting one or more octet wide time-slots . . . . . . . . . . . . . . . . . . . 3-63
Figure 3-18 Clock Mode 5b Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64
Figure 3-19 Clock Mode 6a/6b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
Figure 3-20 Clock Mode 7a/7b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-66
Figure 3-21 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shi ft Enabled) . . 3- 69
Figure 3-22 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shi ft Disabled) . . 3- 69
Figure 3-23 DPLL Algorithm for FM0, FM1 and Manchester Encoding . . . . . . . . 3-70
Fig ure 3-24 Request-to-Sen d in Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73
Figure 3-25 NRZ and N RZ I Data Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 74
Figure 3-26 FM0 and FM1 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 75
Fig ure 3-27 Manc hester Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75
Fig ure 3-28 RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
Fig ure 3-29 SCC Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
Figure 3-30 MISTR AL reques ts and gets the bus. . . . . . . . . . . . . . . . . . . . . . . . . 3-80
Fig ure 3-31 Un-interru pted Series of 32 DMA Bus Cycle s . . . . . . . . . . . . . . . . . . 3-80
Figure 3-32 Bus Preemption and Re-gain of Bus Control. . . . . . . . . . . . . . . . . . . 3-81
Figure 3-33 MISTR AL reques ts and gets the bus. . . . . . . . . . . . . . . . . . . . . . . . . 3-81
Fig ure 3-34 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82
Fig ure 4-1 HDLC Receive Data Processing in 16 bit Automode. . . . . . . . . . . . . 4-87
Fig ure 4-2 HDLC Receive Data Processing in 8 bit Automode. . . . . . . . . . . . . . 4-87
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Preliminary Data Sheet 9 08.99
Figure 4-3 HDLC Recei ve Data Processi ng i n Address Mode 2 (16 bit). . . . . . . 4-87
Figure 4-4 HDLC Recei ve Data Processi ng i n Address Mode 2 (8 bit). . . . . . . . 4- 88
Figure 4-5 HDLC Recei ve Data Processi ng i n Address Mode 1. . . . . . . . . . . . . 4-88
Figure 4-6 HDLC Recei ve Data Processi ng i n Address Mode 0. . . . . . . . . . . . . 4-88
Fig ure 4-7 SCC Transmit Data Flow (HDLC Modes) . . . . . . . . . . . . . . . . . . . . . 4-90
Figure 4-8 PPP Mapping/Unmap ping Example. . . . . . . . . . . . . . . . . . . . . . . . . . 4- 95
Figure 4-9 As ynchronous Character Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-97
Figure 4-10 Out-of-Band DT E-DTE Bi-directional Flow Contro l . . . . . . . . . . . . . 4-102
Figure 4-11 Out-of-Band DT E-DCE Bi-directional Flow Control . . . . . . . . . . . . . 4- 103
Fig ure 4-12 BISYNC Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-104
Fig ure 4-13 Processing o f Received Frames in Auto Mode . . . . . . . . . . . . . . . . 4-108
Figure 4-14 Timer Procedure/Poll Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-110
Figure 4-15 Transm issi on/ Recept io n of I-Frames and Flow Contro l. . . . . . . . . . 4-111
Figure 4-16 Flow Control: Reception of S-Comm ands and Protocol Errors . . . . 4-111
Figure 4-17 No Dat a to Send: Data Reception /Transm issi on . . . . . . . . . . . . . . . 4-114
Figure 4-18 Data Tran smiss ion (without error), Data Transmission (with error) . 4-114
Figure 6-1 Interrupt Driven Data Trans mission (Fl ow Diagr am ) . . . . . . . . . . . . 6-256
Fig ure 6-2 Interrupt Driven Data Re ception (Flow Dia gram). . . . . . . . . . . . . . . 6-258
Fig ure 6-3 DMA Transmit (Single Buffer per Packet) . . . . . . . . . . . . . . . . . . . . 6-260
Figure 6-4 Fragm ent ed DMA Tran smiss ion (Mult iple Buffers per Packet) . . . . 6-261
Figure 6-5 DMA Control led Data Transm issi on (Flow Diagram). . . . . . . . . . . . 6-262
Fig ure 6-6 DMA Receive (Single Buffer per Packet). . . . . . . . . . . . . . . . . . . . . 6-263
Fig ure 6-7 Fragm ented Reception per DMA (Exa mple) . . . . . . . . . . . . . . . . . . 6-264
Figure 6-8 Fragm ent ed Recept io n Sequence (Ex amp le) . . . . . . . . . . . . . . . . . 6-265
Figure 6-9 DMA Control led Data Rec eption (Flow D iagram ) . . . . . . . . . . . . . . 6- 266
Fig ure 7-1 Input/Output Waveform for AC Tes ts. . . . . . . . . . . . . . . . . . . . . . . . 7-271
Fig ure 7-2 Micro processor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . . 7-272
Figure 7-3 Siem ens/I ntel R ead Cycle Timing (Slave Access). . . . . . . . . . . . . . 7-273
Fig ure 7-4 Siemens/Intel Write Cycle Timing (Slave Access). . . . . . . . . . . . . . 7-273
Figure 7-5 Motoro la Read C ycle Timi ng ( S lave Access). . . . . . . . . . . . . . . . . . 7-275
Fig ure 7-6 Motoro la Write Cycle Timing (Slave Access). . . . . . . . . . . . . . . . . . 7-275
Figure 7-7 Siem ens/I ntel R ead Cycle Timing (Master Access). . . . . . . . . . . . . 7-277
Fig ure 7-8 Siemens/Intel Write Cycle Timing (Master Access). . . . . . . . . . . . . 7-277
Figure 7-9 Motoro la Read C ycle Timi ng (Maste r Access ). . . . . . . . . . . . . . . . . 7-279
Fig ure 7-10 Motorola Write Cycle Timing (Master Access). . . . . . . . . . . . . . . . . 7-279
Fig ure 7-11 Bus Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-281
Figure 7-12 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-282
Fig ure 7-13 Receive Cyc le Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-283
Fig ure 7-14 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-285
Figure 7-15 Clock Mode 1 Strobe Timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-287
Figure 7-16 Clock Mode 5 Frame Synchroni sation Timin g . . . . . . . . . . . . . . . . . 7-288
Figure 7-17 Clock Mode 4 Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-289
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Figure 7-18 Clock Mode 4 Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-290
Fig ure 7-19 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-291
Figure 7-20 JTAG-Bound ary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-292
Figure 8-1 Block Diagra m of Test Access Port and Boundary Scan Unit . . . . . 8-293
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Prelimi nary Dat a Sheet 11 08.99
Table 2-1 Micro processor Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Table 2-2 Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
Table 2-3 Serial Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
Table 2-4 General Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
Table 2-5 Test Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
Table 2-6 Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
Table 3-1 Overview of Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 46
Table 3-2 Clock Modes of the SCCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
Table 3-3 BRRL/ BR R H Regist er and Bit-Fields. . . . . . . . . . . . . . . . . . . . . . . . 3-67
Table 3-4 Data Bus Access 16-bit Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
Table 3-5 Data Bus Access 16-bit Motorola Mode. . . . . . . . . . . . . . . . . . . . . . 3-79
Table 4-1 Prot ocol Mode Over vi ew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84
Table 4-2 Addres s Comparison Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85
Table 4-3 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-112
Table 5-1 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-117
Table 6-1 Status Information after RME interupt . . . . . . . . . . . . . . . . . . . . . . 6-257
Table 6-2 DMA Terminolo gy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-259
Table 7-1 Thermal Package Characteristics P-TQFP-144-10 . . . . . . . . . . . . 7-269
Table 7-2 Capacitances
TA = 25 ×C; VDD3 = 3.3 V ± 0.3 V, VSS = 0 V . . . . . . . . . . . . . . . 7-271
Table 7-3 Micro processor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . 7- 272
Table 7-4 Siemens/Intel Bus Interface Timing (Slave Acc ess) . . . . . . . . . . . 7-274
Table 7-5 Motoro la Bus Interfa ce Timing (Slave Access) . . . . . . . . . . . . . . . 7-276
Table 7-6 Siemens/Intel Bus Interface Timing (M aster Access) . . . . . . . . . . 7-278
Table 7-7 Motorola Bus Interface Timing (Master Access) . . . . . . . . . . . . . . 7-280
Table 7-8 Bus Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-281
Table 7-9 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-282
Table 7-10 Receiv e Cyc le Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-284
Table 7-11 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-286
Table 7-12 Clock Mode 1 Str obe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7- 287
Table 7-13 Clock Mode 5 Fram e Synchr oni sat ion Timing . . . . . . . . . . . . . . . . 7-288
Table 7-14 Clock Mode 4 Receive Timin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-289
Table 7-15 Clock Mode 4 Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-290
Table 7-16 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-291
Table 7-17 JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-292
Table 8-1 Boundary Scan Sequence of MISTRAL. . . . . . . . . . . . . . . . . . . . . 8-294
Table 8-2 Bo undar y Scan Test Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-297
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Prelimi nary Dat a Sheet 12 08.99
Register 5 -1 GCMDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-123
Register 5 -2 GMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-124
Register 5 -3 DBSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-127
Register 5 -4 GSTAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-128
Register 5 -5 GPDIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-130
Register 5 -6 GPDAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-131
Register 5 -7 GPIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-132
Register 5 -8 GPIS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-133
Register 5 -9 DCMDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-134
Register 5 -10 DMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-136
Register 5 -11 DISR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-137
Register 5 -12 DIMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-138
Register 5 -13 FIFOL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-139
Register 5 -14 FIFOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-139
Register 5 -15 STARL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-141
Register 5 -16 STARH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-141
Register 5 -17 CMDRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-146
Register 5 -18 CMDRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 146
Register 5 -19 CCR0L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-151
Register 5 -20 CCR0H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-151
Register 5 -21 CCR1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-155
Register 5 -22 CCR1H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-155
Register 5 -23 CCR2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-160
Register 5 -24 CCR2H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-160
Register 5 -25 CCR3L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-167
Register 5 -26 CCR3H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-167
Register 5 -27 PREAMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-175
Register 5 -28 TOLEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-176
Register 5 -29 ACCM0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-177
Register 5 -30 ACCM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-177
Register 5 -31 ACCM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-178
Register 5 -32 ACCM3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-178
Register 5 -33 UDAC0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-180
Register 5 -34 UDAC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-180
Register 5 -35 UDAC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-181
Register 5 -36 UDAC3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-181
Register 5 -37 TTSA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-183
Register 5 -38 TTSA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-183
Register 5 -39 TTSA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-184
Register 5 -40 TTSA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-184
Register 5 -41 RTSA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-186
Register 5 -42 RTSA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-186
PEB 20542
PEF 20542
List of Registers Page
Prelimi nary Dat a Sheet 13 08.99
Register 5 -43 RTSA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-187
Register 5 -44 RTSA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-187
Register 5 -45 PCMTX0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-189
Register 5 -46 PCMTX1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-189
Register 5 -47 PCMTX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-190
Register 5 -48 PCMTX3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-190
Register 5 -49 PCMRX0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-192
Register 5 -50 PCMRX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-192
Register 5 -51 PCMRX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-193
Register 5 -52 PCMRX3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-193
Register 5 -53 BRRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-195
Register 5 -54 BRRH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-195
Register 5 -55 TIMR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-197
Register 5 -56 TIMR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-197
Register 5 -57 TIMR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-198
Register 5 -58 TIMR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-198
Register 5 -59 XAD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-201
Register 5 -60 XAD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-201
Register 5 -61 RAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-203
Register 5 -62 RAH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-203
Register 5 -63 RAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-204
Register 5 -64 RAH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-204
Register 5 -65 AMRAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-206
Register 5 -66 AMRAH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-206
Register 5 -67 AMRAL2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-207
Register 5 -68 AMRAH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-207
Register 5 -69 RLCRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-209
Register 5 -70 RLCRH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-209
Register 5 -71 XON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-211
Register 5 -72 XOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-211
Register 5 -73 MXON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-213
Register 5 -74 MXOFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 213
Register 5 -75 TCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-215
Register 5 -76 TICR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-216
Register 5 -77 ISR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-218
Register 5 -78 ISR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-218
Register 5 -79 ISR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-219
Register 5 -80 IMR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-226
Register 5 -81 IMR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-226
Register 5 -82 IMR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-227
Register 5 -83 RSTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-229
Register 5 -84 SYNCL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-233
PEB 20542
PEF 20542
List of Registers Page
Prelimi nary Dat a Sheet 14 08.99
Register 5 -85 SYNCH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 233
Register 5 -86 TBADDR1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 235
Register 5 -87 TBADDR1M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-235
Register 5 -88 TBADDR1H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-236
Register 5 -89 TBADDR2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 237
Register 5 -90 TBADDR2M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-237
Register 5 -91 TBADDR2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-238
Register 5 -92 XBC1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-239
Register 5 -93 XBC1H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-239
Register 5 -94 XBC2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-241
Register 5 -95 XBC2H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-241
Register 5 -96 RBADDR1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-243
Register 5 -97 RBADDR1M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-243
Register 5 -98 RBADDR1H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-244
Register 5 -99 RBADDR2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-245
Register 5 -100 RBADDR2M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-245
Register 5 -101 RBADDR2H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-246
Register 5 -102 RMBSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-247
Register 5 -103 RMBSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-247
Register 5 -104 RBCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-249
Register 5 -105 RBCH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-249
Register 5 -106 VER0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-251
Register 5 -107 VER1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-251
Register 5 -108 VER2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-252
Register 5 -109 VER3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-252
PEB 20542
PEF 20542
Introduction
Preliminary Data Sheet 1-15 08.99
1 Introduction
The MISTRAL is a DMA Integrated Serial Communication Controller with two
independent serial channels1). The serial channels are derived from updated protocol
logic of the ESCC and DSCC4 device family providing a large set of protocol support and
variety in serial interface configuration. This allows easy integration to different
envi ronment s and appl i cations .
A generic 8- or 16-bit multiplexed/demultiplexed master/slave interface provides fast
device access with low bus utilization and easy software handshaking. The internal DMA
controller is optimized for a minimum CPU intervention. Different control mechanisms
allow easy software development well adapted to the needs of special applications (e.g.
frame/packet oriented and continuous transmission/reception).
Large on-chip FIFOs of 64 byte capacity per port and direction in combination with
enhanced threshold control mechanisms allow decoupling of traffic requirements on host
bus and serial interfaces with little exception probabilities such as data underuns or
overflows.
Each of the two Serial Communication Controllers (SCC) contains an independent Baud
Rate Generator, DPLL and programmable protocol processing (HDLC, PPP, ASYNC
and BISYNC). Data rates of up to 2 Mbit/s (DPLL assisted modes) and 16 Mbit/s (HDLC,
PPP, bit transparen t) are sup ported. The channels can also handle a larg e set of layer-
2 protocol functions (LAPD, SS7) reducing bus and host CPU load. Two channel specific
time rs are provided to sup port protocol functions.
1) The serial channels are also called ’ports ’ or ’cor es’ depending on the context.
DMA Integrated Serial Communication Controller
MISTRAL PEB 20542
PEF 20542
Preliminar
y
Data Sheet 1-16 08.99
Version 1.1 CMOS
Type Package
PEB 20542, PEF 20542 P-TQFP-144-10
1.1 Features
Serial communication controllers (SCCs)
• Two independent channels
• Full duplex data rates on each channel of up to
16 Mbit/s sync - 2 Mbit/s with DPLL
• 64 Bytes deep receive FIFO per SCC
• 64 Bytes deep transmit FIFO per SCC
Serial Interface
• On-c hip clock generat ion or ext erna l clock sour ces
• On-chip DPLLs for clock recovery
• Baud rate gene rator
• Clock gat ing signals
• Clock gappi ng capa bili ty
• Programm abl e t ime- slot capability for connection t o
TDM interfaces (e.g. T1, E1)
• NRZ, NRZ I, FM and Manchester data encod ing
• Optional data flow control using modem control lines (RTS, CTS, CD)
• Support of bus configuration by collision detection and resolution
Bit Processor Functions
•HDLC/SDLC Protocol Modes
– Automatic flag detection and transmission
– Shared opening and closing flag
– Generation of interframe-time fill ’1’s or flags
– Detect ion of receiv e line status
– Zero bit insertion and deletion
•
P-TQFP-144-10
PEB 20542
PEF 20542
Introduction
Preliminary Data Sheet 1-17 08.99
– CRC generation and checking (CRC-CCITT or CRC-32)
– Transpa rent CRC option per channel and/or per fram e
– Progra mmabl e Preambl e (8 bit) with selectabl e repetition rate
– Error detection (abort, long frame, CRC error, short frames)
•Bit Synchronous PPP Mode
– Bit oriented trans mission of HDLC frame (flag, data, CRC, flag)
– Zero bit insertio n/deleti on
– 15 consecut i ve ’1’ bits abort sequence
•Octet Synchronous PPP Mo d e
– Octe t o riented tr a nsm is sion of HDLC fram e (f la g , d ata , CRC, flag)
– Progra mmabl e char act er map of 32 hard-wired char act ers (00H-1FH)
– Four programmable characters for additional mapping
– Insertion/deletion of control-es cape char act er (7DH) for mapped char acters
•Asynchrono us PPP Mode
– Char acter oriented trans mission of HDLC frame (flag, data, CRC, flag)
– Start/stop bit framing of single charac ter
– Progra mmabl e char act er map of 32 hard-wired char act ers (00H-1FH)
– Four programmable characters for additional mapping
– Insertion/deletion of control-es cape char act er (7DH) for mapped char acters
•Asynchrono us (ASYNC) Protocol Mode
– Selectabl e char act er length (5 to 8 bits)
– Eve n, odd, forced or no parity generation/ chec kin g
– 1 or 2 stop bits
– Break det ection /gen eration
– In- band flow control by XON/XOFF
– Immediate characte r insertion
– Term ination char act er detect ion for end of block identification
– Time out detection
– Error detection (parity error, framing error)
•BISYNC Protocol Mode
– Programmable 6/8 bit SYN pattern (MONOSYNC)
– Programmable 12/16 bit SYN pattern (BISYNC)
– Selectabl e char act er length (5 to 8 bits)
– Eve n, odd, forced or no parity generation/ chec kin g
– Generat ion of interframe-time fill ’1’s or SYN characters
– CRC generation (CRC-16 or CRC-CCITT)
– Transpa rent CRC option per channel and/or per fram e
– Progra mmabl e Preambl e (8 bit) with selectabl e repetition rate
– Term ination char act er detect ion for end of block identificat ion
– Error detection (parity error, framing error)
•Extended Transpar ent Mode
– Fully bit transparent (no framing, no bit manipulation)
– Octet-aligned transmission and reception
PEB 20542
PEF 20542
Introduction
Preliminary Data Sheet 1-18 08.99
• Protoc ol and Mode Independent
– Data bi t inversion
– Data over flow and under run detect io n
–Timer
Protocol Support
• Address R ecognition Modes
– No address recognition (Address Mode 0)
– 8-bit (high byte) address recogniti on (Addr ess Mo de 1)
– 8-bit (low byte) or 16-bit (high and low byte) address recognition ( Addr ess Mode 2)
• HDLC Automode
– 8-bit or 16-bit address generatio n/recognition
– Suppor t of LAPB/LAPD
– Automatic handling of S- and I-frames
– Automatic processing of control byte(s)
– Modu lo-8 or mo dulo-128 operatio n
– Progr ammabl e tim e-ou t and retry conditions
– SDLC N ormal Response Mode (NRM ) operation for slave
• Signalin g System #7 (SS7) support
– Detecti on of FISUs, MSUs and LSSUs
– Unchanged Fill-In Signaling Units (FISUs) optionally not forwarded
– Automatic generation of FISUs in transmit direction (incl. sequence number)
– Cou nting of errored si gnaling units
Integrated DMA Controller
• 4 independe nt DMA cha nnels
• Optimized fo r min imum CPU int e rvention
• Efficient block-orien ted data transf er
• Bus preem ption
• Fragmented transmission/reception of data packets from/into multiple buffers
• Switched-Buffer mode for seamless update of buffer base address and size
• 24-bit adressabl e me mory rang e
• Optio nal D T AC K/READY controlled cycles
Micr oprocess or Interface
• 8/16-bit bus inter face
• Multiplexed and De-multipl exed addr ess/dat a bus
• Intel/Motorola style
• Asyn chro nous in ter fa ce
• Maskable interrupts for each channel
PEB 20542
PEF 20542
Introduction
Preliminary Data Sheet 1-19 08.99
General Purpose Port ( GPP) Pins
General
• 3.3V power supply with 5V tolerant inputs
• Low power cons ump tion
• Power safe features
• P-TQFP-144-10 Package (Thermal Resistance: RJA = 39K/W)
PEB 20542
PEF 20542
Introduction
Preliminary Data Sheet 1-20 08.99
1.2 Logic Symbol
•
Figure 1-1 Logic Symbol
A(23:1)
VSS
VDD3
TEST
TCK
TMS
TDI
TDO
TRST
Microprocessor
Interface
JTAG Test
Interface
TxD
A
RxD
A
RTS
A
/TxCLKO
A
/OSR
A
CTS
A
/CxD
A
/TCG
A
CD
A
/FSC
A
/RCG
A
/OST
A
TxCLK
A
RxCLK
A
Serial
Channel A
MISTRAL
PEB 2054 2
PEF 2054 2
XTAL1
XTAL2
TxD
B
RxD
B
RTS
B
/TxCLKO
B
/OSR
B
CTS
B
/CxD
B
/TCG
B
CD
B
/FSC
B
/RCG
B
/OST
B
TxCLK
B
RxCLK
B
Serial
Channel B
D(15:0)
ALE
A0/BLE
DS/LDS
RD
WR
INT/INT
CLK
RESET
CS
READY
BREQ
BGACK
BGNT
GP0
GP1
GP2
Bus
Arbitration
Intel
Mode
General
Purp ose Pin s
BHE
W/R
ADS
A0/UDS
R/W
DTACK
AS
A(23:1)
D(15:0)
Motorola
Mode
PEB 20542
PEF 20542
Introduction
Preliminary Data Sheet 1-21 08.99
1.3 Typical Applications
MISTRAL devices can be used in LAN-WAN inter-networking applications such as
Rou ters, Switches and Tr unk card s and support the common V.35, ISDN BRI (S/T) and
RFC1662 standards. Its new features provide powerful hardware and software
interfaces to develop high performanc e syst ems .
1.3.1 System Integration Example
Figure 1-2 System Integration
MISTRAL
PEB 20542
PEF 20542
. . .
. . .
. . .
. . .
Transceiver,
Framer
Syste m Bus
CPU
RAM
Bank
Bus
Arbiter
PEB 20542
PEF 20542
Introduction
Preliminary Data Sheet 1-22 08.99
1.3.2 Serial Configuration Examples
MISTRAL supports a variety of serial configurations at Layer-1 and Layer-2 level. The
outstanding variety of clock modes supporting a large number of combinations of
external and internal clock sourc es allows easy inte gratio n in application envir onm ents .
Figure 1-3 Point -to-Point Configurat ion
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
TxDRxD RxD TxD
serial transmission
optional modem control signals
Layer-2 LAPD/B or SS7
Protocol Support
MISTRAL
PEB 20542
PEF 20542
MISTRAL
PEB 20542
PEF 20542
PEB 20542
PEF 20542
Introduction
Preliminary Data Sheet 1-23 08.99
Figure 1-4 Point-to-Multipoint Bus Conf iguration
F igure 1-5 Multimaster Bus Co nfiguration
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
TxDRxD RxD TxD
. . .
. . .
. . .
. . .
RxD TxD
...
. . .
. . .
. . .
. . .
TxD
CxDCxDCxD
RxD
Master
Slave nSlave 2Slave 1
Layer-1 collision detecti on
or
Layer-2 SD LC-NRM operation
MISTRAL
PEB 20542
PEF 20542
MISTRAL
PEB 20542
PEF 20542
MISTRAL
PEB 20542
PEF 20542
MISTRAL
PEB 20542
PEF 20542
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
TxDRxD RxD TxD
. . .
. . .
. . .
. . .
RxD TxD
...
CxDCxDCxD
Master nMaster 2Master 1
Layer-1 collision detecti on
MISTRAL
PEB 20542
PEF 20542
MISTRAL
PEB 20542
PEF 20542
MISTRAL
PEB 20542
PEF 20542
PEB 20542
PEF 20542
Introduction
Preliminary Data Sheet 1-24 08.99
1.4 Differences between MISTRAL and the ESCC Family
This chapter is useful for all being familiar with the ESCC family.
1.4.1 Enhancements to the ESCC Serial Core
The MISTRAL SCC cores contain t he core l ogic of the ESCC as the heart of the device.
Some enhancem ents are incor porated in the SCCs. These are:
• Integrated fou r-channel DMA controll er
• Octet-, Bit Synchronous and Asynchronous PPP protocol support as in RFC-1662
• Signalin g System #7 (SS7) support
• 4-kByte packet length byte counter
• Enhan ced addr ess filterin g (16-bit mas kable)
• Enhan ced time slot assi gner
• Suppo rt of high data rates (16 M bit/s)
1.4.2 Simplifications to the ESCC Serial Core
The following features of the ESCC core have been removed:
• Extended transparent mode 0
(this mode pr ovi ded oct et buf fered dat a rec ept ion with out usage of FIFOs; M ISTRAL
supports octet buffered reception via appropriate threshold configurations for the SCC
receive FIFOs)
• Support of interrupt acknowledge cycles
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-25 08.99
2 Pin Descriptions
2.1 Pi n Diagram P-TQFP-144- 10
(top view)
•
Figure 2-1 Pin Configuration P-TQFP-144-10 Package
N.C.
N.C.
N.C.
TDO
TCK
VDD
VSS
CTSB#/CxDB/TCGB#/OSRB
N.C.
VSSA
XTAL2
XTAL1
VDDA
N.C.
CTSA#/CxDA/TCGA#/OSRA
CDA/FSCA/RCGA#/OSTA
RxDA
RxCLKA
TxDA
VDD
VSS
TxCLKA
RTSA#
RESET#
INT/INT#
VDD
VSS
A15
A14
A13
A12
VDD
VSS
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
VDD
A19
A17
VSS
VDD
TMS
R/W# / W/R#
DS#/BHE#/LDS#
CS#
BM/ALE
VSS
VDD
A0/BLE#/UDS#
A1
A2
A3
VDD
VSS
WIDTH
A4
A5
A6
A7
VSS
VDD
A8
A9
A10
A11
N.C.
N.C.
VDD
VSS
RD#
WR#
READY#/DTACK#
CLK
VDD
VSS
D0
D1
D2
D3
VDD
VSS
D4
D5
D6
D7
TEST1
TEST2
VDD
VSS
D8
D9
D10
D11
N.C.
N.C.
A18
A16
N.C.
N.C.
A20
A21
VDD
VSS
A22
A23
BGNT#
BGACK#
GP1
VDD
VSS
GP0
GP2
RTSB#
RxDB
VDD
VSS
RxCLKB
TxDB
TxCLKB
CDB/FSCB/RCGB#/OSTB
ADS#/AS#
VDD
VSS
TRST#
TDI
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VDD
VSS
D12
D13
D14
D15
VDD
VSS
BREQ#
MISTRAL
PEB 20542
PEF 20542
108 73104 100 96 92 88 84 80 76
144
109
140
136
132
128
124
120
116
112
37
72
40
44
48
52
56
60
64
68
14 8 12162024283236
P-TQFP-144-10
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-26 08.99
2.2 Pin Definitions and Functions
Table 2-1 Microprocessor Bus Interface
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
117
116
115
114
106
105
104
103
98
97
96
95
92
91
90
89
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
I/O Data Bus
The data bus lines are bi-directional tri-state lines
which i nterfa ce wit h the system ’s data bus.
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-27 08.99
80
79
76
75
68
67
66
65
28
29
30
31
39
40
41
42
45
46
47
48
52
53
54
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Address Bus
These pins con nect to the system’ s addre ss bus
to select one of the internal registers for read or
write.
During operation of the internal DMA controller,
these lines output the destination address when
the bus is granted to the MISTRAL.
These lines are tri-state whe n unused.
55 A0
BLE
UDS
I/O
I/O
I/O
Address Line A0 ( 8-bit modes)
In Motorola and in Intel 8-bit mode this signal
repres ent s the least significant address line.
Byte Low Enable (16-bit Intel bus mode)
This signal indicates a data transfer on the lower
byte of the data bus (D7..D0). Togeth er with
signal BHE the type of bus access is determ in ed
(byte or word access at even or odd address ).
Upper Data Strobe (16-bit Motorola bus mode)
This active low strobe signal serves to control
read/write oper ations . Together with signal LDS
the type of bus access is determined.
This line is tri-state when unused.
T able 2-1 Micropro cessor Bus Interface
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-28 08.99
58 BM
ALE
I
I
Bus Mode
– BM = static ’1’ for operation in Motorola bus
mode (de-multiplexed).
– BM = static ’0’ for operation in Intel bus mode
with de-multiplexed addr ess and dat a buses.
– Pin BM/ALE has the function of an Address
Latch Enable (ALE) for operation in Intel bus
mode with a multiplexed address/data bus. A
falling edge on this pin selects Intel multiplexed
bus mode.
Address Latch Enable (mux’e d Intel bus)
The address is latched by the MISTRAL with the
falling edge of ALE.
The address pins A(15:0) mus t be externall y
connect ed to the data bus pins D(15:0).
136 ADS
AS O
OAddress Strobe (Intel Bus Mode)
" (Motorola Bus Mode)
Indic a tes th at the MI STRAL is drivin g a valid
address and bus cycle definition on pins A(23:0),
BHE (Intel mode) and R/W.
This line is tri-state when unuse d.
Table 2-1 Microprocessor Bus Interface
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-29 08.99
60 DS
BHE
LDS
I/O
I/O
I/O
Data Strobe (8- bi t Motorola bus m ode only )
This active low strobe signal serves to control
read/write oper ations .
Bus High Enable (16-bit Intel bus mode only)
This signal indicates a data transfer on the upper
byte of the data bus (D15..D8). In 8-bit Intel bus
mode this signal has no functi on.
Lower Data Strobe (16-bit Motorola bus mode)
This active low strobe signal serves to control
read/write oper ations . Together with signal UDS
the type of bus access is determined (byte or word
access at even or odd addre ss).
This line is tri-state when unused.
In 8-bit Intel bus mode, a pull-up resistor to V
DD3
is recommended on this pin.
83 RD I/O Read Strobe (Intel bus mode only)
This signal indicates a read operation. The bus is
able to accept data on lines D(7:0) / D(15:0)
during an active RD signal .
This line is tri-state when unused.
In Motorola bus mode, a pull-up resistor to V
DD3
is
recom me nded on this pin.
T able 2-1 Micropro cessor Bus Interface
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-30 08.99
61 R/W
W/R
I/O
O
Read/Write Enable (Motorola bus mode)
This signal distinguishes between read and write
operation. As an input it must be valid during data
str obe (DS).
Write/Read Enable (Intel bus mode)
Durin g master bus accesses from MISTRAL
(DMA) this signal indicates the transaction
direction (wr ite/read ). When MISTR AL is slave,
this signal is not evaluated.
This line is tri-state when unuse d.
If not used in Intel bus mode, a pull-up resistor to
V
DD3
is recommended on this pin.
59 CS IChip Sele c t
A low signal select s MISTRAL for read/write
operations.
84 WR I/O W rite Strobe (Intel bus mode only)
This signal indicates a write operation. Valid data
is present data on lines D(7:0) / D(15:0) during an
active WR si gnal .
This line is tri-state when unuse d.
In Motorola bus mode, a pull-up resistor to V
DD3
is
recom m ended on th is pin.
49 WIDTH I Width Of Bus Interface
A low signal on this input selects the 8-bit bus
interface m ode.
A high signal on this input selects the 16-bit bus
interface mode. In this case word transfer to/from
the internal registers is enabled . Byte transfers
are implemented by using BLE and BHE (Intel bus
mode) or LDS and UDS (Motorola bus mo de)
86 CLK I Clock
The system clock for MISTRAL is provided
through this pin.
Table 2-1 Microprocessor Bus Interface
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-31 08.99
25 INT/INT O
o/d Interrupt Request
The INT/INT goes active when one or more of the
bits in registers ISR0..ISR2 are set to ’ 1’ . A read
to these registe rs clears the interrupt. The INT/
INT line is inactive when all interrupt status bits
are reset.
Interru pt sources can be unmask ed in register s
IMR0..IMR2 by setting the corresponding bits to
’0’.
85 READY
DTACK I/O
I/O Ready (Inte l bus mode)
Data Transfer Acknowledge (Motorola mode)
During a slave access (register r ead/ w rite) this
signal (output) indicates, that the MISTRAL is
ready for data transfer. The signal remains active
until the data strobe (D S in M otorola bus m ode,
RD/WR in Intel bus mode) and/or the chip select
(CS) go inactive.
When the MISTRAL per forms a DMA master
access, the target may extend the read/write cycle
using this signal (input ) when enabled in register
DCMDR.
This line is tri-state when unused.
A pull-up resistor to V
DD3
is recommended if this
function is not used.
24 RESET IReset
With this act ive low signal the on-chip reg ister s
and state machines are forced to reset state.
During Reset all pins are in a high i m pedance
state.
T able 2-1 Microprocessor Bus Interface
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-32 08.99
Table 2-2 Bus Arbitration
Pin No. Symbol In (I )
O ut (O) Function
P-TQFP-
144-10
120 BREQ o/d Bus Request
By asserting this open-drain signal to low, the
MISTRAL requests m aste r bus acces s from the
external bus arbiter. As soon as the bus is granted
to the MISTRAL and BGACK is asserted, this
sign al turns to high-imped ance.
Bus preemption can be forced by the arbiter if it
asser ts this signal during the MISTRAL drives
BGACK active (low).
A pull-up resistor to V
DD3
must be connected to
this open- drain pi n.
122 BGACK o/d Bus Grant Acknowledge
With this signal the MISTRAL indicates the period
the bus is occupied for mas ter read or write
transf ers of the internal DMA control ler.
A pull-up resistor to V
DD3
must be connected to
this open- drain pi n.
121 BGNT IB us G rant
Wi th this active-low inp ut signal the bus arbiter
grants the bus to MISTRAL. MISTRAL w aits for
BGACK to go high (indicating that the external
bus master has released the bus) and takes over
the bus by asse rting BGACK low.
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-33 08.99
Table 2-3 Serial Port Pins
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
22 TxCLK
AI/O Transmit Clock Channel A
The function of this pin depends on the selected
clock mode and the value of bit ’TOE’ (CCR0L
register, refer to Table 3-2 "Clock Modes of the
SCCs" on page 3-47).
If programmed as Input (CCR0L.TOE=’0’),
either
– the transmit clock for the channel (clock
mode 0a, 2a, 4, 5b, 6a), or
– a transmit strobe signal for the channel (clock
mode 1)
can be provided to this pin.
If programmed as Output (CCR0L.TOE=’1’),
this pin supplies either
– the transmit clock from the baud rate generator
(clock m ode 0b, 2b, 3b, 6b, 7b), or
– the transmit clock from the DPLL circuit (clock
mode 3a, 7a), or
– an active-low control signal marking the
programmed transmit time-slot in clock mode
5a.
18 RxCLK
AIReceive C lock Channel A
The function of this pin d epends on the selec ted
clock mode (r efer to Table 3-2 "Clock Modes of
the SCCs" on page 3-47).
A signal provided on pin RxCLKA ma y supply
– the receiv e clock (clock m ode 0, 4, 5b), or
– the receive and transmit clock (clock mode 1,
5a), or
– the clock input for the baud rate generator
(clock mode 2, 3).
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-34 08.99
16 CDA
FSCA
RCGA
OSTA
I
I
I
I
Carrier Detect Channel A
The functi on of this pin depends on the selected
clock mode.
It can supp ly
– either a modem control or a general purpose
input (clock m odes 0, 2 , 3, 6, 7). I f auto-sta rt is
programmed, it functions as a receiver enable
signal.
– or a receive strobe signal (clock mode 1).
Polarity of CDA can be set to ’acti v e low’ with bit
ICD in register CCR1H.
Additionally, an interrupt may be issued if a state
transiti on occur s at the CDA pin (programmable
feature).
Frame Sync Clock Channel A (cm 5a)
When th e SCC is in the time-slot oriented clock
mode 5a, this pin functio ns as the Frame
Synchronization Clock input.
Rece ive Clock Gating Channel A (cm 4)
In clock mode 4 this pin is used as Receive Clock
Gati ng si g n al .
If no clock gating functi on is required, a pull-up
resi st or to V
DD3
is recommended.
Octet Sync Transmit Channel A (cm 5b)
When th e SCC is in the time-slot oriented clock
mode with oct et-align men t (clock mode 5b) , a
synchr oni zat ion pulse on this input pin aligns
transmit octets.
Table 2-3 Serial Port Pins (cont’d)
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-35 08.99
23 RTSA ORequest to Send Channel A
The function of this pin depends on the settings of
bits RTS, FRTS in register CCR1H .
In bus configuration, RTS can be programmed to:
– go low during the actual transmission of a
frame shifted by one clock period, excluding
collis io n bits .
– go low during reception of a data frame.
– stay always high (RTS disabled).
15 CTSA
CxDA
TCGA
OSRA
I
I
I
I
Clear to Send Channel A
A low on the CTSA inpu t enables t he transm itter.
Additiona lly, an interrupt may be issued if a st at e
transition occurs at the CTSA pin (programmable
feature).
If no ’Clear To Send’ function is required, a pu ll-
down resis tor to V
SS
is recommended.
Collision Data Channel A
In a bus configuration, the extern al seria l bus
must be connected to the corresponding CxDA
pin for collision detection.
A collision is detected whenever a logical ’1’ i s
driven on the open drain TxDA out put but a
logical ’0’ is detected via CxDA input.
Transmit Clock Gating Channel A (cm 4)
In clock mode 4 these pins are used as Transmit
Clock Ga ting si gnal s.
If no clock gating functio n is required, a pull-up
resi stor to V
DD3
is recommended.
Octet Sync Receive Channe l A (cm 5b)
(clock mode 5b)
When the SCC is in the time-slot oriented clock
mode with octe t-alignment (clock m ode 5b),
received octets are aligned to this synchronization
pulse input .
Table 2-3 Serial Port Pins ( cont’ d)
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-36 08.99
19 TxDA O
o/d Transmit Data Channel A
Transm it data is shifted out via this pin. It can be
configured as push/pull or open drain output
charac teris tic via bit ’ODS’ in register CCR1L.
17 RxDA I Receive Dat a Channel A
Serial data is received on this pin.
134 TxCLK
BI/O Transmit Clock Channel B
(corresp ondi ng to chann el A)
132 RxCLK
BIReceive Clock Channel B
(corresponding to channel A)
135 CDB
FSCB
RCGB
OSTB
I
I
I
I
Carrier Detect Channel B
Frame Sync Clock Channel B (cm 5a)
Rece ive Clock Gating Channel B (cm 4)
Octet Sync Transmit Channel B (cm 5b)
(corresponding to channel A)
128 RTSB OReque st to Send Channel B
(corresponding to channel A)
8CTSB
CxDB
TCGB
OSRB
I
I
I
I
Clear to Send Channel B
Collision Data Cha nnel B
Transmit Clock Gating Channel B (cm 4)
Octet Sync Receive Cha nnel B (cm 5b)
(corresp ondi ng to chann el A)
133 TxDB O
o/d Transmit Data Channel B
(corresponding to channel A)
Table 2-3 Serial Port Pins (cont’d)
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-37 08.99
129 RxDB I Recei ve Data Ch annel B
(corresponding to channel A)
12
11 XTAL1
XTAL2 I
OCrystal Connection
If the internal oscil lator is used for clock
generation (clock modes 0b, 6, 7) the external
crystal has to be connected to these pins. The
internal osci llator shou ld be power ed up
(GMODE:OSCPD = ’ 0’ ) and the signal shaper
may be activated (GMODE:DSHP = ’0’).
Moreover, XTAL1 may be used as input for a
common clock source to both SCCs, provided by
an extern al clock gene rat or (osci llat or). In this
case the oscillator unit may be powered down and
it is recommended to bypass the shaper of the
internal osci llator unit by setting bit ’DSH P’ to ’1’.
A pull-down resist or to V
SS
is recommended for
pin XTAL1 if not used.
T able 2-4 General Purpose Pins
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
127
123
126
GP2
GP1
GP0
I/O General Purpose Pins
These pins serve as general purpose input/output
pins.
A pull-up resistor to V
DD3
is recommended if pin is
not used.
Table 2-3 Serial Port Pins ( cont’ d)
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-38 08.99
Table 2-5 Te st Interface Pins
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
139 TRST IJTAG R eset Pin (internal pull-up)
For prope r device operation, a reset for the
boundary scan controller must be supplied to this
active low pin.
If the boundary scan of the MISTRAL is not used,
this pin can be connected to V
SS
to keep it in reset
state.
5TCKI JTAG Test Clock (intern al pull-up)
If the boundary scan of the MISTRAL is not used,
this pin ma y remai n unconnected .
140 TDI I JTAG Test Data Input (inte rnal pull-up)
If the boundary scan of the MISTRAL is not used,
this pin ma y remai n unconnected .
4TDOOJTAG Test Dat a Output
62 TMS I JTAG Test Mode Select (internal pull- up)
If the boundary scan of the MISTRAL is not used,
this pin ma y remai n unconnected .
99 TEST1 I Test Input 1
When connected to VDD3 the MISTRAL works in a
vendor specific test mod e.
This pin must be connected to V
SS
.
100 TEST2 I Tes t Input 2
When connected to VDD3 the MISTRAL works in a
vendor specific test mod e.
This pin must be connec ted to V
SS
.
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-39 08.99
Table 2-6 Power Pins
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
6, 20,
26, 32,
43, 51,
56, 63,
69, 77,
81, 87,
93,
101,
112,
118,
124,
130,
137
VDD3 -Dig ital Supply Voltage 3.3 V ±0.3 V
All pins must be connected to the same voltage
potential.
7, 21,
27, 33,
44, 50,
57, 64,
70, 78,
82, 88,
94,
102,
113,
119,
125,
131,
138
VSS -Digital Ground (0 V)
All pins must be connected to the same voltage
potential.
13 VDDA -Analog Supply Voltage 3.3 V ±0.3 V
This pin supplies t he on-ch ip osc illa tor of the
MISTRAL. It can be directly connected to VDD3.
PEB 20542
PEF 20542
Pin Descriptions
Preliminary Data Sheet 2-40 08.99
10 VSSA -Analog Ground (0 V)
This pin supplie s the ground level to the on-chip
osci llator of the MISTRAL. It can be directly
connect ed to VSS.
1, 2, 3,
9, 14,
34, 35,
36, 37,
38, 71,
72, 73,
74,
107,
108,
109,
110,
111,
141,
142,
143,
144
N.C. - Not Connected
Table 2-6 Power Pins (cont’d)
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-41 08.99
3 Functional Overview
T he functional blocks of MISTRAL can be div ided into two major domains:
– th e microprocesso r interface of MISTRA L pr ovides access t o internal on-chi p and to
the system portion of the receive and transmit FIFOs (RFIFO/XFIFO). Optionally
these FIFOs can be accessed by the built-in 4-channel DMA controller.
– the Serial Communication Controller (SCC) is capable of processing bit-synchronous
(HDLC/SDLC/bits ync PPP) and octet-synchronous (octet-sync PPP) as well as fully
transparent dat a traffic.
Data exchange between the serial communication controller and the microprocessor
interface is performed using FIFOs, decou pling these two cl ocking dom ai ns.
3.1 Block Diagra m
F igure 3-1 Block Diagram
Microprocessor
Interface
JTAG Test
Interface Serial
Channel A
Decoder/
Collision
Detection
Clock
Control
DPLL
FIFO
(3 2 Byte )
FIFO
(3 2 Byte )
XFIFO
(3 2 Byte )
RFIFO
(3 2 Byte )
Transmit
Protocol
Machine
Receive
Protocol
Machine BRG
LA P D/B
SS7
Serial
Channel B
TSA
5
7
7
55 Oscillator
Rx/Tx DM A
Controller
HDLC, ASYNC,
PPP, BIS YN C
XFIFO
(3 2 Byte )
RFIFO
(3 2 Byte )
Rx/Tx DM A
Controller
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-42 08.99
3.2 Serial Communication Controller (SCC)
3.2.1 Protocol Modes Overview
The SCC is a mult i-protocol communi cat ion cont roll er. The core l ogi c provides different
protocol modes w hich are listed bel ow:
• HDLC Modes
– HDLC Tran spar ent Oper ation (Address Mode 0)
– HDLC Addre ss Recogni t ion (A ddress Mode 1, Address Mode 2 8/16-bit)
–Full-Duplex LAPB/LAPD Operation (Automode 8/16-bit)
–Half -Duplex SD LC -NRM Operation (Automode 8-bit)
–Signa ling System #7 (SS7) Operation
• Point-to- Point Prot ocol (PPP) Modes
–Bit Synchronous PPP
–Octet Synchronous PPP
–Asynchronous PPP
• ASYNC Modes
–Asynchronous Mode
–Isoc hron ous Mod e
• BISYNC Modes
– Bisy nchro nous M ode
– Monosynchronous Mode
•Extended Transparent Mode
A detailed description of these protocol modes is given in Chapter 4, starting on page 4-
84.
3.2.2 S CC FIFOs
Each SCC provides its own transmit and receive FIFOs to handle internal arbitration and
microcont ro ller late nci es.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-43 08.99
3.2.2.1 SCC Transmit FIFO
The SCC transmit FIFO is divided into two parts of 32 bytes each (’transmit pools’). The
interface between the two parts provides clock synchronization between the system
clock domain and the protocol logic working with the serial transmit clock.
Figure 3-2 SCC Transmit FIFO
The 32 bytes system clocked FIFO part is accessable by the CPU/DMA controller; it
accepts transm it data even if the SCC is in power-down condition (register CCR0H bit
PU=’0’).
The only exception is a transmit data underrun (XDU) event. In case of an XDU event
(e.g. after excessive bus latency), the FIFO will neither accept more data nor transfer
anot her byte to the protocol logic. This XDU block ing mechanism prevent s unexpect ed
serial data. The blocking condition must be cleared by reading the interrupt status
register ISR1 after the XDU interrupt was generated. Thus, the XDU interrupt indication
shoul d not be masked i n register IMR1.
T ransfer of data t o the 32 byte shado w par t only takes place if the SCC i s in pow er-up
condition and an appropriate transmit clock is provided depending on the selected clock
mode.
Serial data transmission will start as soon as at least one byte is transferred into the
shadow FIFO and transmission is enabled depending on the selected clock mode (CTS
sign al acti ve, clock stro be signal activ e, timesl ot valid or clock gappi ng signal inac tive) .
3.2.2.2 SCC Receive FIFO
The SCC receive FIFO is divided into two parts of 32 bytes each. The interface between
the two parts provides clock synchronization between the system clock domain and the
protocol logic working with the serial receive clock.
32 byte Transm it P ool
(accessable by CPU )
32 byte Shadow part
(not accessable by CPU)
Microprocessor/DMA
Interface
Transmit
Protocol M achine
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-44 08.99
Figure 3-3 SCC Recei ve FIFO
New receive data is announced to the CPU with an interrupt latest when the FIFO fill
level reaches a chosen threshold level (selected with bitfield ’RFTH(1..0)’ in register
"CCR3H" on page 5-167). Default value f or this t hreshold level is 32 bytes in HDLC/ PPP
modes and 1 byte in ASYNC or BISYNC mode.
If the SCC receive FIFO is completely filled, further incoming data is ignored and a
receive data overflow condition (’RDO’) is detected. As soon as the receive FIFO
provides em pt y space, r ecei ve data is accepted again after a frame end or f ram e abort
sequence. The automatically generated receive status byte (RSTA) will contain an ’RDO’
indication in this case and the next incoming frame will be received in a normal way.
Therefore no further CPU intervention is necessary to recover the SCC from an ’RDO’
condition.
A "frame" with ’RDO’ status might be a mixture of a frame partly received before the
’RDO’ event occured and the rest of this frame received after the receive FIFO again
accepted data and the frame was still incoming. A quite arbitrary series of data or
complete frames might get lost in case of an ’RDO’ event. Every frame which is
completely discar ded because of an ’RDO’ conditi on genera tes an ’RFO’ interrupt.
The SCC receive FIFO can b e cleared by command ’RRES’ in register CMDRH. Note
that clearing the receive FIFO during operation might delete a frame end / block end
indication. A frame which was already partly transferred cannot be "closed" in this case.
A new frame received after receiver reset command will be appended to this "open"
frame.
Microprocessor/DMA
Interface
Receive
P rotocol M achine
32 byte R eceive Pool
(accessable by CP U)
32 byte Shadow part
(not accessable by CP U)
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-45 08.99
3.2.2.3 SCC FIFO Access
Figure 3-4 and Figure 3-5 illustrate byte interpretation for Intel and Motorola 16-bit
accesses to the transmit and receive FIFOs.
F igure 3-4 XFIFO/RFIFO Word Access (Intel Mode )
F igure 3-5 XFIFO/RFIFO Word Access (Motor ola Mode)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
B
y
te 1
B
y
te 2
B
y
te 3
B
y
te 4
B
y
te 5
B
y
te 32
D
(
7:0
)
D
(
15:8
)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
B
y
te 1
B
y
te 2
B
y
te 3
B
y
te 4
B
y
te 5
B
y
te 32
D
(
7:0
)
D
(
15:8
)
XFIFO RFIFO
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
B
y
te 1
B
y
te 2
B
y
te 3
B
y
te 4
B
y
te 5
B
y
te 32
D
(
7:0
)
D
(
15:8
)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
B
y
te 1
B
y
te 2
B
y
te 3
B
y
te 4
B
y
te 5
B
y
te 32
D
(
7:0
)
D
(
15:8
)
XFIFO RFIFO
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-46 08.99
3.2.3 Clocking System
The MISTRAL includes an internal Oscillator (OSC) as well as two independent Baud
Rate Generato rs (BRG) and two Digital Phase Locked Loop (DPLL) circ uits.
The transmit and receive clock can be generated either
• external ly, and suppli ed direct ly via the RxCLK and/or TxCLK pins
(called external clock modes)
• inte rnally, by selecting
– the internal oscillator (OSC) and/or the channel specific baud rate generator (BRG)
– the internal DPLL, recovering the receive (and optionally transmit) clock from the
receive dat a stream .
(called inte rnal clo ck mode s)
There are a total of 14 different clocking modes programmable via bit field ’CM’ in
register CCR0L, providing a wide variety of clock generation and clock pin functions, as
shown in Table 3-2.
The transmit clock pins (TxCLK) may also be configured as output clock and control
signals in certain cl ock mo des if enabl ed via bit ’TOE’ in register CCR0L.
The clocking source for the DPLL’s is always the internal channel specific BRG; the
scaling factor (divider) of the BRG can be programmed through BRRL and BRRH
registers.
There are two channel spec ific interna l operationa l clocks in the SCC:
One operational clock (= transmit clock) for the transmitter part and one operational clock
(= receive clock) for the rece iver part of the protocol logic.
Note: The internal timers always run using the internal transmit clock.
Table 3-1 Overview of Clock Modes
Clock
Type Source Generation Clock Mode
Receive
Clock
RxCLK Pins Externally 0, 1, 4, 5
OSC,
DPLL,
BRG,
Internally 2, 3a, 6, 7a
3b, 7b
Transmit
Clock
TxCLK Pins,
RxCLK Pins Externa lly 0a , 2a, 4, 6a
1,5
OSC,
DPLL,
BRG/BCR,
BRG
Internally 3a , 7a
2b, 6b
0b, 3b, 7b
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-47 08.99
The internal structure of each SCC channel consists of 3 clocking domains, transmit,
receive, and system. These three function blocks are clocked with internal transmit
frequency fTRM, internal re cei ve f reque ncy fREC and system frequency fSYS, r e s p e ctive ly
(system frequency fSYS only supplies the SCC receive and transmit FIFO part facing the
microprocessor interface). The internal FIFO interfaces are used to transfer data
between the different clock domain s.
The clocks fTRM and fREC are internal clocks only and need not be identical to external
clock inputs e.g. fTRM and TxCLK input pin.
The features of the different clock modes are summarized in Table 3-2.
T able 3-2 Clock Modes of the SCCs
Channel
Configuration Clock Sources Control Source s
Clock
Mode
CCR0L:
CM(2..0) CCR0L:
SSEL to
BRG to
DPLL to
REC to
TRM CD R- Strobe X- Str obe Frame-
Sync
Tx Rx
Output
via
TxCLK
(if CCR0L:
TOE = ‘1’)
0a
0b
1
2a
2b
3a
3b
4
5a
5b
6a
6b
7a
7b
0
1
X
0
1
0
1
X
0
1
0
1
0
1
–
OSC
–
RxCLK
RxCLK
RxCLK
RxCLK
–
–
–
OSC
OSC
OSC
OSC
–
–
–
BRG
BRG
BRG
–
–
–
–
BRG
BRG
BRG
–
RxCLK
RxCLK
RxCLK
DPLL
DPLL
DPLL
BRG
RxCLK
RxCLK
RxCLK
DPLL
DPLL
DPLL
BRG
TxCLK
BRG
RxCLK
TxCLK
BRG/16
DPLL
BRG
TxCLK
RxCLK
TxCLK
TxCLK
BRG/16
DPLL
BRG
CD
CD
–
CD
CD
CD
CD
–
–
–
CD
CD
CD
CD
–
–
CD
–
–
–
–
RCG
(TSAR/
PCMRX)
(TSAR/
PCMRX)
–
–
–
–
–
–
TxCLK
–
–
–
–
TCG
(TSAX/
PCMTX)
(TSAX/
PCMTX)
–
–
–
–
–
–
–
–
–
–
–
–
FSC
OST
–
–
–
–
–
–
–
–
–
–
–
–
FSC
OSR
–
–
–
–
–
BRG
–
–
BRG/16
DPLL
BRG
-
TS-Control
–
–
BRG/16
DPLL
BRG
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-48 08.99
Note: If one of the clock modes 0b, 6 or 7 is selected, the internal oscillator (OSC) is
enabled which allows connection of an external crystal to pins XTAL1-XTAL2. The
output signal of the OSC can be used for one serial channel, or for both serial
channels (independent baud rate generators and DPLLs). Moreover, XTAL1
alone can be used as input for an externally generated clock.
The first two columns of Table 3-2 list all possible clock modes configured via bit field
’CM’ and bit ’SSEL’ in register CCR0L.
For example , clock mode 6b is ch oosen by writing a ’6’ to regis ter CCR0L.CM (2:0) and
by setting bit CCR0L.SSEL equal to ’1’. The following 4 columns (grouped as ’Clock
Sources’) specify the source of the internal clocks. Columns REC and TRM correspond
to the domain clock f reque nci es fREC and fTRM .
The columns grouped as ’Control Sources’ cover additional clock mode dependent
control signals like strobe signals (clock mode 1), clock gating signals (clock mode 4) or
synchronization signals (clock mode 5). The last column describes the function of signal
TxCLK which in some clock modes can be enabled as output signal monitoring the
effective transm it clock or provid ing a time slot control signal (clock mode 5).
The following is an example of how to read Table 3-2:
For clock mode 6b (row ’6b’) the TRM clock (column ’TRM’) is supplied by the baudrate
generator (BRG) output divided by 16 (source BRG/16). The BRG (column ’BRG’) is
derived from the internal oscillat or which is supplied by pi n XTAL1 and XTAL2.
The REC clock ( column ’REC’) is supplied by t he internal DPLL which itself is supp lied
by the baud rate generator (column ’DPLL’) again.
Note: The REC clock is DPLL clock di vided by 16.
If enabled by bit ’TOE’ in registe r CCR0L the resulting transm it clock can be monitor ed
via pin TxCLK (last column, row ’6b’).
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-49 08.99
T he clockin g concept is illustrated i n a block diagram manner in the foll ow ing figur e:
Additional control signals are not illustrated (please refer to the detailed clock mode
de scr iptions bel ow ).
F igure 3-6 Clock Supply Overview
Oscillator
XTAL1
XTAL2
RxD
BRG
0b
6a/b
7a/b
2a/b
3a/b
DPLL 16:1
RxCLK
TxCLK
f
DPLL
f
BRG
f
BRG/16
f
RxCLK
f
TxCLK
f
DPLL
f
BRG
f
RxCLK
f
TRM
Transmitter Receiver
f
REC
TTL
or
CRYSTAL
f
DPLL
f
BRG
f
BRG/16
f
RxCLK
f
TxCLK
3a
7a 0b
3b
7b
2b
6b 1
5a 0a
2a
6a
4
5b
2a/b
3a
6a/b
7a
3b
7b 0a/b
1
5a/b
4
settings controlled by:
register CCR0, bit field 'CM'
selects the clock mode number
register CCR0, bit 'SSEL'
selects the additional a/b option
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-50 08.99
Clock Modes
3.2.3.1 Clock Mode 0 (0a/0b)
Separate, externa lly gener ated receive and transmit clocks are sup plied t o the SCC via
their respective pins. The transmit clock may be directly supplied by pin TxCLK
(clock mode 0a) or generated by the internal baud rate generator from the clock supplied
at pin XTAL1 ( cl ock m ode 0b).
In clock mo de 0b t he r esulting transm it clock can be dr i ven ou t to pin TxC LK i f enabl ed
via bit ’TOE’ in registe r CCR0L.
Figure 3-7 Clock Mode 0a/0b Configuration
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
2
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
or
(tx clock monitor output)
clock mode 0b
clock mode 0a
OSC
Ctrl.
Ctrl.
Ctrl.
Ctrl.
f
BRG
= f
OSC
/k
K=(n+1)/2
M
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-51 08.99
3.2.3.2 Clock Mode 1
Externally generated RxCLK is supplied to both the receiver and transmitter. In addition,
a rece ive strobe c an be connected vi a CD and a tra nsmit strobe v ia TxCLK pin. The se
strobe signals work on a per bit basis. This operating mode can be used in time division
mult iplex appli cat ions or for adjusting dispara te transmi t and receive data rates.
Note: In Extended Transparent Mode, the above mentioned strobe signals provide byte
synchronization (byte alignment).
This means that the strobe signal needs to be detected once o nly to transmit or
recei ve a com ple te byte.
F igure 3-8 Clock Mode 1 Configuration
RxCLK
CTS
, Cx D , TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clo ck suppl
y
1
clock m ode 1
receive strobe
transm it strobe
RxD
CD
(rx stro b e)
TxCLK
(tx stro b e)
RxCLK
TxD
V
SS
(enables transm it)
Note: In ex t e nd ed tr a nspa r e nt mod e th e strob e si
g
nals need to be detected once o nl
y
to
transm it or receive a com plete b
y
te. Thu s b
y
te ali
g
nme nt is p r ovided in t his mo de .
Ctrl.
Ctrl.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-52 08.99
3.2.3.3 Clock Mode 2 (2a/2b)
The BRG i s driven by an external cl ock (RxC LK pin) and delivers a reference cloc k for
the DPLL which is 16 times of the resulting DPLL output frequency which in turn supplies
the i nternal receive clock. Depending on the pr ogramming of r egister CCR0L bit ’SSEL’,
the transmit clock will be either an external input clock signal provided at pin TxCLK in
clock mode 2a or the clock delivered by the BRG divided by 16 in clock mode 2b. In the
latter case, the transm i t c lock can be dr iven out t o pin TxC LK i f enabled via bit ’ TO E’ in
register CCR0L.
Figure 3-9 Clock Mode 2a/2b Configuration
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
(tx clock monitor output)
clock mode 2b
clock mode 2a
BRG
DPLL 2
BRG
DPLL 16:1
Ctrl.
Ctrl.
Ctrl.
Ctrl.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-53 08.99
3.2.3.4 Clock Mode 3 (3a/3b)
The BRG is fed with an externally generated clock via pin RxCLK. Depending on the
value of bit ’SSEL’ in re gis ter CCR0L t he BR G delivers either a reference clock for t he
DPLL which is 16 times of the resulting DPLL output frequency (clock mode 3a) or
delivers directly the receive and transmit clock (clock mode 3b). In the first case the
DPLL output clock is used as receive and transm i t clock.
F igure 3-10 Clock Mode 3a/3b Configuration
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
(tx clock monitor output)
clock mode 3b
clock mode 3a
BRG
DPLL
(tx clock monitor output)
BRG
Ctrl.
Ctrl.
Ctrl.
Ctrl.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-54 08.99
3.2.3.5 Clock Mode 4
Separate, externally generated receive and transmit clocks are supplied via pins RxCLK
and TxCLK. In addition sepa rate r eceive and transmit clock gating signals are supplied
via pins R CG and TCG. Thes e gating signal s work on a per bit basis.
Figure 3-11 Clock Mo de 4 Configuration
RxCLK
CTS, CxD,
TCG
CD, FSC,
RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock suppl
y
1
clo ck mode 4
tra nsm it clock
g
ate s i
g
nal
receive clo ck
g
ate s i
g
nal
2
TxCLK
TCG
TxD
RxCLK
RCG
RxD
1 clock delay
Ctrl.
Ctrl.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-55 08.99
3.2.3.6 Clock Mode 5a (T ime Slot Mode)
This operation mode has been designed for application in time-slot oriented PCM
systems.
Note: For correct operati on NRZ data codi ng/e ncoding shoul d be used.
The receive and transmit clock are common for each channel and must be supplied
exte rnall y v ia pi n RxCLK. The SCC r ecei ves and t ran smits only during fixed time- slo ts.
Either one time-slot
– of programmabl e w idth (1 … 512 bit, via TTSA and RTSA re gis ters), and
– of programmable location with respect to the frame synchronization signal (via pin
FSC)
or up to 32 time-slots
– of consta nt width (8 bits), and
– of programmable location with respect to the frame synchronization signal (via pin
FSC)
can be sele cted.
The time-slot locations can be programmed independently for receive and transmit
direct ion via TTSA/RTSA and PCMTX/PCMRX registers.
Dep ending on the value pr ogrammed via tho se registers, the re ceive/transmit time-s lot
starts with a delay of 1 (minimum delay) up to 1024 clock periods following the frame
synchronization signal.
Figure 3-12 shows how to select a time-slot of programmable width and location and
Figure 3-13 show s how to select one or more time-slots of 8-bit width.
If bit ’TOE’ in regist er CCR0L is set, the selected transmit time-slot(s) is(are) indicated at
an outp ut stat us signal vi a pin TxCL K, which is driven to ‘low’ during t he activ e transm it
window.
Bit ’TSCM’ in register CCR1H determines whether the internal offset counters are
continuously running even if no synchronization pulse is detected at FSC signal or
stopping at their maximum value.
In the continuo us case th e repeti tion rate of offset coun ter operation is 1024 transmit or
receive clocks respectively. An FSC pulse detected earlier resets the counters and starts
opera tion agai n.
In the non-continuous case the time slot assigner offset counter is stopped after the
count er reached i ts maxi mum val ue and is started again if an FSC pulse is detected.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-56 08.99
Figure 3-12 Se lectin g one time-slot of programmable delay and width
70
0
TTSN TCSTCC 0
RTSN RCSRCC 0
TT SA0..3: T ransm it T im e Slot Assi
g
nmen t R e
g
ister
RTS A0 ..3 : Re c e iv e Time S lo t Ass i
g
nm ent Re
g
ister
T EPCM = '0': T PCM Mask D isabled
RE P CM = '0 ': RP C M Mask D isabled
TS d elay (tr a n s mit):
1 + TTS N *8 + T CS
(1...1024)
T S de lay (receive):
1 + RT SN *8 + R C S
(1...1024)
TS wid th (tra n s mit):
TCC
(1...5 1 2 c lo c ks )
T S w idth (receive):
RCC
(1..512)
FSC
RxCLK
active
time slot
TTSA1 7TTSA0 0707
TTSA3 TTSA2
700RTSA1 7RTSA0 0
707
RTSA3 RTSA2
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-57 08.99
Note: If time-slot 0 is to be selected, the DELAY has to be as long as the PCM frame
itself to achieve synchronization (at least for the 2nd and subsequent PCM
frames ): DE LAY = PCM frame length = 1 + xTSN *8 + xCS. xTSN and xCS have
to be set appropria tely.
Example: Time-slot 0 in E1 (2.048 Mbit/s) system has to be selected.
PCM frame length is 256 clocks. 256 = 1+ xTSN*8 + xCS. => xTSN = 31, xCS = 7.
Note: In extended transpare nt mode the width xCC o f the s ele cted time-slot has to be
n
×
8 bit because of character synchronization (byte alignment). In all other modes
the width can be used to define w indows down to a minimum length of one bit.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-58 08.99
Figure 3-13 Se lectin g one or more time-slots of 8-bit width
The common transmit and receive clock is supplied at pin RxCLK and the common frame
synchronisation signal at pin FSC. The "strobe signals" for active time slots are
generated internally by the time slot a ssigner block (TSA) independent in transmit and
receive direction.
When the transmit and receive PCM masks ar e enabled, bit fields ’TCC’ and ’RCC’ a re
ignored because of the constant 8-bit time slo t width.
TS delay (t ransm it):
1 + TTSN*8 + T CS
(1..1024)
TS delay (r ece ive):
1 + RTSN*8 + RCS
(1..1024)
31 24 23 16 15 8 7 0
PCMTX0..3: Transmit PCM Mask Regist er
...
1
3
1
17
TS0 TS1 TS2 TS3 TS4 TS5 TS16 TS17
8 bit
REPCM = '1': TPCM Mask Enabled
31 24 23 16 15 8 7 0
PCMRX0..3: Re ceive PCM Mask Register
FSC
RxCLK
active
tim e s lo t
700
TTSN TCS
TCC 1
TTSA0..3: Transmit Time Slot Assignment Register
TEPCM = '1': TPC M Mask Enabled
TTSA1 7TTSA0 0707
TTSA3 TTSA2
PCMTX1 PCMTX0
PCMTX3 PCMTX2
RTSN RCS
RCC 1
RTSA0..3: Receive Time Slot Assignm ent Register
700RTSA1 7RTSA0 07 07
RTSA3 RTSA2
PCMRX1 PCMRX0
PCMRX3 PCMRX2
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-59 08.99
F igure 3-14 Clock Mode 5a Configuration
Note: The transmit time slot delay and width is programmable via bit fields ’TTSN’, ’TCS’
and ’TCC’ in registers TTSA0..TTSA3.
The receive time slot delay and width is programmable via bit fields ’RTSN’, ’RCS’
and ’RCC’ in reg is ters RTSA0..RTSA3.
RxCLK
CTS
, CxD, TCG
CD,
FSC
, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
cloc k suppl
y
1
clock m ode 5a
time slot in d ic ato r si
g
nal
Tim e Slot
Assigner
(TSA)
RxCLK
FSC
internal
tx s trobe
TS delay TS width
TxCLK
TS-Control
TxD
internal
rx s tro be
TS de lay TS w idth
RxD
012n... 0n
Ctrl.
Ctrl.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-60 08.99
The following figures provide a more detailed description of the TSA internal counter
operation and exce ptional cases:
Figure 3-15 Clock Mo de 5a "Continuous Mode"
...
FSC
RxCLK,
TxCLK
active
time slot
load offset
ocnt
:
ocnt
:= 1024 -
TSdelay ocnt
:= 1024
ocnt
:= 0
load offset
ocnt
:
ocnt
:= 1024 -
TSdelay
load duration
dcnt
:
ocnt
:=
N
,
N
<
TSdelay
dcnt
:= 0
dcnt
:=
TSwidth
- 1
dcn t
:= 0
dcnt
:= 255
active
time slots according
PCMTX/PCMRX
Mode T EPCM/REPCM = '0'
Mode TEPCM/ REPCM = '1'
Exceptions:
a) FSC pulse period > 1024:
The offset coun ter
ocnt
will automaically restart after 1 024 clock cycles
and will be restarted again by the late FSC pulse!
b) FSC pu lse period < (
TSdelay
+
TSwidth
), i.e. FSC pulse det ected while duration counter still active:
The offset coun ter
ocnt
will automaically restart,
but duration counter
dcnt
continues operation (transmit/receive in active time slots)
clo ck mode 5a
bit TSCM='0' (c onti nuou s m ode)
ocnt
start
TSdelay
+ 1024 clock cycles
ocnt
restart
FSC
< 1024 clock cycles
FSC
dcnt
start
TSdelay
= 1 + xTSN*8 + xCS
(1...1024)
ocnt
restart
ocnt
restart
ocnt
start
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-61 08.99
Each frame sync p ulse st ar ts t he int ern al of fse t count er w i th (10 24 - TSdela y) whereas
TSdelay
is the configured val ue defin ing the start positi on. Whenever the offset counter
reach es its max imum value 1024, it triggers the duration counter to start operat ion.
If continuous mode is selected (bit CCR1H.TSCM=’0’) the offset counter continues
starting with value 0 until another frame sync puls is detected or again the maximum
valu e 1024 is reached.
Once the duration counter is triggered it runs out independently from the offset counter,
i.e. an active time slot period may overlap with the next frame beginning (frame sync
event , refer to exception b) in Figure 3-15).
Figure 3-16 Clock Mode 5a "Non Continuous Mode"
If non-continuous mode is selected (bit CCR1H.TSCM=’1’) the offset counter is stopped
on its maximum value 1024 until another frame sync puls is detected. This allows frame
sync periods greater than 1024 clock cycles, but the accesible part is limited by the range
of TSdelay value (1..1024) plus TSwidth (1..512) or plus 256 clock cycles if the PCM
mask is sele c te d .
ocnt
:=
TSdela
y
- 1
Exceptions:
a
)
FSC pulse period > 1024:
Th e off s et c o un te r
ocnt
will s t op o n it s ma x imu m v a lu e 1 0 2 4, wh ic h tr i
gg
er s th e d ur a tio n c o u nte r
dcnt
a n d w ill b e r e sta rte d a
g
ain b
y
the 'late' FSC pulse!
clo ck mo de 5a
bit TS CM ='1' (non continuous m ode)
ocnt
start
TSdela
y
+ 1024 clock c
y
cles
ocnt
stop
ocnt
start
FSC
A d ifferent behavior to clock m ode 5a continous m o de is
g
ive n o nly in
ca se of Exce ptio n a).
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-62 08.99
3.2.3.7 Clock Mode 5b (Octet Sync Mode)
This operation mode has been designed for applications using Octet Synchronous PPP.
It is based on clock mode 5a, but only 8-bit (octet) wide time slot operation is supported,
i.e. bits TTSA1.TEPCM and RTSA1.REPCM must be set to ’1’. Clock mode 5b provides
octet alignment to time slots if Octet Synchronous PPP protocol mode or extended
transparent mode is selected.
Note: For correct operation NRZ data coding/encoding should be used.
The receive and transmi t clock s are separ at e and m ust be supplied at pins RxC LK and
TxCLK. The SCC receives and transmits only during fixed octet wide time-slots of
programmable location with respect to the oc tet s ynchronization signals (v ia pins OSR
and OST)
The time-slot locations can be programmed independently for receive and transmit
direction via registers TTSA0..TTSA3 / RTSA0..RTSA3 and PCMTX0..PCMTX3 /
PCMRX0..PCMRX3.
Figure 3-17 sho ws how to select one or more octet wide time-slots.
Bit ’ TSCM’ in register CCR1H determines whether the internal counters are continuously
running even if no synchronization pulse is detected at OST/OSR signals or stopping at
t h ei r ma ximum valu e .
In the continuous case the repetition rate of operation is 1024 transmit or receive clocks
respectively. An OST/OSR pulse detected earlier resets the corresponding offset
counter and starts operation again.
In the non-continuous case the transmit/receive time slot assigner offset counter is
stopped after the counter reached its maximum value and is started again if an OST/
OSR pulse is detected.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-63 08.99
F igure 3-17 Selecting one or more octet wide t ime- slots
The transmit and receive clocks are supplied at pins RxCLK and TxCLK. The Octet
synchronisation signals are supplied at pins OSR and OST. The "strobe signals" for
active time slots are generated internally by the time slot assigner blocks (TSA)
inde pendent in transmit and recei ve directio n.
Bit fie lds ’TCC’ and ’RCC’ are ignored because of the constant 8-bit time slot width.
T S de la y (tra n smit):
1 + TTSN*8 + TC S
(1...1024)
TS delay (receive):
1 + RTSN*8 + RCS
(1...1024)
...
TS0 TS1 TS2 TS3 TS4 TS5 TS16 TS17
8 bit
OSR
OST
RxCLK
TxCLK
active
time slot
31 24 23 16 15 8 7 0
PCMTX0..3: Transm it PCM Mask Re
g
ister
1
3
1
17
700
TTSN TCSTCC 1
T T S A 0 ..3: T ra ns mit T ime S lo t As s i
g
nm en t R e
g
ister
T E PCM = '1 ': T PC M Mas k En a b led
TTSA1 7TTSA0 07 07
TTSA3 TTSA2
P C M T X1 P C M T X 0
PCMTX3 PCMTX2
R EP CM = '1': T P CM Mask En ab le d
31 24 23 16 15 8 7 0
PCMRX0..3: Receive PCM Mask Re
g
ister
RTSN RCSRCC 1
R T S A 0..3 : R ec eive Time Slot A ss i
g
nme nt R e
g
ister
70
0RTSA1 7RTSA0 0707
RTSA3 RTSA2
PCMRX1 PCMRX0PCMRX3 PCMRX2
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-64 08.99
Figure 3-18 Clock Mo de 5b Configuration
Note: The transmit time slot delay and width is programmable via bit fields ’TTSN’, ’TCS’
and ’TCC’ in registers TTSA0..TTSA3.
The receive time sl ot delay and widt h is programmable via bit fields ’RTSN’, ’RCS’
and ’RCC’ in registers RTSA0..RTSA3.
RxCLK
CTS, CxD, TCG ,
OST
CD, FSC, RCG ,
OSR
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock su ppl
y
1
clock mode 5b
Time Slot
Assigner
(RTSA)
RxCLK
TxCLK
OSR
OST
internal
tx s tro be
TS delay TS width
TxD
internal
rx strob e
TS delay TS width
RxD
012n... 0n
Ctrl.
Ctrl.
Time Slot
Assigner
(TTSA)
2
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-65 08.99
3.2.3.8 Clock Mode 6 (6a/6b)
This clock mode is identical to clock mode 2a/2b except that the clock source of the BRG
is supp lied at pin XTAL1.
T he BRG is driven by the int erna l oscillator and del i vers a reference clock for the D PLL
which is 16 times the resulting DPLL output frequency which in turn supplies the internal
receive clock. Depending on the programming of register CCR0L bit ’ SSEL’, the transmit
clock will be either an external input clock signal provided at pin TxCLK in clock mode
6a or the clock delivered by the BRG divided by 16 in clock mode 6b. In the latter case,
the transmit clock can be driven out to pin TxCLK if enabled via bit ’TOE’ in register
CCR0L.
F igure 3-19 Clock Mode 6a/6b Configuration
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
(tx clock monitor output)
clock mode 6b
clock mode 6a
BRG
DPLL
BRG
DPLL 16:1
or
V
SS
V
SS
or
OSC
OSC
Ctrl.
Ctrl.
Ctrl.
Ctrl.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-66 08.99
3.2.3.9 Clock Mode 7 (7a/7b)
This clock mode is identical to clock mode 3a/3b except that the clock source of the BRG
is supplied at pin XTAL1.
The BRG is driven by the internal oscillator. Depending on the value of bit ’SSEL’ in
register CCR0L the BRG delivers either a reference clock for the DPLL which is 16 times
the resulting DPLL output frequency (clock mode 7a) or delivers directly the receive and
transmit clock (clock mode 7b). In clock mode 7a the DPLL output clocks receive and
transmit data.
Figure 3-20 Clock Mo de 7a/7b Configuration
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
(tx clock monitor output)
clock mode 7b
clock mode 7a
BRG
DPLL (tx clock monitor output)
BRG
or
V
SS
V
SS
OSC
OSC
or
Ctrl.
Ctrl.
Ctrl.
Ctrl.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-67 08.99
3.2.4 Baud Rat e G enerator (BRG)
Each serial channel provides a baud rate generator (BRG) whose division factor is
controlled by registers BRRL and BRRH. Whether the BRG is in the clocking path or not
depends on the selected clock mode.
The clock division factor k is calculated by:
3.2.5 Clock Recovery (DPLL)
T he SCC offers the a dvantage o f recov ering the received clock fro m the rece ived data
by means of internal DPLL circuitry, thus eliminating the need to transfer additional clock
informat ion via a separ ate serial clock line . For this purpose, the D PLL is supplied w ith
a ‘ref erence clock ’ from the BRG which is 16 times the expected data clock rate (clock
mode 2, 3a, 6, 7a). The transmit clock may be obtained by dividing the output of the BRG
by a constant fac tor of 16 ( clock m ode 2b, 6b; bit ’SSEL’ in register CCR0L set) or al so
direct ly from the DPLL (clock mode 3a, 7a).
The main task of the DPLL is to derive a receive clock and to adjust its phase to the
inco ming dat a stream in order to enable optimal bit sampling.
T he mechan ism for cl ock recov ery depends on t he sel ected data en coding (see "Data
Encoding" on page 3-73).
The following functions have been implemented to facilitate a fast and reliable
synchronization:
Table 3-3 BRRL/BRRH Register and Bit-Fields
Register Bit-Fields
Offset Pos. Name Default Description
BRRL
38H/88H
5..0 BRN 0 Baud Rate Factor N
range N = 0..63
BRRH
39H/89H
11..8 BRM 0 Baud Rate Factor M,
range M = 0..15
kN1
+()
2M
×=
fBRG fin k
⁄=
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-68 08.99
Interference Rejection and Spike Filtering
Two or more edges in the same directional data stream within a time period of 16
reference clocks are considered to be interference and consequently no additional clock
adjustmen t is performed.
Phase Adjustment (PA)
Referring to Figure 3-21, Figure 3-22 and Figure 3-23, in the case where an edge
appears in the data stream within the PA fields of the time window, the phase will be
adjusted by 1/16 of the data.
Phase Shift (PS) (NRZ, NRZI only)
Referring to Figure 3-21 in the case where an edge appe ars in the data stream within
the PS field of the time w in dow, a s econd s amp ling of the bit i s forced an d the phase is
shifted by 180 degrees.
Note: Edges in all other parts of the time window will be ignored.
This operation facilitates a fast and reliable synchronization for most common
applications . Above all, it implies a very fast synchronization beca use of the phase shif t
feature: one edge o n the received data st ream is enough for the D PLL to synchron ize,
thereby eliminating the need for synchronization patterns, sometimes called preambles.
However, in case of extremely high jitter of the incoming data stream the reliability of the
clock recovery cannot be guaranteed.
The SCC offers the option to disable the Phase Shift function for NRZ and NRZI
encodings by setting bit ’PSD’ in register CCR0L to ’1’. In this case, the PA fields are
extended as shown i n Figure 3-22.
Now, the DPLL is more insensitive to high jitter amplitudes but needs more time to reach
the optimal sampling position. To ensure correct data sampling, preambles should
precede the data informa tion.
Figure 3-21, Figure 3-22 and Figure 3-23 explain the DPLL algorithms used for the
different data encodings.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-69 08.99
Figure 3-21 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Enabled)
Figure 3-22 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Disabled)
012345678910 11 12 13 14 15
0 +PA PS -PA 0
Bit Cell
DPLL
Count
Output
DPLL
Correction
ITD01806
0123456789101112131415
0+PA -PA 0
Bit Cell
DPLL
Count
Output
DPLL
Correction
ITD04820
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-70 08.99
Figure 3-23 DPLL Algorithm for FM0, FM1 and Ma nchest er Encoding
To supervise correct function when using bi-phase encoding, a status flag and a
maskable inter rupt infor m about synchr onous/asynchr onous state of the DPLL.
3.2. 6 SC C Tim e r Op er ati on
Each SCC provides a general purpose timer e.g. to support protocol functions. In all
operating modes the timer is clocked by the effective transmit clock. In clock mode 5
(time-slot oriented mode) the clock source for the timer can be optionally switched to the
frame sync clock (input p in FSC) by setting bit ’SRC’ in register TIMR3.
The timer i s c ont rolle d by th e C PU vi a access to re gis ters CMDRL and TIMR0..TIMR3.
The timer can be sta rted any t ime by setting bit ’STI’ in register CMDRL. After the timer
has expired it generates a time r interrupt (’TIN’).
Wit h bit f ield ’CNT( 2..0) ’ in regist er TIMR3 the number of automatic timer restarts can be
programmed. If the maximum value ’111’ is entered, a timer interrupt is generated
periodically, with the time period determined by bit field ’TVALUE’ (registers
TIMR0..TIMR3).
The timer can be stopped any time by setting bit ’TRES’ in register CMDRL to ’1’.
In HDLC Automode the timer is used internally for autonomous protocol functions (refer
to the chapter "Automode" on page 4-85). If this operating mode is selected, bit ’TMD’ in
register TIMR3 m ust be set to ’1’.
0123456789101112131415
0 +PA - ignore - -PA 0
Bit Cell ( FM Coding)
DPLL
Count
Clock
Transmit
Correction
ITD01807
76543210
Bit Cell (Manchester Co ding )
+PA - ignor e -
Receive
Clock
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-71 08.99
3.2.7 SCC Serial Bus Configuration Mode
Besid e the point-to-po int configur ation, the SCC ef fectively sup ports point-to-mult ipoint
(pt-m pt, or bus) configuration s by m eans of internal idle a nd col lision detect i on/col lision
resolution methods.
In a pt-mpt configuration, comprising a central station (master) and several peripheral
stations (slaves), or in a multimaster configuration, data transmission can be initiated by
each station over a common transmit line (bus). In case more than one station attempts
to transmit data simultaneously (collision), the bus has to be assigned to only one
stati on. A col lision-resolu tion procedure is implement ed in the SCC. Bus assignme nt is
based on a priority mechanism with rotating priorities. This allows each station a bus
access within a predetermined maximum time delay (deterministic CSMA/CD), no
matte r how many transmitters are connected to the serial bus.
Prer equisites f or bus operation ar e:
• NRZ encoding
• ‘OR’ing of data from every transmitter on the bus (this can be realized as a wired-OR,
using the TxD open drain capability)
• Feedba ck of bus information (CxD i nput ).
The bus configuration is selected via bitfield SC(2:0) in register CCR0H.
Note: Central clock supply for each station is not necessary if both the receive and
transmit clock is recovered by the DPLL (clock modes 3a, 7a). This minimizes the
ph ase shift between the individua l transm it clocks.
The bus configuration mode operates independently of the clock mode, e.g. also
together with clock mode 1 (receive and transmit strobe operation).
3.2.8 Serial Bus Access Procedure
T he idle state of the bus is i dentified by eight or m ore co nsecutive ‘1’ s. Whe n a devi ce
starts transmissi on of a fram e, the bus is reco gni zed t o be busy by the ot her d e vices at
the moment the first ‘zero’ is transmitted (e.g. first ‘zero’ of the opening flag in
HDLC mode).
After the frame has been transmit ted, the bus become s availab le again (idle).
Note: If the bus is occupied by oth er transmitters and/ or there is no trans mit r equest in
the SCC, logica l ‘1’ will be continuous ly transmitted on TxD.
3.2.9 Serial Bus Collisions and Recovery
During the transmission, t he data transmitted on TxD is compared with t he data on CxD.
In case of a mismatch (‘1’ sent and ‘0’ detected, or vice versa) data transmission is
imme dia tely abor ted , and idle (logical ‘1’) is transmitted.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-72 08.99
HDLC/SDLC: Transmission will be initiated again by the SCC as soon as possible if the
first part of t he frame is still present in the SCC transmit FIFO. I f not, an XMR interrupt is
generated.
Since a ‘zero’ (‘low’) on the bus prevails over a ‘1’ (high impedance) if a wired-OR
connection is implemented, and since the address fields of the HDLC frames sent by
different s tations normally differ from one anot her, the fact that a collision has oc curred
will be detected prior to or at the latest within the address field. The frame of the
transmitter with the highest temporary priority (determined by the address field) is not
affected and is transmitted successfully. All other stations cease transmission
immediate ly and return to bus moni toring state.
Note: If a wired-OR connection has been realized by an external pull-up resistor without
decoupling, the data output (TxD) can be used as an open drain output and
connected direc tly to the CxD input.
For correct identification as to which frame is aborted and thus has to be repeated
after an XMR int errupt has o ccurred, the content s of SCC transm it FIFO have t o
be unique, i.e. SCC transmit FIFO should not contain data of more than one frame.
For this purpose new data may be provided to the transmit FIFO only after ’ALLS’
interrupt status is detected.
3.2.10 Serial Bus Access Priority Scheme
To ensure that all competing stations are given a fair access to the transmission medium,
a two-stage bus access priority scheme is supported by MISTRAL:
Once a station has successfully completed the transmission of a frame, it is given a lower
level of priority. Thi s priority me chani sm is based on t he re quirem ent that a station m ay
attempt transmitting only when a determined number of consecutive ‘1’s are detected on
the bus.
Normally , a transmission can star t wh en ei ght consecut ive ‘ 1’s on the bus are det ect ed
(through pin CxD). When an HDLC frame has been successfully transmitted, the internal
priority class is decreased. Thus, in order for the same station to be able to transmit
another fram e, ten consec utive ‘1’s o n the bus must be detect ed. This gu arantees tha t
the transmission requests of other stations are satisfied before the same station is
allowed a second bus access. When ten consecutive ‘1’s have been detected,
transmission is allowed again and the priority class (of all stations) is increased (to eight
‘1’s).
Inside a priority class, the order of transmission (individual priority) is based on the HDLC
address, as explained in the preceding paragraph. Thus, when a collision occurs, it is
always the station transmitting the only ‘zero’ (i.e. all other stations transmit a ‘one’) in a
bit position of the address field that wins, all other stations cease transmission
immediately.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-73 08.99
3.2.11 Serial Bus Configuration Timing Modes
If a bus configura tion has been selected, the SCC provides two timing modes, diffe ring
in the time interval between sending data and evaluation of the transmitted data for
collision detection.
• Timing mode 1 (CCR0H:SC (2:0) = ‘001’)
Data is output with the rising edge of the transmit clock via the TxD pin, and evaluated
1/2 a clock period later at the CxD pin with the falling clock edge.
• Timing mode 2 (CCR0H:SC (2:0) = ‘011’)
Data is output with the falling clock edge and evaluated with the next falling clock
edge. Thus one complete clock per iod is avai lable between data out put and c ol lision
detection.
3.2.12 Functi ons Of Signal RTS in HDLC Mode
In clock modes 0 and 1, the RTS output can be programmed via register CCR1 (SOC
bits) to be active when data (frame or character) is being transmitted. This signal is
delayed by one clock period with respect to the data output TxD, and marks all data bits
that could be transmitted without collision (see Figure 3-24). In this way a configuration
may be implemented in which the bus access is resolved on a local basis (collision bus)
and wh ere the data are sent one clock per iod later on a separate trans mission line.
Figure 3-24 Reques t-to-Send in Bus O pera tion
Note: For details on the functions of the RTS pin refer to "Modem Control Signals
(RTS, CTS, CD)" on page 3-76.
3.2.13 Data Encoding
The SCC supports the following coding schemes for serial data:
– Non- Re tu rn -To-Ze ro (NRZ)
– Non-Return-To-Zero-Inverted (NRZI)
– F M 0 (also known as Bi-P hase Space)
– F M 1 (also known as Bi-P hase Ma rk)
ITT00242
Collision
TxD
CxD
RTS
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-74 08.99
– Manche ste r (also known as Bi-Phase )
The desired line coding scheme can be selected via bit field ’SC(2:0)’ in register CCR0H.
3.2.13.1 NRZ and NRZI Encoding
NRZ: The signal level corresponds to the value of the data bit. By programming bit ’DIV’
(CCR1L regi st er), the SCC may inve rt the transmis sion and recep tion of data.
NRZI: A logical ‘0’ is indicated by a transition and a logical ‘1’ by no transition at the
beginning of the bit cell.
Figure 3-25 NRZ and NRZI Data Encoding
3.2.1 3.2 FM0 and FM1 Encoding
FM0: An edge occurs at the beginning of every bit cell. A logical ‘0’ has an additional
edge in the center of the bit cell, whereas a logical ‘1’ has none. The transmit clock
precedes the recei ve clock by 90°.
FM1: An edge occurs at the beginning of every bit cell. A logical ‘1’ has an additional
edge in the center of the bit cell, a logical ‘0’ has none. The transmit clock precedes the
receive clock by 90°.
0110010
ITD05313
Transmit/
Receive Clock
NRZ
NRZI
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-75 08.99
F igure 3-26 FM0 and FM1 Data Encoding
3.2.13.3 Manchester E n cod ing
Manchester: In the first half of th e bit cell , the phys ical signal level corre sponds t o the
logical value of the data bit. At the center of the bit cell this level is inverted. The transmit
clock precedes the receive clock by 90°. The bit cell is shifted by 180° in comparison with
F M coding.
Figure 3-27 Manchester Data Encoding
110010
ITD01809
Receive
Clock
FM0
FM1
Transmit
Clock
110010
ITD01810
Receive
Clock
Manchester
Transmit
Clock
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-76 08.99
3.2.14 Modem Control Signals (RTS, CTS, CD)
3.2.14.1 RTS/CTS Handshaking
The SCC provides two pins (RTS, CTS) per serial channel supporting the standard
request-to-send modem handshaking procedure for transmission control.
A tr ansmit request will be indicated by outputt ing logical ‘0’ on the request-to-send output
(RTS). It is also possible to control the RTS output by software. After having received the
permission to trans mit (CTS ) the SCC starts data transmission.
In the case where permission to transmit is withdrawn in the course of transmission, the
frame is a borted and IDLE is sent. After transmission is enabled again by re-activation
of CTS, and if the beginning of the fra me is still avai lable in th e SCC, the frame will be
re-transmi tted (self-recover y). However, if the permission to transm it is withdrawn af ter
the data available in the shadow part of the SCC transmit FIFO has been completely
transmitted and the pool is released, the transmitter and the SCC transmit FIFO are
reset, the RTS output is deactivated and an inter rupt (XMR ) is generated.
Note: For correct identification as to which frame is aborted and thus has to be repeated
after an XMR int errupt has o ccurred, the content s of SCC transm it FIFO have t o
be unique, i.e. SCC transmit FIFO should not contain data of more than one frame,
which could happen if transmission of a new frame is started by providing new
data to the transmitter too early. For this purpose the ’All Sent’ interrupt
(ISR1.ALLS) has to be waited for before providing new transmit data.
Note: In the case where permission to transmit is not required, the CTS input can be
connected direc tly to
V
SS
and/or bit ’FCTS’ (register CCR1H) may be set to ’1’.
Additionally, any transition on the CTS input pin, sampled with the transmit clock, will
generate an interrupt indicated via register ISR1, if this function is enabled by setting the
’CSC’ bit in register IMR1 to ’0’.
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-77 08.99
Figure 3-28 RTS/CTS Handshaking
Beyond this standard RTS function, signifying a transmission request of a frame
(Reques t To Send), in HDLC mode the RTS output may be programmed for a spec ial
function v ia SOC1, SOC0 bits in the CCR1L regist er. This is only avai lable if the serial
channel is operating in a bus configuration mode in clock mode 0 or 1.
• If SOC1, SOC0 bits are set to ‘11’, the RTS output is active (= low) during the
reception of a frame.
• If SOC1, SOC0 bits are set to ‘10’, the RTS output function is disab led and t he RTS
pin remains always high.
3.2.14.2 Carrier Detect (CD) Receiver Control
Similar to the RTS/CTS control f or the t ransmitter, th e SCC su pports th e carrier det ect
modem control function for the serial receiver if the Carrier Detect Auto Start (CAS)
function is programmed by setting the ’CAS’ bit in register CCR1H. This function is
always available in clock modes 0, 2, 3, 6, 7 via the CD pin. In clock mode 1 the CD
func tion is not supporte d. See Table 3-2 for an overview.
If the CAS function is selected, the receiver is enabled and data reception is started when
the CD input is detected to be high. If CD input is set to ‘low’, reception of the current
char acter (b y te ) is st ill co mp le ted.
3.2.15 Local Loop Test Mode
T o provide fast and efficient testin g, the SCC can be operate d in a test mode by setting
the ’TLP’ bit in register CCR2L. The on-chip serial data input and output signals (TxD,
ITT00244
Sampling
CTS
TxCLK
TxD
RTS
~
~~
~~
~~
~
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-78 08.99
RxD) are connected, generating a local loopback. As a result, the user can perform a
self-test of the SCC.
Figure 3-29 SCC Test Loop
Transmit data can be disconnected from pin TxD by setting bit TLPO in register CCR2L.
Note: A sufficient clock mode must be used for test loop operation such that receiver and
transmitter operate with the same frequencies depending on the clock supply (e.g.
clock mode 2b or 6b).
3.3 Microprocessor Interface
The communication between the CPU and MISTRAL is done via a set of directly
accessi ble registers. The interface m ay be conf igured as Intel or Motorola type (re fer to
description of pin ’BM’) with a selectable data bus width of 8 or 16 bit (refer to description
of pin ’WIDTH’).
The CPU transfers data to/from MISTRAL (via 64 byte deep FIFOs per direction and
channel), sets the operating modes, controls function sequences, and gets status
informa tion by wri ting or reading contr ol/stat us regist ers .
All accesses can be done as byte or word accesses if enabled. If 16-bit bus width is
selected, ac cess to the lower/upper part of the data bus is determined by signals BHE/
BLE as shown in Table 3-4 (Int el mode) or by the upp er and l ower dat a strobe signal s
UDS/LDS as s hown in Table 3-5 (Motorola mo de).
Table 3-4 Dat a Bu s Access 16-bit Intel Mode
BHE BLE Regi ster Access Data Pins Used
0 0 Word access (16 bit) D(15:0)
0 1 Byte access (8 bit), odd address D(15:8)
SC C transmit
lo
g
ic
SCC receive
lo
g
ic
TLP='0'
TLP='1'
RxD
TxD
TLPO='0'
TLPO='1'
ID LE '1 '
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-79 08.99
Each of the two serial channels of MISTRAL is controlled via an identical, but completely
independent register set (Channel A and B). Global functions that are common to or
inde pendent from the two ser ial channels ar e located in global registers .
3.4 I nternal DMA Controller
3.4.1 Arbitration for Bus Control
Every time MISTRAL needs to access the bus in order to DMA transfer receive data from
the RFIFO to host memory or transmit data from host memory to the XFIFO, it has to
reque st the bus ar biter for the bus mastership. This is achieved by assertin g the open-
drain BREQ signal to low. When MISTRAL samples the bus grant (BGNT) active, it
1 0 Byte access (8 bit), even address D(7:0)
1 1 no data transfer -
T able 3-5 Data Bus Access 16-bit Motorola Mode
UDS LDS Register Access Data Pins Used
0 0 Word access (16 bit) D(15:0)
0 1 Byte access (8 bit), even address D(15:8)
1 0 Byte access (8 bit), odd address D(7:0 )
1 1 no data transfer -
Table 3-4 Data Bus Access 16-bit Intel Mode
BHE BLE Register Access Data Pins Used
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-80 08.99
acknowledges bus ow ner shi p by asser ting t he bus grant acknowled ge ( B G AC K) line t o
low.
Figure 3-30 MISTRAL requests and gets the bus
The BREQ signal becomes inactive one cl ock later and DMA transf er cyc les start.
MISTRAL holds the BGACK line low for the time it performs DMA read or write cycles on
the bus.
3.4. 2 Perf orm in g DMA Tran sf er s
The maximum number of bus transfers in sequence is 16 (word transfers in 16-bit bus
modes) or 32 (byte transfers in 8-bit bus modes). Each DMA initiated read and write
cycle is performed in four clock cycles, see Figure 3-31 with numbering of the cycle
sections in Intel ( T 1/T2) and Motorola ( S0. .S7) fashion.
Figure 3-31 Un-interrupted Series of 32 DMA Bus Cycles
CLK
BREQ
BGNT
BGACK
Start
Byte/Word Transfer
CLK
BGACK
Address
Strobe
Data
Strobe 1
st
bus cycle 2
nd
bus cycle
T1 T2 T1 T2
S0 S1 S2 S3 S4 S5 S6 S7
T2
32
nd
bus cycle
S0 S1 S2 S3 S4 S5 S6 S7 S5 S6 S7
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-81 08.99
3.4.3 Bus Preemption
Figure 3-32 Bus Preemption and Re-gain of Bus Control
3.4.4 Ending DMA Transfers
Figure 3-33 MISTRAL requests and gets the bus
3.5 Interrupt Architecture
For certain events in MISTRAL an interrupt can be generated, requesting the CPU to
read status information from MISTRAL. The interrupt line INT/INT is asserted with the
output characteristics programmed in bit field ’IPC(1..0)’ in register "GMODE" on page
5-124 (open drain/push pull, active low/high).
CLK
BREQ
BGNT
BGACK
MISTRAL
requests the bus
again
External arbiter
interrupts
MISTRAL
DMA transfers
MISTRAL
completed current
read/wr ite cycle
asserted by
arbiter asserted by
MISTRAL
CLK
BREQ
BGNT
BGACK Last Byte/Word
Transfer completed
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-82 08.99
Since only one interrupt request output is provided, the cause of an interrupt must be
determined by the CPU by reading the interrupt status registers (GSTAR, ISR0, ISR1,
ISR2, DISR, GPIS).
Figure 3-34 Int erru pt Status Registers
Each interrupt indication of registers ISR0, ISR1, ISR2, DISR and GPIS can be
selectively unmasked by resetting the corresponding bit in the corresponding mask
registers IMR0, IMR1, IMR2, DIMR and GPIM. Use of these registers depend s on the
selected serial mode.
If b it ’V IS’ in regi ster CCR0L is set to ’1’, masked interrupt status bits are visible in the
interrupt status registers ISR0..ISR2. Interrupts masked in registers IMR0..IMR2 wi ll not
generate an interrupt though. A read access to the interrupt status registers clears the
bits.
A global interrupt mask bit (bit ’GIM’ in register GMODE) suppresses interrupt generation
at all. To enable the interrup t system after reset, this bit must be set to ’ 0’ .
The Global Interrupt Status Register (GSTAR) serves as pointer to pending channel
related interrupts and gener al purpose port interrupts.
GPIM
GPI DMI ISA2 ISA1 ISA0 ISB2 ISB1 ISB0
GPIS
IMR2 (ch A)
ISR2 (ch A)
IMR1 (ch A)
ISR1 (ch A)
IMR0 (ch A)
ISR0 (ch A)
Ch annel A
Ch annel B
GSTARH
DIMR
DISR
PEB 20542
PEF 20542
Functional Over view
Preliminary Data Sheet 3-83 08.99
3.6 General Purpose Port Pin s
3.6.1 GPP Functional Description
Gen eral purpo se pins are provided on pins GP0... GP2.
Every pin is separately programmable via the General Purpose Port Direction register
GPDIR to operate as an output (bit GPnDIR=’0’) or as an input (bit GPnDIR=’1’, reset
value).
If defined as output, the state of the pin is directly controlled via the General Purpose Port
Data register GPDAT. Read access to these registers delivers the current state of all
GPP pins (input and output signal s).
If defined as input, the state of the pin is monitored. The signal state of the corresponding
GP pins is sampl ed with a rising edge of CLK and is readable via register GPDAT.
3.6.2 GPP Interrupt Indic ation
The GPP block generates interrupts for transitions on each input signal. All changes may
be indicated via interrupt (optional). To enable interrupt generation, the corresponding
interr upt mask bit in register GPIM must be reset to ’0’.
Bit PI in the gloabl interrupt status register (GSTAR) is set to ’1’ if an interrupt was
generated by any one or more of the the general purpose port pins. The GPP pin causing
the interru pt can be located by reading th e GPIS register.
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-84 08.99
4 Detailed Protocol Descr iption
The following Table 4-1 provides an overview of all supported protocol modes and . The
desired protocol mode is selected via bit fields in the channel configuration registers
CCR0L, CCR0H, CCR2L and CCR3L.
Table 4-1 Protocol Mode Overview
All modes are discuss ed in details in this chapter.
Registe r CCR0H - Bit Field SM(1:0) = ’00’ Register CCR2L - Bit Field: CCR3L
(HDLC/SDLC/PPP protocol engine) M DS ADM PPPM ESS7
HDLC Automode
(LAP D / LAP B / SDLC-NRM) 16 bit ’00’ ’1’ ’00’ ’0’
8 bit ’00’ ’0’
HDLC Address Mode 2 16 bit ’01’ ’1’
8 bit ’01’ ’0’
HDLC Address Mode 1 ’10’ ’1’
HDLC Address Mode 0 ’10’ ’0’
Signaling Syste m #7 (SS7) Operation ’10’ ’0’ ’00’ ’1’
Bit Synchronous PPP M ode ’10’ ’0’ ’11’ ’0’
Octet Synchron ous PPP Mode ’01’
Asynchr onous PPP Mode ’10’
Extended Transparent Mode1)
1) Extended transparent mode is a fully bit-transparent transmission/reception mode which is treated as sub-
mode of the HDLC/SDLC/PPP block.
’11’ ’1’ ’00’ ’0’
Registe r CCR0H - Bit Field SM(1:0) = ’11’ Register CCR0L - Bit Field:
(ASYNC protocol engi ne) BCR
Asynchr onous M ode ’1’
Isochronous Mode ’0’
Register CCR0H - Bit Field SM(1:0) = ’10’ Register CCR0L - Bit Field:
(BISYNC protocol engine) EBIM
Bi s yn ch ro no us Mo de ’1 ’
Monosynchronous Mode ’0’
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-85 08.99
4.1 HDLC/SDLC Protocol Modes
The HDLC controller of each serial channel (SCC) can be programmed to operate in
various modes, which are different in the treatment of the HDLC frame in receive
direction. Thus, the receive data flow and the address recognition features can be
performed in a very flexible way satisfying almost any application specific requirements.
There are 4 different HDLC operating modes which can be selected via register CCR2L.
4.1.1 HDLC Submodes Overview
The following table provides an overview of the different address comparison
mechanism s in HDL C operat ing modes:
4.1.1.1 Automode
Characteristics: Window size 1, random message length, address recognition.
The SCC processes autonomously all numbered frames (S-, I-frames) of an HDLC
protocol. The HDLC control field, I-field data of the frames and an additional status byte
are tempo rar ily stored in the SCC receive FIFO.
Depending on the selected address mode, the SCC can perform a 2-byte or 1-byte
address reco gnition.
If a 2-byte address field is selected, the high address byte is compared with the fixed
value FEH or FCH (group address) as well as with two individually programmable values
T able 4-2 A ddr ess Comparison Overview
Mode Address
Field Recognized Address Bytes for a Match:
High Address Byte Low Address Byte
Address
Mode 2
-
Auto
Mode
16 bit FEH / F CH (1111 11 C/R 02)
and
RAL1
FEH / FCH (1111 11 C/R 02)
and
RAL2
RAH1
and
RAL1
RAH2
and
RAL2
8 bit RAL1
don’t care
RAL2
don’t care
Address
Mode 1 8 b it FEH / FCH (1111 11 C/R 02)
don’t care
RAH1
don’t care
RAH2
don’t care
Address
Mode 0 None
don’t care don’t care
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-86 08.99
in RAH1 and RAH2 registers. According to the ISDN LAPD protocol, bit 1 of the high
byte address will be interpreted as COMMAND/RESPONSE bit (C/R), depending on the
setting of the CRI bit in RAH1, and wil l be exc luded from the address compa rison.
Similarly, two comparison values can be programmed in special registers (RAL1, RAL2)
for the low address byte. A valid address will be recognized in case the high and low byte
of the address field correspond to one of the compare values. Thus, the SCC can be
called (addressed) with 6 different address combinations, however, only the logical
connection identified through the address combination RAH1/RAL1 will be processed in
the auto-mode, all others in the non auto-mode. HDLC frames with address fields that
do not match any of the address comb inations, are ignored by the SCC.
In the case of a 1-byte address, only RAL1 and RAL2 will be used as comparison values.
According to the X.25 LAPB protocol, the value in RAL1 will be interpreted as
COMMA ND and the value in RAL2 as RESPONSE.
The address bytes can be masked to allow selective broadcast frame recognition. For
further information see "Receive Address Handling" on page 4-89.
4.1.1.2 Address Mode 2
Characteristics: address recogni tion, arbitrary wi ndow siz e.
All frames with valid addresses (address recognition identical to auto-mode) are
forwarded direct ly to the RFIFO.
The HDLC contr ol fi eld, I-fie ld data and an addi tional st atus byt e ar e t em porar ily s tored
in the SCC receive FIFO.
In address mode 2, all frames with a valid address are treated sim ilarly.
The address bytes can be mas ked to allow select ive broad cast frame recogni tion.
4.1.1.3 Address Mode 1
Characteristics: address recogni tion hig h byte.
Only the high byte of a 2-byte address field will be compared. The address byte is
compared with the fixed value FEH or FCH (group address) as well as with two
individually programmable values RAH1 and RAH2. The whole frame excluding the first
address byte will be sto red in the SCC receive FIFO.
The address bytes can be mas ked to allow select ive broad cast frame recogni tion.
4.1.1.4 Address Mode 0
Characteristics: no address recog nitio
No address recognition is performed and each complete frame will be stored in the SCC
receive FIFO.
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-87 08.99
4.1.2 HDLC Receive Data Processing
The following figures give an overview about the management of the received frames in
the different HDLC operating modes. The graphics show the actual HDLC frame and
how MISTRAL interprets the incoming octets. Below that it is shown which octets are
store d in the RF IFO and will thus be trans ferred in to memo ry .
Figure 4-1 HDLC Receive Data Processing in 16 bit Automode
Figure 4-2 HDLC Receive Data Processing in 8 bit Automode
Figure 4-3 HDLC Receive Data Processing in Address Mode 2 (16 bit)
CRC16
FLAGFLAG (high) (low)
16 bit ADDR
CTRL I -field (data)
/32
to RFIFO
RAH1,2 RAL1,2
option 1) option 2)
RSTA
RSTA
registers
involved (address
compare)
Automode
16 bit
CRC16
FLAGFLAG (low)
8 bit
ADDR
CTRL I-field (data)
/32
to RFIFO
RAL1,2
opt. 1) option 2)
RSTA
RSTA
registers
involved (address
compare)
Automode
8 bit
CRC16
FLAGFLAG (high) (low)
16 bit ADDR
data
/32
to RFIFO
RAH1,2 RAL1,2
option 1) option 2)
RSTA
RSTA
registers
involved (address
compare)
Address Mode 2
16 bit
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-88 08.99
Figure 4-4 HDLC Recei ve Data Process ing in Address Mode 2 (8 bit )
Figure 4-5 HDLC Recei ve Data Process ing in Address Mode 1
Figure 4-6 HDLC Recei ve Data Process ing in Address Mode 0
option 1)
The address field (8 bit address, 16 bit address or the high byte of a 16 bit address) can
optionally be forwarded to the RFIFO (bit 'RADD' in register CCR3H)
option 2)
The 16 bit or 32 bit CRC field can optionally be forwarded to the RFIFO (bit 'RCRC' in
register CCR3H)
CRC16
FLAGFLAG (low)
8 bit
ADDR
data
/32
to RFIFO
RAL1,2
opt. 1) option 2)
RSTA
RSTA
registers
involved (address
compare)
Address Mode 2
8 bit
CRC16
FLAGFLAG
8 bit
ADDR
data
/32
to RFIFO
RAH1,2
opt. 1) option 2)
RSTA
RSTA
registers
involved (address
compare)
Address Mode 1
16 bit ADDR
CRC16
FLAG
FLAG data
/32
to RFIFO option 2)
RSTA
RSTA
registers
involved
Address Mode 0
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-89 08.99
4.1.3 Receive Address Handling
T he Receive Addr ess Low/ High Bytes ( reg isters RAL1/RAH1 and RAL2/RAH2) ca n be
masked on a per bit basis by setting the corresponding bits in the mask registers
AMRAL1/AMRAH1 and AMRAL2/AMRAH2. This allows extended broadcast address
recognition. Masked bit positions always match in comparison of the received frame
address with the respect iv e addres s field s in the Rece ive Address Low /H igh registers.
This feature is applicable to all HDLC protocol modes with address recognition (auto
mode , ad dress mo de 2 and address mode 1). It is disabled if all bits of mask bit fields
AMRAL1/AMRAH1 and AMRAL2/AMRAH2 are set to ‘zero’ (which is the reset value).
Detect ion of the fixed gr oup addr ess FEH or FCH, if applicable to the selected operating
mode, rem ains unchanged.
As an option in the auto mode, address mode 2 and address mode 1, the 8/16 bit
addre ss f ield of re ceived f rames can be p ushed t o t he r ecei ve data buffer (first on e/two
bytes of the frame). This function is especially useful in conjunction with the extended
broadcast address recognition. It is enabled by setting control bit ’RADD’ in register
CCR3H.
4.1.4 HDLC Transmit Data Processing
T wo different types of frames can be transmit ted:
– I-frames and
– transparent frame s
as shown below.
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-90 08.99
Figure 4-7 SCC Transmit Data Fl ow (HDLC Modes)
For transmission of I-frames (selected via transm it command ’ XIF’ in register CMDRL),
the address and control f ields are genera ted a uton omo usl y by the SC C and the data in
the correspo ndi ng t rans mit data buffer is ent ered into the i nf ormat ion fiel d of the frame .
This is possible only if the SCC is operated in Automode.
For (address-) transparent frames, the address and the control fields have to be entered
in the transmit data buffer by software. This is possible in all operating modes and used
also in auto-mode for sending U-fram es .
If bit ’XCRC’ in register CCR2H is set, the CRC checksum will not be generated
internally. The c hecksum has t o be pr ovi ded via t he t rans mit data buffer as t he l ast two
or four bytes by software. The transmitted frame will be closed automatically only with a
(closing) flag.
CRC16
FLAG
FLAG
8 bit
ADDR
data
/32
XFIFO
XAD1
option 2)
registers
involved
Frames with automatic 8 or 16 bit Address and Control Byte Generation
(Automode):
option 2)
Generation of the 16 or 32 b it CRC field can optional ly be disabl ed by setti ng bit 'XCRC' in
register CCR2H, in which case the CRC must b e calculated and written int o the la st 2 or 4
bytes of the t ransmit FIFO, to immediat ely proceed closing flag.
16 bitADDR
XAD2
CRC16
FLAGFLAG data
/32
XFIFO option 2)
Frames withou t automatic Address and Control Byte Generation
(Address Mode 2/1/0):
CTRL
internally
generated
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-91 08.99
Note: The SCC does not check whether the length of the frame, i.e. the number of bytes,
to be transm itt ed make s sense according the HDLC prot ocol or not .
4.1.5 Sha red Flags
If the ‘Shared Flag’ feature is enabled by setting bit ’SFLG’ in register CCR1L the closing
flag of a previously transmitted frame simultaneously becomes the opening flag of the
follo wing frame if there is one already avai lable in the SCC transmit FIFO.
In receive direction the SCC always expects and handles ’Shared Flags’. ’Shared
Z eroes ’ of consecuti ve flags are also supp orted.
4.1.6 One Bit Insertion
Similar to the zero bit insertion (bit stuffing) mechanism, as defined by the HDLC
protocol, the SCC offers a feature of inserting/deleting a ’on e’ after seven consecutive
‘zeros’ into the transmit/receive data stream, if the serial channel is operating in bus
configuration mode. This method is useful if clock recovery is performed by DPLL.
Since only NRZ data encoding is supported in a bus configuration, there are possibly
long sequences without edges in the receive data stream in case of successive ‘0’s
received, and the DPLL may lose synchr onizat ion .
Enabling the one bit insertion feature by setting bit ’OIN’ in register CCR2H, it is
guaranteed that at least after
– 5 consecutive ‘1’s a ‘0’ will appear (bit stuffing), and after
– 7 consecutive ‘0’s a ‘1’ will appear (one insertion)
and thus a correct function of the DPLL is ensured.
Note: As w ith the bit stuffing , the ‘one ins ertio n’ is fully transparent to t he user, but it is
not in accordance with the HDLC protocol, i.e. it can only be applied in proprietary
systems using circuits that also implement this function, such as the PEB 20532
and PEB 20525.
4.1.7 Preamble Transmission
If ena bled via bit ’EPT’ i n regist er CCR2H, a pro grammable 8- bit pattern i s transm itted
wit h a selectable numb er o f repet i tions a fter Interfr ame Timef ill transm i ssi on is stopped
and a new frame is ready to be sent out. The 8 bit preamble pattern can be programmed
in reg ister PREAMB and the repetition time in bit field ’PRE’ of register CCR2H.
Note: Zero Bit Insertion is disabled during prea mble transm i ssi on.
4.1 .8 CRC Generatio n and C he cking
In HDLC/SDLC mode, error protection is done by CRC generation and checking.
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-92 08.99
In standard applications, CRC- CCITT algorithm is used. The Frame Check Sequence at
the end of each frame consists of two bytes of CRC checksum.
If required, the CRC-CCITT algorithm can be replaced by the CRC-32 algorithm,
enabled via bit ’C32’ in register CCR1L. In this case the Frame Check Sequence
consists of four bytes.
Optionally the internal handling of received and transmitted CRC checksum can be
influenced v ia control bits ’RCRC’, ’DRCRC’ in register CCR3H and ’XCRC’ in register
CCR2H.
Receive direction:
If n o t disa bl e d by setting b it ’DRCRC’ (reg is te r CCR3H), t h e re c e iv e d CRC c h e c ksu m is
always assumed to be in the 2 (CRC-CCITT) or 4 (CRC-32) last bytes of a frame,
immediately preceding a closing flag. If bit ’RCRC’ is set, the received CRC ch ecksum
is treated as data and will be forwarded to the RFIFO, where it precedes the frame status
byte. Nevertheless the r eceived CRC checksum is additionall y checked for correctness.
If C RC che cki ng is disable d w i t h bit CCR3H:D RCRC, t he limits for ‘ Val id Fr am e’ check
are modified accordingly (refer to description of the Receive Status Byte, RSTA:VFR).
Transmit direction:
If bi t ’XCRC’ is set, the CRC checksum is not generated internally. The checksum has to
be provided via the transmit data buffer by software. The transmitted frame w ill on ly be
closed automatically with a (closing) flag.
Note: The SCC does not check whether the length of the frame, i.e. the number of bytes,
to be transmitted makes sense or not according the HDLC protocol.
4.1.9 Receive Length Check Feature
The SCC offers the possibility to supervise the maximum length of received frames and
to terminate data reception in the case that this length is exceeded.
This feature is controlled via the special Receive Length Check Registers RLCRL/
RLCRH.
The function is enabled by setting bit ’RCE’ (Receive Length Check Enable) and the
maximum frame length to be checked is programmed via bit field ’RL’. The maximum
receive length can be determined as a multiple of 32-byte blocks as follows:
MAX_LENGTH = (RL + 1) × 32 ,
where RL is the value written to bit field ’RL’. Thus, the maximum length of receive
frames can be program me d between 32 and 65536 bytes.
All frames exceeding this length are tre ated as if they had been a borted b y the remote
station, i.e. the CPU is informed via
– an ’RME’ interrupt generated by the SCC, and
– t he rece ive abort indication ’RAB’ in the Receive Status Byte (RSTA).
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-93 08.99
Additionally an optional ’FLEX’ interrupt is generated prior to ’RME’, indicating that the
max imum receive fram e length was exceeded.
Rec eive operati on cont inues wit h the beginning of the next receive fram e.
4.2 Point-to-Point Pr otocol (PPP) Mo des
PPP (as described in RFC1662) can work over 3 modes: asynchronous HDLC,
synchronous HDLC, and octet synchronous. The MISTRAL supports asynchronous
HDLC PPP over ISDN or DDS circuit s as well as bit and octet synchronous HDLC PPP
for use over dial-up connections. The octet synchronous mode of PPP protocol (RFC
1662) supports PPP over SONET applications.
Both the asynchronous HDLC PPP mode, as well as the synchronous HDLC PPP
modes are submodes of the HDLC mode. Either mode is selected by configuring
MISTRAL for the standard HDLC mode. In addition the appropriate PPP mode is
selected via bit field ’PPPM’ in r egister CCR2L.
The MISTRAL provides logic to convert an HDLC frame to an ASYNC character stream
with the specified m apping funct i ons. Layer 3 PPP functions ar e normally implem ented
in software.
The PPP-support hardware allows soft ware to perform segmentation and reassembly of
PPP payloads, and allows MISTRAL to perform the asynchronous HDLC PPP or the
synchronous HDLC PPP protocol conversions as required for the network interface.
4.2.1 Bit Synchronous PPP
The MISTRAL transmits a data block, inserts HDLC Header (Opening Flag), and
appends the HDLC Trailer (CRC, Ending Flag). Zero-bit stuffing algorithm is also
performed. No character map ping is performed. The bit-synchronous PPP mode differs
from the HDLC mod e (address m ode 0) only in the abort sequenc e:
HDLC requires at least 7 consecutive ’1’ bits as abort sequence, whereas PPP requires
at least 15 ’1’ bits.
For receive operation MISTRAL monitors the incoming data stream for the Opening Flag
(7E Hex) to identify the beginning of a HDLC packet. Subsequent bytes are part of data
and are pro cesse d as normal HDLC packet including checking of CRC.
4.2.2 Octet S ynch ronous PPP
The MISTRAL transmits a data block, inserts HDLC Header (Opening Flag), and
appends the HDLC Trailer (CRC, Ending Flag). Beside this standard HDLC operation,
zero-bi t stuffing is not performed, but charact er mappi ng is performed.
For receive operation MISTRAL monitors the incoming data stream for the Opening Flag
(7E Hex) to identify the beginning of a HDLC packet. Subsequent bytes are part of data
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-94 08.99
and are processed as normal HDLC packet including checking of CRC. Received
mapped char acters ar e unma pped.
4.2.3 Asynchronous P PP
For transmit operation, MISTRAL inserts the HDLC header (Opening Flag), and appends
the HDLC trailer (CRC, Ending Flag), surrounding the transmit data read from the
XFIFO. Each octet (including HDLC framing flags and idle flags) is converted into async
character format (1 start, 8 data bits, 1 stop bit) and then transmitted using the
asynchron ous character formatter bloc k. Charact er mapping l ike in Octet Syn chronous
PPP mode is performed.
In receive direction any async character is transferred into MISTRAL’s ASYNC
Character De-Formatting logic block, where it is translated back into the original
information octet. Mapped characters are unmapped and the information octets are then
transferred to t he RFIFO (as in Octet Synchron ous PPP mode).
4.2.4 Data Transparency in PPP Mode
When transporting bit-files (as opposed to text files), or compressed files, t he characters
could easily represent MODEM control characters (such as CTRL-Q, CTRL-S) which the
MODEM would not pass through. MISTRAL maintains an Async Control Character Map
(ACCM) for characters 00-1F Hex. Whene ver there is a mapped ch arac ter in the data
stream, the tra nsm itte r pr ecedes that character wit h a cont ro l-escape char act er of 7DH.
After the cont rol-e scape, t he character i tself is transmitted wi th bit 5 inverted. char act er
e.g. 13H is mapped to 7DH, 33 H).
At the rece ive end, a 7DH character is discarded and the following character is modified
by inverting bit 5 (e.g. if 7DH, 33H is received, the 7DH is discarded and the 33H is
changed to 13H the original character).
The 32 lookup octet values (00H-1FH) are stored within the on-chip registers ACCM0..3.
In addition to the ACCM, 4 user programmable characters (especially outside the range
00-1F Hex) c an also be mapped using the control-escape seq uence described above.
These characters are specified in registers UDAC0..3.
The receiver disca rds all char acters which are rec eiv ed unmapped, but expec ted t o be
mapped becau se of ACCM0..3 and UDAC0..3 register content s. If this occurs within an
HDLC frame , the u nexpected char act ers are dis card ed bef or e forwar ded t o t he r ecei ve
CRC checking unit.
7DH (control-escape) and 7EH (flag) octets in the data stream are mapped in general.
The sequence of mappi ng cont rol logic is:
1. 7DH and 7EH octets,
2. ACCM0..3,
3. UDAC0..3.
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-95 08.99
This mechanism is applied to asynchronous HDLC PPP mode as well as to octet
synchr onous HDLC PPP mode.
•
Figure 4-8 PPP Mapping/Unmapping Example
A CCM0 . .3 : As
y
nc Control Character Map Re
g
ister
1F
0
00
0
3
1
131E
0
15
0
14
0
...
...
...
...
12
0
11
0
UDAC0..3: User Defined As
y
nc C ontrol C haracter Map R e
g
ister
7Eh 7Eh 7Eh
20h
13H20H01H02H
d a ta in
transmit
FIFO:
HDLC
framing: 13H20H01H02H
7EH7EH
33H00H01H02H
7EH7DH7DH7EH
PPP
mapping:
33H00H01H02H
7EH7DH7DH7EH
received
character:
13H20H01H02H
7EH7EH
PPP
unmapping
:
13H20H01H02H
d a ta in
receive
FIFO:
serial
line
Note: CRC
g
eneration/checkin
g
is assum ed to be disabled in this exam ple; accordin
g
the PPP m appin
g
/
unmappin
g
, C R C characters are tre ated as 'data' characte rs bein
g
m a pped/unmapp ed if nec ess ar
y
.
UDAC1 UDAC0
UDAC3 UDAC2 70070707
ACCM1 ACCM0ACCM3 ACCM2
70
070707
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-96 08.99
4.3 E xtended Transp arent Mode
Characteristics: full y transpar ent
When programmed in the extended transparent mode via the CCR2L register (bits
MDS1, MDS0, ADM = ‘111’), the SCC performs fully transparent data transmission and
reception without HDLC fram in g, i.e. without
• FLAG insertio n and deletion
• CRC generation and checking
• bit stuffing.
This feature can be profitably used e.g. for:
• user specif ic protocol vari ations
• line state monitoring, or
• test purposes, in particular for monitoring or intentionally generating HDLC protocol
rule violations (e.g. wrong CRC)
Character or octet boundary synchronization can be achieved by using clock mode 5 or
clock mode 1 with an extern al receive strobe input to pin CD.
4.4 Asynchronous (ASYNC) Protoc ol Mode
4.4. 1 Ch ar a cte r Fr amin g
Character framing is achieved by start and stop bits. Each data character i s preceded by
one Start bit and termin ated by one or two stop bits. The char acter length is selectable
from 5 up to 8 bits. Optionally, a parity bit can be added which complements the number
of ones to an even or odd quantity (even/odd parity). The parity bit can also be
programm ed to have a f ixed val ue (Mar k or Spa ce). The character forma t con figuration
is performed via appropriate bit fields in registers CCR3L/CCR3H. Figure 4-9 shows the
asynchronous charact er fo rmat.
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-97 08.99
Figure 4-9 Asynchronous Character Frame
4.4.2 Data Reception
The SCC offers the flexibility t o combine clock modes, data encoding and data sampling
in many different ways. However, only definite combinations make sense and are
recom m ended for correct operation:
4.4.2.1 Asynchronous Mode
Prerequisites:
• Bit clock rate 16 sele cted (register CCR0L, bit BCR = ‘1’)
• Clock mode 0, 1, 3b, 4, or 7b select ed (register CCR0L, bit field ’CM’)
• NRZ data encoding selected (register CCR0H, bit field ’SC’ )
T he rec eiver whi ch o pera tes wit h a clock rate equal to 16 times the nom ina l (expec ted)
data bit rate, synchronizes itself to each character by detecting and verifying the start bit.
Since character length, parity and stop bit length is known, the ensuing valid bits are
sampled. Oversampling (3 samples) around the nominal bit center in conjunction with
major ity decisi on is provided for every recei ved bit (includi ng start bit).
T he synchroniz ation l ast s f or one charac ter, the next inc om ing char act er causes a new
synchronization to be performed. As a result, the demand for high clock accuracy is
reduced. Two communication stations using the asynchronous procedure are clocked
independently, their clocks need not be in phase or locked to exactly the same frequency
but, in fact, may differ from one another within a certain range.
4.4.2.2 Isochronous Mode
Prerequisites:
• Bit clock rate 1 selec ted (regist er CCR0L bi t BC R = ‘0’)
D1 D2 D3 D4 D5 D6 D7 Parity
Par. Par. Par.
D0
(LSB)
1
Start
Bit
5 to 8 Data Bits
(6 to 9 Bits with Parity)
1 or 2
Stop
Bits
Char acter F rame
ITD01804
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-98 08.99
• Clock mode 2, 3a, 6, or 7a (DPLL mode) has to be used in conjunction with FM0, FM1
or Manch ester encoding (register CCR0L/CCR0H bit fields ’CM’ and ’SC’).
The isochronous mode uses the asynchronous character format. However, each data bit
is only sampled once (no oversa mpling).
In clock modes 0 ,1 and 4, the input cloc k has to be externa lly phase locked to the data
stream. This mode allows much highe r transfer rates. Clock modes 3b and 7b are no t
recommended due to difficulties with bit synchronization when using the internal baud
rate generator.
In clock modes 2, 3a, 6, and 7a, clock recovery is provided by the internal DPLL. Correct
synchronization of the DPLL is achieved if there are enough edges within the data
stream, which is generally ensured only if Bi-Phase encoding (FM0, FM1 or Manchester)
is used.
4.4.2.3 Storage of Receive Data
If the re ceiver is enabled, received data is stored in the SCC receive FIFO (the LSB is
received first). Moreover, the CD input may be used to control data reception. Character
length, number of stop bits and the optional parity bit are checked. Storage of parity bits
can be disabled. Errors are indicated via interrupts. Additionally, the character specific
error status (framing and parity) can optionally be stored in the SCC receive FIFO.
Filling of the the SCC receive FIFO is controlled by
• a programm abl e threshold lev el (bit field ’RFTH’ in register CCR3H),
• the selecte d data format (bit ’RFDF’ in register CCR3H),
• the parity storage select ion (bit ’DPS’ in register CCR3H),
• detecti on of the programmabl e Termination Cha racter (bit ’TCDE’ in register CCR3L
and bit field ’TC’ in register TCR).
Additionally, the time-out event interrupt as an optional status information indicates that
a certain time (refer to register TOLEN) has elapsed since the reception of the last
character.
4.4.3 Data Transmission
The selection of asynchronous or isochronous operation has no further influence on the
transmitter. The bit clock rate is solely a dividing factor for the selected clock source.
Transmission of the contents of the SCC transmit FIFO starts after the ’XF’ command is
issued (the LSB is sent out first). Fur ther data is requested by an ’XPR ’ inter rupt (or by
DMA). The character frame for each character, consisting of start bit, the character itself
with defined character length, optionally generated parity bit and stop bit(s) is
assembled.
After finishing transmission (indicated by the ‘ALLS’ interrupt), IDLE sequence (logical
‘1’) is transmitted on pin TxD.
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-99 08.99
Additional ly, the CTS signal may be used to control data transmission.
4.4.4 Spe cial Functions
4.4.4.1 Break Detection/Gene ration
Break gener ation:
On issuing the transmit break comma nd (bit ’XBRK’ in reg ister CCR3L), t he TxD pi n is
imme diately fo rced to physica l ‘0’ level with the next f ollowing t ransmit clock edge, and
released with the first transmit clock edge after this command is reset again by software.
Break dete ction:
The SCC recognizes the break condition upon receiving c onsecutive (physical) ‘0’s for
the defined character length, the optional parity and the selected number of stop bits
(‘zero’ character and framing error). The ‘zero’ character is not pushed to RFIFO. If
enabled, the ’Break’ interrupt (BRK) is generated.
The break condition will be present until a ‘1’ is received which is indicated by the ‘Break
Termina te d’ interru pt (BRK T ).
4.4.4.2 In-band Flow Control by XON/XOFF Characters
Programmable XON and XOFF characters:
The XON/XOFF registers contain the programmable values for XON and XOFF
characters. The number of significant bits in a register is determined by the programmed
chara cter length via bit field ’CHL’ in register CCR3L.
Additionally, two programmable eight-bit values in registers MXON and MXOFF serve
as masks for the characters XON and XOFF, respectively:
A ‘1’ in any mask bit position has the effect that no comparison is performed between the
correspon ding bi ts in the re ceived charac ters (‘don’t c ares’) and the XON/XOFF value.
At RESET, the masks are zero’ed, i.e. all bit posit ions will be com pare d.
A received character is considered to be recognized as a valid XON or XOFF character
– if it is correctly framed (correct length),
– if its bits match the ones in the XON or XOFF registers over the programmed character
length,
– if it has correct pa rity (if applicab le).
Rec eived XON and XOFF chara cters are stored in the SCC receive FIFO, as any other
characters, when bit ’DXS’ is set to ’0’ in register CCR3L. Otherwise they are not stored
in the rece iv e FIFO.
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-100 08.99
In-Band Flow Control of Transmitted Characters:
Recognition of an XON or XOFF character causes always a corresponding maskable
interrupt status to be generated.
Further action depends on the setting of control bit ’FLON’ (Flow Control On) in register
CCR2H:
0: No furth er actio n is automatically taken by the SCC.
1: The reception of an XOFF character automatically turns off the transmitter after the
currently transmitted character (if any) has been shifted out completely (entering
XOFF state). The reception of an XON character automatically makes the transmitter
resum e transm itting (enteri ng XON state).
After hardware RESET, bit CCR2H:FLON is ‘0’.
When bit CCR2H:FLON is programmed from ‘0’ to ‘1’, the transmitter is first in the
‘XON state’, until an XOFF character is received.
When bit CCR2H:FLON is programmed from ‘1’ to ‘0’, the transmitter always goes in the
‘XON state’, and transmission is only controlled by the user and by the CTS signal input.
The in-band flow control of the transmitter via received XO N and XOFF c haracters can
be combined with control via CTS pin, i.e. the effect of the CTS pin is independent of
whether in-band control is used or not. The transmitter is enabled only if CTS is ‘low’ and
XON state has been reached.
Transmitter Status Bit:
The status bit ‘Flow Control Status’ (bit ’FCS’ in register STARL) indicates the current
state of the transmitter, as follows:
0: if the transm itter is in XON state,
1: if the transm itter is in XOFF state.
Note: The transmitter can not be t urned off by soft wa re withou t disru pting data poss ibly
remaining in the transmit FIFO.
Flow Control for R ecei ved Data :
After writing a character value to register TICR (Transmit Immediate Character, ’TIC’) its
character contents is inserted into the outgoing character stream
• immediately upon writing this register by the microprocessor if the transmitter is in
IDLE state. If no further characters (transmit FIFO empty) are to be transmitted, i.e.
the transmitter returns to IDLE state after transmission of the ’TIC’ and an ALLS (All
Sent) interrupt will be generated.
• after the end of a character currently being transmitted if the transmitter is not in I DLE
state. This does not affect the contents of the transmit FIFO. Transmission of
character s from transm it FIFO is resumed after the ’TIC’ is send out.
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-101 08.99
Transmission via this register is possible even when the transmitter is in XOFF state
(however, CTS must be ‘low’).
T he ’TIC’ value is an ei ght -b it value. The number of significant bits is determined by the
programme d asynch character length via bit field ’CHL’ in registe r CCR3L. Parity value
(if programmed) and selected number of stop bits are automatically appended, equal to
the characters provided via t he transmit data buffer. The u sage o f ’TIC’ is indep endent
of in-band flow co ntrol m echanism, i. e. is no t affected by bit ’FL ON’ in regi ster CCR2H
anyway.
To control multiple accesses to register TICR, an additional status bit STARL:TEC (TIC
Executing) is provided which signals that the transmission command of currently
programmed ’TIC’ is accepted but not yet completely executed. Further access to
register TICR is only allowed if bit STARL:TEC is ‘0’ a gain.
4.4.4.3 Out-of-band Flow Control
Transmitter:
T he transm itter output is enabl ed if CTS signal is ‘LOW’ AND the XON state is reach ed
in case of in-band flow control is enabled. If the in-band flow control is disabled
(CCR2H:FLON = ‘0’), the transmitter is only controlled by the CTS signal.
Nevertheless setting bit CCR1H:FCTS = ‘1’ allows the transmitter to send data
independent of the condition of the CTS signal, the in-band flow control (XON/XOFF)
mec hani sm would still be operational if enabled via bit CCR2H:FLON = ‘1 ’.
Receiver:
For some applications it is desirable to provide means of out-of-band flow control to
indicat e to the far end transmitter that the local receiver ’s buffer is getting full.
This flow control can be used between two DTEs as shown in Figure 4-10 and between
a DTE and a DCE (MODEM) as shown in Figure 4-11 that supports this kind of bi-
dir ect ion al flow control.
Setting bit CCR1H:FRTS = ‘1’ and CCR1H:RTS = ‘0’ invokes this out-of-band flow
control for the receiver. When the shadow part of the receive FIFO has reached a set
threshold of 28 bytes, the RTS signal is forced inactive (high). When the shadow part of
the receive FIFO is empty, the RTS is re-asserted (low). Note that the data is
immediately transferred from the shadow receive FIFO to the user accessible RFIFO (as
long as there is space available). So when the shadow receive FIFO reaches the 28
byte s threshold, there is 4 more byte s torage ava il able before ove rflow can o ccur. This
allows sufficient time for the far end transmitter to react to the change in the RTS signal
and stop sending more data.
Figure 4-10 shows the connection between two SCC devices as DTEs. The RTS of
DTE-A (SCC) feeds the CTS input of the second DTE-B (another SCC). For example
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-102 08.99
while DTE-A is receiving data and its receive FIFO t hreshold is reached, the RTS signal
goes in-active ’HIGH’ forcing the CTS of DTE-B to become in-active indicating that
transmissi on has to stop af ter f inish ing th e cur re nt char act er. Both D TE devices should
also be using the CTS signal to flow control their transmitters. When the shadow receive
FIFO in DTE-A is cleared its RTS goes activ e (low) and this signals t he far end D TE-B
to resume transmission. Data flow control from DTE-B to DTE-A works in the same way.
Figure 4-10 Out-of-Band DTE-DTE Bi-directional Flow Cont rol
ITS08517
TxD
RxD
CTS
RTS RTS
CTS
RxD
TxD
RS232c Signals
(drivers not shown)
DTE ABDTE
MISTRAL
MISTRAL
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-103 08.99
Figure 4-11 shows an SCC as a DTE connect ed to a DCE (MODEM equipm ent).
The RTSA feeds the RTSB input of the DCE (MODEM equipment) that supports bi-
directional flow control. So when the DTE-A’s receiver threshold is reached, the RTSA
signal goes inactive ’HIGH’ which is sensed by the DCE and it stops transmitting.
Similarly if the DCE’s receiver threshold is reached, it deactivates the CTSB (’HIGH’) and
causes the DT E to stop transmi ssion. These types of DCEs have fairly dee p buffers to
ensure that it can continue to receive data from the line even though it is unable to pass
the data to t he DTE for shor t periods of time. N ote that a SC C can also be use d in t he
DCE equi pm ent as shown. Exchange of signal s (e.g. RTS to CTS) is necessarily inside
the DC E equipment .
Figure 4-11 Out-of-Band DTE-DCE Bi-directional Flow Control
RTS and CTS are used to indicate when the local receiver’s buffer is nearly full. This
alerts the far end transmitter to stop transmission.
The combination of transmitter and receiver out-of-band control features mentioned
above enables data to be exchanged between two devices without software intervention
for flow control.
4.5 BI SYNC Protoc ol Mode
4.5.1 Character Fram ing
Character oriented protocols achieve synchronization between transmitting and
receiving station by means of special SYN characters. Two examples are the
MONOSYNC and IBM’s BISYNC procedures. BISYNC has two starting SYN characters
TxD
RxD
CTS
RTS RTS
CTS
RxD
TxD
RS232c Signals
(drivers not shown)
DTE A BDCE MODEM1)
RTS
CTS
RxD
TxD
1) Some MODEMs support bi-directional flow control.
MISTRAL MISTRAL
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-104 08.99
while MON OSYNC uses onl y one SYN . Figure 4- 12 g ive s an exampl e of the m essage
format.
Figure 4-12 BISYNC Message Format
The SYN character, its length, the length of data characters and additional parity
generation are progr am mab le:
• 1 SYN character with 6 or 8 bit length (MONOSYNC), programmable via register
SYNCL.
• 2 SYN characters with 6 or 8 bit length each (BISYNC), programmable v ia registers
SYNCH/SYNCL.
• Data charac ter length may vary from 5 to 8 bi t s (bit field ’CHL’ in register CCR3L).
• Parity info rmation (even/odd parity, mark, sp ace) may be appe nded to the char acter
(bit ’PARE’ and bit field ’PAR’ in register CCR3H).
4.5.2 Data Reception
The receiver is g enerally activated by s etting bit ’R AC’ in register CCR3L. Additionally,
the CD signal may be used to control data reception depending on the selected clock
mode. After issuing the HUNT command, the receiver monitors the incoming data
stream for the presence of specified SYN character(s). However, d ata reception is s till
disabled. If synchronization is gained by detecting the SYN character(s), an SCD
interrupt is generated and all following data is pushed to the receive FIFO, i.e. control
sequences, data characters and optional CRC frame checking sequence (the LSB is
received first). In normal operation, SYN characters are excluded from storage to receive
FIFO. SYN character length can be specified independently of the selected data
character length. If required, the character parity bit and/or parity status is stored
together with each data byte in the receive FIFO.
As an option, the loading of SYN characters in receive FIF O may be enabled by set ting
the bit ’ SLO AD’ in re gist er CCR3L. Note that in this case SYN characters are treated as
data. Consequently, for correct operation it must be guaranteed that SYN character
SYN
(SYNL) (SYNH)
SYN SOH Header STX Text ETX CRC(Data)
2 Leading
SYN
Characters
Start
of
Header Text
of
Start End
of
Text
Frame
Checking
Sequence
ITD01805
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-105 08.99
length equals the character length + optional parity bit. This is the use r’s responsibility
by appropriate software settings.
F illing of the receive FIFO is controlled by a programmabl e th resho ld level.
Rec ept ion is stopped if
1. the receiver is deactivated by resetting the bit CCR3L:RAC bit, or
2. the CD signal goes inactive (if Carrier Detect Auto Start is enabled in register CCR1H),
or
3. the CMDRH:HUNT command is issued again, or
4. the Receiver Reset command (CMDRH:RRES) is issued, or
5. a programmed Termination Character has been found (optional).
On actions 1. and 2., reception remains disabled until the receiver is activated again.
After this is done, and generally in cases 3. and 4., the receiver returns to the (non-
synchronized) Hunt state. In case 5. a HUNT comman d has to be issued. Reception of
data is internally disabled unt il synchroni zat ion is regaine d.
Note: Further checking of frame length, extraction of text or data information and
verifying the Frame Checking Sequence (e.g. CRC) has to be done by the
microprocessor.
4. 5 .3 D a ta Tr an smis sio n
T ransmi ssion of data provided in the memory is started af ter the Trans mit Fra me (’XF’)
command is issued (the LSB is sent out first). Additionally, the CTS signal may be used
to control data transmission. The message frame is assembled by appending all data
characters to the specified SYN character(s) until Transmit Message End condition is
detected (’XME’ command in interrupt mode or, in DMA mode, when the number of
characters specified in XBC1L/XBC1H have been transferred). Internally generated
parity information may be added to each character (SYN, CRC and Preamble characters
are excl uded).
If enabled via CRC Appe nd bit (bit ’CAPP’ in register CCR2H) , the internal ly cal culated
CRC checksum (16 bit) is added to the message frame. Selection between CRC-16 and
CRC-CCITT algorithms is provided.
Note: - In ternally generated SYN characters are always excluded from CRC calculat ion,
- CRC checksum (2 bytes) is sen t without p arity.
The internal CRC generator is automatically initialized before transmission of a new
frame starts. The initialization val ue is selec table.
After finishing data transmission, interframe-time-fill (SYN characters or IDLE) is
au to mati cally sen t.
A transmit data underrun condition in the XFIFO is indicated with an ’XDU’ interrupt.
Nevertheless, transmission continues inserting SYN characters into the data stream until
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-106 08.99
new data i s available in t he transm it FIFO. Inserte d SYN characters are not par t of the
fra me a nd th u s not used fo r CRC calc u la tion.
4.5.4 Special Functions
4.5.4.1 Preamble Transmission
If enabled via register CCR2H, a programmable 8-bit pattern (register PREAMB) is
transmitted with a selectable number of repetitions after interframe-time-fill transmission
is stopped and a new frame is ready to be sent out.
Note: If the preamble pattern equals the SYN pattern, reception is triggered by the
preamble.
4.6 Procedural Support (Layer-2 Functions)
When operating i n t he auto m ode, t he SCC offers a high degr ee of protocol support. In
addition to address recognition, the SCC autonomously processes all (numbered) S- and
I-frames (window size 1 only) with either normal or extended control field format
(modulo-8 or modulo-128 sequence numbers – selectable via register CCR2H bit
’MCS’).
The following functio ns will be performe d:
– updating of transmit and receive counter
– evaluation of trans mit and receive count er
– processing of S commands
– flow control with RR/RNR
– generation of responses
– recognition of protocol errors
– transmission of S commands, if acknowledgement is not received
– continuous status query of remote station after RNR has been received
– programmabl e tim er/repe ate r functions.
In addition, al l unnumbere d frames are f orwarded dir ectly to the proces sor. The log ical
link can be initialized by software at any t ime (Reset HDLC Rec eiver by R RES command
in register CMDRH).
Additional logical connections can be operated in parallel by software .
4.6.1 Full-Duplex LAPB/LAPD Operation
Initially (i.e. after RESET), the LAP controllers of the two serial channels are configured
to function as a combined (primary/secondary) station, where they autonomously
perform a subset of the balanced X.25 LAPB/IS DN LAPD protocol.
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-107 08.99
Reception of Frames:
The logical processing of received S-frames is performed by the SCC without
interrupting the host. The host is merely informed by interrupt of status changes in the
remote station (receiver ready / receiver not ready) and protocol errors (unacceptable
N(R), or S-frame with I-field).
I-frames are also processed autonomously and checked for protocol errors. The I-frame
will not be accepted in the case of sequence errors (no inter rupt is forwarded to t he host),
but is im med iatel y confi rmed by an S-response. If the host set s the SC C into a ‘re ceive
not ready’ status, an I-fr ame will not be accepted (no int errupt) and an RNR response is
transmitted. U-frames are always stored in the RFIFO and forwarded directly to the host.
T he logi cal sequence and the r ecept io n of a frame i n auto m ode i s ill ustrated in Figure
4-13.
Note: The state variables N(S), N(R) are evaluated within the window size 1, i.e. the
SCC checks only the least significant bit of the receive and transmit counter
regar dless of the sele cted modulo count .
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-108 08.99
Figure 4-13 Pr ocessing of Recei ved Frames in Auto Mode
ITD00230
Command
with p=1
?
Y
?
Ready
Rec. N
f=p
Trm RR
ActivRec.
Set RRNR
Response
PCE
Int :
1
Response
Trm RNR
f=p
?
Overflow
Data
N
:Int RME
Set RDO
Response
Trm RR
f=p
RMEInt:
N
Y
Y
N
=V
Y
N(S) (R)+1
Rec. Ready :Int RME
N
Set RDO
Data
Overflow
?
N
Y
ALLSInt :
Acknowledge
RESET Wait for
+1
(S)=Y
=VN(R) (S)+1
Y
?
Acknowledge
Wait for
N
Y
:Int XMR
RESET Wait for
Acknowledge
Acknowledge
RESET Wait for
ALLSInt :
Response
f=1
?
N
(S)+1N(R)=V
N
Y
Wait for
Acknowledge
?
NN
Y
?
CRC Error
Set CRCE
N
N
Set RAB
Aborted
?
Y
U Frame
1
YProt. Error
?
N
PCEInt:
:Int RME
Set CRCE N
?
CRC Error
Y
Set RAB
Aborted
?N
Y
I Frame
N
1
YProt. Error
?
N
or Abort
CRC Err or
Y
RNR
?
1
RESET RRNR
?
,
YCRC Error
or Abort
N
?
Prot. Err or
Y
N
:Int PCE
SREJREJRR,
1
Y
(R)+1(R)=VV
V(S)
V
V(S)
V=
(S) +1 Y
??
ALLS:Int
?
?
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-109 08.99
T ransmis sion of Frames:
The SCC autonomously transmits S commands and S responses in the auto mode.
Either transparent or I-frames can be transmitted by the user. The software timer has to
be operated in the internal timer mode to transmit I-frames. After the frame has been
transmitted, the timer is self-started, the XFIFO is inhibited, and the SCC waits for the
arrival of a positive acknowledgement. This acknowledgement can be provided by
mean s of an S- or I-frame.
If no positive acknowledgement is received during time t1, the SCC transmits an S-
command (p = ‘1’), which must be answered by an S-response (f = ‘1’). If the S-response
is not received, the process is performed n1 times (in HDLC known as N2, refer to
register TIMR3).
Upon the arrival of an acknowledgement or after the completion of this poll procedure
the XFIFO is enabled and an interrupt is generated. Interrupts may be triggered by the
following:
• message has been positively acknowledged (ALLS interrupt)
• message must be repeated (XMR interrupt)
• response has not been received (TI N interrupt).
In automode, only when the ALLS interrupt has been issued data of a new frame may
be provided to the XFIFO!
Upon arriv al o f an RNR frame, the so ftware timer is sta rted a nd the st a tu s o f the remote
station is polled periodically after expiration of t1, until the status ‘receive ready’ has been
detected. The user is informed via the appropriate interrupt. If no response is received
after n1 times, a TIN interrupt, and t1 clock periods thereafter an ALLS interrupt is
generated and the process is terminated.
Note: The interna l timer mode should onl y be used in the auto mode.
T ransp aren t frames can be transm itted in all operating modes.
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-110 08.99
Figure 4-14 Timer Procedure/Poll Cycle
ITD00231
Wait for
Acknowledge
Set
?
?
2
?
with f=1
Response
Wait for
Acknowledge
?
RRNR
N
NN
Y Y
N
2
YY
=?
(R) (S)+1VN
Y
N
1tLoad
Rec.RNRRec.RRIRec. Frame
T Proc.Act iv
TINInt:
1
Load t1
Y
?
Ready
Rec. N
Command p=1
Trm RR
,,
Trm RNR
Command p=1
n1 n1-1=
N
?
Y
Y
?
N
n1= 7
n1= 0
Run Out
1 2
2
Load t1
Trm RR/RNR
CMDR ; STI
Command p=1
Trm I Frame
Acknowledge
Set wait for
InactivT Proc. 1
RNR
Set RRNR
Rec.
1t
Load n1
Load n1
11.06.1996 B/R
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-111 08.99
Examples
The interaction between SCC and the host during transmission and reception of I-frames
is il lustrated in the following two figures. The flow control with RR/RNR of I-frames during
transmission/reception is illustrated in Fi gure 4-15. Both, the sequence of the poll cycle
and protocol errors are show n in Figure 4-16.
F igure 4-15 Transm ission/R eception of I-Frames and Flow Control
Figure 4-16 Flow Control: Reception of S-Commands and Protocol Er rors
RME
RME
WFA
Transmit with
FrameI
Confirm I Frame
ALLS
ALLS WFA
Reception FrameI
Transmit FrameI
RR(1)
(0.0)
I
RR(1)
I(0.1)
(1.1)
I
(1.2)
I
RR(2)
RR(0)f=1
RNR
RSC
(RNR)
RSC
(RR)
XMR
WFA
t1
t1 RR(0)p=1
RNR(0)f=1
RNR(0)
I(0.0)
RR(0)p=1
ALLS
WFA = Wait For Acknowledge (see Status Register)
RNR
RME
XRNR
RNR(0)
RR
(0.0)
I
RR(0)p=1
RR(0)f=1
RR(0)p=1
RR(0)f=1
I(0.0)
RR(1)
t1
t1
t1
RRp=1
Poll Cycle
Protocol Erro r
I
RR(0)p=1
RR(1)
RR(2)
ALLS
PCE
TIN
WFA
ALLS
RR(0)
WFA
RRp=1
(0.0)
WFA = Wait For Acknowledge (see Status Register)
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-112 08.99
Protocol Err or Handling:
Depending on the error type, erroneous frames are handled according to Table 4-3.
Note: The s tation variabl es ( V(S), V(R) ) are not changed.
4.6.2 Half-Duplex SDLC-NRM Operation
The LAP controllers of the two serial channels can be configured to function in a half-
duplex Normal Response Mode (NRM), where they operate as a slave (secondary)
station, by setting the NRM bit in the CCR2L register of the correspondi ng channel.
In contrast to the full-duplex LAP B/LAP D operation, where the combined
(primary + secondary) station transmits both commands and responses and may
transmi t data at an y time, the NRM mode al lows only r esponses t o be transm itted and
the secondary station may transmit only when instructed to do so by the master (primary)
station. The SCC gets the permission to transmit from the primary station via an S- , or I-
frame with the poll bit (p) set.
The NRM mode can be profitably used in a point-to-m ultipoin t configuratio n with a f i xed
master-slave relationship, which guarantees the absence of collisions on the common
transmit line. It is the responsibility of the master station to poll the slaves periodically
and to handle error situation s.
Prerequisite for NRM oper ation is:
– aut o mo de with 8-bit address field sel ected
Regist er CCR2L bit fields ’MDS1’, ’MDS0’, ’ADM’ = ‘000’
– Register TIMR3 bit ’T MD’ = ‘0 ’
– sam e transm i t and recei ve addre sses, since only respons es can be transm itt ed, i.e.
Regist er XAD1 = XAD2 and register RAL1 = RAL2 ( addre ss of sec ondar y).
Table 4-3 Error Handling
Frame Type Error Type Generated
Response Generated
Interrupt Rec. Status
I CRC erro r
Aborted
Unexpected N(S)
Unexpected N(R)
–
–
S-frame
–
RME
RME
–
PCE
CRC erro r
Abort
–
–
S CRC erro r
Aborted
Unexpected N(R)
With I-field
–
–
–
–
–
–
PCE
PCE
–
–
–
–
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-113 08.99
Note: The broadcast address may be programmed in register RAL2 if broadcasting is
required.
In this case register s RAL1 and RAL2 are not equal.
T he primary st ation has to operate in transp arent HDL C mode.
Reception of Frames:
The reception of frames functions similarly to the LAPB/LAPD operation (see "Full-
Duplex LAPB/LAPD Operation" on page 4-106).
T ransmi ssion of Frame s:
The SCC does not transmit S-, or I-frames if not instructed to do so by the primary station
via an S-, or I-frame with the poll bit set.
T he SCC can be to ld to send an I- frame i ssuing the t ra nsm it command ’ XIF’ in r egi ster
CMDRL. The transmission of the frame, however, will not be initiated by the SCC until
recep tion of either an
• RR, or
• I-frame
with pol l bi t set (p = ‘1’).
After the frame has been transmitted (with the final bit set), the host has to wait for an
ALLS or XMR interrupt.
A secondary does not poll the primary for acknowledgements, thus timer supervision
mus t be done by the primary station.
Upon the arrival of an acknowledgement the SCC transmit FIFO is enabled and an
interrupt is forwarded to the host, either the
– message has been positively acknowledged (ALLS interrupt), or the
– message must be repeated (XMR interrupt).
Additionally, the on-chip timer can be used under host control to provide timer recovery
of the secondar y if no acknowl edgem ent s are recei ved at all.
Note: A secondary will transmit transparent frames only if the permission to send is
given by receiving an S-frame or I-frame with poll bit set (p = ‘1’).
Examples:
A few examples of SCC/host interaction in the case of normal response mode (NRM)
mode are shown in Figure 4-17 and Figure 4-18.
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-114 08.99
Figure 4-17 No Data to Send: Data Reception/Transmission
Figure 4-18 Dat a Transmi ssio n (without error), Data Transmission (with error)
4.6.3 Signaling System #7 (SS7) Operation
The MISTRAL supports the signaling system #7 (SS7) w hich is described in ITU-Q.703.
SS7 support must be activated by setting bit ’ESS7’ in register CCR3L.
RR(0)f=1
RR(0)p=1
Secondary Primary
ITD01800
(0,1)f=1
(0,0 )p = 1
ITD00237
(1,1 )p = 1
RR(2)f=1
ALLS
RME
XIF I
I
I
(0,0)f=1
RR(0)p=1
ITD00238
RR(1)p=0
ALLS
XIF
I (0,0)f=1
RR(0)p=1
ITD01801
RR(0)p=1
XMR
XIF
I
RR(0)f=1
t
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-115 08.99
Receive
The SS7 protocol is supported by the following hardware features in receive direction:
• Recognit ion of Signaling U nit type
• Discard of repeatedly received FISUs and LSSUs if content is unchanged (optional)
• Check if the length of the received signaling unit is at least six octets (including the
opening flag)
• Check if the signal information field of a r ecei ved signal in g unit consists of more than
272 octets (enabled with bit CCR3L.ELC). In this case, reception of the current
signaling unit will be aborted.
• Counting and processing of errored signaling units
In order to reduce the microprocessor load, Fill In Signaling Units (FISUs) are processed
automatically. By examining the length indicator of a received Signal Unit (SU) MISTRAL
decides whether a FISU has been received. Consecutively received FISUs will be
compared and optionally not stored in the RFIFO, if the content is equal to the previous
one. The same applies to Link Status Signaling Units (LSSUs), if enabled with bit
CCR3L.CSF. The different types of Signaling Units as Messag e Signa ling Unit (MSU),
Link Status Signaling Unit (LSSU) and Fill-In Signaling Units (FISU) are indicated in the
RSTA byte (bit f ield ’SU’), which is automatically added to the RFIFO with each received
Signaling Unit. The complete Signaling Unit exce pt sta rt and end flags is stored in the
receive FI FO. The functions of bi ts CCR3H.RCRC and CCR3H.RADD are also valid in
SS7 mode, with bit ’RADD’ related to BSN (backward sequence number) and FSN
(forward sequence number).
Errored signaling units are counted and processed according to ITU-T Q.703. The SU
counter and errored-SU counter are reset by setting CMDRH.RSUC to ’1’. The error
threshol d can be sel ected t o be 6 4 (default) or 32 by cl ear ing /se tting bi t CCR3L.SUET.
If the defined error limit is exceeded, an interrupt (ISR1.SUEX) is generated, if not
mas ked by bit IMR1.SUEX.
Transmit
In transmi t direction, following featur es are supp orted:
• single or repetitive transmi ssion of signal ing units
• automatic gener ation of Fill-In Signaling Units (FISU)
Each Signaling Unit (SU) written to the transmit FIFO (XFIFO) will be sent once or
repeatedly including flags, CRC checksum and stuffed bits. After e.g. an MSU has been
transmitted completely, MISTRAL optionally starts sending of Fill In Signaling Units
(FISUs) containing the forward sequence number (FSN) and the backward sequence
numb er (BSN) of the previously transm i tted signal ing unit. Setting bit CCR3L.AFX to ’1’
causes FISUs to be sent continuously if no Signaling Unit is to be transmitted from
XFIFO. After a new signaling unit has been written to the XFIFO and a transmission has
been initiated, the current FISU is completed and the new SU is sent. After this,
PEB 20542
PEF 20542
Detailed Protocol Description
Preliminary Data Sheet 4-116 08.99
transmission of FISUs continues. The internally generated FISUs contain FSN and BSN
of the l ast transm i tted signaling unit written to XFIFO.
Usin g CMDRL. XREP=’1’, the contents of XFIFO (1..32 bytes) can be sent continuously.
This cyclic trans missi on can be stopped w ith the CMDRL.X RES com man d.
PEB 20542
PEF 20542
Regist er Descript ion
Preliminary Data Sheet 5-117 08.99
5 Register Description
5.1 Register Overview
The MISTRAL global registers are used to configure and control the Serial
Communication Controllers (SCCs), General Purpose Pins (GPP) and DMA operation.
All regist ers are 8-bit organized regist ers, but grouped and optimi zed for 16 bit access.
16 bit access is supported to even addresses only.
T able 5-1 provides an overvi ew about all on-chip registers :
T able 5-1 Registe r Overview
Offset
Ch A Ch B Register
read write Res
Val Meaning Page
Global registers:
00HGCMDR 00HGlobal Command Register 5-123
01HGMODE 0FHGlobal Mode Register 5-124
02HDBSR 00HDMA Buffer Status Register 5-127
03HGSTAR 00HGlobal Status Register 5-128
04H
Reserved
05HGPDIR FFHGPP Direction Register 5-130
06H
Reserved
07HGPDAT 00HG PP Data Regist er 5-131
08H
Reserved
09HGPIM FFHGPP Int er rupt Mask Register 5-132
0AH
Reserved
0BHGPIS 00HGPP Interrupt Status R egister 5-133
0CHDCMDR 00HDMA Command Register 5-134
0DHDMODE 00HDMA Mode Register 5-136
0EHDISR 00HDMA Interrupt Status Register 5-137
0FHDIMR 77HDMA Interrupt Mask Register 5-138
Cha nnel specific registers:
10H60HRFIFO XFIFO -Rec eive/Transm it FIFO (Low Byte) 5-139
11H61H-Rec eive/Transm i t FIFO (High Byte) 5-139
PEB 20542
PEF 20542
Regist er Descript ion
Preliminary Data Sheet 5-118 08.99
12H62HSTARL 00HStatus Registe r (Low Byte) 5-141
13H63HSTARH 10HStatus Register (High Byte) 5-141
14H64HCMDRL 00HCommand R egist er (Low Byte) 5-146
15H65HCMDRH 00HCo mmand R egist er (High Byte ) 5-146
16H66HCCR0L 00HChannel Configur ation Regi ste r 0 (Low
Byte) 5-151
17H67HCCR0H 00HChannel Configur ation Regi ste r 0 (High
Byte) 5-151
18H68HCCR1L 00HChannel Configur ation Regi ste r 1 (Low
Byte) 5-155
19H69HCCR1H 00HChannel Configur ation Regi ste r 1 (High
Byte) 5-155
1AH6AHCCR2L 00HChannel Con figur ation Regi ster 2 (Low
Byte) 5-160
1BH6BHCCR2H 00HChannel Con figur ation Regi ster 2 (High
Byte) 5-160
1CH6CHCCR3L 00HChannel Configur ation Regi ste r 3 (Low
Byte) 5-167
1DH6DHCCR3H 00HChannel Configur ation Regi ste r 3 (High
Byte) 5-167
1EH6EHPREAMB 00HPreamble Re gister 5-175
1FH6FHTOLEN 00HTime Out Length R egister 5-176
20H70HACCM0 00HPPP ASYNC Control Character Map 0 5-177
21H71HACCM1 00HPPP ASYNC Control Character Map 1 5-177
22H72HACCM2 00HPPP ASYNC Control Character Map2 5-178
23H73HACCM3 00HPPP ASYNC Control Character Map 3 5-178
24H74HUDAC0 7EHUser Defi ned PPP ASYNC Control
Character Map 0 5-180
25H75HUDAC1 7EHUser Defi ned PPP ASYNC Control
Character Map 1 5-180
26H76HUDAC2 7EHUser Defi ned PPP ASYNC Control
Character Map 2 5-181
Table 5-1 Regi st er Overview (cont’d)
Offset
Ch A Ch B Register
read write Res
Val Meaning Page
PEB 20542
PEF 20542
Regist er Descript ion
Preliminary Data Sheet 5-119 08.99
27H77HUDAC3 7EHUse r Defined PPP ASYNC Control
Cha racter Map 3 5-181
28H78HTTSA0 00HTransmit Time Slot Assignment Register 0 5-183
29H79HTTSA1 00HTransmit Time Slot Assignment Register 1 5-183
2AH7AHTTSA2 00HTransmit Time Slot Assignment Register 2 5-184
2BH7BHTTSA3 00HTransmit Time Slot Assignment Register 3 5-184
2CH7CHRTSA0 00HReceive Time Slot Assignment Register 0 5-186
2DH7DHRTSA1 00HReceive Time Slot Assignment Register 1 5-186
2EH7EHRTSA2 00HReceive Time Slot Assignment Register 2 5-187
2FH7FHRTSA3 00HReceive Time Slot Assignment Register 3 5-187
30H80HPCMTX0 00HPCM Mask Tra n s mit Di re c tion Regis te r 0 5-189
31H81HPCMTX1 00HPCM Mask Tra n s mit Di re c tion Regis te r 1 5-189
32H82HPCMTX2 00HPCM Mask Tra n s mit Di re c tion Regis te r 2 5-190
33H83HPCMTX3 00HPCM Mask Tra n s mit Di re c tion Regis te r 3 5-190
34H84HPCMRX0 00HPCM Mask Receive Direction Register 0 5-192
35H85HPCMRX1 00HPCM Mask Receive Direction Register 1 5-192
36H86HPCMRX2 00HPCM Mask Receive Direction Register 2 5-193
37H87HPCMRX3 00HPCM Mask Receive Direction Register 3 5-193
38H88HBRRL 00HBaud Rate Register (Low Byte) 5-195
39H89HBRRH 00HBau d Rate Register (High Byte) 5-195
3AH8AHTIMR0 00HTim er Registe r 0 5-197
3BH8BHTIMR1 00HTim er Registe r 1 5-197
3CH8CHTIMR2 00HTim er Regi ste r 2 5-198
3DH8DHTIMR3 00HTim er Regi ste r 3 5-198
3EH8EHXAD1 00HTransmit Address 1 Register 5-201
3FH8FHXAD2 00HTransmit Address 2 Register 5-201
40H90HRAL1 00HR eceive Address 1 Low Register 5-203
41H91HRAH1 00HReceive Address 1 High Register 5-203
42H92HRAL2 00HR eceive Address 2 Low Register 5-204
43H93HRAH2 00HReceive Address 2 High Register 5-204
T able 5-1 Registe r Overvi ew (cont’d)
Offset
Ch A Ch B Register
read write Res
Val Meaning Page
PEB 20542
PEF 20542
Regist er Descript ion
Preliminary Data Sheet 5-120 08.99
44H94HAMRAL1 00HMask Receive Address 1 Low Register 5-206
45H95HAMRAH1 00HMask Receive Address 1 High Register 5-206
46H95HAMRAL2 00HMask Receive Address 2 Low Register 5-207
47H96HAMRAH2 00HMask Receive Address 2 High Register 5-207
48H98HRLCRL 00HReceive Length Che ck Re gister (Low
Byte) 5-209
49H99HRLCRH 00HReceive Length Che ck Re gister (Hig h
Byte) 5-209
4AH9AHXON 00HXON In-Band Flow Control Characte r
Register 5-211
4BH9BHXOFF 00HXOFF In-Band Flow Control Character
Register 5-211
4CH9CHMXON 00HXON In-Band Flow Contro l Mask Regis ter 5-213
4DH9DHMXOFF 00HXOFF In-Band Flow Control Mask
Register 5-213
4EH9EHTCR 00HTermination C har acter Regi ster 5-215
4FH9FHTICR 00HTransmit Immediate Character Register 5-216
50HA0HISR0 00HInterrupt Status Register 0 5-218
51HA1HISR1 00HInterrupt Status Register 1 5-218
52HA2HISR2 00HInterrupt Status Register 2 5-219
53HA3HReserved
54HA4HIMR0 FFHInterrupt Mask Register 0 5-226
55HA5HIMR1 FFHInterrupt Mask Register 1 5-226
56HA6HIMR2 03HInterrupt Mask Register 2 5-227
57HA7HReserved
58HA8HRSTA 00HReceive Status Byte 5-229
59HA9HReserved
5AHAAHSYNCL 00HSYN Char act er Register (Low Byte ) 5-233
5BHABHSYNCH 00HSYN Charact er Register (High Byte) 5-233
5CHACH
... Reserved
Table 5-1 Regi st er Overview (cont’d)
Offset
Ch A Ch B Register
read write Res
Val Meaning Page
PEB 20542
PEF 20542
Regist er Descript ion
Preliminary Data Sheet 5-121 08.99
5FHAFH
Channel specific DMA registers:
B0HCAHTBADDR1L 00HPrimar y Trans mit Base Address (L ow
Byte) 5-235
B1HCBHTBADDR1M 00HPr imar y Trans mit Base Address (Mi d
Byte) 5-235
B2HCCHTBADDR1H 00HPrimar y Trans mit Base Address (High
Byte) 5-236
B3HCDHReserved
B4HCEHTBADDR2L 00HSec ondar y Trans mit Base Address (Low
Byte) 5-237
B5HCFHTBADDR2M 00HSec ondary Transmit Base Address (Mid
Byte) 5-237
B6HD0HTBADDR2H 00HSec ondar y Trans mit Base Address (High
Byte) 5-238
B7HD1HReserved
B8HD2HXBC1L 00HPrimary Transmit Byte Count (Low Byte) 5-239
B9HD3HXBC1H 00HPr imar y Trans mit Byte Count (High Byte) 5-239
BAHD4HXBC2L 00HSec ondar y Trans mit Byte Co unt (Low
Byte) 5-241
BBHD5HXBC2H 00HSecondar y Trans mit Byte Count (High
Byte) 5-241
BCHD6HRBADDR1L 00HPrimar y Re cei ve Base Address (Low
Byte) 5-243
BDHD7HRBADDR1M 00HPr imar y Re cei ve Base Address 1 (Mid
Byte) 5-243
BEHD8HRBADDR1H 00HPrimar y Recei ve Base Addres s 1 (High
Byte) 5-244
BFHD9HReserved
C0HDAHRBADDR2L 00HSecondar y Re cei ve Base Addres s (Low
Byte) 5-245
C1HDBHRBADDR2M 00HSec ondar y Re cei ve Base Addres s (Mid
Byte) 5-245
T able 5-1 Registe r Overvi ew (cont’d)
Offset
Ch A Ch B Register
read write Res
Val Meaning Page
PEB 20542
PEF 20542
Regist er Descript ion
Preliminary Data Sheet 5-122 08.99
C2HDCHRBADDR2H 00HSecondary Receive Base Address2 (High
Byte) 5-246
C3HDDHReserved
C4HDEHRMBSL 00HReceive Max imum Buffer Size (Low Byte) 5-247
C5HDFHRMBSH 00HReceive Maximum Buffer Size (High Byte) 5-247
C6HE0HRBCL 00HRecei ve Byte Count (Low Byte) 5-249
C7HE1HRBCH 00HReceive Byte Count (High Byte) 5-249
C8HE2HReserved
C9HE3HReserved
Miscellaneous:
E4H
... Reserved
EBH
ECHVER0 03HVersion Register 0 5-251
EDHVER1 E0HVersion R egist er 1 5-251
EEHVER2 05HVersion R egist er 2 5-252
EFHVER3 10HVersion R egist er 3 5-252
Table 5-1 Regi st er Overview (cont’d)
Offset
Ch A Ch B Register
read write Res
Val Meaning Page
PEB 20542
PEF 20542
Regist e r Des cription (GCMDR)
Preliminary Data Sheet 5-123 08.99
5.2 Detail ed Register Description
5.2.1 Global Registers
Each regist er desc ription is organized in three parts:
• a head with general information about reset value, access type (read/write), offset
address and usua l handli ng;
• a table containing the bit information (name of bit positions);
• a section containing the detailed description of each bit.
Reg ister 5-1 GCM DR
Global Command Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Offs et Address: 00H
typical usage: written by CPU,
evaluated by MISTRAL
Bit76543210
Global Command Bits
0000000SWR
SWR Software Reset Command
Self clearing comma nd bit:
bit=’0’ No soft ware res et comm and is issued .
bit=’1’ Causes MISTRAL to perform a complete reset identical to
h a rd ware re s et.
PEB 20542
PEF 20542
Register Description (GMODE)
Preliminary Data Sheet 5-124 08.99
Reg ister 5-2 GMODE
Global Mode Register
CPU Acc e ssibilit y : read/write
Reset Value: 0FH
Offs et Address: 01H
typical usage: written by CPU
evaluated by MISTRAL
Bit76543210
DMA and Global Interrupt Control
IDMA 0 IPC(1:0) OSCPD
Reserved
DSHP GIM
IDMA Enable Internal DMA
This bit field controls the DMA operation mode:
IDMA= ’0’ The internal DMA controller functions are disabl ed.
MISTRAL is operated in standard register access
controlled mode.
IDMA= ’1’ The internal DMA controller is enabled.
Single Buffer or Switched Buffer operation mode is
selected with register DMODE.
IPC(1:0) Interrupt-Port Configuration
These bits control the function of interrupt output pin INT/INT:
IPC(1:0) Output Function:
’00’ O pen Drain active low
’01’ P ush/Pu ll active low
’10’ Reserved.
’11’ Push/Pull active high
PEB 20542
PEF 20542
Register Description (GMODE)
Preliminary Data Sheet 5-125 08.99
OSCPD Oscillator Power Down
Setting this bit to ’0’ enables the internal oscillator. For power saving
purposes (escpecially if clock modes are used which do not need the
i nt e rn a l o scillat or) this bit may rema in se t to ’1 ’.
OSCPD=’0’ The internal oscilla tor is active.
OSCPD=’1’ The interna l oscillator is in power down mode.
Note: After reset th is bit is se t to ’1 ’, i.e. th e o scil lato r is in power down
mode!
Reserved
Reserved Bit
The rese t value of this bit is ’1’.
It should be set to ’0’ during configuration in any case.
Note: This bit is a redundant control bit for the shaper in the oscillator
unit. In later revisions of MISTRAL the shaper will be controlled
with bit ’DSHP’ only !
DSHP Disable Shaper
This bit has to be set to ’0’ if the shaping function in the oscillator unit is
desired. The shape r amplifies the osci llator signal and improves the
slope of the clock edges.
DSHP=’0’ Shaper is enabled. Recommended setting if a crystal is
connect ed t o pins XTAL1/XTAL2.
DSHP=’1’ Shaper is disable d (bypas sed) . Recom m ended set ting if
- a TTL level clock signal is supplied to pin XTAL1
- the oscillator unit is unused
Note: (1)
After rese t this bit is set to ’1’, i.e. the shaper is disabled!
(2)
For correct operation the reserved bit 2 must be set to ’0’ (in
later revisions the sha per will be controlled with bit ’DSHP’ only)!
PEB 20542
PEF 20542
Register Description (GMODE)
Preliminary Data Sheet 5-126 08.99
GIM Global Interrupt Mas k
This bits disables all interrupt indications via pin INT/INT. Internal
operation (interrupt generation, interrupt status register update,...) is not
affected.
If set, pin INT /INT immediately changes or remains in inactive state.
GIM=’0’ Global interrupt mask is cleared. Pin INT/INT is controlled
by the internal interrupt control logic and activated as long
as at least one unmasked interrupt indication is pending
(not yet confi rmed by read acc ess to corresponding
interr upt status reg ister ).
GIM=’1’ Global interrupt mask is set. Pin INT/I NT remains inactive.
Note: After reset this bit is set to ’1’ , i.e. all interrupts are disabled!
PEB 20542
PEF 20542
Regist er Descript ion (DBSR)
Preliminary Data Sheet 5-127 08.99
Reg ister 5-3 DBSR
DMA Buffer Status Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Offs et Address: 02H
typical usage: written by MISTRAL evaluated by CPU
Bit76543210
Internal DMAC Status Information
DTBB 0 DRBB 0 DTBA 0 DRBA 0
DTBB DMA Transmit Buffer Channel B
DRBB DMA Receive Buffer Channel B
DTBA DMA Transmit Buffer Channel A
DRBA DMA Receive Buffer Channel A
Onl y va lid in int e rn a l DMA con troller mo des.
These bits indicate on which buffer the corres pondi ng DMA channel is
currently operating on.
These status bits are for debug purposes only.
bit = ’0’ base addr ess 1 is active addre ss
bit = ’1’ base addr ess 2 is active addre ss
PEB 20542
PEF 20542
Regist er Descript ion (GSTAR)
Preliminary Data Sheet 5-128 08.99
Reg ister 5-4 GSTAR
Global Status Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Offs et Address: 03H
typical usage: written by MISTRAL evaluated by CPU
Bit76543210
Global Interrupt Status Inform ation
GPI DMI ISA2 ISA1 ISA0 ISB2 ISB1 ISB0
GPI General Purpose Port Indication (-)
This bit indicates, that a GPP port interrupt indication is pending:
GPI=’0’ No general purpose port interrupt indication is pending.
GPI=’1’ General purpose port interrupt indication is pending. The
source for this interrupt can be further determined by
reading reg ister GPIS (refer to page 5-133).
DMI DMA Interrupt Indi cat ion (-)
This bit indicates, that a DMA interrupt indication is pending:
DMI=’0’ No DM A interrupt indicat ion is pending.
DMI=’1’ DMA interrupt indication is pending. The source for this
interrupt (chann el A/B, receive/tran smit ) can be further
determined by reading register DISR (r ef er to page 5-
137).
PEB 20542
PEF 20542
Regist er Descript ion (GSTAR)
Preliminary Data Sheet 5-129 08.99
ISA2 Channel A Interrupt Status Register 2
ISA1 Channe l A Inter rupt Status Register 1
ISA0 Channel A Interrupt Status Register 0
ISB2 Channel B Interrupt Status Register 2
ISB1 Channe l B Inter rupt Status Register 1
ISB0 Channel B Interrupt Status Register 0
These bits indicate, that an interrupt indication is pending in the
corresponding interrupt status register(s) ISR0/ISR1/ISR2 of the serial
commu nication cont ro ller (SCC):
bit=’0’ No inte rrupt indication is pendi ng.
bit=’1’ An interrupt indicat ion is pending.
PEB 20542
PEF 20542
Register Description (GPDIR)
Preliminary Data Sheet 5-130 08.99
Reg ister 5-5 GPDIR
GPP Direction Register
CPU Acc e ssibilit y : read/write
Reset Value: FFH
Offs et Address: 05H
typical usage: written by CPU eval uat ed by MISTRA L
Bit76543210
GPP I/O Direction Control
11111
GP2DIR GP1DIR GP0DIR
GPnDIR GPP Pin n Direction Control (-)
This bit selects between input and output function of the correspondi ng
GPP pin:
bit = ’0’ outpu t
bit = ’1’ input (reset value)
PEB 20542
PEF 20542
Regist er Descript ion (GPDAT)
Preliminary Data Sheet 5-131 08.99
Reg ister 5-6 GPDAT
GPP Data Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Offs et Address: 07H
typical usage: written by CPU(o utp uts) and MISTR AL(input s) ,
evaluated by MISTRAL(outputs) and CPU(inputs)
Bit76543210
GPP Data I/O
00000
GP2DAT GP1DAT GP0DAT
GPnDAT GPP Pin n Data I/O Va lue (-)
This bit indicates the value of the correspondi ng GPP pin:
bit = ’0’ If direction is input: input level is ’low’;
if dir ect io n is outp ut : out p u t level is ’low’.
bit = ’1’ If direction is input: input level is ’high’;
if direction is output: output level is ’high’.
PEB 20542
PEF 20542
Register Description (GPIM)
Preliminary Data Sheet 5-132 08.99
Reg ister 5-7 GPIM
GPP Interrupt Mask Register
CPU Acc e ssibilit y : read/write
Reset Value: FFH
Offs et Address: 09H
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
GPP Interrupt Mask Bits
11111
GP2IM GP1IM GP0IM
GPnIM GPP Pin n Int errupt Mask (-)
This bit controls the interrupt mask of the corresponding GPP pin:
bit = ’0’ Interrupt generation is enabled. An interrupt is generated
on any state transition of the corresponding port pin
(inputs).
bit = ’1’ Interrupt generati on is disabled (reset value).
PEB 20542
PEF 20542
Register Description (GPIS)
Preliminary Data Sheet 5-133 08.99
Reg ister 5-8 GPIS
GPP Interrupt Status Regi ster
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Offs et Address: 0BH
typical usage: written by MISTRAL, read and evaluated by CPU
Bit76543210
GPP Interrupt Status Bits
00000
GP2I GP1I GP0I
GPnI GPP Pi n n Interrupt In diction (-)
This bit indicates if an interrupt event occured on the corresponding GPP
pin:
bit = ’0’ No inte rrupt indication is pendi ng at this pin (no state
tra nsi tion has occu red) .
bit = ’1’ An interrupt indicat ion is pending (a state transitio n
occur ed). The interrupt indicati on is cleare d after read
access.
PEB 20542
PEF 20542
Register Description (DCMDR)
Preliminary Data Sheet 5-134 08.99
Reg ister 5-9 DCM DR
DMA Command Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Offs et Address: 0CH
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
DMA Controller Reset Command Bits
RDTB DTACK
TB RDRB DTACK
RB RDTA DTACK
TA RDRA DTACK
RA
RDTB Reset DMA Tra nsmit Channel B
RDRB Reset DMA R ecei ve Ch annel B
RDTA Reset DMA Tra nsmit Channel A
RDRA Reset DMA Receive Channel A
Self-clearing com ma nd bit.
These bits bring the corresp onding DMA channel to the reset state:
bit=’0’ No reset is performed .
bit=’1’ Reset is performed.
PEB 20542
PEF 20542
Register Description (DCMDR)
Preliminary Data Sheet 5-135 08.99
DTACKTB DMA Transfer Ack Transmit Channel B
DTAC KRB DMA Transfer Ack Recei ve Cha nnel B
DTACKTB DMA Transfer Ack Transmit Channel A
DTAC KRB DMA Transfer Ack Recei ve Cha nnel A
Onl y va lid in int e rn a l DMA con troller mo des.
bit = ’0’ Th e data transfer acknow ledge si gnal on pin DTACK/
READY pin is ignored for data transfer cycles initiated by
the MISTRAL DMA controller.
bit = ’1’ Fo r dat a transfe r cycles in itia ted by the intern al DMA
cont rolle r the handshake signal DTACK/READY is
evaluated by MISTRAL. This can be used to extend the
duration of read or write cycles.
PEB 20542
PEF 20542
Register Description (DMODE)
Preliminary Data Sheet 5-136 08.99
Reg ister 5-1 0 D M O DE
DMA Mode Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Offs et Address: 0DH
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
DMA Controller Operation Mode
0 TMODEB 0 RMODEB 0 TMODEA 0 RMODEA
TMODEB Transmi t DMA Mode Channel B
RMODEB Receive DMA Mode Channel B
TMODEA Transmi t DMA Mode Channel A
RMODEA Receive DMA Mode Channel A
These bits select the operatin g mode of the corresp onding DMA
channel:
’0’ Si ngle Buffer Mode (stand ard mode)
Us ed base addr ess regi sters are TBADDR1L/M/H
(transmit) and RBADDR1L/M/H (re ceive).
’1’ Sw itc hed Buffer Mode
Base addre ss regist ers switch altern ating from
TBADDR1L/M/H and RBADDR1L/M/H to
TBADDR2L/M/H and RBADDR2L/M/H.
After reset, transm it and receive buff ers #1 are selected.
PEB 20542
PEF 20542
Register Description (DISR )
Preliminary Data Sheet 5-137 08.99
Reg ister 5-11 DISR
DMA Inter rupt Status Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Offs et Address: 0EH
typical usage: written by MISTRAL , evaluat ed by CPU
Bit76543210
DMA Interrupt Status Register
0 RBFB RDTEB TDTEB 0 RBFA RDTEA TDTEA
RBFB Receive Buffer Full Channel B
RBFA Receive Buffer Full Channel A
If a receive buffer size is defined in registers RMBSL/RMBSH and during
reception the end of the receive buffer is reached th is interrupt is
generated indicating that the receive buffe r is full. The corre sponding
DMA channel suspends the write transf ers to memory until a new b uffer
is allocated and resumes the reception.
RDTEB Receive DMA Transfer End Channel B
RDTEA Receive DMA Transfer End Channel A
This bit set to ’1’ indicates that a DMA transfer of receive data is finished
and the receive data is completely mo ved to the correspon ding receive
buffer in host memory.
If this completed DMA transfer filled up the receive buffer (i.e. the receive
byte count RBC matches the buffer size RMBS), bit RBFA/B is also set.
TDTEB Transmit DMA Transfer End Ch annel B
TDTEA Transmit DMA Transfer End Ch annel A
This bit set to ’1’ indicates that a DMA transfer of transmit data is finished
and the data is completely moved from the transmit buffer to the on-chip
tr a n s mi t F IFO.
PEB 20542
PEF 20542
Register Description (DIMR)
Preliminary Data Sheet 5-138 08.99
Reg ister 5-1 2 D I MR
DMA Interrupt Mask Register
CPU Acc e ssibilit y : read/write
Reset Value: 77H
Offs et Address: 0FH
typical usage:
Bit76543210
DMA Interrupt Mask Register
0 MRBFB MRDTEB MTDTEB 0 MRBFA MRDTEA MTDTEA
MRBFB Mask Receive Buffer Full Interrupt Channel B
MRBFA Mask Receive Buffer Full Interrupt Channel A
MRDTEB Mask Receiv e DMA Transfer End Interrupt Cha nnel B
MRDTEA Mask Receiv e DMA Transfer End Interrupt Cha nnel A
MTDTEB Mask Transmit DMA Transfer End Interrupt Channel B
MTDTEA Mask Transmit DMA Transfer End Interrupt Channel A
If a bit in t hi s interrupt mas k register is set to ’1’, the corresponding
interrupt is not generated and not indica ted in the correspondi ng bit
position in the DISR register. After reset all interrupts are masked.
PEB 20542
PEF 20542
Regist er Descr iption (FIFOL)
Preliminary Data Sheet 5-139 08.99
5.2.2 Channel Specific SCC Registers
Each regist er desc ription is organized in three parts:
• a head with gene ral inf ormation about r eset value, access t ype (read/write), channel
specific offset addresses and usual handling;
• a table containing the bit information (name of bit positions) distinguished for the three
major protocol modes HDLC/PPP (H), ASYNC (A) and BISYNC (B) ;
• a section containing the detailed description of each bit; the corresponding modes, the
bit is valid for, are m ar ked agai n by a bracket term right beside the full bit name.
Reg ister 5-13 FIFOL
Receive/Transmit FIFO (Low Byte)
CPU Acc e ssibilit y : read/write
Reset Value: -
Channel A Channel B
Offs et Address: 10H60H
typical usage: XFIFO: written by CPU , evaluated by MISTR AL
RFIFO : written by MISTRAL, evalua ted by CPU
Bit76543210
RF IFO/XF IFO Access Low Byte
FIFO(7:0)
Reg ister 5-14 FIFOH
Receive/Transmit FIFO (High B yt e)
CPU Acc e ssibilit y : read/write
Reset Value: -
Channel A Channel B
Offs et Address: 11H61H
typical usage: XFIFO: written by CPU , evaluated by MISTR AL
RFIFO : written by MISTRAL, evalua ted by CPU
Bit76543210
RFIFO/XFIFO Access High Byte
FIFO(15:8)
PEB 20542
PEF 20542
Register Description (FIFOH )
Preliminary Data Sheet 5-140 08.99
Receive FIFO (RFIFO)
Reading data from the RFIFO can be done in 8-bit (byte) or 16-bit (word) accesses,
dependi ng on th e selected mic roprocessor bus width using signal ’WIDTH ’.
The size of the accessible part of RFIFO is determined by programming the RFIFO
threshold level in bit field CCR3H.RFTH(1:0). If the HDLC/PPP protocol machine is
selected, the threshold can be adjusted to 32 (reset value), 16, 4 or 2 bytes. With the
ASYNC and BISYNC protocol machines following threshold levels can be selected: 1
(reset value), 4, 16 or 32 bytes.
• Interrupt Control led Data Transfer (GMODE.IDMA=’0’)
Up to 32 bytes/16 words of received data can be read from the RFIFO following an RPF
or an RME interrupt (see ISR0 register). The address provided during an RFIFO read
acces s is not inc remental; it is alway s 10 H for channel A or 60H for channel B.
RPF Interrupt: This interrupt indicates that the adjusted receive threshold level is
reach ed. The message is not yet complete. A fix number of bytes, depen dent from the
threshol d level, has to be read.
RME Interrupt: The message is completely received. The number of valid bytes is
determined by reading the RBCL, RBCH registers.
The content of the RFIFO is released by issuing the “Receive Message Complete”
command (CMDRH.RMC).
Transmit FIFO (XFIFO)
Writing data to the XFIFO can be done in 8-bit (byte) or 16-bit (word) accesses,
dependi ng on th e selected mic roproces sor bus wi dth using signal ’WIDTH ’.
• Interrupt Control led Data Transfer (GMODE.IDMA=’0’)
F ollowi ng an XPR (or an ALLS) interrupt , u p t o 32 bytes/16 w ords of new tran smit dat a
can be written into the XFIFO. Transmit data c an be released for transmission with an
XTF command. The address provided during an XFIFO write access is not incremental;
it is alway s 10H for channel A or 60H for channel B.
PEB 20542
PEF 20542
Register Description (STARL)
Preliminary Data Sheet 5-141 08.99
Reg ister 5-15 STARL
Status Register (Low Byte)
CPU Acc e ssibilit y : read only
Reset Value: 00H
Channel A Channel B
Offs et Address: 12H62H
typical usage: updated by MISTRAL
read and evaluat ed by C PU
Bit76543210
Mode
Command Status Transmitter Status
HXREPE 0 0CEC 0 XDOV XFW CTS
AXREPE 0 TEC CEC FCS XDOV XFW CTS
BXREPE 0 0 CEC 0 XDOV XFW CTS
Reg ister 5-16 STARH
Status Register (High Byte)
CPU Acc e ssibilit y : read only
Reset Value: 10H
Channel A Channel B
Offs et Address: 13H63H
typical usage: updated by MISTRAL
read and evaluat ed by C PU
Bit76543210
Mode
Receiver Status Automode Status
H0 0 CD RLI DPLA WFA XRNR RRNR
A0RFNECD0DPLA000
B0 RFNE CD SYNC DPLA 0 0 0
PEB 20542
PEF 20542
Register Descripti on (STARH)
Preliminary Data Sheet 5-142 08.99
XREPE Transmit Repetition Executing (all mod es)
XREPE=’0’ No t rans mit repetition command is in execution.
XREPE=’1’ A XREP command (regis ter CMDRL) is currently in
execution.
TEC TIC Execut ing (async mode)
TIC=’0’ No TIC (transm it imm edia te charact er) is curren tly in
transmission. Access to register TICR is allowed to initiate
a TIC transmission.
TIC=’1’ A TIC comm and (wr ite access to register TICR) is
accepted but not completely executed. No further write
access to register TICR is allowed until ’TIC’ bit is cleared
by MIST RAL.
CEC Command Executing (all mod es)
CEC=’0’ No comm and is curre ntly in execution . The comman d
regist ers CMDRL/CMDRH can be written by CPU.
CEC=’1’ A command (wr itten previously to regis ters CMDRL/
CMDRH) is currently in exec ution. No further command
can be written to register s CMDRL/CMDRH by CPU.
Note: CEC will be active at most 2.5 receive or transmit clock cycles
(depending on whether a receiver or transmitter related command
is executed).
CEC will stay active if the SCC is in power-down mode or if no
serial clock, needed for comm and exec ution, is available.
FCS Flow Contr ol Status (async mode)
If (in-band) flow control mechanism is enabled via bit ’FLON’ in register
CCR2 this bit indicates the current state of transmitter :
FCS=’0’ Transmi tter is ready (always after transmitter reset
command or XON-charact er detected).
FCS=’1’ Transmi tter is stopped (XOFF-chara cter dete cted ).
PEB 20542
PEF 20542
Register Descripti on (STARH)
Preliminary Data Sheet 5-143 08.99
XDOV Transmit FIFO Data Overflow (all mod es)
XDOV=’0’ Less than or equal to 32 bytes have been written to the
XFIFO.
XDOV=’1’ More than 32 bytes have been written to the XFIFO. This
bit is res et by:
– a transmitter reset command ’XRES’
– or when all bytes in the accessible half of the XFIFO
have been moved into the inaccess ible hal f.
XFW Tr ansmit FIFO Write Enable (all modes)
XFW=’0’ The XFIFO is not able to accept further transmit data.
XFW=’1’ Transmit data can be written to the XFIFO.
CTS CTS (Clear To Send) Input Signal State (all modes)
CTS=’0’ CTS input signal is inactive (high level)
CTS=’1’ CTS input signal is active (low level)
Note: A transmit clock must be provided in order to detect the signal
state of the CTS input pin.
Optionally this input can be programm ed to generate an interrupt
on signal level changes.
RFNE Receive FIFO Not Empty (async/bisy nc modes)
This status bit is set if the SCC receive FIFO (RFIFO) holds at least one
valid byte.
RFNE=’0’ The receive FIFO is empty.
RFNE=’1’ The receive FIFO is not empty.
PEB 20542
PEF 20542
Register Descripti on (STARH)
Preliminary Data Sheet 5-144 08.99
CD CD (C ar rier Detect) Input Signal State (all modes)
This status bit gives the signal state of CD input. This bit value is
independe nt of the programme d polari ty of the Carrier Detect function
(b it ’ICD’ in re g is te r CCR1H).
CD=’0’ CD input signal is low.
CD=’1’ CD input signal is high.
Note: A receive clock must be provided in order to detect the signal state
of the CD input pin.
Optionally this input can be programm ed to generate an interrupt
on signal level changes.
SYNC Synchronization Status (bisync mode)
This bit indicates whether the receiver is in synchronized state. After a
’HUNT’ command ’SYNC’ bit is cleared and the receiver starts searching
for a SYNC characte r. When found the ’SYNC’ status bit is set
immediately, an SCD-interrupt is generated (if enabled) and receive data
is forwarded to the receiver FIFO.
SYNC=’0’ Synchronization is lost or not yet achieved.
(after reset or after new ’HUNT’ command has been
iss ued and before SYNC cha racter is found)
SYNC=’1’ Receive line is inactive, i.e. more than 7 conse cutive ’1’
are detect ed on the line.
RLI Receive Line Inactive (hdlc mode)
This bit indicates that neither flags as interfram e time fill nor data are
being received via the receive line.
RLI=’0’ Receive line is active, no constan t high level is detected.
RLI=’1’ Receive line is inactive, i.e. more than 7 consecut ive ’1’
are detect ed on the line.
Note: A receive clock must be provided in order to detect the receive line
state.
PEB 20542
PEF 20542
Register Descripti on (STARH)
Preliminary Data Sheet 5-145 08.99
DPLA DPLL Asynchronous (all mod es)
This bit is only valid if the receive clock is recover ed by the DPLL and
FM0, FM1 or Manchester data encodi ng is selected. It is set when the
DPLL has los t synch ronizat i on. In this case rec eption is disa ble d
(receive abort condition) until synchronization has been regained. In
addition transmi ssi on is interrupte d in all cases where transm it clo ck is
derived from the DPLL (clock mode 3a, 7a). Interruption of transmission
is performed the same way as on deactivation of the CTS signal .
DPLA=’0’ DPLL is synchronized.
DPLA=’1’ DP LL is asynchrono us (re -syn chro niz ation pro cess i s
started automatically).
WFA Wait For Acknowledgement (hdl c mo de)
This status bit is significant in Automode only. It indicates whether the
Automode state machine expects an acknowledging I- or S-Frame for a
previously sent I-Frame.
WFA=’0’ No acknowledge I/S-Frame is expec ted.
WFA=’1’ Th e Automode st ate machine is wait ing for an
achnow ledgi ng S- or I-Frame.
XRNR Transmit RNR Status (hdlc mode)
This status bit is significant in Automode only. It indicates the receiv er
status of the local station (SCC).
XRNR=’0’ The receiver is ready and will autom aticall y answer poll -
frames with a S-Frame with ’receiv er-ready ’ indication.
XRNR=’1’ The receiver is NOT ready and will automat ica lly answer
poll-frames with a S-Frame with a ’receiver-not-ready’
indication.
RRNR Received RNR (Receiver Not Ready) Status (hdlc mode)
This status bit is significant in Automode only. It indicates the receiv er
status of the remote station.
RRNR=’0’ The remote station receiver is ready.
RRNR=’1’ The re mote receiv e r is NOT ready .
(A ’recei ver -not-r eady’ ind ica tion was recei ved from the
remo te station)
PEB 20542
PEF 20542
Register Description (CMD RL )
Preliminary Data Sheet 5-146 08.99
Reg ister 5-1 7 C M D RL
Command Register (Low Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 14H64H
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
Mode
Timer T ransmitter Commands
HSTI TRES XIF XRES XF XME XREP 0
ASTI TRES TXON XRES XF XME XREP TXOFF
BSTI TRES 0 XRES XF XME XREP 0
Reg ister 5-1 8 C M D RH
Command Register (High Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 15H65H
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
Mode
Receiver Commands
HRMC RNR 0 0 RSUC 0 0 RRES
ARMC00000RFRDRRES
BRMC 0 0 0 HUNT 0 RFRD RRES
PEB 20542
PEF 20542
Register Description (CMDRH)
Preliminary Data Sheet 5-147 08.99
STI Start Timer Command (all mod es)
Self-clearing com ma nd bit:
HDLC Automode:
In HDLC Automode the timer is used internally for the autonomous
protocol support functions. The timer is started automatically by the SCC
when an I-Frame is sent out and needs to be acknowledged.
If t he ’ STI’ command i s issued by softwar e:
STI=’1’ An S-Frame with poll bit set i s sent out and the internal
timer is started expec ting an acknowledge from the
remote station via an I- or S-Frame.
The timer is stopped after receivi ng an acknowledg e
otherw is e the timer expires gener ating a time r interrupt.
Note: In HDLC Automode, bit ’TMD’ in register TIMR3
must be set to ’1’
All pr otocol modes except HDLC Autom ode:
In these modes the timer is operating as a general purpose t imer.
STI=’1’ Th is comm ands st arts timer oper ation.
The timer can be stopped by setting bit ’TRES’.
Note: Bit ’TMD’ in register TIMR3 must be cleared for
proper operation
TRES Timer Reset (all mod es)
Self-clearing com ma nd bit.
This bit deactiva tes timer operat io n:
TRES=’0’ Timer operation enabled.
TRES=’1’ Timer operation stopped.
XIF Transm i t I-Frame (hdlc mode)
Self-clearing com ma nd bit.
This command bit is significant in HDLC Automode only.
XIF=’1’ Initiates the transmission of an I-frame in auto-mode.
Additional to the opening flag, the address and control
fields of the frame are add ed by MISTRAL.
PEB 20542
PEF 20542
Register Description (CMDRH)
Preliminary Data Sheet 5-148 08.99
TXOFF Transmi t Off Command (async mode)
Self-clearing com ma nd bit:
This command bit is significant if in-band flow-control is selected.
TXOFF=’1’ Forces the transmitter to enter its ’transmit off’ state. This
is equal to receivin g an XOFF charact er.
TXON Transmit On Command (async mode)
Self-clearing com ma nd bit:
This command bit is significant if in-band flow-control is selected.
TXON=’1’ Forces the transmitter to enter its ’transmit on’ state. This
is equal to receivin g an XON character.
XRES Transmitter Reset Command (all mod es)
Self-clearing com ma nd bit:
XRES=’1’ The SCC transmit FIFO is cleared and the transmitter
protocol engi nes are reset to their initial state.
A transmitter reset command is recommended after all
changes in protocol mode configurations (e.g. switching
between the prot oco l engines HDLC/ASYNC/BI SYNC or
sub-modes of HDLC).
XF Transmit Frame (all mod es)
This self-clearing command bit is significant in interrupt driven operation
only (GMODE.IDMA=’0’).
XF=’1’ Aft er having written up to 32 bytes to the XFIFO, this
command initiates transmission. In packet oriented
protocols like HDLC/PPP the opening flag is automatically
added by MISTRAL. If the end of the packet is part of the
transm it data, bit ’XME’ sho uld be set in addition.
DMA Mode
After having w ritten the length of the data block to be
tra nsm itte d to registers XBC1L and XBC1H, this
command initiates the data transfer from host memory to
MISTRAL by DMA. Transmission on the serial side starts
as soon as 32 byte s are transferred to the XFIFO or the
transmit byte counter value is reached.
PEB 20542
PEF 20542
Register Description (CMDRH)
Preliminary Data Sheet 5-149 08.99
XME Transmit Message End (hdlc/b isy nc modes)
Self-clearing com ma nd bit:
XME=’1’ Indi cates th at the data block written l ast to the XFIFO
contains the end of the packet. This bit should always be
set in conjunction with a transmit command (’XF’ or ’XIF’).
XREP Transm i ssi on Repeat Command (hdlc mode)
Self-clearing com ma nd bit:
XREP=’1’ If bit ’XREP’ is set together with bit ’XME’ and ’XF’,
MISTRAL repeatedly transmits the contents of the XFIFO
(1..32 bytes).
The cycl ic transmissi on can be st opped with th e ’XRES’
command.
RMC Receive Message Complete (all modes)
Self-clearing com ma nd bit:
RMC=’1’ With this bit the CPU indicates to MISTRAL that the
current receive data has been fetched out of the RFIFO.
Thus the corres pondi ng space in the RFIFO can be
released and re-used by MISTRAL for further incoming
data.
RNR Recei ver Not Ready C omm and (hdlc mode)
NON self-clearing com m and bit:
This command bit is significant in HDLC Automode only.
RNR=’0’ Forces the receiver to enter its ’receiver-ready’ state. The
receiver acknowledges received poll or I-Frames with a
’receiver-ready’ indication.
RNR=’1’ Forces the receiver to enter its ’receiver-not-ready’ state.
The receiver acknowledges received poll or I-Frames with
a ’receiver-not-ready’ indication.
RSUC Reset Signaling Unit Counter (hdlc mode)
Self-clearing com ma nd bit:
This command bit is significant if HDLC SS7 mode is selected.
RSUC=’ 1’ The Signaling System #7 (SS7) unit counter is reset.
PEB 20542
PEF 20542
Register Description (CMDRH)
Preliminary Data Sheet 5-150 08.99
HUNT Enter Hunt State Comman d (bisync mode)
Self-clearing com ma nd bit:
HUNT=’ 1’ This command fo rces the receive r to enter its ’HUNT’
state imm edi ately. Thus synchronizati on is ’lost’ and the
receiver starts search ing for new SYNC charact ers.
RFRD Receive FIFO Read Enable Command ( a sync/bisy nc modes)
Self-clearing com ma nd bit:
RFRD=’ 1’ This command fo rces insertion of a ’block end’ condition
into the RFIFO before the receive FI FO threshold is
exceeded or a block end condition (termination character
detected or time-out) is fulfilled. The execution of this
command is reported with a TCD interrupt.
RRES Receiver Reset Com man d (all mod es)
Self-clearing com ma nd bit:
RRES=’1’ The SC C r eceive F I FO is c lear ed and th e r eceiver
protocol engi nes are reset to their initial state.
The SCC receive FIFO accepts new receive data from the
protocol engine immediately after receiver reset
procedure.
It is recommended to disable data reception befor e
iss uing a receiver reset comm and by set ting bi t
CCR3L.RAC = ’0’ and enabling data reception afterwards.
A ’receive r reset’ command is recommended after all
changes in protocol mode configurations (switching
between the protocol engines HDLC/ASYNC/BISYNC or
sub-modes of HDLC).
PEB 20542
PEF 20542
Register Description (CCR0L)
Preliminary Data Sheet 5-151 08.99
Register 5-19 CCR0L
Channel Configuration Register 0 (Low Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 16H66H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
misc. Clock Mode Selection
HVIS PSD BCR TOE SSEL CM(2:0)
AVIS PSD BCR TOE SSEL CM(2:0)
BVIS PSD BCR TOE SSEL CM(2:0)
Register 5-20 CCR0H
Channel Configuration Register 0 (Hi gh Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 17H67H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Power Line Coding Protocol Mode
HPU SC(2:0) 0 0 SM(1:0)
APU SC(2:0) 0 0 SM(1:0)
BPU SC(2:0) 0 0 SM(1:0)
PEB 20542
PEF 20542
Register Descripti on (CCR0H)
Preliminary Data Sheet 5-152 08.99
PU Power Up (all mod es)
PU=’0’ The SCC is in ’power-down’ mode. The protocol engines
are switched off (standby) and no operation is performed.
This may be used to save power when SCC is not in use.
Note: The SCC transmit FIFO accepts transmit data even
in ’powe r-dow n’ mode.
PU=’1’ The SCC is in ’power-up’ mode.
SC(2:0) Serial Port Configuration (all mod es)
This bit field selects the line coding of the serial port.
Note, that special operation modes and settings may require or exclude
operation in special line coding modes. Refer to the ’prerequisites’ in the
dedicated mode descripti ons.
SC = ’000’ NRZ data encoding
SC = ’001’ Bus configuration, timing mode 1 (NRZ data encoding)
SC = ’010’ NRZI data encoding
SC = ’011’ Bus configuration, timing mode 2 (NRZ data encoding)
SC = ’100’ FM0 data encoding
SC = ’101’ FM1 data encoding
SC = ’110’ Manchester data encoding
SC = ’111’ Reserved
Note: If bus configurat ion mode is sel ected, only N RZ data enc oding is
supported.
SM(1:0) Serial Port Mode (all modes)
This bit field selects one of the three protocol engi nes.
Depending on the selected protoc ol engine the SCC related regist ers
change or special bit positions within the registers change their meaning.
SM = ’00’ HDLC/PPP protocol engine
SM = ’ 01’
Reserved
(do not use)
SM = ’10’ BISYNC protocol engine
SM = ’11’ ASYNC protocol engi ne
PEB 20542
PEF 20542
Register Descripti on (CCR0H)
Preliminary Data Sheet 5-153 08.99
VIS Masked Interrupts Visible (all mod es)
VIS=’0’ Masked interrupt status bits are not displayed in the
interr upt status reg ister s (ISR0..ISR2).
VIS=’1’ Masked interrupt status bits are visible and automatically
cleared after interrupt status register (ISR0..ISR2) rea d
access.
Note: Interrupts masked in registers IMR0..IMR2 will not generate an
interrupt.
PSD DPLL Phase Shift Disable (all modes)
This option is only applicable in the case of NRZ or NRZI line encoding
is selected.
PSD=’0’ Nor m al DPLL operation.
PSD=’1’ Th e phase shi ft function of the DPLL is disabled. The
window s for phase adjus tment are extended.
BCR Bi t Cloc k Rate (all modes)
This bit is only valid in asynchronous PPP, ASYNC and BISYNC protocol
mode and only in clock modes not using the DPLL (0, 1, 3b, 7b). It is also
invalid in cl ock mode 4.
BCR=’0’ S elects isochronous operation with bit clock rate 1. Data
bits are sampl ed once.
BCR=’1’ S elects standard asynchrono us opera tion with bit clock
rate 16. Using 16 samples per bit, data bits are sampled 3
times around the nominal bit cent er. The result ing bit
value is determined by majority decision of the 3 samples.
For correct opera tion NRZ data encoding has t o be
selected.
PEB 20542
PEF 20542
Register Descripti on (CCR0H)
Preliminary Data Sheet 5-154 08.99
TOE Transmit Clock Out Enabl e (all mod es)
For clock modes 0b, 2b, 3a, 3b, 6b, 7a and 7b, the internal transmit clock
can be monitored on pin TxCLK as an output signal. In clock mode 5, a
time slot control signal marking the active transmit time slot is output on
pin TxCLK.
Bit ’TOE’ is invalid for all o ther clock mod es.
TOE=’0’ TxCLK pin is input.
TOE=’1’ TxCLK pin is switched to output function if applicab le for
the select ed cl ock mo de.
SSEL Clock Source Select (all mod es)
Distinguishes between the ’a’ and ’b’ option of clock modes 0, 2, 3, 5, 6
and 7.
SSEL=’0’ Option ’a’ is selected.
SSEL=’1’ Option ’b’ is selected.
CM(2:0) Clock Mode (all mod es)
This bit field selects one of mai n clock modes 0..7. For a detailed
description of the clock modes refer to Chapter 3. 2.3
CM = ’000’ clock mode 0
CM = ’001’ clock mode 1
CM = ’010’ clock mode 2
CM = ’011’ clock mode 3
CM = ’100’ clock mode 4
CM = ’101’ clock mode 5 (time-slot or ien ted clocking m odes)
CM = ’110’ clock mode 6
CM = ’111’ clock mode 7
PEB 20542
PEF 20542
Register Description (CCR1L)
Preliminary Data Sheet 5-155 08.99
Register 5-21 CCR1L
Channel Configuration Register 1 (Low Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 18H68H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
misc.
HCRL C32 SOC(1:0) SFLG DIV ODS 0
A00000DIVODS0
BCRL0000DIVODS0
Register 5-22 CCR1H
Channel Configuration Register 1 (Hi gh Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 19H69H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
misc.
H0 ICD 0 RTS FRTS FCTS CAS TSCM
A0 ICD 0 RTS FRTS FCTS CAS TSCM
B0 ICD 0 RTS FRTS FCTS CAS TSCM
PEB 20542
PEF 20542
Register Descripti on (CCR1H)
Preliminary Data Sheet 5-156 08.99
CRL CRC Reset Value (hdlc mode)
This b it d ef in e s the in itial value o f th e inter n a l tra n s mit/re c e iv e CRC
generators:
CRL=’0’ Initial value is 0xFFFFH (16 bit CRC) , 0xFFFF FFFFH
(32 bit CRC).
This is the default value for most HDLC/ PPP appl ications.
CRL=’1’ Initial value is 0x0000 H (16 bit CRC), 0x00000000H
(32 bit CRC).
C32 CRC 32 Select (hdlc mode)
This b it e nab le s 32- b it CRC o per a tio n fo r transmit a nd rec e iv e .
C32= ’0 ’ 16-bit CRC- CCITT gener atio n / che ck in g .
C32=’1’ 32-b it CRC g enerat io n/c h e c ki n g.
Note: The internal ’valid frame’ criteria is updated depending on the
selected n umber of CRC-bytes.
SOC(1:0) Serial Output Control (hdlc mode)
This bit field selects the RT S signal output function.
(This bit field is only valid in bus configuration modes selected via bit field
SC (2 :0) in re g ister CCR0H).
SOC = ’0X’ RTS ouput signal is active during transmission of a frame
(act ive low).
SOC = ’10’ RTS ouput signal is always inactive (high).
SOC = ’11’ RTS ouput signal is active during recep tion of a frame
(act ive low).
SFLG Shared Flags Transmission (hdlc mode)
This bit enables ’shared flag transmission’ in HDLC protocol mode. If
another transmit frame begin is stored in the SCC transmit FIFO, the
closing flag of the preceding frame becomes the opening flag of the next
frame (shared flags):
SFLG = ’0’ Sh ared flag transmission di sabled.
SFLG = ’1’ Shared flag transmission enabled.
Note: The receiver always supports shared flags and shared zeros of
consecutive flags .
PEB 20542
PEF 20542
Register Descripti on (CCR1H)
Preliminary Data Sheet 5-157 08.99
DIV Data Inversion (all mod es)
This bit is only valid if NRZ data encoding is selected via bit field SC(2:0)
in register CCR0H.
DIV=’0’ No Data Inversion.
DIV=’1’ Data is transmitted /recei ved inverted (on a per bit basis).
In HDLC and HDLC Sy nchr onous PPP mode s the
cont inuo us ’1’ idle seque nce is NOT inverted.
Interf ra me time fill flag transm i ssi on is inver ted.
ODS Output Driver Select (all modes)
The transmit data output pin TxD can be configured as push/pull or open
drain output chract er istic.
ODS=’0’ TxD pin is open drain output.
ODS=’1’ TxD pin is push/pull output.
ICD Invert Carrier Detect Pin Polarity (all mod es)
ICD=’0’ Carrier Detect (CD) input pin is active high.
ICD=’1’ Carrier Detect (CD) input pin is active low.
RTS Request To Send Pin Contro l (all mod es)
The request to send pin RTS can be controlled by MISTRAL as an output
autonomousl y or via setting/c learing bit ’RTS’.
This bit is not valid in clock mode 4.
RTS=’0’ Pin RTS (output) pin is controlled by MISTRAL
autonomously.
HDLC Mode:
RTS is activated during transmission. In bus configuration
mode the functionali ty depe nds on bit field ’SOC’ setting.
ASYNC/BISYNC Mode :
The functionality depends on setting of bit ’FRTS’
RTS=’1’ Pin RTS can be controlled by software. The output level of
this pin depends on bit ’FRTS’ .
Note: For RTS pin control a transmit clock is necessary.
PEB 20542
PEF 20542
Register Descripti on (CCR1H)
Preliminary Data Sheet 5-158 08.99
FRTS Flow Control (using signa l RTS )(all modes)
Bit ’ FR TS’ together with bit ’RTS’ determine the function of signal RTS:
RTS, FRTS
0, 0 Pin RTS is controlled by M I STR AL autonomou sly .
RTS is activated (low) as soon as trans mit data is
avai lable within the SCC transmit FIFO.
0, 1 Pin RTS is controlled by M I STR AL autonomou sly
suppor ting bi -directional data flow contr ol.
RTS is activated (low) if the shadow part of the SCC
receive FI FO is empty and de-act iva ted (high ) when the
SCC receive FIFO fill level reac hes its receiv e FIFO
threshold.
1, 0 Fo rces pin RTS t o active st at e (low).
1, 1 Fo rces pin RTS t o inac tive st ate (high ).
Note: For RTS pin control a transmit clock is necessary.
FCTS Flow Control (using signa l CTS ) (all modes)
This bit controls the function of pin CTS.
FCTS = ’0’ The transmitter is stopped if CTS input signal is inactive
(high) and ena bled if active (low).
Note: In the character oriented p rotocol modes (ASYNC,
BISYNC, asynchronous PPP), the current byte is
completely sent even if CTS becomes inactive
during transm is sion.
FCTS = ’1’ The transmitter i s enabled, disregarding CTS input signal.
PEB 20542
PEF 20542
Register Descripti on (CCR1H)
Preliminary Data Sheet 5-159 08.99
CAS Carrier Detect Auto Start (all mod es)
CAS = ’0’ The CD pin is used as general input.
In clock mode 1, 4 and 5, clock m ode specific cont ro l
signals must be provided at this pin (receive strobe,
receive gat i ng RCG, frame sync cl ock FSC ).
A pull-up/dow n resistor is recommended if unused.
CAS = ’1’ The CD pin enables/disables the receiver for data
reception. (Polarity of CD pin can be configured via bit
’ICD’.)
Note: (1) In clock mode 1, 4 and 5 this bit must be set to ’0’.
(2) In ASYNC mode the transmitter is additionally controlled by in-
band flow control mechani sm (if enabl ed) .
(3) A receive clock m ust be provided i n order to detect the signal
state of the CD input pin.
TSCM Time Slot Control Mode (all mod es)
This bit controls internal counter operation in time slot oriented clock
mode 5:
TSCM=’0’ The internal coun ter keeps run ning, restarting with zero
after being expi re d.
TSCM=’1’ The internal counter stops at its maximum value and
restarts w ith the next frame sync pulse agai n.
PEB 20542
PEF 20542
Register Description (CCR2L)
Preliminary Data Sheet 5-160 08.99
Register 5-23 CCR2L
Channel Configuration Register 2 (Low Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 1AH6AH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
misc.
HMDS1 MDS0 ADM NRM PPPM(1:0) TLPO TLP
A000000TLPOTLP
B0 0 0 0 SLEN BISNC TLPO TLP
Register 5-24 CCR2H
Channel Configuration Register 2 (Hi gh Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 1BH6BH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
misc.
HMCS EPT NPRE(1:0) ITF 0 OIN XCRC
A0000000FLON
B0 EPT NPRE(1:0) ITF 0 CAPP CRCM
PEB 20542
PEF 20542
Register Descripti on (CCR2H)
Preliminary Data Sheet 5-161 08.99
MDS(1:0) Mode Select (hdlc modes)
This bit field selects the HDLC protocol sub-mode including the
’extended transpar ent mode ’ .
MDS = ’00’ Automode.
MDS = ’01’ Address Mode 2.
MDS = ’10’ Address Mode 0/1.
(Opt io n ’0’ or ’1’ is sele c ted vi a bit ’ADM’. )
MDS = ’11’ Extended transparent mode (bit transparent transmission/
reception).
Note: ’MD S(1:0) ’ mu st be set t o ’10’ if any PPP mo de is enabled via b it
field ’PPPM’ or if SS7 is enabled via bit ’ESS7’ in register CCR3L.
ADM Address Mode Select (hdlc modes)
The meaning of this bit depends on the selected protocol sub- mod e:
Automode, Address Mode 2:
Determine s the address field len gth of an HDLC frame.
ADM = ’0’ 8-bit address f ield.
ADM = ’1’ 16-bit address field.
Address Mode 0/1:
Determines whether address mode 0 or 1 is selected.
ADM = ’0’ Ad dress Mode 0 (no address recognit ion ).
ADM = ’1’ Ad dress Mode 1 (high byte addre ss reco gni tion) .
Extended Transparent Mode:
ADM = ’1’ recommended setting
NRM Normal Response Mode (hdlc modes)
This bit is valid in HDLC Automode operation only and determines the
function of the Automode LAP-Controller:
NRM = ’0’ Full-d uplex LAP-B / LAP-D operation.
NRM = ’1’ Hal f-dup lex normal response mode (NRM) oper ation.
PEB 20542
PEF 20542
Register Descripti on (CCR2H)
Preliminary Data Sheet 5-162 08.99
PPPM(1:0) PPP Mode Select (hdlc modes)
This bit field enables and selects the HDLC PPP protocol modes:
PPPM = ’00’ No PPP protocol operation. The HDLC sub-m ode is
determined by bit field ’MDS’.
PPPM = ’01’ Octet synchronous PPP protocol operation.
PPPM = ’10’ Asynchronous PPP protoco l operation.
Bit ’B CR’ in re gister CCR0L must be set to ensure proper
asynchronous reception.
PPPM = ’11’ Bit synchronous PPP protocol operation.
Note: ’Address Mode 0’ m ust be selected by set ting bit field ’MDS(1:0)’
to ’10’ and bi t ’ADM’ to ’0’ if a ny PPP mode is enabled.
TLPO Test Loop Out Functi on (all mod es)
This bit is only valid if test loop is enabled and controls whether test loop
transmit data is driven on pin TxD:
TLPO = ’0’ Te st loop transm it data is driven to TxD pin.
TLPO = ’1’ Test loop transmit data is N OT driven to TxD pin. TxD pin
is idle ’1’. Depending on the selected output characteristic
the pin is high impedance (bit CCR1L.ODS =’0’) or driving
high (CCR1L.ODS =’1’ ).
TLP Test Loop (all mod es)
This bit controls the internal test loop between transmit and receive data
signals. The test loop is closed at the far end of serial transmit and
receive line just before the respective TxD and RxD pins:
TLP = ’0’ Test loop disabled.
TLP = ’1’ Test loop enabled.
The software is responsible to select a clock mode which
allows correct reception of transmit data depending on the
external clock supply. Transmit data is sent out via pin
TxD if not d isa bled with bit ’TLPO’. The receive input pin
RxD is internally disconnected during test loop operation.
PEB 20542
PEF 20542
Register Descripti on (CCR2H)
Preliminary Data Sheet 5-163 08.99
SLEN SYNC Character Length (bisync mode)
This bit se lects the SYNC character length in BISYNC/MONOSYNC
operation mode:
SLEN = ’0’ 6 bit (MONOSYNC), 12 bit (BISYNC).
SLEN = ’1’ 8 bit (MONOSYNC), 16 bit (BISYNC).
BISNC Sele ct MO NOSYNC/BISYNC Mode (bisync mode)
This bit selects BISYNC or MONOSYNC operati on mode:
BISNC = ’0’ MONOSYNC mode.
BISNC = ’1 ’ BI SYNC mode.
MCS Modul o Count Select (hdl c mod es)
This bit is valid in HDLC Automode operation only and determines the
control field format:
MCS = ’0’ Basic operation, one byte control field (modulo 8 counter
operation).
MCS = ’1’ Exten ded opera tion, two bytes control field (modu lo 128
count er operat ion).
EPT Enable Preamble Transmission (hdlc/bisync mode)
This bit enables preamble transmission. The preamble is started after
interframe time fill (ITF) transmission is stopped because a new frame is
ready to be transmitted. The preamble pattern consists of 8 bits defined
in register PREAMB, which is sent repetitively. The number of repetitions
is determined by bit field ’PRE(1:0)’:
EPT=’0’ Preambl e transmission is disabled.
EPT=’1’ Preamble transmis sion is enabled.
Note: Preamble operation does NOT influence HDLC shared flag
transmission if enabled.
PEB 20542
PEF 20542
Register Descripti on (CCR2H)
Preliminary Data Sheet 5-164 08.99
NPRE(1:0) Number of Preamble Repetitions (hdlc/bisync mode)
This bit field determines th e numbe r of preambles transm itted:
NPRE = ’00’ 1 pream ble.
NPRE = ’01’ 2 pream bles.
NPRE = ’10’ 4 pream bles.
NPRE = ’11’ 8 pream bles.
ITF Interframe Time Fill (hdlc/bisync mode)
This bit selects the idle state of the transmit pin TxD:
ITF=’0’ Continuous logical ’1’ is sent during idle phase.
ITF=’1’ HDLC Mode:
Continuous flag sequences are sent (’01111110’ flag
pattern).
BISYNC Mode:
Con tinuous SYN charact ers are output.
Note: It is recommended to clear bit ’ITF’ in bus configuration modes, i.e.
continuous ’1’s are sent as idle sequence and data encoding is
NRZ.
OIN One Ins e rt io n (hdlc mode)
In HDLC mode a one-insertio n mech anis m similar to the zero-inser tion
can be activated :
OIN=’0’ The ’1’ insertion mechanism is disabled.
OIN=’1’ In transmit direction a logical ’1’ is inserted to the serial
data stream after 7 consecutive zeros.
In receiv e direction a ’1’ is deleted from the receive data
stream after receiving 7 consecut ive zeros.
This ena bles clock informat ion to be recovered from the
receive data stream by means of a DPLL, even in the case
of NRZ data encoding, because a transition at bit cell
boundary occurs at least every 7 bits.
PEB 20542
PEF 20542
Register Descripti on (CCR2H)
Preliminary Data Sheet 5-165 08.99
XCRC Transmit CRC Checking Mode (hdlc mode)
XCRC=’0’ The transmit checksum (2 or 4 bytes) is generated and
appended to the transmit data automatical ly.
XCRC=’1’ The transmit checksum is not generated automatically.
The checksum is expected to be provided by software as
the last 2 or 4 bytes in the transm it data buffe r.
FLON Flow Contr ol Enable (async mode)
In ASYNC mode, in-band flow control is supported:
FLON=’0’ No automatic in-band flow-control is performed. However
recog niti on of a flow control charac ter (XON/XO FF)
causes always a maskable inter rupt event.
FLON=’1’ Automatic in-band flow-control is performed.
Reception of a XOFF character (defined in register XNXF)
turns off the transmitter after the currently transmitted
chara cte r has been shifted out comp letely (XO FF state).
Reception of a XO N character (defined in register XNXF)
resumes the transmitter from XOFF into XON state ready
to send available transmit data bytes.
The current flow contro l state is indicated via bit ’FCS’ in
regist er Star.
Any transmitter reset switches the flow-control logic to
XON state.
CAPP CRC Append (bisync mode)
In BISYNC mode the CRC generator can be activated:
CAPP = ’0’ No CRC generation/checking is acti ve in BISYNC m ode.
CAPP = ’1’ The CRC generator is activated:
1. The CRC generator is initialized every time the
transmission of a new ’frame’ starts. The CRC
initialization value can be selected via bit ’CRL’ in
re gis te r CCR2 (for BISYNC operat io n).
2. The CRC is automatically to the l ast transmitted data of
a ’frame’.
PEB 20542
PEF 20542
Register Descripti on (CCR2H)
Preliminary Data Sheet 5-166 08.99
CRCM CRC Mode Select (bisync mode)
In BISYNC mode the CRC generator can be configured for tw o different
generator polynom s:
CRCM = ’0’ CRC-16:
The polynominal is x16+x15+x2+1.
CRCM = ’1’ CRC-CCITT:
The polynominal is x16+x15+x5+1.
PEB 20542
PEF 20542
Register Description (CCR3L)
Preliminary Data Sheet 5-167 08.99
Register 5-25 CCR3L
Channel Configuration Register 3 (Low Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 1CH6CH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
misc.
HELC AFX CSF SUET RAC 0 0 ESS7
ATCDE 0 CHL(1:0) RAC DXS XBRK STOP
BTCDE SLOAD CHL(1:0) RAC 0 0 STOP
Register 5-26 CCR3H
Channel Configuration Register 3 (Hi gh Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 1DH6DH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
misc.
H0 DRCRC RCRC RADD 0 0 RFTH(1:0)
APAR(1:0) PARE DPS RFDF 0 RFTH(1:0)
BPAR(1:0) PARE DPS RFDF 0 RFTH(1:0)
PEB 20542
PEF 20542
Register Descripti on (CCR3H)
Preliminary Data Sheet 5-168 08.99
ELC Enable Length Check (hdlc mode)
This bit is only valid in HDLC SS7 mode:
If t he num ber of received octets excee ds 272 + 7 within one Signaling
Unit, reception is aborted and bit RSTA.RAB is set.
ELC=’0’ Length Check disabled.
ELC=’1’ Length Check enabled.
TCDE Termination Character Detection Enable (async/b isy nc mod e s)
This bit is valid in ASYNC/BISYNC modes only and enables/disables the
termination char act er detect ion mechan ism:
TCDE = ’0’ No receive termination character detection is performed.
TCDE = ’1’ The termination character detection is enabled. The
receive dat a stream is monitored for the occurence of a
termination character (TC) programmed via register TCR.
When this character is detecte d, a ’TCD’ interrupt is
generated to the CPU (unless masked).
Note: If the programmed character length (bit field
’CHL(1:0)’) is less than 8 bits, the most significant
unused bits in register TCR must be set to ’0’.
Otherwise no termination character will be
detected.
AFX Automatic FISU Transmission (hdlc mode)
This bit is only valid in HDLC SS7 mode:
After the contents of the transmit FIFO (XFIFO) has been transmit ted
completely, FISUs are transmited automatically. These FISUs contain
the FSN and BSN of t he last transmi tted Signal ing Unit (provided i n
XFIFO).
AFX=’0’ Automatic FISU transmission disabled.
AFX=’1’ Automatic FISU transmission enabled.
PEB 20542
PEF 20542
Register Descripti on (CCR3H)
Preliminary Data Sheet 5-169 08.99
SLOAD Enable SYN Character Load (bisync mode)
In BISYNC mode, SYN characters might be f i ltered out or stored to the
SCC receive FIFO.
SLOAD=’0’ SYN characters are filtered out and not stored in the
receive FIFO.
SLOAD=’1’ All received charact er s, including SYN charact ers, are
stored in the receive FIFO.
CSF Compare Status Field (hdlc mode)
This bit is only valid in HDLC SS7 mode:
If t he st atu s fields of consecutive LSSUs are equa l, only the first will be
stored and every follow ing is ignored
CSF=’0’ Compare is disabled, all received LSSUs are stored in the
receive FIFO.
CSF=’1’ Compar e is enabled , only the first one of consecutive
equal LSSUs is stored in the receive FIFO.
SUET Signalling Unit Counter Threshold (hdlc mode)
This bit is only valid in HDLC SS7 mode:
Def ines the number of signaling units r eceived in error that will cause an
error rate high indication (ISR1.SUEX).
SUET=’0’ threshol d is 64 errored signaling uni ts.
SUET=’1’ threshol d is 32 errored signaling uni ts.
CHL(1:0) Character Length (async/bisync mod es)
This bit field selects the number of data bits within a character:
CHL = ’00’ 8-bit data.
CHL = ’01’ 7-bit data.
CHL = ’10’ 6-bit data.
CHL = ’11’ 5-bit data.
RAC Recei ver active (all mod es)
Switches the receiver between operational /inoperat ion al states:
RAC=’0’ Receiv er inactive , receive line is ignored.
RAC=’1’ Receiv er active.
PEB 20542
PEF 20542
Register Descripti on (CCR3H)
Preliminary Data Sheet 5-170 08.99
DXS Disable Storage of XON/ XOFF Characte rs (async mo de)
In ASYNC mode, XON/XOFF characters might be filtered out or stored
to the SC C rec eive FIFO:
DXS=’0’ All received characters including XON/XOFF characters
are stored in the receiv e FIFO.
DXS=’1’ XO N /X OFF cha racter s are filtered out and not stored in
the recei ve FIFO.
XBRK Transmit Break (async mode)
XBRK=’0’ Nor mal transmit operation.
XBRK=’1’ Forces the TxD pin to ’low’ level immediately (break
condi tion) , regardless of any charact er being current ly
transmitted. This command is executed immediately with
the next rising edge of the transmit clock and further
transmission is disabled. The currently sent character is
lost.
Data stored in the SCC transmit FIFO will be sent as soon
as the break condition is cleared (XBRK=’0’). A transmit
reset command (bit ’XRES’ in register CMDRL) does NOT
clea r the break condit ion automat ica lly.
ESS7 Enable SS7 Mode (hdlc mode)
This bit is only valid in HDLC mode only.
ESS7=’0’ Disable signaling system #7 (SS7) support.
ESS7=’1’ Enable signaling system #7 (SS7) support.
Note: If SS7 mode is enabled, ’Address Mode 0’ must be selected by
setting bit field CCR2L:MDS(1:0) to ’10’ and bit CCR2L:ADM to ’0’.
STOP Stop Bit number (async mode)
This bit selects the number of stop bits per ASYNC character:
STOP=’0’ 1 stop bit per character.
STOP=’1’ 2 stop bits per character.
PEB 20542
PEF 20542
Register Descripti on (CCR3H)
Preliminary Data Sheet 5-171 08.99
PAR(1:0) Parity Format (async mode)
This bit field selects the parity gene ratio n/ch ecki ng mo de:
PAR = ’00’ SPACE (’0’), a consta nt ’0’ is inserted as parity bit.
PAR = ’01’ Odd parity.
PAR = ’10’ Even parity.
PAR = ’ 11’ MAR K (’1’), a constant ’1’ is inserted as parity bit.
The received parity bit is stored in the SCC receive FIFO depending on
the selected cha ract er format:
• as leading bit im mediately preceding the data bits if cha racter length
is 5, 6 or 7 b its and bit ’DPS’ is cleared (’0’).
• as LSB of the status byte belonging to the character if character length
is 8 bits and the corresponding receive FIFO data format is s elected
(bit ’RFDF’ = ’1 ’).
A parity error is indicated in the MSB of the status byte belonging to each
character if enabled. In addition, a parity error interrupt can be
generated.
DRCRC Disable Receive CRC Checking (hdlc mode)
DRCRC=’0’ The rece iv e r exp e c ts a 16 or 32 bit CRC withi n a HDLC
frame. CRC pro cessing depends on the setting of bit
’RCRC’.
Frames shorter than expected are marked ’invalid’ or are
discarded (refer to RSTA desc ription) .
DRCRC=’1’ The rece iv e r doe s not expec t a n y CRC wit hi n a HDLC
frame. The criteria for ’valid frame’ indication is updated
accor din gly (refer to RSTA description).
Bit ’RCRC’ is ignored.
RCRC Receive CRC Checking Mode (hdlc mode)
RCRC=’0’ The received checksum is evaluated, but NOT forwarded
to the receive FIFO.
RCRC= ’1 ’ Th e received checksum (2 or 4 bytes) is evaluat ed and
forwarded to the receive FIFO as data.
PARE Parity Enable (async mode)
PARE=’0’ P arity generation/c hecki ng is disab led.
PARE=’1’ P arity generation/c hecki ng is enable d.
PEB 20542
PEF 20542
Register Descripti on (CCR3H)
Preliminary Data Sheet 5-172 08.99
RADD Receive Address Forward to RFIFO (hdlc mode)
This bit is only valid
– if an HDLC sub-mode with address field support is selected
(Automode, Address Mode 2, Address Mode 1)
– in SS7 mode
RADD=’0’ The received HDLC address field (either 8 or 16 bit,
depending on bit ’ADM’) is evaluated, but NOT forwarded
to the receive FIFO.
In SS7 mode, the signaling unit fields ’FSN’ and ’BSN’ are
NOT forwarded to the receive FIFO.
RADD=’1’ The received HDLC address field (either 8 or 16 bit,
depending on bit ’ADM’) is evaluated and forwarded to the
receive FIFO.
In SS7 mode, the signaling unit fields ’FSN’ and ’BSN’ are
forwa rded to the receive FIFO.
DPS Data Parity Storage (as ync mo de)
Only valid if parity generation/checking is enabled via bit ’PARE’:
DPS=’0’ The parity bit is stored.
DPS=’1’ The parity bit is not stored in the data byte containing
chara cte r data.
The parity bit is always stored in the status byte.
PEB 20542
PEF 20542
Register Descripti on (CCR3H)
Preliminary Data Sheet 5-173 08.99
RFDF Receive FIFO Data Format (async/ bisync mode)
In ASYNC mode, the character format is determined as follows:
Char5
P
Data Byte:
0457
Char6
P
0657
Char7
P
0
6
7
Char8
07
RFDF='0'
(no parity bit stored)
Char5
P
Data Byte (DB):
0457
Char6
P
0657
Char7
P
0
6
7
Char8
07
RFDF='1'
(no parity bit stored)
Status Byte (SB):
PE
0
6
7
FE P
PE
067
FE P
PE
0
6
7
FE P
PE
067
FE P
P
: Parity bit stored in data byte (can be disabled via bit 'DPS')
PE: Parity Error
FE: Fram e Error
P: Parity bit stored in status byte
PEB 20542
PEF 20542
Register Descripti on (CCR3H)
Preliminary Data Sheet 5-174 08.99
RFTH(1:0) Receive FIFO Threshold (all mod es)
This bit field defines the level up to which the SCC receive FIFO is filled
with valid data before an ’RPF’ interrupt is generated.
(In case of a ’frame end / block end’ condition the MISTRAL notifies the
CPU immediat ely, disreg arding th is threshold .)
The meaning depends on the selected protocol engine:
HDLC Modes:
RFTH(1:0) Threshold level in number of data bytes.
’00’ 32 byte
’01’ 16 byte
’10’ 4 byte
’11’ 2 byte
ASYNC/BISYNC Mode:
RFTH(1:0) Threshold level in number of data bytes (DB) and status
byte s (SB) depending on bit ’RFDF’:
RFDF = ’0’ RFDF = ’1’
’00’ 1 DB 1 DB + 1 SB
’01’ 4 DB 2 DB + 2 SB
’10’ 1 6 DB 8 DB + 8 SB
’11’ 3 2 DB 16 DB + 16 SB
PEB 20542
PEF 20542
Register Description (PREAMB)
Preliminary Data Sheet 5-175 08.99
Reg ister 5-27 PREA M B
Preamble Regis ter
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 1EH6EH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Preamble Pattern
HPRE(7:0)
A00000000
BPRE(7:0)
PRE(7:0) Preamble (hdlc/bisync modes)
This bit field determines the preamble pattern which is send out during
preamble transm i ssi on.
Note: In HDLC-mode, zero-bit insertion is disabled during preamble
transmission.
PEB 20542
PEF 20542
Register Description (TOLEN)
Preliminary Data Sheet 5-176 08.99
Reg ister 5-28 TOLEN
Time Out Length Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 1FH6FH
typical usage: written by CPU; read and evaluated by MISTRA L
Bit76543210
Mode
Time Out Length
H00000000
ATOIE TOLEN(6:0)
B00000000
TOIE Tim e Out Indication Enable (async mode)
If this bit is set to ’1’ in ASYNC mode, any time out event will
aut oma tical ly generate a ’RFRD ’ comm and thu s inserting a ’block end’
indication into the RF IF O. This time-out condi tion is indicated wit h the
’TIME’ interrupt (if unmasked).
TOIE = ’0’ Automatic Time Out processing disabled.
TOIE = ’1’ Automatic Time Out processing enabled.
TOLEN(6:0) Time Out Length (async mode)
This bit field determines th e time out period. If there is no receive line
activity for the configured period of time, a time out indication is
generated if enabled via bit ’TOIE’.
The period of time is programmable in multipl es of character fram e
length <CFL> time equivalents including start, parity and stop bits (refer
to Figure 4-9):
TOLEN T = ((TOLEN + 1) * 4) * <CFL>
PEB 20542
PEF 20542
Register Description (ACCM0)
Preliminary Data Sheet 5-177 08.99
Register 5-29 ACCM0
PPP ASYNC Contr ol Character Map 0
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 20H70H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
ASYNC Character Control M ap 07..00
H07 06 05 04 03 02 01 00
A00000000
B00000000
Register 5-30 ACCM1
PPP ASYNC Contr ol Character Map 1
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 21H71H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
ASYNC C haracter Control Map 0F..08
H0F 0E 0D 0C 0B 0A 09 08
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (ACCM2)
Preliminary Data Sheet 5-178 08.99
Register 5-31 ACCM2
PPP ASYNC Contr ol Character Map2
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 22H72H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
ASYNC Character Control M ap 17..10
H17 16 15 14 13 12 11 10
A00000000
B00000000
Register 5-32 ACCM3
PPP ASYNC Contr ol Character Map 3
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 23H73H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
ASYNC C haracter Control Map 1F..18
H1F 1E 1D 1C 1B 1A 19 18
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (ACCM3)
Preliminary Data Sheet 5-179 08.99
ACCM ASYNC Character Cont rol Map (hdlc mod es)
This bit field is valid in HDLC asynchronous and octet-synchronous PPP
mode only:
Each bit selects the correspondi ng char act er (indicated as hex val ue
1FH..00H in the register description table) as control character which has
to be mapped into the transmit data stream.
PEB 20542
PEF 20542
Register Descripti on (UDAC0)
Preliminary Data Sheet 5-180 08.99
Register 5-33 UDAC0
User Defined PPP ASYNC Control Character Map 0
CPU Acc e ssibilit y : read/write
Reset Value: 7EH
Channel A Channel B
Offs et Address: 24H74H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
ASYNC Character 0
HAC0
A00000000
B00000000
Register 5-34 UDAC1
User Defined PPP ASYNC Control Character Map 1
CPU Acc e ssibilit y : read/write
Reset Value: 7EH
Channel A Channel B
Offs et Address: 25H75H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
ASYNC Character 1
HAC1
A00000000
B00000000
PEB 20542
PEF 20542
Register Descripti on (UDAC2)
Preliminary Data Sheet 5-181 08.99
Register 5-35 UDAC2
User Defined PPP ASYNC Control Character Map 2
CPU Acc e ssibilit y : read/write
Reset Value: 7EH
Channel A Channel B
Offs et Address: 26H76H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
ASYNC Character 2
HAC2
A00000000
B00000000
Register 5-36 UDAC3
User Defined PPP ASYNC Control Character Map 3
CPU Acc e ssibilit y : read/write
Reset Value: 7EH
Channel A Channel B
Offs et Address: 27H77H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
ASYNC Character 3
HAC3
A00000000
B00000000
PEB 20542
PEF 20542
Register Descripti on (UDAC3)
Preliminary Data Sheet 5-182 08.99
AC3. .0 User Define d ASYNC Charac ter Cont rol Map (hdlc mode)
This bit field is valid in HDLC asynchronous and octet-synchronous PPP
mode only:
These bit fields define user determined characters as control characters
which have to be mapped into the transm it data stream.
In register ACCM only characters 00H..1FH can be selected as control
charact ers. Re gister UDAC allows to spe cify any fo ur charact ers in t he
range 00H..FFH .
The default value is a 7EH flag which must be always mapped. Thus no
additional char acter is mappe d if 7EH ’s are programe d to bit fields
AC3...0 (reset value).
(7EH is mapped automat ica lly, even if not defined via a AC bit fi el d.)
PEB 20542
PEF 20542
Register Description (TTSA0)
Preliminary Data Sheet 5-183 08.99
Reg ister 5-37 TTSA0
Transmit Time Slot Assignment Register 0
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 28H78H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Tx Cloc k S hift
H00000 TCS(2:0)
A00000000
B00000000
Reg ister 5-38 TTSA1
Transmit Time Slot Assignment Register 1
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 29H79H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Tx Time Slot Number
HTEPCM TTSN(6:0)
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (TTSA2)
Preliminary Data Sheet 5-184 08.99
Reg ister 5-39 TTSA2
Transmit Time Slot Assignment Register 2
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 2AH7AH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Transmit Channel Capacity
HTCC(7:0)
A00000000
B00000000
Reg ister 5-40 TTSA3
Transmit Time Slot Assignment Register 3
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 2BH7BH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Transmit Channel Capacity
H0000000TCC8
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (TTSA3)
Preliminary Data Sheet 5-185 08.99
The following register bit fields allow flexible assignment of bit- or octet-aligned transmit
time-slots to the serial channel. For more detailed information refer to chapters "Clock
Mode 5a (Time Slot Mode)" on page 3-55 and "Clock Mode 5b (Octet Sync Mode)" on
page 3-62.
TCS(2:0) Transmit Clock Shift (hdlc modes)
This bit field determines th e transm it clock shift.
TEPCM Enable PCM Mask Transmit (hdlc modes)
This bit selects the additional Transmi t PCM Mask (refe r to register
PCMTX0..PCMTX3):
TEPCM=’0’ Standa rd time-slot configuration .
TEPCM=’1’ The time-slot width is constant 8 bit, bit fields ’TTSN’ and
’TCS’ determine the offset of the PCM mask and ’TCC’ is
igno red. Each time -slot selec ted via register
PCMTX0..PCMTX3 is an active transmit times lot.
TTSN(6:0) Transmit Time Slot Number (hdl c mod es)
This bit field selects the start position of the timeslot in time-slot
configuration mode (clock mode 5a/5b):
Offset = 1+TTSN*8 + TCS (1..1024 clocks)
TCC(8:0) Transmi t Channel Capacity (hdlc mode s)
This bit field determines the transmit time-slot width in standard time-slot
configuration (bit TEPCM=’0’):
Number of bits = TCC + 1, ( 1. . 512 bi ts/time- sl ot)
PEB 20542
PEF 20542
Register Description (RTSA0)
Preliminary Data Sheet 5-186 08.99
Reg ister 5-41 RTSA0
Receive Time Slot Assignment Register 0
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 2CH7CH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Rx Clock Shift
H00000 RCS(2:0)
A00000000
B00000000
Reg ister 5-42 RTSA1
Receive Time Slot Assignment Register 1
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 2DH7DH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Rx Time Slot Number
HREPCM RTSN(6:0)
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (RTSA2)
Preliminary Data Sheet 5-187 08.99
Reg ister 5-43 RTSA2
Receive Time Slot Assignment Register 2
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 2EH7EH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Receive Channel Capac ity
HRCC(7:0)
A00000000
B00000000
Reg ister 5-44 RTSA3
Receive Time Slot Assignment Register 3
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 2FH7FH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Receive Channel Capac ity
H0000000RCC8
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (RTSA3)
Preliminary Data Sheet 5-188 08.99
The following register bit fields allow flexible assignment of bit- or octet-aligned receive
time-slots to the serial channel. For more detailed information refer to chapters "Clock
Mode 5a (Time Slot Mode)" on page 3-55 and "Clock Mode 5b (Octet Sync Mode)" on
page 3-62.
RCS(2:0) Receive Clock Shift (hdlc mode s)
This bit field determines th e receive clock shi f t.
REPCM Enable PCM Mask Receive (hdlc modes)
This bit selects the additional Receive PCM Mask (refer to register
PCMRX0..PCMRX3):
REPCM=’0’ St andard time-slot conf iguration .
REPCM=’1’ The ti me-slot width is constant 8 bi t, bit f ields ’RTSN’ and
’RCS’ determine the offset of the PCM mask and ’RCC’ is
igno red. Each time -slot selec ted via register
PCMRX0..PCMRX3 is an active receive timeslot.
RTSN(6:0) Receive Time Slot Number (hdlc modes)
This bit field selects the start position of the timeslot in time-slot
configuration mode (clock mode 5a/5b):
Offset = 1+RTSN*8 + RC S (1..1024 clocks)
RCC(8:0) Receive Channel Capacity (hdlc modes)
This bit field determines the receive time-slot width in standard time-slot
configuration (bit REPCM=’0’):
Number of bits = RCC + 1, (1..512 bits/time-slot)
PEB 20542
PEF 20542
Register Description (PCMTX0)
Preliminary Data Sheet 5-189 08.99
Reg ister 5-45 PCM TX0
PCM Mask Transmit Direct ion Register 0
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 30H80H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
PCM Mask for Transmit Direction
HT07 T06 T05 T04 T03 T02 T01 T00
A00000000
B00000000
Reg ister 5-46 PCM TX1
PCM Mask Transmit Direct ion Register 1
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 31H81H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
PCM Mask for Transmit Direction
HT15 T14 T13 T12 T11 T10 T09 T08
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (PCMTX2)
Preliminary Data Sheet 5-190 08.99
Reg ister 5-47 PCM TX2
PCM Mask Transmit Direct ion Register 2
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 32H82H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
PCM Mask for Transmit Direction
HT23 T22 T21 T20 T19 T18 T17 T16
A00000000
B00000000
Reg ister 5-48 PCM TX3
PCM Mask Transmit Direct ion Register 3
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 33H83H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit151413121110 9 8
Mode
PCM Mask for Transmit Direction
HT31 T30 T29 T28 T27 T26 T25 T24
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (PCMTX3)
Preliminary Data Sheet 5-191 08.99
PCMTX PC M Mask for Transmit Direction (hdlc mode)
This bit field is valid in HDLC clock mode 5 only and the PCM mask must
be enabled via bit ’TEPCM’ in register TTSA1.
Each bit selects one of 32 (8-bit) transmit time-slots. The offset of time-
slot zero to the frame sync pulse can be programmed via register TTSA1
bit field ’TTSN’.
PEB 20542
PEF 20542
Regist er Descript ion (PCMRX0)
Preliminary Data Sheet 5-192 08.99
Reg ister 5-49 PCM R X0
PCM Mask Receive Direction Register 0
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 34H84H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
PCM Mask for R e ceiv e Direction
HT07 T06 T05 T04 T03 T02 T01 T00
A00000000
B00000000
Reg ister 5-50 PCM R X1
PCM Mask Receive Direction Register 1
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 35H85H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit151413121110 9 8
Mode
PCM Mask for R e ceiv e Direction
HT15 T14 T13 T12 T11 T10 T09 T08
A00000000
B00000000
PEB 20542
PEF 20542
Regist er Descript ion (PCMRX2)
Preliminary Data Sheet 5-193 08.99
Reg ister 5-51 PCM R X2
PCM Mask Receive Direction Register 2
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 36H86H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
PCM Mask for R e ceiv e Direction
HT23 T22 T21 T20 T19 T18 T17 T16
A00000000
B00000000
Reg ister 5-52 PCM R X3
PCM Mask Receive Direction Register 3
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 37H87H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit151413121110 9 8
Mode
PCM Mask for R e ceiv e Direction
HT31 T30 T29 T28 T27 T26 T25 T24
A00000000
B00000000
PEB 20542
PEF 20542
Regist er Descript ion (PCMRX3)
Preliminary Data Sheet 5-194 08.99
PCMRX PCM Mask for Receive Direction (hdlc mode)
This bit field is valid in HDLC clock mode 5 only and the PCM mask must
be enabled via bit ’REPCM’ in register RTSA1.
Each bit selects one of 32 (8-bit) receive time-slots. The offset of time-
slot zero to the frame sync pulse can be programmed via register RTSA1
bit field ’RTSN’.
PEB 20542
PEF 20542
Register Descripti on (BRRL)
Preliminary Data Sheet 5-195 08.99
Register 5-53 BRRL
Baud Rate Register (Low Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 38H88H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Baud Rate Generator Factor N
H0 0 BRN(5:0)
A0 0 BRN(5:0)
B0 0 BRN(5:0)
Register 5-54 BRRH
Baud Rate Register ( H igh Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 39H89H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Ba ud Rate Generator Factor M
H0000 BRM(3:0)
A0000 BRM(3:0)
B0000 BRM(3:0)
PEB 20542
PEF 20542
Register Description (BRRH)
Preliminary Data Sheet 5-196 08.99
BRM(3:0) Baud Rate Factor ’M ’ (all mod es)
BRN(5:0 ) Baud Rate Factor ’N’ (all mod es)
These bi t fields determi ne the divisi on factor of the internal baud rate
generator. The baud rate generator input clock and the usage of baud
rate generator output depe nds on the select ed clock mo de.
The division factor k is calculated by:
with M=0..15 and N=0..63.
kN1
+()
2M
×=
fBRG fin k
⁄=
PEB 20542
PEF 20542
Register Description (TIMR 0)
Preliminary Data Sheet 5-197 08.99
Reg ister 5-55 TIMR0
Ti mer Re g ister 0
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 3AH8AH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Time r Value
HTVALUE(7:0)
ATVALUE(7:0)
BTVALUE(7:0)
Reg ister 5-56 TIMR1
Ti mer Re g ister 1
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 3BH8BH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Time r Value
HTVALUE(15:0)
ATVALUE(15:0)
BTVALUE(15:0)
PEB 20542
PEF 20542
Register Description (TIMR 2)
Preliminary Data Sheet 5-198 08.99
Reg ister 5-57 TIMR2
Ti mer Re g ister 2
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 3CH8CH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Time r Value
HTVALUE(23:16)
ATVALUE(23:16)
BTVALUE(23:16)
Reg ister 5-58 TIMR3
Ti mer Re g ister 3
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 3DH8DH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Timer Configuration
HSRC 0 0 TMD 0 CNT(2:0)
ASRC0000 CNT(2:0)
BSRC0000 CNT(2:0)
PEB 20542
PEF 20542
Register Description (TIMR 3)
Preliminary Data Sheet 5-199 08.99
SRC Clock Source (valid in clock mode 5 only) (all mod es)
This bit selects the clock source of the internal timer:
SRC = ’0’ The timer is clocked by the effective transm it clock.
SRC = ’1’ The timer is clocked by the frame-sync synchronization
signal supplied via the FSC pin in clock mode 5.
TMD Timer Mode (hdlc modes)
This bit must be set to ’1’ if HDLC Automode operation is selected. In all
other protocol modes it mus t remain ’0’:
TMD=’0’ The timer is controlled by the CPU via access to registers
CMDRL and TIMR0..TIMR3.
The timer can be starte d any time by setting bit ’STI’ in
regist er CMDRL. After the timer has expired it generates
a timer interrupt . The timer can be stopped any time by
setting bit ’TRES’ in register CMDRL to ’1’.
TMD=’1’ The timer is used by the MISTRAL f or proto col speci fic
time-out and retry transactions in HDLC Automode.
CNT(2:0) Counter (all mod es)
The meaning of this bit field depends on the selected protocol mode.
In HDLC Automode, with bit TMD=’1’:
• Retry Counter (in HDL C proto col know n as ’N2’):
Bit fie ld ’CNT’ indicates the number of S-Com mand frames (with poll
bit set) wh ich a re trans mitted autonomously b y MISTR AL after ever y
expiration of the time out period ’t’ (determined by ’TVALUE’), in case
an I-Frame gets not acknowledged by the opposite station. The
maximum value is 6 S-command frames. If ’CNT’ is set to ’7’, the
number of S-commands is unlimited in case of no acknowledgement.
In all other modes, with bit TMD=’0’:
• Restart Co unter :
Bit field ’CNT’ indicates the number of automatic restarts which are
performed by MISTRAL after every expiration of the time-out period
’t’, in case the timer is not stopped by setting bit ’TRES’ in register
CMDRL t o ’1 ’. Th e m axi mum va lu e i s 6 re st ar ts. If ’C NT ’ is s et t o ’7 ’,
a timer interrupt is generated periodically with time period ’t’
determined by bi t field ’TVALUE’.
PEB 20542
PEF 20542
Register Description (TIMR 3)
Preliminary Data Sheet 5-200 08.99
TVALUE
(23:0) Timer Expiration Value (all mod es)
This bit field determines th e timer expiratio n period ’t’:
(’CP’ is the clock period, depending on bit ’SRC’.)
tTVALUE1
+()
CP
⋅=
PEB 20542
PEF 20542
Regist e r Description (XAD1)
Preliminary Data Sheet 5-201 08.99
Reg ister 5-59 XAD1
Transmit Address 1 Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 3EH8EH
typical usage: written by CPU; read and evaluat ed by MISTRA L
Bit76543210
Mode
Transmit Address ( h igh)
HXAD1 (high byte) 0 XAD1_0
or XAD1 (COM MAND )
A00000000
B00000000
Reg ister 5-60 XAD2
Transmit Address 2 Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 3FH8FH
typical usage: written by CPU; read and evaluat ed by MISTRA L
Bit76543210
Mode
Transmit Address ( low)
HXAD2 (low byte)
or XAD2 (RESPONSE)
A00000000
B00000000
PEB 20542
PEF 20542
Regist e r Description (XAD2)
Preliminary Data Sheet 5-202 08.99
XAD1 and XAD2 bit fields are valid in HDLC modes with automatic address f ield
handling only (Automode, Address Mode 1, Non-Automode). They can be programmed
with one individu al address byte w hic h is inserted automa tically into the address field
(8 or 16 bit) of a HDLC transmit frame. The function depends on the selected protocol
mode and addr ess field size (bit ’ADM’ in register CCR2L).
XAD1 Transmit Address 1 ( hdl c mod es)
– 2-byte address field:
Bit field XAD1 constitutes the high byte of the 2-byte address field. Bit
1 must be set to ’0’. According to the ISDN LAP-D protocol, bit 1 is
interpreted as the C/R (COMMAND/RESPONSE) bit. This bit is
manipulated automatically by M ISTRAL according to the setting of bit
’CRI’ in regist er RAH1. The following is the C/R value (on bit 1), when:
- transmitting COMMANDs: ’1’ (if ’CRI’=’1’) ; ’0’ (if ’CRI’=’0’)
- transmitting RESPONSEs: ’0’ (if ’CRI’= ’1’) ; ’1’ (if ’CRI’=’0’)
(In ISDN LAP-D, the high byte is known as ’SAPI’.)
In a ccor dance wi th th e HD LC protoco l, bit ’XAD1_0’ s houl d be s et t o
’0’, to indicate that the address field contains (at least) one more byte.
– 1-byte address field:
According to the X.25 LAP-B protocol, XAD1 is the address of a
’COMMAND’ frame.
XAD2 Transmit Address 2 ( hdl c mod es)
– 2-byte address field:
Bit fi e ld XAD2 constitu te s the low byte of the 2-byte addr ess field.
(In ISDN LAP-D, the low byte is known as ’TEI’.)
– 1-byte address field:
According to the X.25 LAP-B protocol, XAD2 is the address of a
’RESPONSE’ frame.
PEB 20542
PEF 20542
Regist e r Description (RAL1)
Preliminary Data Sheet 5-203 08.99
Reg ister 5-6 1 R A L1
Receive Address 1 Low Regi st er
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 40H90H
typical usage: written by CPU; read and evaluat ed by MISTRA L
Bit76543210
Mode
Receive Address 1 (low )
HRAL1
RAL1
A00000000
B00000000
Register 5-62 RAH1
Receive Addres s 1 High Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 41H91H
typical usage: written by CPU; read and evaluat ed by MISTRA L
Bit76543210
Mode
Receive Address 1 (high)
HRAH1 CRI RAH1_0
or RAH1
A00000000
B00000000
PEB 20542
PEF 20542
Regist e r Description (RAL2)
Preliminary Data Sheet 5-204 08.99
Reg ister 5-6 3 R A L2
Receive Address 2 Low Regi st er
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 42H92H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Receive Address 2 (low )
HRAL2
A00000000
B00000000
Register 5-64 RAH2
Receive Addres s 2 High Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 43H93H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Receive Address 2 (high)
HRAH2
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (RAH2)
Preliminary Data Sheet 5-205 08.99
In operating modes that provide address recognition, the high/low byte of the received
address is compared with the individually programmable values in register RAH2/
RAL2/RAH1/RAL1.
This addresses can be masked on a per bit basis by setting the correspon ding bits in
register s AMRAL1/AMRAH1/AMRAL2/AMRAH2 to allow extended broadcast address
recognition. This feature is applicable to all HDLC sub-modes with address recognition.
RAH1 Receive Address 1 Byte High (hdl c mod es)
In HDLC Automode bit ’1’ is reserved for ’CRI’ (Comma nd Re sponse
Interpretation ). In all other modes RAH1 is an 8 bit address.
CRI Command/Response Interpretation
The setting of this bit effects the meaning of the ’C/R’ bit in t he receiv e
status byte (RSTA). This status bit ’C/R’ should be interpreted after
reception as follows:
’0’ (if ’CRI’=’1’) ; ’1’ (if ’CRI’=’0’) : COMMAND received
’1’ (if ’CRI’=’1’) ; ’0’ (if ’CRI’=’0’) : RESPONSE received
Note: If 1-byte address field is selected in HDLC Automode, RAH1 must
be set to 0x00
H
.
RAL1 Recei ve Address 1 Byte Low (hdlc modes)
The general functio n and its meaning depe nds on the selected H DL C
operating mode:
•Automode / Address Mode 2 (16-bit address)
RAL1 can be programmed with the value of the first individual low
address byte.
•Automode / Address Mode 2 (8-bit address)
According to X.25 LAP-B pr otocol, the address in RAL1 is considered
as the address of a ’COM MAND ’ frame.
RAH2 Receive Address 2 Byte High (hdl c mod es)
RAL2 Recei ve Address 2 Byte Low (hdlc modes)
Value of the second individually programmable high/low address byte. If
a 1-byte address field is selected, RAL2 is considered as the address of
a ’RESPONSE’ frame according to X.25 LAP-B protocol.
PEB 20542
PEF 20542
Re gister Descr iption (AMRAL1)
Preliminary Data Sheet 5-206 08.99
Reg ister 5-65 AMR AL1
Mask Recei ve Ad dress 1 Low Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 44H94H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Receive Mask Address 1 (low)
HAMRAL1
A00000000
B00000000
Regist er 5-66 AMRAH1
Mask Recei ve Ad dress 1 High Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 45H95H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Receive Mask Address 1 ( high)
HAMRAH1
A00000000
B00000000
PEB 20542
PEF 20542
Re gister Descr iption (AMRAL2)
Preliminary Data Sheet 5-207 08.99
Reg ister 5-67 AMR AL2
Mask Recei ve Ad dress 2 Low Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 46H96H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Receive Mask Address 2 (low)
HAMRAL2
A00000000
B00000000
Regist er 5-68 AMRAH2
Mask Recei ve Ad dress 2 High Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 47H97H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Receive Mask Address 2 ( high)
HAMRAH2
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (AMRAH2)
Preliminary Data Sheet 5-208 08.99
AMRAH2 Receive Mask Address 2 Byte High (hdlc modes)
AMRAL2 Receive Mask Address 2 Byte Low (hdlc mod es)
AMRAH1 Receive Mask Address 1 Byte High (hdlc modes)
AMRAL1 Receive Mask Address 1 Byte Low (hdlc mod es)
Setting a bit in thi s registers to ’1’ masks the corre sponding bi t in
register s RAH2/RAL2/RAH1/RAL1. A masked bit position always
matches when comparing the received frame address with registers
RAH2/RAL2/RAH1/RAL1, all ow ing exte nded broa dcast mec hanism .
bit = ’0’ Th e dedicate d bit position is NOT maske d. This bit
po sition in the received addres s must match w ith the
corresponding bit position in registers RAH2/RAL2/RAH1/
RAL1 to accept the frame.
bit = ’1’ The dedicated bit position is masked. This bit position in
the recei ved addr ess N EED NO T match with the
corresponding bit position in registers RAH2/RAL2/RAH1/
RAL1 to accept the frame.
PEB 20542
PEF 20542
Regist er Description (RLCRL)
Preliminary Data Sheet 5-209 08.99
Register 5-69 RLCRL
Receive Length Check Register (Low Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 48H98H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Receive Length Limit
HRL(7:0)
A00000000
B00000000
Register 5-70 RLCRH
Receive Lengt h Check Registe r (High Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 49H99H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Receive Length Check Control Recei ve Length Limit
HRCE 0000 RL(10:8)
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (RLCRH)
Preliminary Data Sheet 5-210 08.99
RCE Receive Length Check Enable (hdlc modes)
This bit is valid in HDLC mode only and enables/disables the receive
length check function:
RCE = ’0’ No receive le ngt h check on rec e iv e d HDLC fr ame s is
performed.
RCE = ’1’ The receive length check is enabled. All bytes of a H DLC
frame whi ch are trans ferred to the receive FIFO
(depending on the selected protocol sub-mode and
receive CRC handling) are counted and checked against
the m aximum len gth che ck lim it which is progr am med in
bit field ’RL’.
A frame exceed ing the maximum length is treated as if it
were abor ted on the receive line (’RME’ interrupt and bit
’RAB’ (receive abort) set in the RSTA byte).
In addition a ’FLEX’ interrupt is generated prior to ’RME’,
if enabled.
Note: The Receive Status Byte (RSTA) is part of the
frame lengt h checki ng.
RL(10:0) Receive L ength Check Limit (hdlc mod es)
This bit-field defines the receive length check limit (32..65536 bytes) if
checking is enabled via bit ’RCE’:
RL(10:0) The receive length limit is calculated by:
Limit RL 1
+()
32
⋅=
PEB 20542
PEF 20542
Regist er Description (XON)
Preliminary Data Sheet 5-211 08.99
Reg ister 5-71 XON
XON In-Band Flow Control Character Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 4AH9AH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
XON Character
H00000000
AXON(7:0)
B00000000
Reg ister 5-72 XOFF
XOFF In-Band Flow Control Character Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 4BH9BH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
XOFF Character
H00000000
AXOFF(7:0)
B00000000
PEB 20542
PEF 20542
Register Description (XOFF)
Preliminary Data Sheet 5-212 08.99
XON(7:0) XON Character (async mode)
This bit field specifies the XON charac ter for in-band flow control in
ASYNC protocol mode. The number of significant bits starting with the
LSB depends on the character length (5..8 bits) selected via bit field
’CHL(1:0)’ in reg is te r CCR3L.
A received character is recog nized as a valid XON- char acter, if
• the charact er was correctly framed (cha racter length as program me d
and correct parity if checking is enabled)
• each bit position of the received character which is not masked via
register MXON mat ches with th e corresponding bit in register XON.
Received characters recognized as XON character are stored in the
receive FIFO as normal receive data unless disabled with bit
CCR3L:DXS. An appropriate ’XON’ interrupt is generated (if enabled)
and the trans mit ter is switched into ’XO N’ s tate if in- band f low c ontrol i s
enabled via bit ’FLON’ in register CCR2H.
XOFF(7:0) XOFF Character (as ync mo de)
This bit field specifies the XOFF character for in-band flow control in
ASYNC protocol mode. The number of significant bits starting with the
LSB depends on the character length (5..8 bits) selected via bit field
’CHL(1:0)’ in reg is te r CCR3L.
A received character is recog nized as a valid XOFF-char act er, if
• the charact er was correctly framed (cha racter length as program me d
and correct parity if checking is enabled)
• each bit position of the received character which is not masked via
register MXOFF matches with the corresponding bit in r egister XOFF.
Received characters recognized as XOFF character are stored in the
receive FIFO as normal receive data unless disabled with bit
CCR3L:DXS. An appropriate ’XOFF’ interrupt is generated (if enabled)
and the transmitter is switched into ’XOFF’ state if in-band flow control is
enabled via bit ’FLON’ in register CCR2H.
PEB 20542
PEF 20542
Register Description (MXON )
Preliminary Data Sheet 5-213 08.99
Reg ister 5-7 3 MXON
XON In-Band Flow Control M ask R egister
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 4CH9CH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
XON Character Mask
H00000000
AMXON(7:0)
B00000000
Reg ister 5-7 4 MXOFF
XOFF In-Band Flow Control Mask Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 4DH9DH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
XOFF Character Mask
H00000000
AMXOFF(7:0)
B00000000
PEB 20542
PEF 20542
Regist er Descript ion (MXOFF)
Preliminary Data Sheet 5-214 08.99
MXON(7:0) XON Character Mask (async mode)
Setting a bit in thi s bit field to ’1’ masks the correspondi ng bit in bit field
’XON(7:0)’ of register XON. A masked bit position always matches when
comparing the received character with bit field ’XON(7:0)’.
bit = ’0’ Th e dedicate d bit position is NOT maske d. This bit
po sition in the received charac ter must mat ch with the
corresponding bit position in bit field ’XON’ to recognize
the recei ved char act er as an XON char act er.
bit = ’1’ The dedicated bit position is masked. This bit position in
the recei ved character NEED NOT match with the
corresponding bit position in bit field ’XON’ to recognize
the recei ved char act er as an XON char act er.
MXOFF(7:0) XOFF Character Mask (as ync mo de)
Setting a bit in thi s bit field to ’1’ masks the correspondi ng bit in bit field
’XOFF(7:0)’ of register XOFF. A m asked bit position alwa ys matches
when comparing th e received character with bit field ’XOFF ( 7:0)’.
bit = ’0’ Th e dedicate d bit position is NOT maske d. This bit
po sition in the received charac ter must mat ch with the
corresponding bit position in bit field ’XOFF’ to recognize
the recei ved char act er as an XOFF char acter.
bit = ’1’ The dedicated bit position is masked. This bit position in
the recei ved character NEED NOT match with the
corresponding bit position in bit field ’XOFF’ to recognize
the recei ved char act er as an XOFF char acter.
PEB 20542
PEF 20542
Registe r Description (TCR)
Preliminary Data Sheet 5-215 08.99
Reg ister 5-75 TCR
Terminat ion Character Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 4EH8 9EH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Termination Character
H00000000
ATC(7:0)
BTC(7:0)
TC(7:0) Termination Character (async mode)
This bit-field defines the termination character which is monitored on the
receive data stream if enabled via bit ’TCDE’ in register CCR3L.
PEB 20542
PEF 20542
Register Description (TICR )
Preliminary Data Sheet 5-216 08.99
Reg ister 5-76 TICR
Transmit Immediate Character Register
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 4FH9FH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
Transmit Immediate Char acter
H00000000
ATIC(7:0)
B00000000
PEB 20542
PEF 20542
Register Description (TICR )
Preliminary Data Sheet 5-217 08.99
TIC Transmi t Immediate Cha racter (async mode)
On write access to this register, the ASYNC protocol engine will
automatically insert the characte r defined by bit field ’T IC ’ into the
transmit data stream.
This happens
• immediat ely after write ac cess t o r egist er TICR if the t ran smitter i s in
IDLE state (no other character is currently transmitted). The
transmitter returns to IDLE state after transmission of the TIC.
• immediately after the character which is currently in transmission is
completed. After transmission of the TIC, the transmitter continues
with transmission of characters which are still stored in the transmit
FIFO. Thus the TIC is inserted into the data stream between the
character s provided vi a the transmit FIFO .
The TIC transmission is independent of in-band flow control. Thus the
TIC is sent out even if the transmitter is in ’XOFF’ state. However the
transmitter must be enabl ed via si gnal C TS (dependin g on bit ’FCTS’ in
register CCR1H).
The number of significant bits (starting with the LSB) depends on the
character length programmed in bit field ’CHL(1:0)’ in register CCR3L.
All character framing related settings in registers CCR3L/CCR3H (start
bit, parity generation, number of stop bits) also apply to the TIC character
framing.
As long as the TIC character is not completely sent, status bit TIC
Execution (’TEC’) in status register STARL is set to ’1’ by MISTRAL. No
further write access to register TICR is allowed until ’TEC’ status
indication is cleared by MISTRAL.
PEB 20542
PEF 20542
Regist er Description (ISR0)
Preliminary Data Sheet 5-218 08.99
Reg ister 5-7 7 I S R0
Interrupt Status Register 0
CPU Acc e ssibilit y : read only
Reset Value: 00H
Channel A Channel B
Offs et Address: 50HA0H
typical usage: updated by MISTRAL
read and evaluat ed by C PU
Bit76543210
Mode
ISR0
HRDO RFO PCE RSC RPF RME RFS FLEX
ATCD RFO FERR PERR RPF 0 TIME 0
BTCD RFO SCD PERR RPF 0 0 0
Reg ister 5-7 8 I S R1
Interrupt Status Register 1
CPU Acc e ssibilit y : read only
Reset Value: 00H
Channel A Channel B
Offs et Address: 51HA1H
typical usage: updated by MISTRAL
read and evaluat ed by C PU
Bit76543210
Mode
ISR1
HTIN CSC XMR XPR ALLS XDU SUEX 0
ATIN CSC XOFF XPR ALLS XON BRK BRKT
BTIN CSC XMR XPR ALLS XDU 0 0
PEB 20542
PEF 20542
Regist er Description (ISR2)
Preliminary Data Sheet 5-219 08.99
Reg ister 5-7 9 I S R2
Interrupt Status Register 2
CPU Acc e ssibilit y : read only
Reset Value: 00H
Channel A Channel B
Offs et Address: 52HA2H
typical usage: updated by MISTRAL
read and evaluat ed by C PU
Bit76543210
Mode
ISR2
H000000PLLACDSC
A000000PLLACDSC
B000000PLLACDSC
PEB 20542
PEF 20542
Regist er Description (ISR2)
Preliminary Data Sheet 5-220 08.99
RDO Receive Data Overflow Interrupt (hdlc mode)
This bit is set t o ’1’, if receive data of the current frame got lost because
of a SCC receive FIFO full condition. However the rest of the frame is
received and di scarded as l ong as the receive FI FO remains ful l and is
stored as soon as FIFO space is available again. The receive status byte
(RSTA) of such a frame contains an ’RDO’ indication. In DMA operation
the ’RDO’ indication is also set in the receive byte count register RBCH.
TCD Termination Charact er Detected Interrupt (async / bis ync mo de)
This bit is set to ’1’, if a termination characte r (TCR) has be en detected
in the receive data stream or an ’RFRD’ command issued in the CMDRH
register has been completed. The SCC will insert a ’block end’ indication
to the RFIFO. The actual block length can be determined by reading
register RBCL.
RFO Receive FIFO Overflow Interrupt (all mod es)
HDLC Mode:
This bit is set to ’1’, if the SCC receive FIFO is full and a complete frame
must be discarded. This interrupt can be used for statistical purposes,
indicating that the host was not able to service the SCC receive FIFO
quickly enough, e.g. due to high bus latency.
ASYNC/BISYNC Mode:
This bit is set to ’1’, if the SCC receive FIFO is full and another received
character has be en discarded. This interrupt can be used for statistical
purposes and might indicate that the host was not able to service the
SCC receive FIFO quickly enough, e.g. bus latencies ar e too high.
PC E P ro to c o l E rror In te rrup t (hdl c mo de)
This bit is valid in HDLC Autom ode onl y .
It is set to ’1’, if the receiver has detected a protocol error, i. e. one of the
following events occured:
• an S- or I-frame was received with wrong N(R ) counter value;
• an S-frame containi ng an Informat ion field was receiv ed.
PEB 20542
PEF 20542
Regist er Description (ISR2)
Preliminary Data Sheet 5-221 08.99
FERR Fr aming Error Interrupt (async mode)
This bit is set to ’1’, if a character framing error is detected, i.e. a ’0’ was
sam pl ed at a position where a stop bit ’1’ was expected due to the
selected char acte r form at.
SCD Sync Character Detected (bisync mode)
Only valid in Hunt Mode.
This bit is set t o ’1’ if a SYN character is found in the receive d data
stream after the ’HUNT’ command has been issued in register CMDRH.
The receive r now is in the synchronous state.
RSC Receive Status Change Interrupt (hdlc mode)
This bit is valid in HDLC Autom ode onl y .
It is set to ’1’, if a status change of the remote station receiver has been
detected by receiving a S-frame with receiver ready (RR) or receiver not
ready (RNR) indication. Because only a status change is indicated via
th is interrupt, the c urrent s tatus c a n b e evaluated by reading bit ’RRNR’
in status register STARH.
PERR Parity Err or Interrupt ( async/bisync modes)
This bit is only valid if parity checking/generation is enabled via bit
’PARE’ in register CCR3H.
It i s set to ’1’, if a character with wrong parity has been received. If
enabled via bit CCR3H:RFD F, this error statu s is additionally stored in
the receive status byte generat ed for each rece ive character .
RPF Receive Pool Full Interrupt (all modes)
This bit is set to ’1’ if the RFIFO threshold le vel, set with bit field
’ RFTH(1 :0 )’ i n regi ste r CCR3H, is reached. Default threshold level is 32
data bytes in HDLC/PPP modes, 1 data byte in ASYNC/BI SYNC modes.
PEB 20542
PEF 20542
Regist er Description (ISR2)
Preliminary Data Sheet 5-222 08.99
RME Receive Message End Interrupt (hdlc mode)
This bit set to ’1’ indicates that the receptio n of one message is
completed, i.e. either
– one message which fits into RFIFO not exceeding the receive FIFO
threshol d, or
– the last part of a message, all in all exceeding the receive FIFO
threshold
is stored in the RFIFO.
The complete message length can be determined by r eading the RBCL/
RBCH registers. The number of bytes stored in RFIFO is given by the 5,
4, 2 or 1 lea st significant bits of register RBCL, depending on the
selected RFIFO threshold (bit field ’RFTH( 1:0 )’ in register CCR3H).
Additional frame status information is available in the RSTA byte, stored
in the RFIFO as the last byte of each frame.
RFS Receive Frame Start Interrupt (hdlc mode)
This bit is set to ’1’, if the beginning of a va lid frame is detected by the
receiver. A valid frame start is detected either if a valid address field is
recognized (in all operating modes with address recognition) or if a start
flag is recognized (in all operating modes with no address recognition).
TIME Time Out Int errupt (as ync mode)
This bit is set to ’1’, if the time out limit is exceeded, i.e. no new character
was received in a programmable period of time (refer to register TOLEN
bi t fields ’TOIE’ and ’TOLEN’ for mor e information ).
FLEX Frame Length Exceeded Interrupt (hdlc mode)
This bit is set to ’1’, if the frame length check fe ature is enabl ed and th e
current received frame is aborted because the programmed frame length
limit was exceeded (refer to registers RLCRL/RLCRH for detailed
description).
TIN Timer Interrupt (all mod es)
This bit is set to ’1’, if the internal timer was activated and has expired
(refer also to description of timer registers TIMR0..TIMR3).
PEB 20542
PEF 20542
Regist er Description (ISR2)
Preliminary Data Sheet 5-223 08.99
CSC CTS Status Change (all mod es)
This bit is set to ’1’, if a transition occurs on signal CTS. The current state
of signal CTS i s monitored by status bit ’CTS’ in status register STARL.
XMR Transmit Message Repeat (hdl c/bisync modes)
This b it is set to ’ 1’, i f t rans mission of t he last f rame has t o be repeated
(by software) , beca use
• the SCC has received a negative acknowledge to an I-frame (in HDLC
Automode oper ation);
• a collision occured after at least 31 bytes of data have been
completely sent out, i.e. automatic re-transmission cannot be
performed by the SCC;
•CTS
signal w as deasserted after at le ast 31 b y tes of dat a hav e been
compl et ely sent out.
Note: For easy recovery from a collision event (in bus configuration
only), the SCC transmit FIFO should not contain more than one
complete frame. This can be achieved by using the ’ALLS’
interrupt to control the corresponding transmit channel forwarding
a new frame on all sent (ALLS) even t only.
XOFF XOFF Character Detected Interrupt (async mode)
ASYNC Mode:
This bit is set to ’1’, if the currently received character matched the XOFF
character programmed in register XOFF and indicates, that the
transmitter is swi tch ed t o ’XO FF’ s t ate if in- band flow control is enabled
via bit ’FLON’ in registe r CCR2H.
XPR Transm it Pool Ready Interrupt (all modes)
This bit is set to ’1’, if a transmitter reset command was executed
successfully (command bit ’XRES’ in register CMDRL) and whenever
the XFIFO is able to accept new transmit data again.
An ’XPR’ interrupt is not generated, if no sufficient transmit clock is
available (depending on the selected clock mode).
PEB 20542
PEF 20542
Regist er Description (ISR2)
Preliminary Data Sheet 5-224 08.99
ALLS ALL Sent Interrupt (all modes)
HDLC Mode:
This bit is set to ’1’:
• if the last bit of the current HDLC frame is sent out via pi n TxD and no
further frame is stored in the SCC transmit FIFO, i.e. the transmit FIFO
is empty (Address Mode 2/1/0);
• if an I-frame is sent out completely via pin TxD and either a valid
acknowledge S-frame has been received or a time-out condition
occured because no valid acknowledge S-frame has been received in
time (Autom ode) .
ASYNC/BISYNC Mode:
This bit is set to ’1’, if the last characte r is completely se nt via pin TxD
and no further data is stored in the SCC transmit FIFO, i.e. the transmit
FIFO is empty.
XDU Transm i t Data Underrun Inte rrupt ( hdlc mode)
This bit is set to ’1’, if the current frame was terminated by the SCC with
an abort sequence, because neither a ’frame end / block end’ indication
was detected in the FIFO (to complete the current frame) nor more data
is available in the SCC transmit FIFO.
Note: The transmitter is stopped if this condition occurs. The XDU
condition MUST be cleared by reading register ISR1, thus bit
’ XDU’ s h ould not be maske d via register IMR1.
XON XON Character Detected Interrupt (async mo de)
This bit is set to ’1’ , if the currently received character matched the XON
character programmed in register XON and indicates, that the
transmitter is switched to ’XON’ state if in-band flow control is enabled
via bit ’FLON’ in registe r CCR2H.
SUEX Signal l ing Unit C ount er Exceed ed Interrupt (hdlc mode)
This bit is set to ’1’, if 256 correct or inco rre ct SU’s have bee n received
and the internal counter is reset to 0.
PEB 20542
PEF 20542
Regist er Description (ISR2)
Preliminary Data Sheet 5-225 08.99
BRK Break Interrupt (async mode)
This bit is set to ’1’, if a break condition was detected on the receive line,
i.e. a low level for a time equal to (character length + parity bit + stop
bit(s)) bits depending on the selected ASYNC character format.
BRKT Break Terminated Interrupt (as ync mo de)
This bit is set to ’1’, if a previously detected break condition on the
receive line is terminated by a low to hi gh t rans ition.
PLLA DPLL Asynchronous Interrupt (all modes)
This bit is only valid, if the receive clock is derived from the internal DPLL
and FM0, FM1 or Ma nchester dat a encoding is selected (depending on
the selected clock mode and data encoding mode). It is set to ’1’ if the
DPLL has lost synchronization. Reception is disabled until
synchronization has been regained again. If the transmitter is supplied
with a clock derived from the DPLL, transmission is also interrupted.
CDSC Carrier Detect Status Change Interrupt (all modes)
This bit is s et to ’1’ , if a stat e t rans ition has been de tected at signal CD .
Because only a state transition is indicated via this interrupt, the current
status can be evaluat e d by reading bit ’CD’ in sta tu s regi s te r STARH.
PEB 20542
PEF 20542
Register Description (IMR 0)
Preliminary Data Sheet 5-226 08.99
Reg ister 5-8 0 I MR0
Interrupt Mask Register 0
CPU Acc e ssibilit y : read/write
Reset Value: FFH
Channel A Channel B
Offs et Address: 54HA4H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
IMR0
HRDO RFO PCE RSC RPF RME RFS FLEX
ATCD RFO FERR PERR RPF 1 TIME 1
BTCD RFO SCD PERR RPF 1 1 1
Reg ister 5-8 1 I MR1
Interrupt Mask Register 1
CPU Acc e ssibilit y : read/write
Reset Value: FFH
Channel A Channel B
Offs et Address: 55HA5H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
IMR1
HTIN CSC XMR XPR ALLS XDU SUEX 1
ATIN CSC XOFF XPR ALLS XON BRK BRKT
BTIN CSC XMR XPR ALLS XDU 1 1
PEB 20542
PEF 20542
Register Description (IMR 2)
Preliminary Data Sheet 5-227 08.99
Reg ister 5-8 2 I MR2
Interrupt Mask Register 2
CPU Acc e ssibilit y : read/write
Reset Value: 03H
Channel A Channel B
Offs et Address: 56HA6H
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
IMR2
H000000PLLACDSC
A000000
PLLA CDSC
B000000
PLLA CDSC
PEB 20542
PEF 20542
Register Description (IMR 2)
Preliminary Data Sheet 5-228 08.99
(IM) Interr upt Mask Bits
Each SCC interrupt event can generate an interrupt signal indication via
pin INT/INT. Each bit position of registers IMR0..IMR2 is a mask for the
corresponding interrupt event in the interrupt status registers
ISR0..ISR2. Masked interrupt events never generate an interrupt
indication via pin INT/INT.
bit = ’0’ The corresponding interrupt event is NOT masked and will
gener ate an interrup t indication vi a pin INT/INT.
bit = ’1’ The corresponding interrupt event is masked and will
NEIT HE R generate an inter rupt vect or NOR an interrupt
indication via pin INT/I NT.
Moreover, masked interrupt events are:
• not displ ayed i n the interr upt status r egiste rs ISR0..ISR2 if bit ’VIS’ in
register CCR0L is pr ogr ammed t o ’0’.
• displayed in interrupt status registers ISR0..ISR2 if bit ’VIS’ in register
CCR0L is pr ogramm ed to ’1’.
Note: After RESET, all interrupt events are masked.
For detailed interrupt event description refer to the corresponding bit
position in registers ISR0..ISR2.
PEB 20542
PEF 20542
Registe r Description (RSTA)
Preliminary Data Sheet 5-229 08.99
The Receive Status Byte ’RSTA’ contains comprehensive status information about the
last received frame (HDLC/PPP) or the last received ASYNC/BISYNC character.
The SCC attaches this status byte to the receive d ata and thus it should be read from
the RFIFO.
In HDLC/PPP modes the RSTA value can optionally be read from this register address;
in ASYNC and BISYNC modes a read to this register is not specified. In extended
transpar ent mode this status field does not apply.
Reg ister 5-83 RSTA
Receive Status Byte
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 58HA8H
typical usage: written by MISTRAL to RFIFO;
read from RFIFO and evaluated by CPU
Bit76543210
Mode
Receive Status Byte
HVFR RDO CRCOK RAB HA(1:0)/
SU(1:0) C/R LA
APEFE00000P
BPEFE00000P
PEB 20542
PEF 20542
Registe r Description (RSTA)
Preliminary Data Sheet 5-230 08.99
VFR Valid Frame (hdlc modes)
Determines whether a valid frame has been received.
VFR=’0’ The received frame is invalid.
An invalid frame is either a frame which is not an integer
numb er of 8 bits (n * 8 bi ts) in length (e.g. 25 bits), or a
frame which is too short, taking into account the operation
mode selected via CCR2L (M DS 1 , MDS0, A DM) and t h e
selected CRC algorithm (CCR1L:C32) as follows:
for CCR3H:DRCRC = ’0’ (CRC rece p tion enabl ed) :
• automode / address mode 2 (16-bit address)
4 by tes (CRC-CCITT) or 6 (CRC-32 )
• automode / address mode 2 (8-bit address)
3 by tes (CRC-CCITT) or 5 (CRC-32 )
• address mode 1:
3 by tes (CRC-CCITT) or 5 (CRC-32 )
• address mode 0:
2 by tes (CRC-CCITT) or 4 (CRC-32 )
for CCR3H:DRCRC = ’1 ’ (CRC r ecep tion disa bl e d):
• automode / address mode 2 (16-bit address):
2bytes
• automode / address mode 2 (8-bit address):
1 byte
• address mode 1:
1 byte
• address mode 0:
1 byte
Note: Shorter frames are not reported at all.
VFR=’1’ The received frame is valid.
RDO Receive Data Overflow (hdlc modes)
RDO=’0’ No re cei ve data overflow has occ urred.
RDO=’1’ A data overflow has occurred during reception of the
frame. Additionally, an interrupt can be generated (refer to
ISR0:RDO/IMR0:RDO).
PEB 20542
PEF 20542
Registe r Description (RSTA)
Preliminary Data Sheet 5-231 08.99
CRCOK CRC Compa re/Check (hdlc modes)
CRCOK=’0’ CRC check failed, receive d frame contains errors.
CRCOK=’1’ CRC check OK; the received frame does not contain CRC
errors.
RAB Receive Message Aborted (hdlc modes)
RAB=’0’ No abort condition was detected during reception of the
frame.
RAB=’1’ The received frame was aborted from the transmitting
stati on. According to the HDLC pro toco l, this frame must
be discarded by the receiver station.
This bit is also set to ’1’ if the maximum receive byte count
(set in registers RLCRL/RLCRH) is reached.
HA(1:0) High Byte Address Compare ( hdlc modes)
Significant only if an address mode with automatic address handling has
been selected. In operating modes w hic h provide high byte address
recognition, MISTRAL compares the high byte of a 2-byte address with
the contents of two individually programmable addresses (RAH1, RAH2)
and the fixed values FEH and FCH (broadcast address) . Dependent on
the result of this comparison, the following bit combinations are possible:
HA(1:0)=’10’ RAH1 has been recognized.
HA(1:0)=’00’ RAH2 has been recognized.
HA(1:0)=’01’ broadcast address has been recognized.
If RAH1 and RAH2 contain ident ical values, a match is indicate d by
HA(1:0)=’10’.
SU(1:0) SS7 Signaling Unit Type (hdl c mod es)
If Si gnaling System #7 supp ort is activated (see CCR3L register, bit
’ESS7’), the bit functions are defin ed as follows:
SU (1 :0)=’ 0 0 ’ n o t v a l id
SU(1:0)=’01’ Fill In Signaling Unit (FISU) detected
SU(1:0)=’10’ Link Status Signaling Unit (LSSU) detected
SU(1:0)=’11’ M ess age Sign aling Unit (MSU) detected
PEB 20542
PEF 20542
Registe r Description (RSTA)
Preliminary Data Sheet 5-232 08.99
C/R Command/Response (hdlc mod e s)
Significant only if 2-byte address mode has been sel ect ed.
Value of the C/R bit (bit 1 of hi gh addr ess byte) in the received fram e.
The interpretation depends on the setting of the ’C RI’ bit in the RAH1
register (See “RAH1” on page 203.).
LA Low Byte Address Compare (hdlc modes)
Significant in automode and address mode 2 only.
The low byte address of a 2-byte address field, or the single address byte
of a 1-byte address field is compared with two addresses (RAL1, RAL2).
LA=’0’ RAL2 has been recognized.
LA=’1’ RAL1 has been recognized.
According to the X.25 LAPB protocol, RAL1 is interpreted as the address
of a COMMAND frame and RAL2 is interpreted as the address of a
RESPONSE fram e.
PEB 20542
PEF 20542
Register Description (SYNCL)
Preliminary Data Sheet 5-233 08.99
Reg ister 5-84 SYNCL
SYN Character Register (Low Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 5AHAAH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
SYN Char acter Low
H00000000
A00000000
BSYNCL(7:0)
Reg ister 5-85 SYNCH
SYN Character Register (High Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: 5BHABH
typical usage: written by CPU;
read and evaluat ed by MISTR AL
Bit76543210
Mode
SYN Character High
H00000000
A00000000
BSYNCH(7:0)
PEB 20542
PEF 20542
Register Description (SYNCH)
Preliminary Data Sheet 5-234 08.99
SYNCH(7:0) Synchronization Character (high) (bisync mode)
SYNCL(7:0) Synchronization Character (low) (bisync mode)
This register is only valid in BISYNC protocol mode.
The synchronizat i on (SYN) charact er format depe nds on the setting of
bit ’BISNC’ and ’SLEN’ in register CCR2L:
• MONOSYNC Mode (CCR2L.BISNC = ’0’)
The SYN character is defined by register ’SYNCL’:
a) SLEN = ’0’: the 6 bit SYN cha racter is specified by bits (5..0)
b) SLEN = ’1’: the 8 bit SYN cha racter is specified by bits (7..0).
• BISYNC Mode (CCR2L.BISNC = ’1’)
The SYN character is defined by registers ’SYNCL’ and ’SYNCH’:
a) SLEN = ’0’: the 12 bit SYN character is specified by bits (5..0) of
each register, i.e. SYN(11..0) = SYNCH(5:0), SYNCL(5:0)
b) SLEN = ’1’: the 16 bit SYN character is specified by bits (7..0) of
each register, i.e. SYN(15..0) = SYNCH(7:0), SYNCL(7:0).
In transmit direction the SYN characte r is sent continuously if no data
has to be transmitted and interframe timefill control is enabled by setting
bit ’ITF’ to ’1 ’ in regi s ter CCR2H.
In receive direction the receiver monitors the data stream for occurence
of the s pecified SYN pattern if operating in ’HUNT’ mode (bit ’HUNT’ in
register CMDRH).
PEB 20542
PEF 20542
Register Description (TBADDR1L)
Preliminary Data Sheet 5-235 08.99
5.2.3 Channel Specific DMA Registers
Each regist er desc ription is organized in three parts:
• a head with gene ral inf ormation about r eset value, access t ype (read/write), channel
specific offset address and usual handling;
• a table containing the bit information (name of bit positions);
• a section containing the detailed description of each bit.
Register 5-86 TBADDR1L
Primary Transmit Base Address (Low Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: B0HCAH
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
TBADDR1(7:0)
Register 5-87 TBADDR1M
Primary Transmit Base Address (Mid By te)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: B1HCBH
typical usage: written by CPU, evaluated by MISTRAL
Bit151413121110 9 8
TBADDR1(15:8)
PEB 20542
PEF 20542
Register Description (TBADDR1H)
Preliminary Data Sheet 5-236 08.99
Register 5-88 TBADDR1H
Primary Transmit Base Address (H igh Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Offs et Address: B2HCCH
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
TBADDR1(23:16)
TBADDR1
(23:0) Primary Transmit Base Address
Onl y v alid in int e rn a l DMA con troll er mo des.
This bit field determines the base address of the primary DMA transmit
buffer (buffer 1).
• If single-buffer operation is selected, this base address is the only one
used; the secondary base address TBADDR2(23:0) is "don’t care" in
this case.
• If switched-buffer operation is selected (refer to register DMODE),
transmissi on takes pla ce based on tw o transmit buffers that are sent
alternating.
Note: If 16-bit bus operation is selected, the base address must be word
aligned, i.e. bit TBADDR1(0) must be set to ’0’.
PEB 20542
PEF 20542
Register Description (TBADDR2L)
Preliminary Data Sheet 5-237 08.99
Register 5-89 TBADDR2L
Second ary Transmit Base Address (L ow Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: B4HCEH
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
TBADDR2(7:0)
Register 5-90 TBADDR2M
Second ary Transmit Base Address (Mi d Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: B5HCFH
typical usage: written by CPU, evaluated by MISTRAL
Bit151413121110 9 8
TBADDR2(15:8)
PEB 20542
PEF 20542
Register Description (TBADDR2H)
Preliminary Data Sheet 5-238 08.99
Register 5-91 TBADDR2H
Second ary Transmit Base Address (High By te)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: B6HD0H
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
TBADDR2(23:16)
TBADDR2
(23:0) Secondary Transmit Base Address
Only valid in switched-buffer DMA controller mode .
Thi s bit field determines the base address of t he secondary DMA
transmit buffer ( buf fer 2) in switched-b uffer ope ration.
• If single-buffer operation is selected, this base address is "don’t care".
Only address TBADDR1(23 :0 ) is used in th is case.
• If switched-buffer operation is selected (refer to register DMODE),
transmission takes place based on both transmit buffers (TBADDR1
and TBADDR2). Data from these transmit buffe rs is sent alternating.
Note: If 16-bit bus operation is selected, the base address must be word
aligned, i.e. bit TBADDR2(0) must be set to ’0’.
PEB 20542
PEF 20542
Regist er Descript ion (XBC1L)
Preliminary Data Sheet 5-239 08.99
Reg ister 5-92 XBC1L
Primary Transmit Byte Count (Low Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: B8HD2H
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
XBC1(7:0)
Reg ister 5-93 XBC1H
Primary Transmit Byte Count (High Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: B9HD3H
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
XME XF XIF 0 XBC1(11:8)
PEB 20542
PEF 20542
Registe r Description (XBC1H)
Preliminary Data Sheet 5-240 08.99
XBC1
(11:0) Primary Transmit Byte Count
Onl y v alid in int e rn a l DMA con troll er mo des.
Thi s bit field determines the size in numb er of bytes of the primary
transmit buffer (with base addr ess TBADD R1 (23:0) ).
• If single-buffer operation i s selected, the primary buffer is the only one
used; the secondary transmit byte count bit field XBC2(11:0) is "don’t
care" in this case.
• If switched-buffer operation is selected (refer to register DMODE),
transmi ssion t akes place b ased on tw o transm it buf f ers (primary and
secondar y) that are sent alternatin g.
XME Transmit Message End Command
Onl y v alid in i nt e rn a l DMA contro ller mode.
This bit is identical to ’XME’ command bit (refer to register "CMDRL" on
page 5-146).
XF Transmit Frame Comm and
Onl y v alid in i nt e rn a l DMA cont ro ller m o de.
This bit is identical to ’XF’ command bit (refer to register "CMDRL" on
page 5-146).
XIF Transm i t I-Frame Command
Onl y v alid in i nt e rn a l DMA cont ro ller m o de.
This bit is identical to ’XIF’ command bit (ref er to register "CM DRL " on
page 5-146) .
PEB 20542
PEF 20542
Regist er Descript ion (XBC2L)
Preliminary Data Sheet 5-241 08.99
Reg ister 5-94 XBC2L
Secondary Transmit Byte Count (Lo w Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: BAHD4H
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
XBC2(7:0)
Reg ister 5-95 XBC2H
Secondary Transmit Byte Count (High By te)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: BBHD5H
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
XME XF XIF 0 XBC2(11:8)
PEB 20542
PEF 20542
Registe r Description (XBC2H)
Preliminary Data Sheet 5-242 08.99
XBC2
(11:0) Secondary Transm it Byte Count
Only valid in switched-buffer DMA controller mode .
This bit field determines th e size in number of bytes of the secondary
transmit buffer (with base addr ess TBADD R2 (23:0) ).
• If single-buffer operation is selected, this bit field is "don’t care". The
primary transmit buffer with transmit byte count XBC1(11:0) is the only
one used in this case.
• If switched-buffer operation is selected (refer to register DMODE),
transmi ssion t akes place b ased on tw o transm it buf f ers (primary and
secondar y) that are sent alternatin g.
XME Transmit Message End Command
Onl y v alid in int e rn a l DMA con troll er mo des.
This bit is identical to ’XME’ command bit (refer to register "CMDRL" on
page 5-146) .
XF Transmit Frame Comm and
Onl y v alid in int e rn a l DMA con troll er mo des.
This bit is identical to ’XF’ comma nd bit (refer to register "CMD RL" on
page 5-146) .
XIF Transm i t I-Frame Command
Onl y v alid in int e rn a l DMA con troll er mo des.
This bit is identical to ’XIF’ command bit (ref er to register "CM DRL " on
page 5-146) .
PEB 20542
PEF 20542
Register Description (RBADDR1L)
Preliminary Data Sheet 5-243 08.99
Register 5-96 RBADDR1L
Primary Receive B ase Ad dress (Low Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: BCHD6H
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
RBADDR1(7:0)
Register 5-97 RBADDR1M
Primary Recei ve B ase Ad dress 1 (Mid Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: BDHD7H
typical usage: written by CPU, evaluated by MISTRAL
Bit151413121110 9 8
RBADDR1(15:8)
PEB 20542
PEF 20542
Register Description (RBADDR1H)
Preliminary Data Sheet 5-244 08.99
Register 5-98 RBADDR1H
Primary Receive B ase Ad dress 1 (High Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: BEHD8H
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
RBADDR1(23:16)
RBADDR1
(23:0) Primary Receive Base Address
Onl y v alid in int e rn a l DMA con troll er mo des.
This bit field determines the base address of the primary DMA receive
buffer (buffer 1).
• If single-buffer operation is selected, this base address is the only one
used; the secondary base addre ss RBAD DR2( 23:0) is " don’ t care" i n
this case.
• If switched-buffer operation is selected (refer to register DMODE),
reception takes place based on two receive buffers that are filled
alternating.
Note: If 16-bit bus operation is selected, the base address must be word
aligned, i.e. bit RBADDR1( 0) must be set to ’0’.
PEB 20542
PEF 20542
Register Description (RBADDR2L)
Preliminary Data Sheet 5-245 08.99
Register 5-99 RBADDR2L
Second ary Receive Base Address (Low B yte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: C0HDAH
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
RBADDR2(7:0)
Register 5-100 RBADDR2M
Secondary Receive Base Address (Mid Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: C1HDBH
typical usage: written by CPU, evaluated by MISTRAL
Bit151413121110 9 8
RBADDR2(15:8)
PEB 20542
PEF 20542
Register Description (RBADDR2H)
Preliminary Data Sheet 5-246 08.99
Register 5-101 RBADDR2H
Secondary Receive Base Address2 (High Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: C2HDCH
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
RBADDRA2(23:8)
RBADDR2
(23:0) Secondary Receive Base Address
Only valid in switched-buffer DMA controller mode .
This bit field determines the base address of the secondary DMA receive
buf fer (buffer 2) in switched-b uffer ope ration .
• If single-buffer operation is selected, this base address is "don’t care".
Only address RBADDR1(23:0) is used in this case.
• If switched-buffer operation is selected (refer to register DMODE),
receptio n takes place base d o n both receive bu ffers (RBADDR1 an d
RBADD R2). Data is received into these buffer s altern ating.
Note: If 16-bit bus operation is selected, the base address must be word
aligned, i.e. bit RBADDR2( 0) must be set to ’0’.
PEB 20542
PEF 20542
Register Description (RMB SL)
Preliminary Data Sheet 5-247 08.99
Reg ister 5-1 02 RM B SL
Receive Maximum Buffer Size (Low Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: C4HDEH
typical usage: written by CPU, evaluated by MISTRAL
Bit76543210
Receive Maximum Buffer Size
RMBS(7:0)
Reg ister 5-1 03 RM B SH
Receive Maximum Buffer Size (High Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: C5HDFH
typical usage: written by CPU, evaluated by MISTRAL
Bit151413121110 9 8
Receive Maximum Buffer Size
RE 0 0 0 RMBS(11:8)
PEB 20542
PEF 20542
Register Description ( RMBSH)
Preliminary Data Sheet 5-248 08.99
RE Receive DMA Enable
Onl y v alid in int e rn a l DMA con troll er mo de.
Self-clearing com ma nd bit:
RE=’0’ The DMA controller is not set up to forward receive data
into a buffer in memory .
RE=’1’ If this bit is set to ’1’, the DMA controller is activated for
transf erring receive dat a into a buffer in memory. This
buffer in memory has to be set up with a valid base
addre ss RBADDRi(23:0) and the max imum buffer size
RMBS(11:0) in advance.
RMBS(11:0) Recei ve Maxim um Bu ffer Size
Onl y v alid in int e rn a l DMA con troll er mo des.
Thi s bit field determines the reser ved size (0..4095 byte) for a receive
buffer in memo ry . Wi th th e base a ddress RBADDRi(2 3 :0 ), the location
of the r ecei ve buf fe r is defined.
PEB 20542
PEF 20542
Register Descripti on (RBCL)
Preliminary Data Sheet 5-249 08.99
Register 5-104 RBCL
Receive Byte Count (Low Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: C6HE0H
typical usage: written by MISTRAL , evaluat ed by CPU
Bit76543210
RBC(7:0)
Register 5-105 RBCH
Receive Byte Count (High Byte)
CPU Acc e ssibilit y : read/write
Reset Value: 00H
Channel A Channel B
Offs et Address: C7HE1H
typical usage: written by MISTRAL , evaluat ed by CPU
Bit76543210
RDO 0 0 0 RBC(11:8)
PEB 20542
PEF 20542
Register Description (RBCH)
Preliminary Data Sheet 5-250 08.99
RBC(11:0) Receive Byte Count
This bit field determines the receive byte count (1..4095) of the currently
received frame/block.
RDO RDO Indi cation
Only valid in DMA controller mode.
This bit is identical to the ’RDO’ status bit belonging to this frame (see
description of register "R STA" on page 5-229).
PEB 20542
PEF 20542
Register Description (VER0)
Preliminary Data Sheet 5-251 08.99
5.2.4 Miscellane o us Registers
Reg ister 5-106 VER0
Version Register 0
CPU Acc e ssibilit y : read/write
Reset Value: 83H
Offs et Address: ECH
typical usage: evaluated by CPU
Bit76543210
Manufacturer Code Fix ’1’
VER(7:0)
Reg ister 5-107 VER1
Version Register 1
CPU Acc e ssibilit y : read/write
Reset Value: E0H
Offs et Address: EDH
typical usage: evaluated by CPU
Bit76543210
Device Code (b i ts 3 .. 0) Manufacturer C ode
VER(15:8)
PEB 20542
PEF 20542
Regist er Descript ion
Preliminary Data Sheet 5-252 08.99
Register 5-108 VER 2
Version Register 2
CPU Accessibili ty: read/write
Reset Va lu e: 05H
Offset Address: EEH
typical usage: evaluated by CPU
Bit76543210
Device Code (b i ts 11 .. 4)
VER(23:16)
Register 5-109 VER 3
Version Register 3
CPU Accessibili ty: read/write
Reset Va lu e: 10H
Offset Address: EFH
typical usage: evaluated by CPU
Bit76543210
Version Num ber Device Code (bits 15 .. 12)
VER(31:24)
PEB 20542
PEF 20542
Regist er Descript ion
Preliminary Data Sheet 5-253 08.99
VER(31:0) Version Register
Identical to 32 bi t bounda ry scan ID string.
The 32 bit string consists of the bit fields:
VER(31:28) 1HVe rsion Number
VER(27:12) 005EHDevice Co de
VER(11:0) 083HM anu fac turer Code (LSB fixed to ’1’)
PEB 20542
PEF 20542
Programming
Preliminary Data Sheet 6-254 08.99
6 Programming
6.1 Initialization
After Reset the CPU has to write a minimum set of registers and an optional set
depending on the required features and operating modes.
First, the following initialization steps must be taken :
• Select ser ial pro toc ol mode ( refer to Tab le 4-1 "Prot ocol Mo de O verv iew" on page 4-
84),
• Select encoding of the serial data (r efer to Chapt er 3.2 .13 "Data Encod ing " on page
3-73),
• Program the output characteristics of
- pin TxD (selected with bit ’ODS’ in "Channel Configuration Register 1 (Low Byte)" on
page 5-155) and
- interrupt pin INT/INT (selected wi th bit f ield ’IPC(1 :0)’ in "Global Mode R egister" on
page 5-124),
• Choos e a clock mode (refe r to Table 3-1 "Overview of Clock Mod es" on page 3-46).
• Power-up the oscillator unit ( with or without shaper) by re-setting bit GMODE:OSCPD
to ’0’, if appropriate (GMODE: DSHP=’ 0’ enables the shaper).
The clock mode must be set before power-up (CCR0H.PU). The CPU may switch the
MISTRAL between power-up and power-down mode. This has no influence upon the
contents of the registers, i.e. the internal state remains stored. In power-down mode
however, all internal clocks are d isabled, no interrupts from t he correspondi ng channe l
are forwarded to the CPU. This state can be used as a standby mode, when the channel
is (tem por aril y) not used, thus substanti ally reduci ng pow er cons ump tion.
The MISTRAL should usually be initialized in Power-Down mode.
The need for programming further registers depends on the selected features (serial
mode, clock mode speci f ic features , operating m ode, address mode, user demands).
6.2 Inter rupt Mode
6.2.1 Data Transm ission (Interrupt Driven )
In transmit direction 2 × 32 byte FIFO buffers (transmit pools) are provided for each
channel. After chec king the XFIFO stat us by polling th e Transmi t FIFO Write Enable bi t
(bit ’XFW’ in STARL r egister) or after a Tra nsm it Pool R eady (’XPR’ ) interr upt, u p to 32
bytes may be entered by the CPU into the XFIFO.
PEB 20542
PEF 20542
Programming
Preliminary Data Sheet 6-255 08.99
HDLC/SDLC/PPP
The transmission of a packet can be started by issuing an ’XF’ or ’XIF’ command via the
CMDRL register. If enabled, a specified number of preambles (refer to registers CCR2H
and PREAMB) are sent out optionally before transmission of the current packet starts.
If the transmit command does not include an end of message indication (CMDRL.XME),
MISTRAL will repeatedly request for the next data block by means of an ’XPR’ interrupt
as soon as no more than 32 bytes are stored in the XFIFO, i.e. a 32-byte pool is
accessible to the CPU.
This process will be repeated until the CPU indicates the end of message per ’XME’
com mand , after which packe t transmission is finished correctly by appending the CRC
and closing flag sequence. Consecutive packets may be transmitted as back-to-back
packets and may even share a flag (enabled via CCR1L.SFLG), if service of XFIFO is
quick enough.
In case no more data is available in the XFIFO prior to the arrival of the end-of-message
indiction (’XME’), the transmission of the packet is terminated with an abort sequence
and the CPU is notified per interrupt (ISR1.XDU, transmit data underrun). The packet
may also be aborted per software at any time (CMDRL.XRES).
The data transmission sequence, from the CPU’s point of view, is outlined in Figure 6- 1.
ASYNC
The transmission of character(s) can be started by issuing a ’XF’ command via the
CMDRL register. MISTRAL will repeatedly request for the next data block b y means of
an ’XPR’ interrupt as soon as no more th an 32 byt es ar e st ore d in the XFIFO , i.e. a 32-
byte pool is accessible to the CPU. Transmission may be aborted per software
(CMDRL.XRES).
BISYNC
The transmission of a block can be started by issuing an ’XF’ command via the CMDRL
register. Further handling of data transmission with respect to preamble transmission
and co mmand ’XME’ is similar to HDLC/SDLC mode. After ’XME’ command h as been
issued, the block is finished by appending the internally generated CRC if enabled (refer
to desc ription of registe r CCR2H).
In case no more data is available in the XFIFO prior to the arrival of ’XME’, the
transm ission of the block is terminated with IDLE and the CPU is notified per interrupt
(ISR1.XDU). The block may also be aborted per software (CMDRL.XRES). The data
transm is sion flow , from the CPU’s point of view, is outlined in Figure 6-1.
PEB 20542
PEF 20542
Programming
Preliminary Data Sheet 6-256 08.99
Figure 6-1 Int errupt Driven Data Transmis sion (Flow Diagram)
6.2.2 Data Reception (Interrupt Driven )
Also 2 × 32 by te FIFO buffers (receive p ools) are pr ovided for each chann el in recei ve
direction.
There are different interrupt indicati ons concerned with the reception of data:
HDLC/SDLC/PPP
•’RPF’ (Receive Pool Full) interrupt, indicating that a specified number of bytes (limited
with the receive FIFO t hreshold in register CCR3H, bi t fi eld ’RFTH(1..0)’; default is 32
bytes) can be read from RFIFO and the received message is not yet complete.
•’RME’ (Receive Message End) interrupt, indicating that the reception of one message
is completed, i.e. either
- one messa ge which fits into RFIFO not exceedi ng the recei ve FIFO threshold, or
- the last part of a message, all in all exceeding the recei ve FIFO threshold
is stored in the RFIFO.
In addition to the message end (’RME’) interrupt the following information about the
received packet is stored by MISTRAL in speci al registers and/ or RFIFO:
START
XFIFO
READY
'X P R ' In te rr up t
R e s e t T ra n smitte r
(CMDRL.XRES)
Wr ite Da ta to
XFIFO
(u p to 32 b yte s )
End of Messa
g
e
?
Yes
No
Issue C om mand
CMDRL.XF+.XME
or
CMDRL.XIF+.XME
Issue C om mand
CMDRL.XF
or
CMDRL.XIF
A c tion ta k e n
by CPU
Interrupt
in dic a tion to CP U
T ransmit serial
data and
append trailer
T ransmit serial
data
A c tion ta k e n
by the SCC
PEB 20542
PEF 20542
Programming
Preliminary Data Sheet 6-257 08.99
ASYNC, BISYNC
• ’RPF’ (Re ceive Pool Full) inte rrupt, indicating that a specified number o f bytes (refer
to register CCR3H, bit field ’RFTH(1..0)’) can be read from RFIFO.
• ’TCD’ (Termina tion Character Detected) interr upt, indicating that reception has been
terminated by reception of a specified character (refer to register TCR and bit
CCR3L.TCDE).
Additionally, the CPU can have access to contents of RFIFO without having received an
interrupt (and thereby causing ’TCD’ to occur) by issuing the RFIFO Read command
(CMDRH.RFRD).
In addition to every re ceived character the assigned status information Parity bit (0/1),
Parity Error (yes/no), Framing Error (yes/no, ASYNC only!) is optionally stored in RFIFO.
In addition to the end conditions (’TCD’ interrupt or after ’RFRD’ command) the length of
the last received dat a bloc k is stored in regist er RBCL.
Note: (For all serial modes) After the received data has been read from the RFIFO, this
must be explicitly acknowledged by the CPU issuing an ’RMC’ (Receive Message
Complete) command. The CPU has to handle the ’RPF’ interrupt before the
complete 2 x 32-byte FIFO is filled up with receive data which would cause a
“Recei ve D ata Overflow ” cond ition.
T he data reception sequence, from the CPU’s point of view, is outlined in Fi gure 6-2.
T able 6-1 S t atus Information after RME interupt
Status In f o rmation Location
Length of received message registers RBCH, RBCL
CRC result ( good/bad) RSTA register (or last byte of received data)
Valid frame (yes/no) RSTA register (or last byte of received data)
ABORT sequence reco gnized (yes /no ) RSTA register (or last byte of received data)
Data over flow (yes /no) RSTA register (or last byte of received data)
Results from address comparison
(with aut oma tic address handl i ng) RSTA register (or last byte of received data)
Type of frame (COMMAND/RESPONSE)
(with aut oma tic address handl i ng) RSTA register (or last byte of received data)
T ype of Signaling Unit
(in SS7 mode) RSTA register (or last byte of received data)
PEB 20542
PEF 20542
Programming
Preliminary Data Sheet 6-258 08.99
1) A receive threshold of 32 bytes is the default for HDLC/PPP mode. It can be programmed with bit field
RFTH(1:0) in register CCR3H.
2) The number of bytes stored in RFIFO can be determined by evaluating the lower bits in register RBCL
(depending on the selected receive threshold RFTH(1:0)).
Figure 6-2 Interru pt Driven Data Reception (Flow Dia gram)
START
WAIT F O R
INTERRUPT
Reset Receiver
(CMDRH.RRES)
A c tiva te R e c e ive r
(CCR3L.RAC)
A c tion ta k e n
by CPU
Interrupt
in dic a tio n to C P U
'RPF'
Interrupt
Read
[32]
1)
b yte s fro m R F IF O
Release RFIFO
(CMDRH.RMC)
Read re
g
isters
RBCL, RBCH
(R c B yte Count)
'RME'/'TCD'
Interrupt
Read
[R B CL % 3 2 ]
1), 2)
b yte s fro m R F IF O
PEB 20542
PEF 20542
Programming
Preliminary Data Sheet 6-259 08.99
6.3 Inter nal DMA Mode
The following table provides a definition of terms used in this chapter to describe the
opera tion of DMA con troller.
6.3.1 Data Transmission (DMA Controlled)
Standard Transfer Mode:
Any packet transmission is prepared by writing the transmit buffer start address into
registers TBADDR1L/M/H and the packe t size in num ber of bytes to registers XBC1L/
XBC1H.
Now there are two possible scenarios:
• If the prepared transmit buffer in memory contains a complete packet including the
end of the packet), the start com man d fo r DM A transm issi on is is sued by setting b its
’XF’ and ’ XME’ in r egi st er XBC1H to ’1’. The D M A controller w ill r equest t he external
bus and then read transmit data beginning at address TBADDR1. The data is
immediate ly t ransferred into t he XFIFO. Af t er th e l ast byte has be en transm itted, t he
T able 6-2 DMA Terminology
Packet A "Packet" is a connected block of data bytes. This can be
an HDLC/PPP frame as well as a num ber of ASYNC/
BISYNC characters up to a specific limit (received
termination char act er, CMDRH:RFRD command). If a
receive status byte ( RSTA) is attached to data bytes, it is
also consider ed as part of the packet.
Buffer A "Buffer" is a li mited space in memory that is r eserved for
DMA reception /trans mission. Every time the DMA
controller compl et es a buffer transfer, it notifies the CPU
with an appropriat e interrupt.
A packet can go into one single buffer, or it can go
fragmented into mu ltiple buffers.
Block A " Bl ock" is the amount of data that is transfered from the
memory to the XFIFO ( transm i t DMA transfer) or from the
RFIFO to the memory. In HDLC/PPP modes the block size
is 32 bytes by default. It can be lowered with the receive
FIFO threshold in register CCR3H, bit field ’RFTH(1..0)’.
Bus Cycle A "Bus Cycle" corresponds to a single byte/word transfer.
Multiple bus cycles make up a block transfer.
DMA Transfer A "DMA Transfer" is the movement of compl ete buffers
and/or packets between the XFIFO/RFIFO and the
memory.
PEB 20542
PEF 20542
Programming
Preliminary Data Sheet 6-260 08.99
protocol machine appends the trailer (e.g. CRC and Flag in HDLC) , i f applicable. The
Transmit DMA Transfer End (TDTE) interrupt is generated (refer to Figure 6-3).
• If a transmit p acket is distributed over more than one transmit buffer in memory, the
’XF’ command (without setting the ’XME’ bit) starts transmission of a buffer. A
Transmit DMA Transfer End (TDTE) interrupt is generated whenever a block of
<XBC1> bytes is completely transferred. For the last buffer, containing the end of the
transmit packet, the ’XF’ command is issued together with bit ’XME’ set (refer to
Figure 6-4).
After transmission is complete, the optional generation of the ALLS interrupt indicates
that all transmit data has been sent on pin TxD.
Any ’XF’ command resets the transmit DMA controller for new operation starting with
TBADDR1 again.
Note: In HDLC Automode, the ’XF’ command may be replaced by the ’XIF’ command in
the same register, when transm i ssion of an I-frame is desired .
Figure 6-3 DM A Transm it (Single Buffer per Packet)
CPU / MEMORY MISTRAL
TBADDR1
XBC1
(write transmit buffer start address)
(wri te tran s mit by t e co u nt wi th
command bit 'XF'+'XME')
...
TFIFO
TFIFO
TFIFO
DMA transfer of
<XBC1> transmit
data bytes
TDTE interrupt
ALLS int errupt (o pti o nal)
TBADDR1
XBC1
(write transmit buffer start address)
(wri te tran s mit by t e co u nt wi th c omm and
bit 'XF'+'XME') ...
Packet n:
Packet (n+1):
PEB 20542
PEF 20542
Programming
Preliminary Data Sheet 6-261 08.99
Figure 6-4 Fragmented DMA Transmission (Multiple Buffers per Packet)
CPU / MEMORY MISTRAL
TBADDR1
XBC1
(write transmit buffer start address)
(wri te tran s mit by t e co u nt wi th
command bit 'X F')
...
TFIFO
TFIFO
TFIFO
DMA transfer of
<XBC1> transmit
data bytes
TDTE interrupt
ALLS int errupt (o pti o nal)
TBADDR1
XBC1
(write transmit buffer start address)
(wri te tran s mit by t e co u nt wi th c omm a nd
bit 'XF')
...
TFIFO
TFIFO
TFIFO
DMA transfer of
<XBC1> transmit
data bytes
TDTE interrupt
TBADDRi1
XBC1
(write transmit buffer start address)
(wri te tran s mit by t e co u nt wi th c omm a nd
bit 'XF'+'XME')
...
TFIFO
TFIFO
TFIFO
DMA transfer of
<XBC1> transmit
data bytes
TDTE interrupt
Packet n, Buffer 0:
Packet n, Buffer 1:
Pack e t n, Buffer m:
PEB 20542
PEF 20542
Programming
Preliminary Data Sheet 6-262 08.99
The data transmiss ion flow, from the CPU’s poin t of view, is outlined in Fi gure 6-9.
Figure 6-5 DMA Controlled Data Transmission (Flow Diagram)
6.3.2 Data Reception (DMA Controlled)
The receive DM A cont r oller has to be pr epar ed by w rit ing an appr opr iate address to its
RBADDR1L/M /H registers and th e maxim um buf fer size to regi ster RMBSL/RMBSH. If
a new packet is received by the SCC, the DMA controller will request the external bus
and then move receive data out of t he RFIFO. The receive data is directly written on the
external bus, begi nning at address R BADDR1.
Now the DMA has to face two possible scen arios:
• If the maximum buffer size programmed in register RMBSL/RMBSH has been
transferred, DMA transfer stops and a Receive Buffer Full (RBF) interrupt is
generated. The CPU now updates the receive buffer base address in the appropriate
registers RBADDR1L/M/H and restarts the DMA receiver by setting the ’RE’ bit in
register RMBSH. Optional ly the m aximum buffer size value c an be updated with the
same register write access.
START
TX DMA
READY
'TD T E ' Interr upt
E nable DM A
(s et bit 'IDMA ' in
re gis ter GMODE)
Set TxBuffer Base
Address
(TBADDR1H/M/L)
E nd of M essag e
in T xB u ffer
?
Yes
No
S et T x By te Count
('XB C') and issue
'XF'+'XME'
command
(regis te r XB C1L/H)
A c tio n ta ke n
by CP U
Interrupt
indic ation to CP U
S et T x By te Count
('XB C') and issue
'XF'
command
(regis te r XB C1L/H)
'TD T E ' Interr upt
A ction taken by
inte rn a l D M A
DM A Controller
rea ds < XBC > bytes
of trans m it da ta
DM A Controller
rea ds <XBC>
byte s of trans m it
data (incl. end of
message)
Transmit
Data a vailable
?
Yes
No
PEB 20542
PEF 20542
Programming
Preliminary Data Sheet 6-263 08.99
• If the end of a received packet/block is contained in the current receive buffer, the
DMA controller generates a Receive DMA Transfer End ( RDTE) interrupt and stops
operation. The C PU now rea ds the received byt e count from regi ste rs RBCL/RBCH,.
The receive D MA con troller wil l not conti nue oper at ion until it is set up again w ith the
’RE’ command in register RMBSH. The software should update RBADDR1L/M/H
register s if necessar y bef ore issui ng the ’RE’ comm and.
If in packet oriented protocol modes (HDLC, PPP) the maximum receive buffer size
RMBS is chosen to be larger than the expected receive packets, each buffer will contain
the whole packet (see Figure 6-6). In th is case a Rece iv e Bu ffer Fu ll (RBF) i n te rrupt will
never occur, simplifying the software. To ensure that no packets exceeding the
maximum buffer size are forwarded from the SCC to the RFIFO, the receive packet
leng th shou ld be limited with registers RLCRL/RLCRH.
Figure 6-6 DMA Receive (Single Buffer per Packet)
CPU / MEMORY MISTRAL
RBADDR1
RMBS
(wri te re c ei v e b uf fer s t ar t addre ss )
...
RFIFO
RFIFO
RFIFO
DMA transfer of all
receive data bytes
RDTE interrupt
...
Packet 0:
Packet 1:
RBC
(read RBC register)
(wri te re c ei v e b uf fer s t ar t addre ss )
RBADDR1
(set max. receive buffer size
and issue 'RE' command)
PEB 20542
PEF 20542
Programming
Preliminary Data Sheet 6-264 08.99
Figure 6-7 shows an example for fragmented reception of a packet larger than the
prepared receive buffers in memory. In this case the length of the received packet is 199
bytes, each of the buffers in host memory is 128 bytes deep:
Figure 6-7 Fragmented Reception per DMA (Example)
After the DMA controller is initialized with the base address of receive buffer #1 and the
maximum buffer size RMBS, simultaneously activated with the ’RE’ command, DMA
transfer from the RFIFO to t he rece ive buff er takes place in bl ocks of 3 2 by tes (unl ess
changed with bit field ’RFTH’ in register CCR3H).
After four 32-byte-blocks have been transferred, the first receive buffer is filled up
completely with recei ve data. The DMA con troller indi cates this by generatin g the RB F
interrupt.
Now the CPU has to provide the base addr ess of the second receive buf f er to the DMA
controller and issue the ’RE’ command again. This allows the DMA controller to continue
data transfers into the second receive buffer. After another two 32-byte-blocks have
been transferred, the remaining 7 bytes (including the RSTA byte) are written to the
buffer, follwed by the generation of the RDTE interrupt. Now the DMA transfer is
completed and software has to read the number of received bytes from the Receive Byte
Count registers RBCL/RBCH.
The following figure (Figure 6-8) gives the seq uence of actions from both, the internal
DMA controller of MISTRAL and the CPU for this example (fragmented reception of 199
bytes into two rece ive buffers ):
32 32 32 32 32 32 7
128
1
...
199 Bytes Payload
128
1
1st packet
fragment 2nd packet
fragment
...
Receive Buffe rs
in Memory
Packet
PEB 20542
PEF 20542
Programming
Preliminary Data Sheet 6-265 08.99
F igure 6-8 Fragme nted Reception Sequence (Example)
Performance:
In s ingle buffer oper ation, on ly 2 regis ter accesses are required f or transmi ssion and 3
for reception for each buffer besides first initialization:
• update TBADDR1, update XBC1 (including com m and ’XF’)
• update RBADDR1, issu e ’RE’ comm and (in RMBS register), read regist er RBC
CPU / MEMORY MISTRAL
RBADDR1
RMBS
(write recei ve buffer start address)
(issue 'RE' com mand)
RFIFO
RFIFO
RFIFO
DMA transfer of 128
receive data bytes
RBF interrupt
...
Packet 1, Fragment 1:
Packet 2, Fragment 1:
RBC
(read RBC register)
(write recei ve buffer start address)
RBADDR1
RBADDR1
(write recei ve buffer start address)
RFIFO
RFIFO
RFIFO
DMA transfer of 71
receive data bytes
RDTE interr upt
Packet 1, Fragment 2:
RFIFO
32
32
32
32
32
32
7
RMBS
(set max. receive buffer size to 128 bytes
and issue 'RE' command)
PEB 20542
PEF 20542
Programming
Preliminary Data Sheet 6-266 08.99
The data reception flow, from the CPU’s point of view, is outlined in Figure 6-9.
Figure 6-9 DMA Controlled Data Reception (Flow Diagram)
6.3.3 Buffer Switched Mode
In buffer switched mode, operation will be similar but the DMA controller will
autonomously switch between buffer base addresses TBADDR1/RBADDR1 and
TBADDR2/RBADDR2 after any buffer completion.
A reset command will force the DMAC to begin with base addresses TBADDR1/
RBADDR1. Setting bit ’XF’ (and ’XME’) in the XBC1H register will start transmission.
Setting bit ’RE’ in register RMBSH enables reception. The DMA controller automatically
reloads the configuration values (base address TBADDRi/RBADDRi and byte count
START
RX DM A R EADY
A c tion ta ke n
by CP U
Interrupt
indication to C PU
'RBF'
Interrupt
R ead R eceive
Byte Count
(RBCL/H)
'RDTE'
Interrupt
Enable DM A
(set bit 'IDM A ' in
re
g
ister GMODE)
RX DM A ACTIV E
Set Base Address
of current R xB uffer
(RBADDR1H/M/L)
Set Max Buffer
Size ('RMBS') and
Enable Rec eive
('RE ') in re
g
ister
RMBSL/H
The 'RD TE ' interrup t
indicates that the end of the
packet currently rec eived is
contained in the current
RxBuffer.
The 'RBF ' interrupt
indicates that the DM A
controller filled the current
R x B u ff e r to t h e ma ximu m
le v el ( < RMBS> bytes).
T
he en d of the packe t is not
contained in this RxBuffer.
PEB 20542
PEF 20542
Programming
Preliminary Data Sheet 6-267 08.99
XBCi/RM BS) from the alternate r egister set. Transm ission ca n be stopped by resetting
the ’XF’ bit back to ’0’.
Status bits in register DBSR indicate which buffer is currently in operation (for debug
purposes).
A TDTE interrupt indicates completion of a transmit buffer, an RDTE/RBF interrupt
indicat es com plet ion of a receive buffer.
Thus DMA operation is completely autonomous with no additional register access during
operation.
In case of HDLC/PPP packet oriented protocol mode, the buffer size is assumed to
contain complete transmit/receive packets (single buffer operation).
F urthermore t his m ode support s continuous trans mission (no HDL C/PPP framing) ver y
effectively.
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-268 08.99
7 Electrical Characteristics (Preli minary)
All electrical characteristi cs giv en in this chapter are preliminar y and subject to change .
7.1 Absol ute Maximum Ratings
Note: Stresses above those listed here may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
7.2 Operating Range
Note: In the operating range , the functions giv en in the circuit description are fulfilled.
Parameter Sym bol Limit Values Unit
Ambient temperature under bias PEB
PEF TA
TA
0 to 70
– 40 to 85 °C
°C
Storage temperature Tstg – 65 to 125 °C
IC supply volta ge VDD3 – 0.3 to 3.6 V
Voltage on any signal pin with respect to
ground VS– 0.3 to 5.5 V
ESD robustness1)
HBM: 1.5 kΩ, 100 pF
1) According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993.
VESD,HBM 2500 V
Parameter Symbol Limit Values Unit Test Condition
min. max.
Ambient temperaturePEB
PEF TA
TA
0
-40 70
85 °C
°C
Junction temper atu re TJ0125
°C
Supply voltage VDD3 3.0 3.6 V
Ground VSS 00V
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-269 08.99
7.3 Thermal Package Characteristics
T able 7-1 Thermal Package Characteris tics P-TQFP-144-10
Parameter Symbol Value Unit
T hermal Packa ge Resistance Junct ion to Ambient
Airflow: Ambient Temperature:
without airflow TA=-40°C θJA(0,-40) 43.0 K/W
without airflow TA=+25°C θJA(0,25) 38.9 K/W
airflow 1 m/s (~200 lfpm) TA=+25°C θJA(1,25) 37.0 K/W
airflow 2 m/s (~400 lfpm) TA=+25°C θJA(2,25) 36.4 K/W
airflow 3 m/s (~600 lfpm) TA=+25°C θJA(3,25) 36.0 K/W
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-270 08.99
7.4 DC Characteristics
Parameter Symbol Limit Values Unit Notes
min. max.
In put low vo lta ge VIL – 0.4 0. 8 V
Input high voltage VIH 2.0 5.5 V
Outpu t low volta ge VOL 0.45 V IOL =7mA
1)
IOL =2mA
2)
1) Apply to the next pins:
tbd
.
2) Appl y to all the I/O and O pins that do not appear in the list in note 1), except
tbd
.
The listed characteristics are ensu red o ver the operating range of the integrated
circuit. Typic al characterist ics specify m ean values e xpected o ver the production
spread. If no t otherw is e spe cif ied, typic al characterist ics app ly at
T
A
= 25
°
C and
the given supply voltage.
Output high voltage VOH 2.4 V IOH =–1.0mA
Power
supply
current
operational
(average) ICC (AV)
tbd
mA VDD =3.3V,
TA=25°C,
CLK = 20 MHz,
XTAL = 20 MHz,
inputs at VSS/VDD,
no output loads
power down
(no clocks) ICC (PD)
tbd
mA VDD =3.3V,
TA=25°C
Power dissipat ion P100 mW VDD =3.3V,
TA=25°C,
CLK = 20 MHz,
XTAL = 20 MHz,
inputs at VSS/VDD,
no output loads
Input leakage current IIL
tbd
µAVDD =3.3V,
GND = 0 V;
inputs at VSS/VDD,
no output loads
Output leakage cur rent IOZ
tbd
µAVDD =3.3V,
GND = 0 V;
VOUT =0V,
VDDP +0.4
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-271 08.99
7.5 AC Characteristics
Interface Pins
TA = 0 to + 70 °C; VDD3 = 3.3 V ± 0.3 V
Inputs are driven to 2.4 V for a logical “1” and to 0.4 V for a logical “0”. Timing
meas urem ents are made at 2.0 V for a logical “1” and at 0.8 V for a l ogical “0”.
The AC testing input/output waveforms are shown below.
Figure 7-1 Input/Output Waveform for AC Tests
7.6 Capacitances
Interface Pins
T able 7-2 Capacitances
TA = 25 °C; VDD3 = 3.3 V ± 0.3 V, VSS = 0 V
Parameter Symbol Limit Values Unit Test Condition
min. max.
Inpu t capac itance CIN
tbd tbd
pF
Output capacitance COUT
tbd tbd
pF
I/O-capacitance CIO
tbd tbd
pF
ITS09800
= 50 pF
Load
C
Test
Under
Device
0.45
2.4 2.0
0.80.8
2.0 Test Points
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-272 08.99
7.7 T im in g Diagr ams
7.7.1 Microprocessor Interface Timing
7.7.1.1 Microprocessor Interface Clock Timing
Figure 7-2 Microprocessor Interface Clock Timing
Table 7-3 Microprocessor Interface Clock Timing
No. Parameter Limit Values Unit
min. max.
1 C LK clock period 30 ns
CLK frequency 33 MHz
2 C LK high time 11 ns
3 CLK lo w time 11 ns
CLK
1
32
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-273 08.99
7.7.1.2 Siemens/Intel Bus Interface Timing (Slave Access)
•
F igure 7-3 Siemens/Int el Read Cycle Timing (Slave Access)
•
Figure 7-4 Siemens/Intel Write Cycle Timing (Slave Access)
(1) Signals BHE and D(15:8) only available in 16-bit Intel bus mode
(2) Interrupt signal shown is pu sh-pull, active high. Same timings apply to push-pul l, active low interrupt signal. In
case of open-drain output the timing depends on external components.
A(7:0)
BHE
1
)
CS
D(7:0)
D(15:8)
1
)
RD
DTACK
4657
8
14a 15a
17
11a
11
INT
2
)
16
10
14 15
A(7:0)
BHE
1
)
CS
D(7:0)
D(15:8)
1
)
WR
DTACK
4657
12 13
9
14a 15a
17
14 15
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-274 08.99
Table 7-4 Siem ens/ Intel Bus Interface Timing ( S lave Access)
No. Parameter Limit Values Unit
min. max.
4 active addres s to active RD/WR setup time 10 ns
5 inactive RD/WR to inactive address hold time 0 ns
6active CS
to active RD/WR setup time 0 ns
7 inactive RD/WR to inactive CS hol d t ime 0 ns
8RD
active pulse width tbd ns
9WR
active pulse width 30 ns
10 active RD to valid data delay 15 ns
11 inactive RD to invalid data hold time 5 ns
11a inactive RD to data high impedance delay 15 ns
12 valid data to inactive WR setup time 15 ns
13 inactive WR to invalid data hold time 5 ns
14 active RD/WR to active DTACK delay 10 ns
14a active CS to driven DTACK delay tbd ns
15 inactive RD/WR to inactive DTACK delay 10 ns
15a inactive CS to DTAC K high impedance del ay tbd ns
16 inactive RD to inactive INT/INT delay 1 TCLK
17 RD/WR in a c tive pulse width tbd n s
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-275 08.99
7.7.1.3 Motorola Bus Interface Timing (Slave Access)
•
Figure 7-5 Motorola Read Cycle Timing (Slave Access)
•
Figure 7-6 Motorola Write Cycle Timing (Slave Access)
(1) Signals LDS, UDS and D(15:8) only ava ilable in 16-bit Motorola bus mode
(2) Interrupt signal shown is pu sh-pull, active high. Same timings apply to push-pul l, active low interrupt signal. In
case of open-drain output the timing depends on external components.
A(7:0)
A(7:1)
1
)
CS
R/W
D(7:0)
D(15:8)
1
)
DS
LD S, UD S
1
)
DTACK
40
42
41
43
44 45
46
52a 53a
55
INT
2
)
49a
49
48
54
52 53
A(7:0)
A(7:1)
1
)
CS
R/W
D(7:0)
D(15:8)
1
)
DS
LD S, U DS
1
)
DTACK
40
42
41
43
44 45
50 51
47
52a 53a
55
52 53
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-276 08.99
Table 7-5 Motorola Bus Interface Timing (Slave Access)
No. Parameter Limit Values Unit
min. max.
40 act iv e addres s to activ e DS setup time 10 ns
41 inactive DS to inactive addres s hold time 0 ns
42 active CS to active DS set up time 0 ns
43 inactive DS to inactive CS hold t ime 0 ns
44 active R/W to active DS setup time 0 ns
45 inactive DS to inactive R/W hol d time 0 ns
46 DS active pulse width (read acces s) tbd ns
47 DS active pulse width (writ e access) 30 ns
48 active DS (read) to valid data delay 15 ns
49 inactive DS (read) to invalid data hold time 5 ns
49a inactive DS (read) to data high impedance delay 15 ns
50 valid data to inactive DS (write) setup tim e 1 5 ns
51 inactive DS (write) to invalid data hold time 5 ns
52 active DS to active DTACK delay 10 ns
52a active CS to driving DTACK delay tbd ns
53 inactive DS to inactiv e DTACK del ay 1 0 ns
53a inactive CS to DTAC K high impedance del ay tbd ns
54 inactive DS (read) to inactive INT/INT delay 1 T CLK
55 DS inactive pulse width tbd ns
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-277 08.99
7.7.1.4 Siemens/Intel Bus Interface Timing (Master Access)
F igure 7-7 Siemens/Int el Read Cycle Timing (Master Access)
•
Figure 7-8 Siemens/Intel Write Cycle Timing (Master Access)
(1)Signals BHE and D(15:8) only avail able in 16-bit Intel bus mode
A(23:0)
BHE
1)
ADS
D(7:0)
D(15:8)
1)
RD
READY
60a
61a
60b
6766
62a
6463
CLK
62b
W/R
61b
T1 T2 T1 T2
BGACK
68a
68a
68a
68a
68a
68b
68b
68b
68b
68b
A(23:0)
BHE
1)
ADS
D(7:0)
D(15:8)
1)
WR
READY
60a
61a
60b
6766
62a
65b
CLK
62b
W/R
61b
T1 T2 T1 T2
BGACK
68a
68a
68a
68a
68a
68a
65a
68b
68b
68b
68b
68b
68b
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-278 08.99
Table 7-6 Siem ens/ Intel Bus Interface Timing (Master Acce ss)
No. Parameter Limit Values Unit
min. max.
60a clock to valid a ddr ess delay 2 10 ns
60b clock to invalid address delay 2 10 ns
61a clock to active ADS del ay 2 10 ns
61b clock to inactive ADS delay 2 10 ns
62a clock to active RD / WR delay 2 10 ns
62b clock to inactive RD / WR del ay 2 10 ns
63 val i d data (read) to clock set up time tbd ns
64 clock to invalid data (read) hold time tbd ns
65a clock to valid data (write) delay 2 10 ns
65b clock to invalid data (write) delay 2 10 ns
66 active READY to clock set up tim e tbd ns
67 clock to inactive READY hold time tbd ns
68a clock to driving bus delay 2 10 ns
68b clock to bus high impe dance del ay 2 10 ns
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-279 08.99
7.7.1.5 Motorola Bus Interface Timi ng (Master A ccess)
Figure 7-9 Motorola Read Cycle Timing (Master Access)
•
Figure 7-10 Motorola Write Cycle Timing (Master Access)
(1) Signals LDS, UDS and D(15:8) only ava ilable in 16-bit Motorola bus mode
D(7:0)
D(15:8)
1)
70a
71a
70b
7776
72a
7473
CLK
72b
71b
BGACK
78a
78a
78a
78a
78a
78b
78b
78b
78b
78b
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
A(23:0)
A(23:1)
1)
AS
DS
LDS, UDS
1)
DTACK
R/W
A(23:0)
A(23:1)
1)
AS
D(7:0)
D(15:8)
1)
DS
LDS, UDS
1)
DTACK
70a
71a
70b
7776
72a
75b
CLK
72b
R/W
71b
S0
BGACK
78a
78a
78a
78a
78a
78a
75a
78b
78b
78b
78b
78b
78b
S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-280 08.99
Table 7-7 Motorola Bus Interface Timing (Master Access)
No. Parameter Limit Values Unit
min. max.
70a clock to valid a ddr ess delay 2 10 ns
70b clock to invalid address delay 2 10 ns
71a clock to active AS de lay 2 10 ns
71b clock to inactive AS del ay 2 10 ns
72a clock to active DS / LDS/UDS delay 2 10 ns
72b clock to inactive DS / LDS/UDS delay 2 10 ns
73 val i d data (read) to clock set up time tbd ns
74 clock to invalid data (read) hold time tbd ns
75a clock to valid data (write) delay 2 10 ns
75b clock to invalid data (write) delay 2 10 ns
76 active DTACK to clock setup tim e tbd ns
77 clock to inactive DTACK hold time tbd ns
78a clock to driving bus delay 2 10 ns
78b clock to bus high impe dance del ay 2 10 ns
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-281 08.99
7.7.1.6 Bus Arbitr ation T iming
Figure 7-11 Bus Arbitration Timing
Table 7-8 Bus Arbitration Timing
No. Parameter Limit Values Unit
min. max.
20 0 clock to acti ve BR E Q delay 2 10 ns
201 active BGNT to clock set up time tbd ns
202 clock to inactiv e BGNT hold time tbd ns
20 3 clock to acti ve BG A C K del ay 2 10 ns
204 clock to inactiv e BREQ delay 2 10 ns
CLK
BREQ
BGNT
BGACK
200 202201
203
204
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-282 08.99
7.7.2 PCM Serial Interface Timing
7.7.2 .1 Clock Input Timing
Figure 7-12 Clock Input Timing
Table 7-9 Clo ck Input Timing
No. P ara meter Limit Values Unit
min. max.
81 R xCLK clo ck period tbd ns
82 RxC LK high time tbd ns
83 RxCLK low time tbd ns
84 TxC LK clock period t bd ns
85 TxCLK hig h time tbd ns
86 TxCLK low time tbd ns
87 XTAL1 cl ock per iod (internal osc illator used) t bd ns
XTAL1 clock period (TTL clock signa l supp lied) tbd ns
88 XTAL1 hi gh time (internal osc illator used) t bd ns
XTAL1 high time (TTL clock signal supplied) tbd ns
89 XTAL1 lo w time (internal oscillat or used ) tbd ns
XTAL1 low time (TTL clock signal supplied ) t bd ns
RxCLK
TxCLK
XTAL1
81,84,87
82,85,88 83,86,89
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-283 08.99
7. 7 .2.2 R e cei ve Cyc l e Timin g
Figure 7-13 Receive Cycle Timing
Note:
1 . Whichever sup plies the recei ve clock dependin g on the select ed clo ck mod e:
externally clocked vi a Rx CLK or XTAL1 or
internally clocked via DPLL, BCR or BRG.
(No edge relation can be measured if the internal receive clock is derived from the
extern al clock sour ce by devi sion sta ges (BR G, BCR) or DPLL)
2. N RZ , NRZI and Manchest er data encoding
3. FM0 and FM1 data encoding
4. If Carrier Detect auto start feature enabled (not for clock modes 1 and 5)
90
91 92
91 92
93 94
Receive Clock
(
Note 1
)
RxD
(
Note 2
)
RxD
(
Note 3
)
CD
(
Note 4
)
91 92
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-284 08.99
Table 7-10 Receive Cycle Timing
No. P ara meter Limit Values Uni t
min. max.
Receive
data rates exter nally clocked
(HDLC) 16 Mbit/s
int ern a lly cl o cked
(DPLL modes) 2Mbit/s
int ern a lly cl o cked
(non DPLL modes) 2Mbit/s
90 Clock
period exter nally clocked
tbd
ns
int ern a lly cl o cked
(DPLL modes)
tbd
ns
int ern a lly cl o cked
(non DPLL modes)
tbd
ns
91 RxD to RxCLK s etup time
tbd
ns
92 RxD to RxCLK hold time
tbd
ns
93 CD to RxCLK rising edge setup time
tbd
ns
94 CD to RxCLK falling edge hold time
tbd
ns
PEB 20542
PEF 20542
Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-285 08.99
7.7.2.3 Transmit Cycle Timing
Figure 7-14 Transmit Cycle Timing
Note:
1. Whichever sup plies th e transm it cloc k dependi ng on the selec ted clock m ode:
externally clocked vi a TxC LK, RxCLK or XTAL1 or
internally clocked via DPLL, BCR or BRG.
(No edge relation can be measured if the internal transmit clock is derived from the
extern al clock sour ce by devisi on sta ges (BR G, BCR) or DPLL)
2. NR Z, NRZI and Manchest er data encod ing
3. FM0 and FM1 data encoding
4. If TxCLK outpu t feature is enabled (only in some clock modes )
5. The timing is valid for non bus configuration modes and bus configuration mode 1. In
bus configuration mode 2, TxD and RTS are right shifted for 0.5 TxCLK periods i.e.
driven by the falling TxCLK edge.
100
101
Transmit Clock
(Note1)
TxD
(Note2,5)
TxD
(Note3)
TxCLK
(Note4)
106
102
103
104 105
106
102
103
CxD
CTS
RTS
(Note5)
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Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-286 08.99
Table 7-11 Transmit Cycle Timing
No. P ara meter Li mit Values Unit
min. max.
Transmit
data rates externally clocked 16 Mbit/s
internally clocked
(DPLL mod es) 2 Mbit/s
internally clocked
(non DP LL mod es) 2 Mbit/s
100 Clock
period externally clocked
tbd
ns
internally clocked
(DPLL mod es)
tbd
ns
internally clocked
(non DP LL mod es)
tbd
ns
101 TxD to TxCLK delay (NRZ, NRZ I encoding )
tbd
ns
102 TxD to TxCLK delay (FM0, FM1, Manchester
encoding)
tbd
ns
103 TxD to TxCLK(out) delay (output function enabled)
tbd tbd
ns
104 CxD to TxCLK setup time,
CTS to TxCLK setu p time
tbd
ns
105 CxD to TxCLK hold time,
CTS to TxCLK hold time
tbd
ns
106 RTS to TxCLK delay (not bus configuration mode)
tbd
ns
RTS to TxCLK dela y (bus configuration mode)
tbd
ns
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Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-287 08.99
7.7.2.4 Clock Mode 1 Strobe Timing
Figure 7-15 Cl oc k Mod e 1 Strobe Timing
Note:
1. No bus conf iguratio n mode and bus con figur ation mo de 1
2. Bus configuration mode 2
3. TxD Idle is either
active high
or
high impedance
if ’open drain’ output type is selected.
T able 7-12 Cl ock Mod e 1 Strobe Timing
No. Parameter Limit Values Unit
min. max.
110 R eceive strobe to RxCLK setup
tbd
ns
111 R eceive strobe to RxCLK hold
tbd
ns
112 Trans mit strobe to RxCLK setup
tbd
ns
113 Trans mit strobe to RxCLK hold
tbd
ns
114 TxD to RxCLK dela y
tbd
ns
115 TxD to RxCLK high impe dance delay
tbd
ns
110 111
valid
112 113
114
114
115
115
RxCLK
CD
(RxStrobe)
RxD
(Note1)
TxCLK
(TxStrobe)
TxD
(Note1,3)
TxD
(Note2,3)
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Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-288 08.99
7.7.2.5 Clock Mode 5 Frame Synchronisation Timing
Figure 7-16 Clock Mo de 5 Frame Synchronisa tion Timing
Note:
1. Nor mal opera tion and bus configuration mod e 1
2. Bus confi gura tion mo de 2
Table 7-13 Clock Mode 5 Frame Synchronisation Timing
No. P ara meter Limit Values Unit
min. max.
130 Sync pulse to RxCLK setup tim e
tbd
ns
131 Sync pulse to RxCLK hold time
tbd
ns
132 TxCLKout to RxCLK delay (time slot monitor)
tbd tbd
ns
132
132
132
132
130 131
RxCLK
CD
(FSC)
TxCLK
Note1
TxCLK
Note2
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Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-289 08.99
7.7.2.6 Clock Mode 4 Receive Cycle Timing
F igure 7-17 Clock Mode 4 Receive Timing
T able 7-14 Cl ock Mode 4 Receive Timing
No. Parameter Limit Values Unit
min. max.
140 R CG setup time
tbd
ns
141 R CG hold time
tbd
ns
142 RxD setup time
tbd
ns
143 RxD hold time
tbd
ns
RxCLK
RCG
RxD
140
141
142
143
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Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-290 08.99
7.7.2.7 Clock Mode 4 Transmit Cycle Timing
Figure 7-18 Clock Mo de 4 Transmit Timing
Note: T
TxCLK
is the TxCLK signal time period.
Timing 149 results from a constant functional one clock offset + signal delay.
Table 7-15 C l ock Mo de 4 Transmit Timing
No. P ara meter Limit Values Unit
min. max.
145 TCG setup time
tbd
ns
146 TCG hold time
tbd
ns
147 TxCLK to TxD delay
tbd
ns
149 TxD to TCG active delay 1 TTxCLK
+
tbd
(ns)
TxCLK
TCG
TxD
145
146
149
147
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Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-291 08.99
7.7.3 Reset Timing
Figure 7-19 Reset Timing
Note: RESET may be asynchronous to CLK when asserted or deasserted. RESET may
be asserted during power-up or asserted after power-up. Nevertheless
de asser tion m ust be clean.
T able 7-16 Reset Timing
No. Parameter Limit Values Unit
min. max.
150
RESET
pulse width
tbd
ns
150 Number of CLK cycles during
RESET active
tbd
CLK
cycles
power-on
VDD3
CLK
RST
150
151
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Electrical Characteristics (Preliminary)
Preliminary Data Sheet 7-292 08.99
7.7.4 JTAG-Boundary Scan Timing
Figure 7-20 J TAG- Boundary Scan Timing
Table 7-17 JTAG-B oundary Scan Timing
No. P ara meter Limit Values Unit
min. max.
160 TCK period
tbd
∞ns
161 TCK high time
tbd
ns
162 TCK low tim e
tbd
ns
163 TMS setup time
tbd
ns
164 TMS hold time
tbd
ns
165 TDI setup time
tbd
ns
166 TDI hold time
tbd
ns
167 TDO valid delay
tbd
ns
160
161 162
163 164
165 166
167
TCK
TMS
TDI
TRST
TDO
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Test Modes
Preliminary Data Sheet 8-293 08.99
8 Test Modes
8.1 J TAG Bo undary Scan Interface
In the MISTRAL a Test A ccess Port (TAP) controller is implemented. The essential part
of the TAP is a finite state machine (16 states) controlling the different operational modes
of the bound ary scan. Bo th, TAP controller and bo undary scan, m eet the requirements
given by the JTAG standard: IEEE 1149.1. Figure 8-1 gives an overview about the TAP
controller.
F igure 8-1 Block Diagram of Test Access Port and Boundary Scan Unit
If no boundary scan operation is planned TRST has to be connected with V SS. TMS, TCK
and TD I do not need to be conne cted since pu ll-up transist ors ensure high i nput levels
in this case. Nevertheless it would be a good practice to put these unused inputs to
defined l evels, using pull-up resis tors.
Test handling (boundary scan operation) is performed via the pins TCK (Test Clock),
T MS (Test Mode Select), TD I (Test Dat a Input) and TD O (Test Data Out put) whe n the
TAP controller is not in its reset state, i.e. TRST is connected to VDD or it remains
unconnected due to its int ernal pull-up. Test dat a at TD I are loaded w i th a 4- MHz c lo ck
Clock Generation
Test Access Port (TAP)
TAP Controller
- Finite State Machine
- Instruction Register (3 bit)
- Test Signal Generator
CLOCK
TCK
TRST
TMS
Reset
Data in
TDI
Test
Control
TDO
Enable
Data out
CLOCK
BS Data IN
Identification Scan (32 bit)
Boundary Scan (n bit)
6
Control
Bus
ID Data out
SS Data
out n
.
.
.
.
.
.
1
2
Pins
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Test Modes
Preliminary Data Sheet 8-294 08.99
signal connected to TCK. ‘ 1’ or ‘ 0’ on TMS c auses a transit ion from o ne cont ro ller state
to another; constan t ’1’ on TMS leads to normal operation of the chip.
Table 8-1 Bounda ry Scan Sequence of MISTRAL
TDI ->
Seq.
No. Pin I/O Number of
Boundary Scan Cells Constant Value
In, Out, Enable
12
00
21
0
33
100
42
00
51
0
61
0
71
0
83
001
93
011
10 3 110
11 3 000
12 1 0
13 3 100
14 1 0
15 2 00
16 2 11
17 2 00
18 2 00
19 2 00
20 2 00
21 2 00
22 2 00
23 1 0
24 2 00
25 2 00
26 2 00
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Test Modes
Preliminary Data Sheet 8-295 08.99
27 2 00
28 2 00
29 2 00
30 2 00
31 2 00
32 1 0
33 3 000
34 3 000
35 3 000
36 2 00
37 2 00
38 2 00
39 2 00
40 2 00
41 2 00
42 2 00
43 2 00
44 3 000
45 3 000
46 1 0
47 1 0
48 3 000
49 3 0
50 3 000
51 3 000
52 1 0
53 3 000
54 3 000
55 3 000
56 3 000
Seq.
No. Pin I/O Number of
Boundary Scan Cells Constant Value
In, Out, Enable
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Test Modes
Preliminary Data Sheet 8-296 08.99
-> TDO
An input pi n (I) uses one boundar y scan cell (data in), an output pin (O) uses two c ells
(data out, enable) and an I /O- pin (I/O) uses three cel ls (data i n, dat a out , enable). Note
that some functional output and input pins of MISTRAL are tested as I/O pins in boundary
scan, hence using three cells. The b oundary scan unit of MISTRAL contains a total of
n = 158 scan cells.
The right column of Tabl e 8-1 gives th e initial iz ation values of the cells .
The desired test mode is selected by serially loading a 3-bit instruction code into the
instruction register via TDI (LSB first); see Table 8- 2.
EXTEST is used to examine the interconnection of the devices on the board. In this test
mode at first all input pins capture the current level on the corresponding external
57 3 000
58 3 000
59 3 000
60 3 000
61 3 000
62 3 000
63 3 000
64 3 000
65 2 00
66 1 0
67 1 0
68 3 000
69 2 00
70 1 0
71 1 0
72 1 0
73 1 0
74 1 0
Seq.
No. Pin I/O Number of
Boundary Scan Cells Constant Value
In, Out, Enable
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Test Modes
Preliminary Data Sheet 8-297 08.99
interconnection line, whereas all output pins are held at constant values (‘0’ or ‘1’,
accor ding to Table 8-1). Th en the contents o f th e boundary sca n is shifted to TDO. At
the same time the next scan vector i s loaded from TDI. Subsequently all output pins are
updated accord ing to the new boundary scan cont ents and al l input pins agai n capture
the curren t externa l level afterward s, and so on.
INTEST supports internal testing of the chip, i.e. the output pins capture the current level
on the corresponding internal line whereas all input pins are held on constant values (‘0’
or ‘1’, according to Table 8-1). The resulting boundary scan vector is shifted to TDO.
The next test vector is serially loaded via TDI. Then all input pins are updated for the
follo wing t est cycle .
Note: In capture IR-state the code ‘001’ is automatically loaded into the instruction
regist er, i.e. if INTEST is w ant ed the shift IR-state does not need to be passed.
SAMPLE/PRELOAD is a test mode which provides a snap-shot of pin levels during
normal operation.
IDCODE: A 32-bit identification register is serially read out via TDO. It contains the
version number (4 b its), the device code (16 bits) and the manufacturer code (11 bits).
The LSB i s fixed to ‘1’.
Note: Since in test logic reset state the code ‘011’ is automatically loaded into the
instruction register, the ID code can easily be read out in shift DR state which is
reached by TMS = 0, 1, 0, 0.
BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle.
Table 8-2 Boundary Scan Test Modes
Instruct ion (Bit 2 … 0) Test Mode
000
001
010
011
111
others
EXTEST (external test ing)
INTEST (internal testing)
SAMPLE/PRELOAD (snap-shot testing)
IDCODE (reading ID code)
BYPASS (bypass operation)
handled like BYPASS
T DI -> 0001 0000 0000 0101 1110 0000 1000 001 1 -> TDO
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Package Outlines
Preliminary Data Sheet 9-298 08.99
9 Package Outlines
P-TQFP-144-10
(Plastic Thin Quad Flat Package)
GPP09243
Sorts of Packing
Package outli nes for tubes, trays etc. ar e contained in our
Data Book “Package Information”. Dimensions in mm
