Automotive Power
Data Sheet
Rev. 1.2, 2014-07-03
TLE42754
Low Dropout Linear Fixed Voltage Regulator
TLE42754D
TLE42754G
TLE42754E
PG-TO252-5
PG-TO263-5
PG-SSOP-14 exposed pad
Type Package Marking
TLE42754D PG-TO252-5 42754D
TLE42754G PG-TO263-5 42754G
TLE42754E PG-SSOP-14 exposed pad 42754E
Data Sheet 2 Rev. 1.2, 2014-07-03
TLE42754Low Dropout Linear Fixed Voltage Regulator
1Overview
Features
• Output Voltage 5 V ± 2%
• Ouput Current up to 450 mA
• Very low Current Consumption
• Power-on and Undervoltage Reset with Programmable Delay Time
• Reset Low Down to VQ = 1 V
• Very Low Dropout Voltage
• Output Current Limitation
• Reverse Polarity Protection
• Overtemperature Protection
• Suitable for Use in Automotive Electronics
• Wide Temperature Range from -40 °C up to 150 °C
• Input Voltage Range from -42 V to 45 V
• Green Product (RoHS compliant)
• AEC Qualified
Description
The TLE42754 is a monolithic integrated low-dropout voltage
regulator in a 5-pin TO-package, especially designed for automotive
applications. An input voltage up to 42 V is regulated to an output
voltage of 5.0 V. The component is able to drive loads up to
450 mA. It is short-circuit proof by the implemented current limitation
and has an integrated overtemperature shutdown. A reset signal is
generated for an output voltage VQ,rt of typically 4.65 V. The power-on
reset delay time can be programmed by the external delay capacitor.
TLE42754
Overview
Data Sheet 3 Rev. 1.2, 2014-07-03
Dimensioning Information on External Components
An input capacitor CI is recommended for compensation of line influences. An output capacitor CQ is necessary
for the stability of the control loop.
Circuit Description
The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and drives
the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any
oversaturation of the power element. The component also has a number of internal circuits for protection against:
• Overload
• Overtemperature
• Reverse polarity
TLE42754
Block Diagram
Data Sheet 4 Rev. 1.2, 2014-07-03
2 Block Diagram
Figure 1 Block Diagram
Reset
Generator
Bandgap
Reference
Protection
Circuits
GND D
Q
RO
I
TLE42754
TLE42754
Pin Configuration
Data Sheet 5 Rev. 1.2, 2014-07-03
3 Pin Configuration
3.1 Pin Assignment TLE42754D (PG-TO252-5) and TLE42754G (PG-TO263-5)
Figure 2 Pin Configuration (top view)
3.2 Pin Definitions and Functions TLE42754D (PG-TO252-5) and TLE42754G (PG-
TO263-5)
Pin Symbol Function
1I Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
2RO Reset Output
open collector output; external pull-up resistor to a positive potential required;
leave open if the reset function is not needed
3GND TLE42754G (PG-TO263-5) only: Ground
internally connected to tab
4D Reset Delay Timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
5Q Output
block to GND with a capacitor close to the IC terminals, respecting the values given
for its capacitance CQ and ESR in the table “Functional Range” on Page 8
TAB GND Ground
connect to heatsink area
AEP02580
15
ROΙDQ
GND
GND
RO
Ι
IEP02528
DQ
PG-TO252-5 (D-PAK) PG-TO263-5 (D²-PAK)
TLE42754
Pin Configuration
Data Sheet 6 Rev. 1.2, 2014-07-03
3.3 Pin Assignment TLE42754E (PG-SSOP-14 exposed pad)
Figure 3 Pin Configuration (top view)
3.4 Pin Definitions and Functions TLE42754E (PG-SSOP-14 exposed pad)
Pin Symbol Function
1,3,5,7 n.c. not connected
leave open or connect to GND
2ROReset Output
open collector output; external pull-up resistor to a positive potential required;
leave open if the reset function is not needed
4GNDGround
6D Reset Delay Timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
8,10,11,12,
14
n.c. not connected
leave open or connect to GND
9Q Output
block to GND with a capacitor close to the IC terminals, respecting the values given
for its capacitance CQ and ESR in the table “Functional Range” on Page 8
13 I Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
Pad – Exposed Pad
connect to heatsink area;
connect with GND on PCB
n.c.
n.c.
Q
n.c.
n.c.
n.c.
I
n.c.
n.c.
D
n.c.
GND
n.c.
RO
1
2
3
4
5
6
7
14
9
10
11
12
13
8
PINCONFIG_SSOP-14.SVG
TLE42754
General Product Characteristics
Data Sheet 7 Rev. 1.2, 2014-07-03
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
Table 1 Absolute Maximum Ratings1)
-40 °C T
j 150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
1) Not subject to production test, specified by design.
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
Input
Voltage VI-42 – 45 V – P_4.1.1
Output
Voltage VQ-0.3 – 7 V – P_4.1.2
Reset Output
Voltage VRO -0.3 – 25 V – P_4.1.3
Reset Delay
Voltage VD-0.3 – 7 V – P_4.1.4
Temperature
Junction Temperature Tj-40 – 150 °C – P_4.1.5
Storage Temperature Tstg -50 – 150 °C – P_4.1.6
ESD Absorption
ESD Absorption VESD,HBM -2 – 2 kV Human Body Model
(HBM)2)
2) ESD HBM Test according AEC-Q100-002 - JESD22-A114
P_4.1.7
ESD Absorption VESD,CDM -500 – 500 V Charge Device Model
(CDM)3)
3) ESD CDM Test according ESDA STM5.3.1
P_4.1.8
ESD Absorption VESD,CDM -750 – 750 V Charge Device Model
(CDM)3) at corner pins
P_4.1.9
TLE42754
General Product Characteristics
Data Sheet 8 Rev. 1.2, 2014-07-03
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Table 2 Functional Range
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
Input Voltage VI5.5 – 42 V – P_4.2.1
Output Capacitor’s Requirements
for Stability
CQ22 – – µF –1)
1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
P_4.2.2
Output Capacitor’s Requirements
for Stability
ESR(CQ)––3 –2)
2) relevant ESR value at f=10kHz
P_4.2.3
Junction Temperature Tj-40 – 150 °C – P_4.2.4
TLE42754
General Product Characteristics
Data Sheet 9 Rev. 1.2, 2014-07-03
4.3 Thermal Resistance
Table 3 Thermal Resistance
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
TLE42754D (PG-TO252-5)
Junction to Case1)
1) not subject to production test, specified by design
RthJC – 3.7 – K/W – P_4.3.1
Junction to Ambient1) RthJA – 27 – K/W FR4 2s2p board2)
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
P_4.3.2
Junction to Ambient1) RthJA – 110 – K/W FR4 1s0p board, footprint
only3)
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
P_4.3.3
Junction to Ambient1) RthJA – 57 – K/W FR4 1s0p board, 300 mm2
heatsink area on PCB3)
P_4.3.4
Junction to Ambient1) RthJA – 42 – K/W FR4 1s0p board, 600 mm2
heatsink area on PCB3)
P_4.3.5
TLE42754G (PG-TO263-5)
Junction to Case1) RthJC – 3.7 – K/W – P_4.3.6
Junction to Ambient1) RthJA – 22 – K/W FR4 2s2p board2) P_4.3.7
Junction to Ambient1) RthJA – 70 – K/W FR4 1s0p board, footprint
only3)
P_4.3.8
Junction to Ambient1) RthJA – 42 – K/W FR4 1s0p board, 300 mm2
heatsink area on PCB3)
P_4.3.9
Junction to Ambient1) RthJA – 33 – K/W FR4 1s0p board, 600 mm2
heatsink area on PCB3)
P_4.3.10
TLE42754E (PG-SSOP-14 exposed pad)
Junction to Case1) RthJC –7–K/W– P_4.3.11
Junction to Ambient1) RthJA – 43 – K/W FR4 2s2p board2) P_4.3.12
Junction to Ambient1) RthJA – 120 – K/W FR4 1s0p board, footprint
only3)
P_4.3.13
Junction to Ambient1) RthJA – 59 – K/W FR4 1s0p board, 300 mm2
heatsink area on PCB3)
P_4.3.14
Junction to Ambient1) RthJA – 49 – K/W FR4 1s0p board, 600 mm2
heatsink area on PCB3)
P_4.3.15
TLE42754
Block Description and Electrical Characteristics
Data Sheet 10 Rev. 1.2, 2014-07-03
5 Block Description and Electrical Characteristics
5.1 Voltage Regulator
The output voltage VQ is controlled by comparing a portion of it to an internal reference and driving a PNP pass
transistor accordingly. The control loop stability depends on the output capacitor CQ, the load current, the chip
temperature and the poles/zeros introduced by the integrated circuit. To ensure stable operation, the output
capacitor’s capacitance and its equivalent series resistor ESR requirements given in the table “Functional
Range” on Page 8 have to be maintained. For details see also the typical performance graph “Output Capacitor
Series Resistor ESR(CQ) versus Output Current IQ” on Page 13. As the output capacitor also has to buffer load
steps it should be sized according to the application’s needs.
An input capacitor CI is strongly recommended to compensate line influences. Connect the capacitors close to the
component’s terminals.
A protection circuitry prevent the IC as well as the application from destruction in case of catastrophic events.
These safeguards contain an output current limitation, a reverse polarity protection as well as a thermal shutdown
in case of overtemperature.
In order to avoid excessive power dissipation that could never be handled by the pass element and the package,
the maximum output current is decreased at input voltages above VI=28V.
The thermal shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output
continuously short-circuited) by switching off the power stage. After the chip has cooled down, the regulator
restarts. This leads to an oscillatory behaviour of the output voltage until the fault is removed. However, junction
temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC’s lifetime.
The TLE42754 allows a negative supply voltage. In this fault condition, small currents are flowing into the IC,
increasing its junction temperature. This has to be considered for the thermal design, respecting that the thermal
protection circuit is not operating during reverse polarity conditions.
Figure 4 Voltage Regulator
Bandgap
Reference
GND
QI
Bl ockDiagram_Vol tageRegulator.vsd
Saturation Control
Current Limitation
Temperature
Shutdown
CQ
ESR
C}LOAD
Supply
CI
Regulated
Output Voltage
IQ
II
TLE42754
Block Description and Electrical Characteristics
Data Sheet 11 Rev. 1.2, 2014-07-03
Table 4 Electrical Characteristics Voltage Regulator
VI = 13.5V, -40°C Tj 150 °C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
Output Voltage VQ4.9 5.0 5.1 V 1 mA < IQ < 450 mA
9V < VI < 28 V
P_5.1.1
Output Voltage VQ4.9 5.0 5.1 V 1 mA < IQ < 400 mA
6V < VI < 28 V
P_5.1.2
Output Voltage VQ4.9 5.0 5.1 V 1 mA < IQ < 200 mA
6V < VI < 40 V
P_5.1.3
Output Current Limitation IQ,max 450 – 1100 mA VQ = 4.8V P_5.1.4
Load Regulation
steady-state
VQ,load -30 -15 – mV IQ= 5mA to 400mA
VI = 8 V
P_5.1.5
Line Regulation
steady-state
VQ,line –5 15mVVI = 8 V to 32 V
IQ = 5 mA
P_5.1.6
Dropout Voltage1)
Vdr = VI - VQ
1) measured when the output voltage VQ has dropped 100mV from the nominal value obtained at VI = 13.5V
Vdr –250500mVIQ = 300 mA P_5.1.7
Power Supply Ripple Rejection2)
2) not subject to production test, specified by design
PSRR –60– dBfripple = 100 Hz
Vripple = 0.5 Vpp
P_5.1.8
Temperature Output Voltage Drift dVQ/dT– 0.5 – mV/K – P_5.1.9
Overtemperature Shutdown
Threshold
Tj,sd 151 – 200 °C Tj increasing2) P_5.1.10
Overtemperature Shutdown
Threshold Hysteresis
Tj,sdh –20– °CTj decreasing2) P_5.1.11
TLE42754
Block Description and Electrical Characteristics
Data Sheet 12 Rev. 1.2, 2014-07-03
Typical Performance Characteristics Voltage Regulator
Output Voltage VQ versus
Junction Temperature Tj
Output Current Limitation IQ,max versus
Input Voltage VI
Power Supply Ripple Rejection PSRR versus
Ripple Frequency fr
Line Regulation VQ,line versus
Input Voltage Change VI
01_VQ_T J.VSD
4,60
4,70
4,80
4,90
5,00
5,10
5,20
-40 0 40 80 120 160
Tj
[°C]
VQ
[V]
VI = 13.5 V
IQ = 50 mA
03_PSRR_FR.VSD
0
10
20
30
40
50
60
70
80
90
100
0,01 0,1 1 10 100 1000
f [kHz]
PSRR [dB]
T
j
= 150 °C
T
j
= 25 °C
T
j
= -40 °C
I
Q
= 10 mA
C
Q
= 22 µF
ceramic
V
I
= 13.5 V
V
ripple
= 0.5 Vpp
04_DVQ_DVI.VSD
0
1
2
3
4
5
6
7
8
9
0 10203040
V
I [V]
Δ
V
Q
[mV]
T
j = 150 °C
T
j = 25 °C
T
j = -40 °C
TLE42754
Block Description and Electrical Characteristics
Data Sheet 13 Rev. 1.2, 2014-07-03
Load Regulation VQ,load versus
Output Current Change IQ
Output Capacitor Series Resistor ESR(CQ) versus
Output Current IQ
Dropout Voltage Vdr versus
Junction Temperature Tj
05_DVQ_DIQ.VSD
-25
-20
-15
-10
-5
0
0 100 200 300 400 500
IQ
[mA]
Δ
VQ
[mV]
VI = 8 V
Tj = -40 °C
Tj = 25 °C
Tj = 150 °C
06_ESR_IQ.VSD
0,01
0,1
1
10
100
1000
0 100 200 300 400 500
I
Q
[mA]
ESR(C Q)
[Ω]
C
Q
= 22 µF
T
j
= -40..150 °C
V
I
= 6..28 V
Stable
Region
Unstable
Region
07_VDR_TJ.VSD
0
50
100
150
200
250
300
350
400
450
500
-40 0 40 80 120 160
T
j
[°C]
V
DR
[mV]
IQ
= 400 mA
IQ
= 300 mA
IQ
= 100 mA
IQ
= 10 mA
TLE42754
Block Description and Electrical Characteristics
Data Sheet 14 Rev. 1.2, 2014-07-03
5.2 Current Consumption
Table 5 Electrical Characteristics Current Consumption
VI = 13.5V, -40°C Tj 150 °C, positive current flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
Current Consumption
Iq = II - IQ
Iq– 150 200 µA IQ = 1 mATj = 25 °C P_5.2.1
Current Consumption
Iq = II - IQ
Iq– 150 220 µA IQ = 1 mATj = 85 °C P_5.2.2
Current Consumption
Iq = II - IQ
Iq–510mAIQ = 250 mA P_5.2.3
Current Consumption
Iq = II - IQ
Iq–1525mAIQ = 400 mA P_5.2.4
TLE42754
Block Description and Electrical Characteristics
Data Sheet 15 Rev. 1.2, 2014-07-03
Typical Performance Characteristics Current Copnsumption
Current Consumption Iq versus
Output Current IQ (IQ low
)
Current Consumption Iq versus
Output Current IQ
Current Consumption Iq versus
Input Voltage VI
08_IQ_IQ_IQLOW.VSD
0
1
2
3
4
5
6
7
0 50 100 150 200
IQ
[mA]
Iq
[mA]
T
j
= 150 °C
T
j
= 25 °C
V
I
= 13.5 V
09_IQ_IQ.VSD
0
5
10
15
20
25
30
0 100 200 300 400 500
I
Q
[mA]
I
q
[mA]
T
j
= 150 °C
T
j
= 25 °C
V
I
= 13.5 V
10_IQ_VI.VSD
0
10
20
30
40
50
60
0 10203040
V
I
[V]
I
q
[mA]
RLOAD
= 12.5 Ω
RLOAD
= 500 Ω
TLE42754
Block Description and Electrical Characteristics
Data Sheet 16 Rev. 1.2, 2014-07-03
5.3 Reset Function
The reset function provides several features:
Output Undervoltage Reset:
An output undervoltage condition is indicated by setting the Reset Output RO to “low”. This signal might be used
to reset a microcontroller during low supply voltage.
Power-On Reset Delay Time:
The power-on reset delay time trd allows a microcontoller and oscillator to start up. This delay time is the time
frame from exceeding the reset switching threshold VRT until the reset is released by switching the reset output
“RO” from “low” to “high”. The power-on reset delay time trd is defined by an external delay capacitor CD connected
to pin D charged by the delay capacitor charge current ID,ch starting from VD=0V.
If the application needs a power-on reset delay time trd different from the value given in Power On Reset Delay
Time, the delay capacitor’s value can be derived from the specified values in Power On Reset Delay Time and
the desired power-on delay time:
(1)
with
•CD: capacitance of the delay capacitor to be chosen
•trd,new: desired power-on reset delay time
•trd: power-on reset delay time specified in this datasheet
For a precise calculation also take the delay capacitor’s tolerance into consideration.
Reset Reaction Time:
The reset reaction time avoids that short undervoltage spikes trigger an unwanted reset “low” signal. The reset
reaction rime trr considers the internal reaction time trr,int and the discharge time trr,d defined by the external delay
capacitor CD (see typical performance graph for details). Hence, the total reset reaction time becomes:
(2)
with
•trr: reset reaction time
•trr,int: internal reset reaction time
•trr,d: reset discharge
Reset Output Pull-Up Resistor RRO:
The Reset Output RO is an open collector output requiring an external pull-up resistor to a voltage VIO, e.g. VQ. In
Table 6 “Electrical Characteristics Reset Function” on Page 19 a minimum value for the external resistor RRO
is given for the case it is connected to VQ or to a voltage VIO < VQ. If the pull-up resistor shall be connected to a
voltage VIO > VQ, use the following formula:
(3)
CD
trd new,
trd
---------------- 47nF×=
trr trd int,trr d,
+=
RRO 5kΩ
VQ
-----------VIO
×=
TLE42754
Block Description and Electrical Characteristics
Data Sheet 17 Rev. 1.2, 2014-07-03
Figure 5 Block Diagram Reset Function
GND
QI
Bl ockDiagram_Reset.vsd
Supply
RO
V
DST
Int.
Supply
I
D,ch
I
DR,dsch
V
RT
Control
D
C
D
Reset
C
Q
VDD
Micro-
Controller
GND
I
RO
R
RO
TLE42754
Block Description and Electrical Characteristics
Data Sheet 18 Rev. 1.2, 2014-07-03
Figure 6 Timing Diagram Reset
VI
t
VQ
t
VRT
VRO
TimingDiagram_Reset.vs
t
VRO,low
1 V
1V
trr,total
trd
Thermal
Shutdown
Input
Voltage Dip
trr,total
trd trd
t < trr,total
trd
Under-
voltage
Spike at
output
Over-
load
tr r ,to tal
VDRL
VDU
t
VD
TLE42754
Block Description and Electrical Characteristics
Data Sheet 19 Rev. 1.2, 2014-07-03
Table 6 Electrical Characteristics Reset Function
VI = 13.5V, -40°C Tj 150 °C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
Output Undervoltage Reset
Output Undervoltage Reset
Switching Thresholds
VRT 4.5 4.65 4.8 V VQ decreasing P_5.3.1
Reset Output RO
Reset Output Low Voltage VRO,low –0.20.4V1V VQ VRT ;
IRO = 0.2 mA
P_5.3.2
Reset Output
Sink Current Capability
IRO,max 0.2 – – mA 1 V VQ VRT ;
VRO = 5 V
P_5.3.3
Reset Output
Leakage Current
IRO,leak –010µAVRO = 5 V P_5.3.4
Reset Output External
Pull-up Resistor to VQ
RRO 5––k1V VQ VRT ;
VRO 0.4 V
P_5.3.5
Reset Delay Timing
Power On Reset Delay Time trd 10 16 22 ms CD = 47 nF P_5.3.6
Upper Delay
Switching Threshold
VDU – 1.8 – V – P_5.3.7
Lower Delay
Switching Threshold
VDRL – 0.65 – V – P_5.3.8
Delay Capacitor
Charge Current
ID,ch –5.5–µAVD = 1 V P_5.3.9
Delay Capacitor
Reset Discharge Current
ID,dch – 100 – mA VD = 1 V P_5.3.10
Delay Capacitor
Discharge Time
trr,d – 0.5 1 µs Calculated Value:
trr,d = CD*(VDU - VDRL)/
ID,dch
CD = 47 nF
P_5.3.11
Internal Reset Reaction
Time
trr,int –47µsCD = 0 nF1)
1) parameter not subject to production test; specified by design
P_5.3.12
Reset Reaction Time trr,total – 4.5 8 µs Calculated Value:
trr,total = trr,int + trr,d
CD= 47 nF
P_5.3.13
TLE42754
Block Description and Electrical Characteristics
Data Sheet 20 Rev. 1.2, 2014-07-03
Typical Performance Characteristics
Undervoltage Reset Switching Threshold
VRT versus Tj
Power On Reset Delay Time trd versus
Junction Temperature Tj
Power On Reset DelayTime trd versus
Capacitance CD
Internal Reset Reaction Time trr,int versus Junction
Temperature Tj
11_VRT_TJ.VSD
4,4
4,5
4,6
4,7
4,8
4,9
5
-40 0 40 80 120 160
T
j
[°C]
V
RT
[V]
12_TRD_TJ.VSD
0
2
4
6
8
10
12
14
16
18
20
-40 0 40 80 120 160
Tj
[°C]
trd
[ms]
C
D
= 47 nF
13_TRD_CD.VSD
0
10
20
30
40
50
60
70
80
90
0 50 100 150 200 250
C
D
[nF]
t
rd
[ms]
T
j
= -40 °C
T
j
= 25 °C
T
j
= 150 °C
14_TRRINT_TJ.VSD
0
0,5
1
1,5
2
2,5
3
3,5
-40 0 40 80 120 160
T
j
[°C]
t
rr,int
[µs]
TLE42754
Block Description and Electrical Characteristics
Data Sheet 21 Rev. 1.2, 2014-07-03
Delay Capacitor Discharge Time trr,d versus
Junction Temperature Tj
15_TRRD_TJ.VSD
0
0,1
0,2
0,3
0,4
0,5
0,6
-40 0 40 80 120 160
T
j
[°C]
t
rr,d
[µs]
CD = 47 nF
TLE42754
Application Information
Data Sheet 22 Rev. 1.2, 2014-07-03
6 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
6.1 Application Diagram
Figure 7 Application Diagram
6.2 Selection of External Components
6.2.1 Input Pin
The typical input circuitry for a linear voltage regulator is shown in the application diagram above.
A ceramic capacitor at the input, in the range of 100nF to 470nF, is recommended to filter out the high frequency
disturbances imposed by the line e.g. ISO pulses 3a/b. This capacitor must be placed very close to the input pin
of the linear voltage regulator on the PCB.
An aluminum electrolytic capacitor in the range of 10µF to 470µF is recommended as an input buffer to smooth
out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of the linear
voltage regulator on the PCB.
An overvoltage suppressor diode can be used to further suppress any high voltage beyond the maximum rating
of the linear voltage regulator and protect the device against any damage due to over-voltage.
The external components at the input are not mandatory for the operation of the voltage regulator, but they are
recommended in case of possible external disturbances.
6.2.2 Output Pin
An output capacitor is mandatory for the stability of linear voltage regulators.
The requirement to the output capacitor is given in “Functional Range” on Page 8. The graph “Output
Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on Page 13 shows the stable operation range
of the device.
Reset
Generator
Bandgap
Reference
Protection
Circuits
GND D
Q
RO
I
TLE42754
Supply
100nF10µF
C
I1
C
I2
Regulated
Output Voltage
I
Q
C
Q
22µF
(ESR<3)
C
D
47nF
<45V
D
I
Load
(e.g.
Micro
Controller)
GND
I
I
R
RO
5k
TLE42754
Application Information
Data Sheet 23 Rev. 1.2, 2014-07-03
TLE42754 is designed to be stable with extremely low ESR capacitors. According to the automotive environment,
ceramic capacitors with X5R or X7R dielectrics are recommended.
The output capacitor should be placed as close as possible to the regulator’s output and GND pins and on the
same side of the PCB as the regulator itself.
In case of rapid transients of input voltage or load current, the capacitance should be dimensioned in accordance
and verified in the real application that the output stability requirements are fulfilled.
6.3 Thermal Considerations
Knowing the input voltage, the output voltage and the load profile of the application, the total power dissipation
can be calculated:
(4)
with
•PD: continuous power dissipation
•VI: input voltage
•VQ: output voltage
•IQ: output current
•Iq: quiescent current
The maximum acceptable thermal resistance RthJA can then be calculated:
(5)
with
•Tj,max: maximum allowed junction temperature
•Ta: ambient temperature
Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with
reference to the specification in “Thermal Resistance” on Page 9.
Example
Application conditions:
VI = 13.5 V
VQ= 5 V
IQ = 250 mA
Ta = 85 °C
Calculation of RthJA,max:
PD=(VI – VQ) • IQ + VI • Iq
= (13.5 V – 5 V) • 250 mA + 13.5 V • 10 mA
= 2.125 W + 0.135 W
=2.26W
PDVIVQ
–()IQVIIq
×+×=
RthJA max,
Tjmax,Ta
–
PD
----------------------------=
TLE42754
Application Information
Data Sheet 24 Rev. 1.2, 2014-07-03
RthJA,max =(Tj,max – Ta) / PD
= (150 °C – 85 °C) / 2.26 W
=28.76K/W
As a result, the PCB design must ensure a thermal resistance RthJA lower than 28.76 K/W. By considering
TLE42754G (PG-TO263-5 package) and according to “Thermal Resistance” on Page 9, only the FR4 2s2p
board is applicable.
6.4 Reverse Polarity Protection
TLE42754 is self protected against reverse polarity faults and allows negative supply voltage. External reverse
polarity diode is not needed. However, the absolute maximum ratings of the device as specified in “Absolute
Maximum Ratings” on Page 7 must be kept.
The reverse voltage causes several small currents to flow into the IC hence increasing its junction temperature.
As the thermal shut down circuitry does not work in the reverse polarity condition, designers have to consider this
in their thermal design.
TLE42754
Package Outlines
Data Sheet 25 Rev. 1.2, 2014-07-03
7 Package Outlines
Figure 8 PG-TO252-5
1) Includes mold flashes on each side.
4.56 0.25
M
A
6.5
5.7 MAX.
±0.1
per side
0.15 MAX.
-0.2
6.22
±0.5
9.98
(4.24) 1
A
1.14
5 x 0.6
±0.15
0.8
±0.1
+0.15
-0.05
0.1
B
-0.04
+0.08
0...0.15
0.51 MIN.
0.5
B
2.3
-0.10
0.5
+0.05
-0.04
+0.08
(5)
-0.01
0.9
+0.20
B
1)
All metal surfaces tin plated, except area of cut.
TLE42754
Package Outlines
Data Sheet 26 Rev. 1.2, 2014-07-03
Figure 9 PG-TO263-5
BA0.25
M
±0.2
GPT09113
10
8.5
1)
(15)
±0.2
9.25
±0.3
1
0...0.15
5 x 0.8
±0.1
±0.1
1.27
4.4
B
0.5
±0.1
±0.3
2.7
4.7
±0.5
2.4
1.7
0...0.3 A
1)
7.55
4 x
All metal surfaces tin plated, except area of cut.
Metal surface min. X = 7.25, Y = 6.9
Typical
1)
0.1 B
0.1
0.05
8˚ MAX.
TLE42754
Package Outlines
Data Sheet 27 Rev. 1.2, 2014-07-03
Figure 10 PG-SSOP-14 exposed pad
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
17
14 8
14
17
8
14x
0.25±0.05
±0.05
2)
M
0.15 DC A-B
0.65 C
STAND OFF
0.05
(1.45)
1.7 MAX.
0.08C
A
B
4.9±0.11)
A-BH0.1 2x
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
Bottom View
±0.2
3
±0.2
2.65
±0.2
D
H
614x
0.64
±0.25
3.9±0.11)
0.35 x 45°
0.1 HD2x
0.2 C
+0.06
0.19
8
°
MAX.
Index
Marking
Exposed
Diepad
SEATING
PLANE
6 x 0.65 = 3.9
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.Dimensions in mm
TLE42754
Revision History
Data Sheet 28 Rev. 1.2, 2014-07-03
8 Revision History
Version Date Changes
1.2 2014-07-03 “Application Information” on Page 22 added.
PG-SSOP-14 EP package outline updated.
1.11 2012-01-20 Page 19: Condition of Parameter Delay Capacitor Discharge Time, Internal
Reset Reaction Time and Reset Reaction Time corrected. Parameters are valid
for all package variants. No need to limit the Measurement conditions.
Coverpage updated.
1.1 2008-09-24 data sheet updated with new package variant in PG-SSOP-14 exposed pad:
In “Overview” on Page 2 package graphic and sales name with marking added
In Table 4.3 “Thermal Resistance” on Page 9 values for package PG-SSOP-14
exposed pad added
In “Package Outlines” on Page 25 Outlines for package PG-SSOP-14 exposed
pad added
1.0 2008-05-29 final data sheet
Edition 2014-07-03
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.