DAC8581
Serial Interface
Shift Register
Control
Logic
SCLK DAC
Latch DAC
SDIN
AVSS DVDD GND VREF
VOUT
AVDD
DAC8581
CS
CLR
DAC8581
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........................................................................................................................................... SLAS481B AUGUST 2005REVISED SEPTEMBER 2009
16-BIT, HIGH-SPEED, LOW-NOISE, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
Check for Samples: DAC8581
1FEATURES DESCRIPTION
23 16-Bit Monotonic The DAC8581 is a 16-bit, high-speed, low-noise DAC
operating from dual ±5-V power supplies. The
±5-V Rail-to-Rail Output DAC8581 is monotonic, and has exceptionally low
Very Low Glitch: 0.5 nV-s noise and exceptionally low glitch. The DAC8581
Fast Settling: 0.65 μshigh-performance, rail-to-rail output buffer is capable
Fast Slew Rate: 35 V/μsof settling within 0.65 μs for a 10-V step. Small-signal
settling time is well under 0.3 μs, supporting data
Low Noise: 20 nV/Hz update rates up to 3 MSPS. A power-on-reset circuit
±25-mA Load Drive sets the output at midscale voltage on power up.
±5-V Dual Power Supply The DAC8581 is simple to use, with a single external
Single External Reference reference and a standard 3-wire SPI interface that
Power-On Reset to Midscale allows clock rates up to 50 MHz.
3-MSPS Update Rate Also see the DAC8580, a member of the same
family. The DAC8580 combines DAC8581
SPI™ Interface, Up to 50 MHz performance with an on-chip, 16x over-sampling
1.8-V–5-V Logic Compatible digital filter.
Twos Complement Data Format The DAC8581 is specified over the –40°C to +85°C
Hardware Reset to Midscale temperature range.
TSSOP-16 Package space
APPLICATIONS
Industrial Process Control
CRT Projection TV Digital Convergence
Waveform Generation
Automated Test Equipment
Ultrasound
FUNCTIONAL BLOCK DIAGRAM OF DAC8581
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SPI is a trademark of Motorola.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DAC8581
SLAS481B AUGUST 2005REVISED SEPTEMBER 2009...........................................................................................................................................
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PACKAGE SPECIFICATION PACKAGE
DRAWING TEMPERATURE ORDERING ORDERING TRANSPORT MEDIA,
PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER QUANTITY
DAC8581IPW Tube, 90-Piece
DAC8581 TSSOP-16 PW –40°C to +85°C D8581I DAC8581IPWR Tape and Reel, 2000-Piece
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
UNIT
AVDD or DVDD to AVSS –0.3 V to 12 V
Digital input voltage to AVSS –0.3 V to 12 V
VOUT or VREF to AVSS –0.3 V to 12 V
DGND and AGND to AVSS –0.3 V to 6 V
Operating temperature range –40°C to +85°C
Storage temperature range –65°C to +150°C
Junction temperature range (TJmax) +150°C
Thermal impedance (θJA) 118°C/W
Power dissipation Thermal impedance (θJC) 29°C/W
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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........................................................................................................................................... SLAS481B AUGUST 2005REVISED SEPTEMBER 2009
ELECTRICAL CHARACTERISTICS
All specifications at TA= TMIN to TMAX, +AVDD = +5 V, –AVDD = –5 V, DVDD = +5 V (unless otherwise noted).
DAC8581
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution 16 Bits
Linearity error VREF = 4.096 V ±0.03 ±0.1 %FS
Differential linearity error ±0.25 ±0.5 LSB
Gain error 1 2 3 %FS
Gain drift ±5 ppm/°C
Bipolar zero error –5 ±25 mV
Bipolar zero drift ±20 μV/°C
Total drift ±10 ppm/°C
OUTPUT CHARACTERISTICS
VREF up to 5.5 V, when AVDD = 6 V, AVSS = –6
Voltage output –VREF VREF V
V
Output impedance 1
Maximum output current ±25 mA
CL< 200 pF, RL= 2 k, to 0.1% FS, 8-V step 0.65
Settling time μs
To 0.003% FS 1
Slew rate(1) 35 V/μs
Code change glitch 1 LSB change around major carry 0.5 nV-S
Overshoot Full-scale change 50 mV
Digital feedthrough(2) 0.5 nV-S
Digital sine wave input, fOUT = 1 kHz,
SNR 108 dB
BW = 10 kHz, 2-MSPS update rate
Digital sine wave input, fOUT = 20 kHz,
THD –72 dB
8-VPP output, 2-MSPS update rate
0.1 Hz to 10 Hz 25 μVPP
Output voltage noise At 10-kHz offset frequency 25 nV/Hz
At 100-kHz offset frequency 20 nV/Hz
Power supply rejection VDD varies ±10% 0.75 mV/V
REFERENCE
Large signal: 2-VPP sine wave on 4 V DC 3 MHz
Reference input bandwidth Small signal: 100-mVPP sine wave on 4 V DC 10 MHz
Reference input voltage range 3 AVDD V
Reference input impedance 5 k
Reference input capacitance 5 pF
DIGITAL INPUTS
VIH 0.7 x DVDD V
VIL GND 0.3 x DVDD
Input current ±1 μA
Input capacitance 10 pF
Power-on delay From VDD high to CS low 20 μs
(1) Slew rate is measured from 10% to 90% of transition when the output changes from 0 to full-scale.
(2) Digital feedthrough is defined as the impulse injected into the analog output from the digital input. It is measured when the DAC output
does not change, CS is held high, and while SCLK and SDIN signals are toggled.
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1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VREF
VOUT
AVSS
AVDD
AGND
DGND
DGND
DGND
DVDD
DGND
CLR
DVDD
DGND
CS
SCLK
SDIN
(TOP VIEW)
DAC8581
SLAS481B AUGUST 2005REVISED SEPTEMBER 2009...........................................................................................................................................
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA= TMIN to TMAX, +AVDD = +5 V, –AVDD = –5 V, DVDD = +5 V (unless otherwise noted).
DAC8581
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
+AVDD 4.0 5 6.0 V
–AVDD –4.0 –5 –6.0 V
DVDD 1.8 AVDD V
IDVDD 10 20 μA
IDD IREF and IDVDD included 17 24 mA
ISS –23 –32 mA
TEMPERATURE RANGE
Specified performance –40 +85 °C
PIN CONFIGURATION
PW PACKAGE
TSSOP-16
TERMINAL FUNCTIONS
TERMINAL
NAME NO.
VREF 1 Reference input voltage.
VOUT 2 DAC output voltage. Output swing is ±VREF
AVSS 3 Negative analog supply voltage, tie to –5 V
AVDD 4 Positive analog supply voltage, tie to +5 V
AGND 5 The ground reference point of all analog circuitry of the device. Tie to 0 V.
DGND 6, 7, 8, 15 Tie to DGND to ensure correct operation.
SDIN 9 Digital input, serial data. Ignored when CS is high.
SCLK 10 Digital input, serial bit clock. Ignored when CS is high.
Digital input. Chip Select (CS) signal. Active low. When CS is high, SCLK and SDI are ignored. When CS is low,
CS 11 data can be transferred into the device.
DGND 12 Ground reference for digital circuitry. Tie to 0 V.
DVDD 13 Positive digital supply, 1.8 V–5.5 V compatible
Digital input for forcing the output to midscale. Active low. When pin CLR is low during 16th SCLK following the
falling edge of CS, the falling edge of 16th SCLK sets DAC Latch to midcode, and the DAC output to 0 V. When
CLR 14 pin CLR is High, the falling edge of 16th SCLK updates DAC latch with the value of input shift register, and
changes DAC output to corresponding level.
DVDD 16 Tie to DVDD to ensure correct operation.
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SCLK
tLead twsck
twsck
tr
tf
-- Don’tCare
BIT-14 BIT-13, …, 1BIT-15 (MSB) BIT-0
SDIN
thi
tsu DACUpdated
tUPDAC
1st 2nd 15th 16th
ttd
CS
tsck tWAIT
DAC8581
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........................................................................................................................................... SLAS481B AUGUST 2005REVISED SEPTEMBER 2009
TIMING REQUIREMENTS(1)
PARAMETER MIN MAX UNIT
tSCK SCLK period 20 ns
tWSCK SCLK high or low time 10 ns
tLead Delay from falling CS to first rising SCLK 20 ns
tTD CS High between two active Periods 20 ns
tSU Data setup time (Input) 5 ns
tHI Data hold time (input) 5 ns
tRRise time 30 ns
tFFall time 30 ns
tWAIT Delay from 16th falling edge of SCLK to CS low 100 ns
tUPDAC Delay from 16th falling edge of SCLK to DAC output 1 μs
VDD High to CS Low (power-up delay) 100 μs
(1) Assured by design. Not production tested.
Figure 1. DAC8581 Timing Diagram
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−20
−15
−10
−5
0
5
10
15
20
0 8192 16384 24576 32768 40960 49152 57344 65536
Input Code
LE − LSBs
−0.5
−0.25
0
0.25
0.5
08192 16384 24576 32768 40960 49152 57344 65536
Input Code
DLE − LSBs
−30
−20
−10
0
10
20
30
3 3.5 4 4.5 5 5.5
INL − LSBs
VREF − Reference Voltage − V
INL max
INL min
AVDD = 6 V,
AVSS = −6 V
−30
−20
−10
0
10
20
30
3 3.5 4 4.5 5 5.5 6
INL − LSBs
INL max
INL min
AVSS = −AVDD,
VREF = AVDD −0.3 V
AVDD − Supply Voltage − V
185
187
189
191
193
−40 −20 0 20 40 60 80
TA − Free-Air Temperature − 5C
Gain Error − mV
AVDD = 5 V,
AVSS = –5 V,
VREF = 4.096 V
DAC8581
SLAS481B AUGUST 2005REVISED SEPTEMBER 2009...........................................................................................................................................
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TYPICAL CHARACTERISTICS
LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR
vs vs
INPUT CODE INPUT CODE
Figure 2. Figure 3.
INTEGRAL NONLINEARITY ERROR INTEGRAL NONLINEARITY ERROR
vs vs
VREF SUPPLY VOLTAGE
Figure 4. Figure 5.
OFFSET ERROR GAIN ERROR
vs vs
TEMPERATURE TEMPERATURE
Figure 6. Figure 7.
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−25
−23
−21
−19
−17
−15
−13
−11
−40 −20 0 20 40 60 80
TA − Free-Air Temperature − °C
ISS − Supply Current − mA
−21
−20.5
−20
−19.5
−32768 −16384 0 16384 32768
Code
ISS − Supply Current − mA
13
13.5
14
14.5
15
−32768 −16384 0 16384 32768
Code
IDD − Supply Current − mA
t − Time − 50 ns
mV − 50 mV/div
t − Time − 1µs
V − 2 V/div
DAC8581
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........................................................................................................................................... SLAS481B AUGUST 2005REVISED SEPTEMBER 2009
TYPICAL CHARACTERISTICS (continued)
POSITIVE SUPPLY CURRENT—IDD NEGATIVE SUPPLY CURRENT—ISS
vs vs
TEMPERATURE TEMPERATURE
Figure 8. Figure 9.
POSITIVE SUPPLY CURRENT—IDD NEGATIVE SUPPLY CURRENT—ISS
vs vs
CODE CODE
Figure 10. Figure 11.
LARGE-SIGNAL SETTLING SMALL-SIGNAL SETTLING
Figure 12. Figure 13.
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t − Time − 1µs
Feedthrough
FSYNC
Glitch
mV − 10 mV/div
1
10
100
1 k
100 k
10 100 1 k 10 k 100 k
10 k
− Output Noise Voltage −VnnV/ Hz
f − Frequency − Hz
−140
−130
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 2000 4000 6000
Gain − dB
f − Frequency − Hz
Fo = 1 kHz,
Fclk = 192 KSPS,
OSR = 1,
THD = −71 dB,
SNR = 113 dBFS,
Digitizer = Delta−Sigma
−140
−120
−100
−80
−60
−40
−20
0
01000 2000 3000 4000 5000 6000
f − Frequency − Hz
Code − dB
Fo = 1 kHz,
Fs = 192 KSPS
−4
−3
−2
−1
0
1
2
3
4
0 16384 32768 49152 65536
Input Code
LE − LSBs
DAC8581
SLAS481B AUGUST 2005REVISED SEPTEMBER 2009...........................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
DIGITAL FEEDTHROUGH AND MIDCODE GLITCH OUTPUT VOLTAGE NOISE
Figure 14. Figure 15.
POWER SPECTRAL DENSITY SOFTWARE-TRIMMED UNIT
FROM DC TO 6 kHz POWER SPECTRAL DENSITY
Figure 16. Figure 17.
SOFTWARE-TRIMMED UNIT
LINEARITY ERROR
vs
INPUT CODE
Figure 18.
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........................................................................................................................................... SLAS481B AUGUST 2005REVISED SEPTEMBER 2009
THEORY OF OPERATION
The DAC8581 uses a proprietary, monotonic, high-speed resistor string architecture. The 16-bit input data are
coded in twos complement, MSB-first format and transmitted using a 3-wire serial interface. The serial interface
sends the input data to the DAC latch. The digital data are then decoded to select a tap voltage of the resistor
string. The resistor string output is sent to a high-performance output amplifier. The output buffer has rail-to-rail
5 V) swing capability on a 600-, 200-pF load. The resistor string DAC architecture provides exceptional
differential linearity and temperature stability whereas the output buffer provides fast-settling, low-glitch, and
exceptionally low idle-channel noise. The DAC8581 settles within 1 μs for large input signals. Exceptionally low
glitch (0.5 nV-s) is attainable for small-signal, code-to-code output changes. The resistor string architecture also
provides code-independent power consumption and code-independent settling time. The DAC8581 resistor string
needs an external reference voltage to set the output voltage range of the DAC. To aid fast settling, VREF input is
internally buffered.
Supply Pins
The DAC8581 uses ±5-V analog power supplies (AVDD, AVSS) and a 1.8-V to 5.5-V digital supply (DVDD). Analog
and digital ground pins (AGND and DGND) are also provided. For low-noise operation, analog and digital power
and ground pins should be separated. Sufficient bypass capacitors, at least 1 μF, should be placed between
AVDD and AVSS, AVSS and DGND, and DVDD and DGND pins. Series inductors are not recommended on the
supply paths. The digital input pins should not exceed the ground potential during power up. During power up,
AGND and DGND are first applied with all digital inputs and the reference input kept at 0 V. Then, AVDD, DVDD,
AVSS, and VREF should be applied together. Care should be taken to avoid applying VREF before AVDD and AVSS.
All digital pins must be kept at ground potential before power up.
Reference Input Voltage
The reference input pin VREF is typically tied to a +3.3-V, +4.096-V, or +5.0-V external reference. A bypass
capacitor (0.1 μF or less) is recommended, depending on the load-driving capability of the voltage reference. To
reduce crosstalk and improve settling time, the VREF pin is internally buffered by a high-performance amplifier.
The VREF pin has constant 5-kimpedance to AGND. The output range of the DAC8581 is equal to ±VREF
voltage. The VREF pin should be powered at the same time, or after the supply pins. REF3133 and REF3140 are
recommended to set the DAC8581 output range to ±3.3 V and ±4.096 V, respectively.
Output Voltage
The input data format is in twos-complement format as shown in Table 1. The DAC8581 uses a
high-performance, rail-to-rail output buffer capable of driving a 600-, 200-pF load with fast 0.65-μs settling. The
buffer has exceptional noise performance (20 nV/Hz) and fast slew rate (35 V/μs). The small-signal settling time
is under 300 ns, allowing update rates up to 3 MSPS. Loads of 50 or 75 could be driven as long as output
current does not exceed ±25 mA continuously. Long cables, up to 1 nF in capacitance, can be driven without the
use of external buffers. To aid stability under large capacitive loads (>1 nF), a small series resistor can be used
at the output.
Table 1. Data Format
DIGITAL CODE
DAC OUTPUT BINARY HEX
+VREF 0111111111111111 7FFF
+VREF/2 0100000000000000 4000
0 0000000000000000 0000
–VREF/2 1011111111111111 BFFF
–VREF 1000000000000000 8000
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Glitch area is low at 0.5 nV-s, with peak glitch amplitude under 10 mV, and the glitch duration under 100 ns. Low
glitch is obtained for code-to-code (small signal) changes across the entire transfer function of the device. For
large signals, settling characteristics of the reference and output amplifiers are observed in terms of overshoot
and undershoot.
Combined with ±5-V output range, and extremely good noise performance, the outstanding differential linearity
performance of this device becomes significant. That is, each DAC step can be clearly observed at the DAC
output, without being corrupted by wideband noise.
SERIAL INTERFACE
The DAC8581 serial interface consists of the serial data input pin SDIN, bit clock pin SCLK, and chip-select pin,
CS. The serial interface is designed to support the industry standard SPI interface up to 50 MHz. The serial
inputs are 1.8-V to 5.5-V logic compatible.
CS operates as an active-low, chip-select signal. The falling edge of CS initiates the data transfer. Each rising
edge of SCLK following the falling edge of CS shifts the SDIN data into a 16-bit shift register, MSB-first. At the
16th rising edge of SCLK, the shift register becomes full and the DAC data updates on the falling edge that
follows the 16th rising edge. After the data update, further clocking gets ignored. The sequence restarts at the
next falling edge of CS. If the CS is brought high before the DAC data are updated, the data are ignored. See the
timing diagram (Figure 1) for details.
Pin CLR
Pin CLR is implemented to set the DAC output to 0 V. When the CS pin is low during the 16th SCLK cycle
following the falling edge of CS, the falling edge of the 16th SCLK sets the DAC latch to midcode, and the DAC
output to 0 V. If the CLR pin is high during the 16th clock, the falling edge of the 16th clock updates the DAC
latch with the input data. Therefore, if the CLR pin is brought back to High from Low during serial communication,
the DAC output stays at 0 V until the falling edge of the next 16th clock is received. The CLR pin is active low.
CLR low does not affect the serial data transfer. The serial data input doe not get interrupted or lost while the
output is set at midscale.
SCLK
This digital input pin is the serial bit-clock. Data are clocked into the device at the rising edge of SCLK.
CS
This digital input pin is the chip-select signal. When CS is low, the serial port is enabled and data can be
transferred into the device. When CS is high, all SCLK and SDIN signals are ignored.
SDIN
This digital input is the serial data input. Serial data are shifted on the rising edge of the SCLK when CS is low.
10 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): DAC8581
MCU DAC8581
Lookup
Table
(FLASH)
MCU DAC8581
Lookup
Table
(FLASH) DVM
Board
Tester
Computer
Board
Tester (A TE)
DAC8581
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........................................................................................................................................... SLAS481B AUGUST 2005REVISED SEPTEMBER 2009
APPLICATION INFORMATION
IMPROVING DAC8581 LINEARITY USING EXTERNAL CALIBRATION
At output frequencies up to 50 kHz, DAC8581 linearity error and total harmonic distortion are dominated by
resistor mismatches in the string. These resistor mismatches are fairly insensitive to temperature and aging
effects and also to reference voltage changes. Therefore, it is possible to use a piece-wise linear (PWL)
approximation to cancel linearity errors, and the calibration remains effective for different supply and VREF
voltages, etc. The cancellation of linearity errors also improves the total harmonic distortion (THD) performance.
It is possible to improve the integral linearity errors from ±25 LSB to ±1 LSB and the THD from 70 dB to almost
–98 dB (see Figure 17 and Figure 18). The improvements are at the expense of ~2x DNL deterioration, which is
not critical for the generation of large-signal waveforms.
Figure 19. A Simple Printed-Circuit Board Scheme for Calibrated Use of DAC8581
Figure 20. Production Test Setup for a DAC8581 Board With Calibration
The PWL calibration scheme uses a DAC8581 and a microcontroller unit (MCU) with flash memory, on a
printed-circuit board as seen in Figure 19. Calibration is done during board test, and the calibration coefficients
are stored permanently in flash memory as seen in Figure 20. An automated board tester is assumed to have a
precision digital voltmeter (DVM) and a tester computer. The test flow for a 1024-segment, piece-wise linear
calibration is as follows:
1. Use the tester computer to load software into the MCU to ramp the DAC8581 and:
Take a reading at each step after a short wait time
Store 65,536 readings in the tester computer volatile memory
2. Use the tester computer to:
Search the 65,536-point capture data and find the actual DAC8581 codes which would generate ideal
DAC outputs for DAC input codes 0, 64, 128, 192, .
Store these actual codes in the onboard microcontroller’s flash memory in a 1025-point array called
COEFF[].
3. Use the tester computer to program the MCU such that, when the end-user provides new 16-bit input data
D0 to the MCU:
The 10 MSBs of D0 directly index the array COEFF[].
The content of indexed memory of COEFF[] and the content of the next higher memory location are
placed in variables I1 and I2.
The six LSBs of the user data D0 with two variables I1 and I2 are used for computing Equation 1 (see
Figure 21).
Instead of D0, I0 is loaded to DAC8581
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VI1
VI0
VI2
I1
I0
I2
MainDACTransferCurve
VI0B
PWL Segment
I0B
Ideal−DACTransferCurve
I0 +I1 )(I2 *I1)(D0 *VI1)
VI2 *VI1
DAC8581
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Figure 21. The Geometry Behind the PWL Calibration
(1)
Where both x-axis and y-axis are normalized from 0 to 65535, and:
VI0: Desired ideal DAC voltage corresponding to input code D0.
VI0B: DAC8581 output voltage, which approximates VI0 after PWL calibration. This is the actual DAC8581
output for input code D0 after PWL calibration.
I0: DAC8581 code generating VI0B, an approximation to the desired voltage VI0. This is actual code
loaded into DAC latch for input code D0, after PWL calibration.
I0B: DAC8581 code, which generates output VI0. This code is approximated by the N-segment PWL
calibration.
I1: Contents of memory COEFF[], addressed by the 10 MSBs of user input code D0.
I2: Contents of the next memory location in COEFF[].
VI1: DAC8581 output voltage corresponding to code I1. Notice that (D0–VI1) is nothing but the six LSBs of
the input code D0, given that the y-axis is normalized from 0 to 65,536.
VI2: DAC8581 output voltage corresponding to code I2. Notice that (VI2–VI1) is always equal to number 64,
given that the y-axis is normalized from 0 to 65,536. Division becomes a 6-bit arithmetic right shift.
Other similar PWL calibration implementations exist. This particular algorithm does not need digital division, and
it does not accumulate measurement errors at each segment.
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........................................................................................................................................... SLAS481B AUGUST 2005REVISED SEPTEMBER 2009
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August, 2005) to Revision B ............................................................................................... Page
Updated document format to current stylistic standards ...................................................................................................... 1
Deleted lead temperature specifications from Absolute Maximum Ratings table ................................................................ 2
Deleted footnote 1 from Electrical Characteristics table ....................................................................................................... 3
Revised test conditions for voltage output specification ....................................................................................................... 3
Copyright © 2005–2009, Texas Instruments Incorporated Submit Documentation Feedback 13
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
DAC8581IPW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
DAC8581IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
DAC8581IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
DAC8581IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Sep-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC8581IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC8581IPWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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