FEATURES = Dual Outputs: 3.3V and 5V, Two Adjustables or Adjustable and 5V @ Wide Vjy Range: 4V to 40V = Ultra-High Efficiency: Up to 95% = Low Supply Current in Shutdown: 20uA Current Mode Operation for Excellent Line and Load Transient Response High Efficiency Maintained Over a Wide Output Current Range @ Independent Micropower Shutdown = Very Low Dropout Operation: 100% Duty Cycle a Synchronous FET Switching for High Efficiency Available in Standard 28-Pin SSOP APPLICATIONS Notebook and Paimtop Computers Battery-Operated Digital Devices Portable Instruments DC Power Distribution Systems TECHNOLOGY L1C1267 LTC1267-ADJ/LIC1267-ADJ5 Dual High Efficiency Synchronous Step-Down Switching Regulators DESCRIPTION The LTC1267 series are dual synchronous step-down switching regulator controllers featuring automatic Burst Mode operation to maintain high efficiencies at low output currents. The LTC1267 is composed of two sepa- rate regulator blocks, each driving a pair of external comple- mentary power MOSFETs at switching frequencies up to 400kHz. The LTC1267 uses a constant off-time current- mode architecture to provide constant ripple current in the inductor and provide excellent line and load transient response. A separate pin and on-board switch allow the MOSFET driver power to be derived from the regulated output voltage, providing significant efficiency improvement when operating at high input voltage. The output current level is user-programmable via an external current sense resistor. The LTC1267 series is ideal for applications requiring dual output voltages with high conversion efficiencies over a wide load current range in a small amount of board space. Y, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Modeis a trademark of Linear Technology Corporation. Vin 5.4V to 25V ls Cons + } soithe tout Lt 4 _ sv 3.3nF A inaras Anas tL ase | = Fav = = pcHed eecH sigazspy b+ > sisassoy = Reenses _, L8 a = O.4,F LS -RseNses Vours 0.052 20H Ou x 33nH_ 0.052 | Vous v pd PP ee 5V 2A 034 hy 5 mersi4oTs A @ varsia073 + Sours N-CH +) Sours Ut gue si9410DY tL ape =~ 0 -T 10V x2 Cr3 Cts x2 2TtpF 3Sb0pr ae 2TtpF Asengea: KRL SL-1ROSOJ Rgenses: KRL SL-1R050J L3: COILTRONICS CTX20-4 L5: COILTRONICS CTX33-4 = SHDN3, SHDNS, MSHDN ween OV = NORMAL, >2V = SHDN Figure 1. High Efficiency Dual 3.3V, 5V 4-248 MH 5518468 0012810 b10 a LI HEABSOLUTE MAXIMUM RATINGS LTC1267 LIC1267-ADJ/LIC1267-ADJ5 PACKAGE/ORDER INFORMATION Input Supply Voltage (Pin 2).............c0. -0.3V to 40V Voc Output Current (Pin 1) oes 50mA TOP VIEW OEE EXT Vog Input Voltage (Pin 28) ........scsssssessesssessees 10V Veo [7 a) ext Continuous Output Current (Pins 5, 6, 23, 24) .... 50mA vn Faz] MsHON Sense Voltages caps [3 | r75] CAPS LTC1267CG LTC1267 (Pins 13, 14, 17, 18) ............. Vec to -0.3V PaaTe 3 [4 | [25] PGATE 5 LTC1267-ADJ (Pins 12, 13, 17, 18) ..... Voc to -0.3V PORIVE 3 [5 | [24] PORIVE LTC1267-ADJS (Pins 12, 13, 17, 18)... Vogto-0.3V | SSATSL| 28] NaarE 5 Shutdown Voltages vb .. a ez vee LTC1267 (Pins 12, 19, 27) csessssscessssssecssesesenee 7V oe Fa] sans LTC1267-ADd (Pins 11, 27) ...ccssssssesssssessesesssees 7V inna [10] 119] SHONS LTC1267-ADJ5 (Pins 11, 19, 27) ....ecceessssssesseeees 7V SanD3 [11] [18] SENSE*S Operating Ambient Temperature Range...... 0C to 70C SHON [12| }17] sense-s Extended Commercial Sener 16] rs Temperature Range ........cce.ccccccssseee -40C to 85C ense's [i 8] Junction Temperature (Note 1) ........scccscsseeccssees 125C 98-L EAD PLASTIE SSOP Storage Temperature Range................ - 65C to 150C Tymax = 125C, @jq = 95C/W Lead Temperature (Soldering, 10 sec)................. 300C ropwew ORDER PART _ ORDER PART Vec Li] [28] EXT Voc NUMBER Vee Li [28] EXT Veg NUMBER vin [2] 27] MSHDN Vin [2] |27 | MSHON capt [3 26] cap2 capi [3 26] CAPS rome ie ee eeeg | LICI267CG-ADJ | penesen aeemes | LTC1267CG-ADJS PDAIVE 1 [5 | [24] PDRIVE 2 PORIVE 1 [6 | |24] PDRIVE 5 Neate 1 [6 | [23] NGATE 2 NGATE 1 [6 | [23] NGATE 5 Veer [7] [22] PGND Veot [7 | [22 ) PGND Cr [8] [24] Veco cr [8] 121] Voces hat 19 [20 | SGND2 Ia [9] 20] SGNDS senot [10] 19] Vepe SGND1 [10 19] SHONS SHON [77] 18 | SENSE*2 SHONT [11 18 | SENSE*S SENSE1 [12] [17 | SENSE2 SENSE1 [12] 17] SENSE~5 SENSE? [13] Kalen SENSE*1 [13] 16 | Cts Ves [14] 15] tre Vest [14] 15] tras G PACKAGE G PACKAGE 28-LEAD PLASTIC SSOP 28-LEAD PLASTIC SSOP Tamax = 125C, 6ya = 95C/W Tymax = 125C, By, = 95C/W Consult factory for Industrial and Military grade parts. The LTC1267 demo circuit board is now available. Consult factory. LT Wie 4-249 me 5528468 0012611 557LTC1267 LTC1267-ADJ/LIC1267-ADJ5 ELECTRICAL CHARACTERISTICS Ty = 25C, Viy = 12V, Vnsun, Vsiont,3,5 = OV (Note 2), unless otherwise nated. SYMBOL PARAMETER CONDITIONS MIN TYP MAX | UNITS Vest, 2 Feedback Voltage LTC1267-ADJ, LTC1267-ADJ5: Viy = 9V 1.21 125 1.29 V lept. 2 Feedback Current LTC1267-ADJ, LTC1267-ADJ5 0.2 1 pA Vout Regulated Output Voltage 3.3V Output LTC1267: Viy = 9V, ILoap = 700mA 3.23 3.33 3.43 V 5V Output LTC1267, LTC1267-ADJ5: Vin = 9V, ILoap = 700MA 490 5.05 5.20 V AVout Output Voltage Line Regulation Vin = 9V to 40V -40 0 40 mV Output Voltage Load Regulation | Figure 1 Circuit 3.3V Qutput 5mA < Iigap < 2.0A 40 65 mV 5V Output 5mA < Ioan < 2.0A 60 100 mV Burst Mode Output Ripple ILoap = OA 50 mVp.p Vec Internal Regulator Voltage Vin = 12V to 40V, EXT Voc = OV, lec = 10mA 425 45 475 v Vin - Voc Voc Dropout Voltage Vin = 4V, EXT Voc = Open, leg = 10MA 200 =. 300 mV lextvee EXT Veg Pin Current (Note 3) EXT Voc = 5V, Sleep Mode 360 pA lin Vin Pin Current (Note 3) Normal Viy = 12V, EXT Voc = 5V 320 yA Vin = 40V, EXT Veg = 5V 990 HA Shutdown Vin = 12V, Vusnon = 2V 15 pA Vin = 40V, VugHon = 2V 25 pA Vextyeo- | EXT Veg Switch Drop Vin = 12V, EXT Vee = 5V, lswircH = 10mA 200 = 300 mV Vec VpGaTE PGate to Source Voltage (Off) Vin = 12V -0.2 0 V Vin Vin = 40V -0.2 0 V Vsense*1,2-] Current Sense Threshold Voltage | LTC1267-ADJ, LTC1267-ADJ5 VsENSE 4,2 Vgense 1,2 =5-1V, Vept, 2 = Vour/4 + 25mV (Forced) 25 mV Vsense 1,2 =4.9V, Vepi, 2 = Vour/4 25mvV (Forced) 135 160 7180 mV Vcense*s,5| Current Sense Threshold Voltage | LTC1267 : VSENSE 3,5 Vsense_3,5 = Vour + 100mV (Forced) 25 mV VsenseE 3,5 = Vour 100mV (Forced) 135 160 180 mV VsHpn Shutdown Threshold MSHDON 0.8 1.4 2.0 Vv SHDN1, 3,5 0.6 0.8 2.0 Vv IMSHDN MSHDN Input Current Vesupn = SV 12 20 pA lor Cy Pin Discharge Current Vour in Regulation 50 70 90 pA Vout = OV 2 10 pA torr Off-Time (Note 4) Cr = 390pF, ILpap = 700mA, Viy = 10V 4 5 6 Ls ty ty Driver Output Transition Times C, = 3000pF (PDrive and NGate Pins), Vin = 6V 100 200 ns 4-250 M@ 5518468 00124612 493 a LT WBLIC1267 L1C1267-ADJ/LIC1267-ADJ5 ELECTRICAL CHARACTERISTICS ~40C < Ty < 85C, Vin = 12V, Versuon, VsHoni,3,5 = OV (Notes 2, 5), unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX | UNITS Vest. 2 Feedback Voltage LTC1267-ADJ, LTC1267-ADJS: Viy = 9V 12 125 13 =f V Vout Regulated Output Voltage Vin = 9V J 3.3V Output lLoap = 700mA 3.17 3.30 - 3.48 V 5V Output lLoap = 700mA 485 6.05 5.25 V lin Vin Pin Current (Note 3) , Normal Viy = 12V, EXT Voc = 5V 320 pA Vin = 40V, EXT Veo = 5V 550 pA Shutdown Vin = 12V, Vasuon = 2V . 15 pA Vin = 40V, Vaisupn = 2V 28 pA lextvec EXT Veg Pin Current (Note 3) EXT Vg = 5V, Sleep Mode , 360 yA Vec Internal Regulator Voltage Vin = 12V to 40V, EXT Voc = OV, Ic = 20mA 45 V Vsense*- | Current Sense Threshold Voltage | Low Threshold (Forced) 25 mV VgENSE High Threshold (Forced) 130 160 = 185 mV VMSHON Shutdown Threshold MSHDN 0.8 1.4 2.0 V tore Off-Time (Note 4) Cr = 390pF, ILoap = 700MA, Vin = 10V 3 5 7 us The @ denotes specifications which apply over the full operating "Note 4: In applications where Reenge is placed at ground potential, the temperature range. off-time increases approximately 40%. Note 1: Ty is calculated from the ambient temperature T, and power Note 5: The LTC1267/LTC1267-ADJ/LTC1267-ADJ5 are not tested and ra dissipation Pp according to the following formula: quality-assurance sampled at -40C to 85C. These specifications are LTC1267/.TC1267-ADJ/LTC1267ADJ5: Ty =Ty + (Pp x 95C/W) guaranteed by design and/or correlation. Note 2: On LTC1267 versions which have MSHDN and SHDN1, 3, 5 pins, Note 6: The logic level power MOSFETs shown in Figure 1 are rated for they must be at ground potential for testing. Voscmax) = SQV. For operation at Viy > 30V, use standard threshold Note 3: The LTC1267 Viy and EXT Vc current measurements exclude MOSFETs with EXT Voc powered fram a 9V supply. See applications MOSFET driver currents. When Voc power is derived from the output via information. EXT Voc, the input current increases by (igatecng x Duty Cycle)/Efficiency. Note 7: LTC1267-ADJ and LTC1267-ADJ5 are tested at an output of 3.3V See Typical Performance Characteristics and Applications Information. . : TYPICAL PERFORMANCE CHARACTERISTICS 5V Output Efficiency ' 3.3V Output Efficiency vs Load Current vs Load Current Load Regulation 100 95 90 Vin = 20V Vout = 3.3V Vin = 10V Vout = 3.3V 85 80 EFFICIENCY (%) EFFICIENCY (%) % AOUTPUT VOLTAGE (mV) 70 65 60 60 0.01 0.1 1 10 0.01 04 1 10 0 05 1.0 15 2.0 25 LOAD GURRENT (A) LOAD CURRENT (A) , LOAD CURRENT LTC1267 Go1 LT1267 + Goz LT61267 + Gos LT nye 4-251 MM! 5516468 0012813 3eTLTC1267 LIC1267-ADJ/LIC1267-ADJ5 TYPICAL PERFORMANCE CHARACTERISTICS 5V Output Efficiency vs Line Voltage LOGIC 95 LOGIC THRESHOLD GATE, 1A 4A 40 = NOTES 90 = = as 3 3 8 5 & & 80} tyeesHoLD s S GATE, 0.1A 2 GATE, 0.1A 5 a m7 STANDARD 5 -20 . 2 THRESHOLD GATE, 1A 70 | THRESHOLD GATE, 3 bad Vextvec = 9V ~40 THRESHOLD GATE, 0. 65 THRESHOLD GATE, 0. 3.3V Output Efficiency vs Line Voltage 100 60 Line Regulation QD 3S 10 15 20 2 30 35 40 0 5 10 15 20 25 30 35 40 o 5 10 18 20 2 30 35 40 0 5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V} LTC1287 * G04 LTG+267 + GOS: LT1267 G06 Operating Frequency vs (Vin - Vout) Off-Time vs Output Voltage Current Sense Threshold Voltage 20 160 180 Vout = 5V oc _ fLoap = 700mA ee 140 160 a = is ga F004 120 . S oa 1 we 4 = =| = 10 = 80 5 5 / S us Ss 8 60 B z OUTPUT REGULATOR 2 Z 05 40 S / 5V OUTPUT REGULATOR MINIMUM THRESHOLD 20 o 5 10 15 20 25 (Vin - Vout) VOLTAGE (V) LrG1267 Gor Q 0 05 10 15 20 25 3.0 36 4.0 45 5.0 OUTPUT VOLTAGE (V) LTG1267 + Fos 0 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C) LTG1267 GOS. PIN FUNCTIONS (Applies to both regulator sections Vin: Main Supply Input Pin. EXT Vee: External Vcc Supply for the Regulators. See EXT Vec Pin Connection. Vee: Output of the Internal 4.5V Linear Regulator, EXT Vec Switch, and Supply Inputs for Driver and Control Circuits. The driver and control circuits are powered from the higher of the 4.5V regulator or EXT Voc voltage. Must be closely decoupled to the power ground. PGNO: Power Ground. Connect to the source of N-channel MOSFET and the (-) terminal of Ciy. SGND: Small-Signal Ground. Must be routed separately from other grounds to the (-) terminal of Cour. PGATE: Level Shifted Gate Drive for the Top P-channel MOSFET. The voltage swing at the PGate pin is from Vix to (Vin ~ Voc). PDRIVE: High Current Gate Drive for the Top P-channel MOSFET. The PDrive pin swings from Vcc to GND. NGATE: High Current Drive for the Bottom N-channel MOSFET. The NGate pin swings from GND to Vcc. 4-252 MM S5184b8 oo1eary cbb LT WeePIN FUNCTIONS CAP: Charge Compensation Pin. A capacitor to Voc pro- vides charge required by the PGate level shift capacitor during supply transitions. The charge compensation ca- pacitor must be larger than the gate drive capacitor. Cy: External Capacitor. From this pin to ground sets the operating frequency. (The frequency is also dependent upon the ratio Voyt/Vjn). It : Gain Amplifier Decoupling Point. The regulator cur- rent comparator threshold increases with the lry pin voltage. SENSE- : Connects to internal resistive divider which sets the output voltage. The Sense pin is also the (-) input of the current comparator. LIC1267 LIC1267-ADJ/LIC1267-ADJ5 SENSE*: The (+) Input for the Current Comparator. A built-in offset between the Sense* and Sense pins, in conjunction with Rsense, sets the current trip threshold. Vre1, 2: These pins receive the feedback voltage from an external resistive divider used to set the output voltage of the adjustable section. MSHDN: Master Shutdown Pin. Taking MSHDN high shuts down Veg and all control circuitry. SHDNT, 3, 5: These pins shut down the individual regula- tor control circuitry (Vcc is not affected). Taking SHDN1, 3, 5 pins high turns off the control circuitry of adjustable 1,3.3V, 5V sections and holds both MOSFETs off. Must be at ground potential for normal operation. FUNCTIONAL DIAGRAM (Internal divider broken at Vegi 2 for adjustable versions. Only one regulator block shown.) VIN MSHDN CH LOW DROPOUT 4,.5V REGULATOR LOW DROPOUT 550k SWITCH AAA PGATE > 550k Lr PORIVE PGND , SENSE* SENSE NGATE VtHe OFF-TIME CONTROL | SENSE <A St 25mV TO 150mV AAA VVV Vos +| C] b125y VBI, 2 13k 100k thLAAA IpnvVvv SGND REFERENCE SHON1, 3,5 L7c1267 FO LY Liicae gm 5528468 0012815 ute 4-253LTC1267 LTC1267-ADJ/LIC1267-ADJ5 OPERATION (Refer to Functional Diagram) The LTC1267 series consists of two individual regulator blocks, each using current mode, constant off-time archi- tectures to synchronously switch an external pair of complementary power MOSFETs. The two regulators are internally set to provide output voltages of 3.3V and 5V for the LTC1267. The LTG1267-AD4J is configured to provide two adjustable output voltages, each set by their indi- vidual external resistor dividers. The LTC1267-ADJ5 has adjustable and 5V output voltages. Operating frequency is individually set on each section by the external capacitors attached to the Cr pin. The output voltage is sensed by an internal voltage divider connected to the Sense pin or external divider returned to the Veg pin (LTC1267-ADJ, LTC1267-ADJ5). A voltage comparator V and a gain block G compare the divided output voltage with a reference voltage of 1.25V.-To optimize efficiency, the LTC1267 series automatically switches between two modes of operation, Burst Mode and continuous mode. The voltage comparator is the primary control element when the device is in Burst Mode operation, while the gain block controls the output voltage in continuous mode. A low dropout 4.5V regulator provides the operating voltage Voc for the MOSFET drivers and control circuitry during start-up. During normal operation, the LTC1267 family powers the drivers and control from the output via the EXT Vcc pin to improve efficency. The NGate pin is referenced to ground and drives the N-channel MOSFET gate directly. The P-channel gate drive must be referenced to the main supply input Vjy, which is accomplished by level-shifting the PDrive signal via an internal 550k resis- tor and an external capacitor. During the switch ON cycle in continuous mode, current comparator C monitors the voltage between Sense* and Sense pins connected across an external shunt in series with the inductor. When the voltage across the shunt reaches its threshold value, the PGate output is switched to Viy, turning off the P-channel MOSFET. The timing capacitor Cy is now allowed to discharge at a rate deter- mined by the off-time controller. The discharge current is made proportional to the output voltage to model the inductor current, which decays at a rate that is also proportional to the output voltage. While the timing ca- pacitor is discharging, the NGate output is high, turning on the N-channel MOSFET. When the voltage on the timing capacitor has discharged past Vr, comparator T trips, setting the flip-flop. This causes the NGate output to go low (turning off the N-channel MOSFET) and the PGate output to also go low (turning the P-channel MOSFET back on). The cycle then repeats. As the load current increases, the output voltage decreases slightly. This causes the output of the gain stage to increase the current comparator threshold, thus tracking the load current. The sequence of events for Burst Mode operation is very similar to continuous operation with the cycle interrupted by the voltage comparator. When the output voltage is at or above the desired regulated value, the P-channel MOSFET is held off by comparator V.and the timing capacitor continues to discharge below Vyy1. When the timing capacitor discharges past Vty2, voltage compara- tor S trips, causing the internal SLEEP line to go low and the N-channel MOSFET to turn off. The circuit now enters sleep mode with both power MOSFETs turned off. In sleep mode a majority of the circuitry is turned off, dropping the quiescent current from several mA (with the MOSFETs switching) to 360A. The load current is now being supplied by the output capacitor. When the output voltage has dropped by the amount of hysteresis in comparator V, the P-channel MOSFET is again turned on and this process repeats. To avoid the operation of the current loop interfering with Burst Mode operation, a built-in offset Vos is incorporated in the gain stage. This prevents the current comparator threshold from increasing until the output voltage has dropped below a minimum threshold, To prevent both the external MOSFETs from ever being turned on at the same time, feedback is incorporated to sense the state of the driver output pins. Before the NGate output can go high, the PDrive output must also be high. Likewise, the PDrive output is prevented from going low while the NGate output is high. 4-254 MB 5518468 0012616 039 a LT WeAPPLICATIONS INFORMATION The LTC1267 Compared to the LTC1159, LTC1149 and LTC1142 Family The LTC1267 family is a dual LTC1159. Identical to the LTC1159, the LTC1267 can reduce the quiescent and shutdown currents by making use of an internal switch which allows the driver and control sections to be powered from an external source to improve efficiency. The basic LTC1267 application circuit shown in Figure 1 is limited to a maximum input voltage of 30V due to external MOSFET breakdown. If the application does not require greater than 18V operation the LTC1142HV should be used. Component Selection The basic LTC1267 application circuit is shown in Figure 1. External component selection is driven by the load requirement and begins with the selection of Regyse. Once Reense is known, Cy and L can be chosen. Next, the power MOSFETs and diode are selected. Finally, Cyy and Cour are selected and the loop is compensated. Since the adjustable, 3.3V and 5V sections in the LTC1267 are identical, the process of component selection is the same for both sections. Rsense Selection for Output Current Reense is chosen based on the required output current. The LTG1267 current comparators have a threshold range which extends from a minimum of 25mV/Reense to a maximum of 150mV/Reense. The current comparator threshold sets the peak of the inductor ripple current, yielding a maximum output current Iay equal to the peak value less half the peak-to-peak ripple current. For proper Burst Mode operation, Ipippieip-p) must be less than or equal to the minimum current comparator threshold. Since efficiency generally increases with ripple current, the maximum allowable ripple current is assumed, i.e., IRIPPLE(P-P) = 29MV/Rgense (See Cy and L Selection for Operating Frequency). Solving for Regyge and allowing a margin for variations in the LTC 1267 and external compo- nent values yields: R _ 100mV SENSE = ~TMAX. LIC1267 LTC1267-ADJ/LTC1267-ADJ5 The LTC1267 works well with values of Rsense from 0.022 to 0.20. Figure 2 shows the selection of Rene vs maximum output current. 0.20 0.15 Rgense (2) eS Ss 2 = a 0 1 2 3 4 5 MAXIMUM OUTPUT CURRENT (A) LTC1267 Foz Figure 2. Selecting Rsense The load current below which Burst Mode operation com- mences, lays and the peak short-circuit current Isc(rk) both track Iyax. Once Rgense has been chosen, Igurst and Isccp) can be predicted from the following: _ 15mV BURST ~ Be oe | _ 150mV SC(PK) RSENSE The LTC1267 automatically extends toe during a short circuit to allow sufficient time for the inductor current to decay between switch cycles. The resulting ripple current causes the average short-circuit current Iscjave) to be reduced to approximately Inax. Cy and L Selection for Operating Frequency Fach regulator section of the LTC 1267 uses a constant off- time architecture with tore determined by an external timing capacitor Cr. The value of Cy is calculated from the desired continuous mode operating frequency (fg): _ o) -3 , = 28x10 { ou fo Agraph for selecting Cy vs frequency including the effects of input voltage is given in Figure 3. LY 'ilee We 5518468 0012817 T75 = 4-255L1C1267 LTC1267-ADJ/LTC1267-ADJ5 APPLICATIONS INFORMATION 1400 Vout = 5V 1200 8 8 8 Ss Ss S ya 2S S TIMING CAPACITANCE (pF) ix] a S 2 0 50 100 150 200 250 FREQUENGY (kHz) LTG1267~ Fos Figure 3. Timing Capacitor Value As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The complete expression for operating frequency is given by: 1. py fo= \ Our torr\ Vin where: torr = 1.3 x 104 x Cy Once the frequency has been set by Cr, the inductor L must be chosen to provide no more than 0.025V/Rsense of peak-to-peak inductor ripple current. This results in a minimum required inductor value of: Luin = 5.1 x 105 x Rsense x Ct x Vout As the inductor value is increased from the minimum value, the ESR requirements for the output capacitor are eased at the expense of efficiency. If too smail an inductor is used, the LTC1267 may not enter Burst Mode operation and efficiency will be severely degraded at low currents. Inductor Core Selection Once the minimum value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalioy (MPP), or Kool Mu cores. Actual core loss is independent of core size for a fixed inductor Kool Mu is a registered trademark of Magnetics, Inc. value, but it is very dependent on inductance selected. As inductance increases, core losses go down but copper R losses increase. For additional information regarding in- ductor selection, please refer to the LTC1159 data sheet. Power MOSFET and Diode Selection Two external power MOSFETs must be selected for use with each section of the LTC1267: a P-channel MOSFET for the main switch, and an N-channel MOSFET for the synchronous switch. The peak-to-peak gate drive levels are set by the Voc voltage on the LTC1267. This voltage is typically 4.5V during start-up and 5V to 7V during normal operation (see EXT Vgc Pin Connection). Consequently, /ogic-level thresh- old MOSFETs must be used in most LTC1267 family applications. The only exceptions are applications in which EXT Vec is powered from an external supply greater than 8V, in which standard threshold MOSFETs (Vesitx) > 4V) may be used. Pay close attention to the BVpss specification for the MOSFETs as well; many of the logic- level MOSFETs are limited to 30V. Selection criteria for the power MOSFETs include the on- resistance Rpgon), reverse transfer capacitance Cres, input voltage, and maximum output current. When the LTC1267 is operating in continuous mode, the duty cycles for the two MOSFETs are given by: Duty Cycle = Sout IN N-Channel Duty Cycle = nou The MOSFET dissipations at maximum output current are given by: V P-Ch Pp = Va (Imax)? (1 + 8p) Roscon) +k (Vin)? (Imax) (Crs) fo Vin-V N-Gh Pp = BT OPF (lux)? (1 + 8y) Roscow) 4-256 Me 5518464 0012818 LT We 501APPLICATIONS INFORMATION Where 6 is the temperature dependency of Rogiquy and k is a constant inversely related to the gate drive current. Both MOSFETs have I@R losses, while the P-channel equation includes an additional term for transition losses, which are highest at high input voltages. For Vix < 20V, the high current efficiency generally improves with larger MOSFETs, while for Vy > 20V, the transition losses rapidly increase to the point that the use of a higher Ros(on) device with lower Crse actually provides higher efficiency. The N-channel MOSFET losses are the greatest at high input voltage or during a short circuit when the N-channel duty cycle is nearly 100%. The term (1 + 8) is generally given for a MOSFET in the form of a normalized Rpgon) vs temperature curve, but 8 = 0,007/C can be used as an approximation for low voltage MOSFETS. Crss is usually specified inthe MOSFET electrical characteristics. The constant k = 5 can be used for the LTC1267 to estimate the relative contributions of the two terms in the P-channel dissipation equation. The Schottky diodes D3 and D5 shown in Figure 1 only conduct during the dead-time between the conduction of the respective power MOSFETs. The sole purpose of D3 and D5 is to prevent the body diode of the N-channel MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency (although there are no other harmful effects if D3 and D5 are omitted). Therefore, D3 and D5 should be selected for a forward voltage of less than 0.6V when conducting Imax. Cin and Coyz Selection in continuous mode, the source current of the P-channel MOSFET is a square wave of duty cycle Voy7/Vin. To prevent large voltage transients, a low ESR input capaci- tor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: [Your(Vin - Vour)]2 Vin This formula has a maximum at Viy = 2Voyr where Ips = loyr/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours Cin Required lems ~ MAX LIC126/ LIC1267-ADJ/LIC1267-ADJ5 of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. An additional 0.1pF ceramic capacitor is also required on Vjy for high frequency decoupling. The selection of Coyr is driven by the required Effective Series Resistance (ESR). The ESR of Coy must be less than twice the value of Rsense for proper operation of the LTC1267: Court Required ESR < 2Reense Optimum efficiency is obtained by making the ESR equal to Rgense. As the ESR is increased up to 2Rsenge, the efficiency degrades by less than 1%. if the ESR is greater than 2Reense, the voltage ripple on the output capacitor will prematurely trigger Burst Mode operation, resulting in disruption of continuous mode and an efficiency hit which can be several percent. Manufacturers such as Nichicon, United Chemicon, and Sprague should be considered for high performance ca- pacitors. In surface mount applications multiple capaci- tors may have to be paralleled to meet the capacitance, ESR, or RMS current handling requirements of the appli- cation. For additional information regarding capacitor selection, please refer to the LTC1159 data sheet. At low supply voltages, a minimum capacitance at Coyr is needed to prevent an abnormal low frequency operating mode (see Figure 4). When Coyy is made too small, the output ripple at low frequencies will be large enough to trip 1000 es ee | L=50uH PSN iss = 0.02Q a 800 ' a > L=25yH g Ps NSE = 0.022 IN = 600 ~ rN 2 Ms ms Ns a MN = mM a S 400 sy - 2 L=50uH MN a 5 Reewse = 0.0582 PN M 200 hm 0 0 1 2 3 4 5 (Vin Vou) VOLTAGE (v) (101267 + Foa Figure 4. Minimum Suggested Coyr LY MLS me S5184ba8 0022829 648 = 4-257LTC1267 LTC1267-ADJ/LIC1267-ADJS APPLICATIONS INFORMATION the voltage comparator. This causes Burst Mode opera- tion to be activated when the LTC1267 would normally be in continuous operation. The effect is most pronounced with low values of Rseyse and can be improved by oper- ating at higher frequencies with lower values of L. The output remains in regulation at all times. EXT Vec Pin Connection The LTC1267 contains an internal PNP switch connected between the EXT Voc and Vcc pins. The switch closes and supplies the Vec power whenever the EXT Vcc pinis higher in voltage than the 4.5V internal regulator. This allows the MOSFET driver and control power to be derived from the output during normal operation and from the internal regulator when the output is out of regulation (start-up, short circuit). Significant efficiency gain can be realized by powering Vcc from the output, since the Viy current resulting from the driver and control currents will be scaled by a factor of Duty Cycle/Efficiency. For LTC1267, LTC1267-ADJ or LTC1267-ADJ5 this simply means connecting the EXT Vec pin directly to Voyr of the 5V regulator. The following list summarizes the four possible connec- tions for EXT Veg: 1. EXT Veg left open. This will cause Voc to be powered only from the internal 4.5V regulator, resulting in re- duced MOSFET gate drive levels and an efficiency penalty of up to 10% at high input voltages. 2. EXT Vec connected directly to highest Voyr of the two regulators. This is the normal connection for LTC1267/ LTC1267-ADJ/LTC1267-ADJ5 and provides the high- est efficiency. 3. EXT Vec connected to an output-derived boost net- work. For 3.3V and other low voltage regulators, effi- ciency gains can still be realized by connecting EXT Voc to an output-derived voltage which has been boosted to greater than 4.5V. This can be done either with the inductive boost winding shown in Figure 5a or the capacitive charge pump shown in Figure 5b. The charge pump has the advantage of simple magnetics and generally provides the highest efficiency at the expense of a slightly higher parts count. 1N4148 Le r~ 1pF Pi nl Vout a vvV 3.3V 1 Cour LTC1267FGSA Figure 5a. Inductive Boost Circuit for EXT Ver Cin ~_ ni VN2222LL BAT 8 L___ Rgense Vout 3.3V + Cour = Uici267 + F068" Figure 5b. Capacitive Charge Pump for EXT Voc 4. EXT Veo connected to an external supply. If an external supply is available in the 5V to 10V range it may be used to power EXT Vec providing it is compatible with the MOSFET gate drive requirements. When driving stan- dard threshold MOSFETs, the external supply must always be present during operation to prevent MOSFET failure due to insufficient gate drive. Under the condition that EXT Vec is connected to Voy; which is greater than 5.5V, to power down the whole regulator, both the pins MSHDN and SHDN1 have to be pulled high. lf SHDN1 is left floating or grounded the EXT Voc may self-power from Voyt1, preventing com- plete shutdown. LTC1267 Adjustable Applications When an output voltage other than 3.3V or 5V is required, the LTC1267-ADJ and LTC1267-ADJ5 adjustable ver- sions are used with an external resistive divider from Vout to the Vegi, 2 pins. This is shown in Figure 6. The regulated voltage is determined by: fy, R2 Vour= {1 + Bt 1250 4-258 MB 5518468 0012820 SLT aAPPLICATIONS INFORMATION The Vepi, 2 pin is extremely sensitive to pickup from the inductor switching node. Care should be taken to isolate the feedback network from the inductor and a 100pF capacitor should be connected between the Vegi, 2 and SGND pins next to the package. The circuit in Figure 6 cannot be used to regulate a Voy which is greater than the maximum voltage allowed on the LTC1267 EXT Voc pin (10V). In applications with Vout > 10V, Rsense must be moved to the ground side of the output capacitor and load. This operates the current sense comparator at OV common mode, increasing the off-time approximately 40% and requiring the use of a smaller timing capacitor Cy. RseNse Vegi, 2 Vout + 100pF s Ri Cour SGND STG 1287 + #06 Figure 6. LTC1267-ADJ/LTC1267-ADJ5 External Feedback Network Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. [tis often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100% (L1+L2+L3+...) where L1, L2, etc., are the individual losses as a percent- age of input power. (For high efficiency circuits, only small errors are incurred by expressing losses as a percentage of output power.) Although all dissipative elements in the circuit produce lasses, four main sources usually account for most of the losses in LTC1267 circuits: 1, LTC1267 Viy current 2. LTC1267 Veg current 3. PR losses 4, P-channel transition losses LC1267 LIC1267-ADJ/LIC1267-ADJ5 1. LTC1267 Vjy current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. Viy currents results in a small (<1%) loss which increases with Vy. 2. LTG1267 Ve current is the sum of the MOSFET driver and control circuits currents. The MOSFET driver cur- rent results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from Vec to ground. The resulting dQ/dt is a current out of Voc which is typically much larger than the control circuit current. In continuous mode lgatecug = {9(Qp +Qn), where Qp and Qy are the gate charges of the two MOSFETs. By powering EXT Vcc from an output-derived source, the additional V;y current resulting from the driver and control currents will be scaled by a factor of Duty Cycle/ Efficiency. For example, in a 20V to 5V application, 10mA of Voc current results in approximately 3mA of Vin current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from Vin) to only a few percent. 3. IR losses are easily predicted from the DC resistances of the MOSFET, inductor, and current shunt. In continu- ous mode all the output current flows through L and Rsense; but is chopped between the P-channel and N- channel MOSFETs. If the two MOSFETs have approxi- mately the same Rosion), then the resistance of one MOSFET can simply be summed with the resistances of L and Regge to obtain IR losses. For example, if each Roscon) = 0.10, Ry = 0.158, and Reense = 0.05, then the total resistance is 0.3Q. This results in losses ranging from 3% to 12% as the output current increases from 0.5A to 2A. I@R losses cause the efficiency to roll off at high output currents. 4, Transition losses apply only to the P-channel MOSFET and only when operating at high input voltages (typically 20V or greater). Transition losses can be estimated from: Transition Loss ~ 5 x Viy? x Imax x Crags x fo Other losses including Cjy and Cgy7 ESR dissipative losses, Schottky conduction losses during dead-time, LY Tee Me 5518468 0012421 YT 4-259LTC1267 LTC1267-ADJ/LIC1267-ADJ5 APPLICATIONS INFORMATION and inductor core losses, generally account for less than 2% total additional loss. Auxiliary WindingsSuppressing Burst Mode Operation The LTC1267 synchronous switch removes the normal limitation that power must be drawn from the inductor primary winding in order to extract power from auxiliary windings. With synchronous switching, auxiliary outputs may be loaded without regard to the primary output load, providing that the loop remains in continuous mode operation. Burst-Mode operation can be suppressed at low output currents with a simple external network which cancels the 25mV minimum current comparator threshold. This tech- nique is also useful for eliminating audible noise from certain types of inductors in high current (I9yt > 5A) applications when they are lightly loaded. An external offset is put in series with the Sense~ pin to subtract from the built-in 25mvV offset. An example of this technique is shown in Figure 7. Two 100Q resistors are inserted in series with the sense leads from the sense resistor. (161267 - Fo? Figure 7. Suppressing Burst Mode Operation With the addition of R3 a current is generated through R1 causing an offset of: Vorrset = Vout as a =3| If Vorrser > 25mV, the built-in offset will be cancelled and Burst Mode operation is prevented from occurring. Since Vorrser is constant, the maximum load current is also decreased by the same offset. Thus, to get back to the same Imay, the value of the sense resistor must be reduced: 75 RseNnse ~ iwax moQ To prevent noise spikes from erroneously tripping the current comparator, a 1000pF capacitor is needed across Sense* and Sense pins. Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1267. These items are also illustrated graphically in the layout diagram of Figure 8. In general each block should be self-contained with little cross coupling for best performance. Check the following in your layout: 1. Are the signal and power grounds segregated? The LTC1267 signal ground must return to the () plate of Cour. The power ground returns to the source of the N-channel MOSFET, anode of the Schottky diode, and () plate of Cjy, which should have as short lead lengths as possible. 2. Does the LTC1267 Sense pin connect to a point close to Rsense and the (+) plate of Coyr? In adjustable applications the resistive divider R1 and R2 must be connected between the (+) plate of Coy and signal ground. 3. Are the Sense~ and Sense * leads routed together with minimum PC trace spacing? The 1000pF capacitor between the two Sense pins should be as close as possible to the LTC1267. Up to 1002 may be placed in series with each Sense lead to help decouple the Sense pins. However, when these resistors are used the capacitor should be no larger than 1000pF. 4, Does the (+) plate of Cj connect to the source of the P-channel MOSFET as closely as possible? An addi- tional 0.1yF ceramic capacitor between Viy and power ground may be required in some applications. 5. 1s the Vcc decoupling capacitor connected closely between the Vcc pins of the LTC1267 and power ground? This capacitor carries the MOSFET driver peak currents. 4-260 ME 5518468 0012822 LT WIR 332APPLICATIONS INFORMATION LTC1267 LIC1267-ADJ/LTC1267-ADJ5 1N4148 x a O15 uF P-CH wen ot OApF ba | D3 NO Cing 313 7 + 8 , rr 3300pF = 1k 10 Couts ota R SENSES if "1 WA zt sHons 2 13 == 1000pF , Vouts Vin A 1N4148 MSHDN 0.15uF Lil P-CH O.1uF pe cn I D5 s Cins bs TF + L NS SHONS os Y Cours > < * Rsenses = 10000F Vours BOLD LINES INDICATE HIGH CURRENT PATHS 3300pF tk LTC1267 + Fos Figure 8. LTC1267 Layout Diagram 6. In adjustable versions, the feedback pin is very sensi- tive to pickup from the switch node. Care must be taken to isolate Vrp1, 2 from possible capacitive coupling of the inductor switch signal. 7. Are MSHDN and SHDN1, 3, 5 actively pulled to ground during normal operation? These shutdown pins are high impedance and must not be allowed to float. Troubleshooting Hints Since efficiency is critical to LTC1267 applications, it is very important to verify that the circuit is functioning correctly in both continuous and Burst Mode operation. The waveform to monitor is the voltage on the Cy pin. In continuous mode (I_oap > Igursr) the voltage on the Cy pin should be a sawtooth with a 0.9Vp.p swing. This voltage should never dip below 2V as shown in Figure 9a. When load currents are low (ILoap < Igurst) Burst Mode operation occurs. The voltage on the Cy pin now falls to ground for periods of time as shown in Figure 9b. If the Cy is observed falling to ground at high output currents, itindicates poor decoupling orimproper ground- ing. Refer to the Board Layout Checklist. Inductor current should also be monitored. Look to verify that the peak-to-peak ripple current in continuous mode Operation is approximately the same as in Burst Mode operation. TNE NDNONE NON N ov (a) CONTINUOUS MODE OPERATION TINNY [NN . ov (b) Burst Mode OPERATION LT01267 OD Figure 9. C; Waveforms LY hie 4-261 Mm = 5518468 0012823 279LIC1267 LTC1267-ADJ/LIC1267-ADJ5 TYPICAL APPLICATIONS LTC1267-ADJ Dual Regulator with 3.6V/2.5A and 5V/2A Outputs Vin 5.4V to 25V +h ne + Gini 100uF 1D0uF Div = [+ i 0.15pF 0.15 uF + | Te 1N4148 | | 1N4148 +] 4a 3uF 3! = A 3412 port tfos fas far kepcH sioasspy i sisaasby = Rsenser Lt OApF L2 _Rsense2 Vout 0.040 20nH O.1uF e 33,H 0.05 Vout 3.6V4 b SV 2.5A 2A 1000pF 1000pF pe ey EK ch po ., MBRS140T3 Non AY wprsiaors Court | + Si9410DY L N-GH +] Coure 220uF Le 20 ~(/19 Si9410DY 2L.. s00uF vet. oh R2 Ts 10V 2 100k 100pF 150k > x2 7 i% = 1% J x2 q a her Sonne Se ar = , Sri Rib 2 52.3k Ret ia 49.9k & r 1% ik 1% + Recusc1: KRL SL-1R040J "MSHON, SHON Reengeo: KRE SL-1R050J \rorasr FoI Lt: COILTRONICS CTX20-4 QV = NORMAL, >2V = SHDN L2: COILTRONICS CTX33-4 LTC1267-ADJ5 Dual Regulator with 3.45V/2.5A and 5V/2A Outputs Vin 5.4V to 25V +f Cine + Cnt Ho F 100uF Liv 50V [ 1 = pi A 1N4148 +L 3.3uF = echt Keece oO siosspy j, sisass0Y = Reenser _L Aur L2 Reense2 Vourr (0.042 = 20uH n 33uH 0.050 Vourt2 3.45V 4 4 5V 2.5A 2A 01h, 4 Ch. pe MBRS14073 de A Mersi4073 Court Courz 200ur Lt FL o20uF 10V 2 -T> tov x2 rz _ x2 q S70pr Sidon SeBoor 270pF = Ri 2 56.2k Res 1% r Reensea: KRL SL-1R040J Li: COILTRONICS CTX20-4 3 SHDN1, SHONS QV = NORMAL, >2V = SHDN Reense2: KAL SL-1R050J L2: COILTRONICS CTX33-4 Lreiere rot hm 4-262 Me 5518466 0012424 105 LI LeneLTC1267 LTC1267-ADJ/LIC1267-ADJ5 RELATED PARTS PART NUMBER | DESCRIPTION COMMENTS LTG1142 Dual Step-Down Switching Regulator Controller Dual Version of LTC1148 LTC1143 Dual Step-Down Switching Regulator Controller Dual Version of LTC1147 LTC1147 Step-Down Switching Regulator Controller Nonsynchronous, 8-Pin, Viy < 16V LTC1148 Step-Down Switching Regulator Controller Synchronous, Viy < 20V LT1149 Step-Down Switching Regulator Controiler Synchronous, Vij < 48V, for Standard Threshold FETs LTC1159 Step-Down Switching Regulator Controller Synchronous, Viy < 40V, for Logic Level FETs LTC1174 Step-Down Switching Regulator with Internal 0.5A Switch | Vjy< 18.5V, Comparator/Low Battery Detector 1701265 Step-Down Switching Regulator with Internal 1A Switch Vin < 13V, Comparator/Low Battery Detector _ LTC1266 Step-Up/Down Switching Regulator Controller Synchronous N- or P-Channel FETs, Comparator/Low Battery Detector LTC1574 Step-Down Switching Regulator with Internal 0.54 Switch | Viy < 18.5V, Comparator and Schottky Diode LT tite Me 55184ba O01e825 O41 4-263