AD5679RBCPZ-1-RL7 - ANALOG DEVICES

16-Channel, 12-/16-Bit nanoDAC+ with 2 ppm/°C Voltage

Reference Temperature Coefficient, SPI Interface

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice.

No license is granted by implication or otherwise under any patent or patent rights of Analog

Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

High performance

High relative accuracy (INL): ±4 LSB maximum at 16 bits

(AD5679/AD5679R)

TUE: ±0.14% of FSR maximum

Offset error: ±1.5 mV maximum

Gain error: ±0.06% of FSR maximum

Low drift, 2.5 V voltage reference temperature coefficient:

2 ppm/°C typical

40 mA short-circuit current

Wide operating ranges

−40°C to +125°C temperature range

2.7 V to 5.5 V power supply range

Simplified implementation

User selectable gain of 1 or 2 (GAIN pin)

1.8 V logic compatibility

50 MHz serial peripheral interface (SPI) with readback or

daisy chain

28-lead, 4 mm × 4 mm, RoHS compliant LFCSP

APPLICATIONS

Optical transceivers

Base station power amplifiers

Process control (programmable logic controller (PLC)

input/output cards)

Industrial automation

Data acquisition systems

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD5674/AD5674R/AD5679/AD5679R are low power,

16-channel, 12-/16-bit, buffered voltage output, digital-to-

analog converters (DACs) that include a 2.5 V, 2 ppm/°C internal

reference (enabled by default), and a gain select pin, resulting

in a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The

devices operate from a single, 2.7 V to 5.5 V supply range and

are guaranteed monotonic by design. The AD5674/AD5674R/

AD5679/AD5679R are available in a 28-lead lead frame chip scale

package (LFCSP) and incorporate a power-on reset (POR) circuit

that ensures that the DAC outputs power up to and remains at

zero-scale or midscale until a valid write. The AD5674/AD5674R/

AD5679/AD5679R contain a power-down mode that reduces

the current consumption to 2 μA typical.

Table 1. Octal and 16-Channel nanoDAC+® Devices

No. of

Channels Interface Reference 16-Bit 12-Bit

8 SPI1 Internal AD5676R AD5672R

External AD5676 Not

applicable

2C Internal AD5675R AD5671R

16 SPI Internal AD5679R AD5674R

External AD5679 AD5674

PRODUCT HIGHLIGHTS

1. High channel density: 16 channels in 4 mm × 4 mm

LFCSP.

2. High relative accuracy (integral nonlinearity (INL))

±4 LSB maximum.

3. Low drift, 2.5 V, on-chip reference.

INTERFACE LOGIC

INPUT

SDO

SDI

GND

LDAC

SCLK

AD5679R/AD5679/AD5674R/AD5674

RESET

2.5V REF1

VOUT0

STRING

DAC 0

BUFFER

GAIN

POWER-DOWN

LOGIC

POWER-ON

RESET

VLOG IC

GAIN

×1/×2

VDD VREF

SYNC

VOUT1

VOUT2

VOUT3

VOUT14

VOUT15

INPUT

DAC

STRING

DAC 1

STRING

DAC 2

STRING

DAC 3

STRING

DAC 14

STRING

DAC 15

BUFFER

17326-001

1ONLY APPLI CABLE TO AD5679R/AD5674R.

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 2 of 32

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AD5674/AD5674R Specifications .............................................. 3

AD5679/AD5679R Specifications .............................................. 5

AC Characteristics ........................................................................ 7

Timing Characteristics ................................................................ 7

Daisy-Chain and Readback Timing Characteristics................ 8

Absolute Maximum Ratings .......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 12

Terminology .................................................................................... 21

Theory of Operation ...................................................................... 23

DAC .............................................................................................. 23

Transfer Function ....................................................................... 23

DAC Architecture ....................................................................... 23

Serial Interface ............................................................................ 23

Standalone Operation ................................................................ 25

Write and Update Commands .................................................. 25

Daisy-Chain Operation ............................................................. 25

Readback Operation .................................................................. 25

Power-Down Operation ............................................................ 26

Load DAC (Hardware LDAC Pin) ........................................... 27

LDAC Mask Register ................................................................. 27

Hardware Reset (RESET) .......................................................... 28

Power-On Reset Internal Circuit.............................................. 28

Software Reset ............................................................................. 28

Internal Reference Setup ........................................................... 28

Solder Heat Reflow ..................................................................... 28

Long-Term Temperature Drift ................................................. 29

Thermal Hysteresis .................................................................... 29

Applications Information .............................................................. 30

Power Supply Recommendations ............................................. 30

Microprocessor Interfacing ....................................................... 30

AD5674/AD5674R/AD5679/AD5679R to ADSP-BF531

Interface ....................................................................................... 30

AD5674/AD5674R/AD5679/AD5679R to SPORT Interface 30

Layout Guidelines....................................................................... 30

Galvanically Isolated Interface ................................................. 31

Outline Dimensions ....................................................................... 32

Ordering Guide .......................................................................... 32

REVISION HISTORY

12/2019—Rev. A to Rev. B

Changes to General Description .................................................... 1

Table 2 and Endnote 1 ...................................................................... 4

Changes to Table 3 ............................................................................ 5

Changes to Table 9 .......................................................................... 11

Changes to Figure 9 ........................................................................ 12

Changes to Figure 13 to Figure 18 ................................................ 13

Changes to Figure 19 to Figure 24 ................................................ 14

Changes to Figure 25 to Figure 30 ................................................ 15

Changes to Figure 31 and Figure 32............................................. 16

Changes to Hardware Reset (RESET) Section and Figure 52 and

Figure 53, Moved Table 19............................................................. 19

Added Figure 60 and Changes to Internal Reference Section .. 24

Instantaneous DAC Updating (LDAC Held Low) and Deferred

DAC Updating (LDAC is Pulsed Low) Sections ........................ 28

Hardware Reset (RESET) Section ................................................ 29

Changes to Ordering Guide .......................................................... 32

11/2019—Rev. 0 to Rev. A

Added AD5674, AD5674R, and AD5679................... Throughout

Changes to Functional Block Diagram, Table 1, General

Description Section, and Product Highlights Section ................. 1

Changes to Table 2 ............................................................................. 4

Added AD5679/AD5679R Specifications Section and Table 2;

Renumbered Sequentially ................................................................ 6

Changes to Thermal Resistance Section ..................................... 11

Changes to Figure 7 to Figure 12.................................................. 12

Changes to Figure 13 to Figure 18 ............................................... 13

Changes to Figure 19 to Figure 24 ............................................... 14

Changes to Figure 25 to Figure 30 ............................................... 15

Changes to Figure 31 to Figure 36 ............................................... 16

Changes to Figure 37 to Figure 42 ............................................... 17

Changes to Figure 60...................................................................... 25

Added Long-Term Temperature Drift Section and Figure 64;

Renumbered Sequentially ............................................................. 28

Changes to Figure 67 and Figure 68 ............................................ 30

Changes to Ordering Guide .......................................................... 32

8/2019—Revision 0: Initial Version

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 3 of 32

SPECIFICATIONS

AD5674/AD5674R SPECIFICATIONS

VDD pin voltage (VDD) = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC pin voltage (VLOGIC) ≤ 5.5 V, load resistance (RL) = 2 kΩ, load capacitance

(CL) = 200 pF, all specifications are TJ = −40°C to +125°C, typical at TA = 25°C, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE1

Resolution 12 Bits

INL ±0.12 ±1 LSB Gain = 1

±0.12 ±1 LSB Gain = 2

Differential Nonlinearity (DNL) ±0.05 ±0.1 LSB Gain = 1

±0.05 ±0.1 LSB Gain = 2

Zero Code Error 0.8 1.6 mV Gain = 1 or gain = 2

Offset Error −0.75 ±2 mV Gain = 1

−0.1 ±1.5 mV Gain = 2

Full-Scale Error −0.018 ±0.14 % of FSR Gain = 1

−0.013 ±0.07 % of FSR Gain = 2, VDD = 5.5 V

Gain Error +0.04 ±0.12 % of FSR Gain = 1

−0.02 ±0.06 % of FSR Gain = 2

Total Unadjusted Error (TUE) ±0.03 ±0.18 % of FSR Gain = 1

±0.006 ±0.14 % of FSR Gain = 2

Offset Error Drift ±2 µV/°C Gain = 1

DC Power Supply Rejection Ratio

(PSRR)

0.25 mV/V DAC code = midscale, VDD = 5 V ± 10%

DC Crosstalk ±2 µV Due to single channel, full-scale output change, internal

reference, gain = 1

±3 µV/mA Due to load current change, external reference, gain = 2

±2 µV

Due to powering down (per channel), internal reference,

gain = 1

OUTPUT CHARACTERISTICS

Output Power-Up Voltage 0 V Gain = 1, AD5674-1, AD5674R-1

0 V Gain = 2, AD5674-1, AD5674R-1

1.25 V Gain = 1, AD5674R-2

2.5 V Gain = 2, AD5674R-2

Output Voltage Range 0 2.5 V Gain = 1

Gain = 2

Capacitive Load Stability 2 nF RL = ∞

10 nF RL = 1 kΩ

Load Regulation 183 µV/mA VDD = 5 V ± 10%, DAC code = midscale, −30 mA ≤ output

current (IOUT) ≤ +30 mA

177 µV/mA VDD = 3 V ± 10%, DAC code = midscale, −20 mA ≤ IOUT ≤

+20 mA

Short-Circuit Current2 40 mA

Load Impedance at Rails3 25 Ω

Power-Up Time4 3 µs Exiting power-down mode, VDD = 5 V

REFERENCE INPUT

Reference Input Current 0.8 mA Reference voltage (VREF) = VDD = VLOGIC = 5.5 V, gain = 1

1.6 mA VREF = VDD = VLOGIC = 5.5 V, gain = 2

Reference Input Range 1 VDD V Gain = 1

1 VDD/2 V Gain = 2

Reference Input Impedance 7 kΩ Gain = 1

3.5 kΩ Gain = 2

REFERENCE OUTPUT

AD5674R-1; AD5674R-2

Output Voltage5 2.4975 2.5025 V

Voltage Reference Temperature

Coefficient (TC)6, 7

2 5 ppm/°C See the Terminology section

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 4 of 32

Parameter Min Typ Max Unit Test Conditions/Comments

Output Impedance 0.04 Ω

Output Voltage Noise 13 µV p-p 0.1 Hz to 10 Hz

Output Voltage Noise Density 240 nV/√Hz At ambient temperature (TA), f = 10 kHz, CL = 10 nF, gain =

1 or 2

Load Regulation Sourcing 29 µV/mA At ambient temperature

Load Regulation Sinking 74 µV/mA At ambient temperature

Output Current Load Capability

±20

≥ 3 V

Line Regulation 43 µV/V At ambient temperature

Long-Term Stability Drift 77 ppm After 1000 hours at 25°C

Thermal Hysteresis 125 ppm First cycle

25 ppm Additional cycles

LOGIC INPUTS

Input Current ±1 µA Per pin

Input Voltage (VIN)

Low (VINL) 0.3 ×

VLOGIC

High (VINH) 0.7 × VLOGIC V

Pin Capacitance 4 pF

LOGIC OUTPUTS (SDO)

Output Voltage (VOUT)

Low (VOL) 0.4 V Sink current (ISINK) = 200 μA

High (VOH) VLOGIC − 0.4 V Source current (ISOURCE) = 200 μA

Floating State Output Capacitance 9 pF

POWER REQUIREMENTS

VLOGIC 1.62 5.5 V

ILOGIC 1 µA Power-on, −40°C to +105°C

1.3 µA Power-on, −40°C to +125°C

0.5 µA Power-down, −40°C to +105°C

1.3

µA

Power-down, −40°C to +125°C

VDD 2.7 5.5 V Gain = 1

VREF + 1.5 5.5 V Gain = 2

Supply Current (IDD) VINH = VDD, VINL = GND, VDD = 2.7 V to 5.5 V

Normal Mode8 2.3 2.53 mA Internal reference off, −40°C to +85°C

3.4 3.8 mA Internal reference on, −40°C to +85°C

2.3 2.6 mA Internal reference off

3.4 4.2 mA Internal reference on

All Power-Down Modes9 2 3.4 µA Power-down to 1 kΩ, −40°C to +85°C

2 5 µA Power-down to 1 kΩ, −40°C to +105°C

2 11 µA Power-down to 1 kΩ, −40°C to +125°C

1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1, or when VREF/2 =

VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 4080.

2 VDD = 5 V. The device includes current limiting intended to protect the devices during temporary overload conditions. Junction temperature (TJ) can be exceeded

during current limit. Operation above the specified maximum operation junction temperature can impair device reliability.

3 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output

devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.

4 Time to exit power-down to normal mode of operation, SYNC rising edge to 90% of DAC midscale value, with output unloaded.

5 Initial accuracy presolder reflow is ±750 µV. Output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.

6 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +125°C.

7 Voltage reference temperature coefficient is calculated as per the box method. See the Terminology section for further information.

8 Interface inactive. All DACs active. DAC outputs unloaded.

9 All DACs powered down.

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 5 of 32

AD5679/AD5679R SPECIFICATIONS

VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ, CL = 200 pF, all specifications are TJ = −40°C to +125°C, typical at TA = 25°C,

unless otherwise noted.

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE1

Resolution 16 Bits

INL ±1.8 ±4 LSB Gain = 1

±1.7 ±4 LSB Gain = 2

DNL ±0.7 ±1 LSB Gain = 1

±0.5 ±1 LSB Gain = 2

Zero Code Error

0.8

1.6

Gain = 1 or gain = 2

Offset Error −0.75 ±2 mV Gain = 1

−0.1 ±1.5 mV Gain = 2

Full-Scale Error −0.018 ±0.14 % of

FSR

Gain = 1

−0.013 ±0.07 % of

FSR

Gain = 2, VDD = 5.5 V

Gain Error +0.04 ±0.12 % of

FSR

Gain = 1

−0.02 ±0.06 % of

FSR

Gain = 2

TUE ±0.03 ±0.18 % of

FSR

Gain = 1

±0.006 ±0.14 % of

FSR

Gain = 2

Offset Error Drift ±2 µV/°C Gain = 1

DC PSRR 0.25 mV/V DAC code = midscale, VDD = 5 V ± 10%

DC Crosstalk ±2 µV Due to single channel, full-scale output change, internal

reference, gain = 1

±3 µV/mA Due to load current change, external reference, gain = 2

±2 µV Due to powering down (per channel), internal reference,

gain = 1

OUTPUT CHARACTERISTICS

Output Power-Up Voltage 0 V Gain = 1, AD5679-1, AD5679R-1

0 V Gain = 2, AD5679-1, AD5679R-1

1.25 V Gain = 1, AD5679R-2

2.5 V Gain = 2, AD5679R-2

Output Voltage Range 0 2.5 V Gain = 1

0 5 V Gain = 2

Capacitive Load Stability 2 nF RL = ∞

10 nF RL = 1 kΩ

Load Regulation 183 µV/mA VDD = 5 V ± 10%, DAC code = midscale, −30 mA ≤ IOUT ≤

+30 mA

177 µV/mA VDD = 3 V ± 10%, DAC code = midscale, −20 mA ≤ IOUT ≤

+20 mA

Short-Circuit Current

Load Impedance at Rails3 25 Ω

Power-Up Time4 3 µs Exiting power-down mode, VDD = 5 V

REFERENCE INPUT

Reference Input Current 0.8 mA VREF = VDD = VLOGIC = 5.5 V, gain = 1

1.6 mA VREF = VDD = VLOGIC = 5.5 V, gain = 2

Reference Input Range 1 VDD V Gain = 1

1 VDD/2 V Gain = 2

Reference Input Impedance 7 kΩ Gain = 1

3.5 kΩ Gain = 2

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 6 of 32

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE OUTPUT AD5679R-1; AD5679R-2

Output Voltage5 2.4975 2.5025 V

Voltage Reference TC6, 7 2 5 ppm/°C See the Terminology section

Output Impedance 0.04 Ω

Output Voltage Noise 13 µV p-p 0.1 Hz to 10 Hz

Output Voltage Noise Density 240 nV/√Hz At TA, f = 10 kHz, CL = 10 nF, gain = 1 or 2

Load Regulation Sourcing 29 µV/mA At ambient temperature

Load Regulation Sinking 74 µV/mA At ambient temperature

Output Current Load Capability ±20 mA VDD ≥ 3 V

Line Regulation 43 µV/V At ambient temperature

Long-Term Stability Drift 77 ppm After 1000 hours at 25°C

Thermal Hysteresis 125 ppm First cycle

25 ppm Additional cycles

LOGIC INPUTS

Input Current ±1 µA Per pin

VIN

VINL 0.3 × VLOGIC V

VINH 0.7 ×

VLOGIC

Pin Capacitance 4 pF

LOGIC OUTPUTS (SDO)

VOUT

VOL 0.4 V ISINK = 200 μA

VOH VLOGIC −

0.4

V ISOURCE = 200 μA

Floating State Output Capacitance 9 pF

POWER REQUIREMENTS

VLOGIC 1.62 5.5 V

LOGIC

µA

Power-on, −40°C to +105°C

1.3 µA Power-on, −40°C to +125°C

0.5 µA Power-down, −40°C to +105°C

1.3 µA Power-down, −40°C to +125°C

VDD 2.7 5.5 V Gain = 1

VREF + 1.5 5.5 V Gain = 2

IDD VINH = VDD, VINL = GND, VDD = 2.7 V to 5.5 V

Normal Mode8 2.3 2.53 mA Internal reference off, −40°C to +85°C

3.4 3.8 mA Internal reference on, −40°C to +85°C

2.3 2.6 mA Internal reference off

3.4 4.2 mA Internal reference on

All Power-Down Modes9 2 3.4 µA Power-down to 1 kΩ, −40°C to +85°C

2 5 µA Power-down to 1 kΩ, −40°C to +105°C

2 11 µA Power-down to 1 kΩ, −40°C to +125°C

1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1, or when VREF/2 =

VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280.

2 VDD = 5 V. The device includes current limiting intended to protect the devices during temporary overload conditions. TJ can be exceeded during current limit.

Operation above the specified maximum operation junction temperature can impair device reliability.

3 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output

devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.

4 Time to exit power-down to normal mode of operation, SYNC rising edge to 90% of DAC midscale value, with output unloaded.

5 Initial accuracy presolder reflow is ±750 µV. Output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.

6 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +125°C.

7 Voltage reference temperature coefficient is calculated as per the box method. See the Terminology section for further information.

8 Interface inactive. All DACs active. DAC outputs unloaded.

9 All DACs powered down.

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 7 of 32

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications are TJ = −40°C to +125°C, typical

at TA = 25°C, unless otherwise noted.

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

OUTPUT VOLTAGE SETTLING TIME1 6 8 µs ¼ to ¾ scale settling to ±2 LSB

SLEW RATE 0.8 V/µs

DIGITAL-TO-ANALOG GLITCH IMPULSE1 1.4 nV-sec 1 LSB change around major carry (internal reference, gain = 1)

DIGITAL FEEDTHROUGH1 0.13 nV-sec

CROSSTALK1

Digital 0.1 nV-sec

Analog −0.25 nV-sec

−1.3 nV-sec Internal reference, gain = 2

DAC-to-DAC −2.0 nV-sec Internal reference, gain = 2

TOTAL HARMONIC DISTORTION2 −80 dB At TA, bandwidth = 20 kHz, VDD = 5 V, output frequency (fOUT) = 1 kHz,

internal reference, gain = 2

OUTPUT NOISE SPECTRAL DENSITY1 300 nV/√Hz DAC code = midscale, 10 kHz, gain = 2

OUTPUT NOISE1 6 µV p-p 0.1 Hz to 10 Hz, gain = 1

SIGNAL-TO-NOISE RATIO (SNR) 90 dB At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz, internal

reference

SPURIOUS-FREE DYNAMIC RANGE

(SFDR)

83 dB At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz, internal

reference

SIGNAL-TO-NOISE-AND-DISTORTION

RATIO (SINAD)

80 dB

At T

= 25°C, bandwidth = 20 kHz, V

= 5 V, f

OUT

= 1 kHz, internal

reference, gain = 2

1 See the Terminology section. Measured using internal reference and gain = 1, unless otherwise noted.

2 Digitally generated sine wave (fOUT) at 1 kHz.

TIMING CHARACTERISTICS

All input signals are specified with rise time (tR) = fall time (tF) = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VINL +

VINH)/2. See Figure 2. VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V. VREF = 2.5 V. All specifications are TJ = −40°C to +125°C, unless

otherwise noted.

Table 5.

1.62 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V

Parameter Symbol Min Max Min Max Unit

SCLK Cycle Time t1 20 20 ns

SCLK High Time t2 8 8 ns

SCLK Low Time t3 10 12 ns

SYNC to SCLK Falling Edge Setup Time t4 15 11 ns

Data Setup Time t5 2 3 ns

Data Hold Time t6 2 2 ns

SCLK Falling Edge to SYNC Rising Edge t7 4 4 ns

Minimum SYNC High Time t8 15 12 ns

SYNC Rising Edge to SYNC Rising Edge (DAC Register Updates) t9 870 830 ns

SYNC Falling Edge to SCLK Fall Ignore t10 4 4 ns

LDAC Pulse Width Low t11 12 12 ns

SYNC Rising Edge to LDAC Rising Edge t12 27 27 ns

SYNC Rising Edge to LDAC Falling Edge t13 25 25 ns

LDAC Falling Edge to SYNC Rising Edge t14 840 840 ns

Minimum Pulse Width Low t15 8 10 ns

Pulse Activation Time t16 115 115 ns

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 8 of 32

Figure 2. Serial Write Operation

DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VINL + VINH)/2. See Figure 4 and

Figure 5. VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V. VREF = 2.5 V. All specifications are TJ = −40°C to +125°C, unless otherwise noted.

VDD = 2.7 V to 5.5 V.

Table 6.

1.62 V ≤ V

LOGIC

< 2.7 V

2.7 V ≤ V

LOGIC

≤ 5.5 V

Parameter Symbol Min Max Min Max Unit

SCLK Cycle Time t1 130 110 ns

SCLK High Time t2 33 23 ns

SCLK Low Time t3 12 7 ns

SYNC to SCLK Falling Edge t4 80 80 ns

Data Setup Time

Data Hold Time t6 2 2 ns

SCLK Falling Edge to SYNC Rising Edge t7 35 10 ns

Minimum SYNC High Time t8 55 32 ns

SDO Data Valid from SCLK Rising Edge t9 130 75 ns

SYNC Rising Edge to SCLK Falling Edge t10 15 8 ns

SYNC Rising Edge to SDO Disable t11 218 210 ns

SCLK

SYNC

SDI

DB23

LDAC1

LDAC2

1ASYNCHRO NOUS LDAC UPDAT E MO DE.

2SYNCHRO NOUS LDAC UPDATE MODE.

RESET

VOUT

DB0

17326-002

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 9 of 32

Circuit and Timing Diagrams

Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications

Figure 4. Daisy Chain Timing Diagram

Figure 5. Readback Timing Diagram

200µA I

(MIN)

SDO C

20pF

17326-003

SDO

SDI

SYNC

SCLK 4824

DB23 DB0 DB23 DB0

DB23

INPUT W ORD F OR DAC NUNDEFINED

INPUT W ORD F OR DAC N + 1INPUT W ORD F OR DAC N

DB0

17326-004

SYNC

SCLK 24

124

DB23 DB0 DB23 DB0

SDI

NO OPERATION CONDITIONINPUT WORD SPECIFIES

DB23 DB0

SDO

SELECTED REGISTER DATA

CLO CKE D OUT

HIGH-Z

17326-005

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 10 of 32

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 7.

Parameter Rating

VDD to GND −0.3 V to +7 V

VLOGIC to GND −0.3 V to +7 V

VOUTX to GND −0.3 V to VDD + 0.3 V

VREF to GND −0.3 V to VDD + 0.3 V

Digital Input Voltage to GND −0.3 V to VLOGIC + 0.3

Operating Junction Temperature

Range

−40°C to +125°C

Storage Temperature Range −65°C to +150°C

Absolute Maximum Junction

Temperature

150°C

Reflow Soldering Peak Temperature,

Pb-Free (J-STD-020)

260°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

θJA is the natural convection junction to ambient thermal resistance

measured in a one cubic foot, sealed enclosure. θJB is the junction

to board thermal resistance. θJC is the junction to case thermal

resistance. ΨJT is the junction to top thermal characterization

parameter. ΨJB is the junction to board thermal characterization

parameter.

Table 8. Thermal Resistance

Package Type1 θJA θJB θJC ΨJT ΨJB Unit

CP-28-8 55.09 24.49 19.14 2.62 23.92 °C/W

1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal test

board with nine thermal vias. See JEDEC JESD51.

ESD CAUTION

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 11 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 6. Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Mnemonic Description

VOUT0

Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.

2 VDD

Power Supply Input. These devices operate from 2.7 V to 5.5 V. Decouple the V

supply with a 10 µF capacitor in parallel with a 0.1

µF capacitor to GND.

3 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data transfers in on

the falling edges of the next 24 clocks.

4 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data transfers at rates

of up to 50 MHz.

5 SDI Serial Data Input. The AD5674/AD5674R/AD5679/AD5679R has a 24-bit input shift register. Data is clocked into the register on

the falling edge of the serial clock input.

6 GAIN Span Set Pin. When this pin is tied to GND, all sixteen DAC outputs have a span from 0 V to VREF. If this pin is tied to VLOGIC, all

sixteen DACs output a span of 0 V to 2 × VREF.

7 VOUT7 Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.

8 VOUT6 Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.

9 VOUT5 Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.

10 VOUT4 Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.

11 VOUT15 Analog Output Voltage from DAC 15. The output amplifier has rail-to-rail operation.

12 VOUT14 Analog Output Voltage from DAC 14. The output amplifier has rail-to-rail operation.

13 VOUT13 Analog Output Voltage from DAC 13. The output amplifier has rail-to-rail operation.

14 VOUT12 Analog Output Voltage from DAC 12. The output amplifier has rail-to-rail operation.

15, 16 GND Ground Reference Point for All Circuitry on the Device.

17 LDAC Load DAC. LDAC operates in two modes: asynchronously and synchronously. Pulsing this pin low updates any or all DAC

registers if the input registers have new data, which simultaneously updates all DAC outputs. This pin can also be tied

permanently low.

18 VLOGIC Digital Power Supply. The voltage on this pin is specified in Table 2 and Table 3 in the Power Requirements section.

19 SDO Serial Data Output. This pin can be used to daisy-chain a number of devices together, or it can be used for readback. The serial

data transfers on the rising edge of SCLK and is valid on the falling edge.

20 RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is

activated, the input register and the DAC register are updated with zero-scale or midscale, depending on the model in use.

21 VREF Reference Output Voltage. When using the internal reference, this is the reference output pin. This pin is the reference output

by default.

22 VOUT11 Analog Output Voltage from DAC 11. The output amplifier has rail-to-rail operation.

23 VOUT10 Analog Output Voltage from DAC 10. The output amplifier has rail-to-rail operation.

24 VOUT9 Analog Output Voltage from DAC 9. The output amplifier has rail-to-rail operation.

25 VOUT8 Analog Output Voltage from DAC 8. The output amplifier has rail-to-rail operation.

26 VOUT3 Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.

27 VOUT2 Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.

28 VOUT1 Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.

EPAD Exposed Pad. The exposed pad must be tied to GND.

1VOUT0 2VDD 3SYNC 4SCLK 5SDI 6GAIN 7VOUT7

17 LDAC

18 VLOGIC

19 SDO

20 RESET

21 VREF

16 GND

15 GND

VOUT6 9

VOUT5 10

VOUT4 11

VOUT15 12

VOUT14 13

VOUT13 14

VOUT12

24 VOUT9

25 VOUT8

26 VOUT3

27 VOUT2

28 VOUT1

23 VOUT10

22 VOUT11

TOP VIEW

(No t t o Scal e)

AD5679R/AD5679/AD5674R/AD5674

NOTES

1. EXPOSED PAD. THE EXPOSED PAD MUST BE

TIED TO GND.

17326-006

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 12 of 32

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7. AD5679/AD5679R INL Error vs. Code

Figure 8. AD5674/AD5674R INL Error vs. Code

Figure 9. AD5679/AD5679R DNL Error vs. Code

Figure 10. AD5674/AD5674R DNL Error vs. Code

Figure 11. AD5679/AD5679R Total Unadjusted Error vs. Code

Figure 12. AD5674/AD5674R Total Unadjusted Error vs. Code

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

010000 20000 30000 40000 50000 60000 70000

INL ERRO R ( LSB)

CODE

17326-007

= 5V

= 25°C

INTERNAL REFE RE NCE = 2.5V

0.20

0.15

0.10

0.05

–0.20

–0.15

–0.10

–0.05

0500 1000 1500 2000 2500 3000 4500 4000

INL ERRO R ( LSB)

CODE

VDD = 5V

TA = 25°C

INTERNAL REFE RE NCE = 2.5V

17326-301

DNL ERROR (LSB)

CODE

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

010000 20000 30000 40000 50000 60000 70000

17326-008

= 5V

= 25°C

INTERNAL REFE RE NCE = 2.5V

0.10

0.08

0.06

0.04

0.02

–0.10

–0.08

–0.06

–0.04

–0.02

0500 1000 1500 2000 2500 3000 4500 4000

DNL E RRO R (LS B)

CODE

VDD = 5V

TA = 25°C

INTERNAL REFE RE NCE = 2.5V

17326-302

TO TAL UNADJUS TED E RROR (% OF FSR)

CODE

–0.02

–0.01

0.01

0.02

0.03

0.04

010000 20000 30000 40000 50000 60000 70000

17326-009

= 5V

= 25°C

INTERNAL REFE RE NCE = 2.5V

0.04

0.03

–0.02

0.02

–0.01

0.01

0500 1000 1500 2000 2500 3000 4500 4000

TOTAL UNADJUSTED E RROR (% OF FSR)

CODE

VDD = 5V

TA = 25°C

INTERNAL REFE RE NCE = 2.5V

17326-303

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 13 of 32

Figure 13. AD5679/AD5679R INL Error vs. Temperature

Figure 14. AD5674/AD5674R INL Error vs. Temperature

Figure 15. AD5679/AD5679R DNL Error vs. Temperature

Figure 16. AD5674/AD5674R DNL Error vs. Temperature

Figure 17. AD5679/AD5679R Total Unadjusted Error vs. Temperature

Figure 18. AD5674/AD5674R Total Unadjusted Error vs. Temperature

17326-010

–40 –20 020 40 60 80 100 120

INL ERROR ( LSB)

TEMPERATURE ( °C)

= 5V

INTERNAL REFE RE NCE = 2.5V

–2

–1

–40 –20 020 40 60 80 100 120

INL ERRO R ( LSB)

TEMPERATURE (°C)

= 5V

INTERNAL REFE RE NCE = 2.5V

17326-304

17326-011

0.5

1.0

1.5

2.0

–40 –20 020 40 60 80 100 120

DNL ERRO R ( LSB)

TEMPERATURE ( °C)

VDD = 5V

INTERNAL REFE RE NCE = 2.5V

–2

–1

–40 –20 020 40 60 80 100 120

DNL E RRO R (LS B)

TEMPERATURE (°C)

= 5V

INTERNAL REFE RE NCE = 2.5V

17326-305

17326-012

0.005

0.010

0.015

0.020

0.025

0.030

–40 –20 020 40 60 80 100 120

TOTAL UNADJUSTE D E RROR (% OF FSR)

TEMPERATURE ( °C)

VDD = 5V

INTERNAL REFE RE NCE = 2.5V

0.030

0.025

0.010

0.020

0.005

0.015

–40 –20 020 40 60 80 100 120

TOTAL UNADJUSTED E RROR (% OF FSR)

TEMPERATURE (°C)

= 5V

INTERNAL REFE RE NCE = 2.5V

17326-306

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 14 of 32

Figure 19. AD5679/AD5679R INL Error vs. Supply Voltage

Figure 20. AD5674/AD5674R INL Error vs. Supply Voltage

Figure 21. AD5679/AD5679R DNL Error vs. Supply Voltage

Figure 22. AD5674/AD5674R DNL Error vs. Supply Voltage

Figure 23. AD5679/AD5679R Total Unadjusted Error vs. Supply Voltage

Figure 24. AD5674/AD5674R Total Unadjusted Error vs. Supply Voltage

17326-016

0.5

1.0

1.5

2.0

2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4

INL ERROR ( LSB)

SUPPLY VOLTAGE (V)

TA = 25°C

INTERNAL REFE RE NCE = 2.5V

0.150

0.125

0.050

0.100

0.025

0.075

2.7 3.0 3.3 3.93.6 4.2 4.5 4.8 5.1 5.4

INL ERRO R ( LSB)

SUPPLY VOLT AGE (V)

= 25°C

INTERNAL REFE RE NCE = 2.5V

17326-307

17326-017

0.25

0.50

0.75

1.00

2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4

DNL ERRO R ( LSB)

SUPPLY VOLTAGE (V)

TA = 25°C

INTERNAL REFE RE NCE = 2.5V

0.10

0.04

0.08

0.02

0.06

2.7 3.0 3.3 3.93.6 4.2 4.5 4.8 5.1 5.4

DNL E RRO R (LS B)

SUPPLY VOLT AGE (V)

= 25°C

INTERNAL REFE RE NCE = 2.5V

17326-308

0.005

0.010

0.015

0.020

0.025

0.030

0.035

0.040

2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4

TOTAL UNADJUSTE D E RROR (% OF FSR)

SUPPLY VOLTAGE (V)

= 25°C

INTERNAL REFE RE NCE = 2.5V

17326-115

0.020

0.015

–0.020

–0.015

–0.010

–0.005

0.010

0.005

2.7 3.0 3.3 3.93.6 4.2 4.5 4.8 5.1 5.4

TOTAL UNADJUSTED E RROR (% OF FSR)

SUPPLY VOLT AGE (V)

= 25°C

INTERNAL REFE RE NCE = 2.5V

17326-309

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 15 of 32

Figure 25. AD5679/AD5679R Gain Error and Full-Scale Error vs.

Temperature

Figure 26. AD5674/AD5674R Gain Error and Full-Scale Error vs.

Temperature

Figure 27. AD5679/AD5679R Gain Error and Full-Scale Error vs. Supply

Voltage

Figure 28. AD5674/AD5674R Gain Error and Full-Scale Error vs. Supply

Voltage

Figure 29. AD5679/AD5679R Zero Code Error and Offset Error vs.

Temperature

Figure 30. AD5674/AD5674R Zero Code Error and Offset Error vs.

Temperature

17326-019

–40 –20 020 40 60 80 100 120

–0.020

–0.015

–0.010

–0.005

0.005

0.010

0.015

0.020

GAI N E RROR AND

FULL- S CALE E RROR (% OF FSR)

TEMPERATURE ( °C)

FULL- S CALE E RROR

GAI N E RROR

= 5V

INTERNAL REFE RE NCE = 2.5V

0.05

–0.05

–0.03

0.03

–0.01

0.01

–40 –20 020 40 60 80 100 120

GAI N E RROR AND

FULL- S CALE E RROR (% OF FSR)

TEMPERATURE (°C)

= 5V

INTERNAL REFE RE NCE = 2.5V

17326-310

FULL- S CALE E RROR

GAI N E RROR

17326-020

–0.03

–0.02

–0.01

0.01

0.02

0.03

2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4

GAI N E RROR AND

FULL- S CALE E RROR (% OF FSR)

SUPPLY VOLTAGE (V)

TA = 25°C

INTERNAL REFE RE NCE = 2.5V

GAI N E RROR

FULL- S CALE E RROR

0.05

–0.05

–0.03

0.03

–0.01

–0.04

–0.02

0.01

0.04

0.02

2.7 3.2 3.7 4.2 4.7 5.2

GAI N E RROR AND

FULL- S CALE E RROR (% OF FSR)

TEMPERATURE (°C)

= 25°C

INTERNAL REFE RE NCE = 2.5V

17326-311

FULL- S CALE E RROR

GAI N E RROR

ZERO CO DE E RROR AND OF FSE T ERRO R ( mV )

TEMPERATURE (°C)

–0.6

–0.3

0.3

0.6

0.9

1.2

1.5

1.8

–40 –20 020 40 60 80 100 120

ZERO CO DE E RROR

OFFSET ERROR

VDD = 5V

INT E RNAL REFERE NCE = 2.5V

17326-021

–0.6

–0.3

0.3

0.6

0.9

1.2

1.5

1.8

–40 –20 020 40 60 80 100 120

ZE RO CODE E RROR AND O FF S E T ERROR (mV )

TEMPERATURE (°C)

VDD = 5V

INTERNAL REFE RE NCE = 2.5V

17326-312

ZE RO -CODE E RROR

OFFSET ERROR

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 16 of 32

Figure 31. AD5679/AD5679R Zero Code Error and Offset Error vs. Supply

Voltage

Figure 32. AD5674/AD5674R Zero Code Error and Offset Error vs. Supply

Voltages

Figure 33. Supply Current (IDD) Histogram with Internal Reference

Figure 34. Headroom and Footroom (ΔVOUT) vs. Load Current

Figure 35. Source and Sink Capability at VDD = 3 V

Figure 36. Source and Sink Capability at VDD = 5 V

ZE RO CODE E RROR AND O FF S E T ERROR (mV )

SUPPLY VOLT AGE (V)

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.7 3.2 3.7 4.2 4.7 5.2

= 25° C

INT E RNAL REFERE NCE = 2.5V

ZERO CO DE E RROR

OFFSET ERROR

17326-022

1.5

–1.5

–1.0

1.0

0.5

–0.5

2.7 3.2 3.7 4.2 4.7 5.2

SUPPLY VOLT AGE (V)

ZE RO CODE E RROR AND O FF S E T ERROR (mV )

= 25°C

INTERNAL REFE RE NCE = 2.5V

17326-313

ZE RO -CODE E RROR

OFFSET ERROR

3330 3350 3370 3390 3410 3430 3450 3470 3490 3510 3530 3550

HITS

FULLS CALE ( µA)

= 5. 5V

GAIN = 2

= 25°C

INTERNAL REFERENCE = 2 .5V

17326-209

SOURCING – V DD = 5V; G = 1

SOURCING – V DD = 2. 7V; G = 1

SOURCING – V DD = 5. 5V; G = 2

SOURCING – V DD = 3. 3V; G = 1

SINKING – VDD = 5V; G = 1

SINKING – VDD = 2. 7V; G = 1

SINKING – VDD = 5. 5V; G = 2

SINKING – VDD = 3. 3V; G = 1

1.4

–1.4

–1.0

–0.6

–0.2

0.2

0.4

1.0

00.005 0.010 0.015 0.020 0.025 0.030

∆V

OUT

(V)

LOAD CURRENT ( A)

17326-314

–1.0

–0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

–0.06 –0.04 –0.02 00.02 0.04 0.06

17326-026

OUTPUT CURRE NT (A)

OUT

(V)

0xFFFF

0xC000

0x8000

0x4000

0x0000

= 3V

= 25° C

GAI N = 1

INTERNAL REFE RE NCE = 2.5V

REQUIRED V

HEADROOM

TO MAINTAIN V

OUT

x = 2.5V

OUT

(V)

OUT P UT CURRENT (A)

–2

–1

–0.06 –0.04 –0.02 00.02 0.04 0.06

17326-025

= 5V

= 25° C

GAI N = 2

INTERNAL REFE RE NCE = 2.5V

0xFFFF

0xC000

0x8000

0x4000

0x0000

REQUIRED V

HEADROOM

TO MAINTAIN V

OUT

x = 5V

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 17 of 32

Figure 37. Source and Sink Capability at VDD = 5.5 V

Figure 38. IDD vs. Code

Figure 39. IDD vs. Temperature

Figure 40. IDD vs. Supply Voltage

Figure 41. IDD vs. Logic Input Voltage

Figure 42. Settling Time

–1

–0.06 –0.04 –0.02 00.02 0.04 0.06

OUTPUT CURRE NT (A)

OUT

(V)

0xFFFF

0xC000

0x8000

0x4000

0x0000

= 5.5V

GAI N = 2

= 25° C

INTERNAL REFE RE NCE = 2.5V

17326-224

2.4

2.6

2.8

3.2

3.4

3.6

010000 20000 30000 40000 50000 60000 70000

IDD ( mA)

CODE

DEVICE 1

DEVICE 2

DEVICE 3

17326-206

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

–40 10 60 110

(mA)

TEMPERATURE ( °C)

INTERNAL REFE RE NCE , F UL L SCALE

INTERNAL REFE RE NCE , Z E RO SCALE

EXTERNAL REFERE NCE , F UL L SCALE

= 5.5V

GAI N = 1

INTERNAL REFE RE NCE = 2.5V

17326-210

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

2.7 3.2 3.7 4.2 4.7 5.2

(mA)

SUPPLY VOLTAGE (V)

GAI N = 1

= 25° C

INTERNAL REFE RE NCE = 2.5V

17326-208

INTERNAL REFE RE NCE , F UL L SCALE

INTERNAL REFE RE NCE , Z E RO SCALE

EXTERNAL REFERE NCE , F UL L SCALE

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

IDD ( mA)

LOGIC INPUT VOLTAGE (V)

INTERNAL REFE RE NCE , F UL L SCALE

INTERNAL REFE RE NCE , Z E RO SCALE

EXTERNAL REFERE NCE , F UL L SCALE

VDD = 5.5V

GAI N = 1

TA = 25° C

INTERNAL REFE RE NCE = 2.5V

17326-211

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

–2 –1 0 1 2 3 4 5

OUT

(V)

TIME (µs)

CH 0

CH 1

CH 2

CH 3

CH 4

CH 5

CH 6

CH 7

CH 8

CH 9

CH 10

CH 11

CH 12

CH 13

CH 14

CH 15

17326-205

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 18 of 32

Figure 43. POR to 0 V Output

Figure 44. Exiting Power-Down to Midscale

Figure 45. Digital-to-Analog Glitch Impulse

Figure 46. Analog Crosstalk

Figure 47. DAC-to-DAC Crosstalk

Figure 48. 0.1 Hz to 10 Hz Output Noise

(V)

TIME (Seconds)

–0.001

0.001

0.002

0.003

0.004

0.005

0.006

–1

00.002 0.004 0.006 0.008 0.010

OUT

(V)

OUT

0 (V)

OUT

1 (V)

OUT

2 (V)

OUT

3 (V)

OUT

4 (V)

OUT

5 (V)

OUT

6 (V)

OUT

7 (V)

17326-033

–2.5

2.5

5.0

7.5

10.0

12.5

15.0

–0.5

0.5

1.0

1.5

2.0

2.5

3.0

–5 0 5 10

SYNC (V)

VOUT (V)

TIME (µs)

MI DS CALE, GAI N = 2

MI DS CALE, GAI N = 1

SYNC

–0.006

–0.004

–0.002

0.002

0.004

0.006

0.008

22.5 22.7 22.9 23.1 23.3 23.5 23.7 23.9 24.1 24.3 24.5

AMPLITUDE (V)

TIME (µs)

VDD = 5V

GAI N = 1

= 25° C

INTERNAL REFE RE NCE

CODE = 7FF F TO 8000

ENERGY = 0. 636nV

WITH LO AD CH0

WITH LO AD CH8

17326-203

–0.006

–0.004

–0.002

0.002

0.004

0.006

0.008

22.5 22.7 22.9 23.1 23.3 23.5 23.7 23.9 24.1 24.3 24.5

AMPLITUDE (V)

TIME (µs)

CH 1

CH 2

CH 3

CH 4

CH 5

CH 6

CH 7

CH 8

CH 9

CH 10

CH 11

CH 12

CH 13

CH 14

CH 15

ATTACK CHANNEL

= 5V

GAI N = 1

= 25° C

INTERNAL REFE RE NCE

CODE = 0000 TO FFFF

17326-201

–0.009

–0.004

0.001

0.006

0.011

21.5 21.7 21.9 22.1 22.3 22.5 22.7 22.9 23.1 23.3 23.5

AMPLITUDE (V)

TIME (µs)

= 5V

GAI N = 1

= 25° C

INTERNAL REFE RE NCE

CODE = 0000 TO FFFF

CH 0

CH 1

CH 2

CH 3

CH 4

CH 5

CH 6

CH 8

CH 9

CH 10

CH 11

CH 12

CH 13

CH 14

CH 15

ATTACK CHANNEL

17326-202

CH1 50.0mV M1.00s A CH1 401mV

17326-134

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 19 of 32

Figure 49. Noise Spectral Density (NSD)

Figure 50. Total Harmonic Distortion (THD) at 1 kHz

Figure 51. Settling Time at Various Capacitive Loads

Figure 52. Hardware Reset

Figure 53. Internal Reference ND vs. Frequency

Figure 54. VREF vs. Temperature

17326-043

200

400

600

800

1000

1200

10 100 1k 10k 100k 1M

NSD (nV/√Hz)

FREQUENCY (Hz)

= 5V

= 25°C

GAIN = 1

INTERNAL REFERENCE = 2.5V

LL SCALE

MIDSCALE

ZERO SCALE

–170

–150

–130

–110

–90

–70

–50

–30

–10

0 5 10 15 20

dB LEVEL (dBV)

FREQUENCY (kHz)

17326-204

TIME (ms)

VOUT (V)

0.13 0.14 0.15

0.16

17326-039

0.5

1.0

1.5

2.0

2.5

= 5V

GAI N = 1

= 25° C

REF

= 2.5V

0nF

0.1nF

1nF

4.7nF

10nF

17326-042

–0.10

–0.05

0.30

0.25

0.20

0.15

0.10

0.05

–2

–1

–10 10 30 50

OUT

AT Z S (V)

OUT

AT MS AND RESET (V)

TIME (µs)

RESET

ZERO SCALE, GAIN = 1

MI DS CALE, GAI N = 1

200

400

600

800

1000

1200

1400

1600

10 100 1k 10k 100k 1M

INTERNAL REFERENCE NSD (nV/√Hz)

FREQUENCY (Hz)

= 5V

= 25° C

17326-140

2.4980

2.4985

2.4990

2.4995

2.5000

2.5005

2.5010

2.5015

2.5020

–40 –20 020 40 60 80 100 120

TEMPERATURE ( °C)

DEVICE1

DEVICE2

DEVICE3

DEVICE4

DEVICE5

VREF (V)

17326-142

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 20 of 32

Figure 55. VREF vs. Load Current Figure 56. VREF vs. VDD

2.4995

2.5000

2.5005

2.5010

2.5015

2.5020

2.5025

2.5030

2.5035

–0.035 –0.025 –0.015 –0.005 0.005 0.015 0.025 0.035

REF

(V)

LOAD CURRENT ( A)

= 5V

= 25° C

17326-143

REF

(V)

2.50010

2.50015

2.50020

2.50025

2.50030

2.50035

2.50040

2.50045

2.50050

2.5 3.0 3.5 4.0 4.5 5.0 5.5

= 25° C

DEVICE1

DEVICE2

DEVICE3

17326-144

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 21 of 32

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy or integral nonlinearity is a

measurement of the maximum deviation, in LSBs, from a straight

line passing through the endpoints of the DAC transfer function.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of ±1 LSB maximum

ensures monotonicity. These DACs are guaranteed monotonic

by design.

Zero Code Error

Zero code error is a measurement of the output error when zero

code (0x0000) is loaded to the DAC register. The ideal output is

0 V. The zero code error is always positive because the output of

the DAC cannot go below 0 V due to a combination of the offset

errors in the DAC and the output amplifier. Zero code error is

expressed in mV.

Full-Scale Error

Full-scale error is a measurement of the output error when full-

scale code (0xFFFF) is loaded to the DAC register. The ideal

output is VDD − 1 LSB. Full-scale error is expressed in percent of

full-scale range (% of FSR).

Gain Error

Gain error is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from the

ideal expressed as % of FSR.

Offset Error Drift

Offset error drift is a measurement of the change in offset error

with a change in temperature. Offset error drift is expressed in

µV/°C.

Offset Error

Offset error is a measure of the difference between VOUT (actual)

and VOUT (ideal) expressed in mV in the linear region of the

transfer function. Offset error is measured with Code 256 loaded

in the DAC register. Offset error can be negative or positive.

DC Power Supply Rejection Ratio (PSRR)

The dc PSRR indicates how the output of the DAC is affected by

changes in the supply voltage. PSRR is the ratio of the change in

VOUT to a change in VDD for full-scale output of the DAC. PSRR

is measured in mV/V. VREF is held at 2 V, and VDD is varied by

±10%.

Output Voltage Settling Time

The output voltage settling time is the amount of time it takes for

the output of a DAC to settle to a specified level for a ¼ to ¾ full-

scale input change and is measured from the rising edge of SYNC.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. Digital-to-analog glitch impulse is normally specified as the

area of the glitch in nV-sec, and is measured when the digital

input code is changed by 1 LSB at the major carry transition

(0x7FFF to 0x8000).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the

analog output of the DAC from the digital inputs of the DAC,

but is measured when the DAC output is not updated. Digital

feedthrough is specified in nV-sec and measured with a full-

scale code change on the data bus, that is, from all 0s to all 1s

and vice versa.

Reference Feedthrough

Reference feedthrough is the ratio of the amplitude of the signal

at the DAC output to the reference input when the DAC output

is not being updated. Reference feedthrough is expressed in dB.

Noise Spectral Density

Noise spectral density is a measurement of the internally generated

random noise. Random noise is characterized as a spectral density

(nV/√Hz). Noise spectral density is measured by loading the DAC

to midscale and measuring noise at the output. Noise spectral

density is measured in nV/√Hz.

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in

response to a change in the output of another DAC. DC crosstalk

is measured with a full-scale output change on one DAC (or soft

power-down and power-up) when monitoring another DAC

kept at midscale. DC crosstalk is expressed in μV.

DC crosstalk due to load current change is a measure of the impact

that a change in load current on one DAC has on another DAC

kept at midscale. DC crosstalk due to load current change is

expressed in μV/mA.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output

of one DAC at midscale in response to a full-scale code change

(all 0s to all 1s and vice versa) in the input register of another

DAC. Digital crosstalk is measured in standalone mode and is

expressed in nV-sec.

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output

of one DAC due to a change in the output of another DAC.

Analog crosstalk is measured by first loading one of the input

registers with a full-scale code change (all 0s to all 1s and vice

versa). Then, execute a software LDAC and monitor the output

of the DAC whose digital code was not changed. The area of the

glitch is expressed in nV-sec.

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 22 of 32

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the

output of one DAC due to a digital code change and subsequent

analog output change of another DAC. DAC-to-DAC crosstalk

is measured by loading the attack channel with a full-scale code

change (all 0s to all 1s and vice versa), using the write to and

update commands when monitoring the output of the victim

channel that is at midscale. The energy of the glitch is expressed

in nV-sec.

Multiplying Bandwidth

The multiplying bandwidth is a measure of the finite bandwidth

of the amplifiers within the DAC. A sine wave on the reference

(with full-scale code loaded to the DAC) appears on the output.

The multiplying bandwidth is the frequency at which the output

amplitude falls to 3 dB below the input.

Total Harmonic Distortion (THD)

THD is the difference between an ideal sine wave and its

attenuated version using the DAC. The sine wave is used as the

reference for the DAC, and the THD is a measurement of the

harmonics present on the DAC output. THD is measured in dB.

Voltage Reference TC

Voltage reference TC is a measure of the change in the reference

output voltage with a change in temperature. The voltage

reference TC is calculated using the box method, which defines

the TC as the maximum change in the reference output over a

given temperature range, expressed in ppm/°C, shown in the

following equation:

( ) () 6

()

REF MAX REF MIN

REF NOM

TC V Temperature Range



−

= ×





where:

VREF (MAX) is the maximum reference output measured over the

total temperature range.

VREF (MIN) is the minimum reference output measured over the

total temperature range.

VREF (NOM) is the nominal reference output voltage, 2.5 V.

Temperature Range is the specified temperature range of −40°C

to +125°C.

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 23 of 32

THEORY OF OPERATION

DAC

The AD5674/AD5674R/AD5679/AD5679R are 16-channel,

12-/16-bit, serial input, voltage output DAC with an internal

reference. The device operates from supply voltages of 2.7 V to

5.5 V. Data is written to the AD5674/AD5674R/AD5679/

AD5679R in a 24-bit word format via a 3-wire serial interface.

The AD5674/AD5674R/AD5679/AD5679R incorporate a POR

circuit to ensure that the DAC output powers up to a known

output state. The device also has a software power-down mode

that reduces the typical current consumption to 2 µA.

TRANSFER FUNCTION

The internal reference is on by default.

The gain of the output amplifier can be set to ×1 or ×2 using the

span set pin (GAIN). When the GAIN pin is tied to GND, all

16 DAC outputs have a span from 0 V to VREF. When the GAIN

pin is tied to VLOGIC, all 16 DACs output a span of 0 V to

2 × VREF.

DAC ARCHITECTURE

The AD5674/AD5674R/AD5679/AD5679R implement a

segmented string DAC architecture with an internal output

buffer. Figure 57 shows the internal block diagram.

Figure 57. Single DAC Channel Architecture Block Diagram

Figure 58. Resistor String Structure

Figure 58 shows the resistor string structure. The code loaded to

the DAC register determines the node on the string where the

voltage is tapped off and fed into the output amplifier. The voltage

is tapped off by closing one of the switches and connecting the

string to the amplifier. Because each resistance in the string has

the same value, R, the string DAC is guaranteed monotonic.

Internal Reference

The AD5674R/AD5679R on-chip reference is enabled at power-

up, but can be disabled via a write to the control register. See the

Internal Reference Setup section for details.

The AD5674R/AD5679R have a 2.5 V, 2 ppm/°C reference,

resulting in a full-scale output of 2.5 V or 5 V, depending on the

state of the GAIN pin. The internal reference associated with

the device is available at the VREF pin. This buffered reference

is capable of driving external loads of up to 15 mA.

Output Amplifiers

The output buffer amplifier generates rail-to-rail voltages on its

output. The actual range depends on the value of VREF, the gain

setting, the offset error, and the gain error.

The output amplifiers can drive a load of 1 kΩ in parallel with

10 nF to GND. The slew rate is 0.8 V/µs, with a typical ¼ to ¾

scale settling time of 6 µs.

SERIAL INTERFACE

The AD5674/AD5674R/AD5679/AD5679R use a 3-wire serial

interface (SYNC, SCLK, and SDI, compatible with SPI, QSPI™,

and MICROWIRE interface standards, as well as most digital

signal processors (DSPs). See Figure 2 for a timing diagram of a

typical write sequence. The

AD5674/AD5674R/AD5679/AD5679R contain an SDO pin to

allow the user to daisy-chain multiple devices together (see the

Daisy-Chain Operation section) or for readback.

Input Shift Register

The input shift register of the

AD5674/AD5674R/AD5679/AD5679R is 24 bits wide. Data is

loaded MSB first (DB23), and the first four bits are the command

bits, C3 to C0 (see Table 10, followed by the 4-bit DAC address

bits, A3 to A0 (see Table 11), and finally, the 16-bit data-word.

The data-word is comprised of a 16-bit input code for the AD5679

and AD5679R, and a 12-bit code followed by four zeroes, or

don’t care bits, for the AD5674 and AD5674R models (see

Figure 60 and Figure 59). These data bits are transferred to the

input register on the 24 falling edges of SCLK and are updated

on the rising edge of SYNC.

Commands execute on individual DAC channels, combined DAC

channels, or on all DACs, depending on the DAC address bits

selected.

INPUT

2.5V

REF

DAC

STRING

REF (+)

REF ( –)

REF

VOUTx

GND

GAIN

(GAIN = 1 OR 2)

17326-057

RTO OUTPUT

AMPLIFIER

REF

17326-058

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 24 of 32

Table 10. Command Definitions

Command

C3 C2 C1 C0 Description

0 0 0 0 No operation

0 0 0 1 Write to Input Register n where n = 1 to 8, depending on the DAC selected from the

address bits in Table 11 (dependent on LDAC)

0 0 1 0 Update DAC Register n with contents of Input Register n

0 0 1 1 Write to and update DAC Channel n

0 1 0 0 Power down/power up the DAC

0 1 0 1 Hardware LDAC mask register

0 1 1 0 Software reset (power-on reset)

0 1 1 1 Internal reference setup register

1 0 0 0 Set up the daisy-chain enable (DCEN) register

Set up the readback register (readback enable)

1 0 1 0 Update all channels of the input register simultaneously with the input data

1 0 1 1 Update all channels of the DAC register and input register simultaneously with the input

data

1 1 0 0 Reserved

… … … …

1 1 1 1 No operation, daisy-chain mode

Table 11. Address Commands

Channel Address[3:0]

Selected Channel A3 A2 A1 A0

0 0 0 0 DAC 0

0 0 0 1 DAC 1

0 0 1 0 DAC 2

0 0 1 1 DAC 3

0 1 0 0 DAC 4

0 1 0 1 DAC 5

0 1 1 0 DAC 6

0 1 1 1 DAC 7

1 0 0 0 DAC 8

1 0 0 1 DAC 9

DAC 10

1 0 1 1 DAC 11

1 1 0 0 DAC 12

1 1 0 1 DAC 13

1 1 1 0 DAC 14

1 1 1 1 DAC 15

Figure 59. AD5679/AD5679R Input Shift Register Content

Figure 60. AD5674/AD5674R Input Shift Register Content

DB23 (MS B) DB0 (L S B)

C3 C2 C1 C0 D11 D10 D9 D8D15 D14 D13 D12 D7 D6 D5 D4 D3 D2 D1 D0

COM M AND BITS ADDRESS BIT S

DATA BI TS

A3 A2 A1 A0

17326-060

DB23 (MS B)

C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

COM M AND BITS ADDRE S S BIT S

DATA BITS

DB0 (L S B)

17326-059

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 25 of 32

STANDALONE OPERATION

Bring the SYNC line low to begin the write sequence. Data from

the SDI line is clocked into the 24-bit input shift register on the

falling edge of SCLK. After the last of 24 data bits is clocked in,

bring SYNC high. The programmed function is then executed,

that is, an LDAC dependent change in DAC register contents

and/or a change in the mode of operation. If SYNC is brought

high at a clock before the 24th clock, it is considered a valid

frame, and invalid data is loaded to the DAC. Bring SYNC high

for a minimum of 20 ns (single channel, see t8 in Figure 2)

before the next write sequence so that a falling edge of SYNC

can initiate the next write sequence. Idle SYNC at rails between

write sequences for even lower power operation. The SYNC line

is kept low for 24 falling edges of SCLK, and the DAC is

updated on the rising edge of SYNC.

When data is transferred to the input register of the addressed

DAC, all DAC registers and outputs update by bringing LDAC

low while the SYNC line is high.

WRITE AND UPDATE COMMANDS

Write to Input Register n (Dependent on LDAC)

Command 0001 allows the user to write the dedicated input

Update DAC Register n with Contents of Input Register n

Command 0010 loads the DAC registers and outputs with the

contents of the input registers selected and updates the DAC

outputs directly. Data Bit D15 to Bit D0 determine which DACs

have data from the input register transferred to the DAC register.

Setting a bit to 1 transfers data from the input register to the

appropriate DAC register.

Write to and Update DAC Channel n (Independent of LDAC)

Command 0011 allows the user to write to the DAC registers

and updates the DAC outputs directly. The address bits are used

to select the DAC channel.

DAISY-CHAIN OPERATION

For systems that contain several DACs, the SDO pin can daisy-

chain several devices together and is enabled through a software

executable DCEN command. Command 1000 is reserved for

this DCEN function (see Table 10). The daisy-chain mode is

enabled by setting Bit DB0 in the DCEN register. The default

setting is standalone mode, where DB0 = 0. Table 12 shows how

the state of the bit corresponds to the mode of operation of the

device.

Table 12. DCEN Register

DB0 Description

0 Standalone mode (default)

1 DCEN mode

Figure 61. Daisy-Chaining the AD5674/AD5674R/AD5679/AD5679R to a

Motorola® 68HC11

The SCLK pin is continuously applied to the input shift register

when SYNC is low. If more than 24 clock pulses are applied, the

data ripples out of the input shift register and appears on the SDO

line. This data is clocked out on the rising edge of SCLK and is

valid on the falling edge. By connecting this line to the SDI

input on the next DAC in the chain, a daisy-chain interface is

constructed. Each DAC in the system requires 24 clock pulses.

Therefore, the total number of clock cycles must equal 24 × N,

where N is the total number of devices updated. If SYNC is

brought high at a clock that is not a multiple of 24, it is considered

a valid frame, and invalid data may be loaded to the DAC. When

the serial transfer to all devices is complete, SYNC goes high,

which latches the input data in each device in the daisy-chain

and prevents any further data from being clocked into the input

shift register. The serial clock can be continuous or a gated clock.

If SYNC is held low for the correct number of clock cycles, a

continuous SCLK source is used. In gated clock mode, use a

burst clock containing the exact number of clock cycles, and

bring SYNC high after the final clock to latch the data.

READBACK OPERATION

Readback mode is invoked through a software executable readback

command. If the SDO output is disabled via the daisy-chain mode

disable bit in the control register, the SDO output is automatically

MOSI

68HC11

AD5679R/

AD5679/

AD5674R/

AD5674

AD5679R/

AD5679/

AD5674R/

AD5674

AD5679R/

AD5679/

AD5674R/

AD5674

MISO SDO

SDI

SCK

PC7

PC6

SDI

SCLK

SYNC

LDAC

SDO

SCLK

SYNC

LDAC

SDO

SCLK

SYNC

LDAC

SDO

SCLK

SYNC

LDAC

17326-061

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 26 of 32

enabled for the duration of the read operation, after which the

SDO output is disabled again. Command 1001 is reserved for the

readback function. This command, in association with the

address bits (A3 to A0), selects the DAC input register to read

(see Table 10 and Table 11). During readback, only one input

sequence are don’t care bits. During the next SPI write, the data

appearing on the SDO output contains the data from the

previously addressed register.

For example, to read back the DAC register for Channel 0,

implement the following sequence:

1. Write 0x900000 to the AD5674/AD5674R/AD5679/

AD5679R input register. This configures the device for

read mode with the DAC register of Channel 0 selected.

Note that all data bits, DB15 to DB0, are don’t care bits.

2. Follow Step 1 with a second write, a no operation (NOP)

condition, 0x000000 or 0xF00000 when in daisy-chain

mode. During this write, the data from the register is

clocked out on the SDO line. DB23 to DB20 contain

undefined data, and the last 20 bits contain the DB19 to

DB0 DAC register contents.

When SYNC is high, the SDO pin is driven by a weak latch that

holds the last data bit. The SDO pin can be overdriven by the

SDO pin of another device. Multiple devices can be read using

the same SPI interface.

POWER-DOWN OPERATION

Command 0100 is designated for the power-down function (see

Table 10). These power-down modes are software programmable

by setting 16 bits, Bit DB15 to Bit DB0, in the input shift register.

There are two bits associated with each DAC channel. Table 13

shows how the state of the two bits corresponds to the mode of

operation of the device.

Any or all DACs (DAC 0 to DAC 15) power down to the

selected mode by setting the corresponding bits. See Table 14

and Table 15 for the contents of the input shift register during

the power-down/power-up operation.

Table 13. Modes of Operation

Operating Mode PD1 PD0

Normal Operation 0 0

Power-Down Modes

1 kΩ to GND 0 1

When both Bit PD1 and Bit PD0 in the input shift register are set

to 0, the device works normally with a typical power consumption

of 2.3 mA at 5 V. However, for the 1 kΩ power-down mode, the

supply current typically falls to 2 µA. In addition to this fall, the

output stage switches internally from the amplifier output to a

resistor network of a known value. Therefore, the DAC channel

output impedance is defined when the channel is powered down

by internally connecting the output to GND through a 1 kΩ

resistor. Figure 62 shows the output stage.

Figure 62. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other

associated linear circuitry shut down when power-down mode is

activated. However, the contents of the DAC register are unaffected

when in power-down. The DAC register updates while the device

is in power-down mode. The time required to exit power-down is

typically 3 µs for VDD = 5 V.

To reduce the current consumption further, power off the on-chip

reference. See the Internal Reference Setup section.

Table 14. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation for Output Channels DAC 7 to DAC 0

[DB23:DB20] DB19 [DB18:DB16]

DAC 7 DAC 6 DAC 5 DAC 4 DAC 3 DAC 2 DAC 1 DAC 0

[DB15:DB14] [DB13:DB12] [DB11:DB10] [DB9:DB8] [DB7:DB6] [DB5:DB4] [DB3:DB2] [DB1:DB0]

0100 0 XXX1 [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0]

Table 15. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation for Output Channels DAC 15 to DAC 8

[DB23:DB20] DB19 [DB18:DB16]

DAC 15 DAC 14 DAC 13 DAC 12 DAC 11 DAC 10 DAC 9 DAC 8

[DB15:DB14] [DB13:DB12] [DB11:DB10] [DB9:DB8] [DB7:DB6] [DB5:DB4] [DB3:DB2] [DB1:DB0]

0100 1 XXX1 [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0] [PD1:PD0]

1 X means don’t care.

RESISTOR

NETWORK

OUT

DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

17326-062

1 X means don’t care.

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 27 of 32

LOAD DAC (HARDWARE LDAC PIN)

The AD5674/AD5674R/AD5679/AD5679R DACs have double

buffered interfaces consisting of two banks of registers: input

registers and DAC registers. The user can write to any

combination of the input registers. Updates to the DAC register

are controlled by the LDAC pin.

Instantaneous DAC Updating (LDAC Held Low)

For instantaneous updating of the DACs, LDAC is held low and

data is clocked to the input register using Command 0001. Both

the addressed input register and the DAC register are updated

on the rising edge of SYNC, and the output begins to change

(see Table 17).

Figure 63. Simplified Diagram of Input Loading Circuitry for a Single DAC

Deferred DAC Updating (LDAC is Pulsed Low)

For deferred updating of the DACs, LDAC is held high and data

is clocked to the input register using Command 0001. All DAC

outputs are asynchronously updated by bringing LDAC low

after SYNC is brought high. The update now occurs on the

falling edge of LDAC.

LDAC MASK REGISTER

Command 0101 is reserved for this software LDAC function.

Address bits are ignored. Writing to the DAC, using

Command 0101, loads the 16-bit LDAC register (DB15 to DB0).

The default for each channel is 0, that is, the LDAC pin works

normally. Setting the bits to 1 forces this DAC channel to ignore

transitions on the LDAC pin, regardless of the state of the

hardware LDAC pin. This flexibility is useful in applications

where the user wants to select which channels respond to the

LDAC pin.

The LDAC register gives the user extra flexibility and control

over the hardware LDAC pin (see Table 16). Setting the LDAC

bits (DB0 to DB15) to 0 for a DAC channel means that this

channel update is controlled by the hardware LDAC pin.

Table 16. LDAC Overwrite Definition

Load LDAC Register

LDAC Bits (DB15 to DB0) LDAC Pin LDAC Operation

0000000000000000 1 or 0 Determined by the LDAC pin.

1111111111111111 X1DAC channels update and override the LDAC pin. DAC channels see LDAC as 1.

Table 17. Write Commands and LDAC Pin Truth Table1

Command Description

Hardware LDAC Pin

State

Input Register

Contents DAC Register Contents

0001 Write to Input Register n (dependent on

LDAC)

VLOGIC Data update No change (no update)

GND2 Data update Data update

0010 Update DAC Register n with contents of

Input Register n

VLOGIC No change Updated with input register

contents

GND No change Updated with input register

contents

0011 Write to and update DAC Channel n VLOGIC Data update Data update

GND Data update Data update

1 A high to low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked

(blocked) by the LDAC mask register.

2 When LDAC is permanently tied low, the LDAC mask bits are ignored.

SCLK

DAC

INTERFACE

LOGIC

AMPLIFIER

LDAC

INPUT

SDI

16-BIT

DAC VOUTXV

REF

17326-063

1 X means don’t care.

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 28 of 32

HARDWARE RESET (RESET)

The RESET pin is an active low reset that allows the outputs to

be cleared to zero scale or midscale. The clear code value

depends on the model in use and refers to the power-up voltage.

It is necessary to keep the RESET pin low for a minimum time

(see Table 5) to complete the operation. When the RESET signal

is returned high, the output remains at the cleared value until a

new value is programmed. When the RESET pin is low, the

outputs cannot be updated with a new value. Any events on the

LDAC pin or RESET pin during power-on reset are ignored. If

the RESET pin is pulled low at power-up, the device does not

initialize properly until the pin is released.

POWER-ON RESET INTERNAL CIRCUIT

The AD5674/AD5674R/AD5679/AD5679R contain a power-on

reset circuit that controls the output voltage during power-up.

Depending on the model selected, the output powers up to zero

scale (AD5679R-1, AD5674R-1) or the output powers up to

midscale (AD5679R-2, AD5674R-2). The output remains

powered up at this level until a valid write sequence is made to

the DAC.

SOFTWARE RESET

A software executable reset function is also available that resets

the DAC to the power-on reset code. Command 0110 is

designated for this software reset function. The DAC address

bits must be set to 0x0 and the data bits set to 0x1234 for the

software reset command to execute.

INTERNAL REFERENCE SETUP

The on-chip reference is on at power-up by default. To reduce

the supply current, turn off this reference by setting the software

programmable bit, DB0, in the control register. Table 18 shows

how the state of the bit corresponds to the mode of operation.

Command 0111 is reserved for setting up the internal reference

(see Table 10 and Table 19).

Table 18. Internal Reference Setup Register

Bit Description

DB2 Reserved

DB0 Reference enable

DB0 = 0: internal reference enabled (default)

DB0 = 1: internal reference disabled

Table 19. 24-Bit Input Shift Register Contents for Internal Reference Setup Command

DB23 (MSB) DB22 DB21 DB20 DB19 to DB3 DB2 DB1 DB0 (LSB)

0 1 1 1 Don’t care Reserved Reserved, set to 0 Reference enable

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 29 of 32

SOLDER HEAT REFLOW

As with all IC reference voltage circuits, the reference value

experiences a shift induced by the soldering process. Analog

Devices, Inc., performs a reliability test called precondition to

mimic the effect of soldering a device to a board. The output

voltage specification quoted previously includes the effect of

this reliability test.

Figure 64 shows the effect of solder heat reflow (SHR) as

measured through the reliability test (precondition).

Figure 64. SHR Reference Voltage Shift

LONG-TERM TEMPERATURE DRIFT

Figure 65 shows the change in VREF value after 1000 hours at 25°C

ambient temperature.

Figure 65. Reference Drift Through to 1000 Hours

THERMAL HYSTERESIS

Thermal hysteresis is the voltage difference induced on the

reference voltage by sweeping the temperature from ambient to

cold to hot, and then back to ambient.

Figure 66 shows thermal hysteresis data. Thermal hysteresis is

measured by sweeping the temperature from ambient to −40°C,

then to +125°C, and returning to ambient. The ∆VREF, shown in

blue in Figure 66, is then measured between the two ambient

measurements. The same temperature sweep and measurements

are immediately repeated and the results are shown in red in

Figure 66.

Figure 66. Thermal Hysteresis

2.49853

2.49873

2.49893

2.49913

2.49933

2.49953

2.49973

2.49993

2.50013

2.50033

2.50053

2.50073

2.50093

100

150

200

250

300

350

400

HITS

VREF (V)

POSTSOL DER HEAT REFLOW

PRESOL DE R HEAT REFLOW

17326-207

INTERNAL REFERENCE DRIFT (PPM)

120

–40

–30

–20

–10

100

110

ELAPSED TIME (Hours)

0100 200 300 400 500 600 700 800 900 1000

17326-315

–130 –110 –90 –70 –50 –30 –10 10 30 50 70

HITS

DISTORTION (ppm)

FIRST T EMPERATURE SWEEP

SUBSEQUENT TEMPERATURE SWEEPS

17326-075

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 30 of 32

APPLICATIONS INFORMATION

POWER SUPPLY RECOMMENDATIONS

The following supplies typically power the AD5674/AD5674R/

AD5679/AD5679R: VDD = 3.3 V and VLOGIC = 1.8 V.

The ADP7118 can be used to power the VDD pin. The ADP160

can be used to power the VLOGIC pin. Figure 67 shows this setup.

The ADP7118 can operate from input voltages up to 20 V. T he

ADP160 can operate from input voltages up to 5.5 V.

Figure 67. Low Noise Power Solution for the

AD5674/AD5674R/AD5679/AD5679R

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5674/AD5674R/AD5679/

AD5679R is performed via a serial bus that uses a standard

protocol compatible with DSP processors and microcontrollers.

The communications channel requires a 3-wire or 4-wire interface

consisting of a clock signal, a data signal, and a synchronization

signal. The device requires a 24-bit data-word with data valid

on the rising edge of SYNC.

AD5674/AD5674R/AD5679/AD5679R TO ADSP-

BF531 INTERFACE

The SPI interface of the AD5674/AD5674R/AD5679/AD5679R

can connect to industry-standard DSPs and microcontrollers.

Figure 68 shows the AD5674/AD5674R/AD5679/AD5679R

connected to the Analog Devices Blackfin® DSP. The Blackfin

has an integrated SPI port that can connect directly to the SPI

pins of the AD5674/AD5674R/AD5679/AD5679R.

Figure 68. ADSP-BF531 Interface

AD5674/AD5674R/AD5679/AD5679R TO SPORT

INTERFACE

The Analog Devices ADSP-BF527 has one SPORT® serial port.

Figure 69 shows how a SPORT interface is used to control the

AD5674/AD5674R/AD5679/AD5679R.

Figure 69. SPORT Interface

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the rated performance. Design the PCB on which the AD5674/

AD5674R/AD5679/AD5679R is mounted so that the device lies

on the analog plane.

The AD5674/AD5674R/AD5679/AD5679R must have ample

supply bypassing of 10 µF in parallel with 0.1 µF on each supply,

located as close to the package as possible, ideally up against the

device. The 10 µF capacitors are tantalum bead type. The 0.1 µF

capacitors must have low effective series resistance (ESR) and low

effective series inductance (ESI), such as the common ceramic

types, which provide a low impedance path to ground at high

frequencies to handle transient currents due to internal logic

switching.

In systems where there are many devices on one board, it is often

useful to provide some heat sinking capability to allow the

power to dissipate easily.

The GND plane on the device can be increased (as shown in

Figure 70) to provide a natural heat sinking effect.

Figure 70. Pad Connection to the Board

ADP160

LDO 1.8V: VLOGIC

ADP7118

LDO 3.3V: VDD

INPUT

17326-067

ADSP-BF531

SYNCSPISELx

SCLKSCK

LDACPF9

RESETPF8

SDIMOSI

AD5679R/

AD5679/

AD5674R/

AD5674

17326-068

ADSP-BF531

SYNCTFS0

SCLKTSCLK0

LDAC

PF8

RESET

PF9

SDIDT0PRI

AD5679R/

AD5679/

AD5674R/

AD5674

17326-069

GND PLANE

BOARD

17326-070

Data Sheet AD5674/AD5674R/AD5679/AD5679R

Rev. B | Page 31 of 32

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to provide

an isolation barrier between the controller and the unit being

controlled to protect and isolate the controlling circuitry from

any hazardous common-mode voltages that can occur. iCoupler®

products from Analog Devices can provide voltage isolation

>2.5 kV. The serial loading structure of the AD5679R makes the

device ideal for isolated interfaces because the number of interface

lines is kept to a minimum. Figure 71 shows a 4-channel, isolated

interface to the AD5674/AD5674R/AD5679/AD5679R using

the ADuM1400. For further information, visit

www.analog.com/icoupler.

Figure 71. Isolated Interface

ENCODE

SERIAL

CLOCK IN

CONTROLLER

ADuM14001

SERIAL

DATA OUT

SYNC

LOAD DAC

ADDITIONAL PINS OMITTED FOR CLARITY.

OUT

DECODE TO

SCLK

SDI

LDAC

ENCODE DECODE

SYNC

17326-071

AD5674/AD5674R/AD5679/AD5679R Data Sheet

Rev. B | Page 32 of 32

OUTLINE DIMENSIONS

Figure 72. 28-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.95 mm Package Height

(CP-28-9)

Dimensions shown in millimeters

ORDERING GUIDE

Model1, 2, 3Resolution

Temperature

Range Reset Value Package Description

Package

Option

AD5674BCPZ-1 12-bits −40°C to +125°C Zero scale 28-Lead LFCSP CP-28-9

AD5674BCPZ-1-RL7 12-bits −40°C to +125°C Zero scale 28-Lead LFCSP CP-28-9

AD5674RBCPZ-1 12-bits −40°C to +125°C Zero scale 28-Lead LFCSP CP-28-9

AD5674RBCPZ-1-RL7 12-bits −40°C to +125°C Zero scale 28-Lead LFCSP CP-28-9

AD5674RBCPZ-2 12-bits −40°C to +125°C Midscale 28-Lead LFCSP CP-28-9

AD5674RBCPZ-2-RL7 12-bits −40°C to +125°C Midscale 28-Lead LFCSP CP-28-9

AD5679BCPZ-1 16-bit −40°C to +125°C Zero scale 28-Lead LFCSP CP-28-9

AD5679BCPZ-1-RL7

16-bit

−40°C to +125°C

Zero scale

28-Lead LFCSP

CP-28-9

AD5679RBCPZ-1 16-bit −40°C to +125°C Zero scale 28-Lead LFCSP CP-28-9

AD5679RBCPZ-1-RL7 16-bit −40°C to +125°C Zero scale 28-Lead LFCSP CP-28-9

AD5679RBCPZ-2 16-bit −40°C to +125°C Midscale 28-Lead LFCSP CP-28-9

AD5679RBCPZ-2-RL7 16-bit −40°C to +125°C Midscale 28-Lead LFCSP CP-28-9

EVAL-AD5679RSDZ AD5679R Evaluation

Board

1 Z = RoHS Compliant Part.

2 The EVAL-SDP-CB1Z is used in conjunction with the EVAL-AD5679RSDZ.

3 The EVAL-AD5679RSDZ is compatible with all models of the AD5674/AD5674R/AD5679/AD5679R.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

2.70

2.60 SQ

2.50

1.00

0.95

0.90

TOP VI EW

SIDE VIEW

BOTTOM VIEW

PKG-004997

0.40

BSC

0.45

0.40

0.35

0.05 MAX

0.02 NO M

0.20 REF

COPLANARITY

0.08

0.25

0.20

0.15

COMPLIANT

JEDEC STANDARDS M O-220- V GG E

4.10

4.00 SQ

3.90

09-10-2018-A

0.20 MIN

SEATING

PLANE

EXPOSED

PAD

PIN 1

IN D ICATO R AR EA OPTIO NS

(SEE DETAIL A)

DETAIL A

(JEDEC 95)

FO R P ROPE R CONNECTI ON O F

THE EXPOSED PAD, REFER TO

THE P IN CO NFI GURAT IO N AND

FUNCT IO N DE S CRIPTI ONS

SECTION OF THIS DATA SHEET.

PIN 1

INDICATOR

AREA

registered trademarks are the property of their respective owners.

D17326-0-12/19(B)