89HPES3T3 Data Sheet 3-Lane 3-Port PCI Express(R) Switch (R) Device Overview u The 89HPES3T3 is a member of IDT's PRECISETM family of PCI Express switching solutions. The PES3T3 is a 3-lane, 3-port peripheral chip that performs PCI Express Base switching. It provides connectivity and switching functions between a PCI Express upstream port and up to four downstream ports and supports switching between downstream ports. u Features u u u High Performance PCI Express Switch - Three 2.5Gbps PCI Express lanes - Three switch ports - x1 Upstream port - Two x1 Downstream ports - Low latency cut-through switch architecture - Support for Max payload sizes up to 256 bytes - One virtual channel - Eight traffic classes - PCI Express Base Specification Revision 1.1 compliant Flexible Architecture with Numerous Configuration Options - Automatic lane reversal on all ports - Automatic polarity inversion on all lanes - Ability to load device configuration from serial EEPROM Legacy Support - PCI compatible INTx emulation - Bus locking u u Highly Integrated Solution - Requires no external components - Incorporates on-chip internal memory for packet buffering and queueing - Integrates three 2.5 Gbps embedded SerDes with 8B/10B encoder/decoder (no separate transceivers needed) Reliability, Availability, and Serviceability (RAS) Features - Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) - Supports ECRC and Advanced Error Reporting - Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O - Compatible with Hot-Plug I/O expanders used on PC motherboards Power Management - Utilizes advanced low-power design techniques to achieve low typical power consumption - Supports PCI Power Management Interface specification (PCIPM 1.2) - Unused SerDes are disabled. - Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI) supporting active link state Testability and Debug Features - Built in Pseudo-Random Bit Stream (PRBS) generator - Numerous SerDes test modes - Ability to bypass link training and force any link into any mode - Provides statistics and performance counters Block Diagram 3-Port Switch Core / 3 PCI Express Lanes Frame Buffer Port Arbitration Route Table Scheduler Transaction Layer Transaction Layer Transaction Layer Data Link Layer Data Link Layer Data Link Layer Mux / Demux Mux / Demux Mux / Demux Phy Logical Layer Phy Logical Layer Phy Logical Layer SerDes SerDes SerDes (Port 0) (Port 2) (Port 3) Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 31 2014 Integrated Device Technology, Inc. June 12, 2014 IDT 89HPES3T3 Data Sheet u u u Five General Purpose Input/Output Pins - Each pin may be individually configured as an input or output - Each pin may be individually configured as an interrupt input - Four pins have selectable alternate functions Option A Package: 13mm x 13mm 144-ball BGA with 1mm ball spacing Option B Package: 10mm x 10mm 132-ball QFN with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES3T3 provides the most efficient fan-out solution for applications requiring x1 connectivity, low latency, and simple board layout with a minimum number of board layers. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.1. The PES3T3 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.1. The PES3T3 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to allow efficient switching for applications requiring additional narrow port connectivity and also some high-end connectivity. Processor Processor Memory Memory Memory Memory North Bridge South Bridge x1 PES3T3 x1 x1 GE LOM 1394 Figure 2 I/O Expansion Application SMBus Interface The PES3T3 contains an SMBus master interface. This master interface allows the default configuration register values of the PES3T3 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Two pins make up the SMBus master interface. These pins consist of an SMBus clock pin and an SMBus data pin. Hot-Plug Interface The PES3T3 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES3T3 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES3T3 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES3T3. In response to an I/O expander interrupt, the PES3T3 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. 2 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet General Purpose Input/Output The PES3T3 provides 5 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control, and each GPIO pin is shared with another on-chip function. These alternate functions may be enabled via software or serial configuration EEPROM. Pin Description The following tables lists the functions of the pins provided on the PES3T3. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an "N" are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal Type Name/Description PE0RP[0] PE0RN[0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pair for port 0. PE0TP[0] PE0TN[0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pair for port 0. PE2RP[0] PE2RN[0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pair for port 2. PE2TP[0] PE2TN[0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pair for port 2. PE3RP[0] PE3RN[0] I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pair for port 3. PE3TP[0] PE3TN[0] O PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pair for port 3. PEREFCLKP PEREFCLKN I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is 100 MHz. Table 1 PCI Express Interface Pins Signal Type Name/Description MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the master SMBus. Table 2 SMBus Interface Pins 3 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O Expander interrupt 0 input GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output GPIO[9] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P3RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 3 Table 3 General Purpose I/O Pins Signal Type Name/Description APWRDISN I Auxiliary Power Disable Input. When this pin is active, it disables the device from using auxiliary power supply. CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be override by modifying the SCLK bit in the downstream port's PCIELSTS register. CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the PA_PCIELSTS register. PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the PES3T3 and initiates a PCI Express fundamental reset. Table 4 System Pins (Part 1 of 2) 4 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Signal Type Name/Description RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES3T3 executes the reset procedure and remains in a reset state with the Master SMBus active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the PA_SWCTL register by the SMBus master. SWMODE[2:0] I Switch Mode. These configuration pins determine the PES3T3 switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0xF Reserved WAKEN I/O Wake Input/Output. The WAKEN signal is an input or output. The WAKEN signal input/output selection can be made through WAKEDIR bit setting in the WAKEUPCNTL register. Table 4 System Pins (Part 2 of 2) Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 5 Test Pins Signal Type Name/Description VDDCORE I Core VDD. Power supply for core logic. VDDI/O I I/O VDD. LVTTL I/O buffer power supply. VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. VTTPE I PCI Express Termination Power. VSS I Ground. Table 6 Power and Ground Pins 5 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Pin Characteristics Note: Some input pads of the PES3T3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function PCI Express Interface Type Buffer I/O Type PE0RN[0] I CML Serial Link PE0RP[0] I Diff. Clock Input STI1 Pin Name PE0TN[0] O PE0TP[0] O PE2RN[0] I PE2RP[0] I PE2TN[0] O PE2TP[0] O PE3RN[0] I PE3RP[0] I Internal Resistor PE3TN[0] O PE3TP[0] O PEREFCLKN I PEREFCLKP I LVPECL/ CML MSMBCLK I/O LVTTL MSMBDAT I/O General Purpose I/O GPIO[9,7,2:0] I/O LVTTL High Drive pull-up System Pins APWRDISN I LVTTL Input pull-down CCLKDS I pull-up CCLKUS I pull-up PERSTN I RSTHALT I SMBus SWMODE[2:0] WAKEN EJTAG / JTAG 1. STI pull-down I pull-down open-drain I JTAG_TDI I JTAG_TDO O JTAG_TMS JTAG_TRST_N Schmitt Trigger Input (STI). Refer toTable 8 I/O JTAG_TCK Notes LVTTL STI pull-up STI pull-up I STI pull-up I STI pull-up Table 7 Pin Characteristics 6 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Logic Diagram -- PES3T3 Reference Clocks PEREFCLKP PEREFCLKN PE0TP[0] PE0TN[0] PCI Express Switch SerDes Input Port 0 PE0RP[0] PE0RN[0] PE2TP[0] PE2TN[0] PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Output Port 2 PE2RP[0] PE2RN[0] PE3TP[0] PE3TN[0] PCI Express Switch SerDes Input Port 3 PE3RN[0] Master SMBus Interface MSMBCLK System Pins PCI Express Switch SerDes Output Port 0 PES3T3 PE3RP[0] 5 General Purpose I/O JTAG_TCK JTAG_TDI MSMBDAT JTAG_TDO JTAG Pins JTAG_TMS CCLKDS JTAG_TRST_N CCLKUS RSTHALT VDDCORE PERSTN SWMODE[2:0] GPIO[9,7,2:0] PCI Express Switch SerDes Output Port 3 VDDI/O 3 VDDPE WAKEN VDDAPE APWRDISN VSS Power/Ground VTTPE Figure 3 PES3T3 Logic Diagram 7 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13. Parameter Description Min Typical Max Unit PEREFCLK RefclkFREQ Input reference clock frequency range 100 RefclkDC1 Duty cycle of input clock 40 TR, TF Rise/Fall time of input clocks VSW Differential input voltage swing3 Tjitter Input clock jitter (cycle-to-cycle) MHz 50 0.6 60 % 0.2*RCUI RCUI2 1.6 V 125 ps Table 8 Input Clock Requirements 1. ClkIn must be AC coupled. Use 0.01 -- 0.1 F ceramic capacitors. 2. RCUI (Reference Clock Unit Interval) refers to the reference clock period. 3. AC coupling required. AC Timing Characteristics Parameter Description Min1 Typical1 Max1 Units 399.88 400 400.12 ps 0.7 .9 PCIe Transmit UI Unit Interval TTX-EYE Minimum Tx Eye Width TTX-EYE-MEDIAN-toMAX-JITTER Maximum time between the jitter median and maximum deviation from the median TTX-RISE, TTX-FALL D+ / D- Tx output rise/fall time 50 TTX- IDLE-MIN Minimum time in idle 50 TTX-IDLE-SET-TO- Maximum time to transition to a valid Idle after sending an Idle ordered set 20 UI IDLE TTX-IDLE-TO-DIFF- Maximum time to transition from valid idle to diff data 20 UI UI 0.15 90 UI ps UI DATA TTX-SKEW Transmitter data skew between any 2 lanes 500 1300 ps TBTEn Time from asserting Beacon TxEn to beacon being transmitted on the lane 30 80 ns 400 400.12 ps PCIe Receive UI Unit Interval 399.88 TRX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) TRX-EYE-MEDIUM TO Max time between jitter median & max deviation 0.3 UI Unexpected Idle Enter Detect Threshold Integration Time 10 ms Lane to lane input skew 20 ns 0.4 UI MAX JITTER TRX-IDLE-DET-DIFFENTER TIME TRX-SKEW Table 9 PCIe AC Timing Characteristics 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 8 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Signal Symbol Reference Min Max Unit Edge Timing Diagram Reference GPIO GPIO[9,7,2:0]1 Tpw_13b2 None 50 -- ns See Figure 4. Table 10 GPIO AC Timing Characteristics 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. EXTCLK Tdo_13a Tdo_13a GPIO (synchronous output) Tpw_13b GPIO (asynchronous input) Figure 4 GPIO AC Timing Waveform Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference Tper_16a none 25.0 50.0 ns See Figure 5. 10.0 25.0 ns 2.4 -- ns 1.0 -- ns -- 11.3 ns -- 11.3 ns 25.0 -- ns JTAG JTAG_TCK Thigh_16a, Tlow_16a JTAG_TMS1, JTAG_TDI JTAG_TDO Tsu_16b JTAG_TCK rising Thld_16b Tdo_16c JTAG_TCK falling Tdz_16c2 JTAG_TRST_N Tpw_16d2 none Table 11 JTAG AC Timing Characteristics 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. 2. The values for this symbol were determined by calculation, not by testing. 9 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Tlow_16a Tper_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Tdo_16c Tdz_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure 5 JTAG AC Timing Waveform Recommended Operating Supply Voltages Symbol Parameter Minimum Typical Maximum Unit 0.9 1.0 1.1 V 3.135 3.3 3.465 V VDDCORE Internal logic supply VDDI/O I/O supply except for SerDes LVPECL/CML VDDPE PCI Express Digital Power 0.9 1.0 1.1 V VDDAPE PCI Express Analog Power 0.9 1.0 1.1 V VTTPE PCI Express Serial Data Transmit Termination Voltage 1.425 1.5 1.575 V VSS Common ground 0 0 0 V Table 12 PES3T3 Operating Voltages Power-Up/Power-Down Sequence This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the PES3T3, the power-up sequence must be as follows: 1. VDDI/O -- 3.3V 2. VDDCore, VDDPE, VDDAPE -- 1.0V 3. VTTPE -- 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the power-up sequence. 10 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Recommended Operating Temperature Grade Temperature Commercial 0C to +70C Ambient Industrial -40C to +85C Ambient Table 13 PES3T3 Operating Temperatures Power Consumption Typical power is measured under the following conditions: 25C Ambient, 35% total link usage on all ports, typical voltages defined in Table 12. Maximum power is measured under the following conditions: 70C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 12. All power measurements assume that the part is mounted on a 10 layer printed circuit board with 0 LFM airflow. Core Supply PCIe Digital Supply PCIe Analog Supply PCIe Termination Supply Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.5V Max 1.575V Typ 3.3V Max 3.465V mA 254 330 173 220 99 117 75 94 3 3.3 Watts 0.25 0.36 0.17 0.24 0.10 0.13 0.11 0.15 0.01 0.01 Number of Connected Lanes 1/1/1 I/O Supply Total (Watts) Typ Max 0.65 0.89 Table 14 PES3T3 Power Consumption Thermal Considerations -- Option A Package This section describes thermal considerations for the PES3T3 (13mm2 BCG144 package). The data in Table 15 below contains information that is relevant to the thermal performance of the PES3T3 switch. Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oC Maximum 70 oC Maximum for commercial-rated products 85 o TA(max) TA(max) JA(effective) Ambient Temperature Ambient Temperature Effective Thermal Resistance, Junction-to-Ambient C Maximum for industrial-rated products 34.6 oC/W Zero air flow 30.3 oC/W 1 m/S air flow 28.4 o 2 m/S air flow C/W JB Thermal Resistance, Junction-to-Board 18.8 oC/W JC Thermal Resistance, Junction-to-Case 10 oC/W P Power Dissipation of the Device 0.89 Watts Maximum Table 15 Thermal Specifications for PES3T3, 13x13mm BCG144 Package 11 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Thermal Considerations -- Option B Package This section describes thermal considerations for the PES3T3 (10mm2 NQG132 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES3T3 switch. Symbol Parameter Value TJ(max) Junction Temperature 125 o Maximum 70 o TA(max) JA(effective) JB Ambient Temperature Effective Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Board Units Conditions C C Maximum for commercial-rated products 23.5 o C/W Zero air flow 19.6 o 1 m/S air flow 17.4 o 2 m/S air flow 0.2 o C/W C/W C/W JC Thermal Resistance, Junction-to-Case 7.6 oC/W P Power Dissipation of the Device 0.89 Watts Maximum Table 16 Thermal Specifications for PES3T3, 10x10mm NQG132 Package 12 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. I/O Type Serial Link Parameter Min1 Description Typ1 Max1 Unit 800 1200 mV -3 -4 dB 3.7 V Conditions PCIe Transmit VTX-DIFFp-p VTX-DE-RATIO Differential peak-to-peak output voltage De-emphasized differential output voltage VTX-DC-CM DC Common mode voltage VTX-CM-ACP RMS AC peak common mode output voltage 20 mV VTX-CM-DC- Abs delta of DC common mode voltage between L0 and idle 100 mV Abs delta of DC common mode voltage between D+ and D- 25 mV Electrical idle diff peak output 20 mV Voltage change during receiver detection 600 mV active-idle-delta VTX-CM-DC-linedelta VTX-Idle-DiffP VTX-RCV-Detect -0.1 1 RLTX-DIFF Transmitter Differential Return loss 10 dB RLTX-CM Transmitter Common Mode Return loss 6 dB ZTX-DEFF-DC DC Differential TX impedance 80 100 120 ZOSE Single ended TX Impedance 40 50 60 Transmitter Eye Diagram TX Eye Height (De-emphasized bits) 505 650 mV Transmitter Eye Diagram TX Eye Height (Transition bits) 800 950 mV VRX-DIFFp-p Differential input voltage (peak-to-peak) 175 VRX-CM-AC Receiver common-mode voltage for AC coupling RLRX-DIFF Receiver Differential Return Loss 10 dB RLRX-CM Receiver Common Mode Return Loss 6 dB Differential input impedance (DC) 80 100 120 Single-ended input impedance 40 50 60 200k 350k PCIe Receive ZRX-DIFF-DC ZRX-COMM-DC ZRX-COMM-HIGH- Powered down input common mode impedance (DC) Z-DC VRX-IDLE-DET- Electrical idle detect threshold 65 Input Capacitance 1.5 1200 mV 150 mV 175 mV DIFFp-p PCIe REFCLK CIN -- pF Table 17 DC Electrical Characteristics (Part 1 of 2) 13 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet I/O Type Min1 Typ1 Max1 Unit Conditions IOL -- 2.5 -- mA VOL = 0.4v IOH -- -5.5 -- mA VOH = 1.5V IOL -- 12.0 -- mA VOL = 0.4v IOH -- -20.0 -- mA VOH = 1.5V Parameter Description Other I/Os LOW Drive Output High Drive Output Schmitt Trigger Input (STI) VIL -0.3 -- 0.8 V -- VIH 2.0 -- VDDI/O + 0.5 V -- Input VIL -0.3 -- 0.8 V -- VIH 2.0 -- VDDI/O + 0.5 V -- CIN -- -- 8.5 pF -- Inputs -- -- + 10 A VDDI/O (max) I/OLEAK W/O Pull-ups/downs -- -- + 10 A VDDI/O (max) I/OLEAK WITH Pull-ups/downs -- -- + 80 A VDDI/O (max) Capacitance Leakage Table 17 DC Electrical Characteristics (Part 2 of 2) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1. 14 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Option A Package -- 144-BGA Signal Pinout for PES3T3 The following table lists the pin numbers and signal names for the PES3T3 device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function A1 VSS C11 VDDCORE F9 VDDCORE J7 VSS A2 VDDIO C12 VSS F10 VDDIO J8 VDDCORE A3 APWRDISN D1 JTAG_TDO F11 VDDIO J9 VSS A4 VTTPE D2 MSMBCLK F12 GPIO_01 J10 VSS A5 VTTPE D3 VDDCORE G1 VSS J11 VDDIO A6 PE0TP00 D4 VSS G2 JTAG_TRST_N J12 GPIO_09 A7 VDDPE D5 VSS G3 VSS K1 VSS A8 PE0RP00 D6 VSS G4 VDDCORE K2 VDDCORE A9 VDDIO D7 VDDCORE G5 VSS K3 VDDIO A10 SWMODE_0 D8 VSS G6 VDDCORE K4 VDDCORE A11 SWMODE_1 D9 VSS G7 VSS K5 VDDPE A12 VSS D10 VSS G8 VDDCORE K6 VSS B1 VDDCORE D11 PERSTN G9 VSS K7 VDDPE B2 WAKEN D12 RSTHALT G10 VDDCORE K8 VSS B3 CCLKUS E1 JTAG_TDI G11 VSS K9 VDDCORE B4 VDDPE E2 MSMBDAT G12 GPIO_02 K10 VDDIO B5 VDDPE E3 VDDIO H1 PEREFCLKP K11 VSS B6 PE0TN00 E4 VDDCORE H2 VDDIO K12 VSS B7 VDDPE E5 VSS H3 VDDAPE L1 PE2RN00 B8 PE0RN00 E6 VDDCORE H4 VSS L2 VSS B9 CCLKDS E7 VSS H5 VSS L3 PE2TP00 B10 SWMODE_2 E8 VSS H6 VSS L4 VSS B11 VSS E9 VSS H7 VDDCORE L5 PE3TN00 B12 VSS E10 VDDCORE H8 VSS L6 VDDAPE C1 JTAG_TMS E11 VSS H9 VSS L7 PE3RN00 C2 VSS E12 GPIO_00 H10 VDDCORE L8 VTTPE C3 VSS F1 JTAG_TCK H11 VSS L9 NC C4 VDDCORE F2 VDDIO H12 GPIO_07 L10 VSS C5 VDDAPE F3 VDDCORE J1 PEREFCLKN L11 NC C6 VDDAPE F4 VSS J2 VSS L12 VDDCORE C7 VSS F5 VDDCORE J3 VSS M1 PE2RP00 C8 VDDCORE F6 VSS J4 VSS M2 VSS C9 VDDCORE F7 VDDCORE J5 VSS M3 PE2TN00 C10 VSS F8 VSS J6 VDDCORE M4 VTTPE 1 1 1 Alt 1 Table 18 PES3T3 (13x13, 144-pin) Signal Pin-Out (Part 1 of 2) 15 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Pin Function Alt Pin Function Alt Pin Function Alt Pin Function M5 PE3TP00 M7 PE3RP00 M9 NC M11 NC M6 VSS M8 VDDAPE M10 VSS M12 VSS Alt Table 18 PES3T3 (13x13, 144-pin) Signal Pin-Out (Part 2 of 2) Option A Package -- Alternate Signal Functions Pin GPIO Alternate E12 GPIO_00 P2RSTN G12 GPIO_02 IOEXPINTN0 H12 GPIO_07 GPEN J12 GPIO_09 P3RSTN Table 19 PES3T3 (13x13, 144-pin) Alternate Signal Functions Option A Package -- Power Pins VDDCore VDDCore VDDI/O VDDPE VDDAPE VTTPE B1 F9 A2 A7 C5 A4 C4 G4 A9 B4 C6 A5 C8 G6 E3 B5 H3 L8 C9 G8 F2 B7 L6 M4 C11 G10 F10 K5 M8 D3 H7 F11 K7 D7 H10 H2 E4 J6 J11 E6 J8 K3 E10 K2 K10 F3 K4 F5 K9 F7 L12 Table 20 PES3T3 (13x13, 144-pin) Power Pins 16 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Option A Package -- Ground Pins Vss Vss Vss Vss A1 D10 G11 K1 A12 E5 H4 K6 B11 E7 H5 K8 B12 E8 H6 K11 C2 E9 H8 K12 C3 E11 H9 L2 C7 F4 H11 L4 C10 F6 J2 L10 C12 F8 J3 M2 D4 G1 J4 M6 D5 G3 J5 M10 D6 G5 J7 M12 D8 G7 J9 D9 G9 J10 Table 21 PES3T3 (13x13, 144-pin) Ground Pins Option A Package -- Signals Listed Alphabetically Signal Name I/O Type Location Signal Category APWRDISN I A3 System CCLKDS I B9 CCLKUS I B3 GPIO_00 I/O E12 GPIO_01 I/O F12 GPIO_02 I/O G12 GPIO_07 I/O H12 GPIO_09 I/O J12 JTAG_TCK I F1 JTAG_TDI I E1 JTAG_TDO I D1 JTAG-TMS O C1 JTAG-TRST_N I G2 MSMBCLK I/O D2 MSMBDAT I/O E2 General Purpose Input/Output JTAG SMBus Table 22 89PES3T3 (13x13, 144-pin) Alphabetical Signal List (Part 1 of 2) 17 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Signal Name I/O Type No Connection Location L9, L11, M9, M11 PE0RN00 I B8 PE0RP00 I A8 PE0TN00 O B6 PE0TP00 O A6 PE2RN00 I L1 PE2RP00 I M1 PE2TN00 O M3 PE2TP00 O L3 PE3RN00 I L7 PE3RP00 I M7 PE3TN00 O L5 PE3TP00 O M5 PEREFCLKN I J1 PEREFCLKP I H1 PERSTN I D11 RSTHALT I D12 SWMODE_0 I A10 SWMODE_1 I A11 SWMODE_2 I B10 I/O B2 WAKEN Signal Category PCI Express System VDDCORE, VDDAPE, VDDI/O, VDDPE, VTTPE See Table 20 for a listing of power pins. VSS See Table 21 for a listing of ground pins. Table 22 89PES3T3 (13x13, 144-pin) Alphabetical Signal List (Part 2 of 2) 18 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Option A Package Pinout -- Top View 1 2 3 A 4 5 X X 6 7 8 9 10 11 12 A B B C C D D E E F F G G H H J J K K X L X M 1 2 3 4 VDDCore (Power) VDDI/O (Power) 5 x 6 7 VTTPE (Power) VDDPE (Power) VDDAPE (Power) 19 of 31 8 X X9 10 X X 11 Vss (Ground) X L M 12 Signals No Connect June 12, 2014 IDT 89HPES3T3 Data Sheet 1.50 1.60 1.70 Option A Package Drawing -- 144-Pin BC144/BCG144 20 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Option A Package Drawing -- Page Two 21 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Package B Package Pinout -- 132-QFN Signal Pinout for PES3T3 The following table lists the pin numbers and signal names for the PES3T3 132-pin device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function A1 NC A34 VDDCORE A67 VDDPE B28 VDDPE A2 NC A35 NC A68 VDDCORE B29 VDDPE A3 VDDI/O A36 NC A69 VDDI/O B30 VDDCORE A4 VDDI/O A37 NC A70 WAKEN B31 VDDCORE A5 VDDCORE A38 NC A71 NC B32 VSS A6 VDDCORE A39 GPIO_09 A72 NC B33 VDDCORE A7 MSMBDAT A40 VDDCORE B1 VSS B34 VSS A8 MSMBCLK A41 VDDCORE B2 VSS B35 VDDI/O A9 VSS A42 GPIO_07 B3 VDDI/O B36 VSS A10 JTAG_TRST_N A43 VSS B4 VSS B37 VDDCORE A11 JTAG_TMS A44 NC B5 VDDCORE B38 VDDI/O A12 JTAG_TDO A45 NC B6 VSS B39 VDDCORE A13 JTAG_TDI A46 VSS B7 VSS B40 VDDCORE A14 JTAG_TCK A47 VDDI/O B8 VDDCORE B41 VDDI/O A15 PEREFCLKP A48 GPIO_02 1 B9 VDDI/O B42 VDDCORE A16 PEREFCLKN A49 GPIO_01 1 B10 VDDCORE B43 VSS A17 NC A50 GPIO_00 1 B11 VSS B44 RSTHALT A18 NC A51 VDDI/O B12 VDDCORE B45 PERSTN A19 NC A52 VDDCORE B13 VSS B46 SWMODE_2 A20 NC A53 NC B14 VDDAPE B47 VSS A21 VDDCORE A54 NC B15 VSS B48 VDDCORE A22 PE2RP00 A55 NC B16 VDDI/O B49 CCLKDS A23 PE2TP00 A56 NC B17 PE2RN00 B50 VSS A24 PE2TN00 A57 SWMODE_1 B18 VSS B51 VDDPE A25 PE3TN00 A58 SWMODE_0 B19 VDDPE B52 VDDPE A26 PE3TP00 A59 VDDI/O B20 VTTPE B53 VTTPE A27 PE3RP00 A60 PE0RN00 B21 VDDPE B54 VDDAPE A28 PE3RN00 A61 PE0RP00 B22 VSS B55 VDDAPE A29 VDDAPE A62 PE0TP00 B23 VSS B56 VDDAPE A30 NC A63 PE0TN00 B24 VDDAPE B57 VSS A31 NC A64 VDDPE B25 VSS B58 APWRDISN A32 NC A65 VDDAPE B26 VSS B59 VDDCORE A33 NC A66 VDDAPE B27 VTTPE B60 CCLKUS 1 1 Alt Table 23 PES3T3 (10x10, 132-pin) Signal Pin-Out 22 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Package B Alternate Signal Functions Pin GPIO Alternate A50 GPIO_00 P2RSTN A49 GPIO_01 P4RSTN A48 GPIO_02 IOEXPINTN0 A42 GPIO_07 GPEN A39 GPIO_09 P3RSTN Table 24 PES3T3 (10x10, 132-pin) Alternate Signal Functions Package B Power Pins VDDCore VDDCore VDDI/O VDDPE VDDAPE VTTPE A5 B12 A3 A64 A29 B20 A6 B30 A4 A67 A65 B27 A21 B31 A47 B19 A66 B53 A34 B33 A51 B21 B14 A40 B37 A59 B28 B24 A41 B39 A69 B29 B54 A52 B40 B3 B51 B55 A68 B42 B9 B52 B56 B5 B48 B16 B8 B59 B35 B10 -- B38 B41 Table 25 PES3T3 (10x10, 132-pin) Power Pins 23 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Package B Ground Pins Vss Vss Vss Vss A9 B6 B22 B36 A43 B7 B23 B43 A46 B11 B25 B47 B1 B13 B26 B50 B2 B15 B32 B57 B4 B18 B34 -- Table 26 PES3T3 (10x10, 132-pin) Ground Pins Package B No Connection Pins NC NC A1 A36 A2 A37 A17 A38 A18 A44 A19 A45 A20 A53 A30 A54 A31 A55 A32 A56 A33 A71 A35 A72 Table 27 PES3T3 (10x10, 132-pin) No Connection Pins 24 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Package B Pin Signals Listed Alphabetically Signal Name I/O Type Location Signal Category APWRDISN I B58 System CCLKDS I B49 CCLKUS I B60 GPIO_00 I/O A50 GPIO_01 I/O A49 GPIO_02 I/O A48 GPIO_07 I/O A42 GPIO_09 I/O A39 JTAG_TCK I A14 JTAG_TDI I A13 JTAG_TDO I A12 JTAG-TMS O A11 JTAG-TRST_N I A10 MSMBCLK I/O A8 MSMBDAT I/O A7 NC General Purpose Input/Output JTAG SMBus See Table 27 for a listing of no connection pins. PE0RN00 I A60 PE0RP00 I A61 PE0TN00 O A63 PE0TP00 O A62 PE2RN00 I B17 PE2RP00 I A22 PE2TN00 O A24 PE2TP00 O A23 PE3RN00 I A28 PE3RP00 I A27 PE3TN00 O A25 PE3TP00 O A26 PEREFCLKN I A16 PEREFCLKP I A15 PCI Express Table 28 89PES3T3 (10x10, 132-pin) Alphabetical Signal List (Part 1 of 2) 25 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Signal Name I/O Type Location Signal Category PERSTN I B45 System RSTHALT I B44 SWMODE_0 I A58 SWMODE_1 I A57 SWMODE_2 I B46 I/O A70 WAKEN VDDCORE, VDDAPE, VDDI/O, VDDPE, VTTPE See Table 25 for a listing of power pins. VSS See Table 26 for a listing of ground pins. Table 28 89PES3T3 (10x10, 132-pin) Alphabetical Signal List (Part 2 of 2) 26 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Package B Pinout -- Top View A72 A71 A70 A69 A68 A67 A66 A65 A63 A64 A62 A61 A60 A59 A58 A57 A56 A55 X A1 B60 B59 B58 B57 B56 B55 B54 A54 B53 B52 B51 B50 B49 B48 B47 B46 A53 A2 B1 B45 B2 B44 B3 B43 B4 B42 B5 B41 B6 B40 B7 B39 B8 B38 B9 B37 B10 B36 B11 B35 B12 B34 B13 B33 B14 B32 B15 B31 A52 A3 A51 A4 A50 A5 A49 A6 A48 A7 A47 A8 A46 A9 A10 A45 A11 A44 A43 A12 A42 A13 A41 A14 A40 A15 A39 A16 A38 A17 B17 B16 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 A19 A20 A21 VDDCore (Power) VDDI/O (Power) A22 x A23 A24 B29 B30 X X A18 B28 A25 A26 A27 A28 A29 A30 A31 A37 A32 A33 A34 VTTPE (Power) VDDAPE (Power) Signals VDDPE (Power) Vss (Ground) No Connection 27 of 31 A35 A36 June 12, 2014 IDT 89HPES3T3 Data Sheet Package B Package Drawing -- 132-Pin NQ132/NQG132 28 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet : 6.5mm x 6.5mm Package B Package Drawing -- Page Two 29 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Revision History March 31, 2008: Publication of final data sheet. June 4, 2008: For the 132-QFN package, changed pins A44 and A45 from GPIO to No Connect and changed pin B6 from VDDCORE to VSS. August 6, 2008: Added industrial temperature information to Tables 13 and 15 and to Ordering Information section. Revised Package B Pinout Top View graphic to match page 3 of the Package B drawing. May 7, 2009: Revised labels in Table 14, Power Consumption, for greater clarification. October 8, 2010: Added package height data to Note 10 on Page Two of Package B drawing and removed page 3 of Package B drawing. June 12, 2014: Changed symbol A in Option A Package Drawing -- 144-Pin BC144/BCG144 to match the package characteristics of the part. The new definition for the symbol is 1.50 minimum, 1.60 nominal, and 1.70 maximum. 30 of 31 June 12, 2014 IDT 89HPES3T3 Data Sheet Ordering Information NN A AAA NNAN AA Product Family Operating Voltage Device Family Product Detail Device Revision AA Legend A = Alpha Character N = Numeric Character A Package Temp Range Blank Commercial Temperature (0C to +70C Ambient) I Industrial Temperature (-40 C to +85 C Ambient) BC BCG NQ NQG BC144 144-ball CABGA BCG144 144-ball CABGA, Green NQ132 132-ball QFN NQG132 132-ball QFN, Green ZB ZB revision 3T3 3-lane, 3-port PES PCI Express Switch H 1.0V +/- 0.1V Core Voltage 89 Serial Switching Product Valid Combinations Option A Package 89HPES3T3ZBBC 144-pin BC144 package, Commercial Temperature 89HPES3T3ZBBCG 144-pin Green BC144 package, Commercial Temperature 89HPES3T3ZBBCI 144-pin BC144 package, Industrial Temperature 89HPES3T3ZBBCGI 144-pin Green BC144 package, Industrial Temperature Option B Package 89HPES3T3ZBNQ 132-pin NQ132 package, Commercial Temperature 89HPES3T3ZBNQG 132-pin Green NQ132 package, Commercial Temperature (R) CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 31 of 31 for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208 June 12, 2014